STM32F745xx HAL User Manual: STM32F7xx HAL Drivers

STM32F745xx HAL User Manual
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STM32F7xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32F745xx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization/de-initialization functions

  • Data Structures
  • Files
  • Directories
Functions
Initialization/de-initialization functions

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 195 of file stm32f7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 118 of file stm32f7xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 251 of file stm32f7xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 236 of file stm32f7xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 300 of file stm32f7xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 358 of file stm32f7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC state.

Parameters:
hcrc,: CRC handle
Return values:
HAL state

Definition at line 500 of file stm32f7xx_hal_crc.c.

References CRC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, and instruction cache through ART accelerator.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface the NVIC allocation and initial clock
          configuration. It initializes the systick also when timeout is needed
          and the backup domain when enabled.
      (+) de-Initializes common part of the HAL
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) Systick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the systick.

This function is optional.

Return values:
HAL status

Definition at line 179 of file stm32f7xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, and instruction cache through ART accelerator.

Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz). Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32f7xx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 154 of file stm32f7xx_hal.c.

References __HAL_FLASH_ART_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 248 of file stm32f7xx_hal.c.

References HAL_NVIC_SetPriority(), HAL_RCC_GetHCLKFreq(), and HAL_SYSTICK_Config().

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 222 of file stm32f7xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 208 of file stm32f7xx_hal.c.

Referenced by HAL_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_EnableFMCMemorySwapping (void)
Enables the FMC Memory Mapping Swapping.
void | HAL_DisableFMCMemorySwapping (void)
Disables the FMC Memory Mapping Swapping.

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 404 of file stm32f7xx_hal.c.

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 440 of file stm32f7xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Return values:
None

Definition at line 422 of file stm32f7xx_hal.c.

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 395 of file stm32f7xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 431 of file stm32f7xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Return values:
None

Definition at line 413 of file stm32f7xx_hal.c.

void HAL_Delay ( __IO uint32_t Delay )

This function provides accurate delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay,: specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 323 of file stm32f7xx_hal.c.

References HAL_GetTick().

Referenced by ETH_FlushTransmitFIFO(), ETH_MACDMAConfig(), ETH_MACReceptionDisable(), ETH_MACReceptionEnable(), ETH_MACTransmissionDisable(), ETH_MACTransmissionEnable(), HAL_ETH_ConfigDMA(), HAL_ETH_ConfigMAC(), HAL_ETH_Init(), and SD_PowerON().

void HAL_DisableCompensationCell ( void )

Power-down the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 462 of file stm32f7xx_hal.c.

void HAL_DisableFMCMemorySwapping ( void )

Disables the FMC Memory Mapping Swapping.

Note:
SDRAM is accessible at 0xC0000000 (default mapping) and NOR/RAM is accessible at 0x60000000 (default mapping)
Return values:
None

Definition at line 488 of file stm32f7xx_hal.c.

void HAL_EnableCompensationCell ( void )

Enables the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 451 of file stm32f7xx_hal.c.

void HAL_EnableFMCMemorySwapping ( void )

Enables the FMC Memory Mapping Swapping.

Note:
SDRAM is accessible at 0x60000000 and NOR/RAM is accessible at 0xC0000000
Return values:
None

Definition at line 475 of file stm32f7xx_hal.c.

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 386 of file stm32f7xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 368 of file stm32f7xx_hal.c.

References __STM32F7xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 377 of file stm32f7xx_hal.c.

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 307 of file stm32f7xx_hal.c.

References uwTick.

Referenced by FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_WakeUp(), HAL_CEC_Receive(), HAL_CEC_Transmit(), HAL_DCMI_Stop(), HAL_Delay(), HAL_DMA2D_Abort(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_Suspend(), HAL_DMA_Abort(), HAL_DMA_PollForTransfer(), HAL_ETH_Init(), HAL_ETH_ReadPHYRegister(), HAL_ETH_WritePHYRegister(), HAL_I2C_IsDeviceReady(), HAL_IWDG_Init(), HAL_IWDG_Refresh(), HAL_IWDG_Start(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), HAL_NOR_GetStatus(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableOverDrive(), HAL_PWREx_EnableBkUpReg(), HAL_PWREx_EnableOverDrive(), HAL_PWREx_EnterUnderDriveSTOPMode(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SPI_TransmitReceive(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_WaitOnFlagUntilTimeout(), QSPI_WaitFlagStateUntilTimeout(), RTC_EnterInitMode(), SAI_Disable(), SMARTCARD_WaitOnFlagUntilTimeout(), SPDIFRX_WaitOnFlagUntilTimeout(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), UART_WaitOnFlagUntilTimeout(), and USART_WaitOnFlagUntilTimeout().

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 296 of file stm32f7xx_hal.c.

References uwTick.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 358 of file stm32f7xx_hal.c.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 342 of file stm32f7xx_hal.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL Exported Macros

Defines
HAL Exported Macros
HAL

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000.
#define | __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()
FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000.

Define Documentation

#define __HAL_DBGMCU_FREEZE_CAN1 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))

Definition at line 84 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_CAN2 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))

Definition at line 85 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

Definition at line 80 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))

Definition at line 81 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))

Definition at line 82 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))

Definition at line 83 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))

Definition at line 79 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))

Definition at line 76 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))

Definition at line 77 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))

Definition at line 86 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM10 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))

Definition at line 89 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM11 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))

Definition at line 90 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM12 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))

Definition at line 73 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM13 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))

Definition at line 74 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM14 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))

Definition at line 75 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))

Freeze/Unfreeze Peripherals in Debug mode.

Definition at line 67 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))

Definition at line 68 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))

Definition at line 69 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM5 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))

Definition at line 70 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))

Definition at line 71 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))

Definition at line 72 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM8 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))

Definition at line 87 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM9 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))

Definition at line 88 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))

Definition at line 78 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_CAN1 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))

Definition at line 109 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_CAN2 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))

Definition at line 110 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

Definition at line 105 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))

Definition at line 106 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))

Definition at line 107 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))

Definition at line 108 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))

Definition at line 104 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM1 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))

Definition at line 101 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))

Definition at line 102 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))

Definition at line 111 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM10 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))

Definition at line 114 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM11 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))

Definition at line 115 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM12 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))

Definition at line 98 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM13 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))

Definition at line 99 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM14 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))

Definition at line 100 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))

Definition at line 92 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))

Definition at line 93 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))

Definition at line 94 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM5 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))

Definition at line 95 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM6 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))

Definition at line 96 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM7 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))

Definition at line 97 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM8 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))

Definition at line 112 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM9 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))

Definition at line 113 of file stm32f7xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))

Definition at line 103 of file stm32f7xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FMC ( ) (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))

FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000.

Definition at line 120 of file stm32f7xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM ( )
Value:
do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
                                          SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
                                         }while(0);

FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000.

Definition at line 125 of file stm32f7xx_hal.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL Private Variables

Variables
HAL Private Variables
HAL

Variables

static __IO uint32_t uwTick

Variable Documentation

__IO uint32_t uwTick [static]

Definition at line 92 of file stm32f7xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL Private Constants

Defines
HAL Private Constants
HAL

Defines

#define | __STM32F7xx_HAL_VERSION_MAIN (0x01)
STM32F7xx HAL Driver version number V1.0.3.
#define | __STM32F7xx_HAL_VERSION_SUB1 (0x00)
#define | __STM32F7xx_HAL_VERSION_SUB2 (0x03)
#define | __STM32F7xx_HAL_VERSION_RC (0x00)
#define | __STM32F7xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Define Documentation

#define __STM32F7xx_HAL_VERSION
Value:
((__STM32F7xx_HAL_VERSION_MAIN << 24)\
                                        |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
                                        |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
                                        |(__STM32F7xx_HAL_VERSION_RC))

Definition at line 77 of file stm32f7xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32F7xx_HAL_VERSION_MAIN (0x01)

STM32F7xx HAL Driver version number V1.0.3.

[31:24] main version

Definition at line 73 of file stm32f7xx_hal.c.

#define __STM32F7xx_HAL_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 76 of file stm32f7xx_hal.c.

#define __STM32F7xx_HAL_VERSION_SUB1 (0x00)

[23:16] sub1 version

Definition at line 74 of file stm32f7xx_hal.c.

#define __STM32F7xx_HAL_VERSION_SUB2 (0x03)

[15:8] sub2 version

Definition at line 75 of file stm32f7xx_hal.c.

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Definition at line 82 of file stm32f7xx_hal.c.

Referenced by HAL_GetDEVID().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitializes the ADCx peripheral registers to their default reset values.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitializes the ADCx peripheral registers to their default reset values.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 336 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_DISABLE, ADC_CLEAR_ERRORCODE, assert_param, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.

Note:
This function is used to configure the global features of the ADC ( ClockPrescaler, Resolution, Data Alignment and number of conversion), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, DMA continuous request after the last transfer and End of conversion selection).
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 259 of file stm32f7xx_hal_adc.c.

References ADC_CLEAR_ERRORCODE, ADC_Init(), ADC_SOFTWARE_START, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::EOCSelection, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_DATA_ALIGN, IS_ADC_EOCSelection, IS_ADC_EXT_TRIG, IS_ADC_EXT_TRIG_EDGE, IS_ADC_REGULAR_LENGTH, IS_ADC_RESOLUTION, ADC_HandleTypeDef::Lock, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::Resolution, ADC_InitTypeDef::ScanConvMode, and ADC_HandleTypeDef::State.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitializes the ADC MSP.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 398 of file stm32f7xx_hal_adc.c.

Referenced by HAL_ADC_DeInit().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initializes the ADC MSP.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 383 of file stm32f7xx_hal_adc.c.

Referenced by HAL_ADC_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
ADC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for regular conversion complete.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Disables the interrupt and stop ADC conversion of regular channels.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Gets the converted value from data register of regular channel.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion half DMA transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
Error ADC callback.

Detailed Description

IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular channel.
      (+) Stop conversion of regular channel.
      (+) Start conversion of regular channel and enable interrupt.
      (+) Stop conversion of regular channel and disable interrupt.
      (+) Start conversion of regular channel and enable DMA transfer.
      (+) Stop conversion of regular channel and disable DMA transfer.
      (+) Handle ADC interrupt request.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Regular conversion complete callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1187 of file stm32f7xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), and HAL_ADC_IRQHandler().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Regular conversion half DMA transfer callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1202 of file stm32f7xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt(), and ADC_MultiModeDMAHalfConvCplt().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

Error ADC callback.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1232 of file stm32f7xx_hal_adc.c.

Referenced by ADC_DMAError(), ADC_MultiModeDMAError(), and HAL_ADC_IRQHandler().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Gets the converted value from data register of regular channel.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
Converted value

Definition at line 1175 of file stm32f7xx_hal_adc.c.

References ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handles ADC interrupt request.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 865 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, __HAL_ADC_GET_IT_SOURCE, ADC_FLAG_AWD, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_FLAG_OVR, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_AWD, ADC_IT_EOC, ADC_IT_JEOC, ADC_IT_OVR, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADCEx_InjectedConvCpltCallback(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EOCSelection, IS_ADC_REGULAR_LENGTH, ADC_InitTypeDef::NbrOfConversion, and ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1217 of file stm32f7xx_hal_adc.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Poll for regular conversion complete.

Note:
ADC conversion flags EOS (end of sequence) and EOC (end of conversion) are cleared by this function.
This function cannot be used in a particular setup: ADC configured in DMA mode and polling for end of each conversion (ADC init parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. Nevertheless, polling can still be performed on the complete sequence.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 581 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_FLAG_EOC, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_REGULAR, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for conversion event.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
EventType,: the ADC event type. This parameter can be one of the following values:
  • ADC_AWD_EVENT: ADC Analog watch Dog event.
  • ADC_OVR_EVENT: ADC Overrun event.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 666 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD_EVENT, ADC_FLAG_AWD, ADC_FLAG_OVR, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enables ADC and starts conversion of the regular channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 437 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, ADC_CLEAR_ERRORCODE, ADC_FLAG_EOC, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
pData,: The destination Buffer address.
Length,: The length of data to be transferred from ADC peripheral to memory.
Return values:
HAL status

Definition at line 1010 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_FLAG_EOC, ADC_IT_OVR, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enables the interrupt and starts ADC conversion of regular channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 728 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_FLAG_EOC, ADC_IT_EOC, ADC_IT_OVR, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Disables ADC and stop conversion of regular channels.

Note:
Caution: This function will stop also injected channels.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 538 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_DISABLE, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 1129 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Disables the interrupt and stop ADC conversion of regular channels.

Note:
Caution: This function will stop also injected channels.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 831 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_DISABLE, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure regular channels.
      (+) Configure injected channels.
      (+) Configure multimode.
      (+) Configure the analog watch dog.

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configures the analog watchdog.

Note:
Analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: the programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure that contains the configuration information of ADC analog watchdog.
Return values:
HAL status

Definition at line 1384 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_GET_RESOLUTION, ADC_IT_AWD, assert_param, ADC_AnalogWDGConfTypeDef::Channel, ADC_AnalogWDGConfTypeDef::HighThreshold, ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, ADC_AnalogWDGConfTypeDef::LowThreshold, and ADC_AnalogWDGConfTypeDef::WatchdogMode.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
sConfig,: ADC configuration structure.
Return values:
HAL status

Definition at line 1270 of file stm32f7xx_hal_adc.c.

References ADC_CHANNEL_18, ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_SMPR1, ADC_SMPR2, ADC_SQR1_RK, ADC_SQR2_RK, ADC_SQR3_RK, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_ChannelConfTypeDef::Channel, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_ChannelConfTypeDef::Rank, and ADC_ChannelConfTypeDef::SamplingTime.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Peripheral State functions

Functions
ADC Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral State and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the ADC state
      (+) Check the ADC Error

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
ADC Error Code

Definition at line 1478 of file stm32f7xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

return the ADC state

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL state

Definition at line 1466 of file stm32f7xx_hal_adc.c.

References ADC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

static void | ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct without initializing the ADC MSP.
static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

static void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1585 of file stm32f7xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_EOC, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_ConvCpltCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1651 of file stm32f7xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1638 of file stm32f7xx_hal_adc.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA().

static void ADC_Init ( ADC_HandleTypeDef * hadc ) [static]

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct without initializing the ADC MSP.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1504 of file stm32f7xx_hal_adc.c.

References ADC_CR1_DISCONTINUOUS, ADC_CR1_SCANCONV, ADC_CR2_CONTINUOUS, ADC_CR2_DMAContReq, ADC_CR2_EOCSelection, ADC_SOFTWARE_START, ADC_SQR1, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::EOCSelection, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_REGULAR_DISC_NUMBER, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Resolution, and ADC_InitTypeDef::ScanConvMode.

Referenced by HAL_ADC_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Exported Types

Data Structures | Defines
ADC Exported Types
ADC

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration multi-mode structure definition. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)

Define Documentation

#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)

Out-of-window occurrence of analog watchdog 1

Definition at line 196 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)

Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2

Definition at line 197 of file stm32f7xx_hal_adc.h.

#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)

Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3

Definition at line 198 of file stm32f7xx_hal_adc.h.

#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)

ADC is busy to internal process (initialization, calibration)

Definition at line 176 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)

Configuration error occurrence

Definition at line 181 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)

DMA error occurrence

Definition at line 182 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), ADC_MultiModeDMAConvCplt(), and ADC_MultiModeDMAError().

#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)

Internal error occurrence

Definition at line 180 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)

A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 191 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)

Conversion data available on group injected

Definition at line 193 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)

Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master (

Definition at line 201 of file stm32f7xx_hal_adc.h.

#define HAL_ADC_STATE_READY ((uint32_t)0x00000001)

ADC peripheral ready for use

Definition at line 175 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)

A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 185 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)

Conversion data available on group regular

Definition at line 187 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)

Overrun occurrence

Definition at line 188 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000)

HAL ADC state machine: ADC states definition (bitfields)

ADC not yet initialized or disabled

Definition at line 174 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)

TimeOut occurrence

Definition at line 177 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC and regular group initialization. More...

#include <stm32f7xx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | EOCSelection
uint32_t | ContinuousConvMode
uint32_t | NbrOfConversion
uint32_t | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
uint32_t | DMAContinuousRequests

Detailed Description

Structure definition of ADC and regular group initialization.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
  • Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
  • For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).

Definition at line 75 of file stm32f7xx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock prescaler. The clock is common for all the ADCs. This parameter can be a value of ADC Clock Prescaler

Definition at line 77 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ContinuousConvMode

Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 98 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Init(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::DataAlign

Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of ADC Data Align

Definition at line 82 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DiscontinuousConvMode

Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 104 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DMAContinuousRequests

Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) or in Continuous mode (DMA transfer unlimited, whatever number of conversions). Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). This parameter can be set to ENABLE or DISABLE.

Definition at line 118 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::EOCSelection

Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of ADC EOC Selection. Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence

Definition at line 91 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge by default. This parameter can be a value of ADC External Trigger Source Regular

Definition at line 111 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Selects the external trigger edge of regular group. If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC External Trigger Edge Regular

Definition at line 115 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16.

Definition at line 101 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 108 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

uint32_t ADC_InitTypeDef::Resolution

Configures the ADC resolution. This parameter can be a value of ADC Resolution

Definition at line 80 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'.

Definition at line 85 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_adc.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32f7xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | Offset

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC can be either disabled or enabled without conversion on going on regular group.

Definition at line 132 of file stm32f7xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specifies the channel to configure into ADC regular group. This parameter can be a value of ADC Common Channels

Definition at line 134 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Reserved for future use, can be set to 0

Definition at line 147 of file stm32f7xx_hal_adc.h.

uint32_t ADC_ChannelConfTypeDef::Rank

Specifies the rank in the regular group sequencer. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 136 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). This parameter can be a value of ADC Sampling Times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min).

Definition at line 138 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_adc.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

ADC Configuration multi-mode structure definition. More...

#include <stm32f7xx_hal_adc.h>

Data Fields

uint32_t | WatchdogMode
uint32_t | HighThreshold
uint32_t | LowThreshold
uint32_t | Channel
uint32_t | ITMode
uint32_t | WatchdogNumber

Detailed Description

ADC Configuration multi-mode structure definition.

Definition at line 153 of file stm32f7xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Configures ADC channel for the analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel This parameter can be a value of ADC Common Channels

Definition at line 161 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value.

Definition at line 157 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::ITMode

Specifies whether the analog watchdog is configured is interrupt mode or in polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 164 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value.

Definition at line 159 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configures the ADC analog watchdog mode. This parameter can be a value of ADC Analog Watchdog Selection

Definition at line 155 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Reserved for future use, can be set to 0

Definition at line 167 of file stm32f7xx_hal_adc.h.

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_adc.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32f7xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
__IO uint32_t | NbrOfCurrentConversionRank
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

ADC handle Structure definition.

Definition at line 207 of file stm32f7xx_hal_adc.h.

Field Documentation

DMA_HandleTypeDef* ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 215 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

__IO uint32_t ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 221 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAError(), ADC_MultiModeDMAError(), HAL_ADC_GetError(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_InitTypeDef ADC_HandleTypeDef::Init

ADC required parameters

Definition at line 211 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Init(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_TypeDef* ADC_HandleTypeDef::Instance

Register base address

Definition at line 209 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Init(), ADC_MultiModeDMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

HAL_LockTypeDef ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 217 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

__IO uint32_t ADC_HandleTypeDef::NbrOfCurrentConversionRank

ADC number of current conversion rank

Definition at line 213 of file stm32f7xx_hal_adc.h.

__IO uint32_t ADC_HandleTypeDef::State

ADC communication state

Definition at line 219 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), ADC_MultiModeDMAConvCplt(), ADC_MultiModeDMAError(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_adc.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04)

Define Documentation

#define HAL_ADC_ERROR_DMA ((uint32_t)0x04)

DMA transfer error

Definition at line 239 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAError(), ADC_MultiModeDMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)

ADC IP internal error: if problem of clocking, enable/disable, erroneous state

Definition at line 236 of file stm32f7xx_hal_adc.h.

#define HAL_ADC_ERROR_NONE ((uint32_t)0x00)

No error

Definition at line 235 of file stm32f7xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR ((uint32_t)0x02)

Overrun error

Definition at line 238 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Clock Prescaler

Defines
ADC Clock Prescaler
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)

Define Documentation

#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)

Definition at line 248 of file stm32f7xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)

Definition at line 249 of file stm32f7xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)

Definition at line 250 of file stm32f7xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)

Definition at line 251 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Delay Between 2 Sampling Phases

Defines
ADC Delay Between 2 Sampling Phases
ADC Exported Constants

Defines

#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define | ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define | ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)

Define Documentation

#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))

Definition at line 264 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))

Definition at line 265 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Definition at line 266 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)

Definition at line 267 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))

Definition at line 268 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))

Definition at line 269 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Definition at line 270 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))

Definition at line 271 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))

Definition at line 272 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))

Definition at line 273 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)

Definition at line 274 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)

Definition at line 259 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)

Definition at line 260 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)

Definition at line 261 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Definition at line 262 of file stm32f7xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)

Definition at line 263 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Resolution

Defines
ADC Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_12B ((uint32_t)0x00000000)
#define | ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define | ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)

Define Documentation

#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)

Definition at line 283 of file stm32f7xx_hal_adc.h.

#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)

Definition at line 282 of file stm32f7xx_hal_adc.h.

#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)

Definition at line 285 of file stm32f7xx_hal_adc.h.

#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)

Definition at line 284 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC External Trigger Edge Regular

Defines
ADC External Trigger Edge Regular
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)

Definition at line 295 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)

Definition at line 293 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)

Definition at line 294 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)

Definition at line 296 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC External Trigger Source Regular

Defines
ADC External Trigger Source Regular
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define | ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
#define | ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
#define | ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define | ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)

Define Documentation

#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)

Definition at line 323 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)

Definition at line 308 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)

Definition at line 309 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)

Definition at line 310 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))

Definition at line 317 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))

Definition at line 318 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 311 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 319 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))

Definition at line 314 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))

Definition at line 313 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))

Definition at line 320 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)

Definition at line 312 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))

Definition at line 321 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 315 of file stm32f7xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)

Definition at line 316 of file stm32f7xx_hal_adc.h.

#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)

Definition at line 324 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Data Align

Defines
ADC Data Align
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Define Documentation

#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Definition at line 334 of file stm32f7xx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)

Definition at line 333 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Common Channels

Defines
ADC Common Channels
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 ((uint32_t)0x00000000)
#define | ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define | ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)

Define Documentation

#define ADC_CHANNEL_0 ((uint32_t)0x00000000)

Definition at line 342 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)

Definition at line 343 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))

Definition at line 352 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 353 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))

Definition at line 354 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))

Definition at line 355 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))

Definition at line 356 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 357 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)

Definition at line 358 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))

Definition at line 359 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))

Definition at line 360 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)

Definition at line 344 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 345 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)

Definition at line 346 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))

Definition at line 347 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))

Definition at line 348 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 349 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)

Definition at line 350 of file stm32f7xx_hal_adc.h.

#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))

Definition at line 351 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)

Definition at line 363 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)

Definition at line 362 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Sampling Times

Defines
ADC Sampling Times
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
#define | ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define | ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define | ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
#define | ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define | ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)

Define Documentation

#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))

Definition at line 376 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))

Definition at line 377 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)

Definition at line 372 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)

Definition at line 373 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)

Definition at line 371 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)

Definition at line 378 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))

Definition at line 374 of file stm32f7xx_hal_adc.h.

#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)

Definition at line 375 of file stm32f7xx_hal_adc.h.

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STM32F745xx HAL User Manual: ADC EOC Selection

Defines
ADC EOC Selection
ADC Exported Constants

Defines

#define | ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
#define | ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
#define | ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002)

Define Documentation

#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)

Definition at line 386 of file stm32f7xx_hal_adc.h.

#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)

Definition at line 387 of file stm32f7xx_hal_adc.h.

#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002)

reserved for future use

Definition at line 388 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Event Type

Defines
ADC Event Type
ADC Exported Constants

Defines

#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)

Define Documentation

#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)

Definition at line 396 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)

Definition at line 397 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Analog Watchdog Selection

Defines
ADC Analog Watchdog Selection
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)

Definition at line 409 of file stm32f7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)

Definition at line 408 of file stm32f7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 410 of file stm32f7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)

Definition at line 411 of file stm32f7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))

Definition at line 406 of file stm32f7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))

Definition at line 405 of file stm32f7xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 407 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Interrupts Definition

Defines
ADC Interrupts Definition
ADC Exported Constants

Defines

#define | ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define | ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define | ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define | ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)

Define Documentation

#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)

Definition at line 420 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)

Definition at line 419 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_IRQHandler(), and HAL_ADC_Start_IT().

#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)

Definition at line 421 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)

Definition at line 422 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Flags Definition

Defines
ADC Flags Definition
ADC Exported Constants

Defines

#define | ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
#define | ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
#define | ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
#define | ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
#define | ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
#define | ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)

Define Documentation

#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)

Definition at line 430 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)

Definition at line 431 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)

Definition at line 432 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)

Definition at line 433 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)

Definition at line 435 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)

Definition at line 434 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Channels Type

Defines
ADC Channels Type
ADC Exported Constants

Defines

#define | ADC_ALL_CHANNELS ((uint32_t)0x00000001)
#define | ADC_REGULAR_CHANNELS ((uint32_t)0x00000002)
#define | ADC_INJECTED_CHANNELS ((uint32_t)0x00000003)

Define Documentation

#define ADC_ALL_CHANNELS ((uint32_t)0x00000001)

Definition at line 443 of file stm32f7xx_hal_adc.h.

#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003)

reserved for future use

Definition at line 445 of file stm32f7xx_hal_adc.h.

#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002)

reserved for future use

Definition at line 444 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Exported Macros

Defines
ADC Exported Macros
ADC | STM32F7xx_HAL_Driver

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Check if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clear the ADC's pending flags.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__FLAG__))

Clear the ADC's pending flags.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__FLAG__,: ADC flag.
Return values:
None

Definition at line 508 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)

Disable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 477 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))

Disable the ADC end of conversion interrupt.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__INTERRUPT__,: ADC interrupt.
Return values:
None

Definition at line 493 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), HAL_ADC_Stop_DMA(), HAL_ADCEx_InjectedStop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

#define __HAL_ADC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)

Enable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 470 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))

Enable the ADC end of conversion interrupt.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__INTERRUPT__,: ADC Interrupt.
Return values:
None

Definition at line 485 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected ADC's flag status.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__FLAG__,: ADC flag.
Return values:
None

Definition at line 516 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))

Check if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__INTERRUPT__,: specifies the ADC interrupt source to check.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 500 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler().

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 463 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_STAB_DELAY_US ((uint32_t) 3)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)

Define Documentation

#define ADC_STAB_DELAY_US ((uint32_t) 3)

Definition at line 603 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)

Definition at line 607 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_ADC_EXT_TRIG_EDGE(__EDGE__)
#define | IS_ADC_EXT_TRIG(__REGTRIG__)
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
#define | IS_ADC_SAMPLE_TIME(__TIME__)
#define | IS_ADC_EOCSelection(__EOCSelection__)
#define | IS_ADC_EVENT_TYPE(__EVENT__)
#define | IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__)
#define | IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE)
#define | IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
#define | IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
#define | IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
#define | IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)
#define | ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
Set ADC Regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
Enable ADC scan mode.
#define | ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
Enable the ADC end of conversion selection.
#define | ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
Enable the ADC DMA continuous request.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
Return resolution bits in CR1 register.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to error code: "no error")

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 660 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_CR1_DISCONTINUOUS ( _NBR_DISCONTINUOUSCONV_ ) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))

Configures the number of discontinuous conversions for the regular group channels.

Parameters:
_NBR_DISCONTINUOUSCONV_,: Number of discontinuous conversions.
Return values:
None

Definition at line 801 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR1_SCANCONV ( _SCANCONV_MODE_ ) ((_SCANCONV_MODE_) << 8)

Enable ADC scan mode.

Parameters:
_SCANCONV_MODE_,: Scan conversion mode.
Return values:
None

Definition at line 808 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR2_CONTINUOUS ( _CONTINUOUS_MODE_ ) ((_CONTINUOUS_MODE_) << 1)

Enable ADC continuous conversion mode.

Parameters:
_CONTINUOUS_MODE_,: Continuous mode.
Return values:
None

Definition at line 794 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR2_DMAContReq ( _DMAContReq_MODE_ ) ((_DMAContReq_MODE_) << 9)

Enable the ADC DMA continuous request.

Parameters:
_DMAContReq_MODE_,: DMA continuous request mode.
Return values:
None

Definition at line 822 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR2_EOCSelection ( _EOCSelection_MODE_ ) ((_EOCSelection_MODE_) << 10)

Enable the ADC end of conversion selection.

Parameters:
_EOCSelection_MODE_,: End of conversion selection mode.
Return values:
None

Definition at line 815 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)

Return resolution bits in CR1 register.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 829 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
  ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 624 of file stm32f7xx_hal_adc.h.

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 643 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 634 of file stm32f7xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_SMPR1 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))

Set the ADC's sample time for channel numbers between 10 and 18.

Parameters:
_SAMPLETIME_,: Sample time parameter.
_CHANNELNB_,: Channel number.
Return values:
None

Definition at line 755 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR2 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))

Set the ADC's sample time for channel numbers between 0 and 9.

Parameters:
_SAMPLETIME_,: Sample time parameter.
_CHANNELNB_,: Channel number.
Return values:
None

Definition at line 763 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1 ( _NbrOfConversion_ ) (((_NbrOfConversion_) - (uint8_t)1) << 20)

Set ADC Regular channel sequence length.

Parameters:
_NbrOfConversion_,: Regular channel sequence length.
Return values:
None

Definition at line 747 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))

Set the selected regular channel rank for rank between 13 and 16.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 787 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR2_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))

Set the selected regular channel rank for rank between 7 and 12.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 779 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR3_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))

Set the selected regular channel rank for rank between 1 and 6.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 771 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clears and sets specific bits of the handle State.

Note:
: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 653 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define IS_ADC_ANALOG_WATCHDOG ( __WATCHDOG__ )
Value:
(((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))

Definition at line 722 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CHANNELS_TYPE ( CHANNEL_TYPE )
Value:
(((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))

Definition at line 729 of file stm32f7xx_hal_adc.h.

#define IS_ADC_CLOCKPRESCALER ( __ADC_CLOCK__ )
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))

Definition at line 662 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DATA_ALIGN ( __ALIGN__ )
Value:
(((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))

Definition at line 706 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOCSelection ( __EOCSelection__ )
Value:
(((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \
                                               ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \
                                               ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))

Definition at line 717 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EVENT_TYPE ( __EVENT__ )
Value:
(((__EVENT__) == ADC_AWD_EVENT) || \
                                      ((__EVENT__) == ADC_OVR_EVENT))

Definition at line 720 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXT_TRIG ( __REGTRIG__ )
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
                                                                                ((__REGTRIG__) == ADC_SOFTWARE_START))

Definition at line 690 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXT_TRIG_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))

Definition at line 686 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define IS_ADC_RANGE | ( | __RESOLUTION__,
 |  | __ADC_VALUE__
 | ) |
Value:
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))

Definition at line 736 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISC_NUMBER ( __NUMBER__ ) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))

Definition at line 735 of file stm32f7xx_hal_adc.h.

Referenced by ADC_Init().

#define IS_ADC_REGULAR_LENGTH ( __LENGTH__ ) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))

Definition at line 733 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_REGULAR_RANK ( __RANK__ ) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))

Definition at line 734 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B))

Definition at line 682 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_SAMPLE_TIME ( __TIME__ )
Value:
(((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
                                      ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
                                      ((__TIME__) == ADC_SAMPLETIME_480CYCLES))

Definition at line 709 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLING_DELAY ( __DELAY__ )
Value:
(((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))

Definition at line 666 of file stm32f7xx_hal_adc.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_THRESHOLD ( __THRESHOLD__ ) ((__THRESHOLD__) <= ((uint32_t)0xFFF))

Definition at line 732 of file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended features functions

Functions
Extended features functions
ADC Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables the selected ADC software start conversion of the injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for injected conversion complete.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Gets the converted value from data register of injected channel.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Configures the ADC multi-mode.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of injected channel.
      (+) Stop conversion of injected channel.
      (+) Start multimode and enable DMA transfer.
      (+) Stop multimode and disable DMA transfer.
      (+) Get result of injected channel conversion.
      (+) Get result of multimode conversion.
      (+) Configure injected channels.
      (+) Configure multimode.

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
sConfigInjected,: ADC configuration structure for injected channel.
Return values:
None

Definition at line 786 of file stm32f7xx_hal_adc_ex.c.

References ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_GET_RESOLUTION, ADC_INJECTED_SOFTWARE_START, ADC_JSQR, ADC_SMPR1, ADC_SMPR2, ADC_SQR1, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_EXT_INJEC_TRIG, IS_ADC_EXT_INJEC_TRIG_EDGE, IS_ADC_INJECTED_LENGTH, IS_ADC_INJECTED_RANK, IS_ADC_RANGE, and IS_ADC_SAMPLE_TIME.

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 769 of file stm32f7xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Gets the converted value from data register of injected channel.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
InjectedRank,: the ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1: Injected Channel1 selected
  • ADC_INJECTED_RANK_2: Injected Channel2 selected
  • ADC_INJECTED_RANK_3: Injected Channel3 selected
  • ADC_INJECTED_RANK_4: Injected Channel4 selected
Return values:
None

Definition at line 546 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_FLAG_JEOC, ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Poll for injected conversion complete.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 417 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enables the selected ADC software start conversion of the injected channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 177 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, ADC_CLEAR_ERRORCODE, ADC_FLAG_JEOC, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enables the interrupt and starts ADC conversion of injected channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 266 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_FLAG_JEOC, ADC_IT_JEOC, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of auto-injection mode, HAL_ADC_Stop must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 363 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 484 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_JEOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_MultiModeTypeDef * | multimode
 | ) |  |

Configures the ADC multi-mode.

Parameters:
hadc | : pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
multimode | : pointer to an ADC_MultiModeTypeDef structure that contains the configuration information for multimode.
Return values:
HAL status

Definition at line 942 of file stm32f7xx_hal_adc_ex.c.

References assert_param, ADC_MultiModeTypeDef::DMAAccessMode, IS_ADC_DMA_ACCESS_MODE, IS_ADC_MODE, IS_ADC_SAMPLING_DELAY, ADC_MultiModeTypeDef::Mode, and ADC_MultiModeTypeDef::TwoSamplingDelay.

uint32_t HAL_ADCEx_MultiModeGetValue ( ADC_HandleTypeDef * hadc )

Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
The converted data value.

Definition at line 757 of file stm32f7xx_hal_adc_ex.c.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.

Note:
Caution: This function must be used only with the ADC master.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
pData,: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
Length,: The length of data to be transferred from ADC peripheral to memory.
Return values:
HAL status

Definition at line 597 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_FLAG_EOC, ADC_IT_OVR, ADC_MultiModeDMAConvCplt(), ADC_MultiModeDMAError(), ADC_MultiModeDMAHalfConvCplt(), ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, ADC_InitTypeDef::DMAContinuousRequests, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 710 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Exported Functions

Modules | Functions
ADC Exported Functions
ADCEx | STM32F7xx_HAL_Driver

Modules

Extended features functions

Extended features functions.

Functions

static void | ADC_MultiModeDMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_MultiModeDMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | ADC_MultiModeDMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void ADC_MultiModeDMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 981 of file stm32f7xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_EOC, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_ConvCpltCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADCEx_MultiModeStart_DMA().

static void ADC_MultiModeDMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1047 of file stm32f7xx_hal_adc_ex.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADCEx_MultiModeStart_DMA().

static void ADC_MultiModeDMAHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1034 of file stm32f7xx_hal_adc_ex.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADCEx_MultiModeStart_DMA().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Exported Types

ADC Configuration injected Channel structure definition. More...

#include <stm32f7xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedOffset
uint32_t | InjectedNbrOfConversion
uint32_t | InjectedDiscontinuousConvMode
uint32_t | AutoInjectedConv
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge

Detailed Description

ADC Configuration injected Channel structure definition.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
  • Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
  • For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.

Definition at line 74 of file stm32f7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 107 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of ADC External Trigger Source Injected Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 115 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC External Trigger Edge Injected. If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 123 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Selection of ADC channel to configure This parameter can be a value of ADC Common Channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.

Definition at line 76 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 100 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 95 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.

Definition at line 91 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Rank in the injected group sequencer This parameter must be a value of ADC Injected Channel Selection Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted)

Definition at line 79 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). This parameter can be a value of ADC Sampling Times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min).

Definition at line 82 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_adc_ex.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Private Functions

ADC Private Functions
STM32F7xx_HAL_Driver | ADCEx
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADCEx

ADC Configuration multi-mode structure definition. More...

#include <stm32f7xx_hal_adc_ex.h>

Data Fields

uint32_t | Mode
uint32_t | DMAAccessMode
uint32_t | TwoSamplingDelay

Detailed Description

ADC Configuration multi-mode structure definition.

Definition at line 136 of file stm32f7xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::DMAAccessMode

Configures the Direct memory access mode for multi ADC mode. This parameter can be a value of ADC Direct Memory Access Mode For Multi Mode

Definition at line 140 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or multi mode. This parameter can be a value of ADC Common Mode

Definition at line 138 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::TwoSamplingDelay

Configures the Delay between 2 sampling phases. This parameter can be a value of ADC Delay Between 2 Sampling Phases

Definition at line 142 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_adc_ex.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Common Mode

Defines
ADC Common Mode
ADC Exported Constants

Defines

#define | ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))

Define Documentation

#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))

Definition at line 164 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))

Definition at line 161 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))

Definition at line 163 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))

Definition at line 162 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)

Definition at line 160 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)

Definition at line 159 of file stm32f7xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)

Definition at line 158 of file stm32f7xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))

Definition at line 170 of file stm32f7xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))

Definition at line 167 of file stm32f7xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))

Definition at line 169 of file stm32f7xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))

Definition at line 168 of file stm32f7xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))

Definition at line 166 of file stm32f7xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))

Definition at line 165 of file stm32f7xx_hal_adc_ex.h.

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STM32F745xx HAL User Manual: ADC Direct Memory Access Mode For Multi Mode

Defines
ADC Direct Memory Access Mode For Multi Mode
ADC Exported Constants

Defines

#define | ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000)
#define | ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0)
#define | ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1)
#define | ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA)

Define Documentation

#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0)

DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)

Definition at line 179 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1)

DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)

Definition at line 180 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA)

DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)

Definition at line 181 of file stm32f7xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000)

DMA mode disabled

Definition at line 178 of file stm32f7xx_hal_adc_ex.h.

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STM32F745xx HAL User Manual: ADC External Trigger Edge Injected

Defines
ADC External Trigger Edge Injected
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)

Definition at line 191 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)

Definition at line 189 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)

Definition at line 190 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)

Definition at line 192 of file stm32f7xx_hal_adc_ex.h.

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STM32F745xx HAL User Manual: ADC External Trigger Source Injected

Defines
ADC External Trigger Source Injected
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)

Definition at line 201 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000)

Definition at line 200 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3)

Definition at line 208 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 203 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)

Definition at line 202 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))

Definition at line 213 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 211 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2)

Definition at line 204 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))

Definition at line 205 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))

Definition at line 212 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))

Definition at line 214 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 207 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))

Definition at line 209 of file stm32f7xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))

Definition at line 210 of file stm32f7xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)

Definition at line 215 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

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STM32F745xx HAL User Manual: ADC Injected Channel Selection

Defines
ADC Injected Channel Selection
ADC Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

Define Documentation

#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)

Definition at line 223 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)

Definition at line 224 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)

Definition at line 225 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

Definition at line 226 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

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STM32F745xx HAL User Manual: ADC Specific Channels

Defines
ADC Specific Channels
ADC Exported Constants

Defines

#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000)

Define Documentation

#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000)

Definition at line 234 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32F745xx HAL User Manual: ADC Private Constants

ADC Private Constants
STM32F7xx_HAL_Driver
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
STM32F7xx_HAL_Driver

Defines

#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_MODE(__MODE__)
#define | IS_ADC_DMA_ACCESS_MODE(__MODE__)
#define | IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__)
#define | IS_ADC_EXT_INJEC_TRIG(__INJTRIG__)
#define | IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
#define | IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
#define | ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
Set the selected injected Channel rank.

Define Documentation

#define ADC_JSQR | ( | _CHANNELNB_,
 |  | _RANKNB_,
 |  | _JSQR_JL_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))

Set the selected injected Channel rank.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
_JSQR_JL_,: Sequence length.
Return values:
None

Definition at line 347 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) <= ADC_CHANNEL_18)  || \
                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))

Definition at line 298 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_DMA_ACCESS_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
                                          ((__MODE__) == ADC_DMAACCESSMODE_1)        || \
                                          ((__MODE__) == ADC_DMAACCESSMODE_2)        || \
                                          ((__MODE__) == ADC_DMAACCESSMODE_3))

Definition at line 314 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_EXT_INJEC_TRIG ( __INJTRIG__ )
Value:
(((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
                                                                                ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))

Definition at line 322 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXT_INJEC_TRIG_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))

Definition at line 318 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_LENGTH ( __LENGTH__ ) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))

Definition at line 337 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( __RANK__ ) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))

Definition at line 338 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_MODE_INDEPENDENT)                 || \
                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)             || \
                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)               || \
                               ((__MODE__) == ADC_DUALMODE_INTERL)                  || \
                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               || \
                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
                               ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT)           || \
                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT)             || \
                               ((__MODE__) == ADC_TRIPLEMODE_INTERL)                || \
                               ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))

Definition at line 301 of file stm32f7xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

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STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the CAN.
      (+) De-initialize the CAN.

Function Documentation

HAL_StatusTypeDef HAL_CAN_ConfigFilter | ( | CAN_HandleTypeDef * | hcan,
 |  | CAN_FilterConfTypeDef * | sFilterConfig
 | ) |  |

Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
sFilterConfig,: pointer to a CAN_FilterConfTypeDef structure that contains the filter configuration information.
Return values:
None

Definition at line 357 of file stm32f7xx_hal_can.c.

References assert_param, CAN_FilterConfTypeDef::BankNumber, CAN_FILTER_FIFO0, CAN_FILTER_FIFO1, CAN_FILTERMODE_IDMASK, CAN_FILTERSCALE_16BIT, CAN_FILTERSCALE_32BIT, CAN_FilterConfTypeDef::FilterActivation, CAN_FilterConfTypeDef::FilterFIFOAssignment, CAN_FilterConfTypeDef::FilterIdHigh, CAN_FilterConfTypeDef::FilterIdLow, CAN_FilterConfTypeDef::FilterMaskIdHigh, CAN_FilterConfTypeDef::FilterMaskIdLow, CAN_FilterConfTypeDef::FilterMode, CAN_FilterConfTypeDef::FilterNumber, CAN_FilterConfTypeDef::FilterScale, IS_CAN_BANKNUMBER, IS_CAN_FILTER_FIFO, IS_CAN_FILTER_MODE, IS_CAN_FILTER_NUMBER, and IS_CAN_FILTER_SCALE.

HAL_StatusTypeDef HAL_CAN_DeInit ( CAN_HandleTypeDef * hcan )

Deinitializes the CANx peripheral registers to their default reset values.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 458 of file stm32f7xx_hal_can.c.

References assert_param, HAL_CAN_MspDeInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_RESET, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Init ( CAN_HandleTypeDef * hcan )

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 166 of file stm32f7xx_hal_can.c.

References CAN_InitTypeDef::ABOM, assert_param, CAN_InitTypeDef::AWUM, CAN_InitTypeDef::BS1, CAN_InitTypeDef::BS2, CAN_INITSTATUS_FAILED, CAN_INITSTATUS_SUCCESS, CAN_TIMEOUT_VALUE, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_MspInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_RESET, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Init, CAN_HandleTypeDef::Instance, IS_CAN_BS1, IS_CAN_BS2, IS_CAN_MODE, IS_CAN_PRESCALER, IS_CAN_SJW, CAN_HandleTypeDef::Lock, CAN_InitTypeDef::Mode, CAN_InitTypeDef::NART, CAN_InitTypeDef::Prescaler, CAN_InitTypeDef::RFLM, CAN_InitTypeDef::SJW, CAN_HandleTypeDef::State, CAN_InitTypeDef::TTCM, and CAN_InitTypeDef::TXFP.

void HAL_CAN_MspDeInit ( CAN_HandleTypeDef * hcan )

DeInitializes the CAN MSP.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 506 of file stm32f7xx_hal_can.c.

Referenced by HAL_CAN_DeInit().

void HAL_CAN_MspInit ( CAN_HandleTypeDef * hcan )

Initializes the CAN MSP.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 491 of file stm32f7xx_hal_can.c.

Referenced by HAL_CAN_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
CAN Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Transmit a CAN frame message.
      (+) Receive a CAN frame message.
      (+) Enter CAN peripheral in sleep mode.
      (+) Wake up the CAN peripheral from sleep mode.

Function Documentation

void HAL_CAN_ErrorCallback ( CAN_HandleTypeDef * hcan )

Error CAN callback.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1244 of file stm32f7xx_hal_can.c.

Referenced by HAL_CAN_IRQHandler().

void HAL_CAN_IRQHandler ( CAN_HandleTypeDef * hcan )

Handles CAN interrupt request.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1084 of file stm32f7xx_hal_can.c.

References __HAL_CAN_CLEAR_FLAG, __HAL_CAN_GET_FLAG, __HAL_CAN_GET_IT_SOURCE, __HAL_CAN_MSG_PENDING, __HAL_CAN_TRANSMIT_STATUS, CAN_FIFO0, CAN_FIFO1, CAN_FLAG_BOF, CAN_FLAG_EPV, CAN_FLAG_EWG, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_LEC, CAN_IT_TME, CAN_Receive_IT(), CAN_Transmit_IT(), CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_ACK, HAL_CAN_ERROR_BD, HAL_CAN_ERROR_BOF, HAL_CAN_ERROR_BR, HAL_CAN_ERROR_CRC, HAL_CAN_ERROR_EPV, HAL_CAN_ERROR_EWG, HAL_CAN_ERROR_FOR, HAL_CAN_ERROR_NONE, HAL_CAN_ERROR_STF, HAL_CAN_ErrorCallback(), HAL_CAN_STATE_READY, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Receive | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber,
 |  | uint32_t | Timeout
 | ) |  |

Receives a correct CAN frame.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: FIFO Number value
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 799 of file stm32f7xx_hal_can.c.

References __HAL_CAN_FIFO_RELEASE, __HAL_CAN_MSG_PENDING, assert_param, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FMI, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_FIFO, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  |

Receives a correct CAN frame.

Parameters:
hcan,: Pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: Specify the FIFO number
Return values:
HAL status

Definition at line 905 of file stm32f7xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_FIFO0, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_LEC, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, IS_CAN_FIFO, and CAN_HandleTypeDef::State.

void HAL_CAN_RxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non blocking mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1229 of file stm32f7xx_hal_can.c.

Referenced by CAN_Receive_IT().

HAL_StatusTypeDef HAL_CAN_Sleep ( CAN_HandleTypeDef * hcan )

Enters the Sleep (low power) mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 977 of file stm32f7xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Transmit | ( | CAN_HandleTypeDef * | hcan,
 |  | uint32_t | Timeout
 | ) |  |

Initiates and transmits a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 543 of file stm32f7xx_hal_can.c.

References __HAL_CAN_TRANSMIT_STATUS, assert_param, CAN_ID_STD, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CanTxMsgTypeDef::ExtId, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Transmit_IT ( CAN_HandleTypeDef * hcan )

Initiates and transmits a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 677 of file stm32f7xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CAN_HandleTypeDef::ErrorCode, CanTxMsgTypeDef::ExtId, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

void HAL_CAN_TxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non blocking mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1214 of file stm32f7xx_hal_can.c.

Referenced by CAN_Transmit_IT().

HAL_StatusTypeDef HAL_CAN_WakeUp ( CAN_HandleTypeDef * hcan )

Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 1032 of file stm32f7xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
CAN Exported Functions

CAN Peripheral State functions. More...

Functions

HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Check the CAN state.
      (+) Check CAN Errors detected during interrupt process

Function Documentation

uint32_t HAL_CAN_GetError ( CAN_HandleTypeDef * hcan )

Return the CAN error code.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
CAN Error Code

Definition at line 1291 of file stm32f7xx_hal_can.c.

References CAN_HandleTypeDef::ErrorCode.

HAL_CAN_StateTypeDef HAL_CAN_GetState ( CAN_HandleTypeDef * hcan )

return the CAN state

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL state

Definition at line 1279 of file stm32f7xx_hal_can.c.

References CAN_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Exported Functions

Modules | Functions
CAN Exported Functions
CAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral State and Error functions

CAN Peripheral State functions.

Functions

static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.

Function Documentation

static HAL_StatusTypeDef CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  | [static]

Receives a correct CAN frame.

Parameters:
hcan,: Pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: Specify the FIFO number
Return values:
HAL status
None

Definition at line 1353 of file stm32f7xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, __HAL_CAN_FIFO_RELEASE, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_LEC, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FMI, HAL_CAN_RxCpltCallback(), HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

Referenced by HAL_CAN_IRQHandler().

static HAL_StatusTypeDef CAN_Transmit_IT ( CAN_HandleTypeDef * hcan ) [static]

Initiates and transmits a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 1305 of file stm32f7xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, HAL_CAN_TxCpltCallback(), and CAN_HandleTypeDef::State.

Referenced by HAL_CAN_IRQHandler().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Exported Types

Data Structures | Enumerations
CAN Exported Types
CAN

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00, HAL_CAN_STATE_READY = 0x01, HAL_CAN_STATE_BUSY = 0x02, HAL_CAN_STATE_BUSY_TX = 0x12,
HAL_CAN_STATE_BUSY_RX = 0x22, HAL_CAN_STATE_BUSY_TX_RX = 0x32, HAL_CAN_STATE_TIMEOUT = 0x03, HAL_CAN_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_CAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_CAN_STATE_RESET

CAN not yet initialized or disabled

HAL_CAN_STATE_READY

CAN initialized and ready for use

HAL_CAN_STATE_BUSY

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX

CAN process is ongoing

HAL_CAN_STATE_BUSY_RX

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX_RX

CAN process is ongoing

HAL_CAN_STATE_TIMEOUT

Timeout state

HAL_CAN_STATE_ERROR

CAN error state

Definition at line 65 of file stm32f7xx_hal_can.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_InitTypeDef Struct Reference
CAN Exported Types

CAN init structure definition. More...

#include <stm32f7xx_hal_can.h>

Data Fields

uint32_t | Prescaler
uint32_t | Mode
uint32_t | SJW
uint32_t | BS1
uint32_t | BS2
uint32_t | TTCM
uint32_t | ABOM
uint32_t | AWUM
uint32_t | NART
uint32_t | RFLM
uint32_t | TXFP

Detailed Description

CAN init structure definition.

Definition at line 81 of file stm32f7xx_hal_can.h.

Field Documentation

uint32_t CAN_InitTypeDef::ABOM

Enable or disable the automatic bus-off management. This parameter can be set to ENABLE or DISABLE

Definition at line 103 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::AWUM

Enable or disable the automatic wake-up mode. This parameter can be set to ENABLE or DISABLE

Definition at line 106 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS1

Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of CAN Time Quantum in bit segment 1

Definition at line 94 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS2

Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of CAN Time Quantum in bit segment 2

Definition at line 97 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Mode

Specifies the CAN operating mode. This parameter can be a value of CAN Operating Mode

Definition at line 86 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::NART

Enable or disable the non-automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 109 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Prescaler

Specifies the length of a time quantum. This parameter must be a number between Min_Data = 1 and Max_Data = 1024

Definition at line 83 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::RFLM

Enable or disable the receive FIFO Locked mode. This parameter can be set to ENABLE or DISABLE

Definition at line 112 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::SJW

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of CAN Synchronisation Jump Width

Definition at line 89 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TTCM

Enable or disable the time triggered communication mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 100 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TXFP

Enable or disable the transmit FIFO priority. This parameter can be set to ENABLE or DISABLE

Definition at line 115 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_can.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN_FilterConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_FilterConfTypeDef Struct Reference
CAN Exported Types

CAN filter configuration structure definition. More...

#include <stm32f7xx_hal_can.h>

Data Fields

uint32_t | FilterIdHigh
uint32_t | FilterIdLow
uint32_t | FilterMaskIdHigh
uint32_t | FilterMaskIdLow
uint32_t | FilterFIFOAssignment
uint32_t | FilterNumber
uint32_t | FilterMode
uint32_t | FilterScale
uint32_t | FilterActivation
uint32_t | BankNumber

Detailed Description

CAN filter configuration structure definition.

Definition at line 122 of file stm32f7xx_hal_can.h.

Field Documentation

uint32_t CAN_FilterConfTypeDef::BankNumber

Select the start slave bank filter. This parameter must be a number between Min_Data = 0 and Max_Data = 28

Definition at line 157 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterActivation

Enable or disable the filter. This parameter can be set to ENABLE or DISABLE.

Definition at line 154 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterFIFOAssignment

Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of CAN Filter FIFO

Definition at line 142 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdHigh

Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 124 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdLow

Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 128 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdHigh

Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 132 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdLow

Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 137 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMode

Specifies the filter mode to be initialized. This parameter can be a value of CAN Filter Mode

Definition at line 148 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterNumber

Specifies the filter which will be initialized. This parameter must be a number between Min_Data = 0 and Max_Data = 27

Definition at line 145 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterScale

Specifies the filter scale. This parameter can be a value of CAN Filter Scale

Definition at line 151 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_can.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CanTxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanTxMsgTypeDef Struct Reference
CAN Exported Types

CAN Tx message structure definition. More...

#include <stm32f7xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]

Detailed Description

CAN Tx message structure definition.

Definition at line 165 of file stm32f7xx_hal_can.h.

Field Documentation

uint8_t CanTxMsgTypeDef::Data[8]

Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 182 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::DLC

Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8

Definition at line 179 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF

Definition at line 170 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of CAN Identifier Type

Definition at line 173 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::RTR

Specifies the type of frame for the message that will be transmitted. This parameter can be a value of CAN Remote Transmission Request

Definition at line 176 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF

Definition at line 167 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_can.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CanRxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanRxMsgTypeDef Struct Reference
CAN Exported Types

CAN Rx message structure definition. More...

#include <stm32f7xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]
uint32_t | FMI
uint32_t | FIFONumber

Detailed Description

CAN Rx message structure definition.

Definition at line 190 of file stm32f7xx_hal_can.h.

Field Documentation

uint8_t CanRxMsgTypeDef::Data[8]

Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 207 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::DLC

Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8

Definition at line 204 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF

Definition at line 195 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::FIFONumber

Specifies the receive FIFO number. This parameter can be CAN_FIFO0 or CAN_FIFO1

Definition at line 213 of file stm32f7xx_hal_can.h.

uint32_t CanRxMsgTypeDef::FMI

Specifies the index of the filter the message stored in the mailbox passes through. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 210 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be received. This parameter can be a value of CAN Identifier Type

Definition at line 198 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::RTR

Specifies the type of frame for the received message. This parameter can be a value of CAN Remote Transmission Request

Definition at line 201 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF

Definition at line 192 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_can.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_HandleTypeDef Struct Reference
CAN Exported Types

CAN handle Structure definition. More...

#include <stm32f7xx_hal_can.h>

Data Fields

CAN_TypeDef * | Instance
CAN_InitTypeDef Init
CanTxMsgTypeDef * pTxMsg
CanRxMsgTypeDef * pRxMsg
__IO HAL_CAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

CAN handle Structure definition.

Definition at line 221 of file stm32f7xx_hal_can.h.

Field Documentation

__IO uint32_t CAN_HandleTypeDef::ErrorCode

CAN Error code

Definition at line 235 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_GetError(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

CAN_InitTypeDef CAN_HandleTypeDef::Init

CAN required parameters

Definition at line 225 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

CAN_TypeDef* CAN_HandleTypeDef::Instance

Register base address

Definition at line 223 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

HAL_LockTypeDef CAN_HandleTypeDef::Lock

CAN locking object

Definition at line 233 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

CanRxMsgTypeDef* CAN_HandleTypeDef::pRxMsg

Pointer to reception structure

Definition at line 229 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

CanTxMsgTypeDef* CAN_HandleTypeDef::pTxMsg

Pointer to transmit structure

Definition at line 227 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

__IO HAL_CAN_StateTypeDef CAN_HandleTypeDef::State

CAN communication state

Definition at line 231 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_DeInit(), HAL_CAN_GetState(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_can.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL CAN Error Code

Defines
HAL CAN Error Code
CAN Exported Constants

Defines

#define | HAL_CAN_ERROR_NONE 0x00
#define | HAL_CAN_ERROR_EWG 0x01
#define | HAL_CAN_ERROR_EPV 0x02
#define | HAL_CAN_ERROR_BOF 0x04
#define | HAL_CAN_ERROR_STF 0x08
#define | HAL_CAN_ERROR_FOR 0x10
#define | HAL_CAN_ERROR_ACK 0x20
#define | HAL_CAN_ERROR_BR 0x40
#define | HAL_CAN_ERROR_BD 0x80
#define | HAL_CAN_ERROR_CRC 0x100

Define Documentation

#define HAL_CAN_ERROR_ACK 0x20

Acknowledgment error

Definition at line 257 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BD 0x80

LEC dominant

Definition at line 259 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BOF 0x04

BOF error

Definition at line 254 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BR 0x40

Bit recessive

Definition at line 258 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_CRC 0x100

LEC transfer error

Definition at line 260 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EPV 0x02

EPV error

Definition at line 253 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EWG 0x01

EWG error

Definition at line 252 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOR 0x10

Form error

Definition at line 256 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_NONE 0x00

No error

Definition at line 251 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define HAL_CAN_ERROR_STF 0x08

Stuff error

Definition at line 255 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

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STM32F745xx HAL User Manual: CAN InitStatus

Defines
CAN InitStatus
CAN Exported Constants

Defines

#define | CAN_INITSTATUS_FAILED ((uint8_t)0x00)
#define | CAN_INITSTATUS_SUCCESS ((uint8_t)0x01)

Define Documentation

#define CAN_INITSTATUS_FAILED ((uint8_t)0x00)

CAN initialization failed

Definition at line 268 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01)

CAN initialization OK

Definition at line 269 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

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STM32F745xx HAL User Manual: CAN Operating Mode

Defines
CAN Operating Mode
CAN Exported Constants

Defines

#define | CAN_MODE_NORMAL ((uint32_t)0x00000000)
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Define Documentation

#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)

Loopback mode

Definition at line 278 of file stm32f7xx_hal_can.h.

#define CAN_MODE_NORMAL ((uint32_t)0x00000000)

Normal mode

Definition at line 277 of file stm32f7xx_hal_can.h.

#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)

Silent mode

Definition at line 279 of file stm32f7xx_hal_can.h.

#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Loopback combined with silent mode

Definition at line 280 of file stm32f7xx_hal_can.h.

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STM32F745xx HAL User Manual: CAN Synchronisation Jump Width

Defines
CAN Synchronisation Jump Width
CAN Exported Constants

Defines

#define | CAN_SJW_1TQ ((uint32_t)0x00000000)
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

Define Documentation

#define CAN_SJW_1TQ ((uint32_t)0x00000000)

1 time quantum

Definition at line 288 of file stm32f7xx_hal_can.h.

#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)

2 time quantum

Definition at line 289 of file stm32f7xx_hal_can.h.

#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)

3 time quantum

Definition at line 290 of file stm32f7xx_hal_can.h.

#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

4 time quantum

Definition at line 291 of file stm32f7xx_hal_can.h.

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STM32F745xx HAL User Manual: CAN Time Quantum in bit segment 1

Defines
CAN Time Quantum in bit segment 1
CAN Exported Constants

Defines

#define | CAN_BS1_1TQ ((uint32_t)0x00000000)
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

Define Documentation

#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))

10 time quantum

Definition at line 308 of file stm32f7xx_hal_can.h.

#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))

11 time quantum

Definition at line 309 of file stm32f7xx_hal_can.h.

#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

12 time quantum

Definition at line 310 of file stm32f7xx_hal_can.h.

#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))

13 time quantum

Definition at line 311 of file stm32f7xx_hal_can.h.

#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

14 time quantum

Definition at line 312 of file stm32f7xx_hal_can.h.

#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

15 time quantum

Definition at line 313 of file stm32f7xx_hal_can.h.

#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

16 time quantum

Definition at line 314 of file stm32f7xx_hal_can.h.

#define CAN_BS1_1TQ ((uint32_t)0x00000000)

1 time quantum

Definition at line 299 of file stm32f7xx_hal_can.h.

#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)

2 time quantum

Definition at line 300 of file stm32f7xx_hal_can.h.

#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)

3 time quantum

Definition at line 301 of file stm32f7xx_hal_can.h.

#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

4 time quantum

Definition at line 302 of file stm32f7xx_hal_can.h.

#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)

5 time quantum

Definition at line 303 of file stm32f7xx_hal_can.h.

#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

6 time quantum

Definition at line 304 of file stm32f7xx_hal_can.h.

#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

7 time quantum

Definition at line 305 of file stm32f7xx_hal_can.h.

#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

8 time quantum

Definition at line 306 of file stm32f7xx_hal_can.h.

#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)

9 time quantum

Definition at line 307 of file stm32f7xx_hal_can.h.

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STM32F745xx HAL User Manual: CAN Time Quantum in bit segment 2

Defines
CAN Time Quantum in bit segment 2
CAN Exported Constants

Defines

#define | CAN_BS2_1TQ ((uint32_t)0x00000000)
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

Define Documentation

#define CAN_BS2_1TQ ((uint32_t)0x00000000)

1 time quantum

Definition at line 322 of file stm32f7xx_hal_can.h.

#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)

2 time quantum

Definition at line 323 of file stm32f7xx_hal_can.h.

#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)

3 time quantum

Definition at line 324 of file stm32f7xx_hal_can.h.

#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))

4 time quantum

Definition at line 325 of file stm32f7xx_hal_can.h.

#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)

5 time quantum

Definition at line 326 of file stm32f7xx_hal_can.h.

#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))

6 time quantum

Definition at line 327 of file stm32f7xx_hal_can.h.

#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))

7 time quantum

Definition at line 328 of file stm32f7xx_hal_can.h.

#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

8 time quantum

Definition at line 329 of file stm32f7xx_hal_can.h.

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STM32F745xx HAL User Manual: CAN Filter Mode

Defines
CAN Filter Mode
CAN Exported Constants

Defines

#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01)

Define Documentation

#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01)

Identifier list mode

Definition at line 338 of file stm32f7xx_hal_can.h.

#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00)

Identifier mask mode

Definition at line 337 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

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STM32F745xx HAL User Manual: CAN Filter Scale

Defines
CAN Filter Scale
CAN Exported Constants

Defines

#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01)

Define Documentation

#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00)

Two 16-bit filters

Definition at line 346 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01)

One 32-bit filter

Definition at line 347 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

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STM32F745xx HAL User Manual: CAN Filter FIFO

Defines
CAN Filter FIFO
CAN Exported Constants

Defines

#define | CAN_FILTER_FIFO0 ((uint8_t)0x00)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01)

Define Documentation

#define CAN_FILTER_FIFO0 ((uint8_t)0x00)

Filter FIFO 0 assignment for filter x

Definition at line 355 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTER_FIFO1 ((uint8_t)0x01)

Filter FIFO 1 assignment for filter x

Definition at line 356 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

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STM32F745xx HAL User Manual: CAN Identifier Type

Defines
CAN Identifier Type
CAN Exported Constants

Defines

#define | CAN_ID_STD ((uint32_t)0x00000000)
#define | CAN_ID_EXT ((uint32_t)0x00000004)

Define Documentation

#define CAN_ID_EXT ((uint32_t)0x00000004)

Extended Id

Definition at line 365 of file stm32f7xx_hal_can.h.

#define CAN_ID_STD ((uint32_t)0x00000000)

Standard Id

Definition at line 364 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_Receive(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

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STM32F745xx HAL User Manual: CAN Remote Transmission Request

Defines
CAN Remote Transmission Request
CAN Exported Constants

Defines

#define | CAN_RTR_DATA ((uint32_t)0x00000000)
#define | CAN_RTR_REMOTE ((uint32_t)0x00000002)

Define Documentation

#define CAN_RTR_DATA ((uint32_t)0x00000000)

Data frame

Definition at line 373 of file stm32f7xx_hal_can.h.

#define CAN_RTR_REMOTE ((uint32_t)0x00000002)

Remote frame

Definition at line 374 of file stm32f7xx_hal_can.h.

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STM32F745xx HAL User Manual: CAN Receive FIFO Number Constants

Defines
CAN Receive FIFO Number Constants
CAN Exported Constants

Defines

#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)

Define Documentation

#define CAN_FIFO0 ((uint8_t)0x00)

CAN FIFO 0 used to receive

Definition at line 382 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define CAN_FIFO1 ((uint8_t)0x01)

CAN FIFO 1 used to receive

Definition at line 383 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Flags

Defines
CAN Flags
CAN Exported Constants

Defines

#define | CAN_FLAG_RQCP0 ((uint32_t)0x00000500)
#define | CAN_FLAG_RQCP1 ((uint32_t)0x00000508)
#define | CAN_FLAG_RQCP2 ((uint32_t)0x00000510)
#define | CAN_FLAG_TXOK0 ((uint32_t)0x00000501)
#define | CAN_FLAG_TXOK1 ((uint32_t)0x00000509)
#define | CAN_FLAG_TXOK2 ((uint32_t)0x00000511)
#define | CAN_FLAG_TME0 ((uint32_t)0x0000051A)
#define | CAN_FLAG_TME1 ((uint32_t)0x0000051B)
#define | CAN_FLAG_TME2 ((uint32_t)0x0000051C)
#define | CAN_FLAG_FF0 ((uint32_t)0x00000203)
#define | CAN_FLAG_FOV0 ((uint32_t)0x00000204)
#define | CAN_FLAG_FF1 ((uint32_t)0x00000403)
#define | CAN_FLAG_FOV1 ((uint32_t)0x00000404)
#define | CAN_FLAG_WKU ((uint32_t)0x00000103)
#define | CAN_FLAG_SLAK ((uint32_t)0x00000101)
#define | CAN_FLAG_SLAKI ((uint32_t)0x00000104)
#define | CAN_FLAG_EWG ((uint32_t)0x00000300)
#define | CAN_FLAG_EPV ((uint32_t)0x00000301)
#define | CAN_FLAG_BOF ((uint32_t)0x00000302)

Define Documentation

#define CAN_FLAG_BOF ((uint32_t)0x00000302)

Bus-Off flag

Definition at line 424 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EPV ((uint32_t)0x00000301)

Error passive flag

Definition at line 423 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EWG ((uint32_t)0x00000300)

Error warning flag

Definition at line 422 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_FF0 ((uint32_t)0x00000203)

FIFO 0 Full flag

Definition at line 408 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_FF1 ((uint32_t)0x00000403)

FIFO 1 Full flag

Definition at line 411 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_FOV0 ((uint32_t)0x00000204)

FIFO 0 Overrun flag

Definition at line 409 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_FOV1 ((uint32_t)0x00000404)

FIFO 1 Overrun flag

Definition at line 412 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500)

Request MailBox0 flag

Definition at line 397 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508)

Request MailBox1 flag

Definition at line 398 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510)

Request MailBox2 flag

Definition at line 399 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_SLAK ((uint32_t)0x00000101)

Sleep acknowledge flag

Definition at line 416 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_SLAKI ((uint32_t)0x00000104)

Sleep acknowledge flag

Definition at line 417 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_TME0 ((uint32_t)0x0000051A)

Transmit mailbox 0 empty flag

Definition at line 403 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_TME1 ((uint32_t)0x0000051B)

Transmit mailbox 0 empty flag

Definition at line 404 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_TME2 ((uint32_t)0x0000051C)

Transmit mailbox 0 empty flag

Definition at line 405 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501)

Transmission OK MailBox0 flag

Definition at line 400 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509)

Transmission OK MailBox1 flag

Definition at line 401 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511)

Transmission OK MailBox2 flag

Definition at line 402 of file stm32f7xx_hal_can.h.

#define CAN_FLAG_WKU ((uint32_t)0x00000103)

Wake up flag

Definition at line 415 of file stm32f7xx_hal_can.h.

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STM32F745xx HAL User Manual: CAN Interrupts

Defines
CAN Interrupts
CAN Exported Constants

Defines

#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Define Documentation

#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)

Bus-off interrupt

Definition at line 449 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)

Error passive interrupt

Definition at line 448 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Error Interrupt

Definition at line 451 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)

Error warning interrupt

Definition at line 447 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)

FIFO 0 full interrupt

Definition at line 436 of file stm32f7xx_hal_can.h.

#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)

FIFO 1 full interrupt

Definition at line 439 of file stm32f7xx_hal_can.h.

#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)

FIFO 0 message pending interrupt

Definition at line 435 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)

FIFO 1 message pending interrupt

Definition at line 438 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)

FIFO 0 overrun interrupt

Definition at line 437 of file stm32f7xx_hal_can.h.

#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)

FIFO 1 overrun interrupt

Definition at line 440 of file stm32f7xx_hal_can.h.

#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)

Last error code interrupt

Definition at line 450 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)

Sleep acknowledge interrupt

Definition at line 444 of file stm32f7xx_hal_can.h.

#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)

Transmit mailbox empty interrupt

Definition at line 432 of file stm32f7xx_hal_can.h.

Referenced by CAN_Transmit_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Transmit_IT().

#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)

Wake-up interrupt

Definition at line 443 of file stm32f7xx_hal_can.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Mailboxes Definition

Defines
CAN Mailboxes Definition
CAN Exported Constants

Defines

#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)

Define Documentation

#define CAN_TXMAILBOX_0 ((uint8_t)0x00)

Definition at line 459 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_TXMAILBOX_1 ((uint8_t)0x01)

Definition at line 460 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_TXMAILBOX_2 ((uint8_t)0x02)

Definition at line 461 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Exported Macros

Defines
CAN Exported Macros
CAN

Defines

#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupts.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupts.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified CAN interrupt source is enabled or disabled.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disable the DBG Freeze for CAN.

Define Documentation

#define __HAL_CAN_CANCEL_TRANSMIT | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))

Cancel a transmit request.

Parameters:
__HANDLE__,: CAN Handle
__TRANSMITMAILBOX__,: the number of the mailbox that is used for transmission.
Return values:
None

Definition at line 611 of file stm32f7xx_hal_can.h.

#define __HAL_CAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))

Clear the specified CAN pending flag.

Parameters:
__HANDLE__,: CAN Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
  • CAN_FLAG_EWG: Error Warning Flag
  • CAN_FLAG_EPV: Error Passive Flag
  • CAN_FLAG_BOF: Bus-Off Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 567 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_DBG_FREEZE | ( | __HANDLE__,
 |  | __NEWSTATE__
 | ) |
Value:
(((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))

Enable or disable the DBG Freeze for CAN.

Parameters:
__HANDLE__,: CAN Handle
__NEWSTATE__,: new state of the CAN peripheral. This parameter can be: ENABLE (CAN reception/transmission is frozen during debug. Reception FIFOs can still be accessed/controlled normally) or DISABLE (CAN is working during debug).
Return values:
None

Definition at line 625 of file stm32f7xx_hal_can.h.

#define __HAL_CAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable the specified CAN interrupts.

Parameters:
__HANDLE__,: CAN handle
__INTERRUPT__,: CAN Interrupt
Return values:
None

Definition at line 495 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and CAN_Transmit_IT().

#define __HAL_CAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable the specified CAN interrupts.

Parameters:
__HANDLE__,: CAN handle
__INTERRUPT__,: CAN Interrupt
Return values:
None

Definition at line 487 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define __HAL_CAN_FIFO_RELEASE | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))

Release the specified receive FIFO.

Parameters:
__HANDLE__,: CAN handle
__FIFONUMBER__,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
None

Definition at line 602 of file stm32f7xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

#define __HAL_CAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))

Check whether the specified CAN flag is set or not.

Parameters:
__HANDLE__,: CAN Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
  • CAN_FLAG_EWG: Error Warning Flag
  • CAN_FLAG_EPV: Error Passive Flag
  • CAN_FLAG_BOF: Bus-Off Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 533 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check if the specified CAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: CAN Handle
__INTERRUPT__,: specifies the CAN interrupt source to check. This parameter can be one of the following values:
  • CAN_IT_TME: Transmit mailbox empty interrupt enable
  • CAN_IT_FMP0: FIFO0 message pending interrupt enable
  • CAN_IT_FMP1: FIFO1 message pending interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 583 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_MSG_PENDING | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))

Return the number of pending received messages.

Parameters:
__HANDLE__,: CAN handle
__FIFONUMBER__,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
The number of pending message.

Definition at line 503 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

#define __HAL_CAN_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)

Reset CAN handle state.

Parameters:
__HANDLE__,: specifies the CAN Handle.
Return values:
None

Definition at line 479 of file stm32f7xx_hal_can.h.

#define __HAL_CAN_TRANSMIT_STATUS | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))

Check the transmission status of a CAN Frame.

Parameters:
__HANDLE__,: CAN Handle
__TRANSMITMAILBOX__,: the number of the mailbox that is used for transmission.
Return values:
The new status of transmission (TRUE or FALSE).

Definition at line 591 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Transmit().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Private Types

CAN Private Types
CAN
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Private Variables

CAN Private Variables
CAN
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Private Constants

Defines
CAN Private Constants
CAN

Defines

#define | CAN_TIMEOUT_VALUE 10
#define | CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)
#define | CAN_FLAG_MASK ((uint32_t)0x000000FF)

Define Documentation

#define CAN_FLAG_MASK ((uint32_t)0x000000FF)

Definition at line 705 of file stm32f7xx_hal_can.h.

#define CAN_TIMEOUT_VALUE 10

Definition at line 123 of file stm32f7xx_hal_can.c.

Referenced by HAL_CAN_Init(), HAL_CAN_Sleep(), and HAL_CAN_WakeUp().

#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)

CAN cell did not provide CAN_TxStatus_NoMailBox

Definition at line 704 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Private Macros

Defines
CAN Private Macros
CAN

Defines

#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define | IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Define Documentation

#define IS_CAN_BANKNUMBER ( BANKNUMBER ) ((BANKNUMBER) <= 28)

Definition at line 730 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_BS1 ( BS1 ) ((BS1) <= CAN_BS1_16TQ)

Definition at line 720 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_BS2 ( BS2 ) ((BS2) <= CAN_BS2_8TQ)

Definition at line 721 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_DLC ( DLC ) ((DLC) <= ((uint8_t)0x08))

Definition at line 735 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_EXTID ( EXTID ) ((EXTID) <= ((uint32_t)0x1FFFFFFF))

Definition at line 734 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_FIFO ( FIFO ) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Definition at line 740 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define IS_CAN_FILTER_FIFO ( FIFO )
Value:
(((FIFO) == CAN_FILTER_FIFO0) || \
                                  ((FIFO) == CAN_FILTER_FIFO1))

Definition at line 728 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_MODE ( MODE )
Value:
(((MODE) == CAN_FILTERMODE_IDMASK) || \
                                  ((MODE) == CAN_FILTERMODE_IDLIST))

Definition at line 724 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_NUMBER ( NUMBER ) ((NUMBER) <= 27)

Definition at line 723 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_SCALE ( SCALE )
Value:
(((SCALE) == CAN_FILTERSCALE_16BIT) || \
                                    ((SCALE) == CAN_FILTERSCALE_32BIT))

Definition at line 726 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_IDTYPE ( IDTYPE )
Value:
(((IDTYPE) == CAN_ID_STD) || \
                                ((IDTYPE) == CAN_ID_EXT))

Definition at line 737 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_MODE ( MODE )
Value:
(((MODE) == CAN_MODE_NORMAL) || \
                           ((MODE) == CAN_MODE_LOOPBACK)|| \
                           ((MODE) == CAN_MODE_SILENT) || \
                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))

Definition at line 714 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))

Definition at line 722 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_RTR ( RTR ) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))

Definition at line 739 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_SJW ( SJW )
Value:
(((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))

Definition at line 718 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_STDID ( STDID ) ((STDID) <= ((uint32_t)0x7FF))

Definition at line 733 of file stm32f7xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_TRANSMITMAILBOX ( TRANSMITMAILBOX ) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))

Definition at line 732 of file stm32f7xx_hal_can.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CAN Private Functions

CAN Private Functions
CAN
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Private Constants

Defines
CEC Private Constants
CEC

Defines

#define CEC_CFGR_FIELDS

Define Documentation

#define CEC_CFGR_FIELDS
Value:
(CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
                           | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
                           | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)

Definition at line 97 of file stm32f7xx_hal_cec.c.

Referenced by HAL_CEC_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Private Functions

CEC Private Functions
CEC
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CEC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the CEC
      (+) The following parameters need to be configured:
        (++) SignalFreeTime
        (++) Tolerance
        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
        (++) SignalFreeTimeOption      (SFT Timer start definition)
        (++) OwnAddress                (CEC device address)
        (++) ListenMode

Function Documentation

HAL_StatusTypeDef HAL_CEC_DeInit ( CEC_HandleTypeDef * hcec )

DeInitializes the CEC peripheral.

Parameters:
hcec,: CEC handle
Return values:
HAL status

Definition at line 215 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_DISABLE, assert_param, CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_NONE, HAL_CEC_MspDeInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_RESET, CEC_HandleTypeDef::Instance, and CEC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CEC_Init ( CEC_HandleTypeDef * hcec )

Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .

Parameters:
hcec,: CEC handle
Return values:
HAL status

Definition at line 152 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, assert_param, CEC_InitTypeDef::BREErrorBitGen, CEC_InitTypeDef::BRERxStop, CEC_InitTypeDef::BroadcastMsgNoErrorBitGen, CEC_CFGR_FIELDS, CEC_CFGR_OAR_LSB_POS, HAL_CEC_MspInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, CEC_HandleTypeDef::Init, CEC_InitTypeDef::InitiatorAddress, CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_BREERRORBITGEN, IS_CEC_BRERXSTOP, IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION, IS_CEC_LBPEERRORBITGEN, IS_CEC_LISTENING_MODE, IS_CEC_OAR_ADDRESS, IS_CEC_SFTOP, IS_CEC_SIGNALFREETIME, IS_CEC_TOLERANCE, CEC_InitTypeDef::LBPEErrorBitGen, CEC_InitTypeDef::ListenMode, CEC_HandleTypeDef::Lock, CEC_InitTypeDef::OwnAddress, CEC_InitTypeDef::SignalFreeTime, CEC_InitTypeDef::SignalFreeTimeOption, CEC_HandleTypeDef::State, and CEC_InitTypeDef::Tolerance.

void HAL_CEC_MspDeInit ( CEC_HandleTypeDef * hcec )

CEC MSP DeInit.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 261 of file stm32f7xx_hal_cec.c.

Referenced by HAL_CEC_DeInit().

void HAL_CEC_MspInit ( CEC_HandleTypeDef * hcec )

CEC MSP Init.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 247 of file stm32f7xx_hal_cec.c.

Referenced by HAL_CEC_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CEC Exported Functions

CEC Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Transmit (CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Send data in blocking mode.
HAL_StatusTypeDef | HAL_CEC_Receive (CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
Receive data in blocking mode.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
HAL_StatusTypeDef | HAL_CEC_Receive_IT (CEC_HandleTypeDef *hcec, uint8_t *pData)
Receive data in interrupt mode.
uint32_t | HAL_CEC_GetReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.

Detailed Description

CEC Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the CEC data transfers.

    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (+) No-Blocking mode: The communication is performed using Interrupts.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated CEC IRQ when using Interrupt mode.
           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_CEC_ErrorCallback()user callback will be executed when a communication
           error is detected

    (#) Blocking mode API's are :
        (+) HAL_CEC_Transmit()
        (+) HAL_CEC_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_CEC_Transmit_IT()
        (+) HAL_CEC_Receive_IT()
        (+) HAL_CEC_IRQHandler()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (+) HAL_CEC_TxCpltCallback()
        (+) HAL_CEC_RxCpltCallback()
        (+) HAL_CEC_ErrorCallback()

Function Documentation

void HAL_CEC_ErrorCallback ( CEC_HandleTypeDef * hcec )

CEC error callbacks.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 910 of file stm32f7xx_hal_cec.c.

Referenced by HAL_CEC_IRQHandler().

uint32_t HAL_CEC_GetReceivedFrameSize ( CEC_HandleTypeDef * hcec )

Get size of the received frame.

Parameters:
hcec,: CEC handle
Return values:
Frame size

Definition at line 765 of file stm32f7xx_hal_cec.c.

References CEC_HandleTypeDef::RxXferSize.

void HAL_CEC_IRQHandler ( CEC_HandleTypeDef * hcec )

This function handles CEC interrupt requests.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 775 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_GET_FLAG, __HAL_CEC_GET_IT_SOURCE, CEC_FLAG_ARBLST, CEC_FLAG_BRE, CEC_FLAG_LBPE, CEC_FLAG_RXACKE, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_RXOVR, CEC_FLAG_SBPE, CEC_FLAG_TXACKE, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_FLAG_TXERR, CEC_FLAG_TXUDR, CEC_ISR_ALL_ERROR, CEC_IT_ARBLST, CEC_IT_BRE, CEC_IT_LBPE, CEC_IT_RXACKE, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_RXOVR, CEC_IT_SBPE, CEC_IT_TXACKE, CEC_IT_TXBR, CEC_IT_TXEND, CEC_IT_TXERR, CEC_IT_TXUDR, CEC_Receive_IT(), CEC_Transmit_IT(), CEC_HandleTypeDef::ErrorCode, HAL_CEC_ErrorCallback(), HAL_CEC_STATE_ERROR, CEC_HandleTypeDef::Instance, and CEC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CEC_Receive | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive data in blocking mode.

Must be invoked when RXBR has been set.

Parameters:
hcec,: CEC handle
pData,: pointer to received data buffer.
Timeout,: Timeout duration. Note that the received data size is not known beforehand, the latter is known when the reception is complete and is stored in hcec->RxXferSize. hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). If only a header is received, hcec->RxXferSize = 0
Return values:
HAL status

Definition at line 477 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, assert_param, CEC_FLAG_BRE, CEC_FLAG_LBPE, CEC_FLAG_RXACKE, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_RXOVR, CEC_FLAG_SBPE, CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_ERROR, HAL_CEC_STATE_READY, HAL_CEC_STATE_TIMEOUT, HAL_GetTick(), CEC_HandleTypeDef::Instance, IS_CEC_MSGSIZE, CEC_HandleTypeDef::RxXferSize, and CEC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CEC_Receive_IT | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t * | pData
 | ) |  |

Receive data in interrupt mode.

Parameters:
hcec,: CEC handle
pData,: pointer to received data buffer. Note that the received data size is not known beforehand, the latter is known when the reception is complete and is stored in hcec->RxXferSize. hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). If only a header is received, hcec->RxXferSize = 0
Return values:
HAL status

Definition at line 713 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, __HAL_CEC_ENABLE_IT, CEC_IER_RX_ALL_ERR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_ERROR, HAL_CEC_STATE_READY, HAL_CEC_STATE_STANDBY_RX, CEC_HandleTypeDef::pRxBuffPtr, CEC_HandleTypeDef::RxXferSize, and CEC_HandleTypeDef::State.

void HAL_CEC_RxCpltCallback ( CEC_HandleTypeDef * hcec )

Rx Transfer completed callback.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 896 of file stm32f7xx_hal_cec.c.

Referenced by CEC_Receive_IT().

HAL_StatusTypeDef HAL_CEC_Transmit | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t | DestinationAddress,
 |  | uint8_t * | pData,
 |  | uint32_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send data in blocking mode.

Parameters:
hcec,: CEC handle
DestinationAddress,: destination logical address
pData,: pointer to input byte data buffer
Size,: amount of data to be sent in bytes (without counting the header). 0 means only the header is sent (ping operation). Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 328 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_FIRST_BYTE_TX_SET, __HAL_CEC_GET_TRANSMISSION_START_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, assert_param, CEC_FLAG_ARBLST, CEC_FLAG_TXACKE, CEC_FLAG_TXBR, CEC_FLAG_TXERR, CEC_FLAG_TXUDR, CEC_INITIATOR_LSB_POS, CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_ERROR, HAL_CEC_STATE_READY, HAL_CEC_STATE_TIMEOUT, HAL_GetTick(), CEC_HandleTypeDef::Init, CEC_InitTypeDef::InitiatorAddress, CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_MSGSIZE, CEC_HandleTypeDef::State, and CEC_HandleTypeDef::TxXferCount.

HAL_StatusTypeDef HAL_CEC_Transmit_IT | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t | DestinationAddress,
 |  | uint8_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Send data in interrupt mode.

Parameters:
hcec,: CEC handle
DestinationAddress,: destination logical address
pData,: pointer to input byte data buffer
Size,: amount of data to be sent in bytes (without counting the header). 0 means only the header is sent (ping operation). Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
Return values:
HAL status

Definition at line 580 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_DISABLE, __HAL_CEC_DISABLE_IT, __HAL_CEC_ENABLE, __HAL_CEC_ENABLE_IT, __HAL_CEC_FIRST_BYTE_TX_SET, __HAL_CEC_GET_TRANSMISSION_START_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, assert_param, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_IER_TX_ALL_ERR, CEC_INITIATOR_LSB_POS, CEC_IT_TXBR, CEC_IT_TXEND, CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_ERROR, HAL_CEC_STATE_READY, HAL_CEC_STATE_STANDBY_RX, HAL_CEC_TxCpltCallback(), CEC_HandleTypeDef::Init, CEC_InitTypeDef::InitiatorAddress, CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_MSGSIZE, CEC_HandleTypeDef::pTxBuffPtr, CEC_HandleTypeDef::State, and CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_TxCpltCallback ( CEC_HandleTypeDef * hcec )

Tx Transfer completed callback.

Parameters:
hcec,: CEC handle
Return values:
None

Definition at line 882 of file stm32f7xx_hal_cec.c.

Referenced by CEC_Transmit_IT(), and HAL_CEC_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control function

Functions
Peripheral Control function
CEC Exported Functions

CEC control functions. More...

Functions

HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC control functions.

 ===============================================================================
                      ##### Peripheral Control function #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the CEC.
     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.

Function Documentation

uint32_t HAL_CEC_GetError ( CEC_HandleTypeDef * hcec )

Return the CEC error code.

Parameters:
hcec : pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC.
Return values:
CEC Error Code

Definition at line 951 of file stm32f7xx_hal_cec.c.

References CEC_HandleTypeDef::ErrorCode.

HAL_CEC_StateTypeDef HAL_CEC_GetState ( CEC_HandleTypeDef * hcec )

return the CEC state

Parameters:
hcec,: CEC handle
Return values:
HAL state

Definition at line 940 of file stm32f7xx_hal_cec.c.

References CEC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Exported Functions

Modules | Functions
CEC Exported Functions
CEC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

CEC Transmit/Receive functions.

Peripheral Control function

CEC control functions.

Functions

static HAL_StatusTypeDef | CEC_Transmit_IT (CEC_HandleTypeDef *hcec)
Send data in interrupt mode.
static HAL_StatusTypeDef | CEC_Receive_IT (CEC_HandleTypeDef *hcec)
Receive data in interrupt mode.

Function Documentation

static HAL_StatusTypeDef CEC_Receive_IT ( CEC_HandleTypeDef * hcec ) [static]

Receive data in interrupt mode.

Parameters:
hcec,: CEC handle. Function called under interruption only, once interruptions have been enabled by HAL_CEC_Receive_IT()
Return values:
HAL status

Definition at line 1039 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, CEC_FLAG_RXBR, CEC_FLAG_RXEND, HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY_RX, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_READY, HAL_CEC_STATE_STANDBY_RX, CEC_HandleTypeDef::Instance, CEC_HandleTypeDef::pRxBuffPtr, CEC_HandleTypeDef::RxXferSize, and CEC_HandleTypeDef::State.

Referenced by HAL_CEC_IRQHandler().

static HAL_StatusTypeDef CEC_Transmit_IT ( CEC_HandleTypeDef * hcec ) [static]

Send data in interrupt mode.

Parameters:
hcec,: CEC handle. Function called under interruption only, once interruptions have been enabled by HAL_CEC_Transmit_IT()
Return values:
HAL status

Definition at line 967 of file stm32f7xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_DISABLE, __HAL_CEC_DISABLE_IT, __HAL_CEC_ENABLE, __HAL_CEC_GET_TRANSMISSION_START_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_IER_TX_ALL_ERR, CEC_IT_TXBR, CEC_IT_TXEND, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_READY, HAL_CEC_TxCpltCallback(), CEC_HandleTypeDef::Instance, CEC_HandleTypeDef::pTxBuffPtr, CEC_HandleTypeDef::State, and CEC_HandleTypeDef::TxXferCount.

Referenced by HAL_CEC_IRQHandler().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Exported Types

Data Structures | Enumerations
CEC Exported Types
CEC

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | CEC_HandleTypeDef
CEC handle Structure definition. More...

Enumerations

enum HAL_CEC_StateTypeDef {
HAL_CEC_STATE_RESET = 0x00, HAL_CEC_STATE_READY = 0x01, HAL_CEC_STATE_BUSY = 0x02, HAL_CEC_STATE_BUSY_TX = 0x03,
HAL_CEC_STATE_BUSY_RX = 0x04, HAL_CEC_STATE_STANDBY_RX = 0x05, HAL_CEC_STATE_TIMEOUT = 0x06, HAL_CEC_STATE_ERROR = 0x07
}
HAL CEC State structures definition. More...

Enumeration Type Documentation

enum HAL_CEC_StateTypeDef

HAL CEC State structures definition.

Enumerator:
HAL_CEC_STATE_RESET

Peripheral Reset state

HAL_CEC_STATE_READY

Peripheral Initialized and ready for use

HAL_CEC_STATE_BUSY

an internal process is ongoing

HAL_CEC_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_CEC_STATE_BUSY_RX

Data Reception process is ongoing

HAL_CEC_STATE_STANDBY_RX

IP ready to receive, doesn't prevent IP to transmit

HAL_CEC_STATE_TIMEOUT

Timeout state

HAL_CEC_STATE_ERROR

State Error

Definition at line 130 of file stm32f7xx_hal_cec.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_InitTypeDef Struct Reference
CEC Exported Types

CEC Init Structure definition. More...

#include <stm32f7xx_hal_cec.h>

Data Fields

uint32_t | SignalFreeTime
uint32_t | Tolerance
uint32_t | BRERxStop
uint32_t | BREErrorBitGen
uint32_t | LBPEErrorBitGen
uint32_t | BroadcastMsgNoErrorBitGen
uint32_t | SignalFreeTimeOption
uint32_t | OwnAddress
uint32_t | ListenMode
uint8_t | InitiatorAddress

Detailed Description

CEC Init Structure definition.

Definition at line 65 of file stm32f7xx_hal_cec.h.

Field Documentation

uint32_t CEC_InitTypeDef::BREErrorBitGen

Set BREGEN bit CEC Error Bit Generation if Bit Rise Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set.

Definition at line 81 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BRERxStop

Set BRESTP bit CEC Reception Stop on Error : specifies whether or not a Bit Rising Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped.

Definition at line 77 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BroadcastMsgNoErrorBitGen

Set BRDNOGEN bit CEC Error Bit Generation on Broadcast message : allows to avoid an Error-Bit generation on the CEC line upon an error detected on a broadcast message.

It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:

1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.

2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. no error-bit generation in case neither a) nor b) are satisfied. Additionally, there is no error-bit generation in case of Short Bit Period Error detection in a broadcast message while LSTN bit is set.

Definition at line 91 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t CEC_InitTypeDef::InitiatorAddress

Definition at line 123 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

uint32_t CEC_InitTypeDef::LBPEErrorBitGen

Set LBPEGEN bit CEC Error Bit Generation if Long Bit Period Error reported : specifies whether or not an Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation.

Definition at line 86 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::ListenMode

Set LSTN bit CEC Listening mode option : specifies device listening mode. It can take two values:

CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.

CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

Definition at line 113 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::OwnAddress

Set OAR field, specifies CEC device address within a 15-bit long field

Definition at line 111 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::SignalFreeTime

Set SFT field, specifies the Signal Free Time. It can be one of CEC Signal Free Time setting parameter and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods

Definition at line 67 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::SignalFreeTimeOption

Set SFTOP bit CEC Signal Free Time start option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception.

Definition at line 107 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::Tolerance

Set RXTOL bit, specifies the tolerance accepted on the received waveforms, it can be a value of CEC Receiver Tolerance : it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE

Definition at line 73 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_cec.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_HandleTypeDef Struct Reference
CEC Exported Types

CEC handle Structure definition. More...

#include <stm32f7xx_hal_cec.h>

Data Fields

CEC_TypeDef * | Instance
CEC_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint32_t | ErrorCode
HAL_LockTypeDef | Lock
HAL_CEC_StateTypeDef State

Detailed Description

CEC handle Structure definition.

Definition at line 145 of file stm32f7xx_hal_cec.h.

Field Documentation

uint32_t CEC_HandleTypeDef::ErrorCode

Definition at line 159 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetError(), HAL_CEC_IRQHandler(), HAL_CEC_Receive(), HAL_CEC_Receive_IT(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

CEC_InitTypeDef CEC_HandleTypeDef::Init

Definition at line 149 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

CEC_TypeDef* CEC_HandleTypeDef::Instance

Definition at line 147 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), CEC_Transmit_IT(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_Receive(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

HAL_LockTypeDef CEC_HandleTypeDef::Lock

Definition at line 162 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_HandleTypeDef::pRxBuffPtr

Definition at line 155 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), and HAL_CEC_Receive_IT().

uint8_t* CEC_HandleTypeDef::pTxBuffPtr

Definition at line 151 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), and HAL_CEC_Transmit_IT().

uint16_t CEC_HandleTypeDef::RxXferSize

Definition at line 157 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), HAL_CEC_GetReceivedFrameSize(), HAL_CEC_Receive(), and HAL_CEC_Receive_IT().

HAL_CEC_StateTypeDef CEC_HandleTypeDef::State

Definition at line 164 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), CEC_Transmit_IT(), HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_Receive(), HAL_CEC_Receive_IT(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

uint16_t CEC_HandleTypeDef::TxXferCount

Definition at line 153 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_cec.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Error Code

Defines
CEC Error Code
CEC Exported Constants

Defines

#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

Define Documentation

#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST

CEC Arbitration Lost

Definition at line 185 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_BRE CEC_ISR_BRE

CEC Rx Bit Rising Error

Definition at line 181 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE

CEC Rx Long Bit period Error

Definition at line 183 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_NONE (uint32_t) 0x0

no error

Definition at line 179 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Receive(), HAL_CEC_Receive_IT(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE

CEC Rx Missing Acknowledge

Definition at line 184 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR

CEC Rx-Overrun

Definition at line 180 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE

CEC Rx Short Bit period Error

Definition at line 182 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

CEC Tx Missing Acknowledge

Definition at line 188 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR

CEC Tx-Error

Definition at line 187 of file stm32f7xx_hal_cec.h.

#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR

CEC Tx-Buffer Underrun

Definition at line 186 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Signal Free Time setting parameter

Defines
CEC Signal Free Time setting parameter
CEC Exported Constants

Defines

#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)

Define Documentation

#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)

Definition at line 197 of file stm32f7xx_hal_cec.h.

#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)

Definition at line 198 of file stm32f7xx_hal_cec.h.

#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)

Definition at line 199 of file stm32f7xx_hal_cec.h.

#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)

Definition at line 200 of file stm32f7xx_hal_cec.h.

#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)

Definition at line 201 of file stm32f7xx_hal_cec.h.

#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)

Definition at line 202 of file stm32f7xx_hal_cec.h.

#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)

Definition at line 203 of file stm32f7xx_hal_cec.h.

#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)

Definition at line 196 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Receiver Tolerance

Defines
CEC Receiver Tolerance
CEC Exported Constants

Defines

#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Define Documentation

#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Definition at line 212 of file stm32f7xx_hal_cec.h.

#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)

Definition at line 211 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Reception Stop on Error

Defines
CEC Reception Stop on Error
CEC Exported Constants

Defines

#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Define Documentation

#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)

Definition at line 220 of file stm32f7xx_hal_cec.h.

#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Definition at line 221 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Error Bit Generation if Bit Rise Error reported

Defines
CEC Error Bit Generation if Bit Rise Error reported
CEC Exported Constants

Defines

#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Define Documentation

#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Definition at line 230 of file stm32f7xx_hal_cec.h.

#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)

Definition at line 229 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Error Bit Generation if Long Bit Period Error reported

Defines
CEC Error Bit Generation if Long Bit Period Error reported
CEC Exported Constants

Defines

#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Define Documentation

#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Definition at line 239 of file stm32f7xx_hal_cec.h.

#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)

Definition at line 238 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Error Bit Generation on Broadcast message

Defines
CEC Error Bit Generation on Broadcast message
CEC Exported Constants

Defines

#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Define Documentation

#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)

Definition at line 247 of file stm32f7xx_hal_cec.h.

#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Definition at line 248 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Signal Free Time start option

Defines
CEC Signal Free Time start option
CEC Exported Constants

Defines

#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Define Documentation

#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Definition at line 257 of file stm32f7xx_hal_cec.h.

#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)

Definition at line 256 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Listening mode option

Defines
CEC Listening mode option
CEC Exported Constants

Defines

#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Define Documentation

#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Definition at line 266 of file stm32f7xx_hal_cec.h.

#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)

Definition at line 265 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Device Own Address position in CEC CFGR register

Defines
CEC Device Own Address position in CEC CFGR register
CEC Exported Constants

Defines

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)

Define Documentation

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)

Definition at line 274 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

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STM32F745xx HAL User Manual: CEC Initiator logical address position in message header

Defines
CEC Initiator logical address position in message header
CEC Exported Constants

Defines

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)

Define Documentation

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)

Definition at line 282 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

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STM32F745xx HAL User Manual: CEC Interrupts definition

Defines
CEC Interrupts definition
CEC Exported Constants

Defines

#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE

Define Documentation

#define CEC_IT_ARBLST CEC_IER_ARBLSTIE

Definition at line 295 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_BRE CEC_IER_BREIE

Definition at line 299 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_LBPE CEC_IER_LBPEIE

Definition at line 297 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_RXACKE CEC_IER_RXACKEIE

Definition at line 296 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_RXBR CEC_IER_RXBRIE

Definition at line 302 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive_IT().

#define CEC_IT_RXEND CEC_IER_RXENDIE

Definition at line 301 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive_IT().

#define CEC_IT_RXOVR CEC_IER_RXOVRIE

Definition at line 300 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_SBPE CEC_IER_SBPEIE

Definition at line 298 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_TXACKE CEC_IER_TXACKEIE

Definition at line 290 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_TXBR CEC_IER_TXBRIE

Definition at line 294 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define CEC_IT_TXEND CEC_IER_TXENDIE

Definition at line 293 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define CEC_IT_TXERR CEC_IER_TXERRIE

Definition at line 291 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_IT_TXUDR CEC_IER_TXUDRIE

Definition at line 292 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

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STM32F745xx HAL User Manual: CEC Flags definition

Defines
CEC Flags definition
CEC Exported Constants

Defines

#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR

Define Documentation

#define CEC_FLAG_ARBLST CEC_ISR_ARBLST

Definition at line 315 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit().

#define CEC_FLAG_BRE CEC_ISR_BRE

Definition at line 319 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_LBPE CEC_ISR_LBPE

Definition at line 317 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_RXACKE CEC_ISR_RXACKE

Definition at line 316 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_RXBR CEC_ISR_RXBR

Definition at line 322 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_RXEND CEC_ISR_RXEND

Definition at line 321 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_RXOVR CEC_ISR_RXOVR

Definition at line 320 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_SBPE CEC_ISR_SBPE

Definition at line 318 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Receive().

#define CEC_FLAG_TXACKE CEC_ISR_TXACKE

Definition at line 310 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit().

#define CEC_FLAG_TXBR CEC_ISR_TXBR

Definition at line 314 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_IRQHandler(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define CEC_FLAG_TXEND CEC_ISR_TXEND

Definition at line 313 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define CEC_FLAG_TXERR CEC_ISR_TXERR

Definition at line 311 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit().

#define CEC_FLAG_TXUDR CEC_ISR_TXUDR

Definition at line 312 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit().

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STM32F745xx HAL User Manual: CEC all RX or TX errors flags

Defines
CEC all RX or TX errors flags
CEC Exported Constants

Defines

#define CEC_ISR_ALL_ERROR

Define Documentation

#define CEC_ISR_ALL_ERROR
Value:
((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
                                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)

Definition at line 330 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

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STM32F745xx HAL User Manual: CEC all RX errors interrupts enabling flag

Defines
CEC all RX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Define Documentation

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Definition at line 339 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Receive_IT().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC all TX errors interrupts enabling flag

Defines
CEC all TX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Define Documentation

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Definition at line 347 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), and HAL_CEC_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Exported Macros

Defines
CEC Exported Macros
CEC

Defines

#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
Reset CEC handle state.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Define Documentation

#define __HAL_CEC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR |= (__FLAG__))

Clears the interrupt or status flag when raised (write at 1)

Parameters:
__HANDLE__,: specifies the CEC Handle.
__FLAG__,: specifies the interrupt/status flag to clear. This parameter can be one of the following values:
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
none

Definition at line 406 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Receive_IT(), CEC_Transmit_IT(), HAL_CEC_IRQHandler(), HAL_CEC_Receive(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_CLEAR_OAR ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)

Clear OAR register.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 512 of file stm32f7xx_hal_cec.h.

#define __HAL_CEC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)

Disables the CEC device.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 481 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_Receive_IT(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disables the specified CEC interrupt.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__INTERRUPT__,: specifies the CEC interrupt to disable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 448 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)

Enables the CEC device.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 475 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_Init(), HAL_CEC_Receive_IT(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified CEC interrupt.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__INTERRUPT__,: specifies the CEC interrupt to enable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 427 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Receive_IT(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_FIRST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)

Set Transmission Start flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none

Definition at line 487 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Checks whether or not the specified CEC interrupt flag is set.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__FLAG__,: specifies the flag to check.
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
ITStatus

Definition at line 385 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define __HAL_CEC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Checks whether or not the specified CEC interrupt is enabled.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__INTERRUPT__,: specifies the CEC interrupt to check. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
FlagStatus

Definition at line 469 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define __HAL_CEC_GET_TRANSMISSION_END_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)

Get Transmission End flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 506 of file stm32f7xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_START_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)

Get Transmission Start flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 500 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_LAST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)

Set Transmission End flag.

Parameters:
__HANDLE__,: specifies the CEC Handle.
Return values:
none If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.

Definition at line 494 of file stm32f7xx_hal_cec.h.

Referenced by CEC_Transmit_IT(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)

Reset CEC handle state.

Parameters:
__HANDLE__,: CEC handle.
Return values:
None

Definition at line 365 of file stm32f7xx_hal_cec.h.

#define __HAL_CEC_SET_OAR | ( | __HANDLE__,
 |  | __ADDRESS__
 | ) | SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)

Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Parameters:
__HANDLE__,: specifies the CEC Handle.
__ADDRESS__,: Own Address value (CEC logical address is identified by bit position)
Return values:
none

Definition at line 520 of file stm32f7xx_hal_cec.h.

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STM32F745xx HAL User Manual: CEC Private Types

CEC Private Types
CEC
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Private Variables

CEC Private Variables
CEC
Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CEC Private Macros

Defines
CEC Private Macros
CEC

Defines

#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
Check CEC initiator or destination logical address setting.
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
Check CEC message size.

Define Documentation

#define IS_CEC_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0xF)

Check CEC initiator or destination logical address setting.

Initiator and destination addresses are coded over 4 bits.

Parameters:
__ADDRESS__,: CEC initiator or logical address.
Return values:
Test result (TRUE or FALSE).

Definition at line 641 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define IS_CEC_BREERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))

Definition at line 614 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BRERXSTOP ( __BRERXSTOP__ )
Value:
(((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))

Definition at line 611 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))

Definition at line 620 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LBPEERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))

Definition at line 617 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LISTENING_MODE ( __MODE__ )
Value:
(((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))

Definition at line 626 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_MSGSIZE ( __SIZE__ ) ((__SIZE__) <= 0xF)

Check CEC message size.

The message size is the payload size: without counting the header, it varies from 0 byte (ping operation, one header only, no payload) to 15 bytes (1 opcode and up to 14 operands following the header).

Parameters:
__SIZE__,: CEC message size.
Return values:
Test result (TRUE or FALSE).

Definition at line 650 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Receive(), HAL_CEC_Transmit(), and HAL_CEC_Transmit_IT().

#define IS_CEC_OAR_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0x07FFF)

Check CEC device Own Address Register (OAR) setting.

OAR address is written in a 15-bit field within CEC_CFGR register.

Parameters:
__ADDRESS__,: CEC own address.
Return values:
Test result (TRUE or FALSE).

Definition at line 634 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_SFTOP ( __SFTOP__ )
Value:
(((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))

Definition at line 623 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_SIGNALFREETIME ( __SFT__ ) ((__SFT__) <= CEC_CFGR_SFT)

Definition at line 606 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_TOLERANCE ( __RXTOL__ )
Value:
(((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))

Definition at line 608 of file stm32f7xx_hal_cec.h.

Referenced by HAL_CEC_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disables a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
Return values:
None

Definition at line 221 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enables a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
Return values:
None

Definition at line 205 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
PreemptPriority,: The preemption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority,: the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 183 of file stm32f7xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup,: The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 161 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiates a system reset request to reset the MCU.

Return values:
None

Definition at line 234 of file stm32f7xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb,: Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 247 of file stm32f7xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initializes and configures the Region and the memory to be protected.

Parameters:
MPU_Init,: Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 278 of file stm32f7xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clears the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
Return values:
None

Definition at line 398 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Gets active interrupt ( reads the active register in NVIC and returns the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 415 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 382 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Gets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
pPreemptPriority,: Pointer on the Preemptive priority value (starting from 0).
pSubPriority,: Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 349 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Gets the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 322 of file stm32f7xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Sets Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
Return values:
None

Definition at line 364 of file stm32f7xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 459 of file stm32f7xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configures the SysTick clock source.

Parameters:
CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 432 of file stm32f7xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

This function handles SYSTICK interrupt request.

Return values:
None

Definition at line 450 of file stm32f7xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32f7xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 66 of file stm32f7xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 79 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 72 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 81 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 68 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 87 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 85 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 83 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 70 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 73 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 75 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of MPU TEX Levels

Definition at line 77 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_cortex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

Define Documentation

#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 108 of file stm32f7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 110 of file stm32f7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 112 of file stm32f7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 114 of file stm32f7xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 116 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_Init().

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX _SysTick clock source

Defines
CORTEX _SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Definition at line 126 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)

Definition at line 125 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: MPU HFNMI and PRIVILEGED Access control

Defines
MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Define Documentation

#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)

Definition at line 137 of file stm32f7xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Definition at line 139 of file stm32f7xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)

Definition at line 136 of file stm32f7xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)

Definition at line 138 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 148 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 147 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 157 of file stm32f7xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 156 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 166 of file stm32f7xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 165 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 174 of file stm32f7xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 175 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 183 of file stm32f7xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 184 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: MPU TEX Levels

Defines
MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 192 of file stm32f7xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 193 of file stm32f7xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 194 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06)

Definition at line 204 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 214 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 224 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 211 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 221 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 227 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 207 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 217 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 205 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 215 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 225 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 228 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 208 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 218 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04)

Definition at line 202 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 212 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 222 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 229 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 209 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 219 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 206 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 216 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 226 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05)

Definition at line 203 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 213 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 223 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 210 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 220 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 240 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 237 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 241 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 242 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 238 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 239 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 250 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 251 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 252 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 253 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 254 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 255 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 256 of file stm32f7xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 257 of file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 348 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 345 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 342 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 339 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 336 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 362 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 355 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 371 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FF)

Definition at line 400 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 351 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) >= 0x00)

Definition at line 330 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 326 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 320 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 328 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 332 of file stm32f7xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

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STM32F745xx HAL User Manual: CORTEX Private Functions

Functions
CORTEX Private Functions
CORTEX

CORTEX private functions. More...

Functions

__STATIC_INLINE void | HAL_MPU_Disable (void)
Disables the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

CORTEX private functions.

Function Documentation

__STATIC_INLINE void HAL_MPU_Disable ( void )

Disables the MPU.

Return values:
None

Definition at line 418 of file stm32f7xx_hal_cortex.h.

__STATIC_INLINE void HAL_MPU_Enable ( uint32_t MPU_Control )

Enables the MPU.

Parameters:
MPU_Control,: Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 438 of file stm32f7xx_hal_cortex.h.

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STM32F745xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP
      (+) DeInitialize CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 195 of file stm32f7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 118 of file stm32f7xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

__weak void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 251 of file stm32f7xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

__weak void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 236 of file stm32f7xx_hal_crc.c.

Referenced by HAL_CRC_Init().

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STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Detailed Description

Peripheral Control functions.

 ==============================================================================
                      ##### Peripheral Control functions #####
 ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using combination of the previous CRC value and the new one.

          or

      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer
BufferLength,: input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 456 of file stm32f7xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer
BufferLength,: input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 415 of file stm32f7xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 300 of file stm32f7xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 358 of file stm32f7xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

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STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Detailed Description

Peripheral State functions.

 ==============================================================================
                      ##### Peripheral State functions #####
 ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC state.

Parameters:
hcrc,: CRC handle
Return values:
HAL state

Definition at line 500 of file stm32f7xx_hal_crc.c.

References CRC_HandleTypeDef::State.

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STM32F745xx HAL User Manual: CRC Exported Functions

Modules | Defines
CRC Exported Functions
CRC

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Defines

#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Define Documentation

#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse

Definition at line 306 of file stm32f7xx_hal_crc.h.

#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Definition at line 307 of file stm32f7xx_hal_crc.h.

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STM32F745xx HAL User Manual: CRC State Structure definition

Enumerations
CRC State Structure definition
CRC Exported Types

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00, HAL_CRC_STATE_READY = 0x01, HAL_CRC_STATE_BUSY = 0x02, HAL_CRC_STATE_TIMEOUT = 0x03,
HAL_CRC_STATE_ERROR = 0x04
}

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef
Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 66 of file stm32f7xx_hal_crc.h.

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STM32F745xx HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Init Structure definition

#include <stm32f7xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

Definition at line 81 of file stm32f7xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the IP and indicates CRC length. Value can be either one of CRC_POLYLENGTH_32B (32-bit CRC) CRC_POLYLENGTH_16B (16-bit CRC) CRC_POLYLENGTH_8B (8-bit CRC) CRC_POLYLENGTH_7B (7-bit CRC)

Definition at line 99 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set

Definition at line 89 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set

Definition at line 83 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE

Definition at line 94 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE

Definition at line 106 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of CRC Extended input data inversion modes and specifies input data inversion mode. Can be either one of the following values CRC_INPUTDATA_INVERSION_NONE no input data inversion CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 109 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of CRC Extended output data inversion modes and specifies output data (i.e. CRC) inversion mode. Can be either CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 116 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_crc.h
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STM32F745xx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Handle Structure definition

#include <stm32f7xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

Definition at line 128 of file stm32f7xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 132 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of CRC input buffer format and specifies input data format. Can be either CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data) Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 138 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 130 of file stm32f7xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 134 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 136 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_crc.h
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STM32F745xx HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC exported constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7

Definition at line 162 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F745xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC exported constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF

Definition at line 171 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F745xx HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC exported constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)

Definition at line 181 of file stm32f7xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)

Definition at line 180 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F745xx HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC exported constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)

Definition at line 192 of file stm32f7xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)

Definition at line 191 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F745xx HAL User Manual: Polynomial sizes to configure the IP

Defines
Polynomial sizes to configure the IP
CRC exported constants

Defines

#define | CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Define Documentation

#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)

Definition at line 202 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)

Definition at line 201 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Definition at line 204 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)

Definition at line 203 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32F745xx HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC exported constants

Defines

#define | HAL_CRC_LENGTH_32B 32
#define | HAL_CRC_LENGTH_16B 16
#define | HAL_CRC_LENGTH_8B 8
#define | HAL_CRC_LENGTH_7B 7

Define Documentation

#define HAL_CRC_LENGTH_16B 16

Definition at line 213 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32

Definition at line 212 of file stm32f7xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7

Definition at line 215 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8

Definition at line 214 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32F745xx HAL User Manual: CRC input buffer format

Defines
CRC input buffer format
CRC exported constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define | CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)

Definition at line 229 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)

Definition at line 230 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)

Definition at line 228 of file stm32f7xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)

Definition at line 231 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32F745xx HAL User Manual: CRC exported macros

Defines
CRC exported macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
Stores a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 8-bit data stored in the Independent Data(ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__,: CRC handle
Return values:
None.

Definition at line 256 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
Return values:
8-bit value of the ID register

Definition at line 279 of file stm32f7xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | : CRC handle
__INIT__ | : 32-bit initial value
Return values:
None.

Definition at line 264 of file stm32f7xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__,: CRC handle.
Return values:
None

Definition at line 249 of file stm32f7xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
__VALUE__,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 272 of file stm32f7xx_hal_crc.h.

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STM32F745xx HAL User Manual: CRC Private Types

CRC Private Types
CRC
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CRC Private Defines

CRC Private Defines
CRC
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CRC Private Variables

CRC Private Variables
CRC
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CRC Private Constants

CRC Private Constants
CRC
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(__DEFAULT__)
#define | IS_DEFAULT_INIT_VALUE(__VALUE__)
#define | IS_CRC_POL_LENGTH(__LENGTH__)
#define | IS_CRC_INPUTDATA_FORMAT(__FORMAT__)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( __FORMAT__ )
Value:
(((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 381 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == CRC_POLYLENGTH_32B) || \
                                           ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
                                           ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \
                                           ((__LENGTH__) == CRC_POLYLENGTH_7B))

Definition at line 377 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
                                           ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 375 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( __DEFAULT__ )
Value:
(((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                            ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 373 of file stm32f7xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32F745xx HAL User Manual: CRC Private Functions Prototypes

CRC Private Functions Prototypes
CRC
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STM32F745xx HAL User Manual: CRC Private Functions

CRC Private Functions
CRC
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STM32F745xx HAL User Manual: CRC Extended input data inversion modes

Defines
CRC Extended input data inversion modes
CRC Extended exported constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define | IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)

Definition at line 68 of file stm32f7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)

Definition at line 69 of file stm32f7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)

Definition at line 67 of file stm32f7xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)

Definition at line 70 of file stm32f7xx_hal_crc_ex.h.

#define IS_CRC_INPUTDATA_INVERSION_MODE ( __MODE__ )
Value:
(((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 72 of file stm32f7xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

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STM32F745xx HAL User Manual: CRC Extended output data inversion modes

Defines
CRC Extended output data inversion modes
CRC Extended exported constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)

Definition at line 83 of file stm32f7xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)

Definition at line 84 of file stm32f7xx_hal_crc_ex.h.

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( __MODE__ )
Value:
(((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                       ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 86 of file stm32f7xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

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STM32F745xx HAL User Manual: CRC Extended exported macros

Defines
CRC Extended exported macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ : CRC handle
Return values:
None.

Definition at line 114 of file stm32f7xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ : CRC handle
Return values:
None.

Definition at line 107 of file stm32f7xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ : CRC handle
__POLYNOMIAL__,: 7, 8, 16 or 32-bit polynomial
Return values:
None.

Definition at line 122 of file stm32f7xx_hal_crc_ex.h.

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STM32F745xx HAL User Manual: Extended CRC features functions

Functions
Extended CRC features functions
CRC Extended Exported Functions

Extended CRC features functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initializes the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC features functions.

 ===============================================================================
            ##### CRC Extended features functions #####
 ===============================================================================
    [..]
This subsection provides function allowing to:
      (+) Set CRC polynomial if different from default one.

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc,: CRC handle
InputReverseMode,: Input Data inversion mode This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
Return values:
HAL status

Definition at line 175 of file stm32f7xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc,: CRC handle
OutputReverseMode,: Output Data inversion mode This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 201 of file stm32f7xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initializes the CRC polynomial if different from default one.

Parameters:
hcrc,: CRC handle
Pol,: CRC generating polynomial (7, 8, 16 or 32-bit long) This parameter is written in normal representation, e.g. for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength,: CRC polynomial length This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 109 of file stm32f7xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitializes the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initializes the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitializes the DAC MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitializes the DAC peripheral registers to their default reset values.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 267 of file stm32f7xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 230 of file stm32f7xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, DAC_HandleTypeDef::Lock, and DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitializes the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 319 of file stm32f7xx_hal_dac.c.

Referenced by HAL_DAC_DeInit().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initializes the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 303 of file stm32f7xx_hal_dac.c.

Referenced by HAL_DAC_Init().

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STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.

Function Documentation

__weak void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 689 of file stm32f7xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

__weak void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 705 of file stm32f7xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

__weak void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 737 of file stm32f7xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

__weak void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 721 of file stm32f7xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 621 of file stm32f7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 643 of file stm32f7xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 361 of file stm32f7xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData,: The destination peripheral Buffer address.
Length,: The length of data to be transferred from memory to DAC peripheral
Alignment,: Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 452 of file stm32f7xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 420 of file stm32f7xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 571 of file stm32f7xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, DAC_CHANNEL_1, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

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STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 777 of file stm32f7xx_hal_dac.c.

References assert_param, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_ChannelConfTypeDef::DAC_Trigger, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_TRIGGER, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Alignment,: Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data,: Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 833 of file stm32f7xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

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STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 689 of file stm32f7xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 705 of file stm32f7xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 737 of file stm32f7xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 721 of file stm32f7xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 898 of file stm32f7xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC state

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 885 of file stm32f7xx_hal_dac.c.

References DAC_HandleTypeDef::State.

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 643 of file stm32f7xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

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STM32F745xx HAL User Manual: DAC Exported Functions

Modules | Functions
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 913 of file stm32f7xx_hal_dac.c.

References HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 941 of file stm32f7xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 928 of file stm32f7xx_hal_dac.c.

References HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA().

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STM32F745xx HAL User Manual: DAC Exported Types

Data Structures | Enumerations
DAC Exported Types
DAC

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00, HAL_DAC_STATE_READY = 0x01, HAL_DAC_STATE_BUSY = 0x02, HAL_DAC_STATE_TIMEOUT = 0x03,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 65 of file stm32f7xx_hal_dac.h.

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STM32F745xx HAL User Manual: DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32f7xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode

Detailed Description

DAC handle Structure definition.

Definition at line 77 of file stm32f7xx_hal_dac.h.

Field Documentation

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 85 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 87 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

__IO uint32_t DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 89 of file stm32f7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), and HAL_DAC_IRQHandler().

DAC_TypeDef* DAC_HandleTypeDef::Instance

Register base address

Definition at line 79 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 83 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Init().

__IO HAL_DAC_StateTypeDef DAC_HandleTypeDef::State

DAC communication state

Definition at line 81 of file stm32f7xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dac.h
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STM32F745xx HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32f7xx_hal_dac.h>

Data Fields

uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 96 of file stm32f7xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC Output Buffer

Definition at line 101 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC Trigger Selection

Definition at line 98 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dac.h
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STM32F745xx HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04

DMA error

Definition at line 119 of file stm32f7xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), and DAC_DMAErrorCh2().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01

DAC channel1 DAM underrun error

Definition at line 117 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02

DAC channel2 DAM underrun error

Definition at line 118 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_NONE 0x00

No error

Definition at line 116 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

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STM32F745xx HAL User Manual: DAC Trigger Selection

Defines
DAC Trigger Selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Define Documentation

#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 137 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_NONE ((uint32_t)0x00000000)

Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger

Definition at line 128 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Conversion started by software trigger for DAC channel

Definition at line 138 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 130 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 131 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM5 TRGO selected as external conversion trigger for DAC channel

Definition at line 132 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 133 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 134 of file stm32f7xx_hal_dac.h.

#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM8 TRGO selected as external conversion trigger for DAC channel

Definition at line 135 of file stm32f7xx_hal_dac.h.

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STM32F745xx HAL User Manual: DAC Output Buffer

Defines
DAC Output Buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)

Definition at line 147 of file stm32f7xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)

Definition at line 146 of file stm32f7xx_hal_dac.h.

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STM32F745xx HAL User Manual: DAC Channel Selection

Defines
DAC Channel Selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010)

Define Documentation

#define DAC_CHANNEL_1 ((uint32_t)0x00000000)

Definition at line 155 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_CHANNEL_2 ((uint32_t)0x00000010)

Definition at line 156 of file stm32f7xx_hal_dac.h.

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STM32F745xx HAL User Manual: DAC Data Alignment

Defines
DAC Data Alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008)

Define Documentation

#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)

Definition at line 165 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)

Definition at line 164 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)

Definition at line 166 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

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STM32F745xx HAL User Manual: DAC Flags Definition

Defines
DAC Flags Definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 174 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 175 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

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STM32F745xx HAL User Manual: DAC IT Definition

Defines
DAC IT Definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 183 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 184 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

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STM32F745xx HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))
Disable the DAC channel.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified DAC interrupt source is enabled or disabled.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DMA underrun 1 flag
  • DAC_FLAG_DMAUDR2: DMA underrun 2 flag
Return values:
None

Definition at line 263 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_CHANNEL__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))

Disable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle
__DAC_CHANNEL__,: specifies the DAC channel.
Return values:
None

Definition at line 217 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), and HAL_DAC_Stop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt.
Return values:
None

Definition at line 233 of file stm32f7xx_hal_dac.h.

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_CHANNEL__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))

Enable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle.
__DAC_CHANNEL__,: specifies the DAC channel
Return values:
None

Definition at line 209 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DAC_Start_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt.
Return values:
None

Definition at line 226 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DMA underrun 1 flag
  • DAC_FLAG_DMAUDR2: DMA underrun 2 flag
Return values:
None

Definition at line 253 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified DAC interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: DAC handle
__INTERRUPT__,: DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 243 of file stm32f7xx_hal_dac.h.

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)

Reset DAC handle state.

Parameters:
__HANDLE__,: specifies the DAC handle.
Return values:
None

Definition at line 202 of file stm32f7xx_hal_dac.h.

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STM32F745xx HAL User Manual: DAC Private Constants

DAC Private Constants
DAC
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
Set DHR12RD alignment.

Define Documentation

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000008) + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 368 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000014) + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 374 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000020) + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 380 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 346 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                 ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 349 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0)

Definition at line 345 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 351 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE) || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Definition at line 354 of file stm32f7xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

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STM32F745xx HAL User Manual: DAC Private Functions

DAC Private Functions
DAC
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended features functions

Functions
Extended features functions
DAC Exported Functions

Extended features functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.

Detailed Description

Extended features functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 270 of file stm32f7xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 286 of file stm32f7xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 318 of file stm32f7xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Returns the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 106 of file stm32f7xx_hal_dac_ex.c.

References DAC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data2,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 231 of file stm32f7xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 302 of file stm32f7xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude,: Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 191 of file stm32f7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude,: Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 142 of file stm32f7xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

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STM32F745xx HAL User Manual: DAC Exported Functions

Modules | Functions
DAC Exported Functions
DACEx

Modules

Extended features functions

Extended features functions.

Functions

__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 334 of file stm32f7xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 362 of file stm32f7xx_hal_dac_ex.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 349 of file stm32f7xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

__weak void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 270 of file stm32f7xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

__weak void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 286 of file stm32f7xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

__weak void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 318 of file stm32f7xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

__weak void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 302 of file stm32f7xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DAC LFS Run Mask Triangle Amplitude

Defines
DAC LFS Run Mask Triangle Amplitude
DAC Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 66 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 76 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 77 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 67 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 68 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 69 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 70 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 71 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 72 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 73 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 74 of file stm32f7xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 75 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)

Select max triangle amplitude of 1

Definition at line 78 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 87 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 127

Definition at line 84 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 81 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 2047

Definition at line 88 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 85 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 79 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)

Select max triangle amplitude of 31

Definition at line 82 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 89 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)

Select max triangle amplitude of 511

Definition at line 86 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 83 of file stm32f7xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)

Select max triangle amplitude of 7

Definition at line 80 of file stm32f7xx_hal_dac_ex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DAC Private Constants

DAC Private Constants
DACEx
Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DACEx

Defines

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 138 of file stm32f7xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DACEx

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 334 of file stm32f7xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 362 of file stm32f7xx_hal_dac_ex.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 349 of file stm32f7xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
DCMI Exported Functions

Initialization and Configuration functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DCMI
      (+) De-initialize the DCMI

Function Documentation

HAL_StatusTypeDef HAL_DCMI_DeInit ( DCMI_HandleTypeDef * hdcmi )

Deinitializes the DCMI peripheral registers to their default reset values.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 225 of file stm32f7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_MspDeInit(), HAL_DCMI_STATE_RESET, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_Init ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 143 of file stm32f7xx_hal_dcmi.c.

References __HAL_DCMI_ENABLE, __HAL_DCMI_ENABLE_IT, assert_param, DCMI_InitTypeDef::CaptureRate, DCMI_IT_ERR, DCMI_IT_FRAME, DCMI_IT_LINE, DCMI_IT_OVF, DCMI_IT_VSYNC, DCMI_SYNCHRO_EMBEDDED, DCMI_HandleTypeDef::ErrorCode, DCMI_InitTypeDef::ExtendedDataMode, DCMI_CodesInitTypeDef::FrameEndCode, DCMI_CodesInitTypeDef::FrameStartCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_MspInit(), HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_RESET, DCMI_InitTypeDef::HSPolarity, DCMI_HandleTypeDef::Init, DCMI_HandleTypeDef::Instance, IS_DCMI_CAPTURE_RATE, IS_DCMI_EXTENDED_DATA, IS_DCMI_HSPOLARITY, IS_DCMI_MODE_JPEG, IS_DCMI_PCKPOLARITY, IS_DCMI_SYNCHRO, IS_DCMI_VSPOLARITY, DCMI_InitTypeDef::JPEGMode, DCMI_CodesInitTypeDef::LineEndCode, DCMI_CodesInitTypeDef::LineStartCode, DCMI_HandleTypeDef::Lock, DCMI_InitTypeDef::PCKPolarity, DCMI_HandleTypeDef::State, DCMI_InitTypeDef::SynchroMode, DCMI_InitTypeDef::SyncroCode, and DCMI_InitTypeDef::VSPolarity.

void HAL_DCMI_MspDeInit ( DCMI_HandleTypeDef * hdcmi )

DeInitializes the DCMI MSP.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 264 of file stm32f7xx_hal_dcmi.c.

Referenced by HAL_DCMI_DeInit().

void HAL_DCMI_MspInit ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI MSP.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 248 of file stm32f7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Init().

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STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
DCMI Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure destination address and data length and
          Enables DCMI DMA request and enables DCMI capture
      (+) Stop the DCMI capture.
      (+) Handles DCMI interrupt request.

Function Documentation

void HAL_DCMI_ErrorCallback ( DCMI_HandleTypeDef * hdcmi )

Error DCMI callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 546 of file stm32f7xx_hal_dcmi.c.

Referenced by DCMI_DMAError(), and HAL_DCMI_IRQHandler().

void HAL_DCMI_FrameEventCallback ( DCMI_HandleTypeDef * hdcmi )

Frame Event callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 591 of file stm32f7xx_hal_dcmi.c.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_IRQHandler().

void HAL_DCMI_IRQHandler ( DCMI_HandleTypeDef * hdcmi )

Handles DCMI interrupt request.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for the DCMI.
Return values:
None

Definition at line 431 of file stm32f7xx_hal_dcmi.c.

References __HAL_DCMI_CLEAR_FLAG, __HAL_DCMI_DISABLE_IT, __HAL_DCMI_GET_FLAG, __HAL_DCMI_GET_IT_SOURCE, DCMI_FLAG_ERRRI, DCMI_FLAG_FRAMERI, DCMI_FLAG_LINERI, DCMI_FLAG_OVFRI, DCMI_FLAG_VSYNCRI, DCMI_IT_ERR, DCMI_IT_FRAME, DCMI_IT_LINE, DCMI_IT_OVF, DCMI_IT_VSYNC, DCMI_HandleTypeDef::DMA_Handle, DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_OVF, HAL_DCMI_ERROR_SYNC, HAL_DCMI_ErrorCallback(), HAL_DCMI_FrameEventCallback(), HAL_DCMI_LineEventCallback(), HAL_DCMI_STATE_ERROR, HAL_DCMI_VsyncEventCallback(), HAL_DMA_Abort(), and DCMI_HandleTypeDef::State.

void HAL_DCMI_LineEventCallback ( DCMI_HandleTypeDef * hdcmi )

Line Event callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 562 of file stm32f7xx_hal_dcmi.c.

Referenced by HAL_DCMI_IRQHandler().

HAL_StatusTypeDef HAL_DCMI_Start_DMA | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | uint32_t | DCMI_Mode,
 |  | uint32_t | pData,
 |  | uint32_t | Length
 | ) |  |

Enables DCMI DMA request and enables DCMI capture.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
DCMI_Mode,: DCMI capture mode snapshot or continuous grab.
pData,: The destination memory Buffer address (LCD Frame buffer).
Length,: The length of capture to be transferred.
Return values:
HAL status

Definition at line 303 of file stm32f7xx_hal_dcmi.c.

References assert_param, DCMI_DMAConvCplt(), DCMI_DMAError(), DCMI_HandleTypeDef::DMA_Handle, HAL_DCMI_STATE_BUSY, HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart_IT(), DCMI_HandleTypeDef::Instance, IS_DCMI_CAPTURE_MODE, DCMI_HandleTypeDef::pBuffPtr, DCMI_HandleTypeDef::State, DCMI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferM1CpltCallback, DCMI_HandleTypeDef::XferSize, and DCMI_HandleTypeDef::XferTransferNumber.

HAL_StatusTypeDef HAL_DCMI_Stop ( DCMI_HandleTypeDef * hdcmi )

Disable DCMI DMA request and Disable DCMI capture.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 376 of file stm32f7xx_hal_dcmi.c.

References __HAL_DCMI_DISABLE, DCMI_HandleTypeDef::DMA_Handle, DCMI_HandleTypeDef::ErrorCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_ERROR_TIMEOUT, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_TIMEOUT, HAL_DMA_Abort(), HAL_GetTick(), HAL_TIMEOUT_DCMI_STOP, DCMI_HandleTypeDef::Instance, and DCMI_HandleTypeDef::State.

void HAL_DCMI_VsyncEventCallback ( DCMI_HandleTypeDef * hdcmi )

VSYNC Event callback.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
None

Definition at line 575 of file stm32f7xx_hal_dcmi.c.

Referenced by HAL_DCMI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DCMI Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DCMI_ConfigCROP (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_DisableCROP (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_EnableCROP (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
[..]  This section provides functions allowing to:
      (+) Configure the CROP feature.
      (+) Enable/Disable the CROP feature.
            (+) Enable/Disable the JPEG feature.

Function Documentation

HAL_StatusTypeDef HAL_DCMI_ConfigCROP | ( | DCMI_HandleTypeDef * | hdcmi,
 |  | uint32_t | X0,
 |  | uint32_t | Y0,
 |  | uint32_t | XSize,
 |  | uint32_t | YSize
 | ) |  |

Configure the DCMI CROP coordinate.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
YSize,: DCMI Line number
XSize,: DCMI Pixel per line
X0,: DCMI window X offset
Y0,: DCMI window Y offset
Return values:
HAL status

Definition at line 631 of file stm32f7xx_hal_dcmi.c.

References assert_param, HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, IS_DCMI_WINDOW_COORDINATE, IS_DCMI_WINDOW_HEIGHT, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_DisableCROP ( DCMI_HandleTypeDef * hdcmi )

Disable the Crop feature.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 664 of file stm32f7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, and DCMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DCMI_EnableCROP ( DCMI_HandleTypeDef * hdcmi )

Enable the Crop feature.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 690 of file stm32f7xx_hal_dcmi.c.

References HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, and DCMI_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DCMI Exported Functions

Peripheral State functions. More...

Functions

HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
               ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DCMI state.
      (+) Get the specific DCMI error flag.

Function Documentation

uint32_t HAL_DCMI_GetError ( DCMI_HandleTypeDef * hdcmi )

Return the DCMI error code.

Parameters:
hdcmi : pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
DCMI Error Code

Definition at line 747 of file stm32f7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::ErrorCode.

HAL_DCMI_StateTypeDef HAL_DCMI_GetState ( DCMI_HandleTypeDef * hdcmi )

Return the DCMI state.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL state

Definition at line 736 of file stm32f7xx_hal_dcmi.c.

References DCMI_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI Private Functions

Functions
DCMI Private Functions
DCMI Exported Functions | DCMI

Functions

static void | DCMI_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DCMI_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DCMI_DMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 765 of file stm32f7xx_hal_dcmi.c.

References __HAL_DCMI_GET_FLAG, DCMI_FLAG_FRAMERI, DCMI_HandleTypeDef::DMA_Handle, HAL_DCMI_FrameEventCallback(), HAL_DCMI_STATE_READY, HAL_DMAEx_ChangeMemory(), __DMA_HandleTypeDef::Instance, MEMORY0, MEMORY1, DCMI_HandleTypeDef::pBuffPtr, DCMI_HandleTypeDef::State, DCMI_HandleTypeDef::XferCount, DCMI_HandleTypeDef::XferSize, and DCMI_HandleTypeDef::XferTransferNumber.

Referenced by HAL_DCMI_Start_DMA().

static void DCMI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 819 of file stm32f7xx_hal_dcmi.c.

References HAL_DCMI_ErrorCallback(), HAL_DCMI_STATE_READY, and DCMI_HandleTypeDef::State.

Referenced by HAL_DCMI_Start_DMA().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI Exported Types

Data Structures | Enumerations
DCMI Exported Types
DCMI

Data Structures

struct DCMI_HandleTypeDef
DCMI handle Structure definition. More...

Enumerations

enum HAL_DCMI_StateTypeDef {
HAL_DCMI_STATE_RESET = 0x00, HAL_DCMI_STATE_READY = 0x01, HAL_DCMI_STATE_BUSY = 0x02, HAL_DCMI_STATE_TIMEOUT = 0x03,
HAL_DCMI_STATE_ERROR = 0x04
}
HAL DCMI State structures definition. More...

Enumeration Type Documentation

enum HAL_DCMI_StateTypeDef

HAL DCMI State structures definition.

Enumerator:
HAL_DCMI_STATE_RESET

DCMI not yet initialized or disabled

HAL_DCMI_STATE_READY

DCMI initialized and ready for use

HAL_DCMI_STATE_BUSY

DCMI internal processing is ongoing

HAL_DCMI_STATE_TIMEOUT

DCMI timeout state

HAL_DCMI_STATE_ERROR

DCMI error state

Definition at line 69 of file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_HandleTypeDef Struct Reference
DCMI Exported Types

DCMI handle Structure definition. More...

#include <stm32f7xx_hal_dcmi.h>

Data Fields

DCMI_TypeDef * | Instance
DCMI_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DCMI_StateTypeDef | State
__IO uint32_t | XferCount
__IO uint32_t | XferSize
uint32_t | XferTransferNumber
uint32_t | pBuffPtr
DMA_HandleTypeDef * DMA_Handle
__IO uint32_t | ErrorCode

Detailed Description

DCMI handle Structure definition.

Definition at line 81 of file stm32f7xx_hal_dcmi.h.

Field Documentation

DMA_HandleTypeDef* DCMI_HandleTypeDef::DMA_Handle

Pointer to the DMA handler

Definition at line 99 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), HAL_DCMI_IRQHandler(), HAL_DCMI_Start_DMA(), and HAL_DCMI_Stop().

__IO uint32_t DCMI_HandleTypeDef::ErrorCode

DCMI Error code

Definition at line 101 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_DeInit(), HAL_DCMI_GetError(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), and HAL_DCMI_Stop().

DCMI_InitTypeDef DCMI_HandleTypeDef::Init

DCMI parameters

Definition at line 85 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

DCMI_TypeDef* DCMI_HandleTypeDef::Instance

DCMI Register base address

Definition at line 83 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), HAL_DCMI_Start_DMA(), and HAL_DCMI_Stop().

HAL_LockTypeDef DCMI_HandleTypeDef::Lock

DCMI locking object

Definition at line 87 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_HandleTypeDef::pBuffPtr

Pointer to DMA output buffer

Definition at line 97 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_Start_DMA().

__IO HAL_DCMI_StateTypeDef DCMI_HandleTypeDef::State

DCMI state

Definition at line 89 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), DCMI_DMAError(), HAL_DCMI_ConfigCROP(), HAL_DCMI_DeInit(), HAL_DCMI_DisableCROP(), HAL_DCMI_EnableCROP(), HAL_DCMI_GetState(), HAL_DCMI_Init(), HAL_DCMI_IRQHandler(), HAL_DCMI_Start_DMA(), and HAL_DCMI_Stop().

__IO uint32_t DCMI_HandleTypeDef::XferCount

DMA transfer counter

Definition at line 91 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_Start_DMA().

__IO uint32_t DCMI_HandleTypeDef::XferSize

DMA transfer size

Definition at line 93 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_Start_DMA().

uint32_t DCMI_HandleTypeDef::XferTransferNumber

DMA transfer number

Definition at line 95 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_Start_DMA().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dcmi.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI Error Code

Defines
DCMI Error Code
DCMI Exported Constants

Defines

#define | HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001)
#define | HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002)
#define | HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020)

Define Documentation

#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 116 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_DeInit(), HAL_DCMI_Init(), and HAL_DCMI_Stop().

#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001)

Overflow error

Definition at line 117 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002)

Synchronization error

Definition at line 118 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020)

Timeout error

Definition at line 119 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Stop().

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STM32F745xx HAL User Manual: DCMI Capture Mode

Defines
DCMI Capture Mode
DCMI Exported Constants

Defines

#define | DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000)
#define | DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)

Define Documentation

#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000)

The received data are transferred continuously into the destination memory through the DMA

Definition at line 127 of file stm32f7xx_hal_dcmi.h.

#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)

Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA

Definition at line 129 of file stm32f7xx_hal_dcmi.h.

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STM32F745xx HAL User Manual: DCMI Synchronization Mode

Defines
DCMI Synchronization Mode
DCMI Exported Constants

Defines

#define | DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000)
#define | DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)

Define Documentation

#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)

Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow

Definition at line 140 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000)

Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals

Definition at line 138 of file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI PIXCK Polarity

Defines
DCMI PIXCK Polarity
DCMI Exported Constants

Defines

#define | DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000)
#define | DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)

Define Documentation

#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000)

Pixel clock active on Falling edge

Definition at line 150 of file stm32f7xx_hal_dcmi.h.

#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)

Pixel clock active on Rising edge

Definition at line 151 of file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI VSYNC Polarity

Defines
DCMI VSYNC Polarity
DCMI Exported Constants

Defines

#define | DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000)
#define | DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)

Define Documentation

#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)

Vertical synchronization active High

Definition at line 161 of file stm32f7xx_hal_dcmi.h.

#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000)

Vertical synchronization active Low

Definition at line 160 of file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI HSYNC Polarity

Defines
DCMI HSYNC Polarity
DCMI Exported Constants

Defines

#define | DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000)
#define | DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)

Define Documentation

#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)

Horizontal synchronization active High

Definition at line 171 of file stm32f7xx_hal_dcmi.h.

#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000)

Horizontal synchronization active Low

Definition at line 170 of file stm32f7xx_hal_dcmi.h.

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STM32F745xx HAL User Manual: DCMI MODE JPEG

Defines
DCMI MODE JPEG
DCMI Exported Constants

Defines

#define | DCMI_JPEG_DISABLE ((uint32_t)0x00000000)
#define | DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)

Define Documentation

#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000)

Mode JPEG Disabled

Definition at line 180 of file stm32f7xx_hal_dcmi.h.

#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)

Mode JPEG Enabled

Definition at line 181 of file stm32f7xx_hal_dcmi.h.

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STM32F745xx HAL User Manual: DCMI Capture Rate

Defines
DCMI Capture Rate
DCMI Exported Constants

Defines

#define | DCMI_CR_ALL_FRAME ((uint32_t)0x00000000)
#define | DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)
#define | DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)

Define Documentation

#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000)

All frames are captured

Definition at line 190 of file stm32f7xx_hal_dcmi.h.

#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)

Every alternate frame captured

Definition at line 191 of file stm32f7xx_hal_dcmi.h.

#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)

One frame in 4 frames captured

Definition at line 192 of file stm32f7xx_hal_dcmi.h.

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STM32F745xx HAL User Manual: DCMI Extended Data Mode

Defines
DCMI Extended Data Mode
DCMI Exported Constants

Defines

#define | DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000)
#define | DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)
#define | DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)
#define | DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))

Define Documentation

#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)

Interface captures 10-bit data on every pixel clock

Definition at line 202 of file stm32f7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)

Interface captures 12-bit data on every pixel clock

Definition at line 203 of file stm32f7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))

Interface captures 14-bit data on every pixel clock

Definition at line 204 of file stm32f7xx_hal_dcmi.h.

#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000)

Interface captures 8-bit data on every pixel clock

Definition at line 201 of file stm32f7xx_hal_dcmi.h.

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STM32F745xx HAL User Manual: DCMI Window Coordinate

Defines
DCMI Window Coordinate
DCMI Exported Constants

Defines

#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF)

Define Documentation

#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF)

Window coordinate

Definition at line 213 of file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI Window Height

Defines
DCMI Window Height
DCMI Exported Constants

Defines

#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF)

Define Documentation

#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF)

Window Height

Definition at line 222 of file stm32f7xx_hal_dcmi.h.

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STM32F745xx HAL User Manual: DCMI interrupt sources

Defines
DCMI interrupt sources
DCMI Exported Constants

Defines

#define | DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define | DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
#define | DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define | DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define | DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)

Define Documentation

#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)

Definition at line 233 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)

Definition at line 231 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)

Definition at line 235 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)

Definition at line 232 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)

Definition at line 234 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init(), and HAL_DCMI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI Flags

Defines
DCMI Flags
DCMI Exported Constants

Defines

#define | DCMI_FLAG_HSYNC ((uint32_t)0x2001)
DCMI SR register.
#define | DCMI_FLAG_VSYNC ((uint32_t)0x2002)
#define | DCMI_FLAG_FNE ((uint32_t)0x2004)
#define | DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)
DCMI RISR register.
#define | DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)
#define | DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)
#define | DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)
#define | DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)
#define | DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)
DCMI MISR register.
#define | DCMI_FLAG_OVFMI ((uint32_t)0x1002)
#define | DCMI_FLAG_ERRMI ((uint32_t)0x1004)
#define | DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
#define | DCMI_FLAG_LINEMI ((uint32_t)0x1010)

Define Documentation

#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)

Definition at line 263 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)

Definition at line 255 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_FNE ((uint32_t)0x2004)

Definition at line 249 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)

DCMI MISR register.

Definition at line 261 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)

DCMI RISR register.

Definition at line 253 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_IRQHandler().

#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)

DCMI SR register.

Definition at line 247 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)

Definition at line 265 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)

Definition at line 257 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_OVFMI ((uint32_t)0x1002)

Definition at line 262 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)

Definition at line 254 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)

Definition at line 248 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)

Definition at line 264 of file stm32f7xx_hal_dcmi.h.

#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)

Definition at line 256 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

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STM32F745xx HAL User Manual: DCMI Exported Macros

Defines
DCMI Exported Macros
DCMI

Defines

#define | __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
Reset DCMI handle state.
#define | __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
Enable the DCMI.
#define | __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
Disable the DCMI.
#define | __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)
Get the DCMI pending flags.
#define | __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the DCMI pending flags.
#define | __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified DCMI interrupts.
#define | __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified DCMI interrupts.
#define | __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
Check whether the specified DCMI interrupt has occurred or not.

Define Documentation

#define __HAL_DCMI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the DCMI pending flags.

Parameters:
__HANDLE__,: DCMI handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DCMI_FLAG_FRAMERI: Frame capture complete flag mask
  • DCMI_FLAG_OVFRI: Overflow flag mask
  • DCMI_FLAG_ERRRI: Synchronization error flag mask
  • DCMI_FLAG_VSYNCRI: VSYNC flag mask
  • DCMI_FLAG_LINERI: Line flag mask
Return values:
None

Definition at line 328 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))

Disable the DCMI.

Parameters:
__HANDLE__,: DCMI handle
Return values:
None

Definition at line 297 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Stop().

#define __HAL_DCMI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

Disable the specified DCMI interrupts.

Parameters:
__HANDLE__,: DCMI handle
__INTERRUPT__,: specifies the DCMI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
None

Definition at line 356 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)

Enable the DCMI.

Parameters:
__HANDLE__,: DCMI handle
Return values:
None

Definition at line 290 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define __HAL_DCMI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified DCMI interrupts.

Parameters:
__HANDLE__,: DCMI handle
__INTERRUPT__,: specifies the DCMI interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
None

Definition at line 342 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define __HAL_DCMI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
 (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))

Get the DCMI pending flags.

Parameters:
__HANDLE__,: DCMI handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DCMI_FLAG_FRAMERI: Frame capture complete flag mask
  • DCMI_FLAG_OVFRI: Overflow flag mask
  • DCMI_FLAG_ERRRI: Synchronization error flag mask
  • DCMI_FLAG_VSYNCRI: VSYNC flag mask
  • DCMI_FLAG_LINERI: Line flag mask
Return values:
The state of FLAG.

Definition at line 312 of file stm32f7xx_hal_dcmi.h.

Referenced by DCMI_DMAConvCplt(), and HAL_DCMI_IRQHandler().

#define __HAL_DCMI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))

Check whether the specified DCMI interrupt has occurred or not.

Parameters:
__HANDLE__,: DCMI handle
__INTERRUPT__,: specifies the DCMI interrupt source to check. This parameter can be one of the following values:
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
  • DCMI_IT_OVF: Overflow interrupt mask
  • DCMI_IT_ERR: Synchronization error interrupt mask
  • DCMI_IT_VSYNC: VSYNC interrupt mask
  • DCMI_IT_LINE: Line interrupt mask
Return values:
The state of INTERRUPT.

Definition at line 370 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_IRQHandler().

#define __HAL_DCMI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)

Reset DCMI handle state.

Parameters:
__HANDLE__,: specifies the DCMI handle.
Return values:
None

Definition at line 283 of file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI Private Macros

Defines
DCMI Private Macros
DCMI

Defines

#define | IS_DCMI_CAPTURE_MODE(MODE)
#define | IS_DCMI_SYNCHRO(MODE)
#define | IS_DCMI_PCKPOLARITY(POLARITY)
#define | IS_DCMI_VSPOLARITY(POLARITY)
#define | IS_DCMI_HSPOLARITY(POLARITY)
#define | IS_DCMI_MODE_JPEG(JPEG_MODE)
#define | IS_DCMI_CAPTURE_RATE(RATE)
#define | IS_DCMI_EXTENDED_DATA(DATA)
#define | IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define | IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)

Define Documentation

#define IS_DCMI_CAPTURE_MODE ( MODE )
Value:
(((MODE) == DCMI_MODE_CONTINUOUS) || \
                                   ((MODE) == DCMI_MODE_SNAPSHOT))

Definition at line 440 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Start_DMA().

#define IS_DCMI_CAPTURE_RATE ( RATE )
Value:
(((RATE) == DCMI_CR_ALL_FRAME)         || \
                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))

Definition at line 458 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_EXTENDED_DATA ( DATA )
Value:
(((DATA) == DCMI_EXTEND_DATA_8B)  || \
                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
                                    ((DATA) == DCMI_EXTEND_DATA_14B))

Definition at line 462 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_HSPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))

Definition at line 452 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_MODE_JPEG ( JPEG_MODE )
Value:
(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))

Definition at line 455 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_PCKPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))

Definition at line 446 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_SYNCHRO ( MODE )
Value:
(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))

Definition at line 443 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_VSPOLARITY ( POLARITY )
Value:
(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))

Definition at line 449 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_WINDOW_COORDINATE ( COORDINATE ) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)

Definition at line 467 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_ConfigCROP().

#define IS_DCMI_WINDOW_HEIGHT ( HEIGHT ) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)

Definition at line 469 of file stm32f7xx_hal_dcmi.h.

Referenced by HAL_DCMI_ConfigCROP().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI

Modules | Defines
DCMI
STM32F7xx_HAL_Driver

DCMI HAL module driver. More...

Modules

DCMI Exported Functions
DCMI Exported Types
DCMI Exported Constants
DCMI Exported Macros
DCMI Private Macros
DCMI Private Functions

Defines

#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */

Detailed Description

DCMI HAL module driver.

Define Documentation

#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */

Definition at line 108 of file stm32f7xx_hal_dcmi.c.

Referenced by HAL_DCMI_Stop().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
DCMIEx Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DCMI
      (+) De-initialize the DCMI

Function Documentation

HAL_StatusTypeDef HAL_DCMI_Init ( DCMI_HandleTypeDef * hdcmi )

Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.

Parameters:
hdcmi,: pointer to a DCMI_HandleTypeDef structure that contains the configuration information for DCMI.
Return values:
HAL status

Definition at line 100 of file stm32f7xx_hal_dcmi_ex.c.

References __HAL_DCMI_ENABLE, __HAL_DCMI_ENABLE_IT, assert_param, DCMI_InitTypeDef::ByteSelectMode, DCMI_InitTypeDef::ByteSelectStart, DCMI_InitTypeDef::CaptureRate, DCMI_IT_ERR, DCMI_IT_FRAME, DCMI_IT_LINE, DCMI_IT_OVF, DCMI_IT_VSYNC, DCMI_SYNCHRO_EMBEDDED, DCMI_HandleTypeDef::ErrorCode, DCMI_InitTypeDef::ExtendedDataMode, DCMI_CodesInitTypeDef::FrameEndCode, DCMI_CodesInitTypeDef::FrameStartCode, HAL_DCMI_ERROR_NONE, HAL_DCMI_MspInit(), HAL_DCMI_STATE_BUSY, HAL_DCMI_STATE_READY, HAL_DCMI_STATE_RESET, DCMI_InitTypeDef::HSPolarity, DCMI_HandleTypeDef::Init, DCMI_HandleTypeDef::Instance, IS_DCMI_BYTE_SELECT_MODE, IS_DCMI_BYTE_SELECT_START, IS_DCMI_CAPTURE_RATE, IS_DCMI_EXTENDED_DATA, IS_DCMI_HSPOLARITY, IS_DCMI_LINE_SELECT_MODE, IS_DCMI_LINE_SELECT_START, IS_DCMI_MODE_JPEG, IS_DCMI_PCKPOLARITY, IS_DCMI_SYNCHRO, IS_DCMI_VSPOLARITY, DCMI_InitTypeDef::JPEGMode, DCMI_CodesInitTypeDef::LineEndCode, DCMI_InitTypeDef::LineSelectMode, DCMI_InitTypeDef::LineSelectStart, DCMI_CodesInitTypeDef::LineStartCode, DCMI_InitTypeDef::PCKPolarity, DCMI_HandleTypeDef::State, DCMI_InitTypeDef::SynchroMode, DCMI_InitTypeDef::SyncroCode, and DCMI_InitTypeDef::VSPolarity.

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STM32F745xx HAL User Manual: DCMI_CodesInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_CodesInitTypeDef Struct Reference
DCMIEx Exported Types

DCMIEx Embedded Synchronisation CODE Init structure definition. More...

#include <stm32f7xx_hal_dcmi_ex.h>

Data Fields

uint8_t | FrameStartCode
uint8_t | LineStartCode
uint8_t | LineEndCode
uint8_t | FrameEndCode

Detailed Description

DCMIEx Embedded Synchronisation CODE Init structure definition.

Definition at line 67 of file stm32f7xx_hal_dcmi_ex.h.

Field Documentation

uint8_t DCMI_CodesInitTypeDef::FrameEndCode

Specifies the code of the frame end delimiter.

Definition at line 72 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::FrameStartCode

Specifies the code of the frame start delimiter.

Definition at line 69 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::LineEndCode

Specifies the code of the line end delimiter.

Definition at line 71 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint8_t DCMI_CodesInitTypeDef::LineStartCode

Specifies the code of the line start delimiter.

Definition at line 70 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dcmi_ex.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DCMI_InitTypeDef Struct Reference
DCMIEx Exported Types

DCMI Init structure definition. More...

#include <stm32f7xx_hal_dcmi_ex.h>

Data Fields

uint32_t | SynchroMode
uint32_t | PCKPolarity
uint32_t | VSPolarity
uint32_t | HSPolarity
uint32_t | CaptureRate
uint32_t | ExtendedDataMode
DCMI_CodesInitTypeDef SyncroCode
uint32_t | JPEGMode
uint32_t | ByteSelectMode
uint32_t | ByteSelectStart
uint32_t | LineSelectMode
uint32_t | LineSelectStart

Detailed Description

DCMI Init structure definition.

Definition at line 78 of file stm32f7xx_hal_dcmi_ex.h.

Field Documentation

uint32_t DCMI_InitTypeDef::ByteSelectMode

Specifies the data to be captured by the interface This parameter can be a value of DCMIEx Byte Select Mode

Definition at line 103 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::ByteSelectStart

Specifies if the data to be captured by the interface is even or odd This parameter can be a value of DCMIEx Byte Select Start

Definition at line 106 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::CaptureRate

Specifies the frequency of frame capture: All, 1/2 or 1/4. This parameter can be a value of DCMI Capture Rate

Definition at line 92 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::ExtendedDataMode

Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of DCMI Extended Data Mode

Definition at line 95 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::HSPolarity

Specifies the Horizontal synchronization polarity: High or Low. This parameter can be a value of DCMI HSYNC Polarity

Definition at line 89 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::JPEGMode

Enable or Disable the JPEG mode. This parameter can be a value of DCMI MODE JPEG

Definition at line 100 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::LineSelectMode

Specifies the line of data to be captured by the interface This parameter can be a value of DCMIEx Line Select Mode

Definition at line 109 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::LineSelectStart

Specifies if the line of data to be captured by the interface is even or odd This parameter can be a value of DCMIEx Line Select Start

Definition at line 112 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::PCKPolarity

Specifies the Pixel clock polarity: Falling or Rising. This parameter can be a value of DCMI PIXCK Polarity

Definition at line 83 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::SynchroMode

Specifies the Synchronization Mode: Hardware or Embedded. This parameter can be a value of DCMI Synchronization Mode

Definition at line 80 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

DCMI_CodesInitTypeDef DCMI_InitTypeDef::SyncroCode

Specifies the code of the frame start delimiter.

Definition at line 98 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

uint32_t DCMI_InitTypeDef::VSPolarity

Specifies the Vertical synchronization polarity: High or Low. This parameter can be a value of DCMI VSYNC Polarity

Definition at line 86 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dcmi_ex.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMIEx Byte Select Mode

Defines
DCMIEx Byte Select Mode
DCMIEx Exported Constants

Defines

#define | DCMI_BSM_ALL ((uint32_t)0x00000000)
#define | DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)
#define | DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)
#define | DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))

Define Documentation

#define DCMI_BSM_ALL ((uint32_t)0x00000000)

Interface captures all received data

Definition at line 128 of file stm32f7xx_hal_dcmi_ex.h.

#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))

Interface captures two bytes out of four

Definition at line 131 of file stm32f7xx_hal_dcmi_ex.h.

#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)

Interface captures one byte out of four

Definition at line 130 of file stm32f7xx_hal_dcmi_ex.h.

#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)

Interface captures every other byte from the received data

Definition at line 129 of file stm32f7xx_hal_dcmi_ex.h.

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STM32F745xx HAL User Manual: DCMIEx Byte Select Start

Defines
DCMIEx Byte Select Start
DCMIEx Exported Constants

Defines

#define | DCMI_OEBS_ODD ((uint32_t)0x00000000)
#define | DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)

Define Documentation

#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)

Interface captures second data from the frame/line start, first one being dropped

Definition at line 141 of file stm32f7xx_hal_dcmi_ex.h.

#define DCMI_OEBS_ODD ((uint32_t)0x00000000)

Interface captures first data from the frame/line start, second one being dropped

Definition at line 140 of file stm32f7xx_hal_dcmi_ex.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DCMIEx Line Select Mode

Defines
DCMIEx Line Select Mode
DCMIEx Exported Constants

Defines

#define | DCMI_LSM_ALL ((uint32_t)0x00000000)
#define | DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)

Define Documentation

#define DCMI_LSM_ALL ((uint32_t)0x00000000)

Interface captures all received lines

Definition at line 150 of file stm32f7xx_hal_dcmi_ex.h.

#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)

Interface captures one line out of two

Definition at line 151 of file stm32f7xx_hal_dcmi_ex.h.

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STM32F745xx HAL User Manual: DCMIEx Line Select Start

Defines
DCMIEx Line Select Start
DCMIEx Exported Constants

Defines

#define | DCMI_OELS_ODD ((uint32_t)0x00000000)
#define | DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)

Define Documentation

#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)

Interface captures second line from the frame start, first one being dropped

Definition at line 161 of file stm32f7xx_hal_dcmi_ex.h.

#define DCMI_OELS_ODD ((uint32_t)0x00000000)

Interface captures first line from the frame start, second one being dropped

Definition at line 160 of file stm32f7xx_hal_dcmi_ex.h.

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STM32F745xx HAL User Manual: DCMIEx Private Macros

Defines
DCMIEx Private Macros
DCMIEx

Defines

#define | IS_DCMI_BYTE_SELECT_MODE(MODE)
#define | IS_DCMI_BYTE_SELECT_START(POLARITY)
#define | IS_DCMI_LINE_SELECT_MODE(MODE)
#define | IS_DCMI_LINE_SELECT_START(POLARITY)

Define Documentation

#define IS_DCMI_BYTE_SELECT_MODE ( MODE )
Value:
(((MODE) == DCMI_BSM_ALL) || \
                                       ((MODE) == DCMI_BSM_OTHER) || \
                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \
                                       ((MODE) == DCMI_BSM_ALTERNATE_2))

Definition at line 180 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_BYTE_SELECT_START ( POLARITY )
Value:
(((POLARITY) == DCMI_OEBS_ODD) || \
                                            ((POLARITY) == DCMI_OEBS_EVEN))

Definition at line 185 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_LINE_SELECT_MODE ( MODE )
Value:
(((MODE) == DCMI_LSM_ALL) || \
                                       ((MODE) == DCMI_LSM_ALTERNATE_2))

Definition at line 188 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

#define IS_DCMI_LINE_SELECT_START ( POLARITY )
Value:
(((POLARITY) == DCMI_OELS_ODD) || \
                                            ((POLARITY) == DCMI_OELS_EVEN))

Definition at line 191 of file stm32f7xx_hal_dcmi_ex.h.

Referenced by HAL_DCMI_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

DMA Exported Types. More...

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00, HAL_DMA_STATE_READY = 0x01, HAL_DMA_STATE_READY_MEM0 = 0x11, HAL_DMA_STATE_READY_MEM1 = 0x21,
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, HAL_DMA_STATE_BUSY = 0x02, HAL_DMA_STATE_BUSY_MEM0 = 0x12,
HAL_DMA_STATE_BUSY_MEM1 = 0x22, HAL_DMA_STATE_TIMEOUT = 0x03, HAL_DMA_STATE_ERROR = 0x04
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00, HAL_DMA_HALF_TRANSFER = 0x01 }
HAL DMA Error Code structure definition. More...

Detailed Description

DMA Exported Types.

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 138 of file stm32f7xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_READY_MEM0

DMA Mem0 process success

HAL_DMA_STATE_READY_MEM1

DMA Mem1 process success

HAL_DMA_STATE_READY_HALF_MEM0

DMA Mem0 Half process success

HAL_DMA_STATE_READY_HALF_MEM1

DMA Mem1 Half process success

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_BUSY_MEM0

DMA Mem0 process is ongoing

HAL_DMA_STATE_BUSY_MEM1

DMA Mem1 process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

HAL_DMA_STATE_ERROR

DMA error state

Definition at line 120 of file stm32f7xx_hal_dma.h.

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STM32F745xx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32f7xx_hal_dma.h>

Data Fields

uint32_t | Channel
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority
uint32_t | FIFOMode
uint32_t | FIFOThreshold
uint32_t | MemBurst
uint32_t | PeriphBurst

Detailed Description

DMA Configuration Structure definition.

Definition at line 67 of file stm32f7xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Channel

Specifies the channel used for the specified stream. This parameter can be a value of DMA Channel selection

Definition at line 69 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 72 of file stm32f7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

uint32_t DMA_InitTypeDef::FIFOMode

Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of DMA FIFO direct mode

Note:
The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream

Definition at line 96 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::FIFOThreshold

Specifies the FIFO threshold level. This parameter can be a value of DMA FIFO threshold level

Definition at line 101 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemBurst

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Memory burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 104 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 85 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 79 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Streamx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream

Definition at line 88 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphBurst

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Peripheral burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 110 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 82 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 76 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Streamx. This parameter can be a value of DMA Priority level

Definition at line 93 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32f7xx_hal_dma.h>

Data Fields

DMA_Stream_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferM1CpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
uint32_t | StreamBaseAddress
uint32_t | StreamIndex

Detailed Description

DMA handle Structure definition.

Definition at line 147 of file stm32f7xx_hal_dma.h.

Field Documentation

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 167 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 151 of file stm32f7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

DMA_Stream_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 149 of file stm32f7xx_hal_dma.h.

Referenced by DCMI_DMAConvCplt(), DMA_CalcBaseAndBitshift(), DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ChangeMemory(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), I2S_DMARxCplt(), I2S_DMATxCplt(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPDIFRX_DMARxCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 153 of file stm32f7xx_hal_dma.h.

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 157 of file stm32f7xx_hal_dma.h.

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 155 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t __DMA_HandleTypeDef::StreamBaseAddress

DMA Stream Base Address

Definition at line 169 of file stm32f7xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

uint32_t __DMA_HandleTypeDef::StreamIndex

DMA Stream Index

Definition at line 171 of file stm32f7xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 159 of file stm32f7xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DCMI_Start_DMA(), HAL_DMA_IRQHandler(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 165 of file stm32f7xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DCMI_Start_DMA(), HAL_DMA_IRQHandler(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 161 of file stm32f7xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_IRQHandler(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete Memory1 callback

Definition at line 163 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DCMI_Start_DMA(), and HAL_DMA_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

DMA Error Code. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001)
#define | HAL_DMA_ERROR_FE ((uint32_t)0x00000002)
#define | HAL_DMA_ERROR_DME ((uint32_t)0x00000004)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020)

Detailed Description

DMA Error Code.

Define Documentation

#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004)

Direct Mode error

Definition at line 194 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002)

FIFO error

Definition at line 193 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 191 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), and HAL_DMA_IRQHandler().

#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001)

Transfer error

Definition at line 192 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020)

Timeout error

Definition at line 195 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), and HAL_DMA_PollForTransfer().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Channel selection

Defines
DMA Channel selection
DMA Exported Constants

DMA channel selection. More...

Defines

#define | DMA_CHANNEL_0 ((uint32_t)0x00000000)
#define | DMA_CHANNEL_1 ((uint32_t)0x02000000)
#define | DMA_CHANNEL_2 ((uint32_t)0x04000000)
#define | DMA_CHANNEL_3 ((uint32_t)0x06000000)
#define | DMA_CHANNEL_4 ((uint32_t)0x08000000)
#define | DMA_CHANNEL_5 ((uint32_t)0x0A000000)
#define | DMA_CHANNEL_6 ((uint32_t)0x0C000000)
#define | DMA_CHANNEL_7 ((uint32_t)0x0E000000)

Detailed Description

DMA channel selection.

Define Documentation

#define DMA_CHANNEL_0 ((uint32_t)0x00000000)

DMA Channel 0

Definition at line 204 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_1 ((uint32_t)0x02000000)

DMA Channel 1

Definition at line 205 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_2 ((uint32_t)0x04000000)

DMA Channel 2

Definition at line 206 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_3 ((uint32_t)0x06000000)

DMA Channel 3

Definition at line 207 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_4 ((uint32_t)0x08000000)

DMA Channel 4

Definition at line 208 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_5 ((uint32_t)0x0A000000)

DMA Channel 5

Definition at line 209 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_6 ((uint32_t)0x0C000000)

DMA Channel 6

Definition at line 210 of file stm32f7xx_hal_dma.h.

#define DMA_CHANNEL_7 ((uint32_t)0x0E000000)

DMA Channel 7

Definition at line 211 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

DMA data transfer direction. More...

Defines

#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Detailed Description

DMA data transfer direction.

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Memory to memory direction

Definition at line 222 of file stm32f7xx_hal_dma.h.

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)

Memory to peripheral direction

Definition at line 221 of file stm32f7xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), and HAL_QSPI_Transmit_DMA().

#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000)

Peripheral to memory direction

Definition at line 220 of file stm32f7xx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

DMA peripheral incremented mode. More...

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000)

Detailed Description

DMA peripheral incremented mode.

Define Documentation

#define DMA_PINC_DISABLE ((uint32_t)0x00000000)

Peripheral increment mode disable

Definition at line 232 of file stm32f7xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)

Peripheral increment mode enable

Definition at line 231 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

DMA memory incremented mode. More...

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000)

Detailed Description

DMA memory incremented mode.

Define Documentation

#define DMA_MINC_DISABLE ((uint32_t)0x00000000)

Memory increment mode disable

Definition at line 242 of file stm32f7xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)

Memory increment mode enable

Definition at line 241 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

DMA peripheral data size. More...

Defines

#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Detailed Description

DMA peripheral data size.

Define Documentation

#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000)

Peripheral data alignment: Byte

Definition at line 252 of file stm32f7xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)

Peripheral data alignment: HalfWord

Definition at line 253 of file stm32f7xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Peripheral data alignment: Word

Definition at line 254 of file stm32f7xx_hal_dma.h.

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STM32F745xx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

DMA memory data size. More...

Defines

#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Detailed Description

DMA memory data size.

Define Documentation

#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000)

Memory data alignment: Byte

Definition at line 264 of file stm32f7xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)

Memory data alignment: HalfWord

Definition at line 265 of file stm32f7xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Memory data alignment: Word

Definition at line 266 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

DMA mode. More...

Defines

#define | DMA_NORMAL ((uint32_t)0x00000000)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Detailed Description

DMA mode.

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)

Circular mode

Definition at line 276 of file stm32f7xx_hal_dma.h.

#define DMA_NORMAL ((uint32_t)0x00000000)

Normal mode

Definition at line 275 of file stm32f7xx_hal_dma.h.

#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Peripheral flow control mode

Definition at line 277 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

DMA priority levels. More...

Defines

#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Detailed Description

DMA priority levels.

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)

Priority level: High

Definition at line 289 of file stm32f7xx_hal_dma.h.

#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)

Priority level: Low

Definition at line 287 of file stm32f7xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)

Priority level: Medium

Definition at line 288 of file stm32f7xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Priority level: Very High

Definition at line 290 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA FIFO direct mode

Defines
DMA FIFO direct mode
DMA Exported Constants

DMA FIFO direct mode. More...

Defines

#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

Detailed Description

DMA FIFO direct mode.

Define Documentation

#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000)

FIFO mode disable

Definition at line 300 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

FIFO mode enable

Definition at line 301 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA FIFO threshold level

Defines
DMA FIFO threshold level
DMA Exported Constants

DMA FIFO level. More...

Defines

#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

Detailed Description

DMA FIFO level.

Define Documentation

#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000)

FIFO threshold 1 quart full configuration

Definition at line 310 of file stm32f7xx_hal_dma.h.

#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)

FIFO threshold 3 quarts full configuration

Definition at line 312 of file stm32f7xx_hal_dma.h.

#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

FIFO threshold full configuration

Definition at line 313 of file stm32f7xx_hal_dma.h.

#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)

FIFO threshold half full configuration

Definition at line 311 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Memory burst

Defines
DMA Memory burst
DMA Exported Constants

DMA memory burst. More...

Defines

#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Detailed Description

DMA memory burst.

Define Documentation

#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Definition at line 325 of file stm32f7xx_hal_dma.h.

#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)

Definition at line 323 of file stm32f7xx_hal_dma.h.

#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)

Definition at line 324 of file stm32f7xx_hal_dma.h.

#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)

Definition at line 322 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Peripheral burst

Defines
DMA Peripheral burst
DMA Exported Constants

DMA peripheral burst. More...

Defines

#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Detailed Description

DMA peripheral burst.

Define Documentation

#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Definition at line 338 of file stm32f7xx_hal_dma.h.

#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)

Definition at line 336 of file stm32f7xx_hal_dma.h.

#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)

Definition at line 337 of file stm32f7xx_hal_dma.h.

#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)

Definition at line 335 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

DMA interrupts definition. More...

Defines

#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080)

Detailed Description

DMA interrupts definition.

Define Documentation

#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)

Definition at line 350 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_FE ((uint32_t)0x00000080)

Definition at line 351 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)

Definition at line 348 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)

Definition at line 347 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)

Definition at line 349 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

DMA flag definitions. More...

Defines

#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)

Detailed Description

DMA flag definitions.

Define Documentation

#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)

Definition at line 361 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)

Definition at line 366 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)

Definition at line 371 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)

Definition at line 376 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)

Definition at line 360 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)

Definition at line 365 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)

Definition at line 370 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)

Definition at line 375 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)

Definition at line 363 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)

Definition at line 368 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)

Definition at line 373 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)

Definition at line 378 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)

Definition at line 364 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)

Definition at line 369 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)

Definition at line 374 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)

Definition at line 379 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)

Definition at line 362 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)

Definition at line 367 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)

Definition at line 372 of file stm32f7xx_hal_dma.h.

#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)

Definition at line 377 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Stream source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitializes the DMA peripheral.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 320 of file stm32f7xx_hal_dma.c.

References __HAL_DMA_DISABLE, DMA_CalcBaseAndBitshift(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_RESET, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 224 of file stm32f7xx_hal_dma.c.

References assert_param, DMA_InitTypeDef::Channel, DMA_InitTypeDef::Direction, DMA_CalcBaseAndBitshift(), DMA_FIFOMODE_DISABLE, DMA_FIFOMODE_ENABLE, __DMA_HandleTypeDef::ErrorCode, DMA_InitTypeDef::FIFOMode, DMA_InitTypeDef::FIFOThreshold, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_CHANNEL, IS_DMA_DIRECTION, IS_DMA_FIFO_MODE_STATE, IS_DMA_FIFO_THRESHOLD, IS_DMA_MEMORY_BURST, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_BURST, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, DMA_InitTypeDef::MemBurst, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphBurst, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, and __DMA_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I/O operation functions

Functions
I/O operation functions
DMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Note:
After disabling a DMA Stream, a check for wait until the DMA Stream is effectively disabled is added. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
Return values:
HAL status

Definition at line 477 of file stm32f7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_STATE_READY, HAL_DMA_STATE_TIMEOUT, HAL_GetTick(), HAL_TIMEOUT_DMA_ABORT, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_DAC_Stop_DMA(), HAL_DCMI_IRQHandler(), HAL_DCMI_Stop(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2S_DMAStop(), HAL_IRDA_DMAStop(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SPI_DMAStop(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_UART_DMAStop(), HAL_USART_DMAStop(), QSPI_DMARxCplt(), QSPI_DMATxCplt(), SD_DMA_RxCplt(), and SD_DMA_TxCplt().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMA interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 671 of file stm32f7xx_hal_dma.c.

References __HAL_DMA_DISABLE_IT, __HAL_DMA_GET_IT_SOURCE, DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_TE, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY_HALF_MEM0, HAL_DMA_STATE_READY_HALF_MEM1, HAL_DMA_STATE_READY_MEM0, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, DMA_Base_Registers::ISR, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __DMA_HandleTypeDef::XferM1CpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CompleteLevel,: Specifies the DMA level complete.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 522 of file stm32f7xx_hal_dma.c.

References DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY_HALF_MEM0, HAL_DMA_STATE_READY_HALF_MEM1, HAL_DMA_STATE_READY_MEM0, HAL_DMA_STATE_READY_MEM1, HAL_DMA_STATE_TIMEOUT, HAL_GetTick(), DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, DMA_Base_Registers::ISR, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 406 of file stm32f7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), HAL_DMA_STATE_BUSY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 438 of file stm32f7xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), HAL_DMA_STATE_BUSY, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DCMI_Start_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_Write_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), and I2C_DMAMemTransmitCplt().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DMA Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
DMA Error Code

Definition at line 901 of file stm32f7xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Returns the DMA state.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL state

Definition at line 890 of file stm32f7xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Exported Functions

Modules | Functions
DMA Exported Functions
DMA

DMA Exported functions. More...

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

I/O operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

Functions

static uint32_t DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.

Detailed Description

DMA Exported functions.

Function Documentation

static uint32_t DMA_CalcBaseAndBitshift ( DMA_HandleTypeDef * hdma ) [static]

Returns the DMA Stream base address depending on stream number.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
Stream base address

Definition at line 916 of file stm32f7xx_hal_dma.c.

References __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Private Constants

Defines
DMA Private Constants
DMA

DMA private defines and constants. More...

Defines

#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */

Detailed Description

DMA private defines and constants.

Define Documentation

#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */

Definition at line 141 of file stm32f7xx_hal_dma.c.

Referenced by HAL_DMA_Abort().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

DMA private macros. More...

Defines

#define | IS_DMA_CHANNEL(CHANNEL)
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Detailed Description

DMA private macros.

Define Documentation

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

Definition at line 708 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define IS_DMA_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DMA_CHANNEL_0) || \
                                 ((CHANNEL) == DMA_CHANNEL_1) || \
                                 ((CHANNEL) == DMA_CHANNEL_2) || \
                                 ((CHANNEL) == DMA_CHANNEL_3) || \
                                 ((CHANNEL) == DMA_CHANNEL_4) || \
                                 ((CHANNEL) == DMA_CHANNEL_5) || \
                                 ((CHANNEL) == DMA_CHANNEL_6) || \
                                 ((CHANNEL) == DMA_CHANNEL_7))

Definition at line 695 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 704 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_MODE_STATE ( STATE )
Value:
(((STATE) == DMA_FIFOMODE_DISABLE ) || \
                                       ((STATE) == DMA_FIFOMODE_ENABLE))

Definition at line 733 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))

Definition at line 736 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_BURST ( BURST )
Value:
(((BURST) == DMA_MBURST_SINGLE) || \
                                    ((BURST) == DMA_MBURST_INC4)   || \
                                    ((BURST) == DMA_MBURST_INC8)   || \
                                    ((BURST) == DMA_MBURST_INC16))

Definition at line 741 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 720 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 713 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR) || \
                           ((MODE) == DMA_PFCTRL))

Definition at line 724 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_BURST ( BURST )
Value:
(((BURST) == DMA_PBURST_SINGLE) || \
                                        ((BURST) == DMA_PBURST_INC4)   || \
                                        ((BURST) == DMA_PBURST_INC8)   || \
                                        ((BURST) == DMA_PBURST_INC16))

Definition at line 746 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 716 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 710 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 728 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

DMA private functions. More...

Functions

static void DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.

Detailed Description

DMA private functions.

Function Documentation

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 162 of file stm32f7xx_hal_dma.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA

Data Structures | Modules | Defines
DMA
STM32F7xx_HAL_Driver

DMA HAL module driver. More...

Data Structures

struct | DMA_Base_Registers

Modules

DMA Exported Types

DMA Exported Types.

DMA Exported Constants

DMA Exported constants.

DMA Exported Functions

DMA Exported functions.

DMA Private Constants

DMA private defines and constants.

DMA Private Macros

DMA private macros.

DMA Private Functions

DMA private functions.

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or not.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Returns the number of remaining data units in the current DMAy Streamx transfer.

Detailed Description

DMA HAL module driver.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))

Clear the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
None

Definition at line 557 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)

Disable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 422 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_I2S_DMAStop(), and HAL_SPDIFRX_DMAStop().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))

Disable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 589 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)

Enable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 415 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))

Enable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 574 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->NDTR)

Returns the number of remaining data units in the current DMAy Streamx transfer.

Parameters:
__HANDLE__,: DMA handle
Return values:
The number of remaining data units in the current DMA Stream transfer.

Definition at line 633 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_DME_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
   DMA_FLAG_DMEIF3_7)

Return the current DMA Stream direct mode error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified direct mode error flag index.

Definition at line 511 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_FE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
   DMA_FLAG_FEIF3_7)

Return the current DMA Stream FIFO error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified FIFO error flag index.

Definition at line 491 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))

Get the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 539 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_FS ( __HANDLE__ ) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))

Return the current DMA Stream FIFO filled level.

Parameters:
__HANDLE__,: DMA handle
Return values:
The FIFO filling state.
  • DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
  • DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
  • DMA_FIFOStatus_HalfFull: if more than 1 half-full.
  • DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
  • DMA_FIFOStatus_Empty: when FIFO is empty
  • DMA_FIFOStatus_Full: when FIFO is full

Definition at line 408 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
   DMA_FLAG_HTIF3_7)

Return the current DMA Stream half transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 451 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))

Check whether the specified DMA Stream interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
The state of DMA_IT.

Definition at line 604 of file stm32f7xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
   DMA_FLAG_TCIF3_7)

Return the current DMA Stream transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 431 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
   DMA_FLAG_TEIF3_7)

Return the current DMA Stream transfer error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 471 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__,: specifies the DMA handle.
Return values:
None

Definition at line 394 of file stm32f7xx_hal_dma.h.

#define __HAL_DMA_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))

Writes the number of data units to be transferred on the DMA Stream.

Parameters:
__HANDLE__,: DMA handle
__COUNTER__,: Number of data units to be transferred (from 0 to 65535) Number of data items depends only on the Peripheral data format.
Note:
If Peripheral data format is Bytes: number of data units is equal to total number of bytes to be transferred.
If Peripheral data format is Half-Word: number of data units is equal to total number of bytes to be transferred / 2.
If Peripheral data format is Word: number of data units is equal to total number of bytes to be transferred / 4.
Return values:
The number of remaining data units in the current DMAy Streamx transfer.

Definition at line 625 of file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA_Base_Registers Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_Base_Registers Struct Reference
DMA

Data Fields

__IO uint32_t | ISR
__IO uint32_t | Reserved0
__IO uint32_t | IFCR

Detailed Description

Definition at line 129 of file stm32f7xx_hal_dma.c.

Field Documentation

__IO uint32_t DMA_Base_Registers::IFCR

DMA interrupt flag clear register

Definition at line 133 of file stm32f7xx_hal_dma.c.

Referenced by HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t DMA_Base_Registers::ISR

DMA interrupt status register

Definition at line 131 of file stm32f7xx_hal_dma.c.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t DMA_Base_Registers::Reserved0

Definition at line 132 of file stm32f7xx_hal_dma.c.

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma.c
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D Exported Types

Data Structures | Defines | Typedefs | Enumerations
DMA2D Exported Types
DMA2D

Data Structures

struct | DMA2D_ColorTypeDef
DMA2D color Structure definition. More...
struct | DMA2D_CLUTCfgTypeDef
DMA2D CLUT Structure definition. More...
struct | DMA2D_InitTypeDef
DMA2D Init structure definition. More...
struct | DMA2D_LayerCfgTypeDef
DMA2D Layer structure definition. More...
struct | __DMA2D_HandleTypeDef
DMA2D handle Structure definition. More...

Defines

#define | MAX_DMA2D_LAYER 2

Typedefs

typedef struct
__DMA2D_HandleTypeDef 		DMA2D_HandleTypeDef
DMA2D handle Structure definition.

Enumerations

enum HAL_DMA2D_StateTypeDef {
HAL_DMA2D_STATE_RESET = 0x00, HAL_DMA2D_STATE_READY = 0x01, HAL_DMA2D_STATE_BUSY = 0x02, HAL_DMA2D_STATE_TIMEOUT = 0x03,
HAL_DMA2D_STATE_ERROR = 0x04, HAL_DMA2D_STATE_SUSPEND = 0x05
}
HAL DMA2D State structures definition. More...

Define Documentation

#define MAX_DMA2D_LAYER 2

Definition at line 62 of file stm32f7xx_hal_dma2d.h.

Typedef Documentation

typedef struct __DMA2D_HandleTypeDef DMA2D_HandleTypeDef

DMA2D handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA2D_StateTypeDef

HAL DMA2D State structures definition.

Enumerator:
HAL_DMA2D_STATE_RESET

DMA2D not yet initialized or disabled

HAL_DMA2D_STATE_READY

Peripheral Initialized and ready for use

HAL_DMA2D_STATE_BUSY

an internal process is ongoing

HAL_DMA2D_STATE_TIMEOUT

Timeout state

HAL_DMA2D_STATE_ERROR

DMA2D state error

HAL_DMA2D_STATE_SUSPEND

DMA2D process is suspended

Definition at line 132 of file stm32f7xx_hal_dma2d.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D_ColorTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_ColorTypeDef Struct Reference
DMA2D Exported Types

DMA2D color Structure definition. More...

#include <stm32f7xx_hal_dma2d.h>

Data Fields

uint32_t | Blue
uint32_t | Green
uint32_t | Red

Detailed Description

DMA2D color Structure definition.

Definition at line 67 of file stm32f7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_ColorTypeDef::Blue

Configures the blue value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 69 of file stm32f7xx_hal_dma2d.h.

uint32_t DMA2D_ColorTypeDef::Green

Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 72 of file stm32f7xx_hal_dma2d.h.

uint32_t DMA2D_ColorTypeDef::Red

Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 75 of file stm32f7xx_hal_dma2d.h.

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma2d.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D_CLUTCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_CLUTCfgTypeDef Struct Reference
DMA2D Exported Types

DMA2D CLUT Structure definition. More...

#include <stm32f7xx_hal_dma2d.h>

Data Fields

uint32_t * | pCLUT
uint32_t | CLUTColorMode
uint32_t | Size

Detailed Description

DMA2D CLUT Structure definition.

Definition at line 82 of file stm32f7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_CLUTCfgTypeDef::CLUTColorMode

configures the DMA2D CLUT color mode. This parameter can be one value of DMA2D CLUT CM

Definition at line 86 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigCLUT().

uint32_t* DMA2D_CLUTCfgTypeDef::pCLUT

Configures the DMA2D CLUT memory address.

Definition at line 84 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigCLUT().

uint32_t DMA2D_CLUTCfgTypeDef::Size

configures the DMA2D CLUT size. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 89 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigCLUT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma2d.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_InitTypeDef Struct Reference
DMA2D Exported Types

DMA2D Init structure definition. More...

#include <stm32f7xx_hal_dma2d.h>

Data Fields

uint32_t | Mode
uint32_t | ColorMode
uint32_t | OutputOffset

Detailed Description

DMA2D Init structure definition.

Definition at line 96 of file stm32f7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_InitTypeDef::ColorMode

configures the color format of the output image. This parameter can be one value of DMA2D Color Mode

Definition at line 101 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), and HAL_DMA2D_Init().

uint32_t DMA2D_InitTypeDef::Mode

configures the DMA2D transfer mode. This parameter can be one value of DMA2D Mode

Definition at line 98 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), HAL_DMA2D_ConfigLayer(), and HAL_DMA2D_Init().

uint32_t DMA2D_InitTypeDef::OutputOffset

Specifies the Offset value. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

Definition at line 104 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma2d.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D_LayerCfgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA2D_LayerCfgTypeDef Struct Reference
DMA2D Exported Types

DMA2D Layer structure definition. More...

#include <stm32f7xx_hal_dma2d.h>

Data Fields

uint32_t | InputOffset
uint32_t | InputColorMode
uint32_t | AlphaMode
uint32_t | InputAlpha

Detailed Description

DMA2D Layer structure definition.

Definition at line 111 of file stm32f7xx_hal_dma2d.h.

Field Documentation

uint32_t DMA2D_LayerCfgTypeDef::AlphaMode

configures the DMA2D foreground alpha mode. This parameter can be one value of DMA2D ALPHA MODE

Definition at line 119 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::InputAlpha

Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode. This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF in case of A8 or A4 color mode (ARGB). Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

Definition at line 122 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::InputColorMode

configures the DMA2D foreground color mode . This parameter can be one value of DMA2D Input Color Mode

Definition at line 116 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

uint32_t DMA2D_LayerCfgTypeDef::InputOffset

configures the DMA2D foreground offset. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

Definition at line 113 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma2d.h
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STM32F745xx HAL User Manual: __DMA2D_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA2D_HandleTypeDef Struct Reference
DMA2D Exported Types

DMA2D handle Structure definition. More...

#include <stm32f7xx_hal_dma2d.h>

Data Fields

DMA2D_TypeDef * | Instance
DMA2D_InitTypeDef Init
void(* | XferCpltCallback )(struct __DMA2D_HandleTypeDef *hdma2d)
void(* | XferErrorCallback )(struct __DMA2D_HandleTypeDef *hdma2d)
DMA2D_LayerCfgTypeDef LayerCfg [MAX_DMA2D_LAYER]
HAL_LockTypeDef | Lock
__IO HAL_DMA2D_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

DMA2D handle Structure definition.

Definition at line 145 of file stm32f7xx_hal_dma2d.h.

Field Documentation

__IO uint32_t __DMA2D_HandleTypeDef::ErrorCode

DMA2D Error code

Definition at line 161 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_DeInit(), HAL_DMA2D_GetError(), HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), HAL_DMA2D_PollForTransfer(), and HAL_DMA2D_Suspend().

DMA2D_InitTypeDef __DMA2D_HandleTypeDef::Init

DMA2D communication parameters

Definition at line 149 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), HAL_DMA2D_ConfigLayer(), and HAL_DMA2D_Init().

DMA2D_TypeDef* __DMA2D_HandleTypeDef::Instance

DMA2D Register base address

Definition at line 147 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_DisableCLUT(), HAL_DMA2D_EnableCLUT(), HAL_DMA2D_Init(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_Resume(), and HAL_DMA2D_Suspend().

DMA2D_LayerCfgTypeDef __DMA2D_HandleTypeDef::LayerCfg[MAX_DMA2D_LAYER]

DMA2D Layers parameters

Definition at line 155 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

HAL_LockTypeDef __DMA2D_HandleTypeDef::Lock

DMA2D Lock

Definition at line 157 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

__IO HAL_DMA2D_StateTypeDef __DMA2D_HandleTypeDef::State

DMA2D transfer state

Definition at line 159 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_DeInit(), HAL_DMA2D_GetState(), HAL_DMA2D_Init(), HAL_DMA2D_IRQHandler(), HAL_DMA2D_PollForTransfer(), HAL_DMA2D_ProgramLineEvent(), HAL_DMA2D_Resume(), HAL_DMA2D_Start(), HAL_DMA2D_Start_IT(), and HAL_DMA2D_Suspend().

void(* __DMA2D_HandleTypeDef::XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d)

DMA2D transfer complete callback

Definition at line 151 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

void(* __DMA2D_HandleTypeDef::XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d)

DMA2D transfer error callback

Definition at line 153 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_dma2d.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D Error Code

Defines
DMA2D Error Code
DMA2D Exported Constants

Defines

#define | HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001)
#define | HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002)
#define | HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020)

Define Documentation

#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002)

Configuration error

Definition at line 177 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 175 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_DeInit(), HAL_DMA2D_Init(), and HAL_DMA2D_IRQHandler().

#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001)

Transfer error

Definition at line 176 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020)

Timeout error

Definition at line 178 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_PollForTransfer(), and HAL_DMA2D_Suspend().

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STM32F745xx HAL User Manual: DMA2D Mode

Defines
DMA2D Mode
DMA2D Exported Constants

Defines

#define | DMA2D_M2M ((uint32_t)0x00000000)
#define | DMA2D_M2M_PFC ((uint32_t)0x00010000)
#define | DMA2D_M2M_BLEND ((uint32_t)0x00020000)
#define | DMA2D_R2M ((uint32_t)0x00030000)

Define Documentation

#define DMA2D_M2M ((uint32_t)0x00000000)

DMA2D memory to memory transfer mode

Definition at line 186 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define DMA2D_M2M_BLEND ((uint32_t)0x00020000)

DMA2D memory to memory with blending transfer mode

Definition at line 188 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_M2M_PFC ((uint32_t)0x00010000)

DMA2D memory to memory with pixel format conversion transfer mode

Definition at line 187 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_R2M ((uint32_t)0x00030000)

DMA2D register to memory transfer mode

Definition at line 189 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig(), and HAL_DMA2D_ConfigLayer().

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STM32F745xx HAL User Manual: DMA2D Color Mode

Defines
DMA2D Color Mode
DMA2D Exported Constants

Defines

#define | DMA2D_ARGB8888 ((uint32_t)0x00000000)
#define | DMA2D_RGB888 ((uint32_t)0x00000001)
#define | DMA2D_RGB565 ((uint32_t)0x00000002)
#define | DMA2D_ARGB1555 ((uint32_t)0x00000003)
#define | DMA2D_ARGB4444 ((uint32_t)0x00000004)

Define Documentation

#define DMA2D_ARGB1555 ((uint32_t)0x00000003)

ARGB1555 DMA2D color mode

Definition at line 200 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

#define DMA2D_ARGB4444 ((uint32_t)0x00000004)

ARGB4444 DMA2D color mode

Definition at line 201 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_ARGB8888 ((uint32_t)0x00000000)

ARGB8888 DMA2D color mode

Definition at line 197 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

#define DMA2D_RGB565 ((uint32_t)0x00000002)

RGB565 DMA2D color mode

Definition at line 199 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

#define DMA2D_RGB888 ((uint32_t)0x00000001)

RGB888 DMA2D color mode

Definition at line 198 of file stm32f7xx_hal_dma2d.h.

Referenced by DMA2D_SetConfig().

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STM32F745xx HAL User Manual: DMA2D COLOR VALUE

Defines
DMA2D COLOR VALUE
DMA2D Exported Constants

Defines

#define COLOR_VALUE ((uint32_t)0x000000FF)

Define Documentation

#define COLOR_VALUE ((uint32_t)0x000000FF)

color value mask

Definition at line 209 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D SIZE

Defines
DMA2D SIZE
DMA2D Exported Constants

Defines

#define | DMA2D_PIXEL (DMA2D_NLR_PL >> 16)
#define | DMA2D_LINE DMA2D_NLR_NL

Define Documentation

#define DMA2D_LINE DMA2D_NLR_NL

DMA2D number of line

Definition at line 218 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16)

DMA2D pixel per line

Definition at line 217 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D Offset

Defines
DMA2D Offset
DMA2D Exported Constants

Defines

#define DMA2D_OFFSET DMA2D_FGOR_LO

Define Documentation

#define DMA2D_OFFSET DMA2D_FGOR_LO

Line Offset

Definition at line 226 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D Input Color Mode

Defines
DMA2D Input Color Mode
DMA2D Exported Constants

Defines

#define | CM_ARGB8888 ((uint32_t)0x00000000)
#define | CM_RGB888 ((uint32_t)0x00000001)
#define | CM_RGB565 ((uint32_t)0x00000002)
#define | CM_ARGB1555 ((uint32_t)0x00000003)
#define | CM_ARGB4444 ((uint32_t)0x00000004)
#define | CM_L8 ((uint32_t)0x00000005)
#define | CM_AL44 ((uint32_t)0x00000006)
#define | CM_AL88 ((uint32_t)0x00000007)
#define | CM_L4 ((uint32_t)0x00000008)
#define | CM_A8 ((uint32_t)0x00000009)
#define | CM_A4 ((uint32_t)0x0000000A)

Define Documentation

#define CM_A4 ((uint32_t)0x0000000A)

A4 color mode

Definition at line 244 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define CM_A8 ((uint32_t)0x00000009)

A8 color mode

Definition at line 243 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define CM_AL44 ((uint32_t)0x00000006)

AL44 color mode

Definition at line 240 of file stm32f7xx_hal_dma2d.h.

#define CM_AL88 ((uint32_t)0x00000007)

AL88 color mode

Definition at line 241 of file stm32f7xx_hal_dma2d.h.

#define CM_ARGB1555 ((uint32_t)0x00000003)

ARGB1555 color mode

Definition at line 237 of file stm32f7xx_hal_dma2d.h.

#define CM_ARGB4444 ((uint32_t)0x00000004)

ARGB4444 color mode

Definition at line 238 of file stm32f7xx_hal_dma2d.h.

#define CM_ARGB8888 ((uint32_t)0x00000000)

ARGB8888 color mode

Definition at line 234 of file stm32f7xx_hal_dma2d.h.

#define CM_L4 ((uint32_t)0x00000008)

L4 color mode

Definition at line 242 of file stm32f7xx_hal_dma2d.h.

#define CM_L8 ((uint32_t)0x00000005)

L8 color mode

Definition at line 239 of file stm32f7xx_hal_dma2d.h.

#define CM_RGB565 ((uint32_t)0x00000002)

RGB565 color mode

Definition at line 236 of file stm32f7xx_hal_dma2d.h.

#define CM_RGB888 ((uint32_t)0x00000001)

RGB888 color mode

Definition at line 235 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D ALPHA MODE

Defines
DMA2D ALPHA MODE
DMA2D Exported Constants

Defines

#define | DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000)
#define | DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001)
#define | DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002)

Define Documentation

#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002)

Replace original alpha channel value by programmed alpha value with original alpha channel value

Definition at line 254 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000)

No modification of the alpha channel value

Definition at line 252 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001)

Replace original alpha channel value by programmed alpha value

Definition at line 253 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D CLUT CM

Defines
DMA2D CLUT CM
DMA2D Exported Constants

Defines

#define | DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000)
#define | DMA2D_CCM_RGB888 ((uint32_t)0x00000001)

Define Documentation

#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000)

ARGB8888 DMA2D C-LUT color mode

Definition at line 263 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001)

RGB888 DMA2D C-LUT color mode

Definition at line 264 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D Size Clut

Defines
DMA2D Size Clut
DMA2D Exported Constants

Defines

#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8)

Define Documentation

#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8)

DMA2D C-LUT size

Definition at line 272 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D DeadTime

Defines
DMA2D DeadTime
DMA2D Exported Constants

Defines

#define LINE_WATERMARK DMA2D_LWR_LW

Define Documentation

#define LINE_WATERMARK DMA2D_LWR_LW

Definition at line 280 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D Interrupts

Defines
DMA2D Interrupts
DMA2D Exported Constants

Defines

#define | DMA2D_IT_CE DMA2D_CR_CEIE
#define | DMA2D_IT_CTC DMA2D_CR_CTCIE
#define | DMA2D_IT_CAE DMA2D_CR_CAEIE
#define | DMA2D_IT_TW DMA2D_CR_TWIE
#define | DMA2D_IT_TC DMA2D_CR_TCIE
#define | DMA2D_IT_TE DMA2D_CR_TEIE

Define Documentation

#define DMA2D_IT_CAE DMA2D_CR_CAEIE

C-LUT Access Error Interrupt

Definition at line 290 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_IT_CE DMA2D_CR_CEIE

Configuration Error Interrupt

Definition at line 288 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_Start_IT().

#define DMA2D_IT_CTC DMA2D_CR_CTCIE

C-LUT Transfer Complete Interrupt

Definition at line 289 of file stm32f7xx_hal_dma2d.h.

#define DMA2D_IT_TC DMA2D_CR_TCIE

Transfer Complete Interrupt

Definition at line 292 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_Start_IT().

#define DMA2D_IT_TE DMA2D_CR_TEIE

Transfer Error Interrupt

Definition at line 293 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_IRQHandler(), and HAL_DMA2D_Start_IT().

#define DMA2D_IT_TW DMA2D_CR_TWIE

Transfer Watermark Interrupt

Definition at line 291 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D Flag

Defines
DMA2D Flag
DMA2D Exported Constants

Defines

#define | DMA2D_FLAG_CE DMA2D_ISR_CEIF
#define | DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
#define | DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
#define | DMA2D_FLAG_TW DMA2D_ISR_TWIF
#define | DMA2D_FLAG_TC DMA2D_ISR_TCIF
#define | DMA2D_FLAG_TE DMA2D_ISR_TEIF

Define Documentation

#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF

C-LUT Access Error Interrupt Flag

Definition at line 303 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_CE DMA2D_ISR_CEIF

Configuration Error Interrupt Flag

Definition at line 301 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF

C-LUT Transfer Complete Interrupt Flag

Definition at line 302 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_TC DMA2D_ISR_TCIF

Transfer Complete Interrupt Flag

Definition at line 305 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_TE DMA2D_ISR_TEIF

Transfer Error Interrupt Flag

Definition at line 306 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define DMA2D_FLAG_TW DMA2D_ISR_TWIF

Transfer Watermark Interrupt Flag

Definition at line 304 of file stm32f7xx_hal_dma2d.h.

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STM32F745xx HAL User Manual: DMA2D Exported Macros

Defines
DMA2D Exported Macros
DMA2D

Defines

#define | __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
Reset DMA2D handle state.
#define | __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
Enable the DMA2D.
#define | __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
Disable the DMA2D.
#define | __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the DMA2D pending flags.
#define | __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
Clears the DMA2D pending flags.
#define | __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enables the specified DMA2D interrupts.
#define | __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disables the specified DMA2D interrupts.
#define | __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Checks whether the specified DMA2D interrupt has occurred or not.

Define Documentation

#define __HAL_DMA2D_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->IFCR = (__FLAG__))

Clears the DMA2D pending flags.

Parameters:
__HANDLE__,: DMA2D handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA2D_FLAG_CE: Configuration error flag
  • DMA2D_FLAG_CTC: C-LUT transfer complete flag
  • DMA2D_FLAG_CAE: C-LUT access error flag
  • DMA2D_FLAG_TW: Transfer Watermark flag
  • DMA2D_FLAG_TC: Transfer complete flag
  • DMA2D_FLAG_TE: Transfer error flag
Return values:
None

Definition at line 368 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define __HAL_DMA2D_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)

Disable the DMA2D.

Parameters:
__HANDLE__,: DMA2D handle
Return values:
None.

Definition at line 337 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Abort(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

#define __HAL_DMA2D_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disables the specified DMA2D interrupts.

Parameters:
__HANDLE__,: DMA2D handle
__INTERRUPT__,: specifies the DMA2D interrupt sources to be disabled. This parameter can be any combination of the following values:
  • DMA2D_IT_CE: Configuration error interrupt mask
  • DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
  • DMA2D_IT_CAE: C-LUT access error interrupt mask
  • DMA2D_IT_TW: Transfer Watermark interrupt mask
  • DMA2D_IT_TC: Transfer complete interrupt mask
  • DMA2D_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 398 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

#define __HAL_DMA2D_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)

Enable the DMA2D.

Parameters:
__HANDLE__,: DMA2D handle
Return values:
None.

Definition at line 330 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

#define __HAL_DMA2D_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enables the specified DMA2D interrupts.

Parameters:
__HANDLE__,: DMA2D handle
__INTERRUPT__,: specifies the DMA2D interrupt sources to be enabled. This parameter can be any combination of the following values:
  • DMA2D_IT_CE: Configuration error interrupt mask
  • DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
  • DMA2D_IT_CAE: C-LUT access error interrupt mask
  • DMA2D_IT_TW: Transfer Watermark interrupt mask
  • DMA2D_IT_TC: Transfer complete interrupt mask
  • DMA2D_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 383 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart_IT(), and HAL_DMA2D_Start_IT().

#define __HAL_DMA2D_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Get the DMA2D pending flags.

Parameters:
__HANDLE__,: DMA2D handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA2D_FLAG_CE: Configuration error flag
  • DMA2D_FLAG_CTC: C-LUT transfer complete flag
  • DMA2D_FLAG_CAE: C-LUT access error flag
  • DMA2D_FLAG_TW: Transfer Watermark flag
  • DMA2D_FLAG_TC: Transfer complete flag
  • DMA2D_FLAG_TE: Transfer error flag
Return values:
The state of FLAG.

Definition at line 353 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler(), and HAL_DMA2D_PollForTransfer().

#define __HAL_DMA2D_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

Checks whether the specified DMA2D interrupt has occurred or not.

Parameters:
__HANDLE__,: DMA2D handle
__INTERRUPT__,: specifies the DMA2D interrupt source to check. This parameter can be one of the following values:
  • DMA2D_IT_CE: Configuration error interrupt mask
  • DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
  • DMA2D_IT_CAE: C-LUT access error interrupt mask
  • DMA2D_IT_TW: Transfer Watermark interrupt mask
  • DMA2D_IT_TC: Transfer complete interrupt mask
  • DMA2D_IT_TE: Transfer error interrupt mask
Return values:
The state of INTERRUPT.

Definition at line 413 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_IRQHandler().

#define __HAL_DMA2D_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)

Reset DMA2D handle state.

Parameters:
__HANDLE__,: specifies the DMA2D handle.
Return values:
None

Definition at line 323 of file stm32f7xx_hal_dma2d.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
DMA2D Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DMA2D
      (+) De-initialize the DMA2D

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_DeInit ( DMA2D_HandleTypeDef * hdma2d )

Deinitializes the DMA2D peripheral registers to their default reset values.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 264 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_MspDeInit(), HAL_DMA2D_STATE_RESET, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Init ( DMA2D_HandleTypeDef * hdma2d )

Initializes the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 181 of file stm32f7xx_hal_dma2d.c.

References assert_param, DMA2D_InitTypeDef::ColorMode, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_MspInit(), HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_RESET, __DMA2D_HandleTypeDef::Init, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CMODE, IS_DMA2D_MODE, IS_DMA2D_OFFSET, __DMA2D_HandleTypeDef::Lock, DMA2D_InitTypeDef::Mode, DMA2D_InitTypeDef::OutputOffset, and __DMA2D_HandleTypeDef::State.

__weak void HAL_DMA2D_MspDeInit ( DMA2D_HandleTypeDef * hdma2d )

DeInitializes the DMA2D MSP.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 309 of file stm32f7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_DeInit().

__weak void HAL_DMA2D_MspInit ( DMA2D_HandleTypeDef * hdma2d )

Initializes the DMA2D MSP.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 293 of file stm32f7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
DMA2D Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handles DMA2D interrupt request.

Detailed Description

IO operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the pdata, destination address and data size and
          Start DMA2D transfer.
      (+) Configure the source for foreground and background, destination address
          and data size and Start MultiBuffer DMA2D transfer.
      (+) Configure the pdata, destination address and data size and
          Start DMA2D transfer with interrupt.
      (+) Configure the source for foreground and background, destination address
          and data size and Start MultiBuffer DMA2D transfer with interrupt.
      (+) Abort DMA2D transfer.
      (+) Suspend DMA2D transfer.
      (+) Continue DMA2D transfer.
      (+) Poll for transfer complete.
      (+) handle DMA2D interrupt request.

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_Abort ( DMA2D_HandleTypeDef * hdma2d )

Abort the DMA2D Transfer.

Parameters:
hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 523 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), HAL_TIMEOUT_DMA2D_ABORT, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_BlendingStart | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1,: The source memory Buffer address of the foreground layer.
SrcAddress2,: The source memory Buffer address of the background layer.
DstAddress,: The destination memory Buffer address
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 443 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, assert_param, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1,: The source memory Buffer address of the foreground layer.
SrcAddress2,: The source memory Buffer address of the background layer.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 481 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

void HAL_DMA2D_IRQHandler ( DMA2D_HandleTypeDef * hdma2d )

Handles DMA2D interrupt request.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 722 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_CLEAR_FLAG, __HAL_DMA2D_DISABLE_IT, __HAL_DMA2D_GET_FLAG, __HAL_DMA2D_GET_IT_SOURCE, DMA2D_FLAG_CE, DMA2D_FLAG_TC, DMA2D_FLAG_TE, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_CE, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_ERROR_TE, HAL_DMA2D_STATE_ERROR, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::State, __DMA2D_HandleTypeDef::XferCpltCallback, and __DMA2D_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_DMA2D_PollForTransfer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete or CLUT loading.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 619 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_CLEAR_FLAG, __HAL_DMA2D_GET_FLAG, DMA2D_FLAG_CAE, DMA2D_FLAG_CE, DMA2D_FLAG_CTC, DMA2D_FLAG_TC, DMA2D_FLAG_TE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_ERROR, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Resume ( DMA2D_HandleTypeDef * hdma2d )

Resume the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 601 of file stm32f7xx_hal_dma2d.c.

References HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Start | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata,: Configure the source memory Buffer address if the memory to memory or memory to memory with pixel format conversion DMA2D mode is selected, and configure the color value if register to memory DMA2D mode is selected.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 362 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, assert_param, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Start_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata,: Configure the source memory Buffer address if the memory to memory or memory to memory with pixel format conversion DMA2D mode is selected, and configure the color value if register to memory DMA2D mode is selected.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 399 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Suspend ( DMA2D_HandleTypeDef * hdma2d )

Suspend the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 565 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_SUSPEND, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), HAL_TIMEOUT_DMA2D_SUSPEND, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DMA2D Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_DisableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Disable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Define the configuration of the line watermark .

Detailed Description

Peripheral Control functions.

 ===============================================================================
                    ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the DMA2D foreground or/and background parameters.
      (+) Configure the DMA2D CLUT transfer.
      (+) Enable DMA2D CLUT.
      (+) Disable DMA2D CLUT.
      (+) Configure the line watermark

Function Documentation

HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D CLUT Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg,: pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 974 of file stm32f7xx_hal_dma2d.c.

References assert_param, DMA2D_CLUTCfgTypeDef::CLUTColorMode, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CLUT_CM, IS_DMA2D_CLUT_SIZE, IS_DMA2D_LAYER, DMA2D_CLUTCfgTypeDef::pCLUT, and DMA2D_CLUTCfgTypeDef::Size.

HAL_StatusTypeDef HAL_DMA2D_ConfigLayer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 838 of file stm32f7xx_hal_dma2d.c.

References DMA2D_LayerCfgTypeDef::AlphaMode, assert_param, CM_A4, CM_A8, DMA2D_M2M, DMA2D_R2M, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Init, DMA2D_LayerCfgTypeDef::InputAlpha, DMA2D_LayerCfgTypeDef::InputColorMode, DMA2D_LayerCfgTypeDef::InputOffset, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_ALPHA_MODE, IS_DMA2D_INPUT_COLOR_MODE, IS_DMA2D_LAYER, IS_DMA2D_OFFSET, __DMA2D_HandleTypeDef::LayerCfg, DMA2D_InitTypeDef::Mode, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_DisableCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the DMA2D CLUT Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 1084 of file stm32f7xx_hal_dma2d.c.

References assert_param, __DMA2D_HandleTypeDef::Instance, and IS_DMA2D_LAYER.

HAL_StatusTypeDef HAL_DMA2D_EnableCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the DMA2D CLUT Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 1056 of file stm32f7xx_hal_dma2d.c.

References assert_param, __DMA2D_HandleTypeDef::Instance, and IS_DMA2D_LAYER.

HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Line
 | ) |  |

Define the configuration of the line watermark .

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Line,: Line Watermark configuration.
Return values:
HAL status

Definition at line 1111 of file stm32f7xx_hal_dma2d.c.

References assert_param, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, IS_DMA2D_LineWatermark, and __DMA2D_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DMA2D Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                  ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Check the DMA2D state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA2D_GetError ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D error code.

Parameters:
hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for DMA2D.
Return values:
DMA2D Error Code

Definition at line 1171 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode.

HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D state.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL state

Definition at line 1160 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA2D Exported Functions

Modules | Functions
DMA2D Exported Functions
DMA2D

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handles DMA2D interrupt request.
HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_DisableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Disable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Define the configuration of the line watermark .
HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.
static void | DMA2D_SetConfig (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D Transfer parameter.

Function Documentation

static void DMA2D_SetConfig | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  | [static]

Set the DMA2D Transfer parameter.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the specified DMA2D.
pdata,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 1191 of file stm32f7xx_hal_dma2d.c.

References DMA2D_InitTypeDef::ColorMode, DMA2D_ARGB1555, DMA2D_ARGB8888, DMA2D_R2M, DMA2D_RGB565, DMA2D_RGB888, __DMA2D_HandleTypeDef::Init, __DMA2D_HandleTypeDef::Instance, and DMA2D_InitTypeDef::Mode.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

HAL_StatusTypeDef HAL_DMA2D_Abort ( DMA2D_HandleTypeDef * hdma2d )

Abort the DMA2D Transfer.

Parameters:
hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 523 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), HAL_TIMEOUT_DMA2D_ABORT, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_BlendingStart | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1,: The source memory Buffer address of the foreground layer.
SrcAddress2,: The source memory Buffer address of the background layer.
DstAddress,: The destination memory Buffer address
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 443 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, assert_param, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | SrcAddress1,
 |  | uint32_t | SrcAddress2,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the multi-source DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
SrcAddress1,: The source memory Buffer address of the foreground layer.
SrcAddress2,: The source memory Buffer address of the background layer.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 481 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | DMA2D_CLUTCfgTypeDef | CLUTCfg,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D CLUT Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
CLUTCfg,: pointer to a DMA2D_CLUTCfgTypeDef structure that contains the configuration information for the color look up table.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 974 of file stm32f7xx_hal_dma2d.c.

References assert_param, DMA2D_CLUTCfgTypeDef::CLUTColorMode, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CLUT_CM, IS_DMA2D_CLUT_SIZE, IS_DMA2D_LAYER, DMA2D_CLUTCfgTypeDef::pCLUT, and DMA2D_CLUTCfgTypeDef::Size.

HAL_StatusTypeDef HAL_DMA2D_ConfigLayer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 838 of file stm32f7xx_hal_dma2d.c.

References DMA2D_LayerCfgTypeDef::AlphaMode, assert_param, CM_A4, CM_A8, DMA2D_M2M, DMA2D_R2M, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::Init, DMA2D_LayerCfgTypeDef::InputAlpha, DMA2D_LayerCfgTypeDef::InputColorMode, DMA2D_LayerCfgTypeDef::InputOffset, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_ALPHA_MODE, IS_DMA2D_INPUT_COLOR_MODE, IS_DMA2D_LAYER, IS_DMA2D_OFFSET, __DMA2D_HandleTypeDef::LayerCfg, DMA2D_InitTypeDef::Mode, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_DeInit ( DMA2D_HandleTypeDef * hdma2d )

Deinitializes the DMA2D peripheral registers to their default reset values.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 264 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_MspDeInit(), HAL_DMA2D_STATE_RESET, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_DisableCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Disable the DMA2D CLUT Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 1084 of file stm32f7xx_hal_dma2d.c.

References assert_param, __DMA2D_HandleTypeDef::Instance, and IS_DMA2D_LAYER.

HAL_StatusTypeDef HAL_DMA2D_EnableCLUT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | LayerIdx
 | ) |  |

Enable the DMA2D CLUT Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
LayerIdx,: DMA2D Layer index. This parameter can be one of the following values: 0(background) / 1(foreground)
Return values:
HAL status

Definition at line 1056 of file stm32f7xx_hal_dma2d.c.

References assert_param, __DMA2D_HandleTypeDef::Instance, and IS_DMA2D_LAYER.

uint32_t HAL_DMA2D_GetError ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D error code.

Parameters:
hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for DMA2D.
Return values:
DMA2D Error Code

Definition at line 1171 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode.

HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState ( DMA2D_HandleTypeDef * hdma2d )

Return the DMA2D state.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL state

Definition at line 1160 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Init ( DMA2D_HandleTypeDef * hdma2d )

Initializes the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 181 of file stm32f7xx_hal_dma2d.c.

References assert_param, DMA2D_InitTypeDef::ColorMode, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_MspInit(), HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_RESET, __DMA2D_HandleTypeDef::Init, __DMA2D_HandleTypeDef::Instance, IS_DMA2D_CMODE, IS_DMA2D_MODE, IS_DMA2D_OFFSET, __DMA2D_HandleTypeDef::Lock, DMA2D_InitTypeDef::Mode, DMA2D_InitTypeDef::OutputOffset, and __DMA2D_HandleTypeDef::State.

void HAL_DMA2D_IRQHandler ( DMA2D_HandleTypeDef * hdma2d )

Handles DMA2D interrupt request.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 722 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_CLEAR_FLAG, __HAL_DMA2D_DISABLE_IT, __HAL_DMA2D_GET_FLAG, __HAL_DMA2D_GET_IT_SOURCE, DMA2D_FLAG_CE, DMA2D_FLAG_TC, DMA2D_FLAG_TE, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_CE, HAL_DMA2D_ERROR_NONE, HAL_DMA2D_ERROR_TE, HAL_DMA2D_STATE_ERROR, HAL_DMA2D_STATE_READY, __DMA2D_HandleTypeDef::State, __DMA2D_HandleTypeDef::XferCpltCallback, and __DMA2D_HandleTypeDef::XferErrorCallback.

void HAL_DMA2D_MspDeInit ( DMA2D_HandleTypeDef * hdma2d )

DeInitializes the DMA2D MSP.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 309 of file stm32f7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_DeInit().

void HAL_DMA2D_MspInit ( DMA2D_HandleTypeDef * hdma2d )

Initializes the DMA2D MSP.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
None

Definition at line 293 of file stm32f7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Init().

HAL_StatusTypeDef HAL_DMA2D_PollForTransfer | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete or CLUT loading.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 619 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_CLEAR_FLAG, __HAL_DMA2D_GET_FLAG, DMA2D_FLAG_CAE, DMA2D_FLAG_CE, DMA2D_FLAG_CTC, DMA2D_FLAG_TC, DMA2D_FLAG_TE, __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_ERROR, HAL_DMA2D_STATE_READY, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | Line
 | ) |  |

Define the configuration of the line watermark .

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Line,: Line Watermark configuration.
Return values:
HAL status

Definition at line 1111 of file stm32f7xx_hal_dma2d.c.

References assert_param, HAL_DMA2D_STATE_BUSY, HAL_DMA2D_STATE_READY, IS_DMA2D_LineWatermark, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Resume ( DMA2D_HandleTypeDef * hdma2d )

Resume the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 601 of file stm32f7xx_hal_dma2d.c.

References HAL_DMA2D_STATE_BUSY, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Start | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata,: Configure the source memory Buffer address if the memory to memory or memory to memory with pixel format conversion DMA2D mode is selected, and configure the color value if register to memory DMA2D mode is selected.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 362 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, assert_param, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Start_IT | ( | DMA2D_HandleTypeDef * | hdma2d,
 |  | uint32_t | pdata,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Width,
 |  | uint32_t | Height
 | ) |  |

Start the DMA2D Transfer with interrupt enabled.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
pdata,: Configure the source memory Buffer address if the memory to memory or memory to memory with pixel format conversion DMA2D mode is selected, and configure the color value if register to memory DMA2D mode is selected.
DstAddress,: The destination memory Buffer address.
Width,: The width of data to be transferred from source to destination.
Height,: The height of data to be transferred from source to destination.
Return values:
HAL status

Definition at line 399 of file stm32f7xx_hal_dma2d.c.

References __HAL_DMA2D_DISABLE, __HAL_DMA2D_ENABLE, __HAL_DMA2D_ENABLE_IT, assert_param, DMA2D_IT_CE, DMA2D_IT_TC, DMA2D_IT_TE, DMA2D_SetConfig(), HAL_DMA2D_STATE_BUSY, IS_DMA2D_LINE, IS_DMA2D_PIXEL, and __DMA2D_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA2D_Suspend ( DMA2D_HandleTypeDef * hdma2d )

Suspend the DMA2D Transfer.

Parameters:
hdma2d,: pointer to a DMA2D_HandleTypeDef structure that contains the configuration information for the DMA2D.
Return values:
HAL status

Definition at line 565 of file stm32f7xx_hal_dma2d.c.

References __DMA2D_HandleTypeDef::ErrorCode, HAL_DMA2D_ERROR_TIMEOUT, HAL_DMA2D_STATE_SUSPEND, HAL_DMA2D_STATE_TIMEOUT, HAL_GetTick(), HAL_TIMEOUT_DMA2D_SUSPEND, __DMA2D_HandleTypeDef::Instance, and __DMA2D_HandleTypeDef::State.

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STM32F745xx HAL User Manual: DMA2D Private Types

DMA2D Private Types
DMA2D
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STM32F745xx HAL User Manual: DMA2D Private Defines

Defines
DMA2D Private Defines
DMA2D

Defines

#define | HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */
#define | HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */

Define Documentation

#define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */

Definition at line 135 of file stm32f7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Abort().

#define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */

Definition at line 136 of file stm32f7xx_hal_dma2d.c.

Referenced by HAL_DMA2D_Suspend().

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STM32F745xx HAL User Manual: DMA2D Private Variables

DMA2D Private Variables
DMA2D
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STM32F745xx HAL User Manual: DMA2D Private Constants

DMA2D Private Constants
DMA2D
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STM32F745xx HAL User Manual: DMA2D Private Macros

Defines
DMA2D Private Macros
DMA2D

Defines

#define | IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define | IS_DMA2D_MODE(MODE)
#define | IS_DMA2D_CMODE(MODE_ARGB)
#define | IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
#define | IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define | IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define | IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define | IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)
#define | IS_DMA2D_ALPHA_MODE(AlphaMode)
#define | IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define | IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define | IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
#define | IS_DMA2D_IT(IT)
#define | IS_DMA2D_GET_FLAG(FLAG)

Define Documentation

#define IS_DMA2D_ALPHA_MODE ( AlphaMode )
Value:
(((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))

Definition at line 509 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define IS_DMA2D_CLUT_CM ( CLUT_CM ) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))

Definition at line 512 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigCLUT().

#define IS_DMA2D_CLUT_SIZE ( CLUT_SIZE ) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)

Definition at line 513 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigCLUT().

#define IS_DMA2D_CMODE ( MODE_ARGB )
Value:
(((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888)   || \
                                               ((MODE_ARGB) == DMA2D_RGB565)   || ((MODE_ARGB) == DMA2D_ARGB1555) || \
                                               ((MODE_ARGB) == DMA2D_ARGB4444))

Definition at line 496 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

#define IS_DMA2D_COLOR ( COLOR ) ((COLOR) <= COLOR_VALUE)

Definition at line 499 of file stm32f7xx_hal_dma2d.h.

#define IS_DMA2D_GET_FLAG ( FLAG )
Value:
(((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))

Definition at line 518 of file stm32f7xx_hal_dma2d.h.

#define IS_DMA2D_INPUT_COLOR_MODE ( INPUT_CM )
Value:
(((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888)   || \
                                               ((INPUT_CM) == CM_RGB565)   || ((INPUT_CM) == CM_ARGB1555) || \
                                               ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8)       || \
                                               ((INPUT_CM) == CM_AL44)     || ((INPUT_CM) == CM_AL88)     || \
                                               ((INPUT_CM) == CM_L4)       || ((INPUT_CM) == CM_A8)       || \
                                               ((INPUT_CM) == CM_A4))

Definition at line 503 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer().

#define IS_DMA2D_IT ( IT )
Value:
(((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))

Definition at line 515 of file stm32f7xx_hal_dma2d.h.

#define IS_DMA2D_LAYER ( LAYER ) ((LAYER) <= MAX_DMA2D_LAYER)

Definition at line 493 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_DisableCLUT(), and HAL_DMA2D_EnableCLUT().

#define IS_DMA2D_LINE ( LINE ) ((LINE) <= DMA2D_LINE)

Definition at line 500 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

#define IS_DMA2D_LineWatermark ( LineWatermark ) ((LineWatermark) <= LINE_WATERMARK)

Definition at line 514 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ProgramLineEvent().

#define IS_DMA2D_MODE ( MODE )
Value:
(((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))

Definition at line 494 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_Init().

#define IS_DMA2D_OFFSET ( OOFFSET ) ((OOFFSET) <= DMA2D_OFFSET)

Definition at line 502 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_ConfigLayer(), and HAL_DMA2D_Init().

#define IS_DMA2D_PIXEL ( PIXEL ) ((PIXEL) <= DMA2D_PIXEL)

Definition at line 501 of file stm32f7xx_hal_dma2d.h.

Referenced by HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_Start(), and HAL_DMA2D_Start_IT().

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STM32F745xx HAL User Manual: DMA2D Private Functions Prototypes

DMA2D Private Functions Prototypes
DMA2D
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STM32F745xx HAL User Manual: DMA2D Private Functions

DMA2D Private Functions
DMA2D
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STM32F745xx HAL User Manual: DMAEx Exported Types

Enumerations
DMAEx Exported Types
DMAEx

DMAEx Exported types. More...

Enumerations

enum HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00, MEMORY1 = 0x01 }
HAL DMA Memory definition. More...

Detailed Description

DMAEx Exported types.

Enumeration Type Documentation

enum HAL_DMA_MemoryTypeDef

HAL DMA Memory definition.

Enumerator:
MEMORY0

Memory 0

MEMORY1

Memory 1

Definition at line 66 of file stm32f7xx_hal_dma_ex.h.

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STM32F745xx HAL User Manual: Extended features functions

Functions
Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer with interrupt
      (+) Change on the fly the memory0 or memory1 address.

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ChangeMemory | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | Address,
 |  | HAL_DMA_MemoryTypeDef | memory
 | ) |  |

Change the memory0 or memory1 address on the fly.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Address,: The new address
memory,: the memory to be changed, This parameter can be one of the following values: MEMORY0 / MEMORY1
Note:
The MEMORY0 address can be changed only when the current transfer use MEMORY1 and the MEMORY1 address can be changed only when the current transfer use MEMORY0.
Return values:
HAL status

Definition at line 268 of file stm32f7xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::Instance, and MEMORY0.

Referenced by DCMI_DMAConvCplt().

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 155 of file stm32f7xx_hal_dma_ex.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_MultiBufferSetConfig(), HAL_DMA_STATE_BUSY_MEM0, HAL_DMA_STATE_BUSY_MEM1, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 202 of file stm32f7xx_hal_dma_ex.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_MultiBufferSetConfig(), HAL_DMA_STATE_BUSY_MEM0, HAL_DMA_STATE_BUSY_MEM1, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

Referenced by HAL_DCMI_Start_DMA().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMAEx Private Functions

Functions
DMAEx Private Functions
DMAEx

DMAEx Private functions. More...

Functions

static void DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.

Detailed Description

DMAEx Private functions.

Function Documentation

static void DMA_MultiBufferSetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Set the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 91 of file stm32f7xx_hal_dma_ex.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Private Constants

Defines
ETH Private Constants
ETH

Defines

#define | LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
#define | AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */

Define Documentation

#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */

Definition at line 118 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_Init().

#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */

Definition at line 117 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Private Functions

Functions
ETH Private Functions
ETH

Functions

static void | ETH_MACDMAConfig (ETH_HandleTypeDef *heth, uint32_t err)
Configures Ethernet MAC and DMA with default parameters.
static void | ETH_MACAddressConfig (ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
Configures the selected MAC address.
static void | ETH_MACReceptionEnable (ETH_HandleTypeDef *heth)
Enables the MAC reception.
static void | ETH_MACReceptionDisable (ETH_HandleTypeDef *heth)
Disables the MAC reception.
static void | ETH_MACTransmissionEnable (ETH_HandleTypeDef *heth)
Enables the MAC transmission.
static void | ETH_MACTransmissionDisable (ETH_HandleTypeDef *heth)
Disables the MAC transmission.
static void | ETH_DMATransmissionEnable (ETH_HandleTypeDef *heth)
Enables the DMA transmission.
static void | ETH_DMATransmissionDisable (ETH_HandleTypeDef *heth)
Disables the DMA transmission.
static void | ETH_DMAReceptionEnable (ETH_HandleTypeDef *heth)
Enables the DMA reception.
static void | ETH_DMAReceptionDisable (ETH_HandleTypeDef *heth)
Disables the DMA reception.
static void | ETH_FlushTransmitFIFO (ETH_HandleTypeDef *heth)
Clears the ETHERNET transmit FIFO.

Function Documentation

static void ETH_DMAReceptionDisable ( ETH_HandleTypeDef * heth ) [static]

Disables the DMA reception.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1987 of file stm32f7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Stop().

static void ETH_DMAReceptionEnable ( ETH_HandleTypeDef * heth ) [static]

Enables the DMA reception.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1975 of file stm32f7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Start().

static void ETH_DMATransmissionDisable ( ETH_HandleTypeDef * heth ) [static]

Disables the DMA transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1963 of file stm32f7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Stop().

static void ETH_DMATransmissionEnable ( ETH_HandleTypeDef * heth ) [static]

Enables the DMA transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1951 of file stm32f7xx_hal_eth.c.

References ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Start().

static void ETH_FlushTransmitFIFO ( ETH_HandleTypeDef * heth ) [static]

Clears the ETHERNET transmit FIFO.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1999 of file stm32f7xx_hal_eth.c.

References ETH_REG_WRITE_DELAY, HAL_Delay(), and ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Start(), and HAL_ETH_Stop().

static void ETH_MACAddressConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | MacAddr,
 |  | uint8_t * | Addr
 | ) |  | [static]

Configures the selected MAC address.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
MacAddr,: The MAC address to configure This parameter can be one of the following values:
  • ETH_MAC_Address0: MAC Address0
  • ETH_MAC_Address1: MAC Address1
  • ETH_MAC_Address2: MAC Address2
  • ETH_MAC_Address3: MAC Address3
Addr,: Pointer to MAC address buffer data (6 bytes)
Return values:
HAL status

Definition at line 1847 of file stm32f7xx_hal_eth.c.

References assert_param, ETH_MAC_ADDR_HBASE, ETH_MAC_ADDR_LBASE, and IS_ETH_MAC_ADDRESS0123.

Referenced by ETH_MACDMAConfig().

static void ETH_MACDMAConfig | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | err
 | ) |  | [static]

Configures Ethernet MAC and DMA with default parameters.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
err,: Ethernet Init error
Return values:
HAL status

Definition at line 1584 of file stm32f7xx_hal_eth.c.

References __HAL_ETH_DMA_ENABLE_IT, ETH_DMAInitTypeDef::AddressAlignedBeats, ETH_MACInitTypeDef::AutomaticPadCRCStrip, ETH_MACInitTypeDef::BackOffLimit, ETH_MACInitTypeDef::BroadcastFramesReception, ETH_MACInitTypeDef::CarrierSense, ETH_InitTypeDef::ChecksumMode, ETH_MACInitTypeDef::ChecksumOffload, ETH_MACInitTypeDef::DeferralCheck, ETH_DMAInitTypeDef::DescriptorSkipLength, ETH_MACInitTypeDef::DestinationAddrFilter, ETH_DMAInitTypeDef::DMAArbitration, ETH_DMAInitTypeDef::DropTCPIPChecksumErrorFrame, ETH_DMAInitTypeDef::EnhancedDescriptorFormat, ETH_ADDRESSALIGNEDBEATS_ENABLE, ETH_AUTOMATICPADCRCSTRIP_DISABLE, ETH_BACKOFFLIMIT_10, ETH_BROADCASTFRAMESRECEPTION_ENABLE, ETH_CARRIERSENCE_ENABLE, ETH_CHECKSUM_BY_HARDWARE, ETH_CHECKSUMOFFLAOD_DISABLE, ETH_CHECKSUMOFFLAOD_ENABLE, ETH_DEFFERRALCHECK_DISABLE, ETH_DESTINATIONADDRFILTER_NORMAL, ETH_DMA_IT_NIS, ETH_DMA_IT_R, ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1, ETH_DMAENHANCEDDESCRIPTOR_ENABLE, ETH_DMAOMR_CLEAR_MASK, ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE, ETH_FIXEDBURST_ENABLE, ETH_FLUSHRECEIVEDFRAME_ENABLE, ETH_FORWARDERRORFRAMES_DISABLE, ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE, ETH_INTERFRAMEGAP_96BIT, ETH_JABBER_ENABLE, ETH_LOOPBACKMODE_DISABLE, ETH_MAC_ADDRESS0, ETH_MACAddressConfig(), ETH_MACCR_CLEAR_MASK, ETH_MACFCR_CLEAR_MASK, ETH_MODE_FULLDUPLEX, ETH_MULTICASTFRAMESFILTER_PERFECT, ETH_PASSCONTROLFRAMES_BLOCKALL, ETH_PAUSELOWTHRESHOLD_MINUS4, ETH_PROMISCUOUS_MODE_DISABLE, ETH_RECEIVEAll_DISABLE, ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES, ETH_RECEIVEFLOWCONTROL_DISABLE, ETH_RECEIVEOWN_ENABLE, ETH_RECEIVESTOREFORWARD_ENABLE, ETH_REG_WRITE_DELAY, ETH_RETRYTRANSMISSION_DISABLE, ETH_RXDMABURSTLENGTH_32BEAT, ETH_RXINTERRUPT_MODE, ETH_SECONDFRAMEOPERARTE_ENABLE, ETH_SOURCEADDRFILTER_DISABLE, ETH_SPEED_100M, ETH_SUCCESS, ETH_TRANSMITFLOWCONTROL_DISABLE, ETH_TRANSMITSTOREFORWARD_ENABLE, ETH_TRANSMITTHRESHOLDCONTROL_64BYTES, ETH_TXDMABURSTLENGTH_32BEAT, ETH_UNICASTFRAMESFILTER_PERFECT, ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, ETH_VLANTAGCOMPARISON_16BIT, ETH_WATCHDOG_ENABLE, ETH_ZEROQUANTAPAUSE_DISABLE, ETH_DMAInitTypeDef::FixedBurst, ETH_DMAInitTypeDef::FlushReceivedFrame, ETH_DMAInitTypeDef::ForwardErrorFrames, ETH_DMAInitTypeDef::ForwardUndersizedGoodFrames, HAL_Delay(), ETH_MACInitTypeDef::HashTableHigh, ETH_MACInitTypeDef::HashTableLow, ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_MACInitTypeDef::InterFrameGap, ETH_MACInitTypeDef::Jabber, ETH_MACInitTypeDef::LoopbackMode, ETH_InitTypeDef::MACAddr, ETH_MACInitTypeDef::MulticastFramesFilter, ETH_MACInitTypeDef::PassControlFrames, ETH_MACInitTypeDef::PauseLowThreshold, ETH_MACInitTypeDef::PauseTime, ETH_MACInitTypeDef::PromiscuousMode, ETH_MACInitTypeDef::ReceiveAll, ETH_MACInitTypeDef::ReceiveFlowControl, ETH_MACInitTypeDef::ReceiveOwn, ETH_DMAInitTypeDef::ReceiveStoreForward, ETH_DMAInitTypeDef::ReceiveThresholdControl, ETH_MACInitTypeDef::RetryTransmission, ETH_DMAInitTypeDef::RxDMABurstLength, ETH_DMAInitTypeDef::SecondFrameOperate, ETH_MACInitTypeDef::SourceAddrFilter, ETH_MACInitTypeDef::TransmitFlowControl, ETH_DMAInitTypeDef::TransmitStoreForward, ETH_DMAInitTypeDef::TransmitThresholdControl, ETH_DMAInitTypeDef::TxDMABurstLength, ETH_MACInitTypeDef::UnicastFramesFilter, ETH_MACInitTypeDef::UnicastPauseFrameDetect, ETH_MACInitTypeDef::VLANTagComparison, ETH_MACInitTypeDef::VLANTagIdentifier, ETH_MACInitTypeDef::Watchdog, and ETH_MACInitTypeDef::ZeroQuantaPause.

Referenced by HAL_ETH_Init().

static void ETH_MACReceptionDisable ( ETH_HandleTypeDef * heth ) [static]

Disables the MAC reception.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1931 of file stm32f7xx_hal_eth.c.

References ETH_REG_WRITE_DELAY, HAL_Delay(), and ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Stop().

static void ETH_MACReceptionEnable ( ETH_HandleTypeDef * heth ) [static]

Enables the MAC reception.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1911 of file stm32f7xx_hal_eth.c.

References ETH_REG_WRITE_DELAY, HAL_Delay(), and ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Start().

static void ETH_MACTransmissionDisable ( ETH_HandleTypeDef * heth ) [static]

Disables the MAC transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1891 of file stm32f7xx_hal_eth.c.

References ETH_REG_WRITE_DELAY, HAL_Delay(), and ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Stop().

static void ETH_MACTransmissionEnable ( ETH_HandleTypeDef * heth ) [static]

Enables the MAC transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1871 of file stm32f7xx_hal_eth.c.

References ETH_REG_WRITE_DELAY, HAL_Delay(), and ETH_HandleTypeDef::Instance.

Referenced by HAL_ETH_Start().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ETH Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ETH_Init (ETH_HandleTypeDef *heth)
Initializes the Ethernet MAC and DMA according to default parameters.
HAL_StatusTypeDef | HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
De-Initializes the ETH peripheral.
HAL_StatusTypeDef | HAL_ETH_DMATxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
Initializes the DMA Tx descriptors in chain mode.
HAL_StatusTypeDef | HAL_ETH_DMARxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
Initializes the DMA Rx descriptors in chain mode.
__weak void | HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
__weak void | HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
            ##### Initialization and de-initialization functions #####
  ===============================================================================
  [..]  This section provides functions allowing to:
      (+) Initialize and configure the Ethernet peripheral
      (+) De-initialize the Ethernet peripheral

Function Documentation

HAL_StatusTypeDef HAL_ETH_DeInit ( ETH_HandleTypeDef * heth )

De-Initializes the ETH peripheral.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 429 of file stm32f7xx_hal_eth.c.

References HAL_ETH_MspDeInit(), HAL_ETH_STATE_BUSY, HAL_ETH_STATE_RESET, and ETH_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ETH_DMARxDescListInit | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_DMADescTypeDef * | DMARxDescTab,
 |  | uint8_t * | RxBuff,
 |  | uint32_t | RxBuffCount
 | ) |  |

Initializes the DMA Rx descriptors in chain mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
DMARxDescTab,: Pointer to the first Rx desc list
RxBuff,: Pointer to the first RxBuffer list
RxBuffCount,: Number of the used Rx desc in the list
Return values:
HAL status

Definition at line 523 of file stm32f7xx_hal_eth.c.

References ETH_DMADescTypeDef::Buffer1Addr, ETH_DMADescTypeDef::Buffer2NextDescAddr, ETH_DMADescTypeDef::ControlBufferSize, ETH_DMARXDESC_DIC, ETH_DMARXDESC_OWN, ETH_DMARXDESC_RCH, ETH_RX_BUF_SIZE, ETH_RXINTERRUPT_MODE, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_HandleTypeDef::RxDesc, ETH_HandleTypeDef::State, and ETH_DMADescTypeDef::Status.

HAL_StatusTypeDef HAL_ETH_DMATxDescListInit | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_DMADescTypeDef * | DMATxDescTab,
 |  | uint8_t * | TxBuff,
 |  | uint32_t | TxBuffCount
 | ) |  |

Initializes the DMA Tx descriptors in chain mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
DMATxDescTab,: Pointer to the first Tx desc list
TxBuff,: Pointer to the first TxBuffer list
TxBuffCount,: Number of the used Tx desc in the list
Return values:
HAL status

Definition at line 456 of file stm32f7xx_hal_eth.c.

References ETH_DMADescTypeDef::Buffer1Addr, ETH_DMADescTypeDef::Buffer2NextDescAddr, ETH_CHECKSUM_BY_HARDWARE, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL, ETH_DMATXDESC_TCH, ETH_TX_BUF_SIZE, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_HandleTypeDef::State, ETH_DMADescTypeDef::Status, and ETH_HandleTypeDef::TxDesc.

HAL_StatusTypeDef HAL_ETH_Init ( ETH_HandleTypeDef * heth )

Initializes the Ethernet MAC and DMA according to default parameters.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 172 of file stm32f7xx_hal_eth.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, AUTONEGO_COMPLETED_TIMEOUT_VALUE, ETH_InitTypeDef::AutoNegotiation, ETH_InitTypeDef::ChecksumMode, ETH_InitTypeDef::DuplexMode, ETH_AUTONEGOTIATION_DISABLE, ETH_ERROR, ETH_MACDMAConfig(), ETH_MACMIIAR_CR_MASK, ETH_MODE_FULLDUPLEX, ETH_MODE_HALFDUPLEX, ETH_SPEED_100M, ETH_SPEED_10M, ETH_SUCCESS, HAL_Delay(), HAL_ETH_MspInit(), HAL_ETH_ReadPHYRegister(), HAL_ETH_STATE_READY, HAL_ETH_STATE_RESET, HAL_ETH_WritePHYRegister(), HAL_GetTick(), HAL_RCC_GetHCLKFreq(), ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, IS_ETH_AUTONEGOTIATION, IS_ETH_CHECKSUM_MODE, IS_ETH_DUPLEX_MODE, IS_ETH_MEDIA_INTERFACE, IS_ETH_RX_MODE, IS_ETH_SPEED, LINKED_STATE_TIMEOUT_VALUE, ETH_HandleTypeDef::Lock, ETH_InitTypeDef::MediaInterface, PHY_AUTONEGO_COMPLETE, PHY_AUTONEGOTIATION, PHY_BCR, PHY_BSR, PHY_CONFIG_DELAY, PHY_DUPLEX_STATUS, PHY_LINKED_STATUS, PHY_RESET, PHY_RESET_DELAY, PHY_SPEED_STATUS, PHY_SR, ETH_InitTypeDef::RxMode, ETH_InitTypeDef::Speed, and ETH_HandleTypeDef::State.

void HAL_ETH_MspDeInit ( ETH_HandleTypeDef * heth )

DeInitializes ETH MSP.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 606 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_DeInit().

void HAL_ETH_MspInit ( ETH_HandleTypeDef * heth )

Initializes the ETH MSP.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 590 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
ETH Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_ETH_TransmitFrame (ETH_HandleTypeDef *heth, uint32_t FrameLength)
Sends an Ethernet frame.
HAL_StatusTypeDef | HAL_ETH_GetReceivedFrame (ETH_HandleTypeDef *heth)
Checks for received frames.
HAL_StatusTypeDef | HAL_ETH_GetReceivedFrame_IT (ETH_HandleTypeDef *heth)
Gets the Received frame in interrupt mode.
void | HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
__weak void | HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
__weak void | HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
__weak void | HAL_ETH_ErrorCallback (ETH_HandleTypeDef *heth)
Ethernet transfer error callbacks.
HAL_StatusTypeDef | HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
Reads a PHY register.
HAL_StatusTypeDef | HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
Writes to a PHY register.

Detailed Description

Data transfers functions.

  ==============================================================================
                          ##### IO operation functions #####
  ==============================================================================
  [..]  This section provides functions allowing to:
        (+) Transmit a frame
            HAL_ETH_TransmitFrame();
        (+) Receive a frame
            HAL_ETH_GetReceivedFrame();
            HAL_ETH_GetReceivedFrame_IT();
        (+) Read from an External PHY register
            HAL_ETH_ReadPHYRegister();
        (+) Write to an External PHY register
            HAL_ETH_WritePHYRegister();

Function Documentation

void HAL_ETH_ErrorCallback ( ETH_HandleTypeDef * heth )

Ethernet transfer error callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1020 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_GetReceivedFrame ( ETH_HandleTypeDef * heth )

Checks for received frames.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 763 of file stm32f7xx_hal_eth.c.

References ETH_DMARxFrameInfos::buffer, ETH_DMADescTypeDef::Buffer2NextDescAddr, ETH_DMARXDESC_FL, ETH_DMARXDESC_FRAMELENGTHSHIFT, ETH_DMARXDESC_FS, ETH_DMARXDESC_LS, ETH_DMARXDESC_OWN, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, ETH_DMARxFrameInfos::length, ETH_DMARxFrameInfos::LSRxDesc, ETH_HandleTypeDef::RxDesc, ETH_HandleTypeDef::RxFrameInfos, ETH_HandleTypeDef::State, and ETH_DMADescTypeDef::Status.

HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT ( ETH_HandleTypeDef * heth )

Gets the Received frame in interrupt mode.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 843 of file stm32f7xx_hal_eth.c.

References ETH_DMARxFrameInfos::buffer, ETH_DMADescTypeDef::Buffer2NextDescAddr, ETH_DMARXDESC_FL, ETH_DMARXDESC_FRAMELENGTHSHIFT, ETH_DMARXDESC_FS, ETH_DMARXDESC_LS, ETH_DMARXDESC_OWN, ETH_RXBUFNB, ETH_DMARxFrameInfos::FSRxDesc, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, ETH_DMARxFrameInfos::length, ETH_DMARxFrameInfos::LSRxDesc, ETH_HandleTypeDef::RxDesc, ETH_HandleTypeDef::RxFrameInfos, ETH_DMARxFrameInfos::SegCount, ETH_HandleTypeDef::State, and ETH_DMADescTypeDef::Status.

void HAL_ETH_IRQHandler ( ETH_HandleTypeDef * heth )

This function handles ETH interrupt request.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 928 of file stm32f7xx_hal_eth.c.

References __HAL_ETH_DMA_CLEAR_IT, __HAL_ETH_DMA_GET_FLAG, ETH_DMA_FLAG_AIS, ETH_DMA_FLAG_R, ETH_DMA_FLAG_T, ETH_DMA_IT_NIS, ETH_DMA_IT_R, ETH_DMA_IT_T, HAL_ETH_ErrorCallback(), HAL_ETH_RxCpltCallback(), HAL_ETH_STATE_READY, HAL_ETH_TxCpltCallback(), and ETH_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ETH_ReadPHYRegister | ( | ETH_HandleTypeDef * | heth,
 |  | uint16_t | PHYReg,
 |  | uint32_t * | RegValue
 | ) |  |

Reads a PHY register.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
PHYReg,: PHY register address, is the index of one of the 32 PHY register. This parameter can be one of the following values: PHY_BCR: Transceiver Basic Control Register, PHY_BSR: Transceiver Basic Status Register. More PHY register could be read depending on the used PHY
RegValue,: PHY register value
Return values:
HAL status

Definition at line 1042 of file stm32f7xx_hal_eth.c.

References assert_param, ETH_MACMIIAR_CR_MASK, HAL_ETH_STATE_BUSY_RD, HAL_ETH_STATE_READY, HAL_GetTick(), ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, IS_ETH_PHY_ADDRESS, PHY_READ_TO, ETH_InitTypeDef::PhyAddress, and ETH_HandleTypeDef::State.

Referenced by HAL_ETH_Init().

void HAL_ETH_RxCpltCallback ( ETH_HandleTypeDef * heth )

Rx Transfer completed callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 1004 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_TransmitFrame | ( | ETH_HandleTypeDef * | heth,
 |  | uint32_t | FrameLength
 | ) |  |

Sends an Ethernet frame.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
FrameLength,: Amount of data to be sent
Return values:
HAL status

Definition at line 650 of file stm32f7xx_hal_eth.c.

References ETH_DMADescTypeDef::Buffer2NextDescAddr, ETH_DMADescTypeDef::ControlBufferSize, ETH_DMATXDESC_FS, ETH_DMATXDESC_LS, ETH_DMATXDESC_OWN, ETH_DMATXDESC_TBS1, ETH_TX_BUF_SIZE, HAL_ETH_STATE_BUSY, HAL_ETH_STATE_BUSY_TX, HAL_ETH_STATE_READY, ETH_HandleTypeDef::Instance, ETH_HandleTypeDef::State, ETH_DMADescTypeDef::Status, and ETH_HandleTypeDef::TxDesc.

void HAL_ETH_TxCpltCallback ( ETH_HandleTypeDef * heth )

Tx Transfer completed callbacks.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
None

Definition at line 988 of file stm32f7xx_hal_eth.c.

Referenced by HAL_ETH_IRQHandler().

HAL_StatusTypeDef HAL_ETH_WritePHYRegister | ( | ETH_HandleTypeDef * | heth,
 |  | uint16_t | PHYReg,
 |  | uint32_t | RegValue
 | ) |  |

Writes to a PHY register.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
PHYReg,: PHY register address, is the index of one of the 32 PHY register. This parameter can be one of the following values: PHY_BCR: Transceiver Control Register. More PHY register could be written depending on the used PHY
RegValue,: the value to write
Return values:
HAL status

Definition at line 1114 of file stm32f7xx_hal_eth.c.

References assert_param, ETH_MACMIIAR_CR_MASK, HAL_ETH_STATE_BUSY_WR, HAL_ETH_STATE_READY, HAL_GetTick(), ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, IS_ETH_PHY_ADDRESS, PHY_WRITE_TO, ETH_InitTypeDef::PhyAddress, and ETH_HandleTypeDef::State.

Referenced by HAL_ETH_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ETH Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ETH_Start (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_Stop (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_ConfigMAC (ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
Set ETH MAC Configuration.
HAL_StatusTypeDef | HAL_ETH_ConfigDMA (ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
Sets ETH DMA Configuration.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                  ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Enable MAC and DMA transmission and reception.
          HAL_ETH_Start();
      (+) Disable MAC and DMA transmission and reception.
          HAL_ETH_Stop();
      (+) Set the MAC configuration in runtime mode
          HAL_ETH_ConfigMAC();
      (+) Set the DMA configuration in runtime mode
          HAL_ETH_ConfigDMA();

Function Documentation

HAL_StatusTypeDef HAL_ETH_ConfigDMA | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_DMAInitTypeDef * | dmaconf
 | ) |  |

Sets ETH DMA Configuration.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
dmaconf,: DMA Configuration structure
Return values:
HAL status

Definition at line 1452 of file stm32f7xx_hal_eth.c.

References ETH_DMAInitTypeDef::AddressAlignedBeats, assert_param, ETH_DMAInitTypeDef::DescriptorSkipLength, ETH_DMAInitTypeDef::DMAArbitration, ETH_DMAInitTypeDef::DropTCPIPChecksumErrorFrame, ETH_DMAInitTypeDef::EnhancedDescriptorFormat, ETH_DMAOMR_CLEAR_MASK, ETH_REG_WRITE_DELAY, ETH_DMAInitTypeDef::FixedBurst, ETH_DMAInitTypeDef::FlushReceivedFrame, ETH_DMAInitTypeDef::ForwardErrorFrames, ETH_DMAInitTypeDef::ForwardUndersizedGoodFrames, HAL_Delay(), HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, ETH_HandleTypeDef::Instance, IS_ETH_ADDRESS_ALIGNED_BEATS, IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX, IS_ETH_DMA_DESC_SKIP_LENGTH, IS_ETH_DROP_TCPIP_CHECKSUM_FRAME, IS_ETH_ENHANCED_DESCRIPTOR_FORMAT, IS_ETH_FIXED_BURST, IS_ETH_FLUSH_RECEIVE_FRAME, IS_ETH_FORWARD_ERROR_FRAMES, IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES, IS_ETH_RECEIVE_STORE_FORWARD, IS_ETH_RECEIVE_THRESHOLD_CONTROL, IS_ETH_RXDMA_BURST_LENGTH, IS_ETH_SECOND_FRAME_OPERATE, IS_ETH_TRANSMIT_STORE_FORWARD, IS_ETH_TRANSMIT_THRESHOLD_CONTROL, IS_ETH_TXDMA_BURST_LENGTH, ETH_DMAInitTypeDef::ReceiveStoreForward, ETH_DMAInitTypeDef::ReceiveThresholdControl, ETH_DMAInitTypeDef::RxDMABurstLength, ETH_DMAInitTypeDef::SecondFrameOperate, ETH_HandleTypeDef::State, ETH_DMAInitTypeDef::TransmitStoreForward, ETH_DMAInitTypeDef::TransmitThresholdControl, and ETH_DMAInitTypeDef::TxDMABurstLength.

HAL_StatusTypeDef HAL_ETH_ConfigMAC | ( | ETH_HandleTypeDef * | heth,
 |  | ETH_MACInitTypeDef * | macconf
 | ) |  |

Set ETH MAC Configuration.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
macconf,: MAC Configuration structure
Return values:
HAL status

Definition at line 1285 of file stm32f7xx_hal_eth.c.

References assert_param, ETH_MACInitTypeDef::AutomaticPadCRCStrip, ETH_MACInitTypeDef::BackOffLimit, ETH_MACInitTypeDef::BroadcastFramesReception, ETH_MACInitTypeDef::CarrierSense, ETH_MACInitTypeDef::ChecksumOffload, ETH_MACInitTypeDef::DeferralCheck, ETH_MACInitTypeDef::DestinationAddrFilter, ETH_InitTypeDef::DuplexMode, ETH_MACCR_CLEAR_MASK, ETH_MACFCR_CLEAR_MASK, ETH_REG_WRITE_DELAY, HAL_Delay(), HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, ETH_MACInitTypeDef::HashTableHigh, ETH_MACInitTypeDef::HashTableLow, ETH_HandleTypeDef::Init, ETH_HandleTypeDef::Instance, ETH_MACInitTypeDef::InterFrameGap, IS_ETH_AUTOMATIC_PADCRC_STRIP, IS_ETH_BACKOFF_LIMIT, IS_ETH_BROADCAST_FRAMES_RECEPTION, IS_ETH_CARRIER_SENSE, IS_ETH_CHECKSUM_OFFLOAD, IS_ETH_CONTROL_FRAMES, IS_ETH_DEFERRAL_CHECK, IS_ETH_DESTINATION_ADDR_FILTER, IS_ETH_DUPLEX_MODE, IS_ETH_INTER_FRAME_GAP, IS_ETH_JABBER, IS_ETH_LOOPBACK_MODE, IS_ETH_MULTICAST_FRAMES_FILTER, IS_ETH_PAUSE_LOW_THRESHOLD, IS_ETH_PAUSE_TIME, IS_ETH_PROMISCUOUS_MODE, IS_ETH_RECEIVE_ALL, IS_ETH_RECEIVE_FLOWCONTROL, IS_ETH_RECEIVE_OWN, IS_ETH_RETRY_TRANSMISSION, IS_ETH_SOURCE_ADDR_FILTER, IS_ETH_SPEED, IS_ETH_TRANSMIT_FLOWCONTROL, IS_ETH_UNICAST_FRAMES_FILTER, IS_ETH_UNICAST_PAUSE_FRAME_DETECT, IS_ETH_VLAN_TAG_COMPARISON, IS_ETH_VLAN_TAG_IDENTIFIER, IS_ETH_WATCHDOG, IS_ETH_ZEROQUANTA_PAUSE, ETH_MACInitTypeDef::Jabber, ETH_MACInitTypeDef::LoopbackMode, ETH_MACInitTypeDef::MulticastFramesFilter, ETH_MACInitTypeDef::PassControlFrames, ETH_MACInitTypeDef::PauseLowThreshold, ETH_MACInitTypeDef::PauseTime, ETH_MACInitTypeDef::PromiscuousMode, ETH_MACInitTypeDef::ReceiveAll, ETH_MACInitTypeDef::ReceiveFlowControl, ETH_MACInitTypeDef::ReceiveOwn, ETH_MACInitTypeDef::RetryTransmission, ETH_MACInitTypeDef::SourceAddrFilter, ETH_InitTypeDef::Speed, ETH_HandleTypeDef::State, ETH_MACInitTypeDef::TransmitFlowControl, ETH_MACInitTypeDef::UnicastFramesFilter, ETH_MACInitTypeDef::UnicastPauseFrameDetect, ETH_MACInitTypeDef::VLANTagComparison, ETH_MACInitTypeDef::VLANTagIdentifier, ETH_MACInitTypeDef::Watchdog, and ETH_MACInitTypeDef::ZeroQuantaPause.

HAL_StatusTypeDef HAL_ETH_Start ( ETH_HandleTypeDef * heth )

Enables Ethernet MAC and DMA reception/transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 1206 of file stm32f7xx_hal_eth.c.

References ETH_DMAReceptionEnable(), ETH_DMATransmissionEnable(), ETH_FlushTransmitFIFO(), ETH_MACReceptionEnable(), ETH_MACTransmissionEnable(), HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, and ETH_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ETH_Stop ( ETH_HandleTypeDef * heth )

Stop Ethernet MAC and DMA reception/transmission.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL status

Definition at line 1245 of file stm32f7xx_hal_eth.c.

References ETH_DMAReceptionDisable(), ETH_DMATransmissionDisable(), ETH_FlushTransmitFIFO(), ETH_MACReceptionDisable(), ETH_MACTransmissionDisable(), HAL_ETH_STATE_BUSY, HAL_ETH_STATE_READY, and ETH_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ETH Exported Functions

Peripheral State functions. More...

Functions

HAL_ETH_StateTypeDef HAL_ETH_GetState (ETH_HandleTypeDef *heth)
Return the ETH HAL state.

Detailed Description

Peripheral State functions.

  ===============================================================================
                         ##### Peripheral State functions #####
  ===============================================================================
  [..]
  This subsection permits to get in run-time the status of the peripheral
  and the data flow.
       (+) Get the ETH handle state:
           HAL_ETH_GetState();

Function Documentation

HAL_ETH_StateTypeDef HAL_ETH_GetState ( ETH_HandleTypeDef * heth )

Return the ETH HAL state.

Parameters:
heth,: pointer to a ETH_HandleTypeDef structure that contains the configuration information for ETHERNET module
Return values:
HAL state

Definition at line 1559 of file stm32f7xx_hal_eth.c.

References ETH_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Exported Types

Data Structures | Enumerations
ETH Exported Types
ETH

Data Structures

struct | ETH_InitTypeDef
ETH Init Structure definition. More...
struct | ETH_MACInitTypeDef
ETH MAC Configuration Structure definition. More...
struct | ETH_DMAInitTypeDef
ETH DMA Configuration Structure definition. More...
struct | ETH_DMADescTypeDef
ETH DMA Descriptors data structure definition. More...
struct | ETH_DMARxFrameInfos
Received Frame Informations structure definition. More...
struct | ETH_HandleTypeDef
ETH Handle Structure definition. More...

Enumerations

enum HAL_ETH_StateTypeDef {
HAL_ETH_STATE_RESET = 0x00, HAL_ETH_STATE_READY = 0x01, HAL_ETH_STATE_BUSY = 0x02, HAL_ETH_STATE_BUSY_TX = 0x12,
HAL_ETH_STATE_BUSY_RX = 0x22, HAL_ETH_STATE_BUSY_TX_RX = 0x32, HAL_ETH_STATE_BUSY_WR = 0x42, HAL_ETH_STATE_BUSY_RD = 0x82,
HAL_ETH_STATE_TIMEOUT = 0x03, HAL_ETH_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_ETH_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_ETH_STATE_RESET

Peripheral not yet Initialized or disabled

HAL_ETH_STATE_READY

Peripheral Initialized and ready for use

HAL_ETH_STATE_BUSY

an internal process is ongoing

HAL_ETH_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_ETH_STATE_BUSY_RX

Data Reception process is ongoing

HAL_ETH_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_ETH_STATE_BUSY_WR

Write process is ongoing

HAL_ETH_STATE_BUSY_RD

Read process is ongoing

HAL_ETH_STATE_TIMEOUT

Timeout state

HAL_ETH_STATE_ERROR

Reception process is ongoing

Definition at line 370 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_InitTypeDef Struct Reference
ETH Exported Types

ETH Init Structure definition. More...

#include <stm32f7xx_hal_eth.h>

Data Fields

uint32_t | AutoNegotiation
uint32_t | Speed
uint32_t | DuplexMode
uint16_t | PhyAddress
uint8_t * | MACAddr
uint32_t | RxMode
uint32_t | ChecksumMode
uint32_t | MediaInterface

Detailed Description

ETH Init Structure definition.

Definition at line 388 of file stm32f7xx_hal_eth.h.

Field Documentation

uint32_t ETH_InitTypeDef::AutoNegotiation

Selects or not the AutoNegotiation mode for the external PHY The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) and the mode (half/full-duplex). This parameter can be a value of ETH AutoNegotiation

Definition at line 390 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

uint32_t ETH_InitTypeDef::ChecksumMode

Selects if the checksum is check by hardware or by software. This parameter can be a value of ETH Checksum Mode

Definition at line 409 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_Init().

uint32_t ETH_InitTypeDef::DuplexMode

Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode This parameter can be a value of ETH Duplex Mode

Definition at line 398 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC(), and HAL_ETH_Init().

uint8_t* ETH_InitTypeDef::MACAddr

MAC Address of used Hardware: must be pointer on an array of 6 bytes

Definition at line 404 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

uint32_t ETH_InitTypeDef::MediaInterface

Selects the media-independent interface or the reduced media-independent interface. This parameter can be a value of ETH Media Interface

Definition at line 412 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

uint16_t ETH_InitTypeDef::PhyAddress

Ethernet PHY address. This parameter must be a number between Min_Data = 0 and Max_Data = 32

Definition at line 401 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ReadPHYRegister(), and HAL_ETH_WritePHYRegister().

uint32_t ETH_InitTypeDef::RxMode

Selects the Ethernet Rx mode: Polling mode, Interrupt mode. This parameter can be a value of ETH Rx Mode

Definition at line 406 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

uint32_t ETH_InitTypeDef::Speed

Sets the Ethernet speed: 10/100 Mbps. This parameter can be a value of ETH Speed

Definition at line 395 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC(), and HAL_ETH_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_eth.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_MACInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_MACInitTypeDef Struct Reference
ETH Exported Types

ETH MAC Configuration Structure definition. More...

#include <stm32f7xx_hal_eth.h>

Data Fields

uint32_t | Watchdog
uint32_t | Jabber
uint32_t | InterFrameGap
uint32_t | CarrierSense
uint32_t | ReceiveOwn
uint32_t | LoopbackMode
uint32_t | ChecksumOffload
uint32_t | RetryTransmission
uint32_t | AutomaticPadCRCStrip
uint32_t | BackOffLimit
uint32_t | DeferralCheck
uint32_t | ReceiveAll
uint32_t | SourceAddrFilter
uint32_t | PassControlFrames
uint32_t | BroadcastFramesReception
uint32_t | DestinationAddrFilter
uint32_t | PromiscuousMode
uint32_t | MulticastFramesFilter
uint32_t | UnicastFramesFilter
uint32_t | HashTableHigh
uint32_t | HashTableLow
uint32_t | PauseTime
uint32_t | ZeroQuantaPause
uint32_t | PauseLowThreshold
uint32_t | UnicastPauseFrameDetect
uint32_t | ReceiveFlowControl
uint32_t | TransmitFlowControl
uint32_t | VLANTagComparison
uint32_t | VLANTagIdentifier

Detailed Description

ETH MAC Configuration Structure definition.

Definition at line 422 of file stm32f7xx_hal_eth.h.

Field Documentation

uint32_t ETH_MACInitTypeDef::AutomaticPadCRCStrip

Selects or not the Automatic MAC Pad/CRC Stripping. This parameter can be a value of ETH Automatic Pad CRC Strip

Definition at line 455 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::BackOffLimit

Selects the BackOff limit value. This parameter can be a value of ETH Back Off Limit

Definition at line 458 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::BroadcastFramesReception

Selects or not the reception of Broadcast Frames. This parameter can be a value of ETH Broadcast Frames Reception

Definition at line 473 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::CarrierSense

Selects or not the Carrier Sense. This parameter can be a value of ETH Carrier Sense

Definition at line 437 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::ChecksumOffload

Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. This parameter can be a value of ETH Checksum Offload

Definition at line 448 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::DeferralCheck

Selects or not the deferral check function (Half-Duplex mode). This parameter can be a value of ETH Deferral Check

Definition at line 461 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::DestinationAddrFilter

Sets the destination filter mode for both unicast and multicast frames. This parameter can be a value of ETH Destination Addr Filter

Definition at line 476 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::HashTableHigh

This field holds the higher 32 bits of Hash table. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF

Definition at line 488 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::HashTableLow

This field holds the lower 32 bits of Hash table. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF

Definition at line 491 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::InterFrameGap

Selects the minimum IFG between frames during transmission. This parameter can be a value of ETH Inter Frame Gap

Definition at line 434 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::Jabber

Selects or not Jabber timer When enabled, the MAC allows no more then 2048 bytes to be sent. When disabled, the MAC can send up to 16384 bytes. This parameter can be a value of ETH Jabber

Definition at line 429 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::LoopbackMode

Selects or not the internal MAC MII Loopback mode. This parameter can be a value of ETH Loop Back Mode

Definition at line 445 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::MulticastFramesFilter

Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. This parameter can be a value of ETH Multicast Frames Filter

Definition at line 482 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::PassControlFrames

Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) This parameter can be a value of ETH Pass Control Frames

Definition at line 470 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::PauseLowThreshold

This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame. This parameter can be a value of ETH Pause Low Threshold

Definition at line 500 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::PauseTime

This field holds the value to be used in the Pause Time field in the transmit control frame. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF

Definition at line 494 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::PromiscuousMode

Selects or not the Promiscuous Mode This parameter can be a value of ETH Promiscuous Mode

Definition at line 479 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::ReceiveAll

Selects or not all frames reception by the MAC (No filtering). This parameter can be a value of ETH Receive All

Definition at line 464 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::ReceiveFlowControl

Enables or disables the MAC to decode the received Pause frame and disable its transmitter for a specified time (Pause Time) This parameter can be a value of ETH Receive Flow Control

Definition at line 508 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::ReceiveOwn

Selects or not the ReceiveOwn, ReceiveOwn allows the reception of frames when the TX_EN signal is asserted in Half-Duplex mode. This parameter can be a value of ETH Receive Own

Definition at line 440 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::RetryTransmission

Selects or not the MAC attempt retries transmission, based on the settings of BL, when a collision occurs (Half-Duplex mode). This parameter can be a value of ETH Retry Transmission

Definition at line 451 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::SourceAddrFilter

Selects the Source Address Filter mode. This parameter can be a value of ETH Source Addr Filter

Definition at line 467 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::TransmitFlowControl

Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) This parameter can be a value of ETH Transmit Flow Control

Definition at line 512 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::UnicastFramesFilter

Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. This parameter can be a value of ETH Unicast Frames Filter

Definition at line 485 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::UnicastPauseFrameDetect

Selects or not the MAC detection of the Pause frames (with MAC Address0 unicast address and unique multicast address). This parameter can be a value of ETH Unicast Pause Frame Detect

Definition at line 504 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::VLANTagComparison

Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering. This parameter can be a value of ETH VLAN Tag Comparison

Definition at line 516 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::VLANTagIdentifier

Holds the VLAN tag identifier for receive frames

Definition at line 520 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::Watchdog

Selects or not the Watchdog timer When enabled, the MAC allows no more then 2048 bytes to be received. When disabled, the MAC can receive up to 16384 bytes. This parameter can be a value of ETH Watchdog

Definition at line 424 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

uint32_t ETH_MACInitTypeDef::ZeroQuantaPause

Selects or not the automatic generation of Zero-Quanta Pause Control frames. This parameter can be a value of ETH Zero Quanta Pause

Definition at line 497 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_eth.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_DMAInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_DMAInitTypeDef Struct Reference
ETH Exported Types

ETH DMA Configuration Structure definition. More...

#include <stm32f7xx_hal_eth.h>

Data Fields

uint32_t | DropTCPIPChecksumErrorFrame
uint32_t | ReceiveStoreForward
uint32_t | FlushReceivedFrame
uint32_t | TransmitStoreForward
uint32_t | TransmitThresholdControl
uint32_t | ForwardErrorFrames
uint32_t | ForwardUndersizedGoodFrames
uint32_t | ReceiveThresholdControl
uint32_t | SecondFrameOperate
uint32_t | AddressAlignedBeats
uint32_t | FixedBurst
uint32_t | RxDMABurstLength
uint32_t | TxDMABurstLength
uint32_t | EnhancedDescriptorFormat
uint32_t | DescriptorSkipLength
uint32_t | DMAArbitration

Detailed Description

ETH DMA Configuration Structure definition.

Definition at line 529 of file stm32f7xx_hal_eth.h.

Field Documentation

uint32_t ETH_DMAInitTypeDef::AddressAlignedBeats

Enables or disables the Address Aligned Beats. This parameter can be a value of ETH Address Aligned Beats

Definition at line 560 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::DescriptorSkipLength

Specifies the number of word to skip between two unchained descriptors (Ring mode) This parameter must be a number between Min_Data = 0 and Max_Data = 32

Definition at line 575 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::DMAArbitration

Selects the DMA Tx/Rx arbitration. This parameter can be a value of ETH DMA Arbitration

Definition at line 578 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::DropTCPIPChecksumErrorFrame

Selects or not the Dropping of TCP/IP Checksum Error Frames. This parameter can be a value of ETH Drop TCP IP Checksum Error Frame

Definition at line 531 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::EnhancedDescriptorFormat

Enables the enhanced descriptor format. This parameter can be a value of ETH DMA Enhanced descriptor format

Definition at line 572 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::FixedBurst

Enables or disables the AHB Master interface fixed burst transfers. This parameter can be a value of ETH Fixed Burst

Definition at line 563 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::FlushReceivedFrame

Enables or disables the flushing of received frames. This parameter can be a value of ETH Flush Received Frame

Definition at line 537 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::ForwardErrorFrames

Selects or not the forward to the DMA of erroneous frames. This parameter can be a value of ETH Forward Error Frames

Definition at line 546 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::ForwardUndersizedGoodFrames

Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) This parameter can be a value of ETH Forward Undersized Good Frames

Definition at line 549 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::ReceiveStoreForward

Enables or disables the Receive store and forward mode. This parameter can be a value of ETH Receive Store Forward

Definition at line 534 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::ReceiveThresholdControl

Selects the threshold level of the Receive FIFO. This parameter can be a value of ETH Receive Threshold Control

Definition at line 553 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::RxDMABurstLength

Indicates the maximum number of beats to be transferred in one Rx DMA transaction. This parameter can be a value of ETH Rx DMA Burst Length

Definition at line 566 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::SecondFrameOperate

Selects or not the Operate on second frame mode, which allows the DMA to process a second frame of Transmit data even before obtaining the status for the first frame. This parameter can be a value of ETH Second Frame Operate

Definition at line 556 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::TransmitStoreForward

Enables or disables Transmit store and forward mode. This parameter can be a value of ETH Transmit Store Forward

Definition at line 540 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::TransmitThresholdControl

Selects or not the Transmit Threshold Control. This parameter can be a value of ETH Transmit Threshold Control

Definition at line 543 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

uint32_t ETH_DMAInitTypeDef::TxDMABurstLength

Indicates the maximum number of beats to be transferred in one Tx DMA transaction. This parameter can be a value of ETH Tx DMA Burst Length

Definition at line 569 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_eth.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_DMADescTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_DMADescTypeDef Struct Reference
ETH Exported Types

ETH DMA Descriptors data structure definition. More...

#include <stm32f7xx_hal_eth.h>

Data Fields

__IO uint32_t | Status
uint32_t | ControlBufferSize
uint32_t | Buffer1Addr
uint32_t | Buffer2NextDescAddr
uint32_t | ExtendedStatus
uint32_t | Reserved1
uint32_t | TimeStampLow
uint32_t | TimeStampHigh

Detailed Description

ETH DMA Descriptors data structure definition.

Definition at line 587 of file stm32f7xx_hal_eth.h.

Field Documentation

uint32_t ETH_DMADescTypeDef::Buffer1Addr

Buffer1 address pointer

Definition at line 593 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit(), and HAL_ETH_DMATxDescListInit().

uint32_t ETH_DMADescTypeDef::Buffer2NextDescAddr

Buffer2 or next descriptor address pointer Enhanced ETHERNET DMA PTP Descriptors

Definition at line 595 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit(), HAL_ETH_DMATxDescListInit(), HAL_ETH_GetReceivedFrame(), HAL_ETH_GetReceivedFrame_IT(), and HAL_ETH_TransmitFrame().

uint32_t ETH_DMADescTypeDef::ControlBufferSize

Control and Buffer1, Buffer2 lengths

Definition at line 591 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit(), and HAL_ETH_TransmitFrame().

uint32_t ETH_DMADescTypeDef::ExtendedStatus

Extended status for PTP receive descriptor

Definition at line 598 of file stm32f7xx_hal_eth.h.

uint32_t ETH_DMADescTypeDef::Reserved1

Reserved

Definition at line 600 of file stm32f7xx_hal_eth.h.

__IO uint32_t ETH_DMADescTypeDef::Status

Status

Definition at line 589 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit(), HAL_ETH_DMATxDescListInit(), HAL_ETH_GetReceivedFrame(), HAL_ETH_GetReceivedFrame_IT(), and HAL_ETH_TransmitFrame().

uint32_t ETH_DMADescTypeDef::TimeStampHigh

Time Stamp High value for transmit and receive

Definition at line 604 of file stm32f7xx_hal_eth.h.

uint32_t ETH_DMADescTypeDef::TimeStampLow

Time Stamp Low value for transmit and receive

Definition at line 602 of file stm32f7xx_hal_eth.h.

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_eth.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_DMARxFrameInfos Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_DMARxFrameInfos Struct Reference
ETH Exported Types

Received Frame Informations structure definition. More...

#include <stm32f7xx_hal_eth.h>

Data Fields

ETH_DMADescTypeDef * FSRxDesc
ETH_DMADescTypeDef * LSRxDesc
uint32_t | SegCount
uint32_t | length
uint32_t | buffer

Detailed Description

Received Frame Informations structure definition.

Definition at line 612 of file stm32f7xx_hal_eth.h.

Field Documentation

uint32_t ETH_DMARxFrameInfos::buffer

Frame buffer

Definition at line 622 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

ETH_DMADescTypeDef* ETH_DMARxFrameInfos::FSRxDesc

First Segment Rx Desc

Definition at line 614 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame_IT().

uint32_t ETH_DMARxFrameInfos::length

Frame length

Definition at line 620 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

ETH_DMADescTypeDef* ETH_DMARxFrameInfos::LSRxDesc

Last Segment Rx Desc

Definition at line 616 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

uint32_t ETH_DMARxFrameInfos::SegCount

Segment count

Definition at line 618 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_eth.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ETH_HandleTypeDef Struct Reference
ETH Exported Types

ETH Handle Structure definition. More...

#include <stm32f7xx_hal_eth.h>

Data Fields

ETH_TypeDef * | Instance
ETH_InitTypeDef Init
uint32_t | LinkStatus
ETH_DMADescTypeDef * RxDesc
ETH_DMADescTypeDef * TxDesc
ETH_DMARxFrameInfos RxFrameInfos
__IO HAL_ETH_StateTypeDef | State
HAL_LockTypeDef | Lock

Detailed Description

ETH Handle Structure definition.

Definition at line 631 of file stm32f7xx_hal_eth.h.

Field Documentation

ETH_InitTypeDef ETH_HandleTypeDef::Init

Ethernet Init Configuration

Definition at line 635 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), HAL_ETH_ConfigMAC(), HAL_ETH_DMARxDescListInit(), HAL_ETH_DMATxDescListInit(), HAL_ETH_Init(), HAL_ETH_ReadPHYRegister(), and HAL_ETH_WritePHYRegister().

ETH_TypeDef* ETH_HandleTypeDef::Instance

Register base address

Definition at line 633 of file stm32f7xx_hal_eth.h.

Referenced by ETH_DMAReceptionDisable(), ETH_DMAReceptionEnable(), ETH_DMATransmissionDisable(), ETH_DMATransmissionEnable(), ETH_FlushTransmitFIFO(), ETH_MACDMAConfig(), ETH_MACReceptionDisable(), ETH_MACReceptionEnable(), ETH_MACTransmissionDisable(), ETH_MACTransmissionEnable(), HAL_ETH_ConfigDMA(), HAL_ETH_ConfigMAC(), HAL_ETH_DMARxDescListInit(), HAL_ETH_DMATxDescListInit(), HAL_ETH_Init(), HAL_ETH_ReadPHYRegister(), HAL_ETH_TransmitFrame(), and HAL_ETH_WritePHYRegister().

uint32_t ETH_HandleTypeDef::LinkStatus

Ethernet link status

Definition at line 637 of file stm32f7xx_hal_eth.h.

HAL_LockTypeDef ETH_HandleTypeDef::Lock

ETH Lock

Definition at line 647 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

ETH_DMADescTypeDef* ETH_HandleTypeDef::RxDesc

Rx descriptor to Get

Definition at line 639 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit(), HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

ETH_DMARxFrameInfos ETH_HandleTypeDef::RxFrameInfos

last Rx frame infos

Definition at line 643 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

__IO HAL_ETH_StateTypeDef ETH_HandleTypeDef::State

ETH communication state

Definition at line 645 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA(), HAL_ETH_ConfigMAC(), HAL_ETH_DeInit(), HAL_ETH_DMARxDescListInit(), HAL_ETH_DMATxDescListInit(), HAL_ETH_GetReceivedFrame(), HAL_ETH_GetReceivedFrame_IT(), HAL_ETH_GetState(), HAL_ETH_Init(), HAL_ETH_IRQHandler(), HAL_ETH_ReadPHYRegister(), HAL_ETH_Start(), HAL_ETH_Stop(), HAL_ETH_TransmitFrame(), and HAL_ETH_WritePHYRegister().

ETH_DMADescTypeDef* ETH_HandleTypeDef::TxDesc

Tx descriptor to Set

Definition at line 641 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMATxDescListInit(), and HAL_ETH_TransmitFrame().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_eth.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Buffers setting

Defines
ETH Buffers setting
ETH Exported Constants

Defines

#define | ETH_MAX_PACKET_SIZE ((uint32_t)1524)
#define | ETH_HEADER ((uint32_t)14)
#define | ETH_CRC ((uint32_t)4)
#define | ETH_EXTRA ((uint32_t)2)
#define | ETH_VLAN_TAG ((uint32_t)4)
#define | ETH_MIN_ETH_PAYLOAD ((uint32_t)46)
#define | ETH_MAX_ETH_PAYLOAD ((uint32_t)1500)
#define | ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000)
#define | ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
#define | ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#define | ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
#define | ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */

Define Documentation

#define ETH_CRC ((uint32_t)4)

Ethernet CRC

Definition at line 665 of file stm32f7xx_hal_eth.h.

#define ETH_EXTRA ((uint32_t)2)

Extra bytes in some cases

Definition at line 666 of file stm32f7xx_hal_eth.h.

#define ETH_HEADER ((uint32_t)14)

6 byte Dest addr, 6 byte Src addr, 2 byte length/type

Definition at line 664 of file stm32f7xx_hal_eth.h.

#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000)

Jumbo frame payload size

Definition at line 670 of file stm32f7xx_hal_eth.h.

#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500)

Maximum Ethernet payload size

Definition at line 669 of file stm32f7xx_hal_eth.h.

#define ETH_MAX_PACKET_SIZE ((uint32_t)1524)

ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC

Definition at line 663 of file stm32f7xx_hal_eth.h.

#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46)

Minimum Ethernet payload size

Definition at line 668 of file stm32f7xx_hal_eth.h.

#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE

Definition at line 690 of file stm32f7xx_hal_eth.h.

#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */

Definition at line 695 of file stm32f7xx_hal_eth.h.

#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE

Definition at line 717 of file stm32f7xx_hal_eth.h.

#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */

Definition at line 722 of file stm32f7xx_hal_eth.h.

#define ETH_VLAN_TAG ((uint32_t)4)

optional 802.1q VLAN Tag

Definition at line 667 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA TX Descriptor

Defines
ETH DMA TX Descriptor
ETH Exported Constants

Defines

#define | ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
Bit definition of TDES0 register: DMA Tx descriptor status register.
#define | ETH_DMATXDESC_IC ((uint32_t)0x40000000)
#define | ETH_DMATXDESC_LS ((uint32_t)0x20000000)
#define | ETH_DMATXDESC_FS ((uint32_t)0x10000000)
#define | ETH_DMATXDESC_DC ((uint32_t)0x08000000)
#define | ETH_DMATXDESC_DP ((uint32_t)0x04000000)
#define | ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)
#define | ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)
#define | ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
#define | ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)
#define | ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)
#define | ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)
#define | ETH_DMATXDESC_TER ((uint32_t)0x00200000)
#define | ETH_DMATXDESC_TCH ((uint32_t)0x00100000)
#define | ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
#define | ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
#define | ETH_DMATXDESC_ES ((uint32_t)0x00008000)
#define | ETH_DMATXDESC_JT ((uint32_t)0x00004000)
#define | ETH_DMATXDESC_FF ((uint32_t)0x00002000)
#define | ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
#define | ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
#define | ETH_DMATXDESC_NC ((uint32_t)0x00000400)
#define | ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
#define | ETH_DMATXDESC_EC ((uint32_t)0x00000100)
#define | ETH_DMATXDESC_VF ((uint32_t)0x00000080)
#define | ETH_DMATXDESC_CC ((uint32_t)0x00000078)
#define | ETH_DMATXDESC_ED ((uint32_t)0x00000004)
#define | ETH_DMATXDESC_UF ((uint32_t)0x00000002)
#define | ETH_DMATXDESC_DB ((uint32_t)0x00000001)
#define | ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000)
Bit definition of TDES1 register.
#define | ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF)
#define | ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES2 register.
#define | ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES3 register.
#define | ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
#define | ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */

Define Documentation

#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */

Definition at line 805 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */

Definition at line 802 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)

Bit definition of TDES2 register.

Buffer1 Address Pointer

Definition at line 788 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)

Bit definition of TDES3 register.

Buffer2 Address Pointer

Definition at line 793 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CC ((uint32_t)0x00000078)

Collision Count

Definition at line 774 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)

Checksum Insertion Control: 4 cases

Definition at line 756 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)

Do Nothing: Checksum Engine is bypassed

Definition at line 757 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)

IPV4 header Checksum Insertion

Definition at line 758 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)

TCP/UDP/ICMP Checksum Insertion fully calculated

Definition at line 760 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)

TCP/UDP/ICMP Checksum Insertion calculated over segment only

Definition at line 759 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_DB ((uint32_t)0x00000001)

Deferred Bit

Definition at line 777 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_DC ((uint32_t)0x08000000)

Disable CRC

Definition at line 753 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_DP ((uint32_t)0x04000000)

Disable Padding

Definition at line 754 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_EC ((uint32_t)0x00000100)

Excessive Collision: transmission aborted after 16 collisions

Definition at line 772 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_ED ((uint32_t)0x00000004)

Excessive Deferral

Definition at line 775 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_ES ((uint32_t)0x00008000)

Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT

Definition at line 765 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_FF ((uint32_t)0x00002000)

Frame Flushed: DMA/MTL flushed the frame due to SW flush

Definition at line 767 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_FS ((uint32_t)0x10000000)

First Segment

Definition at line 752 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_TransmitFrame().

#define ETH_DMATXDESC_IC ((uint32_t)0x40000000)

Interrupt on Completion

Definition at line 750 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)

IP Header Error

Definition at line 764 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_JT ((uint32_t)0x00004000)

Jabber Timeout

Definition at line 766 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)

Loss of Carrier: carrier lost during transmission

Definition at line 769 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)

Late Collision: transmission aborted due to collision

Definition at line 771 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_LS ((uint32_t)0x20000000)

Last Segment

Definition at line 751 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_TransmitFrame().

#define ETH_DMATXDESC_NC ((uint32_t)0x00000400)

No Carrier: no carrier signal from the transceiver

Definition at line 770 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)

Bit definition of TDES0 register: DMA Tx descriptor status register.

OWN bit: descriptor is owned by DMA engine

Definition at line 749 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_TransmitFrame().

#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)

Payload Checksum Error

Definition at line 768 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF)

Transmit Buffer1 Size

Definition at line 783 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_TransmitFrame().

#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000)

Bit definition of TDES1 register.

Transmit Buffer2 Size

Definition at line 782 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000)

Second Address Chained

Definition at line 762 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMATxDescListInit().

#define ETH_DMATXDESC_TER ((uint32_t)0x00200000)

Transmit End of Ring

Definition at line 761 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)

Transmit Time Stamp Enable

Definition at line 755 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)

Tx Time Stamp Status

Definition at line 763 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_UF ((uint32_t)0x00000002)

Underflow Error: late data arrival from the memory

Definition at line 776 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_VF ((uint32_t)0x00000080)

VLAN Frame

Definition at line 773 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA RX Descriptor

Defines
ETH DMA RX Descriptor
ETH Exported Constants

Defines

#define | ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
Bit definition of RDES0 register: DMA Rx descriptor status register.
#define | ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
#define | ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
#define | ETH_DMARXDESC_ES ((uint32_t)0x00008000)
#define | ETH_DMARXDESC_DE ((uint32_t)0x00004000)
#define | ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
#define | ETH_DMARXDESC_LE ((uint32_t)0x00001000)
#define | ETH_DMARXDESC_OE ((uint32_t)0x00000800)
#define | ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
#define | ETH_DMARXDESC_FS ((uint32_t)0x00000200)
#define | ETH_DMARXDESC_LS ((uint32_t)0x00000100)
#define | ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
#define | ETH_DMARXDESC_LC ((uint32_t)0x00000040)
#define | ETH_DMARXDESC_FT ((uint32_t)0x00000020)
#define | ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
#define | ETH_DMARXDESC_RE ((uint32_t)0x00000008)
#define | ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
#define | ETH_DMARXDESC_CE ((uint32_t)0x00000002)
#define | ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
#define | ETH_DMARXDESC_DIC ((uint32_t)0x80000000)
Bit definition of RDES1 register.
#define | ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000)
#define | ETH_DMARXDESC_RER ((uint32_t)0x00008000)
#define | ETH_DMARXDESC_RCH ((uint32_t)0x00004000)
#define | ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF)
#define | ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)
Bit definition of RDES2 register.
#define | ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)
Bit definition of RDES3 register.
#define | ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
#define | ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
#define | ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
#define | ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
#define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
#define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
#define | ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
#define | ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
#define | ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
#define | ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
#define | ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
#define | ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
#define | ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
#define | ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
#define | ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
#define | ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
#define | ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */

Define Documentation

#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */

Definition at line 892 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */

Definition at line 894 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */

Definition at line 893 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */

Definition at line 895 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */

Definition at line 898 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */

Definition at line 897 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */

Definition at line 896 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */

Definition at line 891 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */

Definition at line 890 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */

Definition at line 881 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */

Definition at line 882 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */

Definition at line 885 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */

Definition at line 886 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */

Definition at line 884 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */

Definition at line 887 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */

Definition at line 888 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */

Definition at line 889 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */

Definition at line 883 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */

Definition at line 880 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */

Definition at line 904 of file stm32f7xx_hal_eth.h.

#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */

Definition at line 901 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)

DA Filter Fail for the rx frame

Definition at line 831 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)

Bit definition of RDES2 register.

Buffer1 Address Pointer

Definition at line 862 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)

Bit definition of RDES3 register.

Buffer2 Address Pointer

Definition at line 867 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_CE ((uint32_t)0x00000002)

CRC error

Definition at line 847 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)

Dribble bit error: frame contains non int multiple of 8 bits

Definition at line 846 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_DE ((uint32_t)0x00004000)

Descriptor error: no more descriptors for receive frame

Definition at line 834 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000)

Bit definition of RDES1 register.

Disable Interrupt on Completion

Definition at line 853 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit().

#define ETH_DMARXDESC_ES ((uint32_t)0x00008000)

Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE

Definition at line 833 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)

Receive descriptor frame length

Definition at line 832 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

#define ETH_DMARXDESC_FS ((uint32_t)0x00000200)

First descriptor of the frame

Definition at line 839 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

#define ETH_DMARXDESC_FT ((uint32_t)0x00000020)

Frame type - Ethernet, otherwise 802.3

Definition at line 843 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)

IPC Checksum Error: Rx Ipv4 header checksum error

Definition at line 841 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_LC ((uint32_t)0x00000040)

Late collision occurred during reception

Definition at line 842 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_LE ((uint32_t)0x00001000)

Frame size not matching with length field

Definition at line 836 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_LS ((uint32_t)0x00000100)

Last descriptor of the frame

Definition at line 840 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)

Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error

Definition at line 848 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_OE ((uint32_t)0x00000800)

Overflow Error: Frame was damaged due to buffer overflow

Definition at line 837 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)

Bit definition of RDES0 register: DMA Rx descriptor status register.

OWN bit: descriptor is owned by DMA engine

Definition at line 830 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit(), HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF)

Receive Buffer1 Size

Definition at line 857 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000)

Receive Buffer2 Size

Definition at line 854 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000)

Second Address Chained

Definition at line 856 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMARxDescListInit().

#define ETH_DMARXDESC_RE ((uint32_t)0x00000008)

Receive error: error reported by MII interface

Definition at line 845 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_RER ((uint32_t)0x00008000)

Receive End of Ring

Definition at line 855 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)

Receive Watchdog Timeout: watchdog timer expired during reception

Definition at line 844 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)

SA Filter Fail for the received frame

Definition at line 835 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)

VLAN Tag: received frame is a VLAN frame

Definition at line 838 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH AutoNegotiation

Defines
ETH AutoNegotiation
ETH Exported Constants

Defines

#define | ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
#define | ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)

Definition at line 912 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)

Definition at line 911 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Speed

Defines
ETH Speed
ETH Exported Constants

Defines

#define | ETH_SPEED_10M ((uint32_t)0x00000000)
#define | ETH_SPEED_100M ((uint32_t)0x00004000)

Define Documentation

#define ETH_SPEED_100M ((uint32_t)0x00004000)

Definition at line 921 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_Init().

#define ETH_SPEED_10M ((uint32_t)0x00000000)

Definition at line 920 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

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STM32F745xx HAL User Manual: ETH Duplex Mode

Defines
ETH Duplex Mode
ETH Exported Constants

Defines

#define | ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
#define | ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)

Define Documentation

#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)

Definition at line 929 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_Init().

#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)

Definition at line 930 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Rx Mode

Defines
ETH Rx Mode
ETH Exported Constants

Defines

#define | ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
#define | ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)

Define Documentation

#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)

Definition at line 938 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_DMARxDescListInit().

#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)

Definition at line 937 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH Checksum Mode

Defines
ETH Checksum Mode
ETH Exported Constants

Defines

#define | ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
#define | ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)

Define Documentation

#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)

Definition at line 946 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_DMATxDescListInit().

#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)

Definition at line 947 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Media Interface

Defines
ETH Media Interface
ETH Exported Constants

Defines

#define | ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
#define | ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)

Define Documentation

#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)

Definition at line 955 of file stm32f7xx_hal_eth.h.

#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)

Definition at line 956 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Watchdog

Defines
ETH Watchdog
ETH Exported Constants

Defines

#define | ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
#define | ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)

Define Documentation

#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)

Definition at line 965 of file stm32f7xx_hal_eth.h.

#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)

Definition at line 964 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Jabber

Defines
ETH Jabber
ETH Exported Constants

Defines

#define | ETH_JABBER_ENABLE ((uint32_t)0x00000000)
#define | ETH_JABBER_DISABLE ((uint32_t)0x00400000)

Define Documentation

#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)

Definition at line 974 of file stm32f7xx_hal_eth.h.

#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)

Definition at line 973 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Inter Frame Gap

Defines
ETH Inter Frame Gap
ETH Exported Constants

Defines

#define | ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000)
#define | ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000)
#define | ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000)
#define | ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000)
#define | ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000)
#define | ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000)
#define | ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000)
#define | ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000)

Define Documentation

#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000)

minimum IFG between frames during transmission is 40Bit

Definition at line 989 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000)

minimum IFG between frames during transmission is 48Bit

Definition at line 988 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000)

minimum IFG between frames during transmission is 56Bit

Definition at line 987 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000)

minimum IFG between frames during transmission is 64Bit

Definition at line 986 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000)

minimum IFG between frames during transmission is 72Bit

Definition at line 985 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000)

minimum IFG between frames during transmission is 80Bit

Definition at line 984 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000)

minimum IFG between frames during transmission is 88Bit

Definition at line 983 of file stm32f7xx_hal_eth.h.

#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000)

minimum IFG between frames during transmission is 96Bit

Definition at line 982 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Carrier Sense

Defines
ETH Carrier Sense
ETH Exported Constants

Defines

#define | ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
#define | ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)

Define Documentation

#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)

Definition at line 998 of file stm32f7xx_hal_eth.h.

#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)

Definition at line 997 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Receive Own

Defines
ETH Receive Own
ETH Exported Constants

Defines

#define | ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
#define | ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)

Define Documentation

#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)

Definition at line 1007 of file stm32f7xx_hal_eth.h.

#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)

Definition at line 1006 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Loop Back Mode

Defines
ETH Loop Back Mode
ETH Exported Constants

Defines

#define | ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
#define | ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)

Definition at line 1016 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)

Definition at line 1015 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Checksum Offload

Defines
ETH Checksum Offload
ETH Exported Constants

Defines

#define | ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
#define | ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)

Definition at line 1025 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)

Definition at line 1024 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Retry Transmission

Defines
ETH Retry Transmission
ETH Exported Constants

Defines

#define | ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
#define | ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)

Define Documentation

#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)

Definition at line 1034 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)

Definition at line 1033 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Automatic Pad CRC Strip

Defines
ETH Automatic Pad CRC Strip
ETH Exported Constants

Defines

#define | ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
#define | ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)

Definition at line 1043 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)

Definition at line 1042 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH Back Off Limit

Defines
ETH Back Off Limit
ETH Exported Constants

Defines

#define | ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
#define | ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
#define | ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
#define | ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)

Define Documentation

#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)

Definition at line 1054 of file stm32f7xx_hal_eth.h.

#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)

Definition at line 1051 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)

Definition at line 1053 of file stm32f7xx_hal_eth.h.

#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)

Definition at line 1052 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Deferral Check

Defines
ETH Deferral Check
ETH Exported Constants

Defines

#define | ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
#define | ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)

Definition at line 1063 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)

Definition at line 1062 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Receive All

Defines
ETH Receive All
ETH Exported Constants

Defines

#define | ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
#define | ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)

Definition at line 1072 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)

Definition at line 1071 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Source Addr Filter

Defines
ETH Source Addr Filter
ETH Exported Constants

Defines

#define | ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
#define | ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
#define | ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)

Definition at line 1082 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)

Definition at line 1081 of file stm32f7xx_hal_eth.h.

#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)

Definition at line 1080 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Pass Control Frames

Defines
ETH Pass Control Frames
ETH Exported Constants

Defines

#define | ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040)
#define | ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080)
#define | ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)

Define Documentation

#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040)

MAC filters all control frames from reaching the application

Definition at line 1090 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080)

MAC forwards all control frames to application even if they fail the Address Filter

Definition at line 1091 of file stm32f7xx_hal_eth.h.

#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)

MAC forwards control frames that pass the Address Filter.

Definition at line 1092 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Broadcast Frames Reception

Defines
ETH Broadcast Frames Reception
ETH Exported Constants

Defines

#define | ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
#define | ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)

Define Documentation

#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)

Definition at line 1101 of file stm32f7xx_hal_eth.h.

#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)

Definition at line 1100 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Destination Addr Filter

Defines
ETH Destination Addr Filter
ETH Exported Constants

Defines

#define | ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
#define | ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)

Define Documentation

#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)

Definition at line 1110 of file stm32f7xx_hal_eth.h.

#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)

Definition at line 1109 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Promiscuous Mode

Defines
ETH Promiscuous Mode
ETH Exported Constants

Defines

#define | ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
#define | ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)

Definition at line 1119 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)

Definition at line 1118 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Multicast Frames Filter

Defines
ETH Multicast Frames Filter
ETH Exported Constants

Defines

#define | ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
#define | ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
#define | ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
#define | ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)

Define Documentation

#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)

Definition at line 1128 of file stm32f7xx_hal_eth.h.

#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)

Definition at line 1130 of file stm32f7xx_hal_eth.h.

#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)

Definition at line 1129 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)

Definition at line 1127 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Unicast Frames Filter

Defines
ETH Unicast Frames Filter
ETH Exported Constants

Defines

#define | ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
#define | ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
#define | ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)

Define Documentation

#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)

Definition at line 1139 of file stm32f7xx_hal_eth.h.

#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)

Definition at line 1140 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)

Definition at line 1138 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Zero Quanta Pause

Defines
ETH Zero Quanta Pause
ETH Exported Constants

Defines

#define | ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
#define | ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)

Define Documentation

#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)

Definition at line 1149 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)

Definition at line 1148 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Pause Low Threshold

Defines
ETH Pause Low Threshold
ETH Exported Constants

Defines

#define | ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000)
#define | ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010)
#define | ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020)
#define | ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030)

Define Documentation

#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020)

Pause time minus 144 slot times

Definition at line 1159 of file stm32f7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030)

Pause time minus 256 slot times

Definition at line 1160 of file stm32f7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010)

Pause time minus 28 slot times

Definition at line 1158 of file stm32f7xx_hal_eth.h.

#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000)

Pause time minus 4 slot times

Definition at line 1157 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Unicast Pause Frame Detect

Defines
ETH Unicast Pause Frame Detect
ETH Exported Constants

Defines

#define | ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
#define | ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)

Definition at line 1169 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)

Definition at line 1168 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Receive Flow Control

Defines
ETH Receive Flow Control
ETH Exported Constants

Defines

#define | ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
#define | ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)

Definition at line 1178 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)

Definition at line 1177 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Transmit Flow Control

Defines
ETH Transmit Flow Control
ETH Exported Constants

Defines

#define | ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
#define | ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)

Definition at line 1187 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)

Definition at line 1186 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH VLAN Tag Comparison

Defines
ETH VLAN Tag Comparison
ETH Exported Constants

Defines

#define | ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
#define | ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)

Define Documentation

#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)

Definition at line 1195 of file stm32f7xx_hal_eth.h.

#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)

Definition at line 1196 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH MAC addresses

Defines
ETH MAC addresses
ETH Exported Constants

Defines

#define | ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
#define | ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
#define | ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
#define | ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)

Define Documentation

#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)

Definition at line 1204 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)

Definition at line 1205 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)

Definition at line 1206 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)

Definition at line 1207 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH MAC addresses filter SA DA

Defines
ETH MAC addresses filter SA DA
ETH Exported Constants

Defines

#define | ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
#define | ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)

Define Documentation

#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)

Definition at line 1216 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)

Definition at line 1215 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH MAC addresses filter Mask bytes

Defines
ETH MAC addresses filter Mask bytes
ETH Exported Constants

Defines

#define | ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000)
#define | ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000)
#define | ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000)
#define | ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000)
#define | ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000)
#define | ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000)

Define Documentation

#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000)

Mask MAC Address low reg bits [70]

Definition at line 1229 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000)

Mask MAC Address low reg bits [15:8]

Definition at line 1228 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000)

Mask MAC Address low reg bits [23:16]

Definition at line 1227 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000)

Mask MAC Address low reg bits [31:24]

Definition at line 1226 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000)

Mask MAC Address high reg bits [7:0]

Definition at line 1225 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000)

Mask MAC Address high reg bits [15:8]

Definition at line 1224 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH MAC Debug flags

Defines
ETH MAC Debug flags
ETH Exported Constants

Defines

#define | ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define | ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define | ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define | ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define | ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define | ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define | ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define | ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define | ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define | ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define | ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define | ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define | ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#define | ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define | ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define | ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define | ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define | ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define | ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define | ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define | ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define | ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define | ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */

Define Documentation

#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */

Definition at line 1263 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */

Definition at line 1249 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */

Definition at line 1257 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */

Definition at line 1254 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */

Definition at line 1255 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */

Definition at line 1256 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */

Definition at line 1252 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */

Definition at line 1251 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */

Definition at line 1250 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */

Definition at line 1253 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */

Definition at line 1258 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */

Definition at line 1259 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */

Definition at line 1260 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */

Definition at line 1262 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */

Definition at line 1261 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */

Definition at line 1244 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */

Definition at line 1247 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */

Definition at line 1245 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */

Definition at line 1248 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */

Definition at line 1246 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */

Definition at line 1237 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */

Definition at line 1240 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */

Definition at line 1241 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */

Definition at line 1242 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */

Definition at line 1239 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */

Definition at line 1243 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */

Definition at line 1238 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Drop TCP IP Checksum Error Frame

Defines
ETH Drop TCP IP Checksum Error Frame
ETH Exported Constants

Defines

#define | ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
#define | ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)

Define Documentation

#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)

Definition at line 1272 of file stm32f7xx_hal_eth.h.

#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)

Definition at line 1271 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Receive Store Forward

Defines
ETH Receive Store Forward
ETH Exported Constants

Defines

#define | ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
#define | ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)

Definition at line 1281 of file stm32f7xx_hal_eth.h.

#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)

Definition at line 1280 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Flush Received Frame

Defines
ETH Flush Received Frame
ETH Exported Constants

Defines

#define | ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
#define | ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)

Define Documentation

#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)

Definition at line 1290 of file stm32f7xx_hal_eth.h.

#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)

Definition at line 1289 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Transmit Store Forward

Defines
ETH Transmit Store Forward
ETH Exported Constants

Defines

#define | ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
#define | ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)

Definition at line 1299 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)

Definition at line 1298 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Transmit Threshold Control

Defines
ETH Transmit Threshold Control
ETH Exported Constants

Defines

#define | ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000)

Define Documentation

#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000)

threshold level of the MTL Transmit FIFO is 128 Bytes

Definition at line 1308 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000)

threshold level of the MTL Transmit FIFO is 16 Bytes

Definition at line 1314 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000)

threshold level of the MTL Transmit FIFO is 192 Bytes

Definition at line 1309 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000)

threshold level of the MTL Transmit FIFO is 24 Bytes

Definition at line 1313 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000)

threshold level of the MTL Transmit FIFO is 256 Bytes

Definition at line 1310 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000)

threshold level of the MTL Transmit FIFO is 32 Bytes

Definition at line 1312 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000)

threshold level of the MTL Transmit FIFO is 40 Bytes

Definition at line 1311 of file stm32f7xx_hal_eth.h.

#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)

threshold level of the MTL Transmit FIFO is 64 Bytes

Definition at line 1307 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Forward Error Frames

Defines
ETH Forward Error Frames
ETH Exported Constants

Defines

#define | ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
#define | ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)

Definition at line 1323 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)

Definition at line 1322 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Forward Undersized Good Frames

Defines
ETH Forward Undersized Good Frames
ETH Exported Constants

Defines

#define | ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
#define | ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)

Definition at line 1332 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)

Definition at line 1331 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Receive Threshold Control

Defines
ETH Receive Threshold Control
ETH Exported Constants

Defines

#define | ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018)

Define Documentation

#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018)

threshold level of the MTL Receive FIFO is 128 Bytes

Definition at line 1343 of file stm32f7xx_hal_eth.h.

#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008)

threshold level of the MTL Receive FIFO is 32 Bytes

Definition at line 1341 of file stm32f7xx_hal_eth.h.

#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)

threshold level of the MTL Receive FIFO is 64 Bytes

Definition at line 1340 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010)

threshold level of the MTL Receive FIFO is 96 Bytes

Definition at line 1342 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Second Frame Operate

Defines
ETH Second Frame Operate
ETH Exported Constants

Defines

#define | ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
#define | ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)

Definition at line 1352 of file stm32f7xx_hal_eth.h.

#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)

Definition at line 1351 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Address Aligned Beats

Defines
ETH Address Aligned Beats
ETH Exported Constants

Defines

#define | ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
#define | ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)

Definition at line 1361 of file stm32f7xx_hal_eth.h.

#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)

Definition at line 1360 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Fixed Burst

Defines
ETH Fixed Burst
ETH Exported Constants

Defines

#define | ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
#define | ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)

Definition at line 1370 of file stm32f7xx_hal_eth.h.

#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)

Definition at line 1369 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Rx DMA Burst Length

Defines
ETH Rx DMA Burst Length
ETH Exported Constants

Defines

#define | ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000)
#define | ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000)
#define | ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000)
#define | ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000)
#define | ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000)
#define | ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000)

Define Documentation

#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000)

maximum number of beats to be transferred in one RxDMA transaction is 16

Definition at line 1382 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000)

maximum number of beats to be transferred in one RxDMA transaction is 1

Definition at line 1378 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000)

maximum number of beats to be transferred in one RxDMA transaction is 2

Definition at line 1379 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000)

maximum number of beats to be transferred in one RxDMA transaction is 32

Definition at line 1383 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000)

maximum number of beats to be transferred in one RxDMA transaction is 4

Definition at line 1380 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000)

maximum number of beats to be transferred in one RxDMA transaction is 128

Definition at line 1389 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000)

maximum number of beats to be transferred in one RxDMA transaction is 16

Definition at line 1386 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000)

maximum number of beats to be transferred in one RxDMA transaction is 32

Definition at line 1387 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000)

maximum number of beats to be transferred in one RxDMA transaction is 4

Definition at line 1384 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000)

maximum number of beats to be transferred in one RxDMA transaction is 64

Definition at line 1388 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000)

maximum number of beats to be transferred in one RxDMA transaction is 8

Definition at line 1385 of file stm32f7xx_hal_eth.h.

#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000)

maximum number of beats to be transferred in one RxDMA transaction is 8

Definition at line 1381 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Tx DMA Burst Length

Defines
ETH Tx DMA Burst Length
ETH Exported Constants

Defines

#define | ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100)
#define | ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200)
#define | ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400)
#define | ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800)
#define | ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000)
#define | ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000)
#define | ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100)
#define | ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200)
#define | ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400)
#define | ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800)
#define | ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000)
#define | ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000)

Define Documentation

#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 16

Definition at line 1401 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 1

Definition at line 1397 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 2

Definition at line 1398 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 32

Definition at line 1402 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 4

Definition at line 1399 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 128

Definition at line 1408 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 16

Definition at line 1405 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 32

Definition at line 1406 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 4

Definition at line 1403 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 64

Definition at line 1407 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 8

Definition at line 1404 of file stm32f7xx_hal_eth.h.

#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800)

maximum number of beats to be transferred in one TxDMA (or both) transaction is 8

Definition at line 1400 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA Enhanced descriptor format

Defines
ETH DMA Enhanced descriptor format
ETH Exported Constants

Defines

#define | ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
#define | ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)

Definition at line 1417 of file stm32f7xx_hal_eth.h.

#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)

Definition at line 1416 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA Arbitration

Defines
ETH DMA Arbitration
ETH Exported Constants

Defines

#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
#define | ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)

Define Documentation

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)

Definition at line 1425 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)

Definition at line 1426 of file stm32f7xx_hal_eth.h.

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)

Definition at line 1427 of file stm32f7xx_hal_eth.h.

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)

Definition at line 1428 of file stm32f7xx_hal_eth.h.

#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)

Definition at line 1429 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA Tx descriptor segment

Defines
ETH DMA Tx descriptor segment
ETH Exported Constants

Defines

#define | ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000)
#define | ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000)

Define Documentation

#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000)

First Segment

Definition at line 1438 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000)

Last Segment

Definition at line 1437 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA Tx descriptor Checksum Insertion Control

Defines
ETH DMA Tx descriptor Checksum Insertion Control
ETH Exported Constants

Defines

#define | ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000)
#define | ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000)
#define | ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000)
#define | ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000)

Define Documentation

#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000)

Checksum engine bypass

Definition at line 1446 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000)

IPv4 header checksum insertion

Definition at line 1447 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000)

TCP/UDP/ICMP checksum fully in hardware including pseudo header

Definition at line 1449 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_DMATxDescListInit().

#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000)

TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present

Definition at line 1448 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA Rx descriptor buffers

Defines
ETH DMA Rx descriptor buffers
ETH Exported Constants

Defines

#define | ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000)
#define | ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001)

Define Documentation

#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000)

DMA Rx Desc Buffer1

Definition at line 1457 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001)

DMA Rx Desc Buffer2

Definition at line 1458 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH PMT Flags

Defines
ETH PMT Flags
ETH Exported Constants

Defines

#define | ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000)
#define | ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040)
#define | ETH_PMT_FLAG_MPR ((uint32_t)0x00000020)

Define Documentation

#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020)

Magic Packet Received

Definition at line 1468 of file stm32f7xx_hal_eth.h.

#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000)

Wake-Up Frame Filter Register Pointer Reset

Definition at line 1466 of file stm32f7xx_hal_eth.h.

#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040)

Wake-Up Frame Received

Definition at line 1467 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH MMC Tx Interrupts

Defines
ETH MMC Tx Interrupts
ETH Exported Constants

Defines

#define | ETH_MMC_IT_TGF ((uint32_t)0x00200000)
#define | ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000)
#define | ETH_MMC_IT_TGFSC ((uint32_t)0x00004000)

Define Documentation

#define ETH_MMC_IT_TGF ((uint32_t)0x00200000)

When Tx good frame counter reaches half the maximum value

Definition at line 1476 of file stm32f7xx_hal_eth.h.

#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000)

When Tx good multi col counter reaches half the maximum value

Definition at line 1477 of file stm32f7xx_hal_eth.h.

#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000)

When Tx good single col counter reaches half the maximum value

Definition at line 1478 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH MMC Rx Interrupts

Defines
ETH MMC Rx Interrupts
ETH Exported Constants

Defines

#define | ETH_MMC_IT_RGUF ((uint32_t)0x10020000)
#define | ETH_MMC_IT_RFAE ((uint32_t)0x10000040)
#define | ETH_MMC_IT_RFCE ((uint32_t)0x10000020)

Define Documentation

#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040)

When Rx alignment error counter reaches half the maximum value

Definition at line 1487 of file stm32f7xx_hal_eth.h.

#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020)

When Rx crc error counter reaches half the maximum value

Definition at line 1488 of file stm32f7xx_hal_eth.h.

#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000)

When Rx good unicast frames counter reaches half the maximum value

Definition at line 1486 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH MAC Flags

Defines
ETH MAC Flags
ETH Exported Constants

Defines

#define | ETH_MAC_FLAG_TST ((uint32_t)0x00000200)
#define | ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040)
#define | ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020)
#define | ETH_MAC_FLAG_MMC ((uint32_t)0x00000010)
#define | ETH_MAC_FLAG_PMT ((uint32_t)0x00000008)

Define Documentation

#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010)

MMC flag (on MAC)

Definition at line 1499 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020)

MMC receive flag

Definition at line 1498 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040)

MMC transmit flag

Definition at line 1497 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008)

PMT flag (on MAC)

Definition at line 1500 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200)

Time stamp trigger flag (on MAC)

Definition at line 1496 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA Flags

Defines
ETH DMA Flags
ETH Exported Constants

Defines

#define | ETH_DMA_FLAG_TST ((uint32_t)0x20000000)
#define | ETH_DMA_FLAG_PMT ((uint32_t)0x10000000)
#define | ETH_DMA_FLAG_MMC ((uint32_t)0x08000000)
#define | ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)
#define | ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000)
#define | ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000)
#define | ETH_DMA_FLAG_NIS ((uint32_t)0x00010000)
#define | ETH_DMA_FLAG_AIS ((uint32_t)0x00008000)
#define | ETH_DMA_FLAG_ER ((uint32_t)0x00004000)
#define | ETH_DMA_FLAG_FBE ((uint32_t)0x00002000)
#define | ETH_DMA_FLAG_ET ((uint32_t)0x00000400)
#define | ETH_DMA_FLAG_RWT ((uint32_t)0x00000200)
#define | ETH_DMA_FLAG_RPS ((uint32_t)0x00000100)
#define | ETH_DMA_FLAG_RBU ((uint32_t)0x00000080)
#define | ETH_DMA_FLAG_R ((uint32_t)0x00000040)
#define | ETH_DMA_FLAG_TU ((uint32_t)0x00000020)
#define | ETH_DMA_FLAG_RO ((uint32_t)0x00000010)
#define | ETH_DMA_FLAG_TJT ((uint32_t)0x00000008)
#define | ETH_DMA_FLAG_TBU ((uint32_t)0x00000004)
#define | ETH_DMA_FLAG_TPS ((uint32_t)0x00000002)
#define | ETH_DMA_FLAG_T ((uint32_t)0x00000001)

Define Documentation

#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000)

Error bits 0-data buffer, 1-desc. access

Definition at line 1513 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000)

Abnormal interrupt summary flag

Definition at line 1515 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)

Error bits 0-Rx DMA, 1-Tx DMA

Definition at line 1511 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000)

Early receive flag

Definition at line 1516 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400)

Early transmit flag

Definition at line 1518 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000)

Fatal bus error flag

Definition at line 1517 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000)

MMC interrupt (on DMA)

Definition at line 1510 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000)

Normal interrupt summary flag

Definition at line 1514 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000)

PMT interrupt (on DMA)

Definition at line 1509 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_R ((uint32_t)0x00000040)

Receive flag

Definition at line 1522 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080)

Receive buffer unavailable flag

Definition at line 1521 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000)

Error bits 0-write transfer, 1-read transfer

Definition at line 1512 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010)

Overflow flag

Definition at line 1524 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100)

Receive process stopped flag

Definition at line 1520 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200)

Receive watchdog timeout flag

Definition at line 1519 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_T ((uint32_t)0x00000001)

Transmit flag

Definition at line 1528 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004)

Transmit buffer unavailable flag

Definition at line 1526 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008)

Transmit jabber timeout flag

Definition at line 1525 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002)

Transmit process stopped flag

Definition at line 1527 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000)

Time-stamp trigger interrupt (on DMA)

Definition at line 1508 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020)

Underflow flag

Definition at line 1523 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH MAC Interrupts

Defines
ETH MAC Interrupts
ETH Exported Constants

Defines

#define | ETH_MAC_IT_TST ((uint32_t)0x00000200)
#define | ETH_MAC_IT_MMCT ((uint32_t)0x00000040)
#define | ETH_MAC_IT_MMCR ((uint32_t)0x00000020)
#define | ETH_MAC_IT_MMC ((uint32_t)0x00000010)
#define | ETH_MAC_IT_PMT ((uint32_t)0x00000008)

Define Documentation

#define ETH_MAC_IT_MMC ((uint32_t)0x00000010)

MMC interrupt (on MAC)

Definition at line 1539 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020)

MMC receive interrupt

Definition at line 1538 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040)

MMC transmit interrupt

Definition at line 1537 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_IT_PMT ((uint32_t)0x00000008)

PMT interrupt (on MAC)

Definition at line 1540 of file stm32f7xx_hal_eth.h.

#define ETH_MAC_IT_TST ((uint32_t)0x00000200)

Time stamp trigger interrupt (on MAC)

Definition at line 1536 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH DMA Interrupts

Defines
ETH DMA Interrupts
ETH Exported Constants

Defines

#define | ETH_DMA_IT_TST ((uint32_t)0x20000000)
#define | ETH_DMA_IT_PMT ((uint32_t)0x10000000)
#define | ETH_DMA_IT_MMC ((uint32_t)0x08000000)
#define | ETH_DMA_IT_NIS ((uint32_t)0x00010000)
#define | ETH_DMA_IT_AIS ((uint32_t)0x00008000)
#define | ETH_DMA_IT_ER ((uint32_t)0x00004000)
#define | ETH_DMA_IT_FBE ((uint32_t)0x00002000)
#define | ETH_DMA_IT_ET ((uint32_t)0x00000400)
#define | ETH_DMA_IT_RWT ((uint32_t)0x00000200)
#define | ETH_DMA_IT_RPS ((uint32_t)0x00000100)
#define | ETH_DMA_IT_RBU ((uint32_t)0x00000080)
#define | ETH_DMA_IT_R ((uint32_t)0x00000040)
#define | ETH_DMA_IT_TU ((uint32_t)0x00000020)
#define | ETH_DMA_IT_RO ((uint32_t)0x00000010)
#define | ETH_DMA_IT_TJT ((uint32_t)0x00000008)
#define | ETH_DMA_IT_TBU ((uint32_t)0x00000004)
#define | ETH_DMA_IT_TPS ((uint32_t)0x00000002)
#define | ETH_DMA_IT_T ((uint32_t)0x00000001)

Define Documentation

#define ETH_DMA_IT_AIS ((uint32_t)0x00008000)

Abnormal interrupt summary

Definition at line 1552 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_ER ((uint32_t)0x00004000)

Early receive interrupt

Definition at line 1553 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_ET ((uint32_t)0x00000400)

Early transmit interrupt

Definition at line 1555 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_FBE ((uint32_t)0x00002000)

Fatal bus error interrupt

Definition at line 1554 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_MMC ((uint32_t)0x08000000)

MMC interrupt (on DMA)

Definition at line 1550 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_NIS ((uint32_t)0x00010000)

Normal interrupt summary

Definition at line 1551 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_IRQHandler().

#define ETH_DMA_IT_PMT ((uint32_t)0x10000000)

PMT interrupt (on DMA)

Definition at line 1549 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_R ((uint32_t)0x00000040)

Receive interrupt

Definition at line 1559 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_IRQHandler().

#define ETH_DMA_IT_RBU ((uint32_t)0x00000080)

Receive buffer unavailable interrupt

Definition at line 1558 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_RO ((uint32_t)0x00000010)

Overflow interrupt

Definition at line 1561 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_RPS ((uint32_t)0x00000100)

Receive process stopped interrupt

Definition at line 1557 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_RWT ((uint32_t)0x00000200)

Receive watchdog timeout interrupt

Definition at line 1556 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_T ((uint32_t)0x00000001)

Transmit interrupt

Definition at line 1565 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define ETH_DMA_IT_TBU ((uint32_t)0x00000004)

Transmit buffer unavailable interrupt

Definition at line 1563 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_TJT ((uint32_t)0x00000008)

Transmit jabber timeout interrupt

Definition at line 1562 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_TPS ((uint32_t)0x00000002)

Transmit process stopped interrupt

Definition at line 1564 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_TST ((uint32_t)0x20000000)

Time-stamp trigger interrupt (on DMA)

Definition at line 1548 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_IT_TU ((uint32_t)0x00000020)

Underflow interrupt

Definition at line 1560 of file stm32f7xx_hal_eth.h.

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STM32F745xx HAL User Manual: ETH DMA transmit process state

Defines
ETH DMA transmit process state
ETH Exported Constants

Defines

#define | ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000)
#define | ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000)
#define | ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000)
#define | ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000)
#define | ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000)
#define | ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000)

Define Documentation

#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000)

Running - closing Rx descriptor

Definition at line 1578 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000)

Running - fetching the Tx descriptor

Definition at line 1574 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000)

Running - reading the data from host memory

Definition at line 1576 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000)

Stopped - Reset or Stop Tx Command issued

Definition at line 1573 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000)

Suspended - Tx Descriptor unavailable

Definition at line 1577 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000)

Running - waiting for status

Definition at line 1575 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA receive process state

Defines
ETH DMA receive process state
ETH Exported Constants

Defines

#define | ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000)
#define | ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000)
#define | ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000)
#define | ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000)
#define | ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000)
#define | ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000)

Define Documentation

#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000)

Running - closing descriptor

Definition at line 1592 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000)

Running - fetching the Rx descriptor

Definition at line 1589 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000)

Running - queuing the receive frame into host memory

Definition at line 1593 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000)

Stopped - Reset or Stop Rx Command issued

Definition at line 1588 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000)

Suspended - Rx Descriptor unavailable

Definition at line 1591 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000)

Running - waiting for packet

Definition at line 1590 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH DMA overflow

Defines
ETH DMA overflow
ETH Exported Constants

Defines

#define | ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000)
#define | ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)

Define Documentation

#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)

Overflow bit for missed frame counter

Definition at line 1603 of file stm32f7xx_hal_eth.h.

#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000)

Overflow bit for FIFO overflow counter

Definition at line 1602 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH EXTI LINE WAKEUP

Defines
ETH EXTI LINE WAKEUP
ETH Exported Constants

Defines

#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000)

Define Documentation

#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000)

External interrupt line 19 Connected to the ETH EXTI Line

Definition at line 1611 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH Exported Macros

Defines
ETH Exported Macros
ETH

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Reset ETH handle state.
#define | __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
#define | __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
#define | __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Enables the specified DMA Rx Desc receive interrupt.
#define | __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
Disables the specified DMA Rx Desc receive interrupt.
#define | __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
Set the specified DMA Rx Desc Own bit.
#define | __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Returns the specified ETHERNET DMA Tx Desc collision count.
#define | __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
Set the specified DMA Tx Desc Own bit.
#define | __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
Enables the specified DMA Tx Desc Transmit interrupt.
#define | __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Disables the specified DMA Tx Desc Transmit interrupt.
#define | __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
#define | __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Enables the DMA Tx Desc CRC.
#define | __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
Disables the DMA Tx Desc CRC.
#define | __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
#define | __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
#define | __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
Enables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Disables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
Initiate a Pause Control Frame (Full-duplex only).
#define | __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Checks whether the ETHERNET flow control busy bit is set or not.
#define | __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
Enables the MAC Back Pressure operation activation (Half-duplex only).
#define | __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Disables the MAC BackPressure operation activation (Half-duplex only).
#define | __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET MAC flag is set or not.
#define | __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
Enables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Disables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Clears the ETHERNET DMA IT pending bit.
#define | __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET DMA flag is set or not.
#define | __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Checks whether the specified ETHERNET DMA flag is set or not.
#define | __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Checks whether the specified ETHERNET DMA overflow flag is set or not.
#define | __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Set the DMA Receive status watchdog timer register value.
#define | __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
Enables any unicast packet filtered by the MAC address recognition to be a wake-up frame.
#define | __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Disables any unicast packet filtered by the MAC address recognition to be a wake-up frame.
#define | __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
Enables the MAC Wake-Up Frame Detection.
#define | __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Disables the MAC Wake-Up Frame Detection.
#define | __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
Enables the MAC Magic Packet Detection.
#define | __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Disables the MAC Magic Packet Detection.
#define | __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
Enables the MAC Power Down.
#define | __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Disables the MAC Power Down.
#define | __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET PMT flag is set or not.
#define | __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
#define | __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)
Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
#define | __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
Enables the MMC Counter Freeze.
#define | __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Disables the MMC Counter Freeze.
#define | __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
Enables the MMC Reset On Read.
#define | __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Disables the MMC Reset On Read.
#define | __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Enables the MMC Counter Stop Rollover.
#define | __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
Disables the MMC Counter Stop Rollover.
#define | __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
Resets the MMC Counters.
#define | __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Enables the specified ETHERNET MMC Rx interrupts.
#define | __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
Disables the specified ETHERNET MMC Rx interrupts.
#define | __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Enables the specified ETHERNET MMC Tx interrupts.
#define | __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
Disables the specified ETHERNET MMC Tx interrupts.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
Enables the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Disables the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
Enable event on ETH External event line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Disable event on ETH External event line.
#define | __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Get flag of the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Clear flag of the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
Enables rising edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Disables the rising edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
Enables falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Disables falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()
Enables rising/falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
Disables rising/falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
Generate a Software interrupt on selected EXTI line.

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)

Disables the MAC BackPressure operation activation (Half-duplex only).

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1789 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)

Enables the MAC Back Pressure operation activation (Half-duplex only).

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1782 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->DMASR = (__FLAG__))

Checks whether the specified ETHERNET DMA flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag to clear. ETH DMA Flags
Return values:
The new state of ETH_DMA_FLAG (SET or RESET).

Definition at line 1845 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMA_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))

Clears the ETHERNET DMA IT pending bit.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. ETH DMA Interrupts
Return values:
None

Definition at line 1829 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))

Disables the specified ETHERNET DMA interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET DMA interrupt sources to be disabled. ETH DMA Interrupts
Return values:
None

Definition at line 1821 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))

Enables the specified ETHERNET DMA interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET DMA interrupt sources to be enabled ETH DMA Interrupts
Return values:
None

Definition at line 1812 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig().

#define __HAL_ETH_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))

Checks whether the specified ETHERNET DMA flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag to check. ETH DMA Flags
Return values:
The new state of ETH_DMA_FLAG (SET or RESET).

Definition at line 1837 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_IRQHandler().

#define __HAL_ETH_DMARXDESC_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)

Disables the specified DMA Rx Desc receive interrupt.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1661 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMARXDESC_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))

Enables the specified DMA Rx Desc receive interrupt.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1654 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMARXDESC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))

Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag of RDES0 to check.
Return values:
the ETH_DMATxDescFlag (SET or RESET).

Definition at line 1647 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMARXDESC_SET_OWN_BIT ( __HANDLE__ ) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)

Set the specified DMA Rx Desc Own bit.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1668 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION | ( | __HANDLE__,
 |  | __CHECKSUM__
 | ) | ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))

Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.

Parameters:
__HANDLE__,: ETH Handle
__CHECKSUM__,: specifies is the DMA Tx desc checksum insertion. This parameter can be one of the following values:
  • ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
  • ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
  • ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
  • ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
Return values:
None

Definition at line 1709 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_CRC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)

Disables the DMA Tx Desc CRC.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1723 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_CRC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)

Enables the DMA Tx Desc CRC.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1716 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)

Disables the specified DMA Tx Desc Transmit interrupt.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1696 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)

Enables the specified DMA Tx Desc Transmit interrupt.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1689 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT ( __HANDLE__ ) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)

Returns the specified ETHERNET DMA Tx Desc collision count.

Parameters:
__HANDLE__,: ETH Handle
Return values:
The Transmit descriptor collision counter value.

Definition at line 1675 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))

Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag of TDES0 to check.
Return values:
the ETH_DMATxDescFlag (SET or RESET).

Definition at line 1639 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_SET_OWN_BIT ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)

Set the specified DMA Tx Desc Own bit.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1682 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)

Disables the DMA Tx Desc padding for frame shorter than 64 bytes.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1737 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE ( __HANDLE__ ) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)

Enables the DMA Tx Desc padding for frame shorter than 64 bytes.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1730 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)

Disables the MMC Counter Stop Rollover.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1991 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)

Enables the MMC Counter Stop Rollover.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1984 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)

Disables the MMC Reset On Read.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1977 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)

Enables the MMC Reset On Read.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1970 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS | ( | __HANDLE__,
 |  | __OVERFLOW__
 | ) | (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))

Checks whether the specified ETHERNET DMA overflow flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__OVERFLOW__,: specifies the DMA overflow flag to check. This parameter can be one of the following values:
  • ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
  • ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
Return values:
The state of ETHERNET DMA overflow Flag (SET or RESET).

Definition at line 1856 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS ( __HANDLE__ ) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)

Checks whether the ETHERNET flow control busy bit is set or not.

Parameters:
__HANDLE__,: ETH Handle
Return values:
The new state of flow control busy status bit (SET or RESET).

Definition at line 1775 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_GET_PMT_FLAG_STATUS | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))

Checks whether the specified ETHERNET PMT flag is set or not.

Parameters:
__HANDLE__,: ETH Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
  • ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
  • ETH_PMT_FLAG_MPR : Magic Packet Received
Return values:
The new state of ETHERNET PMT Flag (SET or RESET).

Definition at line 1934 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)

Disables any unicast packet filtered by the MAC address recognition to be a wake-up frame.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1880 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)

Enables any unicast packet filtered by the MAC address recognition to be a wake-up frame.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1872 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME ( __HANDLE__ ) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)

Initiate a Pause Control Frame (Full-duplex only).

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1768 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))

Disables the specified ETHERNET MAC interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET MAC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • ETH_MAC_IT_TST : Time stamp trigger interrupt
  • ETH_MAC_IT_PMT : PMT interrupt
Return values:
None

Definition at line 1761 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))

Enables the specified ETHERNET MAC interrupts.

Parameters:
__HANDLE__ : ETH Handle
__INTERRUPT__,: specifies the ETHERNET MAC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • ETH_MAC_IT_TST : Time stamp trigger interrupt
  • ETH_MAC_IT_PMT : PMT interrupt
Return values:
None

Definition at line 1749 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))

Checks whether the specified ETHERNET MAC flag is set or not.

Parameters:
__HANDLE__,: ETH Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • ETH_MAC_FLAG_TST : Time stamp trigger flag
  • ETH_MAC_FLAG_MMCT : MMC transmit flag
  • ETH_MAC_FLAG_MMCR : MMC receive flag
  • ETH_MAC_FLAG_MMC : MMC flag
  • ETH_MAC_FLAG_PMT : PMT flag
Return values:
The state of ETHERNET MAC flag.

Definition at line 1803 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)

Disables the MAC Magic Packet Detection.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1908 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)

Enables the MAC Magic Packet Detection.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1901 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)

Disables the MMC Counter Freeze.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1963 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)

Enables the MMC Counter Freeze.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1956 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_COUNTER_FULL_PRESET ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))

Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1941 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_COUNTER_HALF_PRESET ( __HANDLE__ )
Value:
do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
                                                                          (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)

Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1948 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_COUNTERS_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)

Resets the MMC Counters.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1998 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_RX_IT_DISABLE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)

Disables the specified ETHERNET MMC Rx interrupts.

Parameters:
__HANDLE__,: ETH Handle.
__INTERRUPT__,: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
  • ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
  • ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Return values:
None

Definition at line 2021 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_RX_IT_ENABLE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)

Enables the specified ETHERNET MMC Rx interrupts.

Parameters:
__HANDLE__,: ETH Handle.
__INTERRUPT__,: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
  • ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
  • ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Return values:
None

Definition at line 2010 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_TX_IT_DISABLE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))

Disables the specified ETHERNET MMC Tx interrupts.

Parameters:
__HANDLE__,: ETH Handle.
__INTERRUPT__,: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
  • ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
  • ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Return values:
None

Definition at line 2044 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_MMC_TX_IT_ENABLE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))

Enables the specified ETHERNET MMC Tx interrupts.

Parameters:
__HANDLE__,: ETH Handle.
__INTERRUPT__,: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
  • ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
  • ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Return values:
None

Definition at line 2032 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_POWER_DOWN_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)

Disables the MAC Power Down.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1922 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_POWER_DOWN_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)

Enables the MAC Power Down.

Parameters:
__HANDLE__,: ETH Handle
Return values:
None

Definition at line 1915 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)

Reset ETH handle state.

Parameters:
__HANDLE__,: specifies the ETH handle.
Return values:
None

Definition at line 1631 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))

Set the DMA Receive status watchdog timer register value.

Parameters:
__HANDLE__,: ETH Handle
__VALUE__,: DMA Receive status watchdog timer register value
Return values:
None

Definition at line 1864 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI->PR = (ETH_EXTI_LINE_WAKEUP)

Clear flag of the ETH External interrupt line.

Return values:
None

Definition at line 2080 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT ( ) EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)

Disable event on ETH External event line.

Return values:
None.

Definition at line 2068 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER ( ) EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)

Disables falling edge trigger to the ETH External interrupt line.

Return values:
None

Definition at line 2104 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER ( )
Value:
EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
                                                               EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)

Disables rising/falling edge trigger to the ETH External interrupt line.

Return values:
None

Definition at line 2117 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)

Disables the ETH External interrupt line.

Return values:
None

Definition at line 2056 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER ( ) EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)

Disables the rising edge trigger to the ETH External interrupt line.

Return values:
None

Definition at line 2092 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT ( ) EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)

Enable event on ETH External event line.

Return values:
None.

Definition at line 2062 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER ( ) EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)

Enables falling edge trigger to the ETH External interrupt line.

Return values:
None

Definition at line 2098 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER ( )
Value:
EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
                                                              EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP

Enables rising/falling edge trigger to the ETH External interrupt line.

Return values:
None

Definition at line 2110 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)

Enables the ETH External interrupt line.

Return values:
None

Definition at line 2050 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER ( ) EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP

Enables rising edge trigger to the ETH External interrupt line.

Return values:
None

Definition at line 2086 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT ( ) EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP

Generate a Software interrupt on selected EXTI line.

Return values:
None.

Definition at line 2124 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG ( ) EXTI->PR & (ETH_EXTI_LINE_WAKEUP)

Get flag of the ETH External interrupt line.

Return values:
None

Definition at line 2074 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)

Disables the MAC Wake-Up Frame Detection.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1894 of file stm32f7xx_hal_eth.h.

#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)

Enables the MAC Wake-Up Frame Detection.

Parameters:
__HANDLE__,: ETH Handle.
Return values:
None

Definition at line 1887 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_Private_Macros

Defines
ETH_Private_Macros
ETH

Defines

#define | IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
#define | IS_ETH_AUTONEGOTIATION(CMD)
#define | IS_ETH_SPEED(SPEED)
#define | IS_ETH_DUPLEX_MODE(MODE)
#define | IS_ETH_RX_MODE(MODE)
#define | IS_ETH_CHECKSUM_MODE(MODE)
#define | IS_ETH_MEDIA_INTERFACE(MODE)
#define | IS_ETH_WATCHDOG(CMD)
#define | IS_ETH_JABBER(CMD)
#define | IS_ETH_INTER_FRAME_GAP(GAP)
#define | IS_ETH_CARRIER_SENSE(CMD)
#define | IS_ETH_RECEIVE_OWN(CMD)
#define | IS_ETH_LOOPBACK_MODE(CMD)
#define | IS_ETH_CHECKSUM_OFFLOAD(CMD)
#define | IS_ETH_RETRY_TRANSMISSION(CMD)
#define | IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD)
#define | IS_ETH_BACKOFF_LIMIT(LIMIT)
#define | IS_ETH_DEFERRAL_CHECK(CMD)
#define | IS_ETH_RECEIVE_ALL(CMD)
#define | IS_ETH_SOURCE_ADDR_FILTER(CMD)
#define | IS_ETH_CONTROL_FRAMES(PASS)
#define | IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD)
#define | IS_ETH_DESTINATION_ADDR_FILTER(FILTER)
#define | IS_ETH_PROMISCUOUS_MODE(CMD)
#define | IS_ETH_MULTICAST_FRAMES_FILTER(FILTER)
#define | IS_ETH_UNICAST_FRAMES_FILTER(FILTER)
#define | IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
#define | IS_ETH_ZEROQUANTA_PAUSE(CMD)
#define | IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD)
#define | IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD)
#define | IS_ETH_RECEIVE_FLOWCONTROL(CMD)
#define | IS_ETH_TRANSMIT_FLOWCONTROL(CMD)
#define | IS_ETH_VLAN_TAG_COMPARISON(COMPARISON)
#define | IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
#define | IS_ETH_MAC_ADDRESS0123(ADDRESS)
#define | IS_ETH_MAC_ADDRESS123(ADDRESS)
#define | IS_ETH_MAC_ADDRESS_FILTER(FILTER)
#define | IS_ETH_MAC_ADDRESS_MASK(MASK)
#define | IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD)
#define | IS_ETH_RECEIVE_STORE_FORWARD(CMD)
#define | IS_ETH_FLUSH_RECEIVE_FRAME(CMD)
#define | IS_ETH_TRANSMIT_STORE_FORWARD(CMD)
#define | IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD)
#define | IS_ETH_FORWARD_ERROR_FRAMES(CMD)
#define | IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD)
#define | IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD)
#define | IS_ETH_SECOND_FRAME_OPERATE(CMD)
#define | IS_ETH_ADDRESS_ALIGNED_BEATS(CMD)
#define | IS_ETH_FIXED_BURST(CMD)
#define | IS_ETH_RXDMA_BURST_LENGTH(LENGTH)
#define | IS_ETH_TXDMA_BURST_LENGTH(LENGTH)
#define | IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
#define | IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO)
#define | IS_ETH_DMATXDESC_GET_FLAG(FLAG)
#define | IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT)
#define | IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM)
#define | IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
#define | IS_ETH_DMARXDESC_GET_FLAG(FLAG)
#define | IS_ETH_DMA_RXDESC_BUFFER(BUFFER)
#define | IS_ETH_PMT_GET_FLAG(FLAG)
#define | IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
#define | IS_ETH_DMA_GET_FLAG(FLAG)
#define | IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
#define | IS_ETH_MAC_GET_IT(IT)
#define | IS_ETH_MAC_GET_FLAG(FLAG)
#define | IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
#define | IS_ETH_DMA_GET_IT(IT)
#define | IS_ETH_DMA_GET_OVERFLOW(OVERFLOW)
#define | IS_ETH_MMC_IT(IT)
#define | IS_ETH_MMC_GET_IT(IT)
#define | IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD)

Define Documentation

#define IS_ETH_ADDRESS_ALIGNED_BEATS ( CMD )
Value:
(((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
                                           ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))

Definition at line 181 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_AUTOMATIC_PADCRC_STRIP ( CMD )
Value:
(((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
                                            ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))

Definition at line 95 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_AUTONEGOTIATION ( CMD )
Value:
(((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
                                     ((CMD) == ETH_AUTONEGOTIATION_DISABLE))

Definition at line 61 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

#define IS_ETH_BACKOFF_LIMIT ( LIMIT )
Value:
(((LIMIT) == ETH_BACKOFFLIMIT_10) || \
                                     ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
                                     ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
                                     ((LIMIT) == ETH_BACKOFFLIMIT_1))

Definition at line 97 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_BROADCAST_FRAMES_RECEPTION ( CMD )
Value:
(((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
                                                ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))

Definition at line 111 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_CARRIER_SENSE ( CMD )
Value:
(((CMD) == ETH_CARRIERSENCE_ENABLE) || \
                                   ((CMD) == ETH_CARRIERSENCE_DISABLE))

Definition at line 85 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_CHECKSUM_MODE ( MODE )
Value:
(((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
                                      ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))

Definition at line 69 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

#define IS_ETH_CHECKSUM_OFFLOAD ( CMD )
Value:
(((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
                                      ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))

Definition at line 91 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_CONTROL_FRAMES ( PASS )
Value:
(((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))

Definition at line 108 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_DEFERRAL_CHECK ( CMD )
Value:
(((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
                                    ((CMD) == ETH_DEFFERRALCHECK_DISABLE))

Definition at line 101 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_DESTINATION_ADDR_FILTER ( FILTER )
Value:
(((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
                                                ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))

Definition at line 113 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX ( RATIO )
Value:
(((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
                                                       ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))

Definition at line 210 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_DMA_DESC_SKIP_LENGTH ( LENGTH ) ((LENGTH) <= 0x1F)

Definition at line 209 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_DMA_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))

Definition at line 268 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_GET_FLAG ( FLAG )
Value:
(((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
                                   ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
                                   ((FLAG) == ETH_DMA_FLAG_T))

Definition at line 269 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_GET_IT ( IT )
Value:
(((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))

Definition at line 288 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_GET_OVERFLOW ( OVERFLOW )
Value:
(((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
                                           ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))

Definition at line 297 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_IT ( IT ) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))

Definition at line 287 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_RXDESC_BUFFER ( BUFFER )
Value:
(((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
                                          ((BUFFER) == ETH_DMARXDESC_BUFFER2))

Definition at line 264 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_TXDESC_CHECKSUM ( CHECKSUM )
Value:
(((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))

Definition at line 241 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMA_TXDESC_SEGMENT ( SEGMENT )
Value:
(((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
                                            ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))

Definition at line 239 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMARXDESC_GET_FLAG ( FLAG )
Value:
(((FLAG) == ETH_DMARXDESC_OWN) || \
                                         ((FLAG) == ETH_DMARXDESC_AFM) || \
                                         ((FLAG) == ETH_DMARXDESC_ES) || \
                                         ((FLAG) == ETH_DMARXDESC_DE) || \
                                         ((FLAG) == ETH_DMARXDESC_SAF) || \
                                         ((FLAG) == ETH_DMARXDESC_LE) || \
                                         ((FLAG) == ETH_DMARXDESC_OE) || \
                                         ((FLAG) == ETH_DMARXDESC_VLAN) || \
                                         ((FLAG) == ETH_DMARXDESC_FS) || \
                                         ((FLAG) == ETH_DMARXDESC_LS) || \
                                         ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
                                         ((FLAG) == ETH_DMARXDESC_LC) || \
                                         ((FLAG) == ETH_DMARXDESC_FT) || \
                                         ((FLAG) == ETH_DMARXDESC_RWT) || \
                                         ((FLAG) == ETH_DMARXDESC_RE) || \
                                         ((FLAG) == ETH_DMARXDESC_DBE) || \
                                         ((FLAG) == ETH_DMARXDESC_CE) || \
                                         ((FLAG) == ETH_DMARXDESC_MAMPCE))

Definition at line 246 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMATXDESC_BUFFER_SIZE ( SIZE ) ((SIZE) <= 0x1FFF)

Definition at line 245 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DMATXDESC_GET_FLAG ( FLAG )
Value:
(((FLAG) == ETH_DMATXDESC_OWN) || \
                                         ((FLAG) == ETH_DMATXDESC_IC) || \
                                         ((FLAG) == ETH_DMATXDESC_LS) || \
                                         ((FLAG) == ETH_DMATXDESC_FS) || \
                                         ((FLAG) == ETH_DMATXDESC_DC) || \
                                         ((FLAG) == ETH_DMATXDESC_DP) || \
                                         ((FLAG) == ETH_DMATXDESC_TTSE) || \
                                         ((FLAG) == ETH_DMATXDESC_TER) || \
                                         ((FLAG) == ETH_DMATXDESC_TCH) || \
                                         ((FLAG) == ETH_DMATXDESC_TTSS) || \
                                         ((FLAG) == ETH_DMATXDESC_IHE) || \
                                         ((FLAG) == ETH_DMATXDESC_ES) || \
                                         ((FLAG) == ETH_DMATXDESC_JT) || \
                                         ((FLAG) == ETH_DMATXDESC_FF) || \
                                         ((FLAG) == ETH_DMATXDESC_PCE) || \
                                         ((FLAG) == ETH_DMATXDESC_LCA) || \
                                         ((FLAG) == ETH_DMATXDESC_NC) || \
                                         ((FLAG) == ETH_DMATXDESC_LCO) || \
                                         ((FLAG) == ETH_DMATXDESC_EC) || \
                                         ((FLAG) == ETH_DMATXDESC_VF) || \
                                         ((FLAG) == ETH_DMATXDESC_CC) || \
                                         ((FLAG) == ETH_DMATXDESC_ED) || \
                                         ((FLAG) == ETH_DMATXDESC_UF) || \
                                         ((FLAG) == ETH_DMATXDESC_DB))

Definition at line 215 of file stm32f7xx_hal_eth.h.

#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME ( CMD )
Value:
(((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
                                               ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))

Definition at line 155 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_DUPLEX_MODE ( MODE )
Value:
(((MODE) == ETH_MODE_FULLDUPLEX) || \
                                  ((MODE) == ETH_MODE_HALFDUPLEX))

Definition at line 65 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC(), and HAL_ETH_Init().

#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT ( CMD )
Value:
(((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
                                                ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))

Definition at line 304 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_FIXED_BURST ( CMD )
Value:
(((CMD) == ETH_FIXEDBURST_ENABLE) || \
                                 ((CMD) == ETH_FIXEDBURST_DISABLE))

Definition at line 183 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_FLUSH_RECEIVE_FRAME ( CMD )
Value:
(((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
                                         ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))

Definition at line 159 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_FORWARD_ERROR_FRAMES ( CMD )
Value:
(((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
                                          ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))

Definition at line 171 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES ( CMD )
Value:
(((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
                                                    ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))

Definition at line 173 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_INTER_FRAME_GAP ( GAP )
Value:
(((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
                                     ((GAP) == ETH_INTERFRAMEGAP_40BIT))

Definition at line 77 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_JABBER ( CMD )
Value:
(((CMD) == ETH_JABBER_ENABLE) || \
                            ((CMD) == ETH_JABBER_DISABLE))

Definition at line 75 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_LOOPBACK_MODE ( CMD )
Value:
(((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
                                   ((CMD) == ETH_LOOPBACKMODE_DISABLE))

Definition at line 89 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_MAC_ADDRESS0123 ( ADDRESS )
Value:
(((ADDRESS) == ETH_MAC_ADDRESS0) || \
                                         ((ADDRESS) == ETH_MAC_ADDRESS1) || \
                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \
                                         ((ADDRESS) == ETH_MAC_ADDRESS3))

Definition at line 140 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACAddressConfig().

#define IS_ETH_MAC_ADDRESS123 ( ADDRESS )
Value:
(((ADDRESS) == ETH_MAC_ADDRESS1) || \
                                        ((ADDRESS) == ETH_MAC_ADDRESS2) || \
                                        ((ADDRESS) == ETH_MAC_ADDRESS3))

Definition at line 144 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MAC_ADDRESS_FILTER ( FILTER )
Value:
(((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
                                           ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))

Definition at line 147 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MAC_ADDRESS_MASK ( MASK )
Value:
(((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))

Definition at line 149 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MAC_GET_FLAG ( FLAG )
Value:
(((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
                                   ((FLAG) == ETH_MAC_FLAG_PMT))

Definition at line 284 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MAC_GET_IT ( IT )
Value:
(((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
                               ((IT) == ETH_MAC_IT_PMT))

Definition at line 281 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MAC_IT ( IT ) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))

Definition at line 280 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MEDIA_INTERFACE ( MODE )
Value:
(((MODE) == ETH_MEDIA_INTERFACE_MII) || \
                                              ((MODE) == ETH_MEDIA_INTERFACE_RMII))

Definition at line 71 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

#define IS_ETH_MMC_GET_IT ( IT )
Value:
(((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))

Definition at line 301 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MMC_IT ( IT )
Value:
(((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
                           ((IT) != 0x00))

Definition at line 299 of file stm32f7xx_hal_eth.h.

#define IS_ETH_MULTICAST_FRAMES_FILTER ( FILTER )
Value:
(((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))

Definition at line 117 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_PAUSE_LOW_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))

Definition at line 127 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_PAUSE_TIME ( TIME ) ((TIME) <= 0xFFFF)

Definition at line 124 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_PHY_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0x20)

Definition at line 60 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ReadPHYRegister(), and HAL_ETH_WritePHYRegister().

#define IS_ETH_PMT_GET_FLAG ( FLAG )
Value:
(((FLAG) == ETH_PMT_FLAG_WUFR) || \
                                   ((FLAG) == ETH_PMT_FLAG_MPR))

Definition at line 266 of file stm32f7xx_hal_eth.h.

#define IS_ETH_PROMISCUOUS_MODE ( CMD )
Value:
(((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
                                      ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))

Definition at line 115 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_RECEIVE_ALL ( CMD )
Value:
(((CMD) == ETH_RECEIVEALL_ENABLE) || \
                                 ((CMD) == ETH_RECEIVEAll_DISABLE))

Definition at line 103 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_RECEIVE_FLOWCONTROL ( CMD )
Value:
(((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
                                         ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))

Definition at line 133 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_RECEIVE_OWN ( CMD )
Value:
(((CMD) == ETH_RECEIVEOWN_ENABLE) || \
                                 ((CMD) == ETH_RECEIVEOWN_DISABLE))

Definition at line 87 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_RECEIVE_STORE_FORWARD ( CMD )
Value:
(((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
                                           ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))

Definition at line 157 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_RECEIVE_THRESHOLD_CONTROL ( THRESHOLD )
Value:
(((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))

Definition at line 175 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_RETRY_TRANSMISSION ( CMD )
Value:
(((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
                                        ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))

Definition at line 93 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_RX_MODE ( MODE )
Value:
(((MODE) == ETH_RXPOLLING_MODE) || \
                                 ((MODE) == ETH_RXINTERRUPT_MODE))

Definition at line 67 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

#define IS_ETH_RXDMA_BURST_LENGTH ( LENGTH )
Value:
(((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))

Definition at line 185 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_SECOND_FRAME_OPERATE ( CMD )
Value:
(((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
                                          ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))

Definition at line 179 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_SOURCE_ADDR_FILTER ( CMD )
Value:
(((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
                                        ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
                                        ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))

Definition at line 105 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_SPEED ( SPEED )
Value:
(((SPEED) == ETH_SPEED_10M) || \
                             ((SPEED) == ETH_SPEED_100M))

Definition at line 63 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC(), and HAL_ETH_Init().

#define IS_ETH_TRANSMIT_FLOWCONTROL ( CMD )
Value:
(((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
                                          ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))

Definition at line 135 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_TRANSMIT_STORE_FORWARD ( CMD )
Value:
(((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
                                            ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))

Definition at line 161 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL ( THRESHOLD )
Value:
(((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))

Definition at line 163 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_TXDMA_BURST_LENGTH ( LENGTH )
Value:
(((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))

Definition at line 197 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigDMA().

#define IS_ETH_UNICAST_FRAMES_FILTER ( FILTER )
Value:
(((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))

Definition at line 121 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT ( CMD )
Value:
(((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
                                                ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))

Definition at line 131 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_VLAN_TAG_COMPARISON ( COMPARISON )
Value:
(((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
                                                ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))

Definition at line 137 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_VLAN_TAG_IDENTIFIER ( IDENTIFIER ) ((IDENTIFIER) <= 0xFFFF)

Definition at line 139 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_WATCHDOG ( CMD )
Value:
(((CMD) == ETH_WATCHDOG_ENABLE) || \
                              ((CMD) == ETH_WATCHDOG_DISABLE))

Definition at line 73 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

#define IS_ETH_ZEROQUANTA_PAUSE ( CMD )
Value:
(((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
                                        ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))

Definition at line 125 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_ConfigMAC().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: ETH_Private_Defines

Defines
ETH_Private_Defines
ETH

Defines

#define | ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
#define | ETH_SUCCESS ((uint32_t)0)
#define | ETH_ERROR ((uint32_t)1)
#define | ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
#define | ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
#define | ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
#define | ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
#define | ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
#define | ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
#define | ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
#define | ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
#define | ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
#define | ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
#define | ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
#define | ETH_WAKEUP_REGISTER_LENGTH 8
#define | ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17

Define Documentation

#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17

Definition at line 357 of file stm32f7xx_hal_eth.h.

#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)

Definition at line 351 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigDMA().

#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)

Definition at line 332 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)

Definition at line 329 of file stm32f7xx_hal_eth.h.

#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)

Definition at line 335 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_GetReceivedFrame(), and HAL_ETH_GetReceivedFrame_IT().

#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)

Definition at line 326 of file stm32f7xx_hal_eth.h.

#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)

Definition at line 323 of file stm32f7xx_hal_eth.h.

#define ETH_ERROR ((uint32_t)1)

Definition at line 320 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init().

#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */

Definition at line 338 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACAddressConfig().

#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */

Definition at line 339 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACAddressConfig().

#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)

Definition at line 345 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)

Definition at line 348 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_ConfigMAC().

#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)

Definition at line 342 of file stm32f7xx_hal_eth.h.

Referenced by HAL_ETH_Init(), HAL_ETH_ReadPHYRegister(), and HAL_ETH_WritePHYRegister().

#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)

Definition at line 316 of file stm32f7xx_hal_eth.h.

Referenced by ETH_FlushTransmitFIFO(), ETH_MACDMAConfig(), ETH_MACReceptionDisable(), ETH_MACReceptionEnable(), ETH_MACTransmissionDisable(), ETH_MACTransmissionEnable(), HAL_ETH_ConfigDMA(), and HAL_ETH_ConfigMAC().

#define ETH_SUCCESS ((uint32_t)0)

Definition at line 319 of file stm32f7xx_hal_eth.h.

Referenced by ETH_MACDMAConfig(), and HAL_ETH_Init().

#define ETH_WAKEUP_REGISTER_LENGTH 8

Definition at line 354 of file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue,: The value saved in this parameter depends on the ongoing procedure
  • Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
  • Program : Address which was selected for data program
  • Mass Erase : No return value expected
Return values:
None

Definition at line 456 of file stm32f7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

This function handles FLASH interrupt request.

Return values:
None

Definition at line 313 of file stm32f7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_Erase_Sector(), FLASH_FLAG_EOP, FLASH_FLAG_ERSERR, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_WRPERR, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_MER_BIT, FLASH_PROC_MASSERASE, FLASH_PROC_NONE, FLASH_PROC_PROGRAM, FLASH_PROC_SECTERASE, FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_ProcessTypeDef::Sector, SECTOR_MASK, and FLASH_ProcessTypeDef::VoltageForErase.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue,: The value saved in this parameter depends on the ongoing procedure
  • Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
  • Program : Address which was selected for data program
  • Mass Erase : No return value expected
Return values:
None

Definition at line 475 of file stm32f7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program byte, halfword, word or double word at a specified address.

Parameters:
TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 182 of file stm32f7xx_hal_flash.c.

References assert_param, FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), FLASH_Program_Word(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_BYTE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, FLASH_WaitForLastOperation(), and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program byte, halfword, word or double word at a specified address with interrupt enabled.

Parameters:
TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed
Return values:
HAL Status

Definition at line 251 of file stm32f7xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_FLAG_EOP, FLASH_FLAG_ERSERR, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_WRPERR, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_PROC_PROGRAM, FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), FLASH_Program_Word(), FLASH_TYPEPROGRAM_BYTE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control register access.

Return values:
HAL Status

Definition at line 528 of file stm32f7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 572 of file stm32f7xx_hal_flash.c.

References FLASH_TIMEOUT_VALUE, and FLASH_WaitForLastOperation().

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 560 of file stm32f7xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 540 of file stm32f7xx_hal_flash.c.

References FLASH_OPT_KEY1, and FLASH_OPT_KEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 508 of file stm32f7xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

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STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported Functions

Peripheral Errors functions. More...

Functions

uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operationtimeout
Return values:
HAL Status

Definition at line 622 of file stm32f7xx_hal_flash.c.

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode,: The returned value can be:
  • FLASH_ERROR_ERS: FLASH Erasing Sequence error flag
  • FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
  • FLASH_ERROR_PGA: FLASH Programming Alignment error flag
  • FLASH_ERROR_WRP: FLASH Write protected error flag
  • FLASH_ERROR_OPERATION: FLASH operation Error flag

Definition at line 608 of file stm32f7xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

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STM32F745xx HAL User Manual: FLASH Exported Functions

Modules | Functions
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

management functions

Peripheral State and Errors functions

Peripheral Errors functions.

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program a double word (64-bit) at a specified address.
static void | FLASH_Program_Word (uint32_t Address, uint32_t Data)
Program word (32-bit) at a specified address.
static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_Program_Byte (uint32_t Address, uint8_t Data)
Program byte (8-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.

Function Documentation

static void FLASH_Program_Byte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  | [static]

Program byte (8-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.7V to 3.6V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 760 of file stm32f7xx_hal_flash.c.

References assert_param, CR_PSIZE_MASK, FLASH_PSIZE_BYTE, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_DoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  | [static]

Program a double word (64-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.7V to 3.6V and an External Vpp is present.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 671 of file stm32f7xx_hal_flash.c.

References assert_param, CR_PSIZE_MASK, FLASH_PSIZE_DOUBLE_WORD, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_HalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  | [static]

Program a half-word (16-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.7V to 3.6V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 730 of file stm32f7xx_hal_flash.c.

References assert_param, CR_PSIZE_MASK, FLASH_PSIZE_HALF_WORD, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_Word | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  | [static]

Program word (32-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.7V to 3.6V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 701 of file stm32f7xx_hal_flash.c.

References assert_param, CR_PSIZE_MASK, FLASH_PSIZE_WORD, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_SetErrorCode ( void ) [static]

Set the specific FLASH error flag.

Return values:
None

Definition at line 781 of file stm32f7xx_hal_flash.c.

References __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_ERSERR, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_WRPERR, HAL_FLASH_ERROR_ERS, HAL_FLASH_ERROR_OPERATION, HAL_FLASH_ERROR_PGA, HAL_FLASH_ERROR_PGP, and HAL_FLASH_ERROR_WRP.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operationtimeout
Return values:
HAL Status

Definition at line 622 of file stm32f7xx_hal_flash.c.

References __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_ERSERR, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), HAL_FLASH_ERROR_NONE, and HAL_GetTick().

Referenced by FLASH_OB_BootAddressConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

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STM32F745xx HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum | FLASH_ProcedureTypeDef { FLASH_PROC_NONE = 0, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM }
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_SECTERASE
FLASH_PROC_MASSERASE
FLASH_PROC_PROGRAM

Definition at line 65 of file stm32f7xx_hal_flash.h.

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STM32F745xx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32f7xx_hal_flash.h>

Data Fields

__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | NbSectorsToErase
__IO uint8_t | VoltageForErase
__IO uint32_t | Sector
__IO uint32_t | Address
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FLASH handle Structure definition.

Definition at line 77 of file stm32f7xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Definition at line 87 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

Definition at line 91 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_GetError().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

Definition at line 89 of file stm32f7xx_hal_flash.h.

__IO uint32_t FLASH_ProcessTypeDef::NbSectorsToErase

Definition at line 81 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Definition at line 79 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::Sector

Definition at line 85 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint8_t FLASH_ProcessTypeDef::VoltageForErase

Definition at line 83 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_flash.h
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STM32F745xx HAL User Manual: FLASH Error Code

Defines
FLASH Error Code
FLASH Exported Constants

FLASH Error Code. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002)
#define | HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004)
#define | HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010)
#define | HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020)

Detailed Description

FLASH Error Code.

Define Documentation

#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002)

Programming Sequence error

Definition at line 109 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 108 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020)

Operation Error

Definition at line 113 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)

Programming Alignment error

Definition at line 111 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004)

Programming Parallelism error

Definition at line 110 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010)

Write protection error

Definition at line 112 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

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STM32F745xx HAL User Manual: FLASH Type Program

Defines
FLASH Type Program
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00)
#define | FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01)
#define | FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02)
#define | FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03)

Define Documentation

#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00)

Program byte (8-bit) at a specified address

Definition at line 121 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03)

Program a double word (64-bit) at a specified address

Definition at line 124 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01)

Program a half-word (16-bit) at a specified address

Definition at line 122 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02)

Program a word (32-bit) at a specified address

Definition at line 123 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

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STM32F745xx HAL User Manual: FLASH Flag definition

Defines
FLASH Flag definition
FLASH Exported Constants

Flag definition. More...

Defines

#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_PGPERR FLASH_SR_PGPERR
#define | FLASH_FLAG_ERSERR FLASH_SR_ERSERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY

Detailed Description

Flag definition.

Define Documentation

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 139 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of Operation flag

Definition at line 133 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR

FLASH Erasing Sequence error flag

Definition at line 138 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_OPERR FLASH_SR_OPERR

FLASH operation Error flag

Definition at line 134 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR

FLASH Programming Alignment error flag

Definition at line 136 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR

FLASH Programming Parallelism error flag

Definition at line 137 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protected error flag

Definition at line 135 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

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STM32F745xx HAL User Manual: FLASH Interrupt definition

Defines
FLASH Interrupt definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR ((uint32_t)0x02000000)

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 148 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_ERR ((uint32_t)0x02000000)

Error Interrupt source

Definition at line 149 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Program Parallelism

Defines
FLASH Program Parallelism
FLASH Exported Constants

Defines

#define | FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
#define | FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define | FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define | FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define | CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)

Define Documentation

#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)

Definition at line 161 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), and FLASH_Program_Word().

#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)

Definition at line 157 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_Byte().

#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)

Definition at line 160 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_DoubleWord().

#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)

Definition at line 158 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_HalfWord().

#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)

Definition at line 159 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_Word().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 ((uint32_t)0x45670123)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define | FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
#define | FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)

Define Documentation

#define FLASH_KEY1 ((uint32_t)0x45670123)

Definition at line 169 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)

Definition at line 170 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)

Definition at line 171 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)

Definition at line 172 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
Enable the FLASH Adaptive Real-Time memory accelerator.
#define | __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
Disable the FLASH Adaptive Real-Time memory accelerator.
#define | __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)
Resets the FLASH Adaptive Real-Time memory accelerator.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
Clear the specified FLASH flag.

Define Documentation

#define __HAL_FLASH_ART_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)

Disable the FLASH Adaptive Real-Time memory accelerator.

Return values:
none

Definition at line 224 of file stm32f7xx_hal_flash.h.

#define __HAL_FLASH_ART_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)

Enable the FLASH Adaptive Real-Time memory accelerator.

Note:
The ART accelerator is available only for flash access on ITCM interface.
Return values:
none

Definition at line 218 of file stm32f7xx_hal_flash.h.

Referenced by HAL_Init().

#define __HAL_FLASH_ART_RESET ( ) (FLASH->ACR |= FLASH_ACR_ARTRST)

Resets the FLASH Adaptive Real-Time memory accelerator.

Note:
This function must be used only when the Adaptive Real-Time memory accelerator is disabled.
Return values:
None

Definition at line 232 of file stm32f7xx_hal_flash.h.

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ ) (FLASH->SR = (__FLAG__))

Clear the specified FLASH flag.

Parameters:
__FLAG__,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP : FLASH End of Operation flag
  • FLASH_FLAG_OPERR : FLASH operation Error flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
  • FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
Return values:
none

Definition at line 281 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ ) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_ERR: Error Interrupt
Return values:
none

Definition at line 252 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ ) (FLASH->CR |= (__INTERRUPT__))

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_ERR: Error Interrupt
Return values:
none

Definition at line 242 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ ) ((FLASH->SR & (__FLAG__)))

Get the specified FLASH flag status.

Parameters:
__FLAG__,: specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_EOP : FLASH End of Operation flag
  • FLASH_FLAG_OPERR : FLASH operation Error flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
  • FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
  • FLASH_FLAG_BSY : FLASH Busy flag
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 267 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_GET_LATENCY ( ) (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

Get the FLASH Latency.

Return values:
FLASH Latency The value of this parameter depend on device used within the same series

Definition at line 199 of file stm32f7xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_PRFTEN))

Disable the FLASH prefetch buffer.

Return values:
none

Definition at line 211 of file stm32f7xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_PRFTEN)

Enable the FLASH prefetch buffer.

Return values:
none

Definition at line 205 of file stm32f7xx_hal_flash.h.

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__,: FLASH Latency The value of this parameter depend on device used within the same series
Return values:
none

Definition at line 191 of file stm32f7xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 132 of file stm32f7xx_hal_flash.c.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define | SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define | OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
OPTCR register byte 1 (Bits[15:8]) base address.

Define Documentation

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */

Definition at line 122 of file stm32f7xx_hal_flash.c.

Referenced by HAL_FLASH_OB_Launch(), and HAL_FLASH_Program().

#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)

OPTCR register byte 1 (Bits[15:8]) base address.

Definition at line 352 of file stm32f7xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP(), and FLASH_OB_RDP_LevelConfig().

#define SECTOR_MASK ((uint32_t)0xFFFFFF07)

Definition at line 121 of file stm32f7xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private macros to check input parameters

Defines
FLASH Private macros to check input parameters
FLASH Private Macros

Defines

#define IS_FLASH_TYPEPROGRAM(VALUE)

Define Documentation

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))

Definition at line 366 of file stm32f7xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private Functions

FLASH Private Functions
FLASH
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASHEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extension FLASH
    programming operations Operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | SectorError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory sectors.

Parameters:
[in] pEraseInit,: pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] SectorError,: pointer to variable that contains the configuration information on faulty sector in case of error (0xFFFFFFFF means that all the sectors have been correctly erased)
Return values:
HAL Status

Definition at line 168 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_MER_BIT, FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbSectors, FLASH_EraseInitTypeDef::Sector, SECTOR_MASK, FLASH_EraseInitTypeDef::TypeErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.

Parameters:
pEraseInit,: pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 238 of file stm32f7xx_hal_flash_ex.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_ENABLE_IT, assert_param, FLASH_Erase_Sector(), FLASH_FLAG_EOP, FLASH_FLAG_ERSERR, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_WRPERR, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_MassErase(), FLASH_PROC_MASSERASE, FLASH_PROC_SECTERASE, FLASH_TYPEERASE_MASSERASE, IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbSectors, FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_EraseInitTypeDef::Sector, FLASH_ProcessTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, FLASH_ProcessTypeDef::VoltageForErase, and FLASH_EraseInitTypeDef::VoltageRange.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Parameters:
pOBInit,: pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
None

Definition at line 364 of file stm32f7xx_hal_flash_ex.c.

References FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_OB_GetBootAddress(), FLASH_OB_GetBOR(), FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OPTIONBYTE_BOOTADDR_0, OPTIONBYTE_BOOTADDR_1, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, and FLASH_OBProgramInitTypeDef::WRPSector.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Parameters:
pOBInit,: pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 290 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::BootAddr0, FLASH_OBProgramInitTypeDef::BootAddr1, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_OB_BootAddressConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), IS_OPTIONBYTE, IS_WRPSTATE, OB_IWDG_STDBY_ACTIVE, OB_IWDG_STOP_ACTIVE, OB_IWDG_SW, OB_STDBY_NO_RST, OB_STOP_NO_RST, OB_WRPSTATE_ENABLE, OB_WWDG_SW, OPTIONBYTE_BOOTADDR_0, OPTIONBYTE_BOOTADDR_1, OPTIONBYTE_BOR, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASHEx Exported Functions

Modules | Functions
FLASHEx Exported Functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

Functions

void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.
static void | FLASH_MassErase (uint8_t VoltageRange)
Full erase of FLASH memory sectors.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WRPSector)
Enable the write protection of the desired bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WRPSector)
Disable the write protection of the desired bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t Level)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
static HAL_StatusTypeDef | FLASH_OB_BOR_LevelConfig (uint8_t Level)
Set the BOR Level.
static HAL_StatusTypeDef | FLASH_OB_BootAddressConfig (uint32_t BootOption, uint32_t Address)
Configure Boot base address.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static uint32_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint8_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
static uint32_t | FLASH_OB_GetBootAddress (uint32_t BootOption)
Configure Boot base address.

Function Documentation

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint8_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector,: FLASH sector to erase The value of this parameter depend on device used within the same series
VoltageRange,: The device voltage range which defines the erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
  • FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
  • FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
  • FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
Return values:
None

Definition at line 441 of file stm32f7xx_hal_flash_ex.c.

References assert_param, CR_PSIZE_MASK, FLASH_PSIZE_BYTE, FLASH_PSIZE_DOUBLE_WORD, FLASH_PSIZE_HALF_WORD, FLASH_PSIZE_WORD, FLASH_VOLTAGE_RANGE_1, FLASH_VOLTAGE_RANGE_2, FLASH_VOLTAGE_RANGE_3, IS_FLASH_SECTOR, IS_VOLTAGERANGE, and SECTOR_MASK.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_MassErase ( uint8_t VoltageRange ) [static]

Full erase of FLASH memory sectors.

Parameters:
VoltageRange,: The device voltage range which defines the erase parallelism. This parameter can be one of the following values:
  • VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
  • VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
  • VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
  • VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
Return values:
HAL Status

Definition at line 407 of file stm32f7xx_hal_flash_ex.c.

References assert_param, CR_PSIZE_MASK, and IS_VOLTAGERANGE.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static HAL_StatusTypeDef FLASH_OB_BootAddressConfig | ( | uint32_t | BootOption,
 |  | uint32_t | Address
 | ) |  | [static]

Configure Boot base address.

Parameters:
BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 This parameter can be one of the following values:
  • OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
  • OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
Address,: specifies Boot base address This parameter can be one of the following values:
  • OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
  • OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
  • OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
  • OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
  • OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
  • OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
  • OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
Return values:
HAL Status

Definition at line 677 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_BOOT_ADDRESS, and OPTIONBYTE_BOOTADDR_0.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig ( uint8_t Level ) [static]

Set the BOR Level.

Parameters:
Level,: specifies the Option Bytes BOR Reset Level. This parameter can be one of the following values:
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
  • OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
Return values:
HAL Status

Definition at line 646 of file stm32f7xx_hal_flash_ex.c.

References assert_param, and IS_OB_BOR_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_DisableWRP ( uint32_t WRPSector ) [static]

Disable the write protection of the desired bank1 or bank 2 sectors.

Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Parameters:
WRPSector,: specifies the sector(s) to be write protected. This parameter can be one of the following values:
  • WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
  • OB_WRP_Sector_All
Return values:
HAL Status

Definition at line 526 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_WRP_SECTOR.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_EnableWRP ( uint32_t WRPSector ) [static]

Enable the write protection of the desired bank1 or bank 2 sectors.

Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM7 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Parameters:
WRPSector,: specifies the sector(s) to be write protected. This parameter can be one of the following values:
  • WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
  • OB_WRP_SECTOR_All
Return values:
HAL FLASH State

Definition at line 492 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_WRP_SECTOR.

Referenced by HAL_FLASHEx_OBProgram().

static uint32_t FLASH_OB_GetBootAddress ( uint32_t BootOption ) [static]

Configure Boot base address.

Parameters:
BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 This parameter can be one of the following values:
  • OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
  • OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
Return values:
uint32_t Boot Base Address:
  • OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
  • OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
  • OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
  • OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
  • OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
  • OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
  • OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)

Definition at line 782 of file stm32f7xx_hal_flash_ex.c.

References OPTIONBYTE_BOOTADDR_0.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetBOR ( void ) [static]

Returns the FLASH BOR level.

Return values:
uint32_t The FLASH BOR level:
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
  • OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V

Definition at line 759 of file stm32f7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint8_t FLASH_OB_GetRDP ( void ) [static]

Returns the FLASH Read Protection level.

Return values:
FlagStatus FLASH ReadOut Protection Status: This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection

Definition at line 731 of file stm32f7xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, OB_RDP_LEVEL_2, and OPTCR_BYTE1_ADDRESS.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) and RST_STDBY(Bit2).

Definition at line 707 of file stm32f7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetWRP ( void ) [static]

Return the FLASH Write Protection Option Bytes value.

Return values:
uint32_t FLASH Write Protection Option Bytes value

Definition at line 717 of file stm32f7xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig ( uint8_t Level ) [static]

Set the read protection level.

Parameters:
Level,: specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection
Note:
WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
Return values:
HAL Status

Definition at line 557 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_RDP_LEVEL, and OPTCR_BYTE1_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig | ( | uint32_t | Wwdg,
 |  | uint32_t | Iwdg,
 |  | uint32_t | Stop,
 |  | uint32_t | Stdby,
 |  | uint32_t | Iwdgstop,
 |  | uint32_t | Iwdgstdby
 | ) |  | [static]

Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Parameters:
Wwdg,: Selects the IWDG mode This parameter can be one of the following values:
  • OB_WWDG_SW: Software WWDG selected
  • OB_WWDG_HW: Hardware WWDG selected
Iwdg,: Selects the WWDG mode This parameter can be one of the following values:
  • OB_IWDG_SW: Software IWDG selected
  • OB_IWDG_HW: Hardware IWDG selected
Stop,: Reset event when entering STOP mode. This parameter can be one of the following values:
  • OB_STOP_NO_RST: No reset generated when entering in STOP
  • OB_STOP_RST: Reset generated when entering in STOP
Stdby,: Reset event when entering Standby mode. This parameter can be one of the following values:
  • OB_STDBY_NO_RST: No reset generated when entering in STANDBY
  • OB_STDBY_RST: Reset generated when entering in STANDBY
Iwdgstop,: Independent watchdog counter freeze in Stop mode. This parameter can be one of the following values:
  • OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
  • OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
Iwdgstdby,: Independent watchdog counter freeze in standby mode. This parameter can be one of the following values:
  • OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
  • OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
Return values:
HAL Status

Definition at line 603 of file stm32f7xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_IWDG_SOURCE, IS_OB_IWDG_STDBY_FREEZE, IS_OB_IWDG_STOP_FREEZE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, and IS_OB_WWDG_SOURCE.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32f7xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeErase
uint32_t | Sector
uint32_t | NbSectors
uint32_t | VoltageRange

Detailed Description

FLASH Erase structure definition.

Definition at line 65 of file stm32f7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::NbSectors

Number of sectors to be erased. This parameter must be a value between 1 and (max number of sectors - value of Initial sector)

Definition at line 73 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Sector

Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of FLASH Sectors

Definition at line 70 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or sector Erase. This parameter can be a value of FLASH Type Erase

Definition at line 67 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::VoltageRange

The device voltage range which defines the erase parallelism This parameter must be a value of FLASH Voltage Range

Definition at line 76 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_flash_ex.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32f7xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPState
uint32_t | WRPSector
uint32_t | RDPLevel
uint32_t | BORLevel
uint32_t | USERConfig
uint32_t | BootAddr0
uint32_t | BootAddr1

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 84 of file stm32f7xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::BootAddr0

Boot base address when Boot pin = 0. This parameter can be a value of FLASH Boot Address

Definition at line 104 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BootAddr1

Boot base address when Boot pin = 1. This parameter can be a value of FLASH Boot Address

Definition at line 107 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BORLevel

Set the BOR Level. This parameter can be a value of FLASH BOR Reset Level

Definition at line 98 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a value of FLASH Option Type

Definition at line 86 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level. This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 95 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERConfig

Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY.

Definition at line 101 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPSector

Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series

Definition at line 92 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPState

Write protection activation or deactivation. This parameter can be a value of FLASH WRP State

Definition at line 89 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_flash_ex.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Type Erase

Defines
FLASH Type Erase
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_SECTORS ((uint32_t)0x00)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)

Define Documentation

#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)

Flash Mass erase activation

Definition at line 125 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00)

Sectors erase only

Definition at line 124 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH Voltage Range

Defines
FLASH Voltage Range
FLASH Exported Constants

Defines

#define | FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00)
#define | FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01)
#define | FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02)
#define | FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03)

Define Documentation

#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00)

Device operating range: 1.8V to 2.1V

Definition at line 133 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01)

Device operating range: 2.1V to 2.7V

Definition at line 134 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02)

Device operating range: 2.7V to 3.6V

Definition at line 135 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03)

Device operating range: 2.7V to 3.6V + External Vpp

Definition at line 136 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH WRP State

Defines
FLASH WRP State
FLASH Exported Constants

Defines

#define | OB_WRPSTATE_DISABLE ((uint32_t)0x00)
#define | OB_WRPSTATE_ENABLE ((uint32_t)0x01)

Define Documentation

#define OB_WRPSTATE_DISABLE ((uint32_t)0x00)

Disable the write protection of the desired bank 1 sectors

Definition at line 144 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRPSTATE_ENABLE ((uint32_t)0x01)

Enable the write protection of the desired bank 1 sectors

Definition at line 145 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F745xx HAL User Manual: FLASH Option Type

Defines
FLASH Option Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP ((uint32_t)0x01)
#define | OPTIONBYTE_RDP ((uint32_t)0x02)
#define | OPTIONBYTE_USER ((uint32_t)0x04)
#define | OPTIONBYTE_BOR ((uint32_t)0x08)
#define | OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10)
#define | OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20)

Define Documentation

#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10)

Boot 0 Address configuration

Definition at line 157 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddressConfig(), FLASH_OB_GetBootAddress(), HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20)

Boot 1 Address configuration

Definition at line 158 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_BOR ((uint32_t)0x08)

BOR option byte configuration

Definition at line 156 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP ((uint32_t)0x02)

RDP option byte configuration

Definition at line 154 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER ((uint32_t)0x04)

USER option byte configuration

Definition at line 155 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP ((uint32_t)0x01)

WRP option byte configuration

Definition at line 153 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

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STM32F745xx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define | OB_RDP_LEVEL_1 ((uint8_t)0x55)
#define | OB_RDP_LEVEL_2 ((uint8_t)0xCC)

Define Documentation

#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)

Definition at line 166 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 ((uint8_t)0x55)

Definition at line 167 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)

Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0

Definition at line 168 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

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STM32F745xx HAL User Manual: FLASH Option Bytes WWatchdog

Defines
FLASH Option Bytes WWatchdog
FLASH Exported Constants

Defines

#define | OB_WWDG_SW ((uint32_t)0x10)
#define | OB_WWDG_HW ((uint32_t)0x00)

Define Documentation

#define OB_WWDG_HW ((uint32_t)0x00)

Hardware WWDG selected

Definition at line 178 of file stm32f7xx_hal_flash_ex.h.

#define OB_WWDG_SW ((uint32_t)0x10)

Software WWDG selected

Definition at line 177 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F745xx HAL User Manual: FLASH Option Bytes IWatchdog

Defines
FLASH Option Bytes IWatchdog
FLASH Exported Constants

Defines

#define | OB_IWDG_SW ((uint32_t)0x20)
#define | OB_IWDG_HW ((uint32_t)0x00)

Define Documentation

#define OB_IWDG_HW ((uint32_t)0x00)

Hardware IWDG selected

Definition at line 188 of file stm32f7xx_hal_flash_ex.h.

#define OB_IWDG_SW ((uint32_t)0x20)

Software IWDG selected

Definition at line 187 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F745xx HAL User Manual: FLASH Option Bytes nRST_STOP

Defines
FLASH Option Bytes nRST_STOP
FLASH Exported Constants

Defines

#define | OB_STOP_NO_RST ((uint32_t)0x40)
#define | OB_STOP_RST ((uint32_t)0x00)

Define Documentation

#define OB_STOP_NO_RST ((uint32_t)0x40)

No reset generated when entering in STOP

Definition at line 196 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_STOP_RST ((uint32_t)0x00)

Reset generated when entering in STOP

Definition at line 197 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH Option Bytes nRST_STDBY

Defines
FLASH Option Bytes nRST_STDBY
FLASH Exported Constants

Defines

#define | OB_STDBY_NO_RST ((uint32_t)0x80)
#define | OB_STDBY_RST ((uint32_t)0x00)

Define Documentation

#define OB_STDBY_NO_RST ((uint32_t)0x80)

No reset generated when entering in STANDBY

Definition at line 205 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_STDBY_RST ((uint32_t)0x00)

Reset generated when entering in STANDBY

Definition at line 206 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH IWDG Counter Freeze in STOP

Defines
FLASH IWDG Counter Freeze in STOP
FLASH Exported Constants

Defines

#define | OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000)
#define | OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000)

Define Documentation

#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000)

IWDG counter active in STOP mode

Definition at line 215 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000)

Freeze IWDG counter in STOP mode

Definition at line 214 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH IWDG Counter Freeze in STANDBY

Defines
FLASH IWDG Counter Freeze in STANDBY
FLASH Exported Constants

Defines

#define | OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000)
#define | OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000)

Define Documentation

#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000)

IWDG counter active in STANDBY mode

Definition at line 224 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000)

Freeze IWDG counter in STANDBY mode

Definition at line 223 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH BOR Reset Level

Defines
FLASH BOR Reset Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL3 ((uint32_t)0x00)
#define | OB_BOR_LEVEL2 ((uint32_t)0x04)
#define | OB_BOR_LEVEL1 ((uint32_t)0x08)
#define | OB_BOR_OFF ((uint32_t)0x0C)

Define Documentation

#define OB_BOR_LEVEL1 ((uint32_t)0x08)

Supply voltage ranges from 2.10 to 2.40 V

Definition at line 234 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL2 ((uint32_t)0x04)

Supply voltage ranges from 2.40 to 2.70 V

Definition at line 233 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOR_LEVEL3 ((uint32_t)0x00)

Supply voltage ranges from 2.70 to 3.60 V

Definition at line 232 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOR_OFF ((uint32_t)0x0C)

Supply voltage ranges from 1.62 to 2.10 V

Definition at line 235 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH Boot Address

Defines
FLASH Boot Address
FLASH Exported Constants

Defines

#define | OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000)
#define | OB_BOOTADDR_SYSTEM ((uint32_t)0x0040)
#define | OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080)
#define | OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000)
#define | OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000)
#define | OB_BOOTADDR_SRAM1 ((uint32_t)0x8004)
#define | OB_BOOTADDR_SRAM2 ((uint32_t)0x8013)

Define Documentation

#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000)

Boot from Flash on AXIM interface (0x08000000)

Definition at line 247 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000)

Boot from DTCM RAM (0x20000000)

Definition at line 248 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080)

Boot from Flash on ITCM interface (0x00200000)

Definition at line 246 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000)

Boot from ITCM RAM (0x00000000)

Definition at line 244 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004)

Boot from SRAM1 (0x20010000)

Definition at line 249 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013)

Boot from SRAM2 (0x2004C000)

Definition at line 250 of file stm32f7xx_hal_flash_ex.h.

#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040)

Boot from System memory bootloader (0x00100000)

Definition at line 245 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero Latency cycle

Definition at line 258 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One Latency cycle

Definition at line 259 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS

FLASH Ten Latency cycles

Definition at line 268 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS

FLASH Eleven Latency cycles

Definition at line 269 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS

FLASH Twelve Latency cycles

Definition at line 270 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS

FLASH Thirteen Latency cycles

Definition at line 271 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS

FLASH Fourteen Latency cycles

Definition at line 272 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

FLASH Fifteen Latency cycles

Definition at line 273 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two Latency cycles

Definition at line 260 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three Latency cycles

Definition at line 261 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four Latency cycles

Definition at line 262 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH Five Latency cycles

Definition at line 263 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH Six Latency cycles

Definition at line 264 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH Seven Latency cycles

Definition at line 265 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS

FLASH Eight Latency cycles

Definition at line 266 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS

FLASH Nine Latency cycles

Definition at line 267 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH Mass Erase bit

Defines
FLASH Mass Erase bit
FLASH Exported Constants

Defines

#define FLASH_MER_BIT (FLASH_CR_MER)

Define Documentation

#define FLASH_MER_BIT (FLASH_CR_MER)

MER bit to clear

Definition at line 281 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Sectors

Defines
FLASH Sectors
FLASH Exported Constants

Defines

#define | FLASH_SECTOR_0 ((uint32_t)0)
#define | FLASH_SECTOR_1 ((uint32_t)1)
#define | FLASH_SECTOR_2 ((uint32_t)2)
#define | FLASH_SECTOR_3 ((uint32_t)3)
#define | FLASH_SECTOR_4 ((uint32_t)4)
#define | FLASH_SECTOR_5 ((uint32_t)5)
#define | FLASH_SECTOR_6 ((uint32_t)6)
#define | FLASH_SECTOR_7 ((uint32_t)7)

Define Documentation

#define FLASH_SECTOR_0 ((uint32_t)0)

Sector Number 0

Definition at line 289 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_1 ((uint32_t)1)

Sector Number 1

Definition at line 290 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_2 ((uint32_t)2)

Sector Number 2

Definition at line 291 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_3 ((uint32_t)3)

Sector Number 3

Definition at line 292 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_4 ((uint32_t)4)

Sector Number 4

Definition at line 293 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_5 ((uint32_t)5)

Sector Number 5

Definition at line 294 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_6 ((uint32_t)6)

Sector Number 6

Definition at line 295 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_SECTOR_7 ((uint32_t)7)

Sector Number 7

Definition at line 296 of file stm32f7xx_hal_flash_ex.h.

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STM32F745xx HAL User Manual: FLASH Option Bytes Write Protection

Defines
FLASH Option Bytes Write Protection
FLASH Exported Constants

Defines

#define | OB_WRP_SECTOR_0 ((uint32_t)0x00010000)
#define | OB_WRP_SECTOR_1 ((uint32_t)0x00020000)
#define | OB_WRP_SECTOR_2 ((uint32_t)0x00040000)
#define | OB_WRP_SECTOR_3 ((uint32_t)0x00080000)
#define | OB_WRP_SECTOR_4 ((uint32_t)0x00100000)
#define | OB_WRP_SECTOR_5 ((uint32_t)0x00200000)
#define | OB_WRP_SECTOR_6 ((uint32_t)0x00400000)
#define | OB_WRP_SECTOR_7 ((uint32_t)0x00800000)
#define | OB_WRP_SECTOR_All ((uint32_t)0x00FF0000)

Define Documentation

#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000)

Write protection of Sector0

Definition at line 305 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000)

Write protection of Sector1

Definition at line 306 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000)

Write protection of Sector2

Definition at line 307 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000)

Write protection of Sector3

Definition at line 308 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000)

Write protection of Sector4

Definition at line 309 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000)

Write protection of Sector5

Definition at line 310 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000)

Write protection of Sector6

Definition at line 311 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000)

Write protection of Sector7

Definition at line 312 of file stm32f7xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000)

Write protection of all Sectors

Definition at line 313 of file stm32f7xx_hal_flash_ex.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASHEx

Defines

#define | SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define | FLASH_SECTOR_TOTAL 8

Define Documentation

#define FLASH_SECTOR_TOTAL 8

Definition at line 351 of file stm32f7xx_hal_flash_ex.h.

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */

Definition at line 100 of file stm32f7xx_hal_flash_ex.c.

Referenced by FLASH_OB_BootAddressConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), and HAL_FLASHEx_Erase().

#define SECTOR_MASK ((uint32_t)0xFFFFFF07)

Definition at line 99 of file stm32f7xx_hal_flash_ex.c.

Referenced by FLASH_Erase_Sector(), and HAL_FLASHEx_Erase().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private macros to check input parameters

Defines
FLASH Private macros to check input parameters
FLASH Private Macros

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_VOLTAGERANGE(RANGE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE)
#define | IS_OB_BOOT_ADDRESS(ADDRESS)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define | IS_FLASH_SECTOR(SECTOR)
#define | IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))

Define Documentation

#define IS_FLASH_ADDRESS ( ADDRESS ) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))

Definition at line 423 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), and FLASH_Program_Word().

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_LATENCY_0)  || \
                                   ((LATENCY) == FLASH_LATENCY_1)  || \
                                   ((LATENCY) == FLASH_LATENCY_2)  || \
                                   ((LATENCY) == FLASH_LATENCY_3)  || \
                                   ((LATENCY) == FLASH_LATENCY_4)  || \
                                   ((LATENCY) == FLASH_LATENCY_5)  || \
                                   ((LATENCY) == FLASH_LATENCY_6)  || \
                                   ((LATENCY) == FLASH_LATENCY_7)  || \
                                   ((LATENCY) == FLASH_LATENCY_8)  || \
                                   ((LATENCY) == FLASH_LATENCY_9)  || \
                                   ((LATENCY) == FLASH_LATENCY_10) || \
                                   ((LATENCY) == FLASH_LATENCY_11) || \
                                   ((LATENCY) == FLASH_LATENCY_12) || \
                                   ((LATENCY) == FLASH_LATENCY_13) || \
                                   ((LATENCY) == FLASH_LATENCY_14) || \
                                   ((LATENCY) == FLASH_LATENCY_15))

Definition at line 406 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_NBSECTORS ( NBSECTORS ) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))

Definition at line 425 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_SECTOR ( SECTOR )
Value:
(((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))

Definition at line 427 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 365 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_OB_BOOT_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == OB_BOOTADDR_ITCM_RAM)   || \
                                     ((ADDRESS) == OB_BOOTADDR_SYSTEM)     || \
                                     ((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \
                                     ((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \
                                     ((ADDRESS) == OB_BOOTADDR_DTCM_RAM)   || \
                                     ((ADDRESS) == OB_BOOTADDR_SRAM1)      || \
                                     ((ADDRESS) == OB_BOOTADDR_SRAM2))

Definition at line 379 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BootAddressConfig().

#define IS_OB_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))

Definition at line 403 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_BOR_LevelConfig().

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 393 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_IWDG_STDBY_FREEZE ( FREEZE ) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))

Definition at line 401 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_IWDG_STOP_FREEZE ( FREEZE ) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))

Definition at line 399 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                ((LEVEL) == OB_RDP_LEVEL_1)   ||\
                                ((LEVEL) == OB_RDP_LEVEL_2))

Definition at line 387 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_RDP_LevelConfig().

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 397 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

Definition at line 395 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRP_SECTOR ( SECTOR ) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))

Definition at line 432 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_OB_WWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))

Definition at line 391 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OPTIONBYTE ( VALUE )
Value:
(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))

Definition at line 376 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define IS_VOLTAGERANGE ( RANGE )
Value:
(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))

Definition at line 368 of file stm32f7xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector(), and FLASH_MassErase().

#define IS_WRPSTATE ( VALUE )
Value:
(((VALUE) == OB_WRPSTATE_DISABLE) || \
                           ((VALUE) == OB_WRPSTATE_ENABLE))

Definition at line 373 of file stm32f7xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASHEx

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.

Function Documentation

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint8_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector,: FLASH sector to erase The value of this parameter depend on device used within the same series
VoltageRange,: The device voltage range which defines the erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
  • FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
  • FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
  • FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
Return values:
None

Definition at line 441 of file stm32f7xx_hal_flash_ex.c.

References assert_param, CR_PSIZE_MASK, FLASH_PSIZE_BYTE, FLASH_PSIZE_DOUBLE_WORD, FLASH_PSIZE_HALF_WORD, FLASH_PSIZE_WORD, FLASH_VOLTAGE_RANGE_1, FLASH_VOLTAGE_RANGE_2, FLASH_VOLTAGE_RANGE_3, IS_FLASH_SECTOR, IS_VOLTAGERANGE, and SECTOR_MASK.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operationtimeout
Return values:
HAL Status

Definition at line 622 of file stm32f7xx_hal_flash.c.

References __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_ERSERR, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), HAL_FLASH_ERROR_NONE, and HAL_GetTick().

Referenced by FLASH_OB_BootAddressConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASHEx_Private_Variables

Variables
FLASHEx_Private_Variables
FLASHEx

Variables

FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 132 of file stm32f7xx_hal_flash.c.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]
    This section provides functions allowing to initialize and de-initialize the GPIOs
    to be ready for use.

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 312 of file stm32f7xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and GPIO_NUMBER.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Init,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 187 of file stm32f7xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_NUMBER, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read and Write. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

GPIO Read and Write.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callbacks.

Parameters:
GPIO_Pin,: Specifies the pins connected EXTI line
Return values:
None

Definition at line 515 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

This function handles EXTI interrupt request.

Parameters:
GPIO_Pin,: Specifies the pins connected EXTI line
Return values:
None

Definition at line 500 of file stm32f7xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx,: where x can be (A..F) to select the GPIO peripheral for STM32F7 family
GPIO_Pin,: specifies the port bit to be locked. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 467 of file stm32f7xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 392 of file stm32f7xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pins.

Parameters:
GPIOx,: Where x can be (A..I) to select the GPIO peripheral.
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 448 of file stm32f7xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Sets or clears the selected data port bit.

Note:
This function uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState,: specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 426 of file stm32f7xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 86 of file stm32f7xx_hal_gpio.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32f7xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 65 of file stm32f7xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins. This parameter can be a value of GPIO Alternate Function Selection

Definition at line 79 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode define

Definition at line 70 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins define

Definition at line 67 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull define

Definition at line 73 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed define

Definition at line 76 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_gpio.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO pins define

Defines
GPIO pins define
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 104 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 105 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 114 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 115 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 116 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 117 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 118 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 119 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 106 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 107 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 108 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 109 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 110 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 111 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 112 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 113 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 120 of file stm32f7xx_hal_gpio.h.

#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */

Definition at line 122 of file stm32f7xx_hal_gpio.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO mode define

Defines
GPIO mode define
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT ((uint32_t)0x00000000)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x10110000)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x10210000)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x10120000)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD ((uint32_t)0x00000012)

Alternate Function Open Drain Mode

Definition at line 141 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP ((uint32_t)0x00000002)

Alternate Function Push Pull Mode

Definition at line 140 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG ((uint32_t)0x00000003)

Analog Mode

Definition at line 143 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000)

External Event Mode with Falling edge trigger detection

Definition at line 150 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000)

External Event Mode with Rising edge trigger detection

Definition at line 149 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 151 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_INPUT ((uint32_t)0x00000000)

Input Floating Mode

Definition at line 137 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000)

External Interrupt Mode with Falling edge trigger detection

Definition at line 146 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000)

External Interrupt Mode with Rising edge trigger detection

Definition at line 145 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 147 of file stm32f7xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011)

Output Open Drain Mode

Definition at line 139 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001)

Output Push Pull Mode

Definition at line 138 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO speed define

Defines
GPIO speed define
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002)

Fast speed

Definition at line 162 of file stm32f7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000)

Low speed

Definition at line 160 of file stm32f7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001)

Medium speed

Definition at line 161 of file stm32f7xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003)

High speed

Definition at line 163 of file stm32f7xx_hal_gpio.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO pull define

Defines
GPIO pull define
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL ((uint32_t)0x00000000)
#define | GPIO_PULLUP ((uint32_t)0x00000001)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL ((uint32_t)0x00000000)

No Pull-up or Pull-down activation

Definition at line 172 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_PULLDOWN ((uint32_t)0x00000002)

Pull-down activation

Definition at line 174 of file stm32f7xx_hal_gpio.h.

#define GPIO_PULLUP ((uint32_t)0x00000001)

Pull-up activation

Definition at line 173 of file stm32f7xx_hal_gpio.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clears the EXTI's line pending flags.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 202 of file stm32f7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clears the EXTI's line pending bits.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 218 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 226 of file stm32f7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Checks whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 194 of file stm32f7xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Checks whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 210 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

Defines

#define | GPIO_MODE ((uint32_t)0x00000003)
#define | EXTI_MODE ((uint32_t)0x10000000)
#define | GPIO_MODE_IT ((uint32_t)0x00010000)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000)
#define | RISING_EDGE ((uint32_t)0x00100000)
#define | FALLING_EDGE ((uint32_t)0x00200000)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define | GPIO_NUMBER ((uint32_t)16)

Define Documentation

#define EXTI_MODE ((uint32_t)0x10000000)

Definition at line 145 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE ((uint32_t)0x00200000)

Definition at line 149 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE ((uint32_t)0x00000003)

Definition at line 144 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT ((uint32_t)0x00020000)

Definition at line 147 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT ((uint32_t)0x00010000)

Definition at line 146 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER ((uint32_t)16)

Definition at line 152 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)

Definition at line 150 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE ((uint32_t)0x00100000)

Definition at line 148 of file stm32f7xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Define Documentation

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_MODE_INPUT)              ||\
                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
                            ((MODE) == GPIO_MODE_AF_PP)              ||\
                            ((MODE) == GPIO_MODE_AF_OD)              ||\
                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
                            ((MODE) == GPIO_MODE_ANALOG))

Definition at line 284 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( PIN ) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)

Definition at line 283 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 282 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( PULL )
Value:
(((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
                            ((PULL) == GPIO_PULLDOWN))

Definition at line 298 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \
                              ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))

Definition at line 296 of file stm32f7xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIO
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Alternate Function Selection

Defines
GPIO Alternate Function Selection
GPIO Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
#define | GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
#define | GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
#define | GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define | GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define | GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
#define | GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define | GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define | GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
#define | GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */
#define | GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define | GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define | GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define | GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define | GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */
#define | GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define | GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define | GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
#define | GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define | GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define | GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.

Define Documentation

#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 72 of file stm32f7xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 71 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 73 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */

Definition at line 74 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */

AF 10 selection.

Definition at line 161 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */

Definition at line 162 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */

Definition at line 163 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */

Definition at line 164 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */

AF 11 selection.

Definition at line 169 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */

AF 12 selection.

Definition at line 174 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */

Definition at line 175 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */

Definition at line 176 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */

AF 13 selection.

Definition at line 181 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 192 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */

AF 1 selection.

Definition at line 79 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */

Definition at line 80 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */

AF 2 selection.

Definition at line 85 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */

Definition at line 86 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */

Definition at line 87 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */

Definition at line 97 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */

Definition at line 96 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */

Definition at line 94 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */

Definition at line 95 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */

AF 3 selection.

Definition at line 92 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */

Definition at line 93 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */

Definition at line 106 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */

AF 4 selection.

Definition at line 102 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */

Definition at line 103 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */

Definition at line 104 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */

Definition at line 105 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */

AF 5 selection.

Definition at line 111 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */

Definition at line 112 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */

Definition at line 113 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */

Definition at line 114 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */

Definition at line 115 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */

Definition at line 116 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */

Definition at line 122 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */

AF 6 selection.

Definition at line 121 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */

Definition at line 131 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */

Definition at line 132 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */

Definition at line 133 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */

Definition at line 130 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */

AF 7 selection.

Definition at line 127 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */

Definition at line 128 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */

Definition at line 129 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */

Definition at line 143 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */

Definition at line 142 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */

AF 8 selection.

Definition at line 137 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */

Definition at line 138 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */

Definition at line 140 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */

Definition at line 141 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */

Definition at line 139 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */

AF 9 selection.

Definition at line 149 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */

Definition at line 150 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */

Definition at line 154 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */

Definition at line 151 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */

Definition at line 152 of file stm32f7xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */

Definition at line 153 of file stm32f7xx_hal_gpio_ex.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Exported Macros

GPIO Exported Macros
GPIOEx
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Exported Functions

GPIO Exported Functions
GPIOEx
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIOEx

Defines

#define | GPIOA_PIN_AVAILABLE GPIO_PIN_All
GPIO pin available on the platform.
#define | GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOK_PIN_AVAILABLE

Define Documentation

#define GPIOA_PIN_AVAILABLE GPIO_PIN_All

GPIO pin available on the platform.

Definition at line 229 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOB_PIN_AVAILABLE GPIO_PIN_All

Definition at line 230 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOC_PIN_AVAILABLE GPIO_PIN_All

Definition at line 231 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOD_PIN_AVAILABLE GPIO_PIN_All

Definition at line 232 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOE_PIN_AVAILABLE GPIO_PIN_All

Definition at line 233 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOF_PIN_AVAILABLE GPIO_PIN_All

Definition at line 234 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOG_PIN_AVAILABLE GPIO_PIN_All

Definition at line 235 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOH_PIN_AVAILABLE GPIO_PIN_All

Definition at line 238 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOI_PIN_AVAILABLE GPIO_PIN_All

Definition at line 236 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All

Definition at line 237 of file stm32f7xx_hal_gpio_ex.h.

#define GPIOK_PIN_AVAILABLE
Value:
(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)

Definition at line 239 of file stm32f7xx_hal_gpio_ex.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Get Port Index

Defines
GPIO Get Port Index
GPIO Private Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
                                              ((__GPIOx__) == (GPIOB))? 1U :\
                                              ((__GPIOx__) == (GPIOC))? 2U :\
                                              ((__GPIOx__) == (GPIOD))? 3U :\
                                              ((__GPIOx__) == (GPIOE))? 4U :\
                                              ((__GPIOx__) == (GPIOF))? 5U :\
                                              ((__GPIOx__) == (GPIOG))? 6U :\
                                              ((__GPIOx__) == (GPIOH))? 7U :\
                                              ((__GPIOx__) == (GPIOI))? 8U :\
                                              ((__GPIOx__) == (GPIOJ))? 9U : 10U)

Definition at line 253 of file stm32f7xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Check Alternate Function

Defines
GPIO Check Alternate Function
GPIO Private Macros

Defines

#define IS_GPIO_AF(AF)

Define Documentation

#define IS_GPIO_AF ( AF )
Value:
(((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \
                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \
                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \
                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \
                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \
                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \
                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \
                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \
                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \
                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF10_OTG_FS)    || \
                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \
                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT))

Definition at line 314 of file stm32f7xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Private Macros

Modules | Defines
GPIO Private Macros
GPIOEx

Modules

GPIO Get Port Index
GPIO Check Alternate Function

Defines

#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__, __PIN__)

Define Documentation

#define IS_GPIO_PIN_AVAILABLE | ( | __INSTANCE__,
 |  | __PIN__
 | ) |
Value:
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
            (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
                        (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
                        (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
                        (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
                        (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
                        (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))

Definition at line 267 of file stm32f7xx_hal_gpio_ex.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIOEx
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HCD Private Functions

Functions
HCD Private Functions
HCD

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.

Function Documentation

static void HCD_HC_IN_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel IN interrupt requests.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 801 of file stm32f7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), HCD_HandleTypeDef::hc, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_HC_OUT_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel OUT interrupt requests.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 944 of file stm32f7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_Port_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Host Port interrupt requests.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 1140 of file stm32f7xx_hal_hcd.c.

References HAL_HCD_Connect_Callback(), HCD_SPEED_FULL, HCD_SPEED_HIGH, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_RXQLVL_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Rx Queue Level interrupt requests.

Parameters:
hhcd,: HCD handle
Return values:
none

Definition at line 1087 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
HCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_HCD_DeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 239 of file stm32f7xx_hal_hcd.c.

References __HAL_HCD_DISABLE, HAL_HCD_MspDeInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_RESET, and HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_HC_Halt | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

Halt a host channel.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 223 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_HC_Init | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | epnum,
 |  | uint8_t | dev_address,
 |  | uint8_t | speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | mps
 | ) |  |

Initialize a host channel.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
epnum,: Endpoint number. This parameter can be a value from 1 to 15
dev_address : Current device address This parameter can be a value from 0 to 255
speed,: Current device speed. This parameter can be one of these values: HCD_SPEED_HIGH: High speed mode, HCD_SPEED_FULL: Full speed mode, HCD_SPEED_LOW: Low speed mode
ep_type,: Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type, EP_TYPE_ISOC: Isochronous type, EP_TYPE_BULK: Bulk type, EP_TYPE_INTR: Interrupt type
mps,: Max Packet Size. This parameter can be a value from 0 to32K
Return values:
HAL status

Definition at line 184 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Init ( HCD_HandleTypeDef * hhcd )

Initialize the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 127 of file stm32f7xx_hal_hcd.c.

References __HAL_HCD_DISABLE, assert_param, HAL_HCD_MspInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_READY, HCD_HandleTypeDef::Init, HCD_HandleTypeDef::Instance, IS_HCD_ALL_INSTANCE, and HCD_HandleTypeDef::State.

void HAL_HCD_MspDeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the HCD MSP.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 279 of file stm32f7xx_hal_hcd.c.

Referenced by HAL_HCD_DeInit().

void HAL_HCD_MspInit ( HCD_HandleTypeDef * hhcd )

Initialize the HCD MSP.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 264 of file stm32f7xx_hal_hcd.c.

Referenced by HAL_HCD_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
HCD Exported Functions

HCD IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.

Detailed Description

HCD IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..] This subsection provides a set of functions allowing to manage the USB Host Data
    Transfer

Function Documentation

void HAL_HCD_Connect_Callback ( HCD_HandleTypeDef * hhcd )

Connection Event callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 573 of file stm32f7xx_hal_hcd.c.

Referenced by HCD_Port_IRQHandler().

void HAL_HCD_Disconnect_Callback ( HCD_HandleTypeDef * hhcd )

Disconnection Event callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 588 of file stm32f7xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

void HAL_HCD_HC_NotifyURBChange_Callback | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum,
 |  | HCD_URBStateTypeDef | urb_state
 | ) |  |

Notify URB state change callback.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
urb_state,: This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL/
Return values:
None

Definition at line 613 of file stm32f7xx_hal_hcd.c.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | direction,
 |  | uint8_t | ep_type,
 |  | uint8_t | token,
 |  | uint8_t * | pbuff,
 |  | uint16_t | length,
 |  | uint8_t | do_ping
 | ) |  |

Submit a new URB for processing.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
direction,: Channel number. This parameter can be one of these values: 0 : Output / 1 : Input
ep_type,: Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type/ EP_TYPE_ISOC: Isochronous type/ EP_TYPE_BULK: Bulk type/ EP_TYPE_INTR: Interrupt type/
token,: Endpoint Type. This parameter can be one of these values: 0: HC_PID_SETUP / 1: HC_PID_DATA1
pbuff,: pointer to URB data
length,: Length of URB data
do_ping,: activate do ping protocol (for high speed only). This parameter can be one of these values: 0 : do ping inactive / 1 : do ping active
Return values:
HAL status

Definition at line 331 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

void HAL_HCD_IRQHandler ( HCD_HandleTypeDef * hhcd )

Handle HCD interrupt request.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 455 of file stm32f7xx_hal_hcd.c.

References __HAL_HCD_CLEAR_FLAG, __HAL_HCD_GET_FLAG, __HAL_HCD_IS_INVALID_INTERRUPT, HAL_HCD_Disconnect_Callback(), HAL_HCD_SOF_Callback(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), HCD_RXQLVL_IRQHandler(), HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

void HAL_HCD_SOF_Callback ( HCD_HandleTypeDef * hhcd )

SOF callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 558 of file stm32f7xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
HCD Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the HCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_HCD_ResetPort ( HCD_HandleTypeDef * hhcd )

Reset the host port.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 675 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Start ( HCD_HandleTypeDef * hhcd )

Start the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 647 of file stm32f7xx_hal_hcd.c.

References __HAL_HCD_ENABLE, and HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Stop ( HCD_HandleTypeDef * hhcd )

Stop the host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 662 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

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STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
HCD Exported Functions

Peripheral State functions. More...

Functions

HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_HCD_GetCurrentFrame ( HCD_HandleTypeDef * hhcd )

Return the current Host frame number.

Parameters:
hhcd,: HCD handle
Return values:
Current Host frame number

Definition at line 768 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

uint32_t HAL_HCD_GetCurrentSpeed ( HCD_HandleTypeDef * hhcd )

Return the Host enumeration speed.

Parameters:
hhcd,: HCD handle
Return values:
Enumeration speed

Definition at line 778 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HCD_StateTypeDef HAL_HCD_GetState ( HCD_HandleTypeDef * hhcd )

Return the HCD handle state.

Parameters:
hhcd,: HCD handle
Return values:
HAL state

Definition at line 704 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::State.

HCD_HCStateTypeDef HAL_HCD_HC_GetState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the Host Channel state.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
Host channel state This parameter can be one of these values: HC_IDLE/ HC_XFRC/ HC_HALTED/ HC_NYET/ HC_NAK/ HC_STALL/ HC_XACTERR/ HC_BBLERR/ HC_DATATGLERR

Definition at line 758 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

HCD_URBStateTypeDef HAL_HCD_HC_GetURBState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return URB state for a channel.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
URB state. This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL

Definition at line 723 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

uint32_t HAL_HCD_HC_GetXferCount | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the last host transfer size.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
last transfer size in byte

Definition at line 736 of file stm32f7xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

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STM32F745xx HAL User Manual: HCD State Structure definition

Typedefs | Enumerations
HCD State Structure definition
HCD Exported Types

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Typedef Documentation

typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef

Definition at line 79 of file stm32f7xx_hal_hcd.h.

typedef USB_OTG_HCTypeDef HCD_HCTypeDef

Definition at line 77 of file stm32f7xx_hal_hcd.h.

typedef USB_OTG_CfgTypeDef HCD_InitTypeDef

Definition at line 76 of file stm32f7xx_hal_hcd.h.

typedef USB_OTG_GlobalTypeDef HCD_TypeDef

Definition at line 75 of file stm32f7xx_hal_hcd.h.

typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef

Definition at line 78 of file stm32f7xx_hal_hcd.h.

Enumeration Type Documentation

enum HCD_StateTypeDef
Enumerator:
HAL_HCD_STATE_RESET
HAL_HCD_STATE_READY
HAL_HCD_STATE_ERROR
HAL_HCD_STATE_BUSY
HAL_HCD_STATE_TIMEOUT

Definition at line 66 of file stm32f7xx_hal_hcd.h.

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STM32F745xx HAL User Manual: HCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HCD_HandleTypeDef Struct Reference
HCD Handle Structure definition

#include <stm32f7xx_hal_hcd.h>

Data Fields

HCD_TypeDef * Instance
HCD_InitTypeDef Init
HCD_HCTypeDef | hc [15]
HAL_LockTypeDef | Lock
__IO HCD_StateTypeDef | State
void * | pData

Detailed Description

Definition at line 87 of file stm32f7xx_hal_hcd.h.

Field Documentation

HCD_HCTypeDef HCD_HandleTypeDef::hc[15]

Host channels parameters

Definition at line 91 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_HC_GetState(), HAL_HCD_HC_GetURBState(), HAL_HCD_HC_GetXferCount(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HCD_InitTypeDef HCD_HandleTypeDef::Init

HCD required parameters

Definition at line 90 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HCD_HC_IN_IRQHandler(), and HCD_Port_IRQHandler().

HCD_TypeDef* HCD_HandleTypeDef::Instance

Register base address

Definition at line 89 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_GetCurrentFrame(), HAL_HCD_GetCurrentSpeed(), HAL_HCD_HC_Halt(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_ResetPort(), HAL_HCD_Start(), HAL_HCD_Stop(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HAL_LockTypeDef HCD_HandleTypeDef::Lock

HCD peripheral status

Definition at line 92 of file stm32f7xx_hal_hcd.h.

void* HCD_HandleTypeDef::pData

Pointer Stack Handler

Definition at line 94 of file stm32f7xx_hal_hcd.h.

__IO HCD_StateTypeDef HCD_HandleTypeDef::State

HCD communication state

Definition at line 93 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_GetState(), and HAL_HCD_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_hcd.h
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STM32F745xx HAL User Manual: HCD Speed

Defines
HCD Speed
HCD Exported Constants

Defines

#define | HCD_SPEED_HIGH 0
#define | HCD_SPEED_LOW 2
#define | HCD_SPEED_FULL 3

Define Documentation

#define HCD_SPEED_FULL 3

Definition at line 114 of file stm32f7xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_HIGH 0

Definition at line 112 of file stm32f7xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_LOW 2

Definition at line 113 of file stm32f7xx_hal_hcd.h.

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STM32F745xx HAL User Manual: HCD PHY Module

Defines
HCD PHY Module
HCD Exported Constants

Defines

#define | HCD_PHY_ULPI 1
#define | HCD_PHY_EMBEDDED 2

Define Documentation

#define HCD_PHY_EMBEDDED 2

Definition at line 123 of file stm32f7xx_hal_hcd.h.

#define HCD_PHY_ULPI 1

Definition at line 122 of file stm32f7xx_hal_hcd.h.

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STM32F745xx HAL User Manual: HCD Exported Macros

Defines
HCD Exported Macros
HCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_HCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

Definition at line 141 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_CLEAR_HC_INT | ( | chnum,
 |  | __INTERRUPT__
 | ) | (USBx_HC(chnum)->HCINT = (__INTERRUPT__))

Definition at line 144 of file stm32f7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 138 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), and HAL_HCD_Init().

#define __HAL_HCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 137 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_Start().

#define __HAL_HCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 140 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)

Definition at line 142 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_MASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)

Definition at line 147 of file stm32f7xx_hal_hcd.h.

#define __HAL_HCD_MASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)

Definition at line 145 of file stm32f7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_UNMASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Definition at line 148 of file stm32f7xx_hal_hcd.h.

#define __HAL_HCD_UNMASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)

Definition at line 146 of file stm32f7xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

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STM32F745xx HAL User Manual: HCD Instance definition

Defines
HCD Instance definition
HCD Private Macros

Defines

#define IS_HCD_ALL_INSTANCE(INSTANCE)

Define Documentation

#define IS_HCD_ALL_INSTANCE ( INSTANCE )
Value:
(((INSTANCE) == USB_OTG_FS) || \
                                       ((INSTANCE) == USB_OTG_HS))

Definition at line 239 of file stm32f7xx_hal_hcd.h.

Referenced by HAL_HCD_Init().

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STM32F745xx HAL User Manual: HCD Private Functions Prototypes

HCD Private Functions Prototypes
HCD
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitializes the I2C peripheral.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 372 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 290 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_ERROR_NONE, HAL_I2C_MspInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, I2C_HandleTypeDef::Lock, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

I2C MSP DeInit.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 423 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

I2C MSP Init.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 407 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

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STM32F745xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
Trials,: Number of trials
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 2251 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_TIMEOUT, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 626 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_STOPF, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1331 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_GENERATE_START_READ, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1067 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 506 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1238 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_RELOAD_MODE, I2C_TIMEOUT_TXIS, I2C_TransferConfig(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 995 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1723 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MEM_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_STOPF, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in no-blocking mode with DMA from a specific memory address.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be read
Return values:
HAL status

Definition at line 2152 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_STATE_MEM_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMemReceiveCplt(), I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_GENERATE_START_READ, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TIMEOUT_RXNE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in no-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1952 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_MEM_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1580 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MEM_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_STOPF, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in no-blocking mode with DMA to a specific memory address.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 2043 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MEM_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMemTransmitCplt(), I2C_FLAG_BUSY, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TIMEOUT_TXIS, I2C_TransferConfig(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in no-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1859 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_MEM_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 875 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_TIMEOUT_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1506 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_FLAG_ADDR, I2C_FLAG_DIR, I2C_TIMEOUT_ADDR, I2C_TIMEOUT_DIR, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1187 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 746 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_TIMEOUT_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1420 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::hdmatx, I2C_ADDRESSINGMODE_10BIT, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_FLAG_ADDR, I2C_FLAG_DIR, I2C_TIMEOUT_ADDR, I2C_TIMEOUT_BUSY, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1137 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callbacks.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callbacks.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callbacks.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callbacks.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callbacks.

Function Documentation

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2417 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __HAL_I2C_GET_IT_SOURCE, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, HAL_I2C_ErrorCallback(), HAL_I2C_STATE_READY, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, and I2C_HandleTypeDef::State.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2556 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2371 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __HAL_I2C_GET_IT_SOURCE, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_MEM_BUSY_RX, HAL_I2C_STATE_MEM_BUSY_TX, HAL_I2C_STATE_SLAVE_BUSY_RX, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), and I2C_HandleTypeDef::State.

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2477 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMAMasterReceiveCplt(), and I2C_MasterReceive_ISR().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2461 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMAMasterTransmitCplt(), and I2C_MasterTransmit_ISR().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2540 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMAMemReceiveCplt(), and I2C_MasterReceive_ISR().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2524 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMAMemTransmitCplt(), and I2C_MasterTransmit_ISR().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2508 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMASlaveReceiveCplt(), and I2C_SlaveReceive_ISR().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callbacks.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2492 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMASlaveTransmitCplt(), and I2C_SlaveTransmit_ISR().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2C Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Returns the I2C state.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 2602 of file stm32f7xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Returns the I2C state.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 2591 of file stm32f7xx_hal_i2c.c.

References I2C_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32f7xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 66 of file stm32f7xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C addressing mode

Definition at line 75 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C dual addressing mode

Definition at line 78 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C general call addressing mode

Definition at line 87 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C nostretch mode

Definition at line 90 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 72 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 81 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknoledge mask address second device own address if dual addressing mode is selected This parameter can be a value of I2C own address2 masks

Definition at line 84 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 68 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_i2c.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00, HAL_I2C_STATE_READY = 0x01, HAL_I2C_STATE_BUSY = 0x02, HAL_I2C_STATE_MASTER_BUSY_TX = 0x12,
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, HAL_I2C_STATE_MEM_BUSY_TX = 0x52,
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, HAL_I2C_STATE_TIMEOUT = 0x03, HAL_I2C_STATE_ERROR = 0x04
}

Detailed Description

HAL State structure definition.

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

I2C not yet initialized or disabled

HAL_I2C_STATE_READY

I2C initialized and ready for use

HAL_I2C_STATE_BUSY

I2C internal process is ongoing

HAL_I2C_STATE_MASTER_BUSY_TX

Master Data Transmission process is ongoing

HAL_I2C_STATE_MASTER_BUSY_RX

Master Data Reception process is ongoing

HAL_I2C_STATE_SLAVE_BUSY_TX

Slave Data Transmission process is ongoing

HAL_I2C_STATE_SLAVE_BUSY_RX

Slave Data Reception process is ongoing

HAL_I2C_STATE_MEM_BUSY_TX

Memory Data Transmission process is ongoing

HAL_I2C_STATE_MEM_BUSY_RX

Memory Data Reception process is ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Reception process is ongoing

Definition at line 104 of file stm32f7xx_hal_i2c.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_I2C_ERROR_BERR ((uint32_t)0x00000001)
#define | HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002)
#define | HAL_I2C_ERROR_AF ((uint32_t)0x00000004)
#define | HAL_I2C_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_I2C_ERROR_DMA ((uint32_t)0x00000010)
#define | HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004)

ACKF error

Definition at line 130 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002)

ARLO error

Definition at line 129 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001)

BERR error

Definition at line 128 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 132 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_DMAError().

#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 127 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008)

OVR error

Definition at line 131 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040)

Size Management error

Definition at line 134 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_MasterReceive_ISR(), and I2C_MasterTransmit_ISR().

#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020)

Timeout error

Definition at line 133 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32f7xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

Definition at line 143 of file stm32f7xx_hal_i2c.h.

Field Documentation

__IO uint32_t I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 163 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 157 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMemReceiveCplt().

DMA_HandleTypeDef* I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 155 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAMasterTransmitCplt(), and I2C_DMAMemTransmitCplt().

I2C_InitTypeDef I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 147 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

I2C_TypeDef* I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 145 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), and I2C_TransferConfig().

HAL_LockTypeDef I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 159 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint8_t* I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 149 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

__IO HAL_I2C_StateTypeDef I2C_HandleTypeDef::State

I2C communication state

Definition at line 161 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 153 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

uint16_t I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 151 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), and I2C_SlaveReceive_ISR().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_i2c.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C addressing mode

Defines
I2C addressing mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define | I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)

Definition at line 183 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)

Definition at line 182 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C dual addressing mode

Defines
I2C dual addressing mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)

Definition at line 191 of file stm32f7xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 192 of file stm32f7xx_hal_i2c.h.

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STM32F745xx HAL User Manual: I2C own address2 masks

Defines
I2C own address2 masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00)
#define | I2C_OA2_MASK01 ((uint8_t)0x01)
#define | I2C_OA2_MASK02 ((uint8_t)0x02)
#define | I2C_OA2_MASK03 ((uint8_t)0x03)
#define | I2C_OA2_MASK04 ((uint8_t)0x04)
#define | I2C_OA2_MASK05 ((uint8_t)0x05)
#define | I2C_OA2_MASK06 ((uint8_t)0x06)
#define | I2C_OA2_MASK07 ((uint8_t)0x07)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01)

Definition at line 201 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02)

Definition at line 202 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03)

Definition at line 203 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04)

Definition at line 204 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05)

Definition at line 205 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06)

Definition at line 206 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07)

Definition at line 207 of file stm32f7xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00)

Definition at line 200 of file stm32f7xx_hal_i2c.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C general call addressing mode

Defines
I2C general call addressing mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)

Definition at line 215 of file stm32f7xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 216 of file stm32f7xx_hal_i2c.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C nostretch mode

Defines
I2C nostretch mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)

Definition at line 224 of file stm32f7xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 225 of file stm32f7xx_hal_i2c.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define | I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)

Definition at line 234 of file stm32f7xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)

Definition at line 233 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C ReloadEndMode definition

Defines
I2C ReloadEndMode definition
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE ((uint32_t)0x00000000)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 243 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), and I2C_MasterTransmit_ISR().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 242 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)

Definition at line 244 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C StartStopMode definition

Defines
I2C StartStopMode definition
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP ((uint32_t)0x00000000)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 254 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

#define I2C_GENERATE_START_WRITE I2C_CR2_START

Definition at line 255 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP I2C_CR2_STOP

Definition at line 253 of file stm32f7xx_hal_i2c.h.

#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)

Definition at line 252 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), and I2C_MasterTransmit_ISR().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 270 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 266 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 269 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 271 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), I2C_MasterReceive_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 268 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 267 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 272 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterTransmit_ISR(), and I2C_SlaveTransmit_ISR().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 284 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 285 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 294 of file stm32f7xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 290 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 289 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 295 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMASlaveReceiveCplt(), and I2C_DMASlaveTransmitCplt().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 296 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 291 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 292 of file stm32f7xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 283 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive(), I2C_DMAMasterReceiveCplt(), I2C_DMAMemReceiveCplt(), I2C_MasterReceive_ISR(), I2C_SlaveReceive_ISR(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 286 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 287 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 288 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 293 of file stm32f7xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 281 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_IsAcknowledgeFailed(), and I2C_MasterTransmit_ISR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 282 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), I2C_MasterTransmit_ISR(), I2C_SlaveTransmit_ISR(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C HAL module driver

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupts.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupts.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2C interrupt source is enabled or disabled.
#define | I2C_FLAG_MASK ((uint32_t)0x0001FFFF)
Checks whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))
Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))

Clears the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__,: specifies the I2C Handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_ADDR: Address matched (slave mode)
  • I2C_FLAG_AF: Acknowledge failure received flag
  • I2C_FLAG_STOPF: STOP detection flag
  • I2C_FLAG_BERR: Bus error
  • I2C_FLAG_ARLO: Arbitration lost
  • I2C_FLAG_OVR: Overrun/Underrun
  • I2C_FLAG_PECERR: PEC error in reception
  • I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
  • I2C_FLAG_ALERT: SMBus alert
Return values:
None

Definition at line 408 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__,: specifies the I2C Handle.
Return values:
None

Definition at line 420 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), and HAL_I2CEx_ConfigDigitalFilter().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupts.

Parameters:
__HANDLE__,: specifies the I2C Handle.
__INTERRUPT__,: specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI: Errors interrupt enable
  • I2C_IT_TCI: Transfer complete interrupt enable
  • I2C_IT_STOPI: STOP detection interrupt enable
  • I2C_IT_NACKI: NACK received interrupt enable
  • I2C_IT_ADDRI: Address match interrupt enable
  • I2C_IT_RXI: RX interrupt enable
  • I2C_IT_TXI: TX interrupt enable
Return values:
None

Definition at line 348 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), and I2C_SlaveTransmit_ISR().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__,: specifies the I2C Handle.
Return values:
None

Definition at line 414 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), and HAL_I2CEx_ConfigDigitalFilter().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupts.

Parameters:
__HANDLE__,: specifies the I2C Handle.
__INTERRUPT__,: specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI: Errors interrupt enable
  • I2C_IT_TCI: Transfer complete interrupt enable
  • I2C_IT_STOPI: STOP detection interrupt enable
  • I2C_IT_NACKI: NACK received interrupt enable
  • I2C_IT_ADDRI: Address match interrupt enable
  • I2C_IT_RXI: RX interrupt enable
  • I2C_IT_TXI: TX interrupt enable
Return values:
None

Definition at line 332 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), and HAL_I2C_Slave_Transmit_IT().

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))

Definition at line 390 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_SlaveReceive_ISR(), I2C_SlaveTransmit_ISR(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2C interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the I2C Handle.
__INTERRUPT__,: specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI: Errors interrupt enable
  • I2C_IT_TCI: Transfer complete interrupt enable
  • I2C_IT_STOPI: STOP detection interrupt enable
  • I2C_IT_NACKI: NACK received interrupt enable
  • I2C_IT_ADDRI: Address match interrupt enable
  • I2C_IT_RXI: RX interrupt enable
  • I2C_IT_TXI: TX interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 364 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and HAL_I2C_EV_IRQHandler().

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

Reset I2C handle state.

Parameters:
__HANDLE__,: specifies the I2C Handle.
Return values:
None

Definition at line 315 of file stm32f7xx_hal_i2c.h.

#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF)

Checks whether the specified I2C flag is set or not.

Parameters:
__HANDLE__,: specifies the I2C Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE: Transmit data register empty
  • I2C_FLAG_TXIS: Transmit interrupt status
  • I2C_FLAG_RXNE: Receive data register not empty
  • I2C_FLAG_ADDR: Address matched (slave mode)
  • I2C_FLAG_AF: Acknowledge failure received flag
  • I2C_FLAG_STOPF: STOP detection flag
  • I2C_FLAG_TC: Transfer complete (master mode)
  • I2C_FLAG_TCR: Transfer complete reload
  • I2C_FLAG_BERR: Bus error
  • I2C_FLAG_ARLO: Arbitration lost
  • I2C_FLAG_OVR: Overrun/Underrun
  • I2C_FLAG_PECERR: PEC error in reception
  • I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
  • I2C_FLAG_ALERT: SMBus alert
  • I2C_FLAG_BUSY: Bus busy
  • I2C_FLAG_DIR: Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 389 of file stm32f7xx_hal_i2c.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Private Constants

Defines
I2C Private Constants
I2C HAL module driver | I2C Extended HAL module driver

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
#define | I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define | I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */

Define Documentation

#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */

Definition at line 200 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

#define I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */

Definition at line 201 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Transmit_DMA(), I2C_DMASlaveReceiveCplt(), and I2C_DMASlaveTransmitCplt().

#define I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */

Definition at line 202 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Receive_DMA().

#define I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */

Definition at line 208 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */

Definition at line 203 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMemReceiveCplt().

#define I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */

Definition at line 204 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), and I2C_DMASlaveTransmitCplt().

#define I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */

Definition at line 205 of file stm32f7xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */

Definition at line 206 of file stm32f7xx_hal_i2c.c.

Referenced by I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), and I2C_DMAMemTransmitCplt().

#define I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */

Definition at line 207 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_DMAMasterTransmitCplt(), and I2C_DMAMemTransmitCplt().

#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */

Definition at line 199 of file stm32f7xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C HAL module driver | I2C Extended HAL module driver

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)

Define Documentation

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 567 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))

Definition at line 565 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))

Definition at line 564 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 559 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 524 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 97 of file stm32f7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000F)

Definition at line 100 of file stm32f7xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 527 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                          ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 539 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 545 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 542 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= (uint32_t)0x000003FF)

Definition at line 561 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FF)

Definition at line 562 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                          ((MASK) == I2C_OA2_MASK01) || \
                                          ((MASK) == I2C_OA2_MASK02) || \
                                          ((MASK) == I2C_OA2_MASK03) || \
                                          ((MASK) == I2C_OA2_MASK04) || \
                                          ((MASK) == I2C_OA2_MASK05) || \
                                          ((MASK) == I2C_OA2_MASK06) || \
                                          ((MASK) == I2C_OA2_MASK07))

Definition at line 530 of file stm32f7xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                          ((MODE) == I2C_AUTOEND_MODE) || \
                                          ((MODE) == I2C_SOFTEND_MODE))

Definition at line 549 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)         || \
                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                          ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 553 of file stm32f7xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C HAL module driver | I2C Extended HAL module driver

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAMemTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Write process complete callback.
static void | I2C_DMAMemReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Read process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_MasterTransmit_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Master Transmit Mode.
static HAL_StatusTypeDef | I2C_MasterReceive_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Master Receive Mode.
static HAL_StatusTypeDef | I2C_SlaveTransmit_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Slave Transmit Mode.
static HAL_StatusTypeDef | I2C_SlaveReceive_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Slave Receive Mode.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Function Documentation

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 3912 of file stm32f7xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_DMA, HAL_I2C_ErrorCallback(), HAL_I2C_STATE_READY, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 3379 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_RXNE, I2C_TIMEOUT_STOPF, I2C_TIMEOUT_TCR, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 3172 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_STOPF, I2C_TIMEOUT_TCR, I2C_TIMEOUT_TXIS, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Transmit_DMA().

static void I2C_DMAMemReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C Memory Read process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 3750 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_RXNE, I2C_TIMEOUT_STOPF, I2C_TIMEOUT_TCR, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMemTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C Memory Write process complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 3594 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_STOPF, I2C_TIMEOUT_TCR, I2C_TIMEOUT_TXIS, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 3542 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_TIMEOUT_BUSY, I2C_TIMEOUT_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Slave_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 3328 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_TIMEOUT_BUSY, I2C_TIMEOUT_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 4111 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TXE, I2C_RESET_CR2, and I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static HAL_StatusTypeDef I2C_MasterReceive_ISR ( I2C_HandleTypeDef * hi2c ) [static]

Handle Interrupt Flags Master Receive Mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2764 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_SIZE, HAL_I2C_ErrorCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_STATE_MEM_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TransferConfig(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterTransmit_ISR ( I2C_HandleTypeDef * hi2c ) [static]

Handle Interrupt Flags Master Transmit Mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2625 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_SIZE, HAL_I2C_ErrorCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_STATE_MEM_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXE, I2C_FLAG_TXIS, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TransferConfig(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 3112 of file stm32f7xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress,: Target device address
MemAddress,: Internal memory address
MemAddSize,: Size of internal memory address
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 3047 of file stm32f7xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_SlaveReceive_ISR ( I2C_HandleTypeDef * hi2c ) [static]

Handle Interrupt Flags Slave Receive Mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2984 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ErrorCallback(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveTransmit_ISR ( I2C_HandleTypeDef * hi2c ) [static]

Handle Interrupt Flags Slave Transmit Mode.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2898 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ErrorCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c,: I2C handle.
DevAddress,: specifies the slave address to be programmed.
Size,: specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode,: new state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE: Enable Reload mode .
  • I2C_AUTOEND_MODE: Enable Automatic end mode.
  • I2C_SOFTEND_MODE: Enable Software end mode.
Request,: new state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP: Don't Generate stop and start condition.
  • I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ: Generate Restart for read request.
  • I2C_GENERATE_START_WRITE: Generate Restart for write request.
Return values:
None

Definition at line 4180 of file stm32f7xx_hal_i2c.c.

References assert_param, I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_MasterReceive_ISR(), I2C_MasterTransmit_ISR(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag,: specifies the I2C flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 3937 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_GetTick(), HAL_I2C_STATE_READY, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 4058 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_RESET_CR2, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 4023 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), and I2C_DMASlaveTransmitCplt().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c : Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 3986 of file stm32f7xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsAcknowledgeFailed(), and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Transmit(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemTransmitCplt(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended features functions

Functions
Extended features functions
I2C Extended Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configures I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configures I2C Digital noise filter.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configures I2C Analog noise filter.

Parameters:
hi2c | : pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | : new state of the Analog filter.
Return values:
HAL status

Definition at line 106 of file stm32f7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configures I2C Digital noise filter.

Parameters:
hi2c | : pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | : Coefficient of digital noise filter between 0x00 and 0x0F.
Return values:
HAL status

Definition at line 149 of file stm32f7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and I2C_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2CEx Analog Filter

Defines
I2CEx Analog Filter
I2CEx Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 68 of file stm32f7xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)

Definition at line 67 of file stm32f7xx_hal_i2c_ex.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Extended HAL module driver

Modules | Functions
I2C Extended HAL module driver
STM32F7xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2CEx Exported Constants
I2C Private Constants
I2C Private Macros
I2C Private Functions

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configures I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configures I2C Digital noise filter.

Detailed Description

I2C Extended HAL module driver.

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configures I2C Analog noise filter.

Parameters:
hi2c | : pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | : new state of the Analog filter.
Return values:
HAL status

Definition at line 106 of file stm32f7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configures I2C Digital noise filter.

Parameters:
hi2c | : pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | : Coefficient of digital noise filter between 0x00 and 0x0F.
Return values:
HAL status

Definition at line 149 of file stm32f7xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_MASTER_BUSY_RX, HAL_I2C_STATE_MASTER_BUSY_TX, HAL_I2C_STATE_READY, HAL_I2C_STATE_SLAVE_BUSY_RX, HAL_I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and I2C_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Private Functions

Functions
I2S Private Functions
I2S

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

static void I2S_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1485 of file stm32f7xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

static void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1441 of file stm32f7xx_hal_i2s.c.

References HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1472 of file stm32f7xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback().

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1396 of file stm32f7xx_hal_i2s.c.

References HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1428 of file stm32f7xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback().

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_Receive_IT ( I2S_HandleTypeDef * hi2s ) [static]

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: I2S handle
Return values:
None

Definition at line 1528 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_IRQHandler().

static void I2S_Transmit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1507 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_IRQHandler().

static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag,: Flag checked
State,: Value of the flag expected
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 1143 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity
        (++) Full duplex mode

      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 349 of file stm32f7xx_hal_i2s.c.

References assert_param, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 216 of file stm32f7xx_hal_i2s.c.

References assert_param, I2S_InitTypeDef::AudioFreq, I2S_InitTypeDef::ClockSource, I2S_InitTypeDef::CPOL, I2S_InitTypeDef::DataFormat, I2S_HandleTypeDef::ErrorCode, EXTERNAL_CLOCK_VALUE, HAL_I2S_ERROR_NONE, HAL_I2S_MspInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, I2S_AUDIOFREQ_DEFAULT, I2S_CLOCK_EXTERNAL, I2S_DATAFORMAT_16B, I2S_GetClockFreq(), I2S_MCLKOUTPUT_ENABLE, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, IS_I2S_AUDIO_FREQ, IS_I2S_CLOCKSOURCE, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, I2S_HandleTypeDef::Lock, I2S_InitTypeDef::MCLKOutput, I2S_InitTypeDef::Mode, I2S_InitTypeDef::Standard, and I2S_HandleTypeDef::State.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 396 of file stm32f7xx_hal_i2s.c.

Referenced by HAL_I2S_DeInit().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 380 of file stm32f7xx_hal_i2s.c.

Referenced by HAL_I2S_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio stream playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 956 of file stm32f7xx_hal_i2s.c.

References HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_BUSY_TX_RX, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 997 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Stops the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1032 of file stm32f7xx_hal_i2s.c.

References __HAL_DMA_DISABLE, __HAL_I2S_DISABLE, HAL_DMA_Abort(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_HandleTypeDef::hdmatx, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1273 of file stm32f7xx_hal_i2s.c.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_DMAError().

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1073 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, __HAL_I2S_GET_IT_SOURCE, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, I2S_Receive_IT(), I2S_Transmit_IT(), I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continuous way and as the I2S is not disabled at the end of the I2S transaction.
Return values:
HAL status

Definition at line 574 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_MODE_MASTER_RX, I2S_WaitFlagStateUntilTimeout(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 879 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), I2S_MODE_MASTER_RX, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, I2S_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronisation between Master and Slave otherwise the I2S interrupt should be optimized.
Return values:
HAL status

Definition at line 739 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_RXNE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, and I2S_HandleTypeDef::State.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1257 of file stm32f7xx_hal_i2s.c.

Referenced by I2S_DMARxCplt(), and I2S_Receive_IT().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1241 of file stm32f7xx_hal_i2s.c.

Referenced by I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 467 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_BSY, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_MODE_SLAVE_RX, I2S_MODE_SLAVE_TX, I2S_WaitFlagStateUntilTimeout(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, and I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Transmit data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 801 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 674 of file stm32f7xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, and I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1225 of file stm32f7xx_hal_i2s.c.

Referenced by I2S_DMATxCplt(), and I2S_Transmit_IT().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1209 of file stm32f7xx_hal_i2s.c.

Referenced by I2S_DMATxHalfCplt().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1319 of file stm32f7xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1308 of file stm32f7xx_hal_i2s.c.

References I2S_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Exported Types

Data Structures | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | I2S_HandleTypeDef
I2S handle Structure definition. More...

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00, HAL_I2S_STATE_READY = 0x01, HAL_I2S_STATE_BUSY = 0x02, HAL_I2S_STATE_BUSY_TX = 0x03,
HAL_I2S_STATE_BUSY_RX = 0x04, HAL_I2S_STATE_BUSY_TX_RX = 0x05, HAL_I2S_STATE_TIMEOUT = 0x06, HAL_I2S_STATE_ERROR = 0x07
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 92 of file stm32f7xx_hal_i2s.h.

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STM32F745xx HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32f7xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL
uint32_t | ClockSource

Detailed Description

I2S Init structure definition.

Definition at line 65 of file stm32f7xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 79 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::ClockSource

Specifies the I2S Clock Source. This parameter can be a value of I2S Clock Source

Definition at line 85 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), and I2S_GetClockFreq().

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S Clock Polarity

Definition at line 82 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 73 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S Mclk Output

Definition at line 76 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 67 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), and HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 70 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_i2s.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32f7xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

I2S handle Structure definition.

Definition at line 108 of file stm32f7xx_hal_i2s.h.

Field Documentation

__IO uint32_t I2S_HandleTypeDef::ErrorCode

Definition at line 139 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_GetError(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_DMAError().

DMA_HandleTypeDef* I2S_HandleTypeDef::hdmarx

Definition at line 133 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Receive_DMA().

DMA_HandleTypeDef* I2S_HandleTypeDef::hdmatx

Definition at line 131 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit_DMA().

I2S_InitTypeDef I2S_HandleTypeDef::Init

Definition at line 112 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_Init(), and I2S_GetClockFreq().

SPI_TypeDef* I2S_HandleTypeDef::Instance

Definition at line 110 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), and I2S_Transmit_IT().

__IO HAL_LockTypeDef I2S_HandleTypeDef::Lock

Definition at line 135 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint16_t* I2S_HandleTypeDef::pRxBuffPtr

Definition at line 120 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

uint16_t* I2S_HandleTypeDef::pTxBuffPtr

Definition at line 114 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

__IO uint16_t I2S_HandleTypeDef::RxXferCount

Definition at line 124 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), and I2S_Receive_IT().

__IO uint16_t I2S_HandleTypeDef::RxXferSize

Definition at line 122 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and HAL_I2S_Receive_IT().

__IO HAL_I2S_StateTypeDef I2S_HandleTypeDef::State

Definition at line 137 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), I2S_Transmit_IT(), and I2S_WaitFlagStateUntilTimeout().

__IO uint16_t I2S_HandleTypeDef::TxXferCount

Definition at line 118 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), and I2S_Transmit_IT().

__IO uint16_t I2S_HandleTypeDef::TxXferSize

Definition at line 116 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_i2s.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S_Error_Defintion

Defines
I2S_Error_Defintion
I2S Exported Constants

I2S Error Code. More...

Defines

#define | HAL_I2S_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_I2S_ERROR_OVR ((uint32_t)0x00000002)
#define | HAL_I2S_ERROR_UDR ((uint32_t)0x00000004)
#define | HAL_I2S_ERROR_DMA ((uint32_t)0x00000008)
#define | HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010)

Detailed Description

I2S Error Code.

Define Documentation

#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008)

DMA transfer error

Definition at line 159 of file stm32f7xx_hal_i2s.h.

Referenced by I2S_DMAError().

#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 155 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002)

OVR error

Definition at line 157 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001)

Timeout error

Definition at line 156 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004)

UDR error

Definition at line 158 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010)

Unknow Error error

Definition at line 160 of file stm32f7xx_hal_i2s.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Clock Source

Defines
I2S Clock Source
I2S Exported Constants

Defines

#define | I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
#define | I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)

Define Documentation

#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)

Definition at line 168 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), and I2S_GetClockFreq().

#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)

Definition at line 169 of file stm32f7xx_hal_i2s.h.

Referenced by I2S_GetClockFreq().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
#define | I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
#define | I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
#define | I2S_MODE_MASTER_RX ((uint32_t)0x00000300)

Define Documentation

#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)

Definition at line 180 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)

Definition at line 179 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause().

#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)

Definition at line 178 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit().

#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)

Definition at line 177 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), and HAL_I2S_Transmit().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
#define | I2S_STANDARD_MSB ((uint32_t)0x00000010)
#define | I2S_STANDARD_LSB ((uint32_t)0x00000020)
#define | I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
#define | I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)

Define Documentation

#define I2S_STANDARD_LSB ((uint32_t)0x00000020)

Definition at line 190 of file stm32f7xx_hal_i2s.h.

#define I2S_STANDARD_MSB ((uint32_t)0x00000010)

Definition at line 189 of file stm32f7xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)

Definition at line 192 of file stm32f7xx_hal_i2s.h.

#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)

Definition at line 191 of file stm32f7xx_hal_i2s.h.

#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)

Definition at line 188 of file stm32f7xx_hal_i2s.h.

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STM32F745xx HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
#define | I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
#define | I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
#define | I2S_DATAFORMAT_32B ((uint32_t)0x00000005)

Define Documentation

#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)

Definition at line 200 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)

Definition at line 201 of file stm32f7xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)

Definition at line 202 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)

Definition at line 203 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Mclk Output

Defines
I2S Mclk Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)

Definition at line 212 of file stm32f7xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)

Definition at line 211 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K ((uint32_t)192000)
#define | I2S_AUDIOFREQ_96K ((uint32_t)96000)
#define | I2S_AUDIOFREQ_48K ((uint32_t)48000)
#define | I2S_AUDIOFREQ_44K ((uint32_t)44100)
#define | I2S_AUDIOFREQ_32K ((uint32_t)32000)
#define | I2S_AUDIOFREQ_22K ((uint32_t)22050)
#define | I2S_AUDIOFREQ_16K ((uint32_t)16000)
#define | I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define | I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define | I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)

Define Documentation

#define I2S_AUDIOFREQ_11K ((uint32_t)11025)

Definition at line 227 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K ((uint32_t)16000)

Definition at line 226 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K ((uint32_t)192000)

Definition at line 220 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K ((uint32_t)22050)

Definition at line 225 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K ((uint32_t)32000)

Definition at line 224 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K ((uint32_t)44100)

Definition at line 223 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K ((uint32_t)48000)

Definition at line 222 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K ((uint32_t)8000)

Definition at line 228 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K ((uint32_t)96000)

Definition at line 221 of file stm32f7xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)

Definition at line 229 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

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STM32F745xx HAL User Manual: I2S Clock Polarity

Defines
I2S Clock Polarity
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW ((uint32_t)0x00000000)
#define | I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)

Define Documentation

#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)

Definition at line 239 of file stm32f7xx_hal_i2s.h.

#define I2S_CPOL_LOW ((uint32_t)0x00000000)

Definition at line 238 of file stm32f7xx_hal_i2s.h.

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STM32F745xx HAL User Manual: I2S Interrupts Definition

Defines
I2S Interrupts Definition
I2S Exported Constants

Defines

#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define I2S_IT_ERR SPI_CR2_ERRIE

Definition at line 249 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define I2S_IT_RXNE SPI_CR2_RXNEIE

Definition at line 248 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

#define I2S_IT_TXE SPI_CR2_TXEIE

Definition at line 247 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

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STM32F745xx HAL User Manual: I2S Flags Definition

Defines
I2S Flags Definition
I2S Exported Constants

Defines

#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY

Define Documentation

#define I2S_FLAG_BSY SPI_SR_BSY

Definition at line 265 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit().

#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE

Definition at line 264 of file stm32f7xx_hal_i2s.h.

#define I2S_FLAG_FRE SPI_SR_FRE

Definition at line 262 of file stm32f7xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR

Definition at line 261 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_RXNE SPI_SR_RXNE

Definition at line 258 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_TXE SPI_SR_TXE

Definition at line 257 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define I2S_FLAG_UDR SPI_SR_UDR

Definition at line 260 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

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STM32F745xx HAL User Manual: I2S Exported Macros

Defines
I2S Exported Macros
I2S

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
Enable or disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.

Define Documentation

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                           \
  __IO uint32_t tmpreg = 0x00;                       \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    UNUSED(tmpreg);                             \
  } while(0)

Clears the I2S OVR pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 335 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ )
Value:
do{                                             \
__IO uint32_t tmpreg = 0x00;                         \
  tmpreg = (__HANDLE__)->Instance->SR;          \
  UNUSED(tmpreg);                               \
  } while(0)

Clears the I2S UDR pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 347 of file stm32f7xx_hal_i2s.h.

#define __HAL_I2S_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)

Definition at line 290 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))

Definition at line 302 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)

Enable or disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 289 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_DMAResume(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified I2S interrupts.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 301 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified I2S flag is set or not.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_FRE: Frame error flag
  • I2S_FLAG_CHSIDE: Channel Side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 329 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the I2S Handle. This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
__INTERRUPT__,: specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 314 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)

Reset I2S handle state.

Parameters:
__HANDLE__,: specifies the I2S handle.
Return values:
None

Definition at line 283 of file stm32f7xx_hal_i2s.h.

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STM32F745xx HAL User Manual: I2S Private Constants

I2S Private Constants
I2S
Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_I2S_CLOCKSOURCE(CLOCK)
#define | IS_I2S_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_CPOL(CPOL)

Define Documentation

#define IS_I2S_AUDIO_FREQ ( FREQ )
Value:
((((FREQ) >= I2S_AUDIOFREQ_8K) && \
                                 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
                                 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 458 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CLOCKSOURCE ( CLOCK )
Value:
(((CLOCK) == I2S_CLOCK_EXTERNAL) || \
                                   ((CLOCK) == I2S_CLOCK_SYSCLK))

Definition at line 436 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CPOL ( CPOL )
Value:
(((CPOL) == I2S_CPOL_LOW) || \
                           ((CPOL) == I2S_CPOL_HIGH))

Definition at line 462 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == I2S_DATAFORMAT_16B)          || \
                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
                                    ((FORMAT) == I2S_DATAFORMAT_32B))

Definition at line 450 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 455 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_TX) || \
                           ((MODE) == I2S_MODE_SLAVE_RX) || \
                           ((MODE) == I2S_MODE_MASTER_TX)|| \
                           ((MODE) == I2S_MODE_MASTER_RX))

Definition at line 439 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_STANDARD ( STANDARD )
Value:
(((STANDARD) == I2S_STANDARD_PHILIPS)   || \
                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))

Definition at line 444 of file stm32f7xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

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STM32F745xx HAL User Manual: I2S

Modules | Functions
I2S
STM32F7xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Private Functions
I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private Constants
I2S Private Macros

Functions

static uint32_t I2S_GetClockFreq (I2S_HandleTypeDef *hi2s)
Get I2S Input Clock based on I2S source clock selection.

Detailed Description

I2S HAL module driver.

Function Documentation

static uint32_t I2S_GetClockFreq ( I2S_HandleTypeDef * hi2s ) [static]

Get I2S Input Clock based on I2S source clock selection.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module.
Return values:
I2S Clock Input

Definition at line 1337 of file stm32f7xx_hal_i2s.c.

References I2S_InitTypeDef::ClockSource, EXTERNAL_CLOCK_VALUE, HSE_VALUE, HSI_VALUE, I2S_CLOCK_EXTERNAL, I2S_CLOCK_SYSCLK, I2S_HandleTypeDef::Init, and RCC_PLLSOURCE_HSI.

Referenced by HAL_I2S_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IrDA Initialization and de-initialization functions

Functions
IrDA Initialization and de-initialization functions
IrDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in IrDA mode.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) BaudRate
        (++) WordLength
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M bit (8-bits or 9-bits),
             please refer to Reference manual for possible IRDA frame formats.
        (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
             not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
             specification specifies a minimum of 10 ms delay between transmission and
             reception (IrDA is a half duplex protocol).
        (++) Mode: Receiver/transmitter modes
        (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
    [..]
    The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
    are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitializes the IRDA peripheral.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 265 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 216 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_SetConfig(), IRDA_HandleTypeDef::Lock, and IRDA_HandleTypeDef::State.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

IRDA MSP DeInit.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 314 of file stm32f7xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

IRDA MSP Init.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 298 of file stm32f7xx_hal_irda.c.

Referenced by HAL_IRDA_Init().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
IrDA Exported Functions

IRDA Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.

Detailed Description

IRDA Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the IRDA data transfers.
    [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two modes of transfer:
       (++) Blocking mode: the communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: the communication is performed using Interrupts
           or DMA, these API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
           will be executed respectively at the end of the Transmit or Receive process
           The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()
        (++) IRDA_Transmit_IT()
        (++) IRDA_Receive_IT()

    (#) Non-Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pauses the DMA Transfer.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 790 of file stm32f7xx_hal_irda.c.

References HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resumes the DMA Transfer.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 824 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_OREF, and IRDA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stops the DMA Transfer.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 864 of file stm32f7xx_hal_irda.c.

References HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::State.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1038 of file stm32f7xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), and IRDA_DMAError().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

This function handles IRDA interrupt request.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 899 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, __HAL_IRDA_GET_IT, __HAL_IRDA_GET_IT_SOURCE, __HAL_IRDA_SEND_REQ, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_EndTransmit_IT(), IRDA_IT_ERR, IRDA_IT_FE, IRDA_IT_NE, IRDA_IT_ORE, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_IT_TC, IRDA_IT_TXE, IRDA_Receive_IT(), IRDA_RXDATA_FLUSH_REQUEST, IRDA_Transmit_IT(), and IRDA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 469 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, IRDA_HandleTypeDef::State, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Note:
When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 729 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxXferSize, IRDA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 602 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_MASK_COMPUTATION, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, and IRDA_HandleTypeDef::State.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1022 of file stm32f7xx_hal_irda.c.

Referenced by IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1006 of file stm32f7xx_hal_irda.c.

Referenced by IRDA_DMAReceiveHalfCplt().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Sends an amount of data in blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 389 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::State, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 660 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_FLAG_TC, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::State, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 551 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_TC, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::State, IRDA_HandleTypeDef::TxXferCount, and IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 990 of file stm32f7xx_hal_irda.c.

Referenced by IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_Transmit_IT().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 974 of file stm32f7xx_hal_irda.c.

Referenced by IRDA_DMATransmitHalfCplt().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
IrDA Exported Functions

IRDA control functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA error code.

Detailed Description

IRDA control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the IRDA.
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
     (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA error code.

Parameters:
hirda : pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA.
Return values:
IRDA Error Code

Definition at line 1084 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Returns the IRDA state.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 1073 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IrDA Exported Functions

Modules | Functions
IrDA Exported Functions
IRDA

Modules

IrDA Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit/Receive functions.

Peripheral Control functions

IRDA control functions.

Functions

static void | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles IRDA Communication Timeout.
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in non blocking mode.
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA Tx transfer completed callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA Rx Transfer completed callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1155 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_TIMEOUT, IRDA_HandleTypeDef::Instance, IRDA_WaitOnFlagUntilTimeout(), IRDA_HandleTypeDef::State, and TEACK_REACK_TIMEOUT.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1492 of file stm32f7xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::State, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx Transfer completed callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1448 of file stm32f7xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::State.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1480 of file stm32f7xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback().

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx transfer completed callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1407 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, HAL_IRDA_TxCpltCallback(), IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, IRDA_IT_TC, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1436 of file stm32f7xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback().

Referenced by HAL_IRDA_Transmit_DMA().

static HAL_StatusTypeDef IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wraps up transmission in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1317 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), IRDA_IT_ERR, IRDA_IT_TC, and IRDA_HandleTypeDef::State.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in non blocking mode.

Function called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT()

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1348 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::State, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda,: irda handle
Return values:
None

Definition at line 1098 of file stm32f7xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PCLK1, IRDA_CLOCKSOURCE_PCLK2, IRDA_CLOCKSOURCE_SYSCLK, IRDA_CR1_FIELDS, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static HAL_StatusTypeDef IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1262 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_BUSY_TX_RX, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_IT_ERR, IRDA_IT_TXE, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::State, IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles IRDA Communication Timeout.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag,: specifies the IRDA flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1197 of file stm32f7xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, __HAL_IRDA_GET_FLAG, HAL_GetTick(), HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_IT_TXE, and IRDA_HandleTypeDef::State.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Exported Types

Data Structures | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00, HAL_IRDA_STATE_READY = 0x01, HAL_IRDA_STATE_BUSY = 0x02, HAL_IRDA_STATE_BUSY_TX = 0x12,
HAL_IRDA_STATE_BUSY_RX = 0x22, HAL_IRDA_STATE_BUSY_TX_RX = 0x32, HAL_IRDA_STATE_TIMEOUT = 0x03, HAL_IRDA_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00, IRDA_CLOCKSOURCE_PCLK2 = 0x01, IRDA_CLOCKSOURCE_HSI = 0x02, IRDA_CLOCKSOURCE_SYSCLK = 0x04,
IRDA_CLOCKSOURCE_LSE = 0x08
}
IRDA clock sources definition. More...

Enumeration Type Documentation

enum HAL_IRDA_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_IRDA_STATE_RESET

Peripheral is not yet Initialized

HAL_IRDA_STATE_READY

Peripheral Initialized and ready for use

HAL_IRDA_STATE_BUSY

An internal process is ongoing

HAL_IRDA_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_IRDA_STATE_BUSY_RX

Data Reception process is ongoing

HAL_IRDA_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_IRDA_STATE_TIMEOUT

Timeout state

HAL_IRDA_STATE_ERROR

Error

Definition at line 94 of file stm32f7xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_PCLK1

PCLK1 clock source

IRDA_CLOCKSOURCE_PCLK2

PCLK2 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_SYSCLK

SYSCLK clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

Definition at line 109 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32f7xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint16_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode

Detailed Description

IRDA Init Structure definition.

Definition at line 64 of file stm32f7xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate)))

Definition at line 66 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint16_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 80 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 73 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 87 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 83 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDAEx Word Length

Definition at line 70 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_irda.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32f7xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

IRDA handle Structure definition.

Definition at line 121 of file stm32f7xx_hal_irda.h.

Field Documentation

__IO uint32_t IRDA_HandleTypeDef::ErrorCode

Definition at line 149 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), and IRDA_DMAError().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmarx

Definition at line 143 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAStop(), and HAL_IRDA_Receive_DMA().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmatx

Definition at line 141 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAStop(), and HAL_IRDA_Transmit_DMA().

IRDA_InitTypeDef IRDA_HandleTypeDef::Init

Definition at line 125 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* IRDA_HandleTypeDef::Instance

Definition at line 123 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), IRDA_CheckIdleState(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

HAL_LockTypeDef IRDA_HandleTypeDef::Lock

Definition at line 145 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t IRDA_HandleTypeDef::Mask

Definition at line 139 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pRxBuffPtr

Definition at line 133 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pTxBuffPtr

Definition at line 127 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::RxXferCount

Definition at line 137 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::RxXferSize

Definition at line 135 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::State

Definition at line 147 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

uint16_t IRDA_HandleTypeDef::TxXferCount

Definition at line 131 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), IRDA_DMATransmitCplt(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::TxXferSize

Definition at line 129 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_irda.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Error Code

Defines
IRDA Error Code
IRDA Exported constants

IRDA Error Code. More...

Defines

#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010)

Detailed Description

IRDA Error Code.

Define Documentation

#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 175 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_DMAError().

#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004)

frame error

Definition at line 173 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002)

Noise error

Definition at line 172 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 170 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_CheckIdleState().

#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008)

Overrun error

Definition at line 174 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001)

Parity error

Definition at line 171 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported constants

Defines

#define | IRDA_PARITY_NONE ((uint32_t)0x0000)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 184 of file stm32f7xx_hal_irda.h.

#define IRDA_PARITY_NONE ((uint32_t)0x0000)

Definition at line 183 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 185 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported constants

Defines

#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 194 of file stm32f7xx_hal_irda.h.

#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 195 of file stm32f7xx_hal_irda.h.

#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 196 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported constants

Defines

#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x0000)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Define Documentation

#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Definition at line 205 of file stm32f7xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000)

Definition at line 204 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported constants

Defines

#define | IRDA_STATE_DISABLE ((uint32_t)0x0000)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define IRDA_STATE_DISABLE ((uint32_t)0x0000)

Definition at line 213 of file stm32f7xx_hal_irda.h.

#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Definition at line 214 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported constants

Defines

#define | IRDA_MODE_DISABLE ((uint32_t)0x0000)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Define Documentation

#define IRDA_MODE_DISABLE ((uint32_t)0x0000)

Definition at line 222 of file stm32f7xx_hal_irda.h.

#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Definition at line 223 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA One Bit

Defines
IRDA One Bit
IRDA Exported constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

Definition at line 231 of file stm32f7xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Definition at line 232 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported constants

Defines

#define | IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)

Definition at line 240 of file stm32f7xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Definition at line 241 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported constants

Defines

#define | IRDA_DMA_RX_DISABLE ((uint32_t)0x0000)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000)

Definition at line 249 of file stm32f7xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Definition at line 250 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define | IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define | IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define | IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define | IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)

Definition at line 264 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)

Definition at line 263 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)

Definition at line 262 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_FE ((uint32_t)0x00000002)

Definition at line 270 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_NE ((uint32_t)0x00000004)

Definition at line 269 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_ORE ((uint32_t)0x00000008)

Definition at line 268 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_PE ((uint32_t)0x00000001)

Definition at line 271 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_REACK ((uint32_t)0x00400000)

Definition at line 260 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)

Definition at line 267 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

#define IRDA_FLAG_TC ((uint32_t)0x00000040)

Definition at line 266 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), and HAL_IRDA_Transmit_DMA().

#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)

Definition at line 261 of file stm32f7xx_hal_irda.h.

#define IRDA_FLAG_TXE ((uint32_t)0x00000080)

Definition at line 265 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Interrupt definition

Defines
IRDA Interrupt definition
IRDA Exported constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE ((uint16_t)0x0028)
#define | IRDA_IT_TXE ((uint16_t)0x0727)
#define | IRDA_IT_TC ((uint16_t)0x0626)
#define | IRDA_IT_RXNE ((uint16_t)0x0525)
#define | IRDA_IT_IDLE ((uint16_t)0x0424)
#define | IRDA_IT_ERR ((uint16_t)0x0060)
Elements values convention: 000000000XXYYYYYb.
#define | IRDA_IT_ORE ((uint16_t)0x0300)
Elements values convention: 0000ZZZZ00000000b.
#define | IRDA_IT_NE ((uint16_t)0x0200)
#define | IRDA_IT_FE ((uint16_t)0x0100)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR ((uint16_t)0x0060)

Elements values convention: 000000000XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Definition at line 301 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit_IT(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define IRDA_IT_FE ((uint16_t)0x0100)

Definition at line 308 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_IT_IDLE ((uint16_t)0x0424)

Definition at line 290 of file stm32f7xx_hal_irda.h.

#define IRDA_IT_NE ((uint16_t)0x0200)

Definition at line 307 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_IT_ORE ((uint16_t)0x0300)

Elements values convention: 0000ZZZZ00000000b.

  • ZZZZ : Flag position in the ISR register(4bits)

Definition at line 306 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_IT_PE ((uint16_t)0x0028)

Definition at line 286 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define IRDA_IT_RXNE ((uint16_t)0x0525)

Definition at line 289 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define IRDA_IT_TC ((uint16_t)0x0626)

Definition at line 288 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Transmit_IT(), IRDA_DMATransmitCplt(), and IRDA_EndTransmit_IT().

#define IRDA_IT_TXE ((uint16_t)0x0727)

Definition at line 287 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA IT CLEAR Flags

Defines
IRDA IT CLEAR Flags
IRDA Exported constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 317 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 318 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 319 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), and HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 316 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 320 of file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported constants

Defines

#define | IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Define Documentation

#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 330 of file stm32f7xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 331 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 332 of file stm32f7xx_hal_irda.h.

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STM32F745xx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
Reset IRDA handle state.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF: Parity Error Clear Flag
  • IRDA_CLEAR_FEF: Framing Error Clear Flag
  • IRDA_CLEAR_NEF: Noise detected Clear Flag
  • IRDA_CLEAR_OREF: OverRun Error Clear Flag
  • IRDA_CLEAR_TCF: Transmission Complete Clear Flag
Return values:
None

Definition at line 460 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_IRQHandler(), and HAL_IRDA_Transmit_DMA().

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
Return values:
None

Definition at line 487 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
__INTERRUPT__,: specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_PE: Parity Error interrupt
  • IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 408 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
Return values:
None

Definition at line 480 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                          ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                          ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2. UART peripheral
__INTERRUPT__,: specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_PE: Parity Error interrupt
  • IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 391 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit_IT(), and IRDA_DMATransmitCplt().

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2. UART peripheral
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK: Receive enable acknowledge flag
  • IRDA_FLAG_TEACK: Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY: Busy flag
  • IRDA_FLAG_ABRF: Auto Baud rate detection flag
  • IRDA_FLAG_ABRE: Auto Baud rate detection error flag
  • IRDA_FLAG_TXE: Transmit data register empty flag
  • IRDA_FLAG_TC: Transmission Complete flag
  • IRDA_FLAG_RXNE: Receive data register not empty flag
  • IRDA_FLAG_IDLE: Idle Line detection flag
  • IRDA_FLAG_ORE: OverRun Error flag
  • IRDA_FLAG_NE: Noise Error flag
  • IRDA_FLAG_FE: Framing Error flag
  • IRDA_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 375 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_ORE: OverRun Error interrupt
  • IRDA_IT_NE: Noise Error interrupt
  • IRDA_IT_FE: Framing Error interrupt
  • IRDA_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 427 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
                                                          (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))

Check whether the specified IRDA interrupt source is enabled.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_ORE: OverRun Error interrupt
  • IRDA_IT_NE: Noise Error interrupt
  • IRDA_IT_FE: Framing Error interrupt
  • IRDA_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 444 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)

Reset IRDA handle state.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
Return values:
None

Definition at line 352 of file stm32f7xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. The Handle Instance which can be USART1 or USART2.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
Return values:
None

Definition at line 473 of file stm32f7xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

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STM32F745xx HAL User Manual: IRDA Interruption Mask

Defines
IRDA Interruption Mask
IRDA Private Constants

Defines

#define IRDA_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define IRDA_IT_MASK ((uint16_t)0x001F)

Definition at line 562 of file stm32f7xx_hal_irda.h.

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STM32F745xx HAL User Manual: IRDA Private Constants

Modules | Defines
IRDA Private Constants
IRDA

Modules

IRDA Interruption Mask

Defines

#define | TEACK_REACK_TIMEOUT 1000
#define | HAL_IRDA_TXDMA_TIMEOUTVALUE 22000
#define | IRDA_CR1_FIELDS

Define Documentation

#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000

Definition at line 146 of file stm32f7xx_hal_irda.c.

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

Definition at line 147 of file stm32f7xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define TEACK_REACK_TIMEOUT 1000

Definition at line 145 of file stm32f7xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

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STM32F745xx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
#define | IS_IRDA_POWERMODE(__MODE__)
#define | IS_IRDA_STATE(__STATE__)
#define | IS_IRDA_MODE(__STATE__)
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
#define | IS_IRDA_DMA_TX(__DMATX__)
#define | IS_IRDA_DMA_RX(__DMARX__)
#define | IS_IRDA_REQUEST_PARAMETER(PARAM)

Define Documentation

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__,: specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 579 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Definition at line 608 of file stm32f7xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Definition at line 605 of file stm32f7xx_hal_irda.h.

#define IS_IRDA_MODE ( __STATE__ )
Value:
(((__STATE__) == IRDA_MODE_DISABLE) || \
                                  ((__STATE__) == IRDA_MODE_ENABLE))

Definition at line 599 of file stm32f7xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                               ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Definition at line 602 of file stm32f7xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Definition at line 587 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Definition at line 593 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__,: specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 585 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( PARAM )
Value:
(((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
                                          ((PARAM) == IRDA_SENDBREAK_REQUEST) || \
                                          ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
                                          ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                          ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))

Definition at line 611 of file stm32f7xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Definition at line 596 of file stm32f7xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))

Definition at line 591 of file stm32f7xx_hal_irda.h.

Referenced by IRDA_SetConfig().

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STM32F745xx HAL User Manual: IRDA Private Functions

IRDA Private Functions
IRDA
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG HAL module driver

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
#define | IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA)
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC)
#define | IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555)
#define | IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000)
#define | IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU)
IWDG Flag definition.
#define | IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU)
#define | IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU)

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000

Definition at line 135 of file stm32f7xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init(), HAL_IWDG_Refresh(), and HAL_IWDG_Start().

#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU)

IWDG Flag definition.

Watchdog counter prescaler value update flag

Definition at line 236 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Start().

#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU)

Watchdog counter reload value update flag

Definition at line 237 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), HAL_IWDG_Refresh(), and HAL_IWDG_Start().

#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU)

Watchdog counter window value update flag

Definition at line 238 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Start().

#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC)

IWDG Peripheral Enable

Definition at line 229 of file stm32f7xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA)

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 228 of file stm32f7xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000)

IWDG KR Write Access Disable

Definition at line 231 of file stm32f7xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555)

IWDG KR Write Access Enable

Definition at line 230 of file stm32f7xx_hal_iwdg.h.

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STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.
__weak void | HAL_IWDG_MspInit (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters
          in the IWDG_InitTypeDef and create the associated handle
      (+) Manage Window option
      (+) Initialize the IWDG MSP
      (+) DeInitialize IWDG MSP

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 174 of file stm32f7xx_hal_iwdg.c.

References __HAL_IWDG_GET_FLAG, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, HAL_IWDG_MspInit(), HAL_IWDG_STATE_BUSY, HAL_IWDG_STATE_READY, HAL_IWDG_STATE_RESET, HAL_IWDG_STATE_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_FLAG_PVU, IWDG_FLAG_RVU, IWDG_FLAG_WVU, IWDG_WINDOW_DISABLE, IWDG_HandleTypeDef::Lock, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, IWDG_HandleTypeDef::State, and IWDG_InitTypeDef::Window.

void HAL_IWDG_MspInit ( IWDG_HandleTypeDef * hiwdg )

Initializes the IWDG MSP.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
None

Definition at line 250 of file stm32f7xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_IWDG_Start (IWDG_HandleTypeDef *hiwdg)
Starts the IWDG.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refreshes the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the IWDG.
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refreshes the IWDG.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 340 of file stm32f7xx_hal_iwdg.c.

References __HAL_IWDG_GET_FLAG, __HAL_IWDG_RELOAD_COUNTER, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, HAL_IWDG_STATE_BUSY, HAL_IWDG_STATE_READY, HAL_IWDG_STATE_TIMEOUT, IWDG_FLAG_RVU, and IWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IWDG_Start ( IWDG_HandleTypeDef * hiwdg )

Starts the IWDG.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 285 of file stm32f7xx_hal_iwdg.c.

References __HAL_IWDG_GET_FLAG, __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, HAL_IWDG_STATE_BUSY, HAL_IWDG_STATE_READY, HAL_IWDG_STATE_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_FLAG_PVU, IWDG_FLAG_RVU, IWDG_FLAG_WVU, IWDG_WINDOW_DISABLE, IWDG_HandleTypeDef::State, and IWDG_InitTypeDef::Window.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
IWDG Exported Functions

Peripheral State functions. More...

Functions

HAL_IWDG_StateTypeDef HAL_IWDG_GetState (IWDG_HandleTypeDef *hiwdg)
Returns the IWDG state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_IWDG_StateTypeDef HAL_IWDG_GetState ( IWDG_HandleTypeDef * hiwdg )

Returns the IWDG state.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL state

Definition at line 404 of file stm32f7xx_hal_iwdg.c.

References IWDG_HandleTypeDef::State.

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STM32F745xx HAL User Manual: IWDG Exported Types

Data Structures | Enumerations
IWDG Exported Types
IWDG HAL module driver

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Enumerations

enum HAL_IWDG_StateTypeDef {
HAL_IWDG_STATE_RESET = 0x00, HAL_IWDG_STATE_READY = 0x01, HAL_IWDG_STATE_BUSY = 0x02, HAL_IWDG_STATE_TIMEOUT = 0x03,
HAL_IWDG_STATE_ERROR = 0x04
}
IWDG HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_IWDG_StateTypeDef

IWDG HAL State Structure definition.

Enumerator:
HAL_IWDG_STATE_RESET

IWDG not yet initialized or disabled

HAL_IWDG_STATE_READY

IWDG initialized and ready for use

HAL_IWDG_STATE_BUSY

IWDG internal process is ongoing

HAL_IWDG_STATE_TIMEOUT

IWDG timeout state

HAL_IWDG_STATE_ERROR

IWDG error state

Definition at line 65 of file stm32f7xx_hal_iwdg.h.

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STM32F745xx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32f7xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 78 of file stm32f7xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 80 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 83 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 86 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Start().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_iwdg.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32f7xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * | Instance
IWDG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_IWDG_StateTypeDef | State

Detailed Description

IWDG Handle Structure definition.

Definition at line 94 of file stm32f7xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 98 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Start().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 96 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

HAL_LockTypeDef IWDG_HandleTypeDef::Lock

IWDG Locking object

Definition at line 100 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

__IO HAL_IWDG_StateTypeDef IWDG_HandleTypeDef::State

IWDG communication state

Definition at line 102 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_GetState(), HAL_IWDG_Init(), HAL_IWDG_Refresh(), and HAL_IWDG_Start().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_iwdg.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 ((uint8_t)0x00)
#define | IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0))
#define | IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1))
#define | IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2))
#define | IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))

Define Documentation

#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))

IWDG prescaler set to 128

Definition at line 123 of file stm32f7xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1))

IWDG prescaler set to 16

Definition at line 120 of file stm32f7xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))

IWDG prescaler set to 256

Definition at line 124 of file stm32f7xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))

IWDG prescaler set to 32

Definition at line 121 of file stm32f7xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 ((uint8_t)0x00)

IWDG prescaler set to 4

Definition at line 118 of file stm32f7xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2))

IWDG prescaler set to 64

Definition at line 122 of file stm32f7xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0))

IWDG prescaler set to 8

Definition at line 119 of file stm32f7xx_hal_iwdg.h.

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STM32F745xx HAL User Manual: IWDG Window

Defines
IWDG Window
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)

Define Documentation

#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)

Definition at line 132 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Start().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG HAL module driver

Defines

#define | __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
Reset IWDG handle state.
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enables the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
#define | __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected IWDG's flag status.

Define Documentation

#define __HAL_IWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Gets the selected IWDG's flag status.

Parameters:
__HANDLE__,: IWDG handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IWDG_FLAG_PVU: Watchdog counter reload value update flag
  • IWDG_FLAG_RVU: Watchdog counter prescaler value flag
  • IWDG_FLAG_WVU: Watchdog counter window value flag
Return values:
The new state of __FLAG__ (TRUE or FALSE) .

Definition at line 177 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), HAL_IWDG_Refresh(), and HAL_IWDG_Start().

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 165 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Refresh(), and HAL_IWDG_Start().

#define __HAL_IWDG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)

Reset IWDG handle state.

Parameters:
__HANDLE__,: IWDG handle.
Return values:
None

Definition at line 150 of file stm32f7xx_hal_iwdg.h.

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enables the IWDG peripheral.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 157 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Start().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG HAL module driver

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__,: IWDG prescaler value
Return values:
None

Definition at line 267 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= 0xFFF)

Check IWDG reload value.

Parameters:
__RELOAD__,: IWDG reload value
Return values:
None

Definition at line 280 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= 0xFFF)

Check IWDG window value.

Parameters:
__WINDOW__,: IWDG window value
Return values:
None

Definition at line 287 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 260 of file stm32f7xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 253 of file stm32f7xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Defines

LPTIM Private Defines
LPTIM
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and creates the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 321 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 228 of file stm32f7xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

__weak void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 368 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

__weak void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 353 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1226 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1290 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1265 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1335 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 913 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 991 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 963 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1048 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 583 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 647 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 620 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 703 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 417 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 481 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 454 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 537 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 749 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 813 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 786 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 869 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1086 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function in interrupt mode.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1155 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1123 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1195 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

This function return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1396 of file stm32f7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

This function return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1409 of file stm32f7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

This function returns the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1383 of file stm32f7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM IRQ handler

Functions
LPTIM IRQ handler
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.

Detailed Description

LPTIM IRQ handler.

  ==============================================================================
                      ##### LPTIM IRQ handler  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler function.

Function Documentation

__weak void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1548 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1593 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1533 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1578 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1623 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1608 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

This function handles LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1441 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

__weak void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1563 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Returns the LPTIM state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1656 of file stm32f7xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Exported Functions

Modules | Functions
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1548 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1593 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1533 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1578 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1226 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1290 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1265 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1335 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 321 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1623 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1608 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 913 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 991 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 963 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1048 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Returns the LPTIM state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1656 of file stm32f7xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 228 of file stm32f7xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

This function handles LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1441 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 368 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 353 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 583 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 647 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 620 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 703 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 417 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 481 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 454 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 537 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

This function return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1396 of file stm32f7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

This function return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1409 of file stm32f7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

This function returns the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1383 of file stm32f7xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 749 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 813 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 786 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 869 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1086 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function in interrupt mode.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1155 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1123 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1195 of file stm32f7xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1563 of file stm32f7xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Exported Types

Data Structures | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00, HAL_LPTIM_STATE_READY = 0x01, HAL_LPTIM_STATE_BUSY = 0x02, HAL_LPTIM_STATE_TIMEOUT = 0x03,
HAL_LPTIM_STATE_ERROR = 0x04
}
HAL LPTIM State structure definition. More...

Typedef Documentation

typedef enum __HAL_LPTIM_StateTypeDef HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumeration Type Documentation

enum __HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 138 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32f7xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 66 of file stm32f7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 71 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 68 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_lptim.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32f7xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 79 of file stm32f7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 81 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 88 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_lptim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32f7xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 97 of file stm32f7xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 102 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 106 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 99 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_lptim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32f7xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 114 of file stm32f7xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 116 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 129 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 122 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 120 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 118 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autorelaod and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 125 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_lptim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32f7xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State

Detailed Description

LPTIM handle Structure definition.

Definition at line 150 of file stm32f7xx_hal_lptim.h.

Field Documentation

LPTIM_InitTypeDef LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 154 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 152 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_LockTypeDef LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 158 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

__IO HAL_LPTIM_StateTypeDef LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 160 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_StatusTypeDef LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 156 of file stm32f7xx_hal_lptim.h.

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_lptim.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)

Definition at line 176 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 177 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Define Documentation

#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)

Definition at line 185 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Definition at line 192 of file stm32f7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 189 of file stm32f7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 186 of file stm32f7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))

Definition at line 190 of file stm32f7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 187 of file stm32f7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))

Definition at line 191 of file stm32f7xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))

Definition at line 188 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)

Definition at line 201 of file stm32f7xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Definition at line 202 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 211 of file stm32f7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 212 of file stm32f7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 213 of file stm32f7xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)

Definition at line 210 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 223 of file stm32f7xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)

Definition at line 222 of file stm32f7xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 224 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Define Documentation

#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)

Definition at line 233 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)

Definition at line 234 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 235 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 236 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 237 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 238 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)

Definition at line 232 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 247 of file stm32f7xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 246 of file stm32f7xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 248 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 257 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 258 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 259 of file stm32f7xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)

Definition at line 256 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 269 of file stm32f7xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)

Definition at line 268 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 279 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)

Definition at line 278 of file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Flag Definition

Defines
LPTIM Flag Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 293 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 290 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 294 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 291 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 288 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 292 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 289 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 308 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 305 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 309 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 306 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 303 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 307 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 304 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable/Disable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Starts the LPTIM peripheral in Continuous or in single mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Writes the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Writes the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Checks whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified LPTIM interrupt is set or not.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Writes the passed parameter in the Autoreload register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__ : Autoreload value
Return values:
None

Definition at line 352 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clears the specified LPTIM flag.

Parameters:
__HANDLE__,: LPTIM handle.
__FLAG__ : LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 392 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Writes the passed parameter in the Compare register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__ : Compare value
Return values:
None

Definition at line 360 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))

Definition at line 335 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.

Definition at line 424 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable/Disable the LPTIM peripheral.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 334 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.

Definition at line 408 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Checks whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__,: LPTIM handle
__FLAG__ : LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 376 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks whether the specified LPTIM interrupt is set or not.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 441 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)

Reset LPTIM handle state.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 327 of file stm32f7xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Starts the LPTIM peripheral in Continuous or in single mode.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 342 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Definition at line 343 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Constants

LPTIM Private Constants
LPTIM
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define | IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF)
#define | IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF)

Define Documentation

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ ) ((__AUTORELOAD__) <= 0x0000FFFF)

Definition at line 613 of file stm32f7xx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 586 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 568 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 576 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 581 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                     ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 565 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFF)

Definition at line 615 of file stm32f7xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                     ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 610 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLAR__ )
Value:
(((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 598 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                     ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 578 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( PERIOD ) ((PERIOD) <= 0x0000FFFF)

Definition at line 617 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( PULSE ) ((PULSE) <= 0x0000FFFF)

Definition at line 619 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                                                ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                                                ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                                                ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                                                ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                                                ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                                                ((__TRIG__) == LPTIM_TRIGSOURCE_5))

Definition at line 590 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 602 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                     ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 607 of file stm32f7xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Functions

LPTIM Private Functions
LPTIM
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LPTIM Private Functions Prototypes

LPTIM Private Functions Prototypes
LPTIM
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NAND Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### NAND Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NAND memory

Function Documentation

HAL_StatusTypeDef HAL_NAND_DeInit ( NAND_HandleTypeDef * hnand )

Perform NAND memory De-Initialization sequence.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 174 of file stm32f7xx_hal_nand.c.

References HAL_NAND_MspDeInit(), HAL_NAND_STATE_RESET, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Init | ( | NAND_HandleTypeDef * | hnand,
 |  | FMC_NAND_PCC_TimingTypeDef * | ComSpace_Timing,
 |  | FMC_NAND_PCC_TimingTypeDef * | AttSpace_Timing
 | ) |  |

Perform NAND memory Initialization sequence.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ComSpace_Timing,: pointer to Common space timing structure
AttSpace_Timing,: pointer to Attribute space timing structure
Return values:
HAL status

Definition at line 134 of file stm32f7xx_hal_nand.c.

References HAL_NAND_MspInit(), HAL_NAND_STATE_READY, HAL_NAND_STATE_RESET, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, NAND_HandleTypeDef::Lock, and NAND_HandleTypeDef::State.

void HAL_NAND_IRQHandler ( NAND_HandleTypeDef * hnand )

This function handles NAND device interrupt request.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 230 of file stm32f7xx_hal_nand.c.

References HAL_NAND_ITCallback(), NAND_HandleTypeDef::Init, and NAND_HandleTypeDef::Instance.

void HAL_NAND_ITCallback ( NAND_HandleTypeDef * hnand )

NAND interrupt feature callback.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 280 of file stm32f7xx_hal_nand.c.

Referenced by HAL_NAND_IRQHandler().

void HAL_NAND_MspDeInit ( NAND_HandleTypeDef * hnand )

NAND MSP DeInit.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 213 of file stm32f7xx_hal_nand.c.

Referenced by HAL_NAND_DeInit().

void HAL_NAND_MspInit ( NAND_HandleTypeDef * hnand )

NAND MSP Init.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 197 of file stm32f7xx_hal_nand.c.

Referenced by HAL_NAND_Init().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
NAND Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Write_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory.
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory.
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### NAND Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NAND
    memory

Function Documentation

uint32_t HAL_NAND_Address_Inc | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

Increment the NAND memory address.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
Return values:
The new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 845 of file stm32f7xx_hal_nand.c.

References NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, NAND_HandleTypeDef::Info, NAND_INVALID_ADDRESS, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_AddressTypeDef::Zone, and NAND_InfoTypeDef::ZoneSize.

HAL_StatusTypeDef HAL_NAND_Erase_Block | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

NAND memory Block erase.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress : pointer to NAND address structure
Return values:
HAL status

Definition at line 757 of file stm32f7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_InfoTypeDef::BlockNbr, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_CMD_ERASE0, NAND_CMD_ERASE1, NAND_DEVICE, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_ID | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_IDTypeDef * | pNAND_ID
 | ) |  |

Read the NAND memory electronic signature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pNAND_ID,: NAND ID structure
Return values:
HAL status

Definition at line 316 of file stm32f7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, CMD_AREA, NAND_IDTypeDef::Device_Id, NAND_IDTypeDef::Fourth_Id, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_IDTypeDef::Maker_Id, NAND_CMD_READID, NAND_DEVICE, NAND_HandleTypeDef::State, and NAND_IDTypeDef::Third_Id.

HAL_StatusTypeDef HAL_NAND_Read_Page | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToRead
 | ) |  |

Read Page(s) from NAND memory block.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to destination read buffer
NumPageToRead | : number of pages to read from block
Return values:
HAL status

Definition at line 406 of file stm32f7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_CMD_AREA_A, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_InfoTypeDef::PageSize, NAND_HandleTypeDef::State, and NAND_InfoTypeDef::ZoneSize.

HAL_StatusTypeDef HAL_NAND_Read_SpareArea | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

Read Spare area(s) from NAND memory.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress : pointer to NAND address structure
pBuffer,: pointer to source buffer to write
NumSpareAreaToRead,: Number of spare area to read
Return values:
HAL status

Definition at line 583 of file stm32f7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_CMD_AREA_C, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_InfoTypeDef::SpareAreaSize, NAND_HandleTypeDef::State, and NAND_InfoTypeDef::ZoneSize.

uint32_t HAL_NAND_Read_Status ( NAND_HandleTypeDef * hnand )

NAND memory read status.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
NAND status

Definition at line 809 of file stm32f7xx_hal_nand.c.

References CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_DEVICE, NAND_ERROR, and NAND_READY.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

HAL_StatusTypeDef HAL_NAND_Reset ( NAND_HandleTypeDef * hnand )

NAND memory reset.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 364 of file stm32f7xx_hal_nand.c.

References CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_DEVICE, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_Page | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToWrite
 | ) |  |

Write Page(s) to NAND memory block.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to source buffer to write
NumPageToWrite | : number of pages to write to block
Return values:
HAL status

Definition at line 487 of file stm32f7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, CMD_AREA, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_InfoTypeDef::PageSize, NAND_HandleTypeDef::State, and NAND_InfoTypeDef::ZoneSize.

HAL_StatusTypeDef HAL_NAND_Write_SpareArea | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

Write Spare area(s) to NAND memory.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress | : pointer to NAND address structure
pBuffer | : pointer to source buffer to write
NumSpareAreaTowrite | : number of spare areas to write to block
Return values:
HAL status

Definition at line 663 of file stm32f7xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, CMD_AREA, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, NAND_InfoTypeDef::PageSize, NAND_InfoTypeDef::SpareAreaSize, NAND_HandleTypeDef::State, and NAND_InfoTypeDef::ZoneSize.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
NAND Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.

Detailed Description

management functions

  ==============================================================================
                         ##### NAND Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NAND interface.

Function Documentation

HAL_StatusTypeDef HAL_NAND_ECC_Disable ( NAND_HandleTypeDef * hnand )

Disables dynamically FMC_NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 924 of file stm32f7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_ECC_Enable ( NAND_HandleTypeDef * hnand )

Enables dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 898 of file stm32f7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_GetECC | ( | NAND_HandleTypeDef * | hnand,
 |  | uint32_t * | ECCval,
 |  | uint32_t | Timeout
 | ) |  |

Disables dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ECCval,: pointer to ECC value
Timeout,: maximum timeout to wait
Return values:
HAL status

Definition at line 952 of file stm32f7xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
NAND Exported Functions

Peripheral State functions. More...

Functions

HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                         ##### NAND State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NAND controller
    and the data flow.

Function Documentation

HAL_NAND_StateTypeDef HAL_NAND_GetState ( NAND_HandleTypeDef * hnand )

return the NAND state

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL state

Definition at line 1000 of file stm32f7xx_hal_nand.c.

References NAND_HandleTypeDef::State.

uint32_t HAL_NAND_Read_Status ( NAND_HandleTypeDef * hnand )

NAND memory read status.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
NAND status

Definition at line 809 of file stm32f7xx_hal_nand.c.

References CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_DEVICE, NAND_ERROR, and NAND_READY.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND Exported Types

Data Structures | Enumerations
NAND Exported Types
NAND

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_InfoTypeDef
NAND Memory info Structure definition. More...
struct | NAND_HandleTypeDef
NAND handle Structure definition. More...

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00, HAL_NAND_STATE_READY = 0x01, HAL_NAND_STATE_BUSY = 0x02, HAL_NAND_STATE_ERROR = 0x03 }
HAL NAND State structures definition. More...

Enumeration Type Documentation

enum HAL_NAND_StateTypeDef

HAL NAND State structures definition.

Enumerator:
HAL_NAND_STATE_RESET

NAND not yet initialized or disabled

HAL_NAND_STATE_READY

NAND initialized and ready for use

HAL_NAND_STATE_BUSY

NAND internal process is ongoing

HAL_NAND_STATE_ERROR

NAND error state

Definition at line 66 of file stm32f7xx_hal_nand.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_IDTypeDef Struct Reference
NAND Exported Types

NAND Memory electronic signature Structure definition. More...

#include <stm32f7xx_hal_nand.h>

Data Fields

uint8_t | Maker_Id
uint8_t | Device_Id
uint8_t | Third_Id
uint8_t | Fourth_Id

Detailed Description

NAND Memory electronic signature Structure definition.

Definition at line 77 of file stm32f7xx_hal_nand.h.

Field Documentation

uint8_t NAND_IDTypeDef::Device_Id

Definition at line 83 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Fourth_Id

Definition at line 87 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Maker_Id

Definition at line 81 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Third_Id

Definition at line 85 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nand.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND_AddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_AddressTypeDef Struct Reference
NAND Exported Types

NAND Memory address Structure definition. More...

#include <stm32f7xx_hal_nand.h>

Data Fields

uint16_t | Page
uint16_t | Zone
uint16_t | Block

Detailed Description

NAND Memory address Structure definition.

Definition at line 93 of file stm32f7xx_hal_nand.h.

Field Documentation

uint16_t NAND_AddressTypeDef::Block

NAND memory Block address

Definition at line 99 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

uint16_t NAND_AddressTypeDef::Page

NAND memory Page address

Definition at line 95 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

uint16_t NAND_AddressTypeDef::Zone

NAND memory Zone address

Definition at line 97 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nand.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND_InfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_InfoTypeDef Struct Reference
NAND Exported Types

NAND Memory info Structure definition. More...

#include <stm32f7xx_hal_nand.h>

Data Fields

uint32_t | PageSize
uint32_t | SpareAreaSize
uint32_t | BlockSize
uint32_t | BlockNbr
uint32_t | ZoneSize

Detailed Description

NAND Memory info Structure definition.

Definition at line 106 of file stm32f7xx_hal_nand.h.

Field Documentation

uint32_t NAND_InfoTypeDef::BlockNbr

NAND memory number of blocks

Definition at line 114 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Erase_Block(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

uint32_t NAND_InfoTypeDef::BlockSize

NAND memory block size number of pages

Definition at line 112 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

uint32_t NAND_InfoTypeDef::PageSize

NAND memory page (without spare area) size measured in K. bytes

Definition at line 108 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

uint32_t NAND_InfoTypeDef::SpareAreaSize

NAND memory spare area size measured in K. bytes

Definition at line 110 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea(), and HAL_NAND_Write_SpareArea().

uint32_t NAND_InfoTypeDef::ZoneSize

NAND memory zone size measured in number of blocks

Definition at line 116 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nand.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_HandleTypeDef Struct Reference
NAND Exported Types

NAND handle Structure definition. More...

#include <stm32f7xx_hal_nand.h>

Data Fields

FMC_NAND_TypeDef * | Instance
FMC_NAND_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NAND_StateTypeDef | State
NAND_InfoTypeDef Info

Detailed Description

NAND handle Structure definition.

Definition at line 122 of file stm32f7xx_hal_nand.h.

Field Documentation

NAND_InfoTypeDef NAND_HandleTypeDef::Info

NAND characteristic information structure

Definition at line 132 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Erase_Block(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

FMC_NAND_InitTypeDef NAND_HandleTypeDef::Init

NAND device control configuration parameters

Definition at line 126 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), and HAL_NAND_IRQHandler().

FMC_NAND_TypeDef* NAND_HandleTypeDef::Instance

Register base address

Definition at line 124 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), and HAL_NAND_IRQHandler().

HAL_LockTypeDef NAND_HandleTypeDef::Lock

NAND locking object

Definition at line 128 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Init().

__IO HAL_NAND_StateTypeDef NAND_HandleTypeDef::State

NAND device access state

Definition at line 130 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_Erase_Block(), HAL_NAND_GetECC(), HAL_NAND_GetState(), HAL_NAND_Init(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Reset(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nand.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND Exported Macros

Defines
NAND Exported Macros
NAND

Defines

#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
Reset NAND handle state.

Define Documentation

#define __HAL_NAND_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)

Reset NAND handle state.

Parameters:
__HANDLE__,: specifies the NAND handle.
Return values:
None

Definition at line 148 of file stm32f7xx_hal_nand.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND Private Constants

Defines
NAND Private Constants
NAND

Defines

#define | NAND_DEVICE ((uint32_t)0x80000000)
#define | NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
#define | CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00)
#define | NAND_CMD_AREA_B ((uint8_t)0x01)
#define | NAND_CMD_AREA_C ((uint8_t)0x50)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define | NAND_CMD_READID ((uint8_t)0x90)
#define | NAND_CMD_STATUS ((uint8_t)0x70)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define | NAND_CMD_RESET ((uint8_t)0xFF)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define | NAND_BUSY ((uint32_t)0x00000000)
#define | NAND_ERROR ((uint32_t)0x00000001)
#define | NAND_READY ((uint32_t)0x00000040)

Define Documentation

#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */

Definition at line 230 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */

Definition at line 229 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_BUSY ((uint32_t)0x00000000)

Definition at line 250 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_AREA_A ((uint8_t)0x00)

Definition at line 232 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page(), and HAL_NAND_Write_Page().

#define NAND_CMD_AREA_B ((uint8_t)0x01)

Definition at line 233 of file stm32f7xx_hal_nand.h.

#define NAND_CMD_AREA_C ((uint8_t)0x50)

Definition at line 234 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea(), and HAL_NAND_Write_SpareArea().

#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)

Definition at line 235 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page(), and HAL_NAND_Read_SpareArea().

#define NAND_CMD_ERASE0 ((uint8_t)0x60)

Definition at line 239 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_ERASE1 ((uint8_t)0xD0)

Definition at line 240 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)

Definition at line 243 of file stm32f7xx_hal_nand.h.

#define NAND_CMD_READID ((uint8_t)0x90)

Definition at line 241 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

#define NAND_CMD_RESET ((uint8_t)0xFF)

Definition at line 244 of file stm32f7xx_hal_nand.h.

#define NAND_CMD_STATUS ((uint8_t)0x70)

Definition at line 242 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_WRITE0 ((uint8_t)0x80)

Definition at line 237 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)

Definition at line 238 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_DEVICE ((uint32_t)0x80000000)

Definition at line 226 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_ERROR ((uint32_t)0x00000001)

Definition at line 251 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)

Definition at line 248 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

#define NAND_READY ((uint32_t)0x00000040)

Definition at line 252 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)

Definition at line 249 of file stm32f7xx_hal_nand.h.

#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)

Definition at line 247 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc().

#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)

Definition at line 227 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND Private Macros

Defines
NAND Private Macros
NAND

Defines

#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Define Documentation

#define ADDR_1ST_CYCLE ( __ADDRESS__ ) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */

NAND memory address cycling.

Parameters:
__ADDRESS__,: NAND memory address.
Return values:
NAND address cycling value.

Definition at line 276 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ADDR_2ND_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */

Definition at line 277 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ADDR_3RD_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */

Definition at line 278 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ADDR_4TH_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Definition at line 279 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ARRAY_ADDRESS | ( | __ADDRESS__,
 |  | __HANDLE__
 | ) |
Value:
((__ADDRESS__)->Page + \
                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))

NAND memory address computation.

Parameters:
__ADDRESS__,: NAND memory address.
__HANDLE__ : NAND handle.
Return values:
NAND Raw address value

Definition at line 268 of file stm32f7xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Private Defines

Defines
NOR Private Defines
NOR

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Define Documentation

#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA

Definition at line 111 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555

Definition at line 106 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055

Definition at line 107 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555

Definition at line 110 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA

Definition at line 108 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555

Definition at line 112 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555

Definition at line 109 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090

Definition at line 118 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Read_ID().

#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30

Definition at line 128 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block().

#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25

Definition at line 126 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29

Definition at line 127 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_CFI (uint16_t)0x0098

Definition at line 124 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055

Definition at line 122 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA

Definition at line 121 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080

Definition at line 120 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010

Definition at line 123 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA

Definition at line 116 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0

Definition at line 119 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Program().

#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0

Definition at line 115 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Read(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_CMD_DATA_SECOND (uint16_t)0x0055

Definition at line 117 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020

Definition at line 131 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Definition at line 132 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NOR Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### NOR Initialization and de_initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_DeInit ( NOR_HandleTypeDef * hnor )

Perform NOR memory De-Initialization sequence.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 209 of file stm32f7xx_hal_nor.c.

References NOR_HandleTypeDef::Extended, HAL_NOR_MspDeInit(), HAL_NOR_STATE_RESET, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Init | ( | NOR_HandleTypeDef * | hnor,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Perform the NOR memory Initialization sequence.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timing,: pointer to NOR control timing structure
ExtTiming,: pointer to NOR extended mode timing structure
Return values:
HAL status

Definition at line 169 of file stm32f7xx_hal_nor.c.

References NOR_HandleTypeDef::Extended, HAL_NOR_MspInit(), HAL_NOR_STATE_READY, HAL_NOR_STATE_RESET, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, NOR_HandleTypeDef::Lock, and NOR_HandleTypeDef::State.

void HAL_NOR_MspDeInit ( NOR_HandleTypeDef * hnor )

NOR MSP DeInit.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 248 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_DeInit().

void HAL_NOR_MspInit ( NOR_HandleTypeDef * hnor )

NOR MSP Init.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 232 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_Init().

void HAL_NOR_MspWait | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Timeout
 | ) |  |

NOR MSP Wait for Ready/Busy signal.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timeout,: Maximum timeout value
Return values:
None

Definition at line 265 of file stm32f7xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
NOR Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                ##### NOR Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_Erase_Block | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | BlockAddress,
 |  | uint32_t | Address
 | ) |  |

Erase the specified block of the NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
BlockAddress : Block to erase address
Address,: Device address
Return values:
HAL status

Definition at line 674 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_BLOCK_ERASE, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Erase_Chip | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address
 | ) |  |

Erase the entire NOR chip.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address : Device address
Return values:
HAL status

Definition at line 733 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_SIXTH, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_CHIP_ERASE, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Program | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Program data to NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress,: Device address
pData : pointer to the data to write
Return values:
HAL status

Definition at line 469 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_PROGRAM, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_ProgramBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Writes a half-word buffer to the NOR memory.

This function must be used only with S29GL128P NOR memory.

Parameters:
hnor,: pointer to the NOR handle
uwAddress,: NOR memory internal start write address
pData,: pointer to source data buffer.
uwBufferSize,: Size of the buffer to write
Return values:
HAL status

Definition at line 594 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_DATA_BUFFER_AND_PROG, NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Read | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Read data from NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress,: pointer to Device address
pData : pointer to read data
Return values:
HAL status

Definition at line 410 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Read_CFI | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_CFITypeDef * | pNOR_CFI
 | ) |  |

Read NOR flash CFI IDs.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_CFI : pointer to NOR CFI IDs structure
Return values:
HAL status

Definition at line 791 of file stm32f7xx_hal_nor.c.

References CFI1_ADDRESS, CFI2_ADDRESS, CFI3_ADDRESS, CFI4_ADDRESS, NOR_CFITypeDef::CFI_1, NOR_CFITypeDef::CFI_2, NOR_CFITypeDef::CFI_3, NOR_CFITypeDef::CFI_4, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST_CFI, NOR_CMD_DATA_CFI, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Read_ID | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_IDTypeDef * | pNOR_ID
 | ) |  |

Read NOR flash IDs.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_ID : pointer to NOR ID structure
Return values:
HAL status

Definition at line 300 of file stm32f7xx_hal_nor.c.

References NOR_IDTypeDef::Device_Code1, DEVICE_CODE1_ADDR, NOR_IDTypeDef::Device_Code2, DEVICE_CODE2_ADDR, NOR_IDTypeDef::Device_Code3, DEVICE_CODE3_ADDR, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_IDTypeDef::Manufacturer_Code, MC_ADDRESS, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_AUTO_SELECT, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_ReadBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Reads a half-word buffer from the NOR memory.

Parameters:
hnor,: pointer to the NOR handle
uwAddress,: NOR memory internal address to read from.
pData,: pointer to the buffer that receives the data read from the NOR memory.
uwBufferSize : number of Half word to read.
Return values:
HAL status

Definition at line 529 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_8B, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_ReturnToReadMode ( NOR_HandleTypeDef * hnor )

Returns the NOR memory to Read mode.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 360 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_CMD_DATA_READ_RESET, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Control functions

Functions
NOR Control functions
NOR Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.

Detailed Description

management functions

  ==============================================================================
                        ##### NOR Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NOR interface.

Function Documentation

HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable ( NOR_HandleTypeDef * hnor )

Disables dynamically NOR write operation.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 891 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable ( NOR_HandleTypeDef * hnor )

Enables dynamically NOR write operation.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 868 of file stm32f7xx_hal_nor.c.

References HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR State functions

Functions
NOR State functions
NOR Exported Functions

Peripheral State functions. More...

Functions

HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### NOR State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NOR controller
    and the data flow.

Function Documentation

HAL_NOR_StateTypeDef HAL_NOR_GetState ( NOR_HandleTypeDef * hnor )

return the NOR controller state

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
NOR controller state

Definition at line 936 of file stm32f7xx_hal_nor.c.

References NOR_HandleTypeDef::State.

HAL_NOR_StatusTypeDef HAL_NOR_GetStatus | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address,
 |  | uint32_t | Timeout
 | ) |  |

Returns the NOR operation status.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address,: Device address
Timeout,: NOR programming Timeout
Return values:
NOR_Status,: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR or HAL_NOR_STATUS_TIMEOUT

Definition at line 950 of file stm32f7xx_hal_nor.c.

References HAL_GetTick(), HAL_NOR_MspWait(), HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_TIMEOUT, NOR_MASK_STATUS_DQ5, and NOR_MASK_STATUS_DQ6.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Exported Types

Data Structures | Enumerations
NOR Exported Types
NOR

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | NOR_HandleTypeDef
NOR handle Structure definition. More...

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00, HAL_NOR_STATE_READY = 0x01, HAL_NOR_STATE_BUSY = 0x02, HAL_NOR_STATE_ERROR = 0x03,
HAL_NOR_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...

Enumeration Type Documentation

enum HAL_NOR_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_NOR_STATE_RESET

NOR not yet initialized or disabled

HAL_NOR_STATE_READY

NOR initialized and ready for use

HAL_NOR_STATE_BUSY

NOR internal processing is ongoing

HAL_NOR_STATE_ERROR

NOR error state

HAL_NOR_STATE_PROTECTED

NOR NORSRAM device write protected

Definition at line 66 of file stm32f7xx_hal_nor.h.

enum HAL_NOR_StatusTypeDef

FMC NOR Status typedef.

Enumerator:
HAL_NOR_STATUS_SUCCESS
HAL_NOR_STATUS_ONGOING
HAL_NOR_STATUS_ERROR
HAL_NOR_STATUS_TIMEOUT

Definition at line 78 of file stm32f7xx_hal_nor.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_IDTypeDef Struct Reference
NOR Exported Types

FMC NOR ID typedef. More...

#include <stm32f7xx_hal_nor.h>

Data Fields

uint16_t | Manufacturer_Code
uint16_t | Device_Code1
uint16_t | Device_Code2
uint16_t | Device_Code3

Detailed Description

FMC NOR ID typedef.

Definition at line 89 of file stm32f7xx_hal_nor.h.

Field Documentation

uint16_t NOR_IDTypeDef::Device_Code1

Definition at line 93 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code2

Definition at line 95 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code3

Defines the device's codes used to identify the memory. These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing an Auto Select command

Definition at line 97 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Manufacturer_Code

Defines the device's manufacturer code used to identify the memory

Definition at line 91 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nor.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR_CFITypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_CFITypeDef Struct Reference
NOR Exported Types

FMC NOR CFI typedef. More...

#include <stm32f7xx_hal_nor.h>

Data Fields

uint16_t | CFI_1
uint16_t | CFI_2
uint16_t | CFI_3
uint16_t | CFI_4

Detailed Description

FMC NOR CFI typedef.

Definition at line 106 of file stm32f7xx_hal_nor.h.

Field Documentation

uint16_t NOR_CFITypeDef::CFI_1

< Defines the information stored in the memory's Common flash interface which contains a description of various electrical and timing parameters, density information and functions supported by the memory

Definition at line 112 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_2

Definition at line 114 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_3

Definition at line 116 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_4

Definition at line 118 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nor.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_HandleTypeDef Struct Reference
NOR Exported Types

NOR handle Structure definition. More...

#include <stm32f7xx_hal_nor.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NOR_StateTypeDef | State

Detailed Description

NOR handle Structure definition.

Definition at line 124 of file stm32f7xx_hal_nor.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* NOR_HandleTypeDef::Extended

Extended mode register base address

Definition at line 128 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), and HAL_NOR_Init().

FMC_NORSRAM_InitTypeDef NOR_HandleTypeDef::Init

NOR device control configuration parameters

Definition at line 130 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* NOR_HandleTypeDef::Instance

Register base address

Definition at line 126 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Init(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

HAL_LockTypeDef NOR_HandleTypeDef::Lock

NOR locking object

Definition at line 132 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Init().

__IO HAL_NOR_StateTypeDef NOR_HandleTypeDef::State

NOR device access state

Definition at line 134 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_GetState(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_nor.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Exported Macros

Defines
NOR Exported Macros
NOR

Defines

#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
Reset NOR handle state.

Define Documentation

#define __HAL_NOR_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)

Reset NOR handle state.

Parameters:
__HANDLE__,: specifies the NOR handle.
Return values:
None

Definition at line 150 of file stm32f7xx_hal_nor.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Private Constants

Defines
NOR Private Constants
NOR

Defines

#define | MC_ADDRESS ((uint16_t)0x0000)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000F)
#define | CFI1_ADDRESS ((uint16_t)0x61)
#define | CFI2_ADDRESS ((uint16_t)0x62)
#define | CFI3_ADDRESS ((uint16_t)0x63)
#define | CFI4_ADDRESS ((uint16_t)0x64)
#define | NOR_TMEOUT ((uint16_t)0xFFFF)
#define | NOR_MEMORY_8B ((uint8_t)0x0)
#define | NOR_MEMORY_16B ((uint8_t)0x1)
#define | NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
#define | NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
#define | NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
#define | NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)

Define Documentation

#define CFI1_ADDRESS ((uint16_t)0x61)

Definition at line 233 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI2_ADDRESS ((uint16_t)0x62)

Definition at line 234 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI3_ADDRESS ((uint16_t)0x63)

Definition at line 235 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI4_ADDRESS ((uint16_t)0x64)

Definition at line 236 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)

Definition at line 228 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)

Definition at line 229 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)

Definition at line 230 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define MC_ADDRESS ((uint16_t)0x0000)

Definition at line 227 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define NOR_MEMORY_16B ((uint8_t)0x1)

Definition at line 243 of file stm32f7xx_hal_nor.h.

#define NOR_MEMORY_8B ((uint8_t)0x0)

Definition at line 242 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)

Definition at line 246 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)

Definition at line 247 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)

Definition at line 248 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)

Definition at line 249 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_TMEOUT ((uint16_t)0xFFFF)

Definition at line 239 of file stm32f7xx_hal_nor.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Private Macros

Defines
NOR Private Macros
NOR

Defines

#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__)
NOR memory write data to specified address.

Define Documentation

#define NOR_ADDR_SHIFT | ( | __NOR_ADDRESS,
 |  | __NOR_MEMORY_WIDTH_,
 |  | __ADDRESS__
 | ) |
Value:
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)?              \
              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

NOR memory address shifting.

Parameters:
__NOR_ADDRESS,: NOR base address
__NOR_MEMORY_WIDTH_,: NOR memory width
__ADDRESS__,: NOR memory address
Return values:
NOR shifted address value

Definition at line 265 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_WRITE | ( | __ADDRESS__,
 |  | __DATA__
 | ) |
Value:
do{                                                             \
                                                 (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
                                                 __DSB();                                                    \
                                               } while(0)

NOR memory write data to specified address.

Parameters:
__ADDRESS__,: NOR memory address
__DATA__,: Data to write
Return values:
None

Definition at line 276 of file stm32f7xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

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STM32F745xx HAL User Manual: PCD Instance definition

Defines
PCD Instance definition
PCD Private Macros

Defines

#define IS_PCD_ALL_INSTANCE(INSTANCE)

Define Documentation

#define IS_PCD_ALL_INSTANCE ( INSTANCE )
Value:
(((INSTANCE) == USB_OTG_FS) || \
                                       ((INSTANCE) == USB_OTG_HS))

Definition at line 308 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

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STM32F745xx HAL User Manual: PCD Private Macros

Modules | Defines
PCD Private Macros
PCD

Modules

PCD Instance definition

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Define Documentation

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 97 of file stm32f7xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 96 of file stm32f7xx_hal_pcd.c.

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STM32F745xx HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
Check FIFO for the next packet to be loaded.

Function Documentation

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint32_t | epnum
 | ) |  | [static]

Check FIFO for the next packet to be loaded.

Parameters:
hpcd,: PCD handle
epnum : endpoint number
Return values:
HAL status

Definition at line 1182 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 210 of file stm32f7xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), and PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 135 of file stm32f7xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, HAL_PCD_MspInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCDEx_ActivateLPM(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, IS_PCD_ALL_INSTANCE, PCD_HandleTypeDef::OUT_ep, and PCD_HandleTypeDef::State.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 251 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 236 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_Init().

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STM32F745xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handle PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 767 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 646 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data OUT stage callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 630 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 782 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

Handle PCD interrupt request.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 314 of file stm32f7xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, __HAL_PCD_IS_INVALID_INTERRUPT, PCD_HandleTypeDef::BESL, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, LPM_L0, LPM_L1, PCD_HandleTypeDef::LPM_State, PCD_HandleTypeDef::OUT_ep, PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, PCD_WriteEmptyTxFifo(), PCD_HandleTypeDef::Setup, USBD_FS_TRDT_VALUE, and USBD_HS_TRDT_VALUE.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 752 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 736 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 690 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 720 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 660 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 675 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start The USB OTG Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 285 of file stm32f7xx_hal_pcd.c.

References __HAL_PCD_ENABLE, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop The USB OTG Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 299 of file stm32f7xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 705 of file stm32f7xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

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STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

Activate remote wakeup signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1110 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

De-activate remote wakeup signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1127 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 816 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 829 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 900 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1057 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1087 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

uint16_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
Data Size

Definition at line 970 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
ep_mps,: endpoint max packet size
ep_type,: endpoint type
Return values:
HAL status

Definition at line 858 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the reception buffer
len,: amount of data to be received
Return values:
HAL status

Definition at line 931 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1022 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::OUT_ep, and PCD_HandleTypeDef::Setup.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the transmission buffer
len,: amount of data to be sent
Return values:
HAL status

Definition at line 982 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd,: PCD handle
address,: new device address
Return values:
HAL status

Definition at line 843 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD handle state.

Parameters:
hpcd,: PCD handle
Return values:
HAL state

Definition at line 1159 of file stm32f7xx_hal_pcd.c.

References PCD_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }

Typedef Documentation

typedef USB_OTG_EPTypeDef PCD_EPTypeDef

Definition at line 85 of file stm32f7xx_hal_pcd.h.

typedef USB_OTG_CfgTypeDef PCD_InitTypeDef

Definition at line 84 of file stm32f7xx_hal_pcd.h.

typedef USB_OTG_GlobalTypeDef PCD_TypeDef

Definition at line 83 of file stm32f7xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 75 of file stm32f7xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 65 of file stm32f7xx_hal_pcd.h.

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STM32F745xx HAL User Manual: PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32f7xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
PCD_EPTypeDef | IN_ep [15]
PCD_EPTypeDef | OUT_ep [15]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
void * | pData

Detailed Description

PCD Handle Structure definition.

Definition at line 90 of file stm32f7xx_hal_pcd.h.

Field Documentation

uint32_t PCD_HandleTypeDef::BESL

Definition at line 100 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

PCD_EPTypeDef PCD_HandleTypeDef::IN_ep[15]

IN endpoint parameters

Definition at line 94 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_InitTypeDef PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 93 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_TypeDef* PCD_HandleTypeDef::Instance

Register base address

Definition at line 92 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Flush(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_DeActivateLPM(), HAL_PCDEx_SetRxFiFo(), HAL_PCDEx_SetTxFiFo(), and PCD_WriteEmptyTxFifo().

HAL_LockTypeDef PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 96 of file stm32f7xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 101 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 99 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

PCD_EPTypeDef PCD_HandleTypeDef::OUT_ep[15]

OUT endpoint parameters

Definition at line 95 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), and HAL_PCD_IRQHandler().

void* PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 103 of file stm32f7xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 98 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall(), and HAL_PCD_IRQHandler().

__IO PCD_StateTypeDef PCD_HandleTypeDef::State

PCD communication state

Definition at line 97 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), and HAL_PCD_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_pcd.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define | PCD_SPEED_HIGH 0
#define | PCD_SPEED_HIGH_IN_FULL 1
#define | PCD_SPEED_FULL 2

Define Documentation

#define PCD_SPEED_FULL 2

Definition at line 123 of file stm32f7xx_hal_pcd.h.

#define PCD_SPEED_HIGH 0

Definition at line 121 of file stm32f7xx_hal_pcd.h.

#define PCD_SPEED_HIGH_IN_FULL 1

Definition at line 122 of file stm32f7xx_hal_pcd.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define | PCD_PHY_ULPI 1
#define | PCD_PHY_EMBEDDED 2

Define Documentation

#define PCD_PHY_EMBEDDED 2

Definition at line 132 of file stm32f7xx_hal_pcd.h.

#define PCD_PHY_ULPI 1

Definition at line 131 of file stm32f7xx_hal_pcd.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Turnaround Timeout Value

Defines
Turnaround Timeout Value
PCD Exported Constants

Defines

#define | USBD_HS_TRDT_VALUE 9
#define | USBD_FS_TRDT_VALUE 5

Define Documentation

#define USBD_FS_TRDT_VALUE 5

Definition at line 144 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define USBD_HS_TRDT_VALUE 9

Definition at line 141 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000)
#define | USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

Definition at line 164 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 161 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 160 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GATE_PHYCLOCK ( __HANDLE__ ) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK

Definition at line 171 of file stm32f7xx_hal_pcd.h.

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 163 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)

Definition at line 165 of file stm32f7xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_PHY_SUSPENDED ( __HANDLE__ ) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)

Definition at line 173 of file stm32f7xx_hal_pcd.h.

#define __HAL_PCD_UNGATE_PHYCLOCK ( __HANDLE__ )
Value:
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
                                                       ~(USB_OTG_PCGCCTL_STOPCLK)

Definition at line 168 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 207 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 205 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 213 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 204 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                          EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 209 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                   EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                   EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
                                                                   EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 216 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 221 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG ( ) EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 206 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 189 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 187 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
                                                            EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 194 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 186 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
                                                          EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE

Definition at line 191 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
                                                                    EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
                                                                    EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
                                                                    EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE

Definition at line 197 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 202 of file stm32f7xx_hal_pcd.h.

#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG ( ) EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)

Definition at line 188 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)

Definition at line 176 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000)

External interrupt line 18 Connected to the USB FS EXTI Line

Definition at line 184 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)

Definition at line 175 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)

Definition at line 177 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)

Definition at line 180 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000)

External interrupt line 20 Connected to the USB HS EXTI Line

Definition at line 183 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)

Definition at line 179 of file stm32f7xx_hal_pcd.h.

#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)

Definition at line 181 of file stm32f7xx_hal_pcd.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Extended Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM Feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
DeActivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

Activate LPM Feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 141 of file stm32f7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::lpm_active, LPM_L0, and PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

DeActivate LPM feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 158 of file stm32f7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd,: PCD handle
msg,: LPM message
Return values:
HAL status

Definition at line 175 of file stm32f7xx_hal_pcd_ex.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | size
 | ) |  |

Set Rx FIFO.

Parameters:
hpcd,: PCD handle
size,: Size of Rx fifo
Return values:
HAL status

Definition at line 129 of file stm32f7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | fifo,
 |  | uint16_t | size
 | ) |  |

Set Tx FIFO.

Parameters:
hpcd,: PCD handle
fifo,: The number of Tx fifo
size,: Fifo size
Return values:
HAL status

Definition at line 87 of file stm32f7xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCDEx

Modules | Enumerations
PCDEx
STM32F7xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCD Extended Exported Functions

Enumerations

enum PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }

Detailed Description

PCD Extended HAL module driver.

Enumeration Type Documentation

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 57 of file stm32f7xx_hal_pcd_ex.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data
      registers and backup SRAM) is protected against possible unwanted
      write accesses.
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitializes the HAL PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 118 of file stm32f7xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

void HAL_PWR_DisableBkUpAccess ( void )

Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 144 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_EnableBkUpAccess ( void )

Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 131 of file stm32f7xx_hal_pwr.c.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** Wake-up pin configuration ***
    ================================
    [..]
      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
          forced in input pull-down configuration and is active on rising edges.
      (+) There are to 6 Wake-up pin in the STM32F7 devices family

    *** Low Power modes configuration ***
    =====================================
    [..]
      The devices feature 3 low-power modes:
      (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
      (+) Stop mode: all clocks are stopped, regulator running, regulator
          in low power mode
      (+) Standby mode: 1.2V domain powered off.

   *** Sleep mode ***
   ==================
    [..]
      (+) Entry:
        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
              functions with
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      -@@- The Regulator parameter is not used for the STM32F7 family
              and is kept as parameter just to maintain compatibility with the
              lower power families (STM32L).
      (+) Exit:
        Any peripheral interrupt acknowledged by the nested vectored interrupt
              controller (NVIC) can wake up the device from Sleep mode.

   *** Stop mode ***
   =================
    [..]
      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
      and the HSE RC oscillators are disabled. Internal SRAM and register contents
      are preserved.
      The voltage regulator can be configured either in normal or low-power mode.
      To minimize the consumption In Stop mode, FLASH can be powered off before
      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
      It can be switched on again by software after exiting the Stop mode using
      the HAL_PWREx_DisableFlashPowerDown() function.

      (+) Entry:
         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
             function with:
          (++) Main regulator ON.
          (++) Low Power regulator ON.
      (+) Exit:
        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** Standby mode ***
   ====================
    [..]
    (+)
      The Standby mode allows to achieve the lowest power consumption. It is based
      on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
      the HSE oscillator are also switched off. SRAM and register contents are lost
      except for the RTC registers, RTC backup registers, backup SRAM and Standby
      circuitry.

      The voltage regulator is OFF.

      (++) Entry:
        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
      (++) Exit:
        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
             wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]

     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event or a time-stamp event, without depending on
      an external interrupt (Auto-wakeup mode).

      (+) RTC auto-wakeup (AWU) from the Stop and Standby modes

        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
             is necessary to configure the RTC to detect the tamper or time stamp event using the
                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.

        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

void HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
sConfigPVD,: pointer to an PWR_PVDTypeDef structure that contains the configuration information for the PVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
Return values:
None

Definition at line 278 of file stm32f7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 331 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disables CORTEX M4 SEVONPEND bit.

Note:
Clears SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 590 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 566 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disables the WakeUp PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1
  • PWR_WAKEUP_PIN2
  • PWR_WAKEUP_PIN3
  • PWR_WAKEUP_PIN4
  • PWR_WAKEUP_PIN5
  • PWR_WAKEUP_PIN6
Return values:
None

Definition at line 378 of file stm32f7xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 321 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enables CORTEX M4 SEVONPEND bit.

Note:
Sets SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 578 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 554 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity,: Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values, which sets the default polarity: detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following value where the user can explicitly states the enabled pin and the chosen polarity
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
  • PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None

Definition at line 354 of file stm32f7xx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_EWUP_MASK.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enters Sleep mode.

Note:
In Sleep mode, all I/O pins keep the same state as in Run mode.
In Sleep mode, the systick is stopped to avoid exit from this mode with systick interrupt when used as time base for Timeout
Parameters:
Regulator,: Specifies the regulator state in SLEEP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
Note:
This parameter is not used for the STM32F7 family and is kept as parameter just to maintain compatibility with the lower power families.
Parameters:
SLEEPEntry,: Specifies if SLEEP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 405 of file stm32f7xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enters Standby mode.

Note:
In Standby mode, all I/O pins are high impedance except for:
  • Reset pad (still available)
  • RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC Alarm out, or RTC clock calibration out.
  • RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
  • WKUP pins if enabled.
Return values:
None

Definition at line 497 of file stm32f7xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enters Stop mode.

Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
STOPEntry,: Specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
Return values:
None

Definition at line 448 of file stm32f7xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_IRQHandler().
Return values:
None

Definition at line 518 of file stm32f7xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, and HAL_PWR_PVDCallback().

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 535 of file stm32f7xx_hal_pwr.c.

Referenced by HAL_PWR_PVD_IRQHandler().

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STM32F745xx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32f7xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 66 of file stm32f7xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD Mode

Definition at line 71 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of PWR PVD detection level

Definition at line 68 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_pwr.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR PVD detection level

Defines
PWR PVD detection level
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | PWR_PVDLEVEL_7

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0

Definition at line 87 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1

Definition at line 88 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2

Definition at line 89 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3

Definition at line 90 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4

Definition at line 91 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5

Definition at line 92 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6

Definition at line 93 of file stm32f7xx_hal_pwr.h.

#define PWR_PVDLEVEL_7
Value:
PWR_CR1_PLS_LEV7/* External input analog voltage
                                                          (Compare internally to VREFINT) */

Definition at line 94 of file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR PVD Mode

Defines
PWR PVD Mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)

Event Mode with Falling edge trigger detection

Definition at line 108 of file stm32f7xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)

Event Mode with Rising edge trigger detection

Definition at line 107 of file stm32f7xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Event Mode with Rising/Falling edge trigger detection

Definition at line 109 of file stm32f7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)

External Interrupt Mode with Falling edge trigger detection

Definition at line 105 of file stm32f7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)

External Interrupt Mode with Rising edge trigger detection

Definition at line 104 of file stm32f7xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 106 of file stm32f7xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)

basic mode is used

Definition at line 103 of file stm32f7xx_hal_pwr.h.

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STM32F745xx HAL User Manual: PWR Regulator state in SLEEP/STOP mode

Defines
PWR Regulator state in SLEEP/STOP mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS

Definition at line 118 of file stm32f7xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)

Definition at line 117 of file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Definition at line 127 of file stm32f7xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)

Definition at line 126 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWREx_EnterUnderDriveSTOPMode().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02)

Definition at line 136 of file stm32f7xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01)

Definition at line 135 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR Regulator Voltage Scale

Defines
PWR Regulator Voltage Scale
PWR Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS

Definition at line 144 of file stm32f7xx_hal_pwr.h.

#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Definition at line 145 of file stm32f7xx_hal_pwr.h.

#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0

Definition at line 146 of file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR Flag

Defines
PWR Flag
PWR Exported Constants

Defines

#define | PWR_FLAG_WU PWR_CSR1_WUIF
#define | PWR_FLAG_SB PWR_CSR1_SBF
#define | PWR_FLAG_PVDO PWR_CSR1_PVDO
#define | PWR_FLAG_BRR PWR_CSR1_BRR
#define | PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY

Define Documentation

#define PWR_FLAG_BRR PWR_CSR1_BRR

Definition at line 157 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define PWR_FLAG_PVDO PWR_CSR1_PVDO

Definition at line 156 of file stm32f7xx_hal_pwr.h.

#define PWR_FLAG_SB PWR_CSR1_SBF

Definition at line 155 of file stm32f7xx_hal_pwr.h.

#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY

Definition at line 158 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define PWR_FLAG_WU PWR_CSR1_WUIF

Definition at line 154 of file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR Exported Macro

Defines
PWR Exported Macro
PWR

Defines

#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
macros configure the main internal regulator output voltage.
#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)
Clear the PWR's pending flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Enable the PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
checks whether the specified PVD Exti interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD Exti flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Generates a Software interrupt on PVD EXTI line.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) (PWR->CR1 |= (__FLAG__) << 2)

Clear the PWR's pending flags.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_SB: StandBy flag

Definition at line 216 of file stm32f7xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ ) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))

Check PWR flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
  • PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.
  • PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage scaling output selection is ready.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 209 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_DisableOverDrive(), HAL_PWREx_EnableBkUpReg(), HAL_PWREx_EnableOverDrive(), and HAL_PWREx_EnterUnderDriveSTOPMode().

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) (EXTI->PR = (PWR_EXTI_LINE_PVD))

Clear the PVD Exti flag.

Return values:
None.

Definition at line 290 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))

Disable event on PVD Exti Line 16.

Return values:
None.

Definition at line 240 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 265 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))

Disable the PVD EXTI Line 16.

Return values:
None.

Definition at line 228 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 252 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 278 of file stm32f7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= (PWR_EXTI_LINE_PVD))

Enable event on PVD Exti Line 16.

Return values:
None.

Definition at line 234 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 258 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) (EXTI->IMR |= (PWR_EXTI_LINE_PVD))

Enable the PVD Exti Line 16.

Return values:
None.

Definition at line 222 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 246 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();

PVD EXTI line configuration: set rising & falling edge trigger.

Return values:
None.

Definition at line 272 of file stm32f7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))

Generates a Software interrupt on PVD EXTI line.

Return values:
None

Definition at line 296 of file stm32f7xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) (EXTI->PR & (PWR_EXTI_LINE_PVD))

checks whether the specified PVD Exti interrupt flag is set or not.

Return values:
EXTI PVD Line Status.

Definition at line 284 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler().

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do {                                                     \
                                                          __IO uint32_t tmpreg = 0x00;                               \
                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
                                                            /* Delay after an RCC peripheral clock enabling */  \
                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
                                                            UNUSED(tmpreg);                                     \
                                                                                } while(0)

macros configure the main internal regulator output voltage.

Parameters:
__REGULATOR__,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheets for more details). This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
  • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
  • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
Return values:
None

Definition at line 182 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Constants

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000)
#define | PVD_MODE_EVT ((uint32_t)0x00020000)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002)

Define Documentation

#define PVD_FALLING_EDGE ((uint32_t)0x00000002)

Definition at line 69 of file stm32f7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT ((uint32_t)0x00020000)

Definition at line 67 of file stm32f7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT ((uint32_t)0x00010000)

Definition at line 66 of file stm32f7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE ((uint32_t)0x00000001)

Definition at line 68 of file stm32f7xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR Enable WUP Mask

Defines
PWR Enable WUP Mask
PWR Private Constants

Defines

#define PWR_EWUP_MASK ((uint32_t)0x00003F00)

Define Documentation

#define PWR_EWUP_MASK ((uint32_t)0x00003F00)

Definition at line 77 of file stm32f7xx_hal_pwr.c.

Referenced by HAL_PWR_EnableWakeUpPin().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR PVD EXTI Line

Defines
PWR PVD EXTI Line
PWR Private Constants

Defines

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)

Define Documentation

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 367 of file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR Private macros to check input parameters

Defines
PWR Private macros to check input parameters
PWR Private Macros

Defines

#define | IS_PWR_WAKEUP_POLARITY(POLARITY)
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define | IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 385 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_NORMAL))

Definition at line 389 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 393 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

#define IS_PWR_REGULATOR_VOLTAGE ( VOLTAGE )
Value:
(((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))

Definition at line 397 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 395 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 396 of file stm32f7xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode(), and HAL_PWREx_EnterUnderDriveSTOPMode().

#define IS_PWR_WAKEUP_POLARITY ( POLARITY )
Value:
(((POLARITY) == PWR_POLARITY_RISINGEDGE)  || \
                                                    ((POLARITY) == PWR_POLARITY_FALLINGEDGE))

Definition at line 383 of file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Extended features functions

Functions
Peripheral Extended features functions
PWREx Exported Functions

Peripheral Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enables the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disables the Backup Regulator.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enables the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disables the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableMainRegulatorLowVoltage (void)
Enables Main Regulator low voltage mode.
void | HAL_PWREx_DisableMainRegulatorLowVoltage (void)
Disables Main Regulator low voltage mode.
void | HAL_PWREx_EnableLowRegulatorLowVoltage (void)
Enables Low Power Regulator low voltage mode.
void | HAL_PWREx_DisableLowRegulatorLowVoltage (void)
Disables Low Power Regulator low voltage mode.
HAL_StatusTypeDef | HAL_PWREx_EnableOverDrive (void)
Activates the Over-Drive mode.
HAL_StatusTypeDef | HAL_PWREx_DisableOverDrive (void)
Deactivates the Over-Drive mode.
HAL_StatusTypeDef | HAL_PWREx_EnterUnderDriveSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters in Under-Drive STOP mode.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Returns Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configures the main internal regulator output voltage.

Detailed Description

Peripheral Extended features functions.

 ===============================================================================
                 ##### Peripheral extended features functions #####
 ===============================================================================

    *** Main and Backup Regulators configuration ***
    ================================================
    [..]
      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
          retained even in Standby or VBAT mode when the low power backup regulator
          is enabled. It can be considered as an internal EEPROM when VBAT is
          always present. You can use the HAL_PWREx_EnableBkUpReg() function to
          enable the low power backup regulator.

      (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
          the backup SRAM is powered from VDD which replaces the VBAT power supply to
          save battery life.

      (+) The backup SRAM is not mass erased by a tamper event. It is read
          protected to prevent confidential data, such as cryptographic private
          key, from being accessed. The backup SRAM can be erased only through
          the Flash interface when a protection level change from level 1 to
          level 0 is requested.
      -@- Refer to the description of Read protection (RDP) in the Flash
          programming manual.

      (+) The main internal regulator can be configured to have a tradeoff between
          performance and power consumption when the device does not operate at
          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
          macro which configure VOS bit in PWR_CR register

        Refer to the product datasheets for more details.

    *** FLASH Power Down configuration ****
    =======================================
    [..]
      (+) By setting the FPDS bit in the PWR_CR register by using the
          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
          down mode when the device enters Stop mode. When the Flash memory
          is in power down mode, an additional startup delay is incurred when
          waking up from Stop mode.

    *** Over-Drive and Under-Drive configuration ****
    =================================================
    [..]
       (+) In Run mode: the main regulator has 2 operating modes available:
        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
             voltage scaling (scale 1, scale 2 or scale 3)
        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
            higher frequency than the normal mode for a given voltage scaling (scale 1,
            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
            the sequence described in Reference manual.

       (+) In Stop mode: the main regulator or low power regulator supplies a low power
           voltage to the 1.2V domain, thus preserving the content of registers
           and internal SRAM. 2 operating modes are available:
         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
              available when the main regulator or the low power regulator is used in Scale 3 or
              low voltage mode.
         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
              available when the main regulator or the low power regulator is in low voltage mode.

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configures the main internal regulator output voltage.

Parameters:
VoltageScaling,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, typical output voltage at 1.4 V, system frequency up to 216 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, typical output voltage at 1.2 V, system frequency up to 180 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, typical output voltage at 1.00 V, system frequency up to 151 MHz.
Note:
To update the system clock frequency(SYSCLK):
  • Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
  • Call the HAL_RCC_OscConfig() to configure the PLL.
  • Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
  • Set the new system clock frequency using the HAL_RCC_ClockConfig().
The scale can be modified only when the HSI or HSE clock source is selected as system clock source, otherwise the API returns HAL_ERROR.
When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits value in the PWR_CR1 register are not taken in account.
This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
The new voltage scale is active only when the PLL is ON.
Return values:
HAL Status

Definition at line 487 of file stm32f7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, __HAL_PWR_VOLTAGESCALING_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), IS_PWR_REGULATOR_VOLTAGE, PLL_TIMEOUT_VALUE, PWR_FLAG_VOSRDY, PWR_VOSRDY_TIMEOUT_VALUE, and RCC_FLAG_PLLRDY.

HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg ( void )

Disables the Backup Regulator.

Return values:
HAL status

Definition at line 178 of file stm32f7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_BKPREG_TIMEOUT_VALUE, and PWR_FLAG_BRR.

void HAL_PWREx_DisableFlashPowerDown ( void )

Disables the Flash Power Down in Stop mode.

Return values:
None

Definition at line 213 of file stm32f7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableLowRegulatorLowVoltage ( void )

Disables Low Power Regulator low voltage mode.

Return values:
None

Definition at line 253 of file stm32f7xx_hal_pwr_ex.c.

void HAL_PWREx_DisableMainRegulatorLowVoltage ( void )

Disables Main Regulator low voltage mode.

Return values:
None

Definition at line 233 of file stm32f7xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableOverDrive ( void )

Deactivates the Over-Drive mode.

Note:
This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
It is recommended to enter or exit Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.
Return values:
HAL status

Definition at line 315 of file stm32f7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, __HAL_PWR_OVERDRIVE_DISABLE, __HAL_PWR_OVERDRIVESWITCHING_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, HAL_GetTick(), PWR_FLAG_ODRDY, PWR_FLAG_ODSWRDY, and PWR_OVERDRIVE_TIMEOUT_VALUE.

HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg ( void )

Enables the Backup Regulator.

Return values:
HAL status

Definition at line 153 of file stm32f7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, HAL_GetTick(), PWR_BKPREG_TIMEOUT_VALUE, and PWR_FLAG_BRR.

void HAL_PWREx_EnableFlashPowerDown ( void )

Enables the Flash Power Down in Stop mode.

Return values:
None

Definition at line 203 of file stm32f7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableLowRegulatorLowVoltage ( void )

Enables Low Power Regulator low voltage mode.

Return values:
None

Definition at line 243 of file stm32f7xx_hal_pwr_ex.c.

void HAL_PWREx_EnableMainRegulatorLowVoltage ( void )

Enables Main Regulator low voltage mode.

Return values:
None

Definition at line 223 of file stm32f7xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_EnableOverDrive ( void )

Activates the Over-Drive mode.

Note:
This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
It is recommended to enter or exit Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.
Return values:
HAL status

Definition at line 269 of file stm32f7xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, __HAL_PWR_OVERDRIVE_ENABLE, __HAL_PWR_OVERDRIVESWITCHING_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, HAL_GetTick(), PWR_FLAG_ODRDY, PWR_FLAG_ODSWRDY, and PWR_OVERDRIVE_TIMEOUT_VALUE.

HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enters in Under-Drive STOP mode.

Note:
This mode can be selected only when the Under-Drive is already active
This mode is enabled only with STOP low power mode. In this mode, the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode
If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode. When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: specifies the regulator state in STOP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode
  • PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode
STOPEntry,: specifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
  • PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
Return values:
None

Definition at line 389 of file stm32f7xx_hal_pwr_ex.c.

References __HAL_PWR_CLEAR_ODRUDR_FLAG, __HAL_PWR_GET_FLAG, __HAL_PWR_UNDERDRIVE_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), IS_PWR_REGULATOR_UNDERDRIVE, IS_PWR_STOP_ENTRY, PWR_FLAG_UDRDY, PWR_SLEEPENTRY_WFI, and PWR_UDERDRIVE_TIMEOUT_VALUE.

uint32_t HAL_PWREx_GetVoltageRange ( void )

Returns Voltage Scaling Range.

Return values:
VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1

Definition at line 455 of file stm32f7xx_hal_pwr_ex.c.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx Wake Up Pins

Defines
PWREx Wake Up Pins
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5
#define | PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6
#define | PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5
#define | PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
#define | PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1

Definition at line 65 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1

Definition at line 71 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)

Definition at line 77 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2

Definition at line 66 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2

Definition at line 72 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)

Definition at line 78 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3

Definition at line 67 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3

Definition at line 73 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)

Definition at line 79 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4

Definition at line 68 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4

Definition at line 74 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)

Definition at line 80 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5

Definition at line 69 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5

Definition at line 75 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)

Definition at line 81 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6

Definition at line 70 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6

Definition at line 76 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)

Definition at line 82 of file stm32f7xx_hal_pwr_ex.h.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx Regulator state in UnderDrive mode

Defines
PWREx Regulator state in UnderDrive mode
PWREx Exported Constants

Defines

#define | PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS
#define | PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))

Define Documentation

#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))

Definition at line 92 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS

Definition at line 91 of file stm32f7xx_hal_pwr_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx Over Under Drive Flag

Defines
PWREx Over Under Drive Flag
PWREx Exported Constants

Defines

#define | PWR_FLAG_ODRDY PWR_CSR1_ODRDY
#define | PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
#define | PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY

Define Documentation

#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY

Definition at line 100 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableOverDrive(), and HAL_PWREx_EnableOverDrive().

#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY

Definition at line 101 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableOverDrive(), and HAL_PWREx_EnableOverDrive().

#define PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY

Definition at line 102 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterUnderDriveSTOPMode().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx Wake Up Pin Flags

Defines
PWREx Wake Up Pin Flags
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1
#define | PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2
#define | PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3
#define | PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4
#define | PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5
#define | PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6

Define Documentation

#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1

Definition at line 110 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2

Definition at line 111 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3

Definition at line 112 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4

Definition at line 113 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5

Definition at line 114 of file stm32f7xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6

Definition at line 115 of file stm32f7xx_hal_pwr_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx Exported Macro

Defines
PWREx Exported Macro
PWREx

Defines

#define | __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
Macros to enable or disable the Over drive mode.
#define | __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
#define | __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
Macros to enable or disable the Over drive switching.
#define | __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
#define | __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
Macros to enable or disable the Under drive mode.
#define | __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
#define | __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
Clear the Under-Drive Ready flag.
#define | __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
Check Wake Up flag is set or not.
#define | __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))
Clear the WakeUp pins flags.

Define Documentation

#define __HAL_PWR_CLEAR_ODRUDR_FLAG ( ) (PWR->CSR1 |= PWR_FLAG_UDRDY)

Clear the Under-Drive Ready flag.

Definition at line 166 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterUnderDriveSTOPMode().

#define __HAL_PWR_CLEAR_WAKEUP_FLAG ( __WUFLAG__ ) (PWR->CR2 |= (__WUFLAG__))

Clear the WakeUp pins flags.

Parameters:
__WUFLAG__,: specifies the Wake Up pin flag to clear. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
  • PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
  • PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
  • PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
  • PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
  • PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11

Definition at line 190 of file stm32f7xx_hal_pwr_ex.h.

#define __HAL_PWR_GET_ODRUDR_FLAG ( __FLAG__ ) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))

Check PWR flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode is ready
  • PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode switching is ready
  • PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode is enabled in Stop mode
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 162 of file stm32f7xx_hal_pwr_ex.h.

#define __HAL_PWR_GET_WAKEUP_FLAG ( __WUFLAG__ ) (PWR->CSR2 & (__WUFLAG__))

Check Wake Up flag is set or not.

Parameters:
__WUFLAG__,: specifies the Wake Up flag to check. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
  • PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
  • PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
  • PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
  • PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
  • PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11

Definition at line 178 of file stm32f7xx_hal_pwr_ex.h.

#define __HAL_PWR_OVERDRIVE_DISABLE ( ) (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))

Definition at line 131 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableOverDrive().

#define __HAL_PWR_OVERDRIVE_ENABLE ( ) (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)

Macros to enable or disable the Over drive mode.

Definition at line 130 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableOverDrive().

#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE ( ) (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))

Definition at line 136 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableOverDrive().

#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE ( ) (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)

Macros to enable or disable the Over drive switching.

Definition at line 135 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableOverDrive().

#define __HAL_PWR_UNDERDRIVE_DISABLE ( ) (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))

Definition at line 149 of file stm32f7xx_hal_pwr_ex.h.

#define __HAL_PWR_UNDERDRIVE_ENABLE ( ) (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)

Macros to enable or disable the Under drive mode.

Note:
This mode is enabled only with STOP low power mode. In this mode, the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode.
If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode. When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.

Definition at line 148 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterUnderDriveSTOPMode().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx Private macros to check input parameters

Defines
PWREx Private macros to check input parameters
PWREx Private Macros

Defines

#define | IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR)
#define | IS_PWR_WAKEUP_PIN(__PIN__)

Define Documentation

#define IS_PWR_REGULATOR_UNDERDRIVE ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))

Definition at line 237 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnterUnderDriveSTOPMode().

#define IS_PWR_WAKEUP_PIN ( __PIN__ )
Value:
(((__PIN__) == PWR_WAKEUP_PIN1)       || \
                                            ((__PIN__) == PWR_WAKEUP_PIN2)       || \
                                            ((__PIN__) == PWR_WAKEUP_PIN3)       || \
                                            ((__PIN__) == PWR_WAKEUP_PIN4)       || \
                                            ((__PIN__) == PWR_WAKEUP_PIN5)       || \
                                            ((__PIN__) == PWR_WAKEUP_PIN6)               || \
                                            ((__PIN__) == PWR_WAKEUP_PIN1_HIGH)  || \
                                            ((__PIN__) == PWR_WAKEUP_PIN2_HIGH)  || \
                                            ((__PIN__) == PWR_WAKEUP_PIN3_HIGH)  || \
                                            ((__PIN__) == PWR_WAKEUP_PIN4_HIGH)  || \
                                            ((__PIN__) == PWR_WAKEUP_PIN5_HIGH)  || \
                                            ((__PIN__) == PWR_WAKEUP_PIN6_HIGH)  || \
                                            ((__PIN__) == PWR_WAKEUP_PIN1_LOW)   || \
                                            ((__PIN__) == PWR_WAKEUP_PIN2_LOW)   || \
                                            ((__PIN__) == PWR_WAKEUP_PIN3_LOW)   || \
                                            ((__PIN__) == PWR_WAKEUP_PIN4_LOW)   || \
                                            ((__PIN__) == PWR_WAKEUP_PIN5_LOW)   || \
                                            ((__PIN__) == PWR_WAKEUP_PIN6_LOW))

Definition at line 239 of file stm32f7xx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWREx_Private_Constants

Defines
PWREx_Private_Constants
PWREx

Defines

#define | PWR_OVERDRIVE_TIMEOUT_VALUE 1000
#define | PWR_UDERDRIVE_TIMEOUT_VALUE 1000
#define | PWR_BKPREG_TIMEOUT_VALUE 1000
#define | PWR_VOSRDY_TIMEOUT_VALUE 1000

Define Documentation

#define PWR_BKPREG_TIMEOUT_VALUE 1000

Definition at line 63 of file stm32f7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000

Definition at line 61 of file stm32f7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableOverDrive(), and HAL_PWREx_EnableOverDrive().

#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000

Definition at line 62 of file stm32f7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_EnterUnderDriveSTOPMode().

#define PWR_VOSRDY_TIMEOUT_VALUE 1000

Definition at line 64 of file stm32f7xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ControlVoltageScaling().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
QSPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initializes the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
DeInitializes the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
QSPI MSP Init.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
QSPI MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Initialize the QuadSPI.
      (+) De-initialize the QuadSPI.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_DeInit ( QSPI_HandleTypeDef * hqspi )

DeInitializes the QSPI peripheral.

Parameters:
hqspi,: qspi handle
Return values:
HAL status

Definition at line 316 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_DISABLE, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspDeInit(), HAL_QSPI_STATE_RESET, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Init ( QSPI_HandleTypeDef * hqspi )

Initializes the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and creates the associated handle.

Parameters:
hqspi,: qspi handle
Return values:
HAL status

Definition at line 238 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE, assert_param, QSPI_InitTypeDef::ChipSelectHighTime, QSPI_InitTypeDef::ClockMode, QSPI_InitTypeDef::ClockPrescaler, QSPI_InitTypeDef::DualFlash, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, QSPI_InitTypeDef::FlashID, QSPI_InitTypeDef::FlashSize, HAL_QPSI_TIMEOUT_DEFAULT_VALUE, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspInit(), HAL_QSPI_SetTimeout(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, IS_QSPI_CLOCK_MODE, IS_QSPI_CLOCK_PRESCALER, IS_QSPI_CS_HIGH_TIME, IS_QSPI_DUAL_FLASH_MODE, IS_QSPI_FIFO_THRESHOLD, IS_QSPI_FLASH_ID, IS_QSPI_FLASH_SIZE, IS_QSPI_SSHIFT, QSPI_HandleTypeDef::Lock, QSPI_DUALFLASH_ENABLE, QSPI_FLAG_BUSY, QSPI_WaitFlagStateUntilTimeout(), QSPI_InitTypeDef::SampleShifting, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_MspDeInit ( QSPI_HandleTypeDef * hqspi )

QSPI MSP DeInit.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 365 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_DeInit().

void HAL_QSPI_MspInit ( QSPI_HandleTypeDef * hqspi )

QSPI MSP Init.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 350 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_Init().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
QSPI Exported Functions

QSPI Transmit/Receive functions. More...

Functions

void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
This function handles QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Sets the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Sets the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Sends an amount of data in non blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receives an amount of data in non blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callbacks.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callbacks.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callbacks.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callbacks.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callbacks.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callbacks.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callbacks.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callbacks.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callbacks.

Detailed Description

QSPI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
       [..]
    This subsection provides a set of functions allowing to :
      (+) Handle the interrupts.
      (+) Handle the command sequence.
      (+) Transmit data in blocking, interrupt or DMA mode.
      (+) Receive data in blocking, interrupt or DMA mode.
      (+) Manage the auto-polling functional mode.
      (+) Manage the memory-mapped functional mode.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_AutoPolling | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the QSPI Automatic Polling Mode in blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Timeout : Time out duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1169 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_AUTOMATIC_STOP_ENABLE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_AutoPollingTypeDef::StatusBytesSize.

HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the QSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1270 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_AutoPollingTypeDef::AutomaticStop, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_AUTOMATIC_STOP, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_IT_SM, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_AutoPollingTypeDef::StatusBytesSize, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1463 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Command | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Sets the command configuration.

Parameters:
hqspi,: QSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Time out duration
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 580 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Command_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd
 | ) |  |

Sets the command configuration in interrupt mode.

Parameters:
hqspi,: QSPI handle
cmd : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 671 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_IT_TC, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1448 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), QSPI_DMAError(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

__weak void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1538 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_IRQHandler ( QSPI_HandleTypeDef * hqspi )

This function handles QSPI interrupt request.

Parameters:
hqspi,: QSPI handle
Return values:
None.

Definition at line 404 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_GET_FLAG, __HAL_QSPI_GET_IT_SOURCE, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_Abort(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_TRANSFER, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_ERROR, HAL_QSPI_STATE_READY, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_SM, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FLAG_TO, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::TxXferCount.

HAL_StatusTypeDef HAL_QSPI_MemoryMapped | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1364 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_MEM_MAPPED, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_TIMEOUT_ACTIVATION, IS_QSPI_TIMEOUT_PERIOD, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, QSPI_IT_TO, QSPI_TIMEOUT_COUNTER_ENABLE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::Timeout, QSPI_MemoryMappedTypeDef::TimeOutActivation, and QSPI_MemoryMappedTypeDef::TimeOutPeriod.

HAL_StatusTypeDef HAL_QSPI_Receive | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Time out duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 837 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_Abort(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Receive_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receives an amount of data in non blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1095 of file stm32f7xx_hal_qspi.c.

References DMA_InitTypeDef::Direction, DMA_PERIPH_TO_MEMORY, QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_DMARxHalfCplt(), QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, QSPI_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Receive_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in no-blocking mode with Interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 973 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

__weak void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1478 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMARxCplt().

__weak void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1508 of file stm32f7xx_hal_qspi.c.

Referenced by QSPI_DMARxHalfCplt().

__weak void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1553 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1568 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Transmit | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Time out duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 754 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_Abort(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Sends an amount of data in non blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 1027 of file stm32f7xx_hal_qspi.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAError(), QSPI_DMATxCplt(), QSPI_DMATxHalfCplt(), QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, QSPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Transmit_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 922 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

__weak void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1493 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMATxCplt().

__weak void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1523 of file stm32f7xx_hal_qspi.c.

Referenced by QSPI_DMATxHalfCplt().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control and State functions

Functions
Peripheral Control and State functions
QSPI Exported Functions

QSPI control and State functions. More...

Functions

HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callbacks.
void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callbacks.
void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callbacks.
void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callbacks.
void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callbacks.
void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callbacks.
void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callbacks.
void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callbacks.
void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callbacks.

Detailed Description

QSPI control and State functions.

 ===============================================================================
                  ##### Peripheral Control and State functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Check in run-time the state of the driver.
      (+) Check the error code set during last operation.
      (+) Abort any operation.
.....

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1624 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1463 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1448 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), QSPI_DMAError(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1538 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi,: QSPI handle
Return values:
QSPI Error Code

Definition at line 1614 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI state.

Parameters:
hqspi,: QSPI handle
Return values:
HAL state

Definition at line 1604 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::State.

void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1478 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMARxCplt().

void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1508 of file stm32f7xx_hal_qspi.c.

Referenced by QSPI_DMARxHalfCplt().

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi,: QSPI handle.
Timeout,: Timeout for the QSPI memory access.
Return values:
None

Definition at line 1655 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1553 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1568 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1493 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMATxCplt().

void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callbacks.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1523 of file stm32f7xx_hal_qspi.c.

Referenced by QSPI_DMATxHalfCplt().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI_Exported_Functions_Group4

Functions
QSPI_Exported_Functions_Group4
QSPI Exported Functions

Functions

HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1624 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi,: QSPI handle
Return values:
QSPI Error Code

Definition at line 1614 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI state.

Parameters:
hqspi,: QSPI handle
Return values:
HAL state

Definition at line 1604 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::State.

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi,: QSPI handle.
Timeout,: Timeout for the QSPI memory access.
Return values:
None

Definition at line 1655 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Exported Functions

Modules | Functions
QSPI Exported Functions
QSPI

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

QSPI Transmit/Receive functions.

Peripheral Control and State functions

QSPI control and State functions.

QSPI_Exported_Functions_Group4

Functions

static void | QSPI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process half complete callback.
static void | QSPI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process half complete callback.
static void | QSPI_DMAError (DMA_HandleTypeDef *hdma)
DMA QSPI communication error callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function wait a flag state until time out.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
This function configures the communication registers.

Function Documentation

static void QSPI_Config | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | FunctionalMode
 | ) |  | [static]

This function configures the communication registers.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information
FunctionalMode,: functional mode to configured This parameter can be one of the following values:
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
Return values:
None

Definition at line 1824 of file stm32f7xx_hal_qspi.c.

References QSPI_CommandTypeDef::Address, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytes, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_FUNCTIONAL_MODE, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_DATA_NONE, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, and QSPI_CommandTypeDef::SIOOMode.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

static void QSPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1769 of file stm32f7xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_DMA, HAL_QSPI_ErrorCallback(), HAL_QSPI_STATE_ERROR, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

static void QSPI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1671 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, HAL_DMA_Abort(), HAL_QSPI_Abort(), HAL_QSPI_ErrorCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1745 of file stm32f7xx_hal_qspi.c.

References HAL_QSPI_RxHalfCpltCallback().

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1708 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, HAL_DMA_Abort(), HAL_QSPI_Abort(), HAL_QSPI_ErrorCallback(), HAL_QSPI_STATE_READY, HAL_QSPI_TxCpltCallback(), QSPI_HandleTypeDef::Instance, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::Timeout, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Transmit_DMA().

static void QSPI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1757 of file stm32f7xx_hal_qspi.c.

References HAL_QSPI_TxHalfCpltCallback().

Referenced by HAL_QSPI_Transmit_DMA().

static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function wait a flag state until time out.

Parameters:
hqspi,: QSPI handle
Flag,: Flag checked
State,: Value of the flag expected
Timeout,: Duration of the time out
Return values:
HAL status

Definition at line 1789 of file stm32f7xx_hal_qspi.c.

References __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_TIMEOUT, HAL_QSPI_STATE_ERROR, and QSPI_HandleTypeDef::State.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Exported Types

Data Structures | Enumerations
QSPI Exported Types
QSPI

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00, HAL_QSPI_STATE_READY = 0x01, HAL_QSPI_STATE_BUSY = 0x02, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, HAL_QSPI_STATE_ERROR = 0x04
}
HAL QSPI State structures definition. More...

Enumeration Type Documentation

enum HAL_QSPI_StateTypeDef

HAL QSPI State structures definition.

Enumerator:
HAL_QSPI_STATE_RESET

Peripheral not initialized

HAL_QSPI_STATE_READY

Peripheral initialized and ready for use

HAL_QSPI_STATE_BUSY

Peripheral in indirect mode and busy

HAL_QSPI_STATE_BUSY_INDIRECT_TX

Peripheral in indirect mode with transmission ongoing

HAL_QSPI_STATE_BUSY_INDIRECT_RX

Peripheral in indirect mode with reception ongoing

HAL_QSPI_STATE_BUSY_AUTO_POLLING

Peripheral in auto polling mode ongoing

HAL_QSPI_STATE_BUSY_MEM_MAPPED

Peripheral in memory mapped mode ongoing

HAL_QSPI_STATE_ERROR

Peripheral in error

Definition at line 101 of file stm32f7xx_hal_qspi.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_InitTypeDef Struct Reference
QSPI Exported Types

QSPI Init structure definition. More...

#include <stm32f7xx_hal_qspi.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | FifoThreshold
uint32_t | SampleShifting
uint32_t | FlashSize
uint32_t | ChipSelectHighTime
uint32_t | ClockMode
uint32_t | FlashID
uint32_t | DualFlash

Detailed Description

QSPI Init structure definition.

Definition at line 66 of file stm32f7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_InitTypeDef::ChipSelectHighTime

Definition at line 84 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockMode

Definition at line 88 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockPrescaler

Definition at line 68 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::DualFlash

Definition at line 94 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FifoThreshold

Definition at line 71 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FlashID

Definition at line 91 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FlashSize

Definition at line 78 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::SampleShifting

Definition at line 74 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_qspi.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_HandleTypeDef Struct Reference
QSPI Exported Types

QSPI Handle Structure definition. More...

#include <stm32f7xx_hal_qspi.h>

Data Fields

QUADSPI_TypeDef * | Instance
QSPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdma
__IO HAL_LockTypeDef | Lock
__IO HAL_QSPI_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Timeout

Detailed Description

QSPI Handle Structure definition.

Definition at line 116 of file stm32f7xx_hal_qspi.h.

Field Documentation

__IO uint32_t QSPI_HandleTypeDef::ErrorCode

Definition at line 129 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetError(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAError(), and QSPI_WaitFlagStateUntilTimeout().

DMA_HandleTypeDef* QSPI_HandleTypeDef::hdma

Definition at line 126 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

QSPI_InitTypeDef QSPI_HandleTypeDef::Init

Definition at line 119 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

QUADSPI_TypeDef* QSPI_HandleTypeDef::Instance

Definition at line 118 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_Config(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

__IO HAL_LockTypeDef QSPI_HandleTypeDef::Lock

Definition at line 127 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint8_t* QSPI_HandleTypeDef::pRxBuffPtr

Definition at line 123 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

uint8_t* QSPI_HandleTypeDef::pTxBuffPtr

Definition at line 120 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

__IO uint16_t QSPI_HandleTypeDef::RxXferCount

Definition at line 125 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), QSPI_DMAError(), and QSPI_DMARxCplt().

__IO uint16_t QSPI_HandleTypeDef::RxXferSize

Definition at line 124 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

__IO HAL_QSPI_StateTypeDef QSPI_HandleTypeDef::State

Definition at line 128 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetState(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_DMATxCplt(), and QSPI_WaitFlagStateUntilTimeout().

uint32_t QSPI_HandleTypeDef::Timeout

Definition at line 130 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_SetTimeout(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

__IO uint16_t QSPI_HandleTypeDef::TxXferCount

Definition at line 122 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAError(), and QSPI_DMATxCplt().

__IO uint16_t QSPI_HandleTypeDef::TxXferSize

Definition at line 121 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_qspi.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI_CommandTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_CommandTypeDef Struct Reference
QSPI Exported Types

QSPI Command structure definition. More...

#include <stm32f7xx_hal_qspi.h>

Data Fields

uint32_t | Instruction
uint32_t | Address
uint32_t | AlternateBytes
uint32_t | AddressSize
uint32_t | AlternateBytesSize
uint32_t | DummyCycles
uint32_t | InstructionMode
uint32_t | AddressMode
uint32_t | AlternateByteMode
uint32_t | DataMode
uint32_t | NbData
uint32_t | DdrMode
uint32_t | DdrHoldHalfCycle
uint32_t | SIOOMode

Detailed Description

QSPI Command structure definition.

Definition at line 136 of file stm32f7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_CommandTypeDef::Address

Definition at line 140 of file stm32f7xx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressMode

Definition at line 152 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressSize

Definition at line 144 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateByteMode

Definition at line 154 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytes

Definition at line 142 of file stm32f7xx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytesSize

Definition at line 146 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DataMode

Definition at line 156 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrHoldHalfCycle

Definition at line 163 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrMode

Definition at line 161 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DummyCycles

Definition at line 148 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::Instruction

Definition at line 138 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::InstructionMode

Definition at line 150 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::NbData

Definition at line 158 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::SIOOMode

Definition at line 166 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_qspi.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI_AutoPollingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_AutoPollingTypeDef Struct Reference
QSPI Exported Types

QSPI Auto Polling mode configuration structure definition. More...

#include <stm32f7xx_hal_qspi.h>

Data Fields

uint32_t | Match
uint32_t | Mask
uint32_t | Interval
uint32_t | StatusBytesSize
uint32_t | MatchMode
uint32_t | AutomaticStop

Detailed Description

QSPI Auto Polling mode configuration structure definition.

Definition at line 173 of file stm32f7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_AutoPollingTypeDef::AutomaticStop

Definition at line 185 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Interval

Definition at line 179 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Mask

Definition at line 177 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Match

Definition at line 175 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::MatchMode

Definition at line 183 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::StatusBytesSize

Definition at line 181 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_qspi.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI_MemoryMappedTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_MemoryMappedTypeDef Struct Reference
QSPI Exported Types

QSPI Memory Mapped mode configuration structure definition. More...

#include <stm32f7xx_hal_qspi.h>

Data Fields

uint32_t | TimeOutPeriod
uint32_t | TimeOutActivation

Detailed Description

QSPI Memory Mapped mode configuration structure definition.

Definition at line 192 of file stm32f7xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_MemoryMappedTypeDef::TimeOutActivation

Definition at line 196 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

uint32_t QSPI_MemoryMappedTypeDef::TimeOutPeriod

Definition at line 194 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_qspi.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Error Code

Defines
QSPI Error Code
QSPI Exported Constants

Defines

#define | HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
#define | HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)

Define Documentation

#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)

DMA transfer error

Definition at line 213 of file stm32f7xx_hal_qspi.h.

Referenced by QSPI_DMAError().

#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 210 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)

Timeout error

Definition at line 211 of file stm32f7xx_hal_qspi.h.

Referenced by QSPI_WaitFlagStateUntilTimeout().

#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)

Transfer error

Definition at line 212 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Sample Shifting

Defines
QSPI Sample Shifting
QSPI Exported Constants

Defines

#define | QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000)
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

Define Documentation

#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

1/2 clock cycle shift to sample data

Definition at line 222 of file stm32f7xx_hal_qspi.h.

#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000)

No clock cycle shift to sample data

Definition at line 221 of file stm32f7xx_hal_qspi.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Chip Select High Time

Defines
QSPI Chip Select High Time
QSPI Exported Constants

Defines

#define | QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000)
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

Define Documentation

#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000)

nCS stay high for at least 1 clock cycle between commands

Definition at line 230 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)

nCS stay high for at least 2 clock cycles between commands

Definition at line 231 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)

nCS stay high for at least 3 clock cycles between commands

Definition at line 232 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 4 clock cycles between commands

Definition at line 233 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)

nCS stay high for at least 5 clock cycles between commands

Definition at line 234 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)

nCS stay high for at least 6 clock cycles between commands

Definition at line 235 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 7 clock cycles between commands

Definition at line 236 of file stm32f7xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

nCS stay high for at least 8 clock cycles between commands

Definition at line 237 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Clock Mode

Defines
QSPI Clock Mode
QSPI Exported Constants

Defines

#define | QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Define Documentation

#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)

Clk stays low while nCS is released

Definition at line 245 of file stm32f7xx_hal_qspi.h.

#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Clk goes high while nCS is released

Definition at line 246 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Flash Select

Defines
QSPI Flash Select
QSPI Exported Constants

Defines

#define | QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
#define | QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)

Define Documentation

#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)

Definition at line 254 of file stm32f7xx_hal_qspi.h.

#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)

Definition at line 255 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Dual Flash Mode

Defines
QSPI Dual Flash Mode
QSPI Exported Constants

Defines

#define | QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define | QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)

Definition at line 264 of file stm32f7xx_hal_qspi.h.

#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)

Definition at line 263 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

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STM32F745xx HAL User Manual: QSPI Address Size

Defines
QSPI Address Size
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

Define Documentation

#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)

16-bit address

Definition at line 273 of file stm32f7xx_hal_qspi.h.

#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)

24-bit address

Definition at line 274 of file stm32f7xx_hal_qspi.h.

#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

32-bit address

Definition at line 275 of file stm32f7xx_hal_qspi.h.

#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)

8-bit address

Definition at line 272 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Alternate Bytes Size

Defines
QSPI Alternate Bytes Size
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)

16-bit alternate bytes

Definition at line 284 of file stm32f7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)

24-bit alternate bytes

Definition at line 285 of file stm32f7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

32-bit alternate bytes

Definition at line 286 of file stm32f7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)

8-bit alternate bytes

Definition at line 283 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Instruction Mode

Defines
QSPI Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Define Documentation

#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)

Instruction on a single line

Definition at line 295 of file stm32f7xx_hal_qspi.h.

#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)

Instruction on two lines

Definition at line 296 of file stm32f7xx_hal_qspi.h.

#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Instruction on four lines

Definition at line 297 of file stm32f7xx_hal_qspi.h.

#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)

No instruction

Definition at line 294 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

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STM32F745xx HAL User Manual: QSPI Address Mode

Defines
QSPI Address Mode
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_NONE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Define Documentation

#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)

Address on a single line

Definition at line 306 of file stm32f7xx_hal_qspi.h.

#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)

Address on two lines

Definition at line 307 of file stm32f7xx_hal_qspi.h.

#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Address on four lines

Definition at line 308 of file stm32f7xx_hal_qspi.h.

#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000)

No address

Definition at line 305 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Alternate Bytes Mode

Defines
QSPI Alternate Bytes Mode
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)

Alternate bytes on a single line

Definition at line 317 of file stm32f7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)

Alternate bytes on two lines

Definition at line 318 of file stm32f7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Alternate bytes on four lines

Definition at line 319 of file stm32f7xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)

No alternate bytes

Definition at line 316 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

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STM32F745xx HAL User Manual: QSPI Data Mode

Defines
QSPI Data Mode
QSPI Exported Constants

Defines

#define | QSPI_DATA_NONE ((uint32_t)0X00000000)
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Define Documentation

#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)

Data on a single line

Definition at line 328 of file stm32f7xx_hal_qspi.h.

#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)

Data on two lines

Definition at line 329 of file stm32f7xx_hal_qspi.h.

#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Data on four lines

Definition at line 330 of file stm32f7xx_hal_qspi.h.

#define QSPI_DATA_NONE ((uint32_t)0X00000000)

No data

Definition at line 327 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and QSPI_Config().

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STM32F745xx HAL User Manual: QSPI Ddr Mode

Defines
QSPI Ddr Mode
QSPI Exported Constants

Defines

#define | QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Define Documentation

#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)

Double data rate mode disabled

Definition at line 338 of file stm32f7xx_hal_qspi.h.

#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Double data rate mode enabled

Definition at line 339 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Ddr HoldHalfCycle

Defines
QSPI Ddr HoldHalfCycle
QSPI Exported Constants

Defines

#define | QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)
#define | QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)

Define Documentation

#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)

Delay the data output using analog delay in DDR mode

Definition at line 347 of file stm32f7xx_hal_qspi.h.

#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)

Delay the data output by 1/2 clock cycle in DDR mode

Definition at line 348 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI SIOO Mode

Defines
QSPI SIOO Mode
QSPI Exported Constants

Defines

#define | QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Define Documentation

#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)

Send instruction on every transaction

Definition at line 356 of file stm32f7xx_hal_qspi.h.

#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Send instruction only for the first command

Definition at line 357 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Match Mode

Defines
QSPI Match Mode
QSPI Exported Constants

Defines

#define | QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

Define Documentation

#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)

AND match mode between unmasked bits

Definition at line 365 of file stm32f7xx_hal_qspi.h.

#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

OR match mode between unmasked bits

Definition at line 366 of file stm32f7xx_hal_qspi.h.

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STM32F745xx HAL User Manual: QSPI Automatic Stop

Defines
QSPI Automatic Stop
QSPI Exported Constants

Defines

#define | QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

Define Documentation

#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)

AutoPolling stops only with abort or QSPI disabling

Definition at line 374 of file stm32f7xx_hal_qspi.h.

#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

AutoPolling stops as soon as there is a match

Definition at line 375 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling().

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STM32F745xx HAL User Manual: QSPI TimeOut Activation

Defines
QSPI TimeOut Activation
QSPI Exported Constants

Defines

#define | QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Define Documentation

#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)

Timeout counter disabled, nCS remains active

Definition at line 383 of file stm32f7xx_hal_qspi.h.

#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Timeout counter enabled, nCS released when timeout expires

Definition at line 384 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

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STM32F745xx HAL User Manual: QSPI Flags

Defines
QSPI Flags
QSPI Exported Constants

Defines

#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF

Define Documentation

#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY

Busy flag: operation is ongoing

Definition at line 392 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), and HAL_QSPI_MemoryMapped().

#define QSPI_FLAG_FT QUADSPI_SR_FTF

Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete

Definition at line 395 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

#define QSPI_FLAG_SM QUADSPI_SR_SMF

Status match flag: received data matches in autopolling mode

Definition at line 394 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_FLAG_TC QUADSPI_SR_TCF

Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted

Definition at line 396 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Command(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define QSPI_FLAG_TE QUADSPI_SR_TEF

Transfer error flag: invalid address is being accessed

Definition at line 397 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_FLAG_TO QUADSPI_SR_TOF

Timeout flag: timeout occurs in memory-mapped mode

Definition at line 393 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Interrupts

Defines
QSPI Interrupts
QSPI Exported Constants

Defines

#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE

Define Documentation

#define QSPI_IT_FT QUADSPI_CR_FTIE

Interrupt on the fifo threshold flag

Definition at line 407 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_SM QUADSPI_CR_SMIE

Interrupt on the status match flag

Definition at line 406 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_IT_TC QUADSPI_CR_TCIE

Interrupt on the transfer complete flag

Definition at line 408 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_TE QUADSPI_CR_TEIE

Interrupt on the transfer error flag

Definition at line 409 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_TO QUADSPI_CR_TOIE

Interrupt on the timeout flag

Definition at line 405 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

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STM32F745xx HAL User Manual: QSPI Timeout definition

Defines
QSPI Timeout definition
QSPI Exported Constants

Defines

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */

Define Documentation

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */

Definition at line 417 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Exported Macros

Defines
QSPI Exported Macros
QSPI

Defines

#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable QSPI.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable QSPI.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enables the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disables the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified QSPI interrupt source is enabled.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Get the selected QSPI's flag status.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.

Define Documentation

#define __HAL_QSPI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

Clears the specified QSPI's flag status.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__FLAG__,: specifies the QSPI clear register flag that needs to be set This parameter can be one of the following values:
  • QSPI_FLAG_TO: QSPI Time out flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 514 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define __HAL_QSPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Disable QSPI.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
Return values:
None

Definition at line 447 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_DeInit().

#define __HAL_QSPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Disables the specified QSPI interrupt.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to disable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 474 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

#define __HAL_QSPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Enable QSPI.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
Return values:
None

Definition at line 441 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define __HAL_QSPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Enables the specified QSPI interrupt.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to enable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Time out interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 460 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define __HAL_QSPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)

Get the selected QSPI's flag status.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__FLAG__,: specifies the QSPI flag to check. This parameter can be one of the following values:
  • QSPI_FLAG_BUSY: QSPI Busy flag
  • QSPI_FLAG_TO: QSPI Time out flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_FT: QSPI FIFO threshold flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 502 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_WaitFlagStateUntilTimeout().

#define __HAL_QSPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified QSPI interrupt source is enabled.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to check. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Time out interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 487 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

#define __HAL_QSPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)

Reset QSPI handle state.

Parameters:
__HANDLE__,: QSPI handle.
Return values:
None

Definition at line 435 of file stm32f7xx_hal_qspi.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Private Constants

Defines
QSPI Private Constants
QSPI

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Define Documentation

#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)

Automatic polling mode

Definition at line 176 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)

Indirect read mode

Definition at line 175 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)

Indirect write mode

Definition at line 174 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Memory-mapped mode

Definition at line 177 of file stm32f7xx_hal_qspi.c.

Referenced by HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Clock Prescaler

Defines
QSPI Clock Prescaler
QSPI Private Macros

Defines

#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)

Define Documentation

#define IS_QSPI_CLOCK_PRESCALER ( PRESCALER ) ((PRESCALER) <= 0xFF)

Definition at line 620 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Fifo Threshold

Defines
QSPI Fifo Threshold
QSPI Private Macros

Defines

#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))

Define Documentation

#define IS_QSPI_FIFO_THRESHOLD ( THR ) (((THR) > 0) && ((THR) <= 32))

Definition at line 628 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Flash Size

Defines
QSPI Flash Size
QSPI Private Macros

Defines

#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))

Define Documentation

#define IS_QSPI_FLASH_SIZE ( FSIZE ) (((FSIZE) <= 31))

Definition at line 639 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Instruction

Defines
QSPI Instruction
QSPI Private Macros

Defines

#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)

Define Documentation

#define IS_QSPI_INSTRUCTION ( INSTRUCTION ) ((INSTRUCTION) <= 0xFF)

Definition at line 666 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Dummy Cycles

Defines
QSPI Dummy Cycles
QSPI Private Macros

Defines

#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)

Define Documentation

#define IS_QSPI_DUMMY_CYCLES ( DCY ) ((DCY) <= 31)

Definition at line 685 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Interval

Defines
QSPI Interval
QSPI Private Macros

Defines

#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

Define Documentation

#define IS_QSPI_INTERVAL ( INTERVAL ) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

Definition at line 722 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Status Bytes Size

Defines
QSPI Status Bytes Size
QSPI Private Macros

Defines

#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))

Define Documentation

#define IS_QSPI_STATUS_BYTES_SIZE ( SIZE ) (((SIZE) >= 1) && ((SIZE) <= 4))

Definition at line 730 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI TimeOut Period

Defines
QSPI TimeOut Period
QSPI Private Macros

Defines

#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)

Define Documentation

#define IS_QSPI_TIMEOUT_PERIOD ( PERIOD ) ((PERIOD) <= 0xFFFF)

Definition at line 746 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Private Macros

Modules | Defines
QSPI Private Macros
QSPI

Modules

QSPI Clock Prescaler
QSPI Fifo Threshold
QSPI Flash Size
QSPI Instruction
QSPI Dummy Cycles
QSPI Interval
QSPI Status Bytes Size
QSPI TimeOut Period

Defines

#define | IS_QSPI_FUNCTIONAL_MODE(MODE)
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_FLASH_ID(FLA)
#define | IS_QSPI_DUAL_FLASH_MODE(MODE)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_DDR_HHC(DDR_HHC)
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_GET_FLAG(FLAG)
#define | IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))

Define Documentation

#define IS_QSPI_ADDRESS_MODE ( MODE )
Value:
(((MODE) == QSPI_ADDRESS_NONE)    || \
                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
                                             ((MODE) == QSPI_ADDRESS_4_LINES))

Definition at line 695 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ADDRESS_SIZE ( ADDR_SIZE )
Value:
(((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))

Definition at line 671 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_MODE ( MODE )
Value:
(((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))

Definition at line 700 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_SIZE ( SIZE )
Value:
(((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))

Definition at line 676 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_AUTOMATIC_STOP ( APMS )
Value:
(((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))

Definition at line 737 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_CLOCK_MODE ( CLKMODE )
Value:
(((CLKMODE) == QSPI_CLOCK_MODE_0) || \
                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))

Definition at line 653 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CS_HIGH_TIME ( CSHTIME )
Value:
(((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))

Definition at line 644 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_DATA_MODE ( MODE )
Value:
(((MODE) == QSPI_DATA_NONE)    || \
                                             ((MODE) == QSPI_DATA_1_LINE)  || \
                                             ((MODE) == QSPI_DATA_2_LINES) || \
                                             ((MODE) == QSPI_DATA_4_LINES))

Definition at line 705 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_HHC ( DDR_HHC )
Value:
(((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))

Definition at line 713 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_MODE ( DDR_MODE )
Value:
(((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))

Definition at line 710 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DUAL_FLASH_MODE ( MODE )
Value:
(((MODE) == QSPI_DUALFLASH_ENABLE) || \
                                          ((MODE) == QSPI_DUALFLASH_DISABLE))

Definition at line 659 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FLASH_ID ( FLA )
Value:
(((FLA) == QSPI_FLASH_ID_1) || \
                                  ((FLA) == QSPI_FLASH_ID_2))

Definition at line 656 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FUNCTIONAL_MODE ( MODE )
Value:
(((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))

Definition at line 186 of file stm32f7xx_hal_qspi.c.

Referenced by QSPI_Config().

#define IS_QSPI_GET_FLAG ( FLAG )
Value:
(((FLAG) == QSPI_FLAG_BUSY) || \
                                             ((FLAG) == QSPI_FLAG_TO)   || \
                                             ((FLAG) == QSPI_FLAG_SM)   || \
                                             ((FLAG) == QSPI_FLAG_FT)   || \
                                             ((FLAG) == QSPI_FLAG_TC)   || \
                                             ((FLAG) == QSPI_FLAG_TE))

Definition at line 751 of file stm32f7xx_hal_qspi.h.

#define IS_QSPI_INSTRUCTION_MODE ( MODE )
Value:
(((MODE) == QSPI_INSTRUCTION_NONE)    || \
                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))

Definition at line 690 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_IT ( IT ) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))

Definition at line 758 of file stm32f7xx_hal_qspi.h.

#define IS_QSPI_MATCH_MODE ( MODE )
Value:
(((MODE) == QSPI_MATCH_MODE_AND) || \
                                             ((MODE) == QSPI_MATCH_MODE_OR))

Definition at line 734 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_SIOO_MODE ( SIOO_MODE )
Value:
(((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))

Definition at line 716 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_SSHIFT ( SSHIFT )
Value:
(((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))

Definition at line 633 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_TIMEOUT_ACTIVATION ( TCEN )
Value:
(((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))

Definition at line 740 of file stm32f7xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Private Functions

QSPI Private Functions
QSPI
Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCC Private Macros

Defines

#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define | IS_RCC_PLLP_VALUE(VALUE)
#define | IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
#define | IS_RCC_PCLK(PCLK)
#define | IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_RTCCLKSOURCE(SOURCE)
#define | IS_RCC_LSE_DRIVE(DRIVE)

Define Documentation

#define IS_RCC_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x1F)

Definition at line 1303 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CLOCKTYPE ( CLK ) ((1 <= (CLK)) && ((CLK) <= 15))

Definition at line 1285 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( HCLK )
Value:
(((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
                           ((HCLK) == RCC_SYSCLK_DIV512))

Definition at line 1279 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( HSE )
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_BYPASS))

Definition at line 1253 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( HSI ) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))

Definition at line 1259 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( LSE )
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_BYPASS))

Definition at line 1256 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE_DRIVE ( DRIVE )
Value:
(((DRIVE) == RCC_LSEDRIVE_LOW)        || \
                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \
                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
                                 ((DRIVE) == RCC_LSEDRIVE_HIGH))

Definition at line 1323 of file stm32f7xx_hal_rcc.h.

#define IS_RCC_LSI ( LSI ) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

Definition at line 1261 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( MCOX ) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))

Definition at line 1291 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))

Definition at line 1294 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO2SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))

Definition at line 1297 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( DIV )
Value:
(((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
                             ((DIV) == RCC_MCODIV_5))

Definition at line 1300 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( OSCILLATOR ) ((OSCILLATOR) <= 15)

Definition at line 1251 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( PCLK )
Value:
(((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
                           ((PCLK) == RCC_HCLK_DIV16))

Definition at line 1287 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( PLL ) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))

Definition at line 1263 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLM_VALUE ( VALUE ) ((2 <= (VALUE)) && ((VALUE) <= 63))

Definition at line 1271 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( VALUE ) ((50 <= (VALUE)) && ((VALUE) <= 432))

Definition at line 1273 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
                                  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))

Definition at line 1275 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( VALUE ) ((2 <= (VALUE)) && ((VALUE) <= 15))

Definition at line 1277 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_PLLSOURCE_HSI) || \
                                  ((SOURCE) == RCC_PLLSOURCE_HSE))

Definition at line 1265 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))

Definition at line 1305 of file stm32f7xx_hal_rcc.h.

#define IS_RCC_SYSCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 1268 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Private Macros

Modules | Defines
RCC Private Macros
RCC

Modules

RCC Private macros to check input parameters

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Define Documentation

#define MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 107 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 108 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 109 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOC_CLK_ENABLE()

Definition at line 111 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_GPIO_PORT GPIOC

Definition at line 112 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_PIN GPIO_PIN_9

Definition at line 113 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Private Variables

Variables
RCC Private Variables
RCC

Variables

const uint8_t APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Variable Documentation

const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 122 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_GetHCLKFreq(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
##### Initialization and de-initialization functions #####
  ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
      and APB2).

    [..] Internal/external clock and PLL configuration
      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
          the PLL as System clock source.

      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
          clock source.

      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
        (++) The first output is used to generate the high speed system clock (up to 216 MHz)
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).

      (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
          clock source), the System clock is automatically switched to HSI and an interrupt
          is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
          (Non-Maskable Interrupt) exception vector.

      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
          clock (through a configurable prescaler) on PA8 pin.

      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
          clock (through a configurable prescaler) on PC9 pin.

    [..] System, AHB and APB busses clocks configuration
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
          HSE and PLL.
          The AHB clock (HCLK) is derived from System clock through configurable
          prescaler and used to clock the CPU, memory and peripherals mapped
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
          from AHB clock through configurable prescalers and used to clock
          the peripherals mapped on these busses. You can use
          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
          (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
              from an external clock mapped on the I2S_CKIN pin.
              You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
          (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
              from an external clock mapped on the I2S_CKIN pin.
               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
          (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
              divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
              macros to configure this clock.
          (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
              to work correctly, while the SDIO require a frequency equal or lower than
              to 48. This clock is derived of the main PLL through PLLQ divider.
          (+@) IWDG clock which is always the LSI clock.

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency,: FLASH Latency, this parameter depend on device selected
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 605 of file stm32f7xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_SYSCLK_CONFIG, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_PLLRDY, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

void HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL and PLLI2S OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 217 of file stm32f7xx_hal_rcc.c.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Return values:
HAL status

Definition at line 251 of file stm32f7xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CALIBRATION_VALUE, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_NONE, RCC_PLL_ON, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

  ===============================================================================
                  ##### Peripheral Control functions #####
  ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

Function Documentation

void HAL_RCC_CSSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
None

Definition at line 1173 of file stm32f7xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )

Disables the Clock Security System.

Return values:
None

Definition at line 923 of file stm32f7xx_hal_rcc.c.

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
Return values:
None

Definition at line 914 of file stm32f7xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency,: Pointer on the Flash Latency.
Return values:
None

Definition at line 1130 of file stm32f7xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 1014 of file stm32f7xx_hal_rcc.c.

References APBAHBPrescTable, and HAL_RCC_GetSysClockFreq().

Referenced by HAL_ETH_Init(), HAL_InitTick(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1051 of file stm32f7xx_hal_rcc.c.

References RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1026 of file stm32f7xx_hal_rcc.c.

References APBAHBPrescTable, and HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency

Definition at line 1038 of file stm32f7xx_hal_rcc.c.

References APBAHBPrescTable, and HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 958 of file stm32f7xx_hal_rcc.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, HSE_VALUE, HSI_VALUE, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Referenced by HAL_RCC_GetHCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).

Note:
PA8/PC9 should be configured in alternate function mode.
Parameters:
RCC_MCOx,: specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2: Clock source to output on MCO2 pin(PC9).
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
RCC_MCODiv,: specifies the MCOx prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1: no division applied to MCOx clock
  • RCC_MCODIV_2: division by 2 applied to MCOx clock
  • RCC_MCODIV_3: division by 3 applied to MCOx clock
  • RCC_MCODIV_4: division by 4 applied to MCOx clock
  • RCC_MCODIV_5: division by 5 applied to MCOx clock
Return values:
None

Definition at line 860 of file stm32f7xx_hal_rcc.c.

References GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_CLK_ENABLE, MCO1_GPIO_PORT, MCO1_PIN, MCO2_CLK_ENABLE, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1156 of file stm32f7xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_CSS.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32f7xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ

Detailed Description

RCC PLL configuration structure definition.

Definition at line 66 of file stm32f7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 2 and Max_Data = 63

Definition at line 74 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 100 and Max_Data = 432

Definition at line 77 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for main system clock (SYSCLK). This parameter must be a value of PLLP Clock Divider

Definition at line 80 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 15

Definition at line 83 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 71 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of RCC PLL Config

Definition at line 68 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rcc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...

#include <stm32f7xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.

Definition at line 91 of file stm32f7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of RCC HSE Config

Definition at line 96 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 105 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of RCC HSI Config

Definition at line 102 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of RCC LSE Config

Definition at line 99 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of RCC LSI Config

Definition at line 108 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 93 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

PLL structure parameters

Definition at line 111 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rcc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32f7xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 118 of file stm32f7xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of RCC AHB Clock Source

Definition at line 126 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB1/APB2 Clock Source

Definition at line 129 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC APB1/APB2 Clock Source

Definition at line 132 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of RCC System Clock Type

Definition at line 120 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source (SYSCLKS) used as system clock. This parameter can be a value of RCC System Clock Source

Definition at line 123 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rcc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)

Define Documentation

#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)

Definition at line 150 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)

Definition at line 151 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)

Definition at line 152 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)

Definition at line 153 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)

Definition at line 149 of file stm32f7xx_hal_rcc.h.

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STM32F745xx HAL User Manual: RCC HSE Config

Defines
RCC HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF ((uint32_t)0x00000000)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Definition at line 163 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF ((uint32_t)0x00000000)

Definition at line 161 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

Definition at line 162 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F745xx HAL User Manual: RCC LSE Config

Defines
RCC LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF ((uint32_t)0x00000000)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Definition at line 173 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF ((uint32_t)0x00000000)

Definition at line 171 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

Definition at line 172 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F745xx HAL User Manual: RCC HSI Config

Defines
RCC HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF ((uint32_t)0x00000000)
#define | RCC_HSI_ON RCC_CR_HSION

Define Documentation

#define RCC_HSI_OFF ((uint32_t)0x00000000)

Definition at line 181 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

Definition at line 182 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

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STM32F745xx HAL User Manual: RCC LSI Config

Defines
RCC LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF ((uint32_t)0x00000000)
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF ((uint32_t)0x00000000)

Definition at line 190 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

Definition at line 191 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F745xx HAL User Manual: RCC PLL Config

Defines
RCC PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE ((uint32_t)0x00000000)
#define | RCC_PLL_OFF ((uint32_t)0x00000001)
#define | RCC_PLL_ON ((uint32_t)0x00000002)

Define Documentation

#define RCC_PLL_NONE ((uint32_t)0x00000000)

Definition at line 199 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF ((uint32_t)0x00000001)

Definition at line 200 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLL_ON ((uint32_t)0x00000002)

Definition at line 201 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PLLP Clock Divider

Defines
PLLP Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLP_DIV2 ((uint32_t)0x00000002)
#define | RCC_PLLP_DIV4 ((uint32_t)0x00000004)
#define | RCC_PLLP_DIV6 ((uint32_t)0x00000006)
#define | RCC_PLLP_DIV8 ((uint32_t)0x00000008)

Define Documentation

#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)

Definition at line 209 of file stm32f7xx_hal_rcc.h.

#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)

Definition at line 210 of file stm32f7xx_hal_rcc.h.

#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)

Definition at line 211 of file stm32f7xx_hal_rcc.h.

#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)

Definition at line 212 of file stm32f7xx_hal_rcc.h.

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STM32F745xx HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Definition at line 221 of file stm32f7xx_hal_rcc.h.

#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

Definition at line 220 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and I2S_GetClockFreq().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC System Clock Type

Defines
RCC System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)

Define Documentation

#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)

Definition at line 230 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)

Definition at line 231 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)

Definition at line 232 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)

Definition at line 229 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

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STM32F745xx HAL User Manual: RCC System Clock Source

Defines
RCC System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

Definition at line 241 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

Definition at line 240 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Definition at line 242 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

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STM32F745xx HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 252 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 251 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 253 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC AHB Clock Source

Defines
RCC AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

Definition at line 261 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

Definition at line 267 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

Definition at line 265 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

Definition at line 262 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

Definition at line 268 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

Definition at line 263 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Definition at line 269 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

Definition at line 266 of file stm32f7xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

Definition at line 264 of file stm32f7xx_hal_rcc.h.

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STM32F745xx HAL User Manual: RCC APB1/APB2 Clock Source

Defines
RCC APB1/APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

Definition at line 277 of file stm32f7xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Definition at line 281 of file stm32f7xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

Definition at line 278 of file stm32f7xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

Definition at line 279 of file stm32f7xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

Definition at line 280 of file stm32f7xx_hal_rcc.h.

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STM32F745xx HAL User Manual: RCC RTC Clock Source

Defines
RCC RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
#define | RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)

Definition at line 299 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)

Definition at line 300 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)

Definition at line 301 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)

Definition at line 302 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)

Definition at line 303 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)

Definition at line 304 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)

Definition at line 305 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)

Definition at line 306 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)

Definition at line 307 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)

Definition at line 308 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)

Definition at line 291 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)

Definition at line 309 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)

Definition at line 310 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)

Definition at line 311 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)

Definition at line 312 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)

Definition at line 313 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)

Definition at line 314 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)

Definition at line 315 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)

Definition at line 316 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)

Definition at line 317 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)

Definition at line 318 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)

Definition at line 292 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)

Definition at line 319 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)

Definition at line 320 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)

Definition at line 293 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)

Definition at line 294 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)

Definition at line 295 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)

Definition at line 296 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)

Definition at line 297 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)

Definition at line 298 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)

Definition at line 289 of file stm32f7xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)

Definition at line 290 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC MCO Index

Defines
RCC MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 ((uint32_t)0x00000000)
#define | RCC_MCO2 ((uint32_t)0x00000001)

Define Documentation

#define RCC_MCO1 ((uint32_t)0x00000000)

Definition at line 330 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO2 ((uint32_t)0x00000001)

Definition at line 331 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC MCO1 Clock Source

Defines
RCC MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1

Definition at line 341 of file stm32f7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)

Definition at line 339 of file stm32f7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0

Definition at line 340 of file stm32f7xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1

Definition at line 342 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC MCO2 Clock Source

Defines
RCC MCO2 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define | RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2

Define Documentation

#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1

Definition at line 352 of file stm32f7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2

Definition at line 353 of file stm32f7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0

Definition at line 351 of file stm32f7xx_hal_rcc.h.

#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)

Definition at line 350 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC MCO1 Clock Prescaler

Defines
RCC MCO1 Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 ((uint32_t)0x00000000)
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_5 RCC_CFGR_MCO1PRE

Define Documentation

#define RCC_MCODIV_1 ((uint32_t)0x00000000)

Definition at line 361 of file stm32f7xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2

Definition at line 362 of file stm32f7xx_hal_rcc.h.

#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

Definition at line 363 of file stm32f7xx_hal_rcc.h.

#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 364 of file stm32f7xx_hal_rcc.h.

#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE

Definition at line 365 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Interrupt

Defines
RCC Interrupt
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY ((uint8_t)0x01)
#define | RCC_IT_LSERDY ((uint8_t)0x02)
#define | RCC_IT_HSIRDY ((uint8_t)0x04)
#define | RCC_IT_HSERDY ((uint8_t)0x08)
#define | RCC_IT_PLLRDY ((uint8_t)0x10)
#define | RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define | RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define | RCC_IT_CSS ((uint8_t)0x80)

Define Documentation

#define RCC_IT_CSS ((uint8_t)0x80)

Definition at line 380 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY ((uint8_t)0x08)

Definition at line 376 of file stm32f7xx_hal_rcc.h.

#define RCC_IT_HSIRDY ((uint8_t)0x04)

Definition at line 375 of file stm32f7xx_hal_rcc.h.

#define RCC_IT_LSERDY ((uint8_t)0x02)

Definition at line 374 of file stm32f7xx_hal_rcc.h.

#define RCC_IT_LSIRDY ((uint8_t)0x01)

Definition at line 373 of file stm32f7xx_hal_rcc.h.

#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)

Definition at line 378 of file stm32f7xx_hal_rcc.h.

#define RCC_IT_PLLRDY ((uint8_t)0x10)

Definition at line 377 of file stm32f7xx_hal_rcc.h.

#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)

Definition at line 379 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Flags

Defines
RCC Flags
RCC Exported Constants

Elements values convention: 0XXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define | RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_BORRST ((uint8_t)0x79)
#define | RCC_FLAG_PINRST ((uint8_t)0x7A)
#define | RCC_FLAG_PORRST ((uint8_t)0x7B)
#define | RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7F)

Detailed Description

Elements values convention: 0XXYYYYYb.

  • YYYYY : Flag position in the register
  • 0XX : Register index
    • 01: CR register
    • 10: BDCR register
    • 11: CSR register

Define Documentation

#define RCC_FLAG_BORRST ((uint8_t)0x79)

Definition at line 406 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((uint8_t)0x31)

Definition at line 396 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_HSIRDY ((uint8_t)0x21)

Definition at line 395 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)

Definition at line 410 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)

Definition at line 412 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)0x41)

Definition at line 402 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_LSIRDY ((uint8_t)0x61)

Definition at line 405 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_PINRST ((uint8_t)0x7A)

Definition at line 407 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)

Definition at line 398 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_PLLRDY ((uint8_t)0x39)

Definition at line 397 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)

Definition at line 399 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_PORRST ((uint8_t)0x7B)

Definition at line 408 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)0x7C)

Definition at line 409 of file stm32f7xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)

Definition at line 411 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC LSE Drive configurations

Defines
RCC LSE Drive configurations
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Definition at line 423 of file stm32f7xx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)

Definition at line 420 of file stm32f7xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0

Definition at line 422 of file stm32f7xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1

Definition at line 421 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: AHB1 Peripheral Clock Enable Disable

Defines
AHB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))

Definition at line 460 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 444 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

Definition at line 461 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 452 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_PWR_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 491 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 482 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableOverDrive(), HAL_PWREx_EnableOverDrive(), HAL_PWREx_EnterUnderDriveSTOPMode(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 490 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 474 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 511 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 503 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_ETH_Init(), and HAL_GPIO_Init().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: AHB1 Peripheral Clock Enable Disable Status

Defines
AHB1 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)

Definition at line 527 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)

Definition at line 524 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)

Definition at line 528 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)

Definition at line 525 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB1 Peripheral Clock Enable Disable Status

Defines
APB1 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Definition at line 544 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

Definition at line 541 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

Definition at line 543 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)

Definition at line 540 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB2 Peripheral Clock Enable Disable Status

Defines
APB2 Peripheral Clock Enable Disable Status
RCC Exported Macros

EGet the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)

Detailed Description

EGet the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)

Definition at line 557 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)

Definition at line 556 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Peripheral Clock Force Release

Defines
RCC Peripheral Clock Force Release
RCC Exported Macros

Force or release AHB peripheral reset. More...

Defines

#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))

Detailed Description

Force or release AHB peripheral reset.

Define Documentation

#define __HAL_RCC_AHB1_FORCE_RESET ( ) (RCC->AHB1RSTR = 0xFFFFFFFF)

Definition at line 566 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) (RCC->AHB1RSTR = 0x00)

Definition at line 570 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CRC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))

Definition at line 567 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))

Definition at line 571 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

Definition at line 568 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))

Definition at line 572 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB1 Force Release Reset

Defines
APB1 Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) (RCC->APB1RSTR = 0xFFFFFFFF)

Definition at line 581 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) (RCC->APB1RSTR = 0x00)

Definition at line 585 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_PWR_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))

Definition at line 583 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Definition at line 587 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_WWDG_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))

Definition at line 582 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))

Definition at line 586 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB2 Force Release Reset

Defines
APB2 Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_APB2_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFF)

Definition at line 596 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) (RCC->APB2RSTR = 0x00)

Definition at line 599 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))

Definition at line 597 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))

Definition at line 600 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Peripheral Clock Sleep Enable Disable

Defines
RCC Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Defines

#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))

Detailed Description

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))

Definition at line 616 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))

Definition at line 613 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))

Definition at line 617 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

Definition at line 614 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))

Definition at line 629 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))

Definition at line 626 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))

Definition at line 638 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 637 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))

Definition at line 628 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 625 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: AHB1 Peripheral Clock Sleep Enable Disable Status

Defines
AHB1 Peripheral Clock Sleep Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)

Definition at line 655 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)

Definition at line 652 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)

Definition at line 656 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)

Definition at line 653 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB1 Peripheral Clock Sleep Enable Disable Status

Defines
APB1 Peripheral Clock Sleep Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)

Definition at line 673 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)

Definition at line 670 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)

Definition at line 672 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)

Definition at line 669 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: APB2 Peripheral Clock Sleep Enable Disable Status

Defines
APB2 Peripheral Clock Sleep Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)

Definition at line 687 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)

Definition at line 686 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HSI Configuration

Defines
HSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Define Documentation

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICALIBRATIONVALUE__ )
Value:
(MODIFY_REG(RCC->CR,\
        RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICALIBRATIONVALUE__,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Definition at line 719 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) (RCC->CR &= ~(RCC_CR_HSION))

Definition at line 711 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) (RCC->CR |= (RCC_CR_HSION))

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 710 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LSI Configuration

Defines
LSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))

Define Documentation

#define __HAL_RCC_LSI_DISABLE ( ) (RCC->CSR &= ~(RCC_CSR_LSION))

Definition at line 738 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) (RCC->CSR |= (RCC_CSR_LSION))

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Definition at line 737 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HSE Configuration

Defines
HSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (__HSE__).

Define Documentation

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                     \
                      CLEAR_BIT(RCC->CR, RCC_CR_HSEON);      \
                      if((__STATE__) == RCC_HSE_ON)          \
                      {                                      \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                      }                                      \
                      else if((__STATE__) == RCC_HSE_BYPASS) \
                      {                                      \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                      }                                      \
                      else                                   \
                      {                                      \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
                        }                                    \
                    } while(0)

Macro to configure the External High Speed oscillator (__HSE__).

Note:
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__,: specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator.
  • RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

Definition at line 765 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: LSE Configuration

Defines
LSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).

Define Documentation

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                       \
                      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      if((__STATE__) == RCC_LSE_ON)            \
                      {                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else if((__STATE__) == RCC_LSE_BYPASS)   \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else                                     \
                      {                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
                      }                                        \
                    } while(0)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__,: specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator.
  • RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.

Definition at line 810 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Clock Configuration

Defines
RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) (RCC->BDCR |= (RCC_BDCR_BDRST))

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.

Definition at line 876 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) (RCC->BDCR &= ~(RCC_BDCR_BDRST))

Definition at line 877 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_CLKPRESCALER ( __RTCCLKSource__ )
Value:
(((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by a Power On Reset (POR).
Parameters:
__RTCCLKSource__,: specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Definition at line 864 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_RTC_CONFIG ( __RTCCLKSource__ )
Value:
do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
                                                   } while (0)

Definition at line 867 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) (RCC->BDCR &= ~(RCC_BDCR_RTCEN))

Definition at line 841 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) (RCC->BDCR |= (RCC_BDCR_RTCEN))

Macros to enable or disable the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 840 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PLL Configuration

Defines
PLL Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.

Define Documentation

#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__
 | ) |
Value:
(RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__RCC_PLLSource__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Note:
This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Parameters:
__PLLM__,: specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Parameters:
__PLLN__,: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 100 and Max_Data = 432.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.
Parameters:
__PLLP__,: specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
Note:
You have to set the PLLP parameter correctly to not exceed 216 MHz on the System clock frequency.
Parameters:
__PLLQ__,: specifies the division factor for OTG FS, SDMMC and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Note:
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Definition at line 924 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLON)

Definition at line 894 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLON)

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 893 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG ( __PLLM__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

Macro to configure the PLL multiplication factor.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLM__,: specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Definition at line 948 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Definition at line 937 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PLL I2S Configuration

Defines
PLL I2S Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_I2S_CONFIG(__SOURCE__)
Macro to configure the I2S clock source (I2SCLK).
#define | __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
Macros to enable or disable the PLLI2S.
#define | __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))

Define Documentation

#define __HAL_RCC_I2S_CONFIG ( __SOURCE__ )
Value:
do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
                                             RCC->CFGR |= (__SOURCE__);       \
                                            }while(0)

Macro to configure the I2S clock source (I2SCLK).

Note:
This function must be called before enabling the I2S APB clock.
Parameters:
__SOURCE__,: specifies the I2S clock source. This parameter can be one of the following values:
  • RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
  • RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source.

Definition at line 965 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_DISABLE ( ) (RCC->CR &= ~(RCC_CR_PLLI2SON))

Definition at line 973 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_ENABLE ( ) (RCC->CR |= (RCC_CR_PLLI2SON))

Macros to enable or disable the PLLI2S.

Note:
The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 972 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Get Clock source

Defines
Get Clock source
RCC Exported Macros

Defines

#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Macro to configures the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.

Define Documentation

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 1023 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.

Definition at line 998 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define __HAL_RCC_LSEDRIVE_CONFIG ( __RCC_LSEDRIVE__ ) (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))

Macro to configures the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
Parameters:
__RCC_LSEDRIVE__,: specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Return values:
None

Definition at line 1014 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCLK_CONFIG ( __RCC_SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__RCC_SYSCLKSOURCE__,: specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

Definition at line 989 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Extended MCOx Clock Config

Defines
RCC Extended MCOx Clock Config
RCC Exported Macros

Defines

#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO1 clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
Macro to configure the MCO2 clock.

Define Documentation

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the MCO1 clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1: no division applied to MCOx clock
  • RCC_MCODIV_2: division by 2 applied to MCOx clock
  • RCC_MCODIV_3: division by 3 applied to MCOx clock
  • RCC_MCODIV_4: division by 4 applied to MCOx clock
  • RCC_MCODIV_5: division by 5 applied to MCOx clock

Definition at line 1048 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_MCO2_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));

Macro to configure the MCO2 clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1: no division applied to MCOx clock
  • RCC_MCODIV_2: division by 2 applied to MCOx clock
  • RCC_MCODIV_3: division by 3 applied to MCOx clock
  • RCC_MCODIV_4: division by 4 applied to MCOx clock
  • RCC_MCODIV_5: division by 5 applied to MCOx clock

Definition at line 1067 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.

Parameters:
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
  • RCC_IT_CSS: Clock Security System interrupt

Definition at line 1116 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->CSR |= RCC_CSR_RMVF)

Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

Definition at line 1135 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))

Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

Definition at line 1102 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

Definition at line 1089 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ ) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)

Definition at line 1156 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))

Check the RCC's interrupt has occurred or not.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 1130 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_FLAG_MASK ((uint8_t)0x1F)

Check RCC flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready.
  • RCC_FLAG_HSERDY: HSE oscillator clock ready.
  • RCC_FLAG_PLLRDY: Main PLL clock ready.
  • RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
  • RCC_FLAG_LSERDY: LSE oscillator clock ready.
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready.
  • RCC_FLAG_BORRST: POR/PDR or BOR reset.
  • RCC_FLAG_PINRST: Pin reset.
  • RCC_FLAG_PORRST: POR/PDR reset.
  • RCC_FLAG_SFTRST: Software reset.
  • RCC_FLAG_IWDGRST: Independent Watchdog reset.
  • RCC_FLAG_WWDGRST: Window Watchdog reset.
  • RCC_FLAG_LPWRRST: Low Power reset.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1155 of file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC BitAddress Alias

Defines
RCC BitAddress Alias
RCC Private Constants

RCC registers bit address alias. More...

Defines

#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
#define | RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)

Detailed Description

RCC registers bit address alias.

Define Documentation

#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))

Definition at line 1229 of file stm32f7xx_hal_rcc.h.

#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))

Definition at line 1232 of file stm32f7xx_hal_rcc.h.

#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)

Definition at line 1234 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)

Definition at line 1235 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Private Constants

Modules | Defines
RCC Private Constants
RCC

Modules

RCC BitAddress Alias

RCC registers bit address alias.

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define | LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define | PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */

Define Documentation

#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */

Definition at line 1222 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 1218 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */

Definition at line 1219 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */

Definition at line 1220 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */

Definition at line 1221 of file stm32f7xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_RCC_OscConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Private Defines

Defines
RCCEx Private Defines
RCCEx

Defines

#define | PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
#define | PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */

Define Documentation

#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */

Definition at line 62 of file stm32f7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */

Definition at line 63 of file stm32f7xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCCEx Private Macros

Defines

#define | IS_RCC_PERIPHCLOCK(SELECTION)
#define | IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define | IS_RCC_PLLI2SP_VALUE(VALUE)
#define | IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define | IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define | IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define | IS_RCC_PLLSAIP_VALUE(VALUE)
#define | IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define | IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define | IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define | IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define | IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
#define | IS_RCC_I2SCLKSOURCE(SOURCE)
#define | IS_RCC_SDMMC1CLKSOURCE(SOURCE)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_USART2CLKSOURCE(SOURCE)
#define | IS_RCC_USART3CLKSOURCE(SOURCE)
#define | IS_RCC_UART4CLKSOURCE(SOURCE)
#define | IS_RCC_UART5CLKSOURCE(SOURCE)
#define | IS_RCC_USART6CLKSOURCE(SOURCE)
#define | IS_RCC_UART7CLKSOURCE(SOURCE)
#define | IS_RCC_UART8CLKSOURCE(SOURCE)
#define | IS_RCC_I2C1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_I2C3CLKSOURCE(SOURCE)
#define | IS_RCC_I2C4CLKSOURCE(SOURCE)
#define | IS_RCC_LPTIM1CLK(SOURCE)
#define | IS_RCC_CLK48SOURCE(SOURCE)
#define | IS_RCC_TIMPRES(VALUE)
#define | IS_RCC_SAI1CLKSOURCE(SOURCE)
#define | IS_RCC_SAI2CLKSOURCE(SOURCE)

Define Documentation

#define IS_RCC_CECCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
                                      ((SOURCE) == RCC_CECCLKSOURCE_LSE))

Definition at line 2615 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CLK48SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
                ((SOURCE) == RCC_CLK48SOURCE_PLL))

Definition at line 2685 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
                ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
                ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))

Definition at line 2663 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
                ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
                ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))

Definition at line 2667 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C3CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
                ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
                ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))

Definition at line 2672 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C4CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
                ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
                ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))

Definition at line 2676 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2SCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
                                      ((SOURCE) == RCC_I2SCLKSOURCE_EXT))

Definition at line 2609 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLK ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  || \
                ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  || \
                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))

Definition at line 2680 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PERIPHCLOCK ( SELECTION )
Value:
((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))

Definition at line 2561 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLI2S_DIVQ_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 32))

Definition at line 2603 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLI2SN_VALUE ( VALUE ) ((50 <= (VALUE)) && ((VALUE) <= 432))

Definition at line 2585 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLI2SP_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLLI2SP_DIV2) ||\
                                     ((VALUE) == RCC_PLLI2SP_DIV4) ||\
                                     ((VALUE) == RCC_PLLI2SP_DIV6) ||\
                                     ((VALUE) == RCC_PLLI2SP_DIV8))

Definition at line 2586 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLI2SQ_VALUE ( VALUE ) ((2 <= (VALUE)) && ((VALUE) <= 15))

Definition at line 2590 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLI2SR_VALUE ( VALUE ) ((2 <= (VALUE)) && ((VALUE) <= 7))

Definition at line 2591 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAI_DIVQ_VALUE ( VALUE ) ((1 <= (VALUE)) && ((VALUE) <= 32))

Definition at line 2601 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAI_DIVR_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLLSAIDIVR_2) ||\
                                         ((VALUE) == RCC_PLLSAIDIVR_4) ||\
                                         ((VALUE) == RCC_PLLSAIDIVR_8) ||\
                                         ((VALUE) == RCC_PLLSAIDIVR_16))

Definition at line 2605 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAIN_VALUE ( VALUE ) ((50 <= (VALUE)) && ((VALUE) <= 432))

Definition at line 2593 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAIP_VALUE ( VALUE )
Value:
(((VALUE) == RCC_PLLSAIP_DIV2) ||\
                                     ((VALUE) == RCC_PLLSAIP_DIV4) ||\
                                     ((VALUE) == RCC_PLLSAIP_DIV6) ||\
                                     ((VALUE) == RCC_PLLSAIP_DIV8))

Definition at line 2594 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAIQ_VALUE ( VALUE ) ((2 <= (VALUE)) && ((VALUE) <= 15))

Definition at line 2598 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAIR_VALUE ( VALUE ) ((2 <= (VALUE)) && ((VALUE) <= 7))

Definition at line 2599 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SAI1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))

Definition at line 2693 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SAI2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))

Definition at line 2696 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SDMMC1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
                                        ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))

Definition at line 2612 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_TIMPRES ( VALUE )
Value:
(((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
                ((VALUE) == RCC_TIMPRES_ACTIVATED))

Definition at line 2688 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART4CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \
                ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_UART4CLKSOURCE_HSI))

Definition at line 2634 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART5CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \
                ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_UART5CLKSOURCE_HSI))

Definition at line 2640 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART7CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART7CLKSOURCE_PCLK1)  || \
                ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_UART7CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_UART7CLKSOURCE_HSI))

Definition at line 2652 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART8CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_UART8CLKSOURCE_PCLK1)  || \
                ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_UART8CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_UART8CLKSOURCE_HSI))

Definition at line 2658 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
                ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_USART1CLKSOURCE_HSI))

Definition at line 2617 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART2CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART2CLKSOURCE_PCLK1)  || \
                ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_USART2CLKSOURCE_HSI))

Definition at line 2623 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART3CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART3CLKSOURCE_PCLK1)  || \
                ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_USART3CLKSOURCE_HSI))

Definition at line 2628 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART6CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2)  || \
                ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
                ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
                ((SOURCE) == RCC_USART6CLKSOURCE_HSI))

Definition at line 2646 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions | RCCEx

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_PeriphCLKInitTypeDef according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) and RCC_BDCR register will be set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_PeriphCLKInitTypeDef according to the internal RCC configuration registers.

Parameters:
PeriphClkInit,: pointer to the configured RCC_PeriphCLKInitTypeDef structure
Return values:
None

Definition at line 647 of file stm32f7xx_hal_rcc_ex.c.

References __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_CLK48_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_I2C4_SOURCE, __HAL_RCC_GET_I2SCLKSOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2_SOURCE, __HAL_RCC_GET_SDMMC1_SOURCE, __HAL_RCC_GET_UART4_SOURCE, __HAL_RCC_GET_UART5_SOURCE, __HAL_RCC_GET_UART7_SOURCE, __HAL_RCC_GET_UART8_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USART6_SOURCE, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::Clk48ClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::I2c4ClockSelection, RCC_PeriphCLKInitTypeDef::I2sClockSelection, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLLI2S, RCC_PeriphCLKInitTypeDef::PLLI2SDivQ, RCC_PLLI2SInitTypeDef::PLLI2SN, RCC_PLLI2SInitTypeDef::PLLI2SP, RCC_PLLI2SInitTypeDef::PLLI2SQ, RCC_PLLI2SInitTypeDef::PLLI2SR, RCC_PeriphCLKInitTypeDef::PLLSAI, RCC_PeriphCLKInitTypeDef::PLLSAIDivQ, RCC_PeriphCLKInitTypeDef::PLLSAIDivR, RCC_PLLSAIInitTypeDef::PLLSAIN, RCC_PLLSAIInitTypeDef::PLLSAIP, RCC_PLLSAIInitTypeDef::PLLSAIQ, RCC_PLLSAIInitTypeDef::PLLSAIR, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C4, RCC_PERIPHCLK_I2S, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SDMMC1, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_UART7, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART3, RCC_TIMPRES_ACTIVATED, RCC_TIMPRES_DESACTIVATED, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2ClockSelection, RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection, RCC_PeriphCLKInitTypeDef::TIMPresSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Uart5ClockSelection, RCC_PeriphCLKInitTypeDef::Uart7ClockSelection, RCC_PeriphCLKInitTypeDef::Uart8ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::Usart6ClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for a given peripheral(SAI..)

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk,: Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
  • RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
Return values:
Frequency in KHz

Definition at line 763 of file stm32f7xx_hal_rcc_ex.c.

References EXTERNAL_CLOCK_VALUE, HSE_VALUE, HSI_VALUE, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, and RCC_PLLSOURCE_HSI.

Referenced by SAI_GetInputClock().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that contains the configuration information for the Extended Peripherals clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register are set to their reset values.
Return values:
HAL status

Definition at line 126 of file stm32f7xx_hal_rcc_ex.c.

References __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_CEC_CONFIG, __HAL_RCC_CLK48_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C2_CONFIG, __HAL_RCC_I2C3_CONFIG, __HAL_RCC_I2C4_CONFIG, __HAL_RCC_I2S_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_PLLI2S_CONFIG, __HAL_RCC_PLLI2S_DISABLE, __HAL_RCC_PLLI2S_ENABLE, __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG, __HAL_RCC_PLLSAI_CONFIG, __HAL_RCC_PLLSAI_DISABLE, __HAL_RCC_PLLSAI_ENABLE, __HAL_RCC_PLLSAI_GET_FLAG, __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG, __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_RTC_CONFIG, __HAL_RCC_SAI1_CONFIG, __HAL_RCC_SAI2_CONFIG, __HAL_RCC_SDMMC1_CONFIG, __HAL_RCC_TIMCLKPRESCALER, __HAL_RCC_UART4_CONFIG, __HAL_RCC_UART5_CONFIG, __HAL_RCC_UART7_CONFIG, __HAL_RCC_UART8_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USART2_CONFIG, __HAL_RCC_USART3_CONFIG, __HAL_RCC_USART6_CONFIG, assert_param, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::Clk48ClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::I2c4ClockSelection, RCC_PeriphCLKInitTypeDef::I2sClockSelection, IS_RCC_CECCLKSOURCE, IS_RCC_CLK48SOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C2CLKSOURCE, IS_RCC_I2C3CLKSOURCE, IS_RCC_I2C4CLKSOURCE, IS_RCC_I2SCLKSOURCE, IS_RCC_LPTIM1CLK, IS_RCC_PERIPHCLOCK, IS_RCC_PLLI2S_DIVQ_VALUE, IS_RCC_PLLI2SN_VALUE, IS_RCC_PLLI2SP_VALUE, IS_RCC_PLLI2SQ_VALUE, IS_RCC_PLLI2SR_VALUE, IS_RCC_PLLSAI_DIVQ_VALUE, IS_RCC_PLLSAI_DIVR_VALUE, IS_RCC_PLLSAIN_VALUE, IS_RCC_PLLSAIP_VALUE, IS_RCC_PLLSAIQ_VALUE, IS_RCC_PLLSAIR_VALUE, IS_RCC_SAI1CLKSOURCE, IS_RCC_SAI2CLKSOURCE, IS_RCC_SDMMC1CLKSOURCE, IS_RCC_TIMPRES, IS_RCC_UART4CLKSOURCE, IS_RCC_UART5CLKSOURCE, IS_RCC_UART7CLKSOURCE, IS_RCC_UART8CLKSOURCE, IS_RCC_USART1CLKSOURCE, IS_RCC_USART2CLKSOURCE, IS_RCC_USART3CLKSOURCE, IS_RCC_USART6CLKSOURCE, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLLI2S, PLLI2S_TIMEOUT_VALUE, RCC_PeriphCLKInitTypeDef::PLLI2SDivQ, RCC_PLLI2SInitTypeDef::PLLI2SN, RCC_PLLI2SInitTypeDef::PLLI2SP, RCC_PLLI2SInitTypeDef::PLLI2SQ, RCC_PLLI2SInitTypeDef::PLLI2SR, RCC_PeriphCLKInitTypeDef::PLLSAI, PLLSAI_TIMEOUT_VALUE, RCC_PeriphCLKInitTypeDef::PLLSAIDivQ, RCC_PeriphCLKInitTypeDef::PLLSAIDivR, RCC_PLLSAIInitTypeDef::PLLSAIN, RCC_PLLSAIInitTypeDef::PLLSAIP, RCC_PLLSAIInitTypeDef::PLLSAIQ, RCC_PLLSAIInitTypeDef::PLLSAIR, RCC_CLK48SOURCE_PLLSAIP, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_LSERDY, RCC_FLAG_PLLI2SRDY, RCC_I2SCLKSOURCE_PLLI2S, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_CLK48, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_I2C4, RCC_PERIPHCLK_I2S, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_PLLI2S, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SDMMC1, RCC_PERIPHCLK_SPDIFRX, RCC_PERIPHCLK_TIM, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_UART7, RCC_PERIPHCLK_UART8, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USART6, RCC_SAI1CLKSOURCE_PLLI2S, RCC_SAI1CLKSOURCE_PLLSAI, RCC_SAI2CLKSOURCE_PLLI2S, RCC_SAI2CLKSOURCE_PLLSAI, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2ClockSelection, RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection, RCC_PeriphCLKInitTypeDef::TIMPresSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Uart5ClockSelection, RCC_PeriphCLKInitTypeDef::Uart7ClockSelection, RCC_PeriphCLKInitTypeDef::Uart8ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::Usart6ClockSelection.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC_PLLI2SInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLI2SInitTypeDef Struct Reference
RCCEx Exported Types

PLLI2S Clock structure definition. More...

#include <stm32f7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLLI2SN
uint32_t | PLLI2SR
uint32_t | PLLI2SQ
uint32_t | PLLI2SP

Detailed Description

PLLI2S Clock structure definition.

Definition at line 65 of file stm32f7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLLI2SInitTypeDef::PLLI2SN

Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI

Definition at line 67 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PLLI2SInitTypeDef::PLLI2SP

Specifies the division factor for SPDIF-RX clock. This parameter must be a value of RCCEx PLLI2SP Clock Divider. This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX

Definition at line 79 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PLLI2SInitTypeDef::PLLI2SQ

Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLI2S is selected as Clock Source SAI

Definition at line 75 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PLLI2SInitTypeDef::PLLI2SR

Specifies the division factor for I2S clock. This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI

Definition at line 71 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rcc_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC_PLLSAIInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLSAIInitTypeDef Struct Reference
RCCEx Exported Types

PLLSAI Clock structure definition. More...

#include <stm32f7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLLSAIN
uint32_t | PLLSAIQ
uint32_t | PLLSAIR
uint32_t | PLLSAIP

Detailed Description

PLLSAI Clock structure definition.

Definition at line 87 of file stm32f7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIN

Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC

Definition at line 89 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIP

Specifies the division factor for 48MHz clock. This parameter must be a value of RCCEx PLLSAIP Clock Divider This parameter will be used only when PLLSAI is disabled

Definition at line 101 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIQ

Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC

Definition at line 93 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIR

specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC

Definition at line 97 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rcc_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32f7xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
RCC_PLLI2SInitTypeDef PLLI2S
RCC_PLLSAIInitTypeDef PLLSAI
uint32_t | PLLI2SDivQ
uint32_t | PLLSAIDivQ
uint32_t | PLLSAIDivR
uint32_t | RTCClockSelection
uint32_t | I2sClockSelection
uint32_t | TIMPresSelection
uint32_t | Sai1ClockSelection
uint32_t | Sai2ClockSelection
uint32_t | Usart1ClockSelection
uint32_t | Usart2ClockSelection
uint32_t | Usart3ClockSelection
uint32_t | Uart4ClockSelection
uint32_t | Uart5ClockSelection
uint32_t | Usart6ClockSelection
uint32_t | Uart7ClockSelection
uint32_t | Uart8ClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c2ClockSelection
uint32_t | I2c3ClockSelection
uint32_t | I2c4ClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | CecClockSelection
uint32_t | Clk48ClockSelection
uint32_t | Sdmmc1ClockSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 109 of file stm32f7xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::CecClockSelection

CEC clock source This parameter can be a value of RCCEx CEC Clock Source

Definition at line 185 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Clk48ClockSelection

Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC This parameter can be a value of RCCEx CLK48 Clock Source

Definition at line 188 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

I2C1 clock source This parameter can be a value of RCCEx I2C1 Clock Source

Definition at line 170 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c2ClockSelection

I2C2 clock source This parameter can be a value of RCCEx I2C2 Clock Source

Definition at line 173 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c3ClockSelection

I2C3 clock source This parameter can be a value of RCCEx I2C3 Clock Source

Definition at line 176 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c4ClockSelection

I2C4 clock source This parameter can be a value of RCCEx I2C4 Clock Source

Definition at line 179 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2sClockSelection

Specifies I2S Clock source Selection. This parameter can be a value of RCCEx I2S Clock Source

Definition at line 134 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source This parameter can be a value of RCCEx LPTIM1 Clock Source

Definition at line 182 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of RCC Periph Clock Selection

Definition at line 111 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLLI2SInitTypeDef RCC_PeriphCLKInitTypeDef::PLLI2S

PLL I2S structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI

Definition at line 114 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PLLI2SDivQ

Specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between Min_Data = 1 and Max_Data = 32 This parameter will be used only when PLLI2S is selected as Clock Source SAI

Definition at line 120 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLLSAIInitTypeDef RCC_PeriphCLKInitTypeDef::PLLSAI

PLL SAI structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC

Definition at line 117 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PLLSAIDivQ

Specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between Min_Data = 1 and Max_Data = 32 This parameter will be used only when PLLSAI is selected as Clock Source SAI

Definition at line 124 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PLLSAIDivR

Specifies the PLLSAI division factor for LTDC clock. This parameter must be one value of RCCEx PLLSAI DIVR

Definition at line 128 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC Clock source Selection. This parameter can be a value of RCC RTC Clock Source

Definition at line 131 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai1ClockSelection

Specifies SAI1 Clock Prescalers Selection This parameter can be a value of RCCEx SAI1 Clock Source

Definition at line 140 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai2ClockSelection

Specifies SAI2 Clock Prescalers Selection This parameter can be a value of RCCEx SAI2 Clock Source

Definition at line 143 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection

SDMMC1 clock source This parameter can be a value of RCCEx SDMMC1 Clock Source

Definition at line 191 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::TIMPresSelection

Specifies TIM Clock Prescalers Selection. This parameter can be a value of RCCEx TIM Prescaler Selection

Definition at line 137 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart4ClockSelection

UART4 clock source This parameter can be a value of RCCEx UART4 Clock Source

Definition at line 155 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart5ClockSelection

UART5 clock source This parameter can be a value of RCCEx UART5 Clock Source

Definition at line 158 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart7ClockSelection

UART7 clock source This parameter can be a value of RCCEx UART7 Clock Source

Definition at line 164 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart8ClockSelection

UART8 clock source This parameter can be a value of RCCEx UART8 Clock Source

Definition at line 167 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

USART1 clock source This parameter can be a value of RCCEx USART1 Clock Source

Definition at line 146 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart2ClockSelection

USART2 clock source This parameter can be a value of RCCEx USART2 Clock Source

Definition at line 149 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart3ClockSelection

USART3 clock source This parameter can be a value of RCCEx USART3 Clock Source

Definition at line 152 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart6ClockSelection

USART6 clock source This parameter can be a value of RCCEx USART6 Clock Source

Definition at line 161 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rcc_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Periph Clock Selection

Defines
RCC Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
#define | RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
#define | RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
#define | RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
#define | RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
#define | RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
#define | RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
#define | RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
#define | RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
#define | RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
#define | RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
#define | RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
#define | RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
#define | RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
#define | RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
#define | RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
#define | RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
#define | RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
#define | RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
#define | RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
#define | RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)

Define Documentation

#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)

Definition at line 228 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)

Definition at line 227 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)

Definition at line 220 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)

Definition at line 221 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)

Definition at line 222 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)

Definition at line 223 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)

Definition at line 206 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)

Definition at line 224 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)

Definition at line 231 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)

Definition at line 211 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)

Definition at line 225 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and SAI_GetInputClock().

#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)

Definition at line 226 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and SAI_GetInputClock().

#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)

Definition at line 229 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)

Definition at line 230 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)

Definition at line 210 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)

Definition at line 215 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)

Definition at line 216 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)

Definition at line 218 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)

Definition at line 219 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)

Definition at line 212 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)

Definition at line 213 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)

Definition at line 214 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)

Definition at line 217 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx PLLI2SP Clock Divider

Defines
RCCEx PLLI2SP Clock Divider
RCCEx Exported Constants

Defines

#define | RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000)
#define | RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001)
#define | RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002)
#define | RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003)

Define Documentation

#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000)

Definition at line 240 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001)

Definition at line 241 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002)

Definition at line 242 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003)

Definition at line 243 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx PLLSAIP Clock Divider

Defines
RCCEx PLLSAIP Clock Divider
RCCEx Exported Constants

Defines

#define | RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
#define | RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
#define | RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
#define | RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)

Define Documentation

#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)

Definition at line 251 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)

Definition at line 252 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)

Definition at line 253 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)

Definition at line 254 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx PLLSAI DIVR

Defines
RCCEx PLLSAI DIVR
RCCEx Exported Constants

Defines

#define | RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
#define | RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
#define | RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
#define | RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR

Define Documentation

#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR

Definition at line 265 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)

Definition at line 262 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0

Definition at line 263 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1

Definition at line 264 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx I2S Clock Source

Defines
RCCEx I2S Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
#define | RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC

Define Documentation

#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC

Definition at line 274 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)

Definition at line 273 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32F745xx HAL User Manual: RCCEx SAI1 Clock Source

Defines
RCCEx SAI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
#define | RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1

Define Documentation

#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1

Definition at line 286 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0

Definition at line 285 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)

Definition at line 284 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32F745xx HAL User Manual: RCCEx SAI2 Clock Source

Defines
RCCEx SAI2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
#define | RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
#define | RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1

Define Documentation

#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1

Definition at line 297 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0

Definition at line 296 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)

Definition at line 295 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32F745xx HAL User Manual: RCCEx CEC Clock Source

Defines
RCCEx CEC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
#define | RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/

Define Documentation

#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/

Definition at line 306 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)

Definition at line 305 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx USART1 Clock Source

Defines
RCCEx USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL

Define Documentation

#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1

Definition at line 316 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL

Definition at line 317 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)

Definition at line 314 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0

Definition at line 315 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx USART2 Clock Source

Defines
RCCEx USART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL

Define Documentation

#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1

Definition at line 327 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL

Definition at line 328 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 325 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0

Definition at line 326 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx USART3 Clock Source

Defines
RCCEx USART3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL

Define Documentation

#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1

Definition at line 338 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL

Definition at line 339 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 336 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0

Definition at line 337 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx UART4 Clock Source

Defines
RCCEx UART4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
#define | RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
#define | RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL

Define Documentation

#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1

Definition at line 349 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL

Definition at line 350 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 347 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0

Definition at line 348 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx UART5 Clock Source

Defines
RCCEx UART5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
#define | RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
#define | RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL

Define Documentation

#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1

Definition at line 360 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL

Definition at line 361 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 358 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0

Definition at line 359 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx USART6 Clock Source

Defines
RCCEx USART6 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
#define | RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
#define | RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL

Define Documentation

#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1

Definition at line 371 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL

Definition at line 372 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)

Definition at line 369 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0

Definition at line 370 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx UART7 Clock Source

Defines
RCCEx UART7 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
#define | RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
#define | RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL

Define Documentation

#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1

Definition at line 382 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL

Definition at line 383 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 380 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0

Definition at line 381 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx UART8 Clock Source

Defines
RCCEx UART8 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
#define | RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
#define | RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL

Define Documentation

#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1

Definition at line 393 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL

Definition at line 394 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 391 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0

Definition at line 392 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx I2C1 Clock Source

Defines
RCCEx I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1

Define Documentation

#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1

Definition at line 404 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 402 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0

Definition at line 403 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx I2C2 Clock Source

Defines
RCCEx I2C2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1

Define Documentation

#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1

Definition at line 414 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 412 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0

Definition at line 413 of file stm32f7xx_hal_rcc_ex.h.

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STM32F745xx HAL User Manual: RCCEx I2C3 Clock Source

Defines
RCCEx I2C3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1

Define Documentation

#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1

Definition at line 425 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 423 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0

Definition at line 424 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx I2C4 Clock Source

Defines
RCCEx I2C4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
#define | RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1

Define Documentation

#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1

Definition at line 435 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)

Definition at line 433 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0

Definition at line 434 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx LPTIM1 Clock Source

Defines
RCCEx LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL

Define Documentation

#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1

Definition at line 445 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL

Definition at line 446 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0

Definition at line 444 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)

Definition at line 443 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx CLK48 Clock Source

Defines
RCCEx CLK48 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL

Define Documentation

#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)

Definition at line 455 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL

Definition at line 456 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx TIM Prescaler Selection

Defines
RCCEx TIM Prescaler Selection
RCCEx Exported Constants

Defines

#define | RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
#define | RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE

Define Documentation

#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE

Definition at line 465 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)

Definition at line 464 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx SDMMC1 Clock Source

Defines
RCCEx SDMMC1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
#define | RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL

Define Documentation

#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)

Definition at line 473 of file stm32f7xx_hal_rcc_ex.h.

#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL

Definition at line 474 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx_Peripheral_Clock_Enable_Disable

Defines
RCCEx_Peripheral_Clock_Enable_Disable
RCCEx Exported Macros

Enables or disables the AHB/APB peripheral clock. More...

Defines

#define | __HAL_RCC_BKPSRAM_CLK_ENABLE()
Enables or disables the AHB1 peripheral clock.
#define | __HAL_RCC_DTCMRAMEN_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_DMA2D_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_HS_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_GPIOI_CLK_ENABLE()
#define | __HAL_RCC_GPIOJ_CLK_ENABLE()
#define | __HAL_RCC_GPIOK_CLK_ENABLE()
#define | __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
#define | __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
#define | __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
#define | __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define | __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
#define | __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
#define | __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
#define | __HAL_RCC_ETHMAC_CLK_ENABLE()
Enable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_CLK_ENABLE()
#define | __HAL_RCC_ETHMACRX_CLK_ENABLE()
#define | __HAL_RCC_ETHMACPTP_CLK_ENABLE()
#define | __HAL_RCC_ETH_CLK_ENABLE()
#define | __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Disable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
#define | __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
#define | __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
#define | __HAL_RCC_ETH_CLK_DISABLE()
#define | __HAL_RCC_DCMI_CLK_ENABLE()
Enable or disable the AHB2 peripheral clock.
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
#define | __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
#define | __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
#define | __HAL_RCC_FMC_CLK_ENABLE()
Enables or disables the AHB3 peripheral clock.
#define | __HAL_RCC_QSPI_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
#define | __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
#define | __HAL_RCC_TIM2_CLK_ENABLE()
Enable or disable the Low Speed APB (APB1) peripheral clock.
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_SPDIFRX_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_I2C4_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_CAN2_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_DAC_CLK_ENABLE()
#define | __HAL_RCC_UART7_CLK_ENABLE()
#define | __HAL_RCC_UART8_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define | __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#define | __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#define | __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#define | __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
#define | __HAL_RCC_TIM1_CLK_ENABLE()
Enable or disable the High Speed APB (APB2) peripheral clock.
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_ADC2_CLK_ENABLE()
#define | __HAL_RCC_ADC3_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SPI4_CLK_ENABLE()
#define | __HAL_RCC_TIM9_CLK_ENABLE()
#define | __HAL_RCC_TIM10_CLK_ENABLE()
#define | __HAL_RCC_TIM11_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_SPI6_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define | __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
#define | __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define | __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
#define | __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
#define | __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))

Detailed Description

Enables or disables the AHB/APB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 1189 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1071 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))

Definition at line 1190 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1079 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))

Definition at line 1191 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1087 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))

Definition at line 636 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Enables or disables the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 500 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))

Definition at line 1027 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 958 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))

Definition at line 1028 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 966 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))

Definition at line 1029 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 974 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))

Definition at line 1030 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 982 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))

Definition at line 736 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Enable or disable the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 711 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 638 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 516 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))

Definition at line 639 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 524 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))

Definition at line 637 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 508 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_CLK_DISABLE ( )
Value:
do {                             \
                                      __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
                                      __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
                                      __HAL_RCC_ETHMAC_CLK_DISABLE();      \
                                     } while(0)

Definition at line 700 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_CLK_ENABLE ( )
Value:
do {                            \
                                     __HAL_RCC_ETHMAC_CLK_ENABLE();      \
                                     __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
                                     __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
                                    } while(0)

Definition at line 688 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))

Disable ETHERNET clock.

Definition at line 696 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Enable ETHERNET clock.

Definition at line 656 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))

Definition at line 699 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 680 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))

Definition at line 698 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 672 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))

Definition at line 697 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 664 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))

Definition at line 782 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Enables or disables the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 766 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 642 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 548 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 643 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 556 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 644 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 564 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))

Definition at line 645 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 572 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))

Definition at line 646 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 580 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))

Definition at line 647 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 588 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))

Definition at line 648 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 596 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 649 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 604 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))

Definition at line 650 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 612 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))

Definition at line 651 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 620 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))

Definition at line 652 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 628 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 1023 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 926 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 1024 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 934 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))

Definition at line 1025 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 942 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))

Definition at line 1026 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 950 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))

Definition at line 1015 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 862 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CLK_DISABLE ( ) (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))

Definition at line 783 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 774 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))

Definition at line 737 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 719 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))

Definition at line 1200 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1159 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))

Definition at line 1201 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1167 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))

Definition at line 1192 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1095 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))

Definition at line 1018 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 886 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 1193 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1103 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 1016 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 870 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))

Definition at line 1017 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 878 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))

Definition at line 1194 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1111 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))

Definition at line 1198 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1143 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))

Definition at line 1199 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1151 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))

Definition at line 1196 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1127 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 1197 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1135 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))

Definition at line 1012 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 838 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))

Definition at line 1013 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 846 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))

Definition at line 1014 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 854 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 1185 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1039 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

Definition at line 1006 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 790 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

Definition at line 1007 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 798 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))

Definition at line 1008 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 806 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 1009 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 814 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))

Definition at line 1010 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 822 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))

Definition at line 1011 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 830 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))

Definition at line 1186 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1047 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 1195 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1119 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))

Definition at line 1021 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 910 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))

Definition at line 1022 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 918 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))

Definition at line 1031 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 990 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))

Definition at line 1032 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 998 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 1187 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1055 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 1019 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 894 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))

Definition at line 1020 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 902 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 1188 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 1063 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE ( ) (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))

Definition at line 739 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
                                        UNUSED(tmpreg); \
                                        __HAL_RCC_SYSCFG_CLK_ENABLE();\
                                      } while(0)

Definition at line 727 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))

Definition at line 640 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 532 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))

Definition at line 641 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 540 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Clock Enable Disable Status

Defines
Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the AHB/APB peripheral clock. More...

Defines

#define | __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Get the enable or disable status of the AHB1 peripheral clock.
#define | __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
#define | __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
#define | __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
#define | __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Enable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
#define | __HAL_RCC_ETH_IS_CLK_ENABLED()
#define | __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Disable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
#define | __HAL_RCC_ETH_IS_CLK_DISABLED()
#define | __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Get the enable or disable status of the AHB2 peripheral clock.
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
#define | __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
#define | __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Get the enable or disable status of the AHB3 peripheral clock.
#define | __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
#define | __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Get the enable or disable status of the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define | __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define | __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
#define | __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define | __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
#define | __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define | __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
#define | __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define | __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#define | __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
#define | __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#define | __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#define | __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
#define | __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
#define | __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Get the enable or disable status of the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define | __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
#define | __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
#define | __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
#define | __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define | __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
#define | __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#define | __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
#define | __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
#define | __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
#define | __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
#define | __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
#define | __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB/APB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

Definition at line 1401 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

Definition at line 1381 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)

Definition at line 1402 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)

Definition at line 1382 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)

Definition at line 1403 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)

Definition at line 1383 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)

Definition at line 1241 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)

Get the enable or disable status of the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1223 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)

Definition at line 1365 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)

Definition at line 1337 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)

Definition at line 1366 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)

Definition at line 1338 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)

Definition at line 1367 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)

Definition at line 1339 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)

Definition at line 1368 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)

Definition at line 1340 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)

Definition at line 1289 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)

Get the enable or disable status of the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1285 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)

Definition at line 1243 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)

Definition at line 1225 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)

Definition at line 1244 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)

Definition at line 1226 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)

Definition at line 1242 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)

Definition at line 1224 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_IS_CLK_DISABLED ( )
Value:
(__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
                                                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())

Definition at line 1276 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_IS_CLK_ENABLED ( )
Value:
(__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
                                                                                __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())

Definition at line 1265 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)

Disable ETHERNET clock.

Definition at line 1272 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)

Enable ETHERNET clock.

Definition at line 1261 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)

Definition at line 1275 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)

Definition at line 1264 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)

Definition at line 1274 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)

Definition at line 1263 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)

Definition at line 1273 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)

Definition at line 1262 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)

Definition at line 1308 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)

Get the enable or disable status of the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1305 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)

Definition at line 1247 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)

Definition at line 1229 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)

Definition at line 1248 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)

Definition at line 1230 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)

Definition at line 1249 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)

Definition at line 1231 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)

Definition at line 1250 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)

Definition at line 1232 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)

Definition at line 1251 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)

Definition at line 1233 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)

Definition at line 1252 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)

Definition at line 1234 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)

Definition at line 1253 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)

Definition at line 1235 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)

Definition at line 1254 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)

Definition at line 1236 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)

Definition at line 1255 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)

Definition at line 1237 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)

Definition at line 1256 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)

Definition at line 1238 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)

Definition at line 1257 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)

Definition at line 1239 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

Definition at line 1361 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

Definition at line 1333 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)

Definition at line 1362 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)

Definition at line 1334 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)

Definition at line 1363 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)

Definition at line 1335 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)

Definition at line 1364 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)

Definition at line 1336 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)

Definition at line 1353 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)

Definition at line 1325 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_DISABLED ( ) ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)

Definition at line 1309 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)

Definition at line 1306 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)

Definition at line 1290 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)

Definition at line 1286 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)

Definition at line 1412 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)

Definition at line 1392 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)

Definition at line 1413 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)

Definition at line 1393 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)

Definition at line 1404 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)

Definition at line 1384 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)

Definition at line 1356 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)

Definition at line 1328 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

Definition at line 1405 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

Definition at line 1385 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)

Definition at line 1354 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)

Definition at line 1326 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)

Definition at line 1355 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)

Definition at line 1327 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)

Definition at line 1406 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)

Definition at line 1386 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)

Definition at line 1410 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)

Definition at line 1390 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)

Definition at line 1411 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)

Definition at line 1391 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)

Definition at line 1408 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)

Definition at line 1388 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)

Definition at line 1409 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)

Definition at line 1389 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)

Definition at line 1350 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)

Definition at line 1322 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)

Definition at line 1351 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)

Definition at line 1323 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)

Definition at line 1352 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)

Definition at line 1324 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)

Definition at line 1397 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1377 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)

Definition at line 1344 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1316 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)

Definition at line 1345 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)

Definition at line 1317 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)

Definition at line 1346 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)

Definition at line 1318 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)

Definition at line 1347 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)

Definition at line 1319 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)

Definition at line 1348 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)

Definition at line 1320 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)

Definition at line 1349 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)

Definition at line 1321 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)

Definition at line 1398 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)

Definition at line 1378 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)

Definition at line 1407 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)

Definition at line 1387 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)

Definition at line 1359 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)

Definition at line 1331 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)

Definition at line 1360 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)

Definition at line 1332 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)

Definition at line 1369 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)

Definition at line 1341 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)

Definition at line 1370 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)

Definition at line 1342 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Definition at line 1399 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

Definition at line 1379 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

Definition at line 1357 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

Definition at line 1329 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)

Definition at line 1358 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)

Definition at line 1330 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)

Definition at line 1400 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)

Definition at line 1380 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED ( ) ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)

Definition at line 1291 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)

Definition at line 1287 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)

Definition at line 1245 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)

Definition at line 1227 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)

Definition at line 1246 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)

Definition at line 1228 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Force Release Peripheral Reset

Defines
RCCEx Force Release Peripheral Reset
RCCEx Exported Macros

Forces or releases AHB/APB peripheral reset. More...

Defines

#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Force or release AHB1 peripheral reset.
#define | __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
#define | __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
#define | __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
#define | __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
#define | __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
#define | __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
#define | __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
#define | __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
#define | __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
#define | __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
#define | __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
#define | __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Force or release AHB2 peripheral reset.
#define | __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
#define | __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
#define | __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
#define | __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Force or release AHB3 peripheral reset.
#define | __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define | __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Force or release APB1 peripheral reset.
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
#define | __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
#define | __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
#define | __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
#define | __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define | __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
#define | __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
#define | __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
#define | __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Force or release APB2 peripheral reset.
#define | __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
#define | __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
#define | __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
#define | __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
#define | __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
#define | __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
#define | __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
#define | __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
#define | __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))

Detailed Description

Forces or releases AHB/APB peripheral reset.

Define Documentation

#define __HAL_RCC_ADC_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))

Definition at line 1553 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))

Definition at line 1572 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AHB2_FORCE_RESET ( ) (RCC->AHB2RSTR = 0xFFFFFFFF)

Force or release AHB2 peripheral reset.

Definition at line 1462 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( ) (RCC->AHB2RSTR = 0x00)

Definition at line 1467 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_FORCE_RESET ( ) (RCC->AHB3RSTR = 0xFFFFFFFF)

Force or release AHB3 peripheral reset.

Definition at line 1481 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( ) (RCC->AHB3RSTR = 0x00)

Definition at line 1485 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CAN1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))

Definition at line 1512 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))

Definition at line 1540 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))

Definition at line 1513 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))

Definition at line 1541 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))

Definition at line 1514 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))

Definition at line 1542 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))

Definition at line 1515 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))

Definition at line 1543 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))

Definition at line 1463 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))

Definition at line 1468 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

Force or release AHB1 peripheral reset.

Definition at line 1428 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))

Definition at line 1444 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))

Definition at line 1429 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))

Definition at line 1445 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))

Definition at line 1430 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))

Definition at line 1446 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))

Definition at line 1482 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))

Definition at line 1486 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))

Definition at line 1432 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))

Definition at line 1448 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))

Definition at line 1433 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))

Definition at line 1449 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))

Definition at line 1434 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))

Definition at line 1450 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))

Definition at line 1435 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))

Definition at line 1451 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))

Definition at line 1436 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))

Definition at line 1452 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))

Definition at line 1437 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))

Definition at line 1453 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))

Definition at line 1438 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))

Definition at line 1454 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))

Definition at line 1439 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))

Definition at line 1455 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))

Definition at line 1440 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))

Definition at line 1456 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))

Definition at line 1441 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))

Definition at line 1457 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))

Definition at line 1442 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))

Definition at line 1458 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))

Definition at line 1508 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

Definition at line 1536 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))

Definition at line 1509 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))

Definition at line 1537 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))

Definition at line 1510 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))

Definition at line 1538 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))

Definition at line 1511 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))

Definition at line 1539 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))

Definition at line 1500 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))

Definition at line 1528 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_FORCE_RESET ( ) (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))

Definition at line 1483 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_RELEASE_RESET ( ) (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))

Definition at line 1487 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))

Definition at line 1464 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))

Definition at line 1469 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))

Definition at line 1562 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))

Definition at line 1581 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))

Definition at line 1563 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))

Definition at line 1582 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))

Definition at line 1554 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))

Definition at line 1573 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))

Definition at line 1503 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))

Definition at line 1531 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))

Definition at line 1555 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))

Definition at line 1574 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))

Definition at line 1501 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))

Definition at line 1529 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))

Definition at line 1502 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))

Definition at line 1530 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))

Definition at line 1556 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))

Definition at line 1575 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))

Definition at line 1560 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))

Definition at line 1579 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))

Definition at line 1561 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))

Definition at line 1580 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))

Definition at line 1558 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))

Definition at line 1577 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))

Definition at line 1559 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))

Definition at line 1578 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))

Definition at line 1497 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))

Definition at line 1525 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))

Definition at line 1498 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))

Definition at line 1526 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))

Definition at line 1499 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))

Definition at line 1527 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))

Force or release APB2 peripheral reset.

Definition at line 1549 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))

Definition at line 1568 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))

Force or release APB1 peripheral reset.

Definition at line 1491 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))

Definition at line 1519 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))

Definition at line 1492 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))

Definition at line 1520 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))

Definition at line 1493 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))

Definition at line 1521 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))

Definition at line 1494 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))

Definition at line 1522 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))

Definition at line 1495 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))

Definition at line 1523 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))

Definition at line 1496 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))

Definition at line 1524 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))

Definition at line 1550 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))

Definition at line 1569 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))

Definition at line 1557 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))

Definition at line 1576 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))

Definition at line 1506 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))

Definition at line 1534 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))

Definition at line 1507 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))

Definition at line 1535 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))

Definition at line 1516 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))

Definition at line 1544 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))

Definition at line 1517 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))

Definition at line 1545 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))

Definition at line 1551 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

Definition at line 1570 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))

Definition at line 1504 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))

Definition at line 1532 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))

Definition at line 1505 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))

Definition at line 1533 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))

Definition at line 1552 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))

Definition at line 1571 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_FORCE_RESET ( ) (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))

Definition at line 1465 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET ( ) (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))

Definition at line 1470 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))

Definition at line 1431 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))

Definition at line 1447 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Peripheral Clock Sleep Enable Disable

Defines
RCCEx Peripheral Clock Sleep Enable Disable
RCCEx Exported Macros

Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
#define | __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
#define | __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
#define | __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
#define | __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
#define | __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
#define | __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
#define | __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
#define | __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
#define | __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
#define | __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
#define | __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
#define | __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
#define | __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
#define | __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
#define | __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
#define | __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
#define | __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
#define | __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
#define | __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
#define | __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
#define | __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
#define | __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
#define | __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
#define | __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
#define | __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
#define | __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
#define | __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
#define | __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
#define | __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
#define | __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
#define | __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
#define | __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))

Detailed Description

Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))

Definition at line 1782 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))

Definition at line 1761 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))

Definition at line 1783 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))

Definition at line 1762 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))

Definition at line 1784 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))

Definition at line 1763 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))

Definition at line 1629 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))

Definition at line 1603 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))

Definition at line 1632 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))

Definition at line 1606 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))

Definition at line 1744 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))

Definition at line 1716 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))

Definition at line 1745 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))

Definition at line 1717 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))

Definition at line 1746 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))

Definition at line 1718 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))

Definition at line 1747 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))

Definition at line 1719 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))

Definition at line 1661 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1660 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))

Definition at line 1634 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

Definition at line 1608 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))

Definition at line 1635 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))

Definition at line 1609 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))

Definition at line 1633 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))

Definition at line 1607 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))

Definition at line 1636 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))

Definition at line 1610 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))

Definition at line 1639 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))

Definition at line 1613 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))

Definition at line 1638 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))

Definition at line 1612 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))

Definition at line 1637 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))

Definition at line 1611 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))

Definition at line 1628 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Definition at line 1602 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))

Definition at line 1684 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1683 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))

Definition at line 1642 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))

Definition at line 1616 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))

Definition at line 1643 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))

Definition at line 1617 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))

Definition at line 1644 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))

Definition at line 1618 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))

Definition at line 1645 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))

Definition at line 1619 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))

Definition at line 1646 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))

Definition at line 1620 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))

Definition at line 1647 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))

Definition at line 1621 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))

Definition at line 1648 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))

Definition at line 1622 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))

Definition at line 1649 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))

Definition at line 1623 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))

Definition at line 1650 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))

Definition at line 1624 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))

Definition at line 1651 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))

Definition at line 1625 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))

Definition at line 1652 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))

Definition at line 1626 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))

Definition at line 1740 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))

Definition at line 1712 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))

Definition at line 1741 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))

Definition at line 1713 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))

Definition at line 1742 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))

Definition at line 1714 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))

Definition at line 1743 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))

Definition at line 1715 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))

Definition at line 1732 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))

Definition at line 1704 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE ( ) (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))

Definition at line 1687 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

Definition at line 1686 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))

Definition at line 1664 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

Definition at line 1663 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))

Definition at line 1793 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))

Definition at line 1772 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))

Definition at line 1794 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))

Definition at line 1773 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))

Definition at line 1785 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))

Definition at line 1764 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))

Definition at line 1735 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))

Definition at line 1707 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))

Definition at line 1786 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))

Definition at line 1765 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))

Definition at line 1733 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))

Definition at line 1705 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))

Definition at line 1734 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))

Definition at line 1706 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))

Definition at line 1787 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))

Definition at line 1766 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))

Definition at line 1791 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))

Definition at line 1770 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))

Definition at line 1792 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))

Definition at line 1771 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))

Definition at line 1630 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))

Definition at line 1604 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))

Definition at line 1631 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))

Definition at line 1605 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))

Definition at line 1789 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))

Definition at line 1768 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))

Definition at line 1790 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))

Definition at line 1769 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))

Definition at line 1729 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))

Definition at line 1701 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))

Definition at line 1730 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))

Definition at line 1702 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))

Definition at line 1731 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))

Definition at line 1703 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))

Definition at line 1778 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1757 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))

Definition at line 1723 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1695 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))

Definition at line 1724 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))

Definition at line 1696 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))

Definition at line 1725 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))

Definition at line 1697 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))

Definition at line 1726 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))

Definition at line 1698 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))

Definition at line 1727 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))

Definition at line 1699 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))

Definition at line 1728 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))

Definition at line 1700 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))

Definition at line 1779 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))

Definition at line 1758 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))

Definition at line 1788 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))

Definition at line 1767 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))

Definition at line 1738 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))

Definition at line 1710 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))

Definition at line 1739 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))

Definition at line 1711 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))

Definition at line 1748 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))

Definition at line 1720 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))

Definition at line 1749 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))

Definition at line 1721 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))

Definition at line 1780 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))

Definition at line 1759 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))

Definition at line 1736 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))

Definition at line 1708 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))

Definition at line 1737 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))

Definition at line 1709 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))

Definition at line 1781 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))

Definition at line 1760 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE ( ) (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))

Definition at line 1667 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))

Definition at line 1666 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))

Definition at line 1640 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))

Definition at line 1614 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))

Definition at line 1641 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))

Definition at line 1615 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: AHB/APB Peripheral Clock Sleep Enable Disable Status

Defines
AHB/APB Peripheral Clock Sleep Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
#define | __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
#define | __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
#define | __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
#define | __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
#define | __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
#define | __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
#define | __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
#define | __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
#define | __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
#define | __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
#define | __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
#define | __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
#define | __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
#define | __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
#define | __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
#define | __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
#define | __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
#define | __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
#define | __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
#define | __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
#define | __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
#define | __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
#define | __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
#define | __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)

Definition at line 1998 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)

Definition at line 1977 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)

Definition at line 1999 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)

Definition at line 1978 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)

Definition at line 2000 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)

Definition at line 1979 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)

Definition at line 1845 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)

Definition at line 1819 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)

Definition at line 1848 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)

Definition at line 1822 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)

Definition at line 1960 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)

Definition at line 1932 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)

Definition at line 1961 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)

Definition at line 1933 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)

Definition at line 1962 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)

Definition at line 1934 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)

Definition at line 1963 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)

Definition at line 1935 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)

Definition at line 1877 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)

Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1876 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)

Definition at line 1850 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)

Definition at line 1824 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)

Definition at line 1851 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)

Definition at line 1825 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)

Definition at line 1849 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)

Definition at line 1823 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)

Definition at line 1852 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)

Definition at line 1826 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)

Definition at line 1855 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)

Definition at line 1829 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)

Definition at line 1854 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)

Definition at line 1828 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)

Definition at line 1853 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)

Definition at line 1827 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)

Definition at line 1844 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)

Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1818 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)

Definition at line 1900 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)

Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1899 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)

Definition at line 1858 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)

Definition at line 1832 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)

Definition at line 1859 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)

Definition at line 1833 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)

Definition at line 1860 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)

Definition at line 1834 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)

Definition at line 1861 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)

Definition at line 1835 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)

Definition at line 1862 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)

Definition at line 1836 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)

Definition at line 1863 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)

Definition at line 1837 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)

Definition at line 1864 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)

Definition at line 1838 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)

Definition at line 1865 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)

Definition at line 1839 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)

Definition at line 1866 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)

Definition at line 1840 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)

Definition at line 1867 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)

Definition at line 1841 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)

Definition at line 1868 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)

Definition at line 1842 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)

Definition at line 1956 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)

Definition at line 1928 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)

Definition at line 1957 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)

Definition at line 1929 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)

Definition at line 1958 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)

Definition at line 1930 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)

Definition at line 1959 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)

Definition at line 1931 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)

Definition at line 1948 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)

Definition at line 1920 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)

Definition at line 1903 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)

Definition at line 1902 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)

Definition at line 1880 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)

Definition at line 1879 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)

Definition at line 2009 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)

Definition at line 1988 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)

Definition at line 2010 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)

Definition at line 1989 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)

Definition at line 2001 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)

Definition at line 1980 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)

Definition at line 1951 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)

Definition at line 1923 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)

Definition at line 2002 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)

Definition at line 1981 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)

Definition at line 1949 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)

Definition at line 1921 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)

Definition at line 1950 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)

Definition at line 1922 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)

Definition at line 2003 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)

Definition at line 1982 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)

Definition at line 2007 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)

Definition at line 1986 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)

Definition at line 2008 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)

Definition at line 1987 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)

Definition at line 1846 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)

Definition at line 1820 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)

Definition at line 1847 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)

Definition at line 1821 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)

Definition at line 2005 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)

Definition at line 1984 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)

Definition at line 2006 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)

Definition at line 1985 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)

Definition at line 1945 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)

Definition at line 1917 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)

Definition at line 1946 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)

Definition at line 1918 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)

Definition at line 1947 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)

Definition at line 1919 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)

Definition at line 1994 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)

Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1973 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)

Definition at line 1939 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)

Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 1911 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)

Definition at line 1940 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)

Definition at line 1912 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)

Definition at line 1941 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)

Definition at line 1913 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)

Definition at line 1942 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)

Definition at line 1914 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)

Definition at line 1943 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)

Definition at line 1915 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)

Definition at line 1944 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)

Definition at line 1916 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)

Definition at line 1995 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)

Definition at line 1974 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)

Definition at line 2004 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)

Definition at line 1983 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)

Definition at line 1954 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)

Definition at line 1926 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)

Definition at line 1955 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)

Definition at line 1927 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)

Definition at line 1964 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)

Definition at line 1936 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)

Definition at line 1965 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)

Definition at line 1937 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)

Definition at line 1996 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)

Definition at line 1975 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)

Definition at line 1952 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)

Definition at line 1924 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)

Definition at line 1953 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)

Definition at line 1925 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)

Definition at line 1997 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)

Definition at line 1976 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)

Definition at line 1883 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)

Definition at line 1882 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)

Definition at line 1856 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)

Definition at line 1830 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)

Definition at line 1857 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)

Definition at line 1831 of file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Exported Macros

Modules | Defines
RCCEx Exported Macros
RCCEx

Modules

RCCEx_Peripheral_Clock_Enable_Disable

Enables or disables the AHB/APB peripheral clock.

Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB/APB peripheral clock.

RCCEx Force Release Peripheral Reset

Forces or releases AHB/APB peripheral reset.

RCCEx Peripheral Clock Sleep Enable Disable

Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.

AHB/APB Peripheral Clock Sleep Enable Disable Status

Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.

Defines

#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
#define | __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
Macros to Enable or Disable the PLLISAI.
#define | __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
#define | __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)
Macro to configure the PLLSAI clock multiplication and division factors.
#define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)
Macro to configure the PLLI2S clock multiplication and division factors.
#define | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Macro to configure the SAI clock Divider coming from PLLI2S.
#define | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Macro to configure the SAI clock Divider coming from PLLSAI.
#define | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
Macro to configure the LTDC clock Divider coming from PLLSAI.
#define | __HAL_RCC_SAI1_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
Macro to configure SAI1 clock source selection.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SAI2_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
Macro to configure SAI2 clock source selection.
#define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
Macro to get the SAI2 clock source.
#define | __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
Enable PLLSAI_RDY interrupt.
#define | __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Disable PLLSAI_RDY interrupt.
#define | __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
Clear the PLLSAI RDY interrupt pending bits.
#define | __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Check the PLLSAI RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Check PLLSAI RDY flag is set or not.
#define | __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
Macro to Get I2S clock source selection.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
macro to get the I2C3 clock source.
#define | __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
Macro to configure the I2C4 clock (I2C4CLK).
#define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
macro to get the I2C4 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
macro to get the UART5 clock source.
#define | __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
Macro to configure the USART6 clock (USART6CLK).
#define | __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
macro to get the USART6 clock source.
#define | __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
Macro to configure the UART7 clock (UART7CLK).
#define | __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
macro to get the UART7 clock source.
#define | __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
Macro to configure the UART8 clock (UART8CLK).
#define | __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
macro to get the UART8 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
macro to get the CEC clock source.
#define | __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
Macro to configure the CLK48 source (CLK48CLK).
#define | __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
macro to get the CLK48 source.
#define | __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Macro to configure the SDMMC1 clock (SDMMC1CLK).
#define | __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
macro to get the SDMMC1 clock source.

Define Documentation

#define __HAL_RCC_CEC_CONFIG ( __CEC_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))

Macro to configure the CEC clock (CECCLK).

Parameters:
__CEC_CLKSOURCE__,: specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock

Definition at line 2469 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CLK48_CONFIG ( __CLK48_SOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))

Macro to configure the CLK48 source (CLK48CLK).

Parameters:
__CLK48_SOURCE__,: specifies the CLK48 clock source. This parameter can be one of the following values:
  • RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
  • RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source

Definition at line 2486 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_CEC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))

macro to get the CEC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock

Definition at line 2477 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_CLK48_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))

macro to get the CLK48 source.

Return values:
The clock source can be one of the following values:
  • RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
  • RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source

Definition at line 2494 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))

Macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock

Definition at line 2214 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))

Macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock

Definition at line 2233 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))

macro to get the I2C3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock

Definition at line 2252 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))

macro to get the I2C4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock

Definition at line 2271 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2SCLKSOURCE ( ) (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))

Macro to Get I2S clock source selection.

Return values:
The clock source can be one of the following values:
  • RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
  • RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source

Definition at line 2195 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))

macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

Definition at line 2460 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI1 clock.

Definition at line 2137 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))

Macro to get the SAI2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI2 clock.

Definition at line 2165 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SDMMC1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))

macro to get the SDMMC1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
  • RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock

Definition at line 2511 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))

macro to get the UART4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2355 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART5_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))

macro to get the UART5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2376 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART7_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))

macro to get the UART7 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 2418 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_UART8_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))

macro to get the UART8 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 2439 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))

macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2292 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))

macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2313 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))

macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2334 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART6_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))

macro to get the USART6 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 2397 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1_CLKSOURCE__,: specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock

Definition at line 2205 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2_CLKSOURCE__,: specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock

Definition at line 2224 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C3_CONFIG ( __I2C3_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))

Macro to configure the I2C3 clock (I2C3CLK).

Parameters:
__I2C3_CLKSOURCE__,: specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock

Definition at line 2243 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C4_CONFIG ( __I2C4_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))

Macro to configure the I2C4 clock (I2C4CLK).

Parameters:
__I2C4_CLKSOURCE__,: specifies the I2C4 clock source. This parameter can be one of the following values:
  • RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock

Definition at line 2262 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters:
__LPTIM1_CLKSOURCE__,: specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

Definition at line 2450 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__,
 |  | __PLLI2SP__,
 |  | __PLLI2SQ__,
 |  | __PLLI2SR__
 | ) |
Value:
(RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
                               ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP))                    |\
                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))                    |\
                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))

Macro to configure the PLLI2S clock multiplication and division factors.

Note:
This macro must be used only when the PLLI2S is disabled.
PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API)
Parameters:
__PLLI2SN__,: specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note:
You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Parameters:
__PLLI2SP__,: specifies the division factor for SPDDIF-RX clock. This parameter can be a value of RCCEx PLLI2SP Clock Divider.
__PLLI2SQ__,: specifies the division factor for SAI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15.
__PLLI2SR__,: specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Note:
You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Definition at line 2081 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG ( __PLLI2SDivQ__ ) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))

Macro to configure the SAI clock Divider coming from PLLI2S.

Note:
This function must be called before enabling the PLLI2S.
Parameters:
__PLLI2SDivQ__,: specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__

Definition at line 2093 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_CLEAR_IT ( ) (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))

Clear the PLLSAI RDY interrupt pending bits.

Definition at line 2178 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_CONFIG | ( | __PLLSAIN__,
 |  | __PLLSAIP__,
 |  | __PLLSAIQ__,
 |  | __PLLSAIR__
 | ) |
Value:
(RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
                               ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP))                    |\
                               ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                    |\
                               ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))

Macro to configure the PLLSAI clock multiplication and division factors.

Note:
This function must be used only when the PLLSAI is disabled.
PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )
Parameters:
__PLLSAIN__,: specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note:
You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Parameters:
__PLLSAIP__,: specifies the division factor for USB, RNG, SDMMC clocks This parameter can be a value of RCCEx PLLSAIP Clock Divider.
__PLLSAIQ__,: specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.
__PLLSAIR__,: specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Definition at line 2058 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_DISABLE ( ) (RCC->CR &= ~(RCC_CR_PLLSAION))

Definition at line 2041 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_DISABLE_IT ( ) (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))

Disable PLLSAI_RDY interrupt.

Definition at line 2174 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_ENABLE ( ) (RCC->CR |= (RCC_CR_PLLSAION))

Macros to Enable or Disable the PLLISAI.

Note:
The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 2040 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_ENABLE_IT ( ) (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))

Enable PLLSAI_RDY interrupt.

Definition at line 2170 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_GET_FLAG ( ) ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))

Check PLLSAI RDY flag is set or not.

Return values:
The new state (TRUE or FALSE).

Definition at line 2188 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_GET_IT ( ) ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))

Check the PLLSAI RDY interrupt has occurred or not.

Return values:
The new state (TRUE or FALSE).

Definition at line 2183 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG ( __PLLSAIDivQ__ ) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))

Macro to configure the SAI clock Divider coming from PLLSAI.

Note:
This function must be called before enabling the PLLSAI.
Parameters:
__PLLSAIDivQ__,: specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__

Definition at line 2101 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG ( __PLLSAIDivR__ ) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))

Macro to configure the LTDC clock Divider coming from PLLSAI.

Note:
This function must be called before enabling the PLLSAI.
Parameters:
__PLLSAIDivR__,: specifies the PLLSAI division factor for LTDC clock . This parameter can be a value of RCCEx PLLSAI DIVR. LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__

Definition at line 2110 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __SOURCE__ ) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))

Macro to configure SAI1 clock source selection.

Note:
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
Parameters:
__SOURCE__,: specifies the SAI1 clock source. This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI1 clock.

Definition at line 2125 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI2_CONFIG ( __SOURCE__ ) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))

Macro to configure SAI2 clock source selection.

Note:
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
Parameters:
__SOURCE__,: specifies the SAI2 clock source. This parameter can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI2 clock.

Definition at line 2152 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SDMMC1_CONFIG ( __SDMMC1_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))

Macro to configure the SDMMC1 clock (SDMMC1CLK).

Parameters:
__SDMMC1_CLKSOURCE__,: specifies the SDMMC1 clock source. This parameter can be one of the following values:
  • RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
  • RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock

Definition at line 2503 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIMCLKPRESCALER ( __PRESC__ )
Value:
do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
                                                 RCC->DCKCFGR1 |= (__PRESC__);           \
                                                }while(0)

Macro to configure the Timers clocks prescalers.

Parameters:
__PRESC__ : specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
  • RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Definition at line 2033 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG ( __UART4_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))

Macro to configure the UART4 clock (UART4CLK).

Parameters:
__UART4_CLKSOURCE__,: specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2345 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART5_CONFIG ( __UART5_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))

Macro to configure the UART5 clock (UART5CLK).

Parameters:
__UART5_CLKSOURCE__,: specifies the UART5 clock source. This parameter can be one of the following values:
  • RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2366 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART7_CONFIG ( __UART7_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))

Macro to configure the UART7 clock (UART7CLK).

Parameters:
__UART7_CLKSOURCE__,: specifies the UART7 clock source. This parameter can be one of the following values:
  • RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 2408 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART8_CONFIG ( __UART8_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))

Macro to configure the UART8 clock (UART8CLK).

Parameters:
__UART8_CLKSOURCE__,: specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 2429 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1_CLKSOURCE__,: specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2282 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2_CLKSOURCE__,: specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2303 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3_CLKSOURCE__,: specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2324 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART6_CONFIG ( __USART6_CLKSOURCE__ ) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))

Macro to configure the USART6 clock (USART6CLK).

Parameters:
__USART6_CLKSOURCE__,: specifies the USART6 clock source. This parameter can be one of the following values:
  • RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 2387 of file stm32f7xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Exported Types

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00, HAL_RNG_STATE_READY = 0x01, HAL_RNG_STATE_BUSY = 0x02, HAL_RNG_STATE_TIMEOUT = 0x03,
HAL_RNG_STATE_ERROR = 0x04
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 67 of file stm32f7xx_hal_rng.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32f7xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
uint32_t | RandomNumber
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State

Detailed Description

Definition at line 84 of file stm32f7xx_hal_rng.h.

Field Documentation

RNG_TypeDef* RNG_HandleTypeDef::Instance

Register base address

Definition at line 86 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GetRandomNumber_IT(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 90 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

uint32_t RNG_HandleTypeDef::RandomNumber

Last Generated random number

Definition at line 88 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_GetRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

__IO HAL_RNG_StateTypeDef RNG_HandleTypeDef::State

RNG communication state

Definition at line 92 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rng.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 114 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 113 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 115 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 124 of file stm32f7xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 123 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 125 of file stm32f7xx_hal_rng.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__,: RNG handle
__FLAG__,: RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 181 of file stm32f7xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 221 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 159 of file stm32f7xx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 197 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 152 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 190 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT(), and HAL_RNG_GetRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__,: RNG Handle
__FLAG__,: RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 171 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 209 of file stm32f7xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)

Reset RNG handle state.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 145 of file stm32f7xx_hal_rng.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 156 of file stm32f7xx_hal_rng.c.

References HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 116 of file stm32f7xx_hal_rng.c.

References __HAL_RNG_ENABLE, HAL_RNG_MspInit(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Lock, and RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 204 of file stm32f7xx_hal_rng.c.

Referenced by HAL_RNG_DeInit().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 188 of file stm32f7xx_hal_rng.c.

Referenced by HAL_RNG_Init().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 464 of file stm32f7xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
Each time the random number data is read the RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit,: pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 244 of file stm32f7xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, HAL_GetTick(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and RNG_HandleTypeDef::State.

Referenced by HAL_RNG_GetRandomNumber().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 298 of file stm32f7xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_GetRandomNumber ( RNG_HandleTypeDef * hrng )

Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
Random value

Definition at line 391 of file stm32f7xx_hal_rng.c.

References HAL_RNG_GenerateRandomNumber(), and RNG_HandleTypeDef::RandomNumber.

uint32_t HAL_RNG_GetRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
32-bit random number

Definition at line 410 of file stm32f7xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 349 of file stm32f7xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 436 of file stm32f7xx_hal_rng.c.

References RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit,: generated random number.
Return values:
None

Definition at line 448 of file stm32f7xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 499 of file stm32f7xx_hal_rng.c.

References RNG_HandleTypeDef::State.

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STM32F745xx HAL User Manual: RNG Private Types

RNG Private Types
RNG
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Private Defines

RNG Private Defines
RNG
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Private Variables

RNG Private Variables
RNG
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2

Define Documentation

#define RNG_TIMEOUT_VALUE 2

Definition at line 79 of file stm32f7xx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)

Define Documentation

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                           ((FLAG) == RNG_FLAG_CECS) || \
                           ((FLAG) == RNG_FLAG_SECS))

Definition at line 318 of file stm32f7xx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 315 of file stm32f7xx_hal_rng.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Private Functions Prototypes

RNG Private Functions Prototypes
RNG
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Private Functions

RNG Private Functions
RNG
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC peripheral.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 280 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initializes the RTC peripheral.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 204 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, RTC_InitTypeDef::HourFormat, RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, RTC_HandleTypeDef::Lock, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_HandleTypeDef::State, and RTC_InitTypeDef::SynchPrediv.

__weak void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC MSP.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 401 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

__weak void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initializes the RTC MSP.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 385 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current date.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to Date structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 729 of file stm32f7xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current time.

Parameters:
hrtc,: RTC handle
sTime,: Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Return values:
HAL status

Definition at line 575 of file stm32f7xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current date.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 617 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current time.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • FORMAT_BIN: Binary data format
  • FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 440 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

__weak void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1352 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Alarm interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1311 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_IT, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactive the specified RTC Alarm.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1163 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC Alarm value and masks.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Date structure
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1260 of file stm32f7xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmA Polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1369 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • FORMAT_BIN: Binary data format
  • FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 784 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm with Interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • FORMAT_BIN: Binary data format
  • FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 973 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EXTI_LINE_ALARM_EVENT, RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1431 of file stm32f7xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Returns the RTC state.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL state

Definition at line 1477 of file stm32f7xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_Exported_Functions_Group1

Functions
RTC_Exported_Functions_Group1
RTC Exported Functions

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC peripheral.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 280 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initializes the RTC peripheral.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 204 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, RTC_InitTypeDef::HourFormat, RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, RTC_HandleTypeDef::Lock, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_HandleTypeDef::State, and RTC_InitTypeDef::SynchPrediv.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC MSP.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 401 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initializes the RTC MSP.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 385 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_Exported_Functions_Group2

Functions
RTC_Exported_Functions_Group2
RTC Exported Functions

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current date.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to Date structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 729 of file stm32f7xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current time.

Parameters:
hrtc,: RTC handle
sTime,: Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Return values:
HAL status

Definition at line 575 of file stm32f7xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current date.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 617 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current time.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • FORMAT_BIN: Binary data format
  • FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 440 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_Exported_Functions_Group3

Functions
RTC_Exported_Functions_Group3
RTC Exported Functions

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1352 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Alarm interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1311 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_IT, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactive the specified RTC Alarm.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1163 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC Alarm value and masks.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Date structure
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1260 of file stm32f7xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmA Polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1369 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • FORMAT_BIN: Binary data format
  • FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 784 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm with Interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • FORMAT_BIN: Binary data format
  • FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 973 of file stm32f7xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EXTI_LINE_ALARM_EVENT, RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_Exported_Functions_Group4

Functions
RTC_Exported_Functions_Group4
RTC Exported Functions

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1431 of file stm32f7xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_Exported_Functions_Group5

Functions
RTC_Exported_Functions_Group5
RTC Exported Functions

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Returns the RTC state.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL state

Definition at line 1477 of file stm32f7xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Exported Functions

Modules | Functions
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

RTC_Exported_Functions_Group1
RTC_Exported_Functions_Group2
RTC_Exported_Functions_Group3
RTC_Exported_Functions_Group4
RTC_Exported_Functions_Group5

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Converts from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1544 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Converts a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1526 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1494 of file stm32f7xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Exported Types

Data Structures | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
RTC Handle Structure definition. More...

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00, HAL_RTC_STATE_READY = 0x01, HAL_RTC_STATE_BUSY = 0x02, HAL_RTC_STATE_TIMEOUT = 0x03,
HAL_RTC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 65 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32f7xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutPolarity
uint32_t | OutPutType

Detailed Description

RTC Configuration Structure definition.

Definition at line 78 of file stm32f7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 83 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 80 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTCEx Output selection Definitions

Definition at line 89 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 92 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 95 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 86 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32f7xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint32_t | SubSeconds
uint8_t | TimeFormat
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 102 of file stm32f7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of RTC DayLight Saving Definitions

Definition at line 120 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 104 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 108 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 111 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of RTC Store Operation Definitions

Definition at line 123 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC Time SubSeconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 114 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 117 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32f7xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 131 of file stm32f7xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 139 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 136 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 133 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 142 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32f7xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 150 of file stm32f7xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 167 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 163 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC Alarm Date WeekDay Definitions

Definition at line 160 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC Alarm Mask Definitions

Definition at line 154 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 157 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 152 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32f7xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State

Detailed Description

RTC Handle Structure definition.

Definition at line 174 of file stm32f7xx_hal_rtc.h.

Field Documentation

RTC_InitTypeDef RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 178 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* RTC_HandleTypeDef::Instance

Register base address

Definition at line 176 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), HAL_RTCEx_WakeUpTimerIRQHandler(), and RTC_EnterInitMode().

HAL_LockTypeDef RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 180 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

__IO HAL_RTCStateTypeDef RTC_HandleTypeDef::State

Time communication state

Definition at line 182 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040)

Define Documentation

#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)

Definition at line 199 of file stm32f7xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)

Definition at line 198 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)

Definition at line 208 of file stm32f7xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)

Definition at line 209 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)

Definition at line 217 of file stm32f7xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */

Definition at line 218 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)

Definition at line 226 of file stm32f7xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Definition at line 227 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC DayLight Saving Definitions

Defines
RTC DayLight Saving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)

Definition at line 236 of file stm32f7xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)

Definition at line 237 of file stm32f7xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)

Definition at line 235 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Store Operation Definitions

Defines
RTC Store Operation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000)

Define Documentation

#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)

Definition at line 245 of file stm32f7xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)

Definition at line 246 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001)

Define Documentation

#define RTC_FORMAT_BCD ((uint32_t)0x000000001)

Definition at line 255 of file stm32f7xx_hal_rtc.h.

#define RTC_FORMAT_BIN ((uint32_t)0x000000000)

Definition at line 254 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04)

Definition at line 267 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08)

Definition at line 271 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12)

Definition at line 275 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)

Definition at line 265 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01)

Definition at line 264 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07)

Definition at line 270 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06)

Definition at line 269 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03)

Definition at line 266 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05)

Definition at line 268 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)

Definition at line 274 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10)

Definition at line 273 of file stm32f7xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)

Definition at line 272 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)

Definition at line 287 of file stm32f7xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)

Definition at line 283 of file stm32f7xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)

Definition at line 288 of file stm32f7xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Definition at line 289 of file stm32f7xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)

Definition at line 286 of file stm32f7xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)

Definition at line 284 of file stm32f7xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)

Definition at line 285 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Alarm Date WeekDay Definitions

Defines
RTC Alarm Date WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)

Definition at line 297 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)

Definition at line 298 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Alarm Mask Definitions

Defines
RTC Alarm Mask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080)

Define Documentation

#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)

Definition at line 311 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 307 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 308 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 309 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)

Definition at line 306 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 310 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 319 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 320 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 328 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)

SS[14:0] are compared and must match to activate alarm.

Definition at line 359 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

Definition at line 357 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 331 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

Definition at line 349 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

Definition at line 351 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)

SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared

Definition at line 353 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

Definition at line 355 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

Definition at line 333 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

Definition at line 335 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

Definition at line 337 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

Definition at line 339 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

Definition at line 341 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared

Definition at line 343 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

Definition at line 345 of file stm32f7xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

Definition at line 347 of file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Define Documentation

#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)

Definition at line 370 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)

Definition at line 371 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */

Definition at line 372 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper().

#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)

Definition at line 373 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper().

#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)

Definition at line 374 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper().

#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Definition at line 375 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper().

#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)

Definition at line 368 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)

Definition at line 369 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Define Documentation

#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)

Definition at line 392 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Definition at line 399 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)

Definition at line 391 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)

Definition at line 398 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)

Definition at line 393 of file stm32f7xx_hal_rtc.h.

#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)

Definition at line 395 of file stm32f7xx_hal_rtc.h.

#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)

Definition at line 389 of file stm32f7xx_hal_rtc.h.

#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)

Definition at line 383 of file stm32f7xx_hal_rtc.h.

#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)

Definition at line 394 of file stm32f7xx_hal_rtc.h.

#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)

Definition at line 396 of file stm32f7xx_hal_rtc.h.

#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)

Definition at line 386 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)

Definition at line 385 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)

Definition at line 384 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)

Definition at line 388 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)

Definition at line 387 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)

Definition at line 390 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)

Definition at line 397 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 523 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 488 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 477 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 606 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 558 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 570 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 546 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 582 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 594 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 552 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 564 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 540 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 576 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 588 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None.

Definition at line 612 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 600 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 512 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 499 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 534 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 452 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 445 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 466 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 459 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

Reset RTC handle state.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 417 of file stm32f7xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCA;   \
                            (__HANDLE__)->Instance->WPR = 0x53;   \
                          } while(0)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 424 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFF;   \
                          } while(0)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 435 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)

Define Documentation

#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)

Definition at line 694 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 700 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)

Definition at line 695 of file stm32f7xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)

Definition at line 696 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000

Definition at line 698 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)

Definition at line 693 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_HOUR_FORMAT(__FORMAT__)
#define | IS_RTC_OUTPUT_POL(__POL__)
#define | IS_RTC_OUTPUT_TYPE(__TYPE__)
#define | IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F)
#define | IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7FFF)
#define | IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))
#define | IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23)
#define | IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59)
#define | IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59)
#define | IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(__SAVE__)
#define | IS_RTC_STORE_OPERATION(__OPERATION__)
#define | IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99)
#define | IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))
#define | IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))
#define | IS_RTC_WEEKDAY(__WEEKDAY__)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__)

Define Documentation

#define IS_RTC_ALARM ( __ALARM__ ) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))

Definition at line 754 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( __DATE__ ) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))

Definition at line 743 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                                ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 751 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( __WEEKDAY__ )
Value:
(((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
                                                        ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
                                                        ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
                                                        ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
                                                        ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))

Definition at line 744 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( __MASK__ ) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)

Definition at line 753 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( __MASK__ )
Value:
(((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 756 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)0x00007FFF)

Definition at line 755 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( __PREDIV__ ) ((__PREDIV__) <= (uint32_t)0x7F)

Definition at line 719 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( __DATE__ ) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))

Definition at line 734 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( __SAVE__ )
Value:
(((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 726 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( __FORMAT__ ) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))

Definition at line 731 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))

Definition at line 721 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= (uint32_t)23)

Definition at line 722 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( __FORMAT__ )
Value:
(((__FORMAT__) == RTC_HOURFORMAT_12) || \
                                        ((__FORMAT__) == RTC_HOURFORMAT_24))

Definition at line 713 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( __PM__ ) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))

Definition at line 725 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= (uint32_t)59)

Definition at line 723 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( __MONTH__ ) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))

Definition at line 733 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT_POL ( __POL__ )
Value:
(((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \
                                        ((__POL__) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 715 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( __TYPE__ )
Value:
(((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                        ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 717 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= (uint32_t)59)

Definition at line 724 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( __OPERATION__ )
Value:
(((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
                                               ((__OPERATION__) == RTC_STOREOPERATION_SET))

Definition at line 729 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( __PREDIV__ ) ((__PREDIV__) <= (uint32_t)0x7FFF)

Definition at line 720 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( __WEEKDAY__ )
Value:
(((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
                                     ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
                                     ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
                                     ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
                                     ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
                                     ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
                                     ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))

Definition at line 735 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= (uint32_t)99)

Definition at line 732 of file stm32f7xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Converts from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1544 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Converts a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1526 of file stm32f7xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1494 of file stm32f7xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC TimeStamp and Tamper functions

Functions
RTC TimeStamp and Tamper functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Sets Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper3 Polling.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivates internal TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 343 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivates Tamper.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Tamper,: Selected tamper pin. This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
Return values:
HAL status

Definition at line 614 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivates TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 273 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_IT_TS, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC TimeStamp value.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTimeStamp,: Pointer to Time structure
sTimeStampDate,: Pointer to Date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values: FORMAT_BIN: Binary data format FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 379 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper1 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 836 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper2 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 872 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper3 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 907 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles TimeStamp polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 793 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Sets Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 312 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 431 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 519 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_TamperTypeDef::Interrupt, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_INTERRUPT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Sets TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
Return values:
HAL status

Definition at line 159 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Sets TimeStamp with Interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
Return values:
HAL status

Definition at line 219 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT, RTC_IT_TS, and RTC_HandleTypeDef::State.

__weak void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 745 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

__weak void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 761 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

__weak void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 776 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles TimeStamp interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 656 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_IT, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TAMP3F, RTC_FLAG_TSF, RTC_IT_TS, and RTC_HandleTypeDef::State.

__weak void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 729 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Wake-up functions

Functions
RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

uint32_t HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivates wake up timer counter.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1111 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Gets wake up timer counter.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
Counter value

Definition at line 1166 of file stm32f7xx_hal_rtc_ex.c.

References RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Wake Up Timer Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1223 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Sets wake up timer.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 959 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Sets wake up timer with interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 1032 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_EXTI_LINE_WAKEUPTIMER_EVENT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

__weak void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1206 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Wake Up Timer interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1178 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_IT, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_WUTF, RTC_IT_WUT, and RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extension Peripheral Control functions

Functions
Extension Peripheral Control functions
RTCEx Exported Functions

Extension Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.

Detailed Description

Extension Peripheral Control functions.

 ===============================================================================
              ##### Extension Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1316 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1293 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1554 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1634 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disables the Bypass Shadow feature.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1719 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enables the Bypass Shadow feature.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1686 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
CalibOutput,: Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1515 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enables the RTC reference clock detection.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1584 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmouthCalibMinusPulsesValue
 | ) |  |

Sets the Smooth calibration parameters.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmouthCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmouthCalibMinusPulsesValue must be equal to 0.
Return values:
HAL status

Definition at line 1350 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configures the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
ShiftAdd1S,: Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS,: Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1420 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alram B callback
      (+) RTC Poll for Alarm B request

Function Documentation

__weak void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1769 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmB Polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1786 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx_Exported_Functions_Group1

Functions
RTCEx_Exported_Functions_Group1
RTCEx Exported Functions

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Sets Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper3 Polling.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivates internal TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 343 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivates Tamper.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Tamper,: Selected tamper pin. This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
Return values:
HAL status

Definition at line 614 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivates TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 273 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_IT_TS, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC TimeStamp value.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTimeStamp,: Pointer to Time structure
sTimeStampDate,: Pointer to Date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values: FORMAT_BIN: Binary data format FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 379 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper1 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 836 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper2 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 872 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper3 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 907 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles TimeStamp polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 793 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Sets Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 312 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 431 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 519 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_TamperTypeDef::Interrupt, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_INTERRUPT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Sets TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
Return values:
HAL status

Definition at line 159 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Sets TimeStamp with Interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
Return values:
HAL status

Definition at line 219 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 745 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 761 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 776 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles TimeStamp interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 656 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_IT, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TAMP3F, RTC_FLAG_TSF, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 729 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx_Exported_Functions_Group2

Functions
RTCEx_Exported_Functions_Group2
RTCEx Exported Functions

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.

Function Documentation

uint32_t HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivates wake up timer counter.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1111 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Gets wake up timer counter.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
Counter value

Definition at line 1166 of file stm32f7xx_hal_rtc_ex.c.

References RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Wake Up Timer Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1223 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Sets wake up timer.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 959 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Sets wake up timer with interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 1032 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_EXTI_LINE_WAKEUPTIMER_EVENT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1206 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Wake Up Timer interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1178 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_IT, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_WUTF, RTC_IT_WUT, and RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx_Exported_Functions_Group3

Functions
RTCEx_Exported_Functions_Group3
RTCEx Exported Functions

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1316 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1293 of file stm32f7xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1554 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1634 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disables the Bypass Shadow feature.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1719 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enables the Bypass Shadow feature.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1686 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
CalibOutput,: Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1515 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enables the RTC reference clock detection.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1584 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmouthCalibMinusPulsesValue
 | ) |  |

Sets the Smooth calibration parameters.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmouthCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmouthCalibMinusPulsesValue must be equal to 0.
Return values:
HAL status

Definition at line 1350 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configures the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
ShiftAdd1S,: Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS,: Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1420 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx_Exported_Functions_Group4

Functions
RTCEx_Exported_Functions_Group4
RTCEx Exported Functions

Functions

void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1769 of file stm32f7xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmB Polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1786 of file stm32f7xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and RTC_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Exported Types

RTC Tamper structure definition. More...

#include <stm32f7xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Interrupt
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

RTC Tamper structure definition.

Definition at line 65 of file stm32f7xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the RTC Filter Tamper. This parameter can be a value of RTCEx Tamper Filter Definitions

Definition at line 82 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Interrupt

Specifies the Tamper Interrupt. This parameter can be a value of RTCEx Tamper Interrupt Definitions

Definition at line 70 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTCEx Tamper MaskFlag Definitions

Definition at line 79 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTCEx Tamper EraseBackUp Definitions

Definition at line 76 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTCEx Tamper Pin Precharge Duration Definitions

Definition at line 88 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTCEx Tamper Sampling Frequencies Definitions

Definition at line 85 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTCEx Tamper Pins Definitions

Definition at line 67 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTCEx Tamper Pull UP Definitions

Definition at line 91 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx Tamper TimeStampOnTamperDetection Definitions

Definition at line 94 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTCEx Tamper Trigger Definitions

Definition at line 73 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_rtc_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Output selection Definitions

Defines
RTCEx Output selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)

Define Documentation

#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)

Definition at line 110 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)

Definition at line 111 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)

Definition at line 109 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)

Definition at line 112 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Backup Registers Definitions

Defines
RTC Backup Registers Definitions
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)

Define Documentation

#define RTC_BKP_DR0 ((uint32_t)0x00000000)

Definition at line 120 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 ((uint32_t)0x00000001)

Definition at line 121 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 ((uint32_t)0x0000000A)

Definition at line 130 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 ((uint32_t)0x0000000B)

Definition at line 131 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 ((uint32_t)0x0000000C)

Definition at line 132 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 ((uint32_t)0x0000000D)

Definition at line 133 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 ((uint32_t)0x0000000E)

Definition at line 134 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 ((uint32_t)0x0000000F)

Definition at line 135 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR16 ((uint32_t)0x00000010)

Definition at line 136 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR17 ((uint32_t)0x00000011)

Definition at line 137 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR18 ((uint32_t)0x00000012)

Definition at line 138 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR19 ((uint32_t)0x00000013)

Definition at line 139 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 ((uint32_t)0x00000002)

Definition at line 122 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR20 ((uint32_t)0x00000014)

Definition at line 140 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR21 ((uint32_t)0x00000015)

Definition at line 141 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR22 ((uint32_t)0x00000016)

Definition at line 142 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR23 ((uint32_t)0x00000017)

Definition at line 143 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR24 ((uint32_t)0x00000018)

Definition at line 144 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR25 ((uint32_t)0x00000019)

Definition at line 145 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR26 ((uint32_t)0x0000001A)

Definition at line 146 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR27 ((uint32_t)0x0000001B)

Definition at line 147 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR28 ((uint32_t)0x0000001C)

Definition at line 148 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR29 ((uint32_t)0x0000001D)

Definition at line 149 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 ((uint32_t)0x00000003)

Definition at line 123 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR30 ((uint32_t)0x0000001E)

Definition at line 150 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR31 ((uint32_t)0x0000001F)

Definition at line 151 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 ((uint32_t)0x00000004)

Definition at line 124 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 ((uint32_t)0x00000005)

Definition at line 125 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 ((uint32_t)0x00000006)

Definition at line 126 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 ((uint32_t)0x00000007)

Definition at line 127 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 ((uint32_t)0x00000008)

Definition at line 128 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 ((uint32_t)0x00000009)

Definition at line 129 of file stm32f7xx_hal_rtc_ex.h.

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STM32F745xx HAL User Manual: RTCEx Time Stamp Edges definitions

Defines
RTCEx Time Stamp Edges definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)

Definition at line 160 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)

Definition at line 159 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Tamper Pins Definitions

Defines
RTCEx Tamper Pins Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Define Documentation

#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E

Definition at line 168 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E

Definition at line 169 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Definition at line 170 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Tamper Interrupt Definitions

Defines
RTCEx Tamper Interrupt Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Define Documentation

#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Definition at line 181 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE

Definition at line 178 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE

Definition at line 179 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE

Definition at line 180 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx TimeStamp Pin Selection

Defines
RTCEx TimeStamp Pin Selection
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002)
#define | RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004)

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)

Definition at line 189 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002)

Definition at line 190 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004)

Definition at line 191 of file stm32f7xx_hal_rtc_ex.h.

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STM32F745xx HAL User Manual: RTCEx Tamper Trigger Definitions

Defines
RTCEx Tamper Trigger Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)

Definition at line 200 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 202 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 201 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)

Definition at line 199 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Tamper EraseBackUp Definitions

Defines
RTCEx Tamper EraseBackUp Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)

Define Documentation

#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)

Definition at line 211 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)

Definition at line 210 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Tamper MaskFlag Definitions

Defines
RTCEx Tamper MaskFlag Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)

Define Documentation

#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)

Definition at line 219 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)

Definition at line 220 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Tamper Filter Definitions

Defines
RTCEx Tamper Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)

Tamper is activated after 2 consecutive samples at the active level

Definition at line 230 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)

Tamper is activated after 4 consecutive samples at the active level

Definition at line 232 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)

Tamper is activated after 8 consecutive samples at the active leve.

Definition at line 234 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)

Tamper filter is disabled

Definition at line 228 of file stm32f7xx_hal_rtc_ex.h.

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STM32F745xx HAL User Manual: RTCEx Tamper Sampling Frequencies Definitions

Defines
RTCEx Tamper Sampling Frequencies Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 253 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 245 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 251 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 257 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 243 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 249 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 255 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 247 of file stm32f7xx_hal_rtc_ex.h.

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STM32F745xx HAL User Manual: RTCEx Tamper Pin Precharge Duration Definitions

Defines
RTCEx Tamper Pin Precharge Duration Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 266 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 268 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 270 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 272 of file stm32f7xx_hal_rtc_ex.h.

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STM32F745xx HAL User Manual: RTCEx Tamper TimeStampOnTamperDetection Definitions

Defines
RTCEx Tamper TimeStampOnTamperDetection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)

TimeStamp on Tamper Detection event is not saved

Definition at line 282 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)

TimeStamp on Tamper Detection event saved

Definition at line 281 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Tamper Pull UP Definitions

Defines
RTCEx Tamper Pull UP Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)

TimeStamp on Tamper Detection event is not saved

Definition at line 291 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)

TimeStamp on Tamper Detection event saved

Definition at line 290 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Wakeup Timer Definitions

Defines
RTCEx Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)

Definition at line 303 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)

Definition at line 304 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)

Definition at line 299 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)

Definition at line 302 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)

Definition at line 301 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)

Definition at line 300 of file stm32f7xx_hal_rtc_ex.h.

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STM32F745xx HAL User Manual: RTCEx Smooth calib period Definitions

Defines
RTCEx Smooth calib period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)

If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds

Definition at line 314 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)

If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds

Definition at line 312 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)

If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds

Definition at line 316 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Smooth calib Plus pulses Definitions

Defines
RTCEx Smooth calib Plus pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 328 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 325 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Add 1 Second Parameter Definitions

Defines
RTCEx Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)

Define Documentation

#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)

Definition at line 337 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)

Definition at line 338 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Calib Output selection Definitions

Defines
RTCEx Calib Output selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)

Define Documentation

#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)

Definition at line 347 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)

Definition at line 346 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Exported Macros

Defines
RTCEx Exported Macros
RTCEx

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 652 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 645 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 666 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 659 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Internal Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 638 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 618 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 611 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Internal Time Stamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 628 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 676 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 448 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 441 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 462 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 455 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))

Disable the RTC Tamper3 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 476 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))

Enable the RTC Tamper3 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 469 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to clear. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 528 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 516 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
                                                                                (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 489 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 504 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag.

Return values:
None.

Definition at line 828 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 779 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 791 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 767 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 803 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 816 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 773 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 785 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 761 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 797 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 809 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 834 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 822 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 604 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 542 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 562 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 535 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 552 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 593 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt sources to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 572 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 582 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 434 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 373 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 393 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 366 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 383 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag.

Return values:
None.

Definition at line 749 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 700 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 712 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 688 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 724 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();

Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 737 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 694 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 706 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 682 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 718 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();

Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 730 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 755 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 743 of file stm32f7xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 424 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 403 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 413 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22)
#define | RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define | RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT))

Define Documentation

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21)

External interrupt line 21 Connected to the RTC Tamper and Time Stamp events

Definition at line 927 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22)

External interrupt line 22 Connected to the RTC Wake-up event

Definition at line 928 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))

Definition at line 938 of file stm32f7xx_hal_rtc_ex.h.

#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT))

Definition at line 939 of file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_RTC_OUTPUT(__OUTPUT__)
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(__EDGE__)
#define | IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(__PIN__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_WAKEUP_CLOCK(__CLOCK__)
#define | IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFFF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__)
#define | IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__)
#define | IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)
#define | IS_RTC_SHIFT_ADD1S(__SEL__)
#define | IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)
#define | IS_RTC_CALIB_OUTPUT(__OUTPUT__)

Define Documentation

#define IS_RTC_BKP ( __BKP__ ) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)

Definition at line 956 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( __OUTPUT__ )
Value:
(((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \
                                          ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1011 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_OUTPUT ( __OUTPUT__ )
Value:
(((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \
                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMA)  || \
                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMB)  || \
                                        ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))

Definition at line 952 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SHIFT_ADD1S ( __SEL__ )
Value:
(((__SEL__) == RTC_SHIFTADD1S_RESET) || \
                                     ((__SEL__) == RTC_SHIFTADD1S_SET))

Definition at line 1008 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( __FS__ ) ((__FS__) <= 0x00007FFF)

Definition at line 1010 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( __VALUE__ ) ((__VALUE__) <= 0x000001FF)

Definition at line 1007 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( __PERIOD__ )
Value:
(((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1002 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( __PLUS__ )
Value:
(((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                            ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1005 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( __TAMPER__ ) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))

Definition at line 959 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( __MODE__ )
Value:
(((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                        ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 970 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( __FILTER__ )
Value:
(((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
                                       ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
                                       ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
                                       ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 974 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_INTERRUPT ( __INTERRUPT__ ) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))

Definition at line 961 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_MASKFLAG_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                     ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 972 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( __DURATION__ )
Value:
(((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 986 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
                                       ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 992 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( __FREQ__ )
Value:
(((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 978 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( __DETECTION__ )
Value:
(((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 990 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( __TRIGGER__ )
Value:
(((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 966 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( __PIN__ )
Value:
(((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \
                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS1)  || \
                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS2))

Definition at line 963 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 994 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( __COUNTER__ ) ((__COUNTER__) <= 0xFFFF)

Definition at line 1001 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \
                                     ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 957 of file stm32f7xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Private Typedefs

Enumerations
SAI Private Typedefs
SAI

Enumerations

enum SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Enumeration Type Documentation

enum SAI_ModeTypedef
Enumerator:
SAI_MODE_DMA
SAI_MODE_IT

Definition at line 175 of file stm32f7xx_hal_sai.c.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Private Constants

Defines
SAI Private Constants
SAI

Defines

#define | SAI_FIFO_SIZE 8
#define | SAI_DEFAULT_TIMEOUT 4
#define | SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)

Define Documentation

#define SAI_DEFAULT_TIMEOUT 4

Definition at line 187 of file stm32f7xx_hal_sai.c.

#define SAI_FIFO_SIZE 8

Definition at line 186 of file stm32f7xx_hal_sai.c.

#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)

Definition at line 188 of file stm32f7xx_hal_sai.c.

Referenced by HAL_SAI_EnableRxMuteMode().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SAI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initializes the SAI according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitializes the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
SAI MSP Init.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
SAI MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SAIx peripheral:

      (+) User must implement HAL_SAI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SAI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode (Master/slave TX/RX)
        (++) Protocol
        (++) Data Size
        (++) MCLK Output
        (++) Audio frequency
        (++) FIFO Threshold
        (++) Frame Config
        (++) Slot Config

      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
          of the selected SAI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SAI_DeInit ( SAI_HandleTypeDef * hsai )

DeInitializes the SAI peripheral.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 476 of file stm32f7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_MspDeInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Init ( SAI_HandleTypeDef * hsai )

Initializes the SAI according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 309 of file stm32f7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioFrequency, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, SAI_InitTypeDef::FIFOThreshold, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, HAL_SAI_ERROR_NONE, HAL_SAI_MspInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, IS_SAI_AUDIO_FREQUENCY, IS_SAI_BLOCK_ACTIVE_FRAME, IS_SAI_BLOCK_CLOCK_STROBING, IS_SAI_BLOCK_COMPANDING_MODE, IS_SAI_BLOCK_DATASIZE, IS_SAI_BLOCK_FIFO_THRESHOLD, IS_SAI_BLOCK_FIRST_BIT, IS_SAI_BLOCK_FIRSTBIT_OFFSET, IS_SAI_BLOCK_FRAME_LENGTH, IS_SAI_BLOCK_FS_DEFINITION, IS_SAI_BLOCK_FS_OFFSET, IS_SAI_BLOCK_FS_POLARITY, IS_SAI_BLOCK_MODE, IS_SAI_BLOCK_NODIVIDER, IS_SAI_BLOCK_OUTPUT_DRIVE, IS_SAI_BLOCK_PROTOCOL, IS_SAI_BLOCK_SLOT_NUMBER, IS_SAI_BLOCK_SLOT_SIZE, IS_SAI_BLOCK_SYNCEXT, IS_SAI_BLOCK_SYNCHRO, IS_SAI_BLOCK_TRISTATE_MANAGEMENT, IS_SAI_MONO_STEREO_MODE, IS_SAI_SLOT_ACTIVE, __SAI_HandleTypeDef::Lock, SAI_InitTypeDef::Mckdiv, SAI_InitTypeDef::MonoStereoMode, SAI_InitTypeDef::NoDivider, SAI_InitTypeDef::OutputDrive, SAI_InitTypeDef::Protocol, SAI_ASYNCHRONOUS, SAI_AUDIO_FREQUENCY_MCKDIV, SAI_BlockSynchroConfig(), SAI_CLOCKSTROBING_RISINGEDGE, SAI_Disable(), SAI_GetInputClock(), SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_SYNCHRONOUS, SAI_SYNCHRONOUS_EXT_SAI1, SAI_SYNCHRONOUS_EXT_SAI2, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, SAI_SlotInitTypeDef::SlotSize, __SAI_HandleTypeDef::State, SAI_InitTypeDef::Synchro, SAI_InitTypeDef::SynchroExt, and SAI_InitTypeDef::TriState.

Referenced by HAL_SAI_InitProtocol().

HAL_StatusTypeDef HAL_SAI_InitProtocol | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  |

Initializes the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.

Parameters:
hsai | : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | : one of the supported protocol SAI Supported protocol
datasize | : one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot | : Number of slot.
Return values:
HAL status

Definition at line 270 of file stm32f7xx_hal_sai.c.

References assert_param, HAL_SAI_Init(), IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_InitI2S(), SAI_InitPCM(), SAI_PCM_LONG, and SAI_PCM_SHORT.

void HAL_SAI_MspDeInit ( SAI_HandleTypeDef * hsai )

SAI MSP DeInit.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 533 of file stm32f7xx_hal_sai.c.

Referenced by HAL_SAI_DeInit().

void HAL_SAI_MspInit ( SAI_HandleTypeDef * hsai )

SAI MSP Init.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 517 of file stm32f7xx_hal_sai.c.

Referenced by HAL_SAI_Init().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
SAI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmits an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receives an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stops the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disbaled the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmits an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receives an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
This function handles SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callbacks.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callbacks.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callbacks.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callbacks.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callbacks.

Detailed Description

Data transfers functions.

  ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SAI data
    transfers.

    (+) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (+) Blocking mode functions are :
        (++) HAL_SAI_Transmit()
        (++) HAL_SAI_Receive()
        (++) HAL_SAI_TransmitReceive()

    (+) Non Blocking mode functions with Interrupt are :
        (++) HAL_SAI_Transmit_IT()
        (++) HAL_SAI_Receive_IT()
        (++) HAL_SAI_TransmitReceive_IT()

    (+) Non Blocking mode functions with DMA are :
        (++) HAL_SAI_Transmit_DMA()
        (++) HAL_SAI_Receive_DMA()
        (++) HAL_SAI_TransmitReceive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SAI_TxCpltCallback()
        (++) HAL_SAI_RxCpltCallback()
        (++) HAL_SAI_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SAI_Abort ( SAI_HandleTypeDef * hsai )

Abort the current transfer and disbaled the SAI.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 981 of file stm32f7xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by HAL_SAI_IRQHandler().

HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the rx mute detection.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1218 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the tx mute mode.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1177 of file stm32f7xx_hal_sai.c.

References HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DMAPause ( SAI_HandleTypeDef * hsai )

Pauses the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 892 of file stm32f7xx_hal_sai.c.

References __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAResume ( SAI_HandleTypeDef * hsai )

Resumes the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 912 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, and __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAStop ( SAI_HandleTypeDef * hsai )

Stops the audio stream playing from the Media.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 939 of file stm32f7xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by SAI_DMAError().

HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIcallback | callback,
 |  | uint16_t | counter
 | ) |  |

Enable the rx mute detection.

Parameters:
hsai | : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
callback | : function called when the mute is detected
counter | : number a data before mute detection max 63.
Return values:
HAL status

Definition at line 1195 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE_IT, assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_COUNTER, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, SAI_xCR2_MUTECNT_OFFSET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | uint16_t | val
 | ) |  |

Enable the tx mute mode.

Parameters:
hsai | : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
val | : value sent during the mute SAI Block Mute Value
Return values:
HAL status

Definition at line 1158 of file stm32f7xx_hal_sai.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_VALUE, and __SAI_HandleTypeDef::State.

void HAL_SAI_ErrorCallback ( SAI_HandleTypeDef * hsai )

SAI error callbacks.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1386 of file stm32f7xx_hal_sai.c.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAError().

void HAL_SAI_IRQHandler ( SAI_HandleTypeDef * hsai )

This function handles SAI interrupt request.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1237 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_Abort(), HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_OVR, HAL_SAI_ERROR_UDR, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::mutecallback, SAI_FLAG_AFSDET, SAI_FLAG_CNRDY, SAI_FLAG_LFSDET, SAI_FLAG_MUTEDET, SAI_FLAG_OVRUDR, SAI_FLAG_WCKCFG, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_MUTEDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Receive | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data in blocking mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 688 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, HAL_SAI_STATE_TIMEOUT, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_EMPTY, SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in no-blocking mode with DMA.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 1094 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMARxCplt(), SAI_DMARxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in no-blocking mode with Interrupt.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 834 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_RxCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer completed callbacks.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1354 of file stm32f7xx_hal_sai.c.

Referenced by SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void HAL_SAI_RxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer half completed callbacks.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1370 of file stm32f7xx_hal_sai.c.

Referenced by SAI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SAI_Transmit | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits an amount of data in blocking mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 601 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, HAL_SAI_STATE_TIMEOUT, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_FillFifo(), SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmits an amount of data in no-blocking mode with DMA.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1029 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMATxCplt(), SAI_DMATxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmits an amount of data in no-blocking mode with Interrupt.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 772 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FillFifo(), SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), SAI_Transmit_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_TxCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer completed callbacks.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1322 of file stm32f7xx_hal_sai.c.

Referenced by SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void HAL_SAI_TxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer Half completed callbacks.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1338 of file stm32f7xx_hal_sai.c.

Referenced by SAI_DMATxHalfCplt().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SAI Exported Functions

Peripheral State functions. More...

Functions

HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Returns the SAI state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SAI_GetError ( SAI_HandleTypeDef * hsai )

Return the SAI error code.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for the specified SAI Block.
Return values:
SAI Error Code

Definition at line 1433 of file stm32f7xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode.

HAL_SAI_StateTypeDef HAL_SAI_GetState ( SAI_HandleTypeDef * hsai )

Returns the SAI state.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL state

Definition at line 1422 of file stm32f7xx_hal_sai.c.

References __SAI_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Exported Functions

Modules | Functions
SAI Exported Functions
SAI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State functions

Peripheral State functions.

Functions

static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (SAI_HandleTypeDef *hsai, uint32_t mode)
return the interrupt flag to set according the SAI setup
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
disable the SAI and wait the disabling
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.

Function Documentation

static HAL_StatusTypeDef SAI_Disable ( SAI_HandleTypeDef * hsai ) [static]

disable the SAI and wait the disabling

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1684 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_TIMEOUT, __SAI_HandleTypeDef::Instance, and SAI_TIMEOUT_VALUE.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), and HAL_SAI_Init().

static void SAI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1936 of file stm32f7xx_hal_sai.c.

References HAL_SAI_DMAStop(), HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA(), and HAL_SAI_Transmit_DMA().

static void SAI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1901 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __DMA_HandleTypeDef::Instance, __SAI_HandleTypeDef::Instance, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1924 of file stm32f7xx_hal_sai.c.

References HAL_SAI_RxHalfCpltCallback().

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1863 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __SAI_HandleTypeDef::Instance, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1888 of file stm32f7xx_hal_sai.c.

References HAL_SAI_TxHalfCpltCallback().

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_FillFifo ( SAI_HandleTypeDef * hsai ) [static]

Fill the fifo.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1621 of file stm32f7xx_hal_sai.c.

References SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_NOCOMPANDING, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit(), and HAL_SAI_Transmit_IT().

static HAL_StatusTypeDef SAI_InitI2S | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initializes the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | : one of the supported protocol
datasize | : one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot | : number of slot minimum value is 2 and max is 16. the value must be a multiple of 2.
Return values:
HAL status

Definition at line 1453 of file stm32f7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_ACTIVE_LOW, SAI_FS_BEFOREFIRSTBIT, SAI_FS_CHANNEL_IDENTIFICATION, SAI_FS_FIRSTBIT, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static HAL_StatusTypeDef SAI_InitPCM | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initializes the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | : one of the supported protocol
datasize | : one of the supported datasize SAI protocol data size
nbslot | : number of slot minimum value is 1 and the max is 16.
Return values:
HAL status

Definition at line 1550 of file stm32f7xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_BEFOREFIRSTBIT, SAI_FS_STARTFRAME, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PCM_LONG, SAI_PCM_SHORT, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static uint32_t SAI_InterruptFlag | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | mode
 | ) |  | [static]

return the interrupt flag to set according the SAI setup

Parameters:
hsai | : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
mode | : SAI_MODE_DMA or SAI_MODE_IT
Return values:
the list of the IT flag to enable

Definition at line 1651 of file stm32f7xx_hal_sai.c.

References SAI_InitTypeDef::AudioMode, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_AC97_PROTOCOL, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, SAI_MODE_IT, SAI_MODEMASTER_RX, SAI_MODESLAVE_RX, and SAI_MODESLAVE_TX.

Referenced by HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

static void SAI_Receive_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 16Bit transfer.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1810 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 32Bit transfer.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1836 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode 8Bit transfer.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1784 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Transmit_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 16Bit transfer.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1734 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 32Bit transfer.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1759 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode 8Bit transfer.

Parameters:
hsai : pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None.

Definition at line 1710 of file stm32f7xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Exported Types

Data Structures | Typedefs | Enumerations
SAI Exported Types
SAI

Data Structures

struct | SAI_InitTypeDef
SAI Init Structure definition. More...
struct | SAI_FrameInitTypeDef
SAI Block Frame Init structure definition. More...
struct | SAI_SlotInitTypeDef
SAI Block Slot Init Structure definition. More...
struct | __SAI_HandleTypeDef
SAI handle Structure definition. More...

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef
SAI handle Structure definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00, HAL_SAI_STATE_READY = 0x01, HAL_SAI_STATE_BUSY = 0x02, HAL_SAI_STATE_BUSY_TX = 0x12,
HAL_SAI_STATE_BUSY_RX = 0x22, HAL_SAI_STATE_TIMEOUT = 0x03, HAL_SAI_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __SAI_HandleTypeDef SAI_HandleTypeDef

SAI handle Structure definition.

typedef void(* SAIcallback)(void)

SAI Callback prototype.

Definition at line 80 of file stm32f7xx_hal_sai.h.

Enumeration Type Documentation

enum HAL_SAI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SAI_STATE_RESET

SAI not yet initialized or disabled

HAL_SAI_STATE_READY

SAI initialized and ready for use

HAL_SAI_STATE_BUSY

SAI internal process is ongoing

HAL_SAI_STATE_BUSY_TX

Data transmission process is ongoing

HAL_SAI_STATE_BUSY_RX

Data reception process is ongoing

HAL_SAI_STATE_TIMEOUT

SAI timeout state

HAL_SAI_STATE_ERROR

SAI error state

Definition at line 66 of file stm32f7xx_hal_sai.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_InitTypeDef Struct Reference
SAI Exported Types

SAI Init Structure definition. More...

#include <stm32f7xx_hal_sai.h>

Data Fields

uint32_t | AudioMode
uint32_t | Synchro
uint32_t | SynchroExt
uint32_t | OutputDrive
uint32_t | NoDivider
uint32_t | FIFOThreshold
uint32_t | AudioFrequency
uint32_t | Mckdiv
uint32_t | MonoStereoMode
uint32_t | CompandingMode
uint32_t | TriState
uint32_t | Protocol
uint32_t | DataSize
uint32_t | FirstBit
uint32_t | ClockStrobing

Detailed Description

SAI Init Structure definition.

Definition at line 85 of file stm32f7xx_hal_sai.h.

Field Documentation

uint32_t SAI_InitTypeDef::AudioFrequency

Specifies the audio frequency sampling. This parameter can be a value of SAI Audio Frequency

Definition at line 114 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::AudioMode

Specifies the SAI Block audio Mode. This parameter can be a value of SAI Block Mode

Definition at line 87 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::ClockStrobing

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI Block Clock Strobing

Definition at line 142 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::CompandingMode

Specifies the companding mode type. This parameter can be a value of SAI Block Companding Mode

Definition at line 124 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

uint32_t SAI_InitTypeDef::DataSize

Specifies the SAI Block data size. This parameter can be a value of SAI Block Data Size

Definition at line 136 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::FIFOThreshold

Specifies SAI Block FIFO threshold. This parameter can be a value of SAI Block Fifo Threshold

Definition at line 111 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI Block MSB LSB transmission

Definition at line 139 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::Mckdiv

Specifies the master clock divider, the parameter will be used if for AudioFrequency the user choice This parameter must be a number between Min_Data = 0 and Max_Data = 15

Definition at line 117 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MonoStereoMode

Specifies if the mono or stereo mode is selected. This parameter can be a value of SAI Mono Stereo Mode

Definition at line 121 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::NoDivider

Specifies whether master clock will be divided or not. This parameter can be a value of SAI Block NoDivider

Note:
If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values without constraint since the input clock of the audio block should be equal to the bit clock. There is no MCLK_x clock which can be output.

Definition at line 102 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::OutputDrive

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI Block Output Drive

Note:
this value has to be set before enabling the audio block but after the audio block configuration.

Definition at line 97 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::Protocol

Specifies the SAI Block protocol. This parameter can be a value of SAI Block Protocol

Definition at line 133 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::Synchro

Specifies SAI Block synchronization This parameter can be a value of SAI Block Synchronization

Definition at line 90 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_BlockSynchroConfig().

uint32_t SAI_InitTypeDef::SynchroExt

Specifies SAI Block synchronization, this setup is common for BLOCKA and BLOCKB This parameter can be a value of SAI External synchronisation

Definition at line 93 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_BlockSynchroConfig().

uint32_t SAI_InitTypeDef::TriState

Specifies the companding mode type. This parameter can be a value of SAI TRIState Management

Definition at line 127 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sai.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI_FrameInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_FrameInitTypeDef Struct Reference
SAI Exported Types

SAI Block Frame Init structure definition. More...

#include <stm32f7xx_hal_sai.h>

Data Fields

uint32_t | FrameLength
uint32_t | ActiveFrameLength
uint32_t | FSDefinition
uint32_t | FSPolarity
uint32_t | FSOffset

Detailed Description

SAI Block Frame Init structure definition.

Definition at line 150 of file stm32f7xx_hal_sai.h.

Field Documentation

uint32_t SAI_FrameInitTypeDef::ActiveFrameLength

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 159 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FrameLength

Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256.

Note:
If master clock MCLK_x pin is declared as an output, the frame length should be aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.

Definition at line 153 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSDefinition

Specifies the Frame synchronization definition. This parameter can be a value of SAI Block FS Definition

Definition at line 164 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSOffset

Specifies the Frame synchronization Offset. This parameter can be a value of SAI Block FS Offset

Definition at line 170 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSPolarity

Specifies the Frame synchronization Polarity. This parameter can be a value of SAI Block FS Polarity

Definition at line 167 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sai.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI_SlotInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_SlotInitTypeDef Struct Reference
SAI Exported Types

SAI Block Slot Init Structure definition. More...

#include <stm32f7xx_hal_sai.h>

Data Fields

uint32_t | FirstBitOffset
uint32_t | SlotSize
uint32_t | SlotNumber
uint32_t | SlotActive

Detailed Description

SAI Block Slot Init Structure definition.

Definition at line 179 of file stm32f7xx_hal_sai.h.

Field Documentation

uint32_t SAI_SlotInitTypeDef::FirstBitOffset

Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24

Definition at line 181 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotActive

Specifies the slots in audio frame that will be activated. This parameter can be a value of SAI Block Slot Active

Definition at line 190 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotNumber

Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 187 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotSize

Specifies the Slot Size. This parameter can be a value of SAI Block Slot Size

Definition at line 184 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sai.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: __SAI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SAI_HandleTypeDef Struct Reference
SAI Exported Types

SAI handle Structure definition. More...

#include <stm32f7xx_hal_sai.h>

Data Fields

SAI_Block_TypeDef * | Instance
SAI_InitTypeDef Init
SAI_FrameInitTypeDef FrameInit
SAI_SlotInitTypeDef SlotInit
uint8_t * | pBuffPtr
uint16_t | XferSize
uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
SAIcallback mutecallback
void(* | InterruptServiceRoutine )(struct __SAI_HandleTypeDef *hsai)
HAL_LockTypeDef | Lock
__IO HAL_SAI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SAI handle Structure definition.

Definition at line 197 of file stm32f7xx_hal_sai.h.

Field Documentation

__IO uint32_t __SAI_HandleTypeDef::ErrorCode

SAI Error code

Definition at line 225 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_GetError(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), and SAI_Disable().

SAI_FrameInitTypeDef __SAI_HandleTypeDef::FrameInit

SAI Frame configuration parameters

Definition at line 203 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmarx

SAI Rx DMA handle parameters

Definition at line 215 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), and HAL_SAI_Receive_DMA().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmatx

SAI Tx DMA handle parameters

Definition at line 213 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), and HAL_SAI_Transmit_DMA().

SAI_InitTypeDef __SAI_HandleTypeDef::Init

SAI communication parameters

Definition at line 201 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_BlockSynchroConfig(), SAI_FillFifo(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

SAI_Block_TypeDef* __SAI_HandleTypeDef::Instance

SAI Blockx registers base address

Definition at line 199 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAPause(), HAL_SAI_DMAResume(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_BlockSynchroConfig(), SAI_Disable(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_GetInputClock(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai)

Definition at line 219 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive_IT(), and HAL_SAI_Transmit_IT().

HAL_LockTypeDef __SAI_HandleTypeDef::Lock

SAI locking object

Definition at line 221 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAIcallback __SAI_HandleTypeDef::mutecallback

SAI mute callback

Definition at line 217 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

uint8_t* __SAI_HandleTypeDef::pBuffPtr

Pointer to SAI transfer Buffer

Definition at line 207 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

SAI_SlotInitTypeDef __SAI_HandleTypeDef::SlotInit

SAI Slot configuration parameters

Definition at line 205 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

__IO HAL_SAI_StateTypeDef __SAI_HandleTypeDef::State

SAI communication state

Definition at line 223 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableRxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_GetState(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferCount

SAI transfer counter

Definition at line 211 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferSize

SAI transfer size

Definition at line 209 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sai.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Error Code

Defines
SAI Error Code
SAI Exported Constants

Defines

#define | HAL_SAI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SAI_ERROR_OVR ((uint32_t)0x00000001)
#define | HAL_SAI_ERROR_UDR ((uint32_t)0x00000002)
#define | HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004)
#define | HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008)
#define | HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010)
#define | HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020)
#define | HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040)

Define Documentation

#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004)

Anticipated Frame synchronisation detection

Definition at line 244 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010)

codec not ready

Definition at line 246 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008)

Late Frame synchronisation detection

Definition at line 245 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 241 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001)

Overrun Error

Definition at line 242 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040)

Timeout error

Definition at line 248 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Transmit(), and SAI_Disable().

#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002)

Underrun error

Definition at line 243 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020)

Wrong clock configuration

Definition at line 247 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI External synchronisation

Defines
SAI External synchronisation
SAI Exported Constants

Defines

#define | SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000)
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000001)
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000002)

Define Documentation

#define SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000)

Definition at line 256 of file stm32f7xx_hal_sai.h.

Referenced by SAI_BlockSynchroConfig().

#define SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000001)

Definition at line 257 of file stm32f7xx_hal_sai.h.

Referenced by SAI_BlockSynchroConfig().

#define SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000002)

Definition at line 258 of file stm32f7xx_hal_sai.h.

Referenced by SAI_BlockSynchroConfig().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Supported protocol

Defines
SAI Supported protocol
SAI Exported Constants

Defines

#define | SAI_I2S_STANDARD ((uint32_t)0x00000000)
#define | SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001)
#define | SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002)
#define | SAI_PCM_LONG ((uint32_t)0x00000004)
#define | SAI_PCM_SHORT ((uint32_t)0x00000008)

Define Documentation

#define SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002)

Definition at line 268 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001)

Definition at line 267 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_STANDARD ((uint32_t)0x00000000)

Definition at line 266 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_PCM_LONG ((uint32_t)0x00000004)

Definition at line 269 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

#define SAI_PCM_SHORT ((uint32_t)0x00000008)

Definition at line 270 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI protocol data size

Defines
SAI protocol data size
SAI Exported Constants

Defines

#define | SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000)
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001)
#define | SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002)
#define | SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004)

Define Documentation

#define SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000)

Definition at line 278 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001)

Definition at line 279 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002)

Definition at line 280 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004)

Definition at line 281 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Clock Source

Defines
SAI Clock Source
SAI Exported Constants

Defines

#define | SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
#define | SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000)
#define | SAI_CLKSOURCE_EXT ((uint32_t)0x00200000)
#define | SAI_CLKSOURCE_NA ((uint32_t)0x00400000)

Define Documentation

#define SAI_CLKSOURCE_EXT ((uint32_t)0x00200000)

Definition at line 291 of file stm32f7xx_hal_sai.h.

#define SAI_CLKSOURCE_NA ((uint32_t)0x00400000)

Definition at line 292 of file stm32f7xx_hal_sai.h.

#define SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000)

Definition at line 290 of file stm32f7xx_hal_sai.h.

#define SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000)

Definition at line 289 of file stm32f7xx_hal_sai.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Audio Frequency

Defines
SAI Audio Frequency
SAI Exported Constants

Defines

#define | SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)
#define | SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000)
#define | SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000)
#define | SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100)
#define | SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000)
#define | SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)
#define | SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)
#define | SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)
#define | SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
#define | SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0)

Define Documentation

#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)

Definition at line 307 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)

Definition at line 306 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)

Definition at line 300 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)

Definition at line 305 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000)

Definition at line 304 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100)

Definition at line 303 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000)

Definition at line 302 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)

Definition at line 308 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000)

Definition at line 301 of file stm32f7xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0)

Definition at line 309 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Mode

Defines
SAI Block Mode
SAI Exported Constants

Defines

#define | SAI_MODEMASTER_TX ((uint32_t)0x00000000)
#define | SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define | SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define | SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))

Define Documentation

#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)

Definition at line 319 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODEMASTER_TX ((uint32_t)0x00000000)

Definition at line 318 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))

Definition at line 321 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)

Definition at line 320 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Protocol

Defines
SAI Block Protocol
SAI Exported Constants

Defines

#define | SAI_FREE_PROTOCOL ((uint32_t)0x00000000)
#define | SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define | SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)

Define Documentation

#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)

Definition at line 332 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000)

Definition at line 330 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)

Definition at line 331 of file stm32f7xx_hal_sai.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Data Size

Defines
SAI Block Data Size
SAI Exported Constants

Defines

#define | SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define | SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define | SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define | SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Define Documentation

#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Definition at line 342 of file stm32f7xx_hal_sai.h.

#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)

Definition at line 343 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))

Definition at line 344 of file stm32f7xx_hal_sai.h.

#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))

Definition at line 345 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Definition at line 346 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)

Definition at line 341 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block MSB LSB transmission

Defines
SAI Block MSB LSB transmission
SAI Exported Constants

Defines

#define | SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define | SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)

Define Documentation

#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)

Definition at line 356 of file stm32f7xx_hal_sai.h.

#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)

Definition at line 355 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Clock Strobing

Defines
SAI Block Clock Strobing
SAI Exported Constants

Defines

#define | SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)
#define | SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)0x00000001)

Define Documentation

#define SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)

Definition at line 365 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)0x00000001)

Definition at line 366 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Synchronization

Defines
SAI Block Synchronization
SAI Exported Constants

Defines

#define | SAI_ASYNCHRONOUS ((uint32_t)0x00000000)
#define | SAI_SYNCHRONOUS ((uint32_t)0x00000001)
#define | SAI_SYNCHRONOUS_EXT_SAI1 ((uint32_t)0x00000002)
#define | SAI_SYNCHRONOUS_EXT_SAI2 ((uint32_t)0x00000003)

Define Documentation

#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000)

Asynchronous

Definition at line 375 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS ((uint32_t)0x00000001)

Synchronous with other block of same SAI

Definition at line 376 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI1 ((uint32_t)0x00000002)

Synchronous with other SAI, SAI1

Definition at line 377 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI2 ((uint32_t)0x00000003)

Synchronous with other SAI, SAI2

Definition at line 378 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_BlockSynchroConfig().

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STM32F745xx HAL User Manual: SAI Block Output Drive

Defines
SAI Block Output Drive
SAI Exported Constants

Defines

#define | SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000)
#define | SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)

Define Documentation

#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000)

Definition at line 386 of file stm32f7xx_hal_sai.h.

#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)

Definition at line 387 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Block NoDivider

Defines
SAI Block NoDivider
SAI Exported Constants

Defines

#define | SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000)
#define | SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)

Define Documentation

#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)

Definition at line 397 of file stm32f7xx_hal_sai.h.

#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000)

Definition at line 396 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Block FS Definition

Defines
SAI Block FS Definition
SAI Exported Constants

Defines

#define | SAI_FS_STARTFRAME ((uint32_t)0x00000000)
#define | SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)

Define Documentation

#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)

Definition at line 408 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S().

#define SAI_FS_STARTFRAME ((uint32_t)0x00000000)

Definition at line 407 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitPCM().

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STM32F745xx HAL User Manual: SAI Block FS Polarity

Defines
SAI Block FS Polarity
SAI Exported Constants

Defines

#define | SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)
#define | SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)

Define Documentation

#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)

Definition at line 418 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)

Definition at line 417 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block FS Offset

Defines
SAI Block FS Offset
SAI Exported Constants

Defines

#define | SAI_FS_FIRSTBIT ((uint32_t)0x00000000)
#define | SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)

Define Documentation

#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)

Definition at line 428 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000)

Definition at line 427 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S().

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STM32F745xx HAL User Manual: SAI Block Slot Size

Defines
SAI Block Slot Size
SAI Exported Constants

Defines

#define | SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000)
#define | SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define | SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)

Define Documentation

#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)

Definition at line 439 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)

Definition at line 440 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000)

Definition at line 438 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Block Slot Active

Defines
SAI Block Slot Active
SAI Exported Constants

Defines

#define | SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
#define | SAI_SLOTACTIVE_0 ((uint32_t)0x00000001)
#define | SAI_SLOTACTIVE_1 ((uint32_t)0x00000002)
#define | SAI_SLOTACTIVE_2 ((uint32_t)0x00000004)
#define | SAI_SLOTACTIVE_3 ((uint32_t)0x00000008)
#define | SAI_SLOTACTIVE_4 ((uint32_t)0x00000010)
#define | SAI_SLOTACTIVE_5 ((uint32_t)0x00000020)
#define | SAI_SLOTACTIVE_6 ((uint32_t)0x00000040)
#define | SAI_SLOTACTIVE_7 ((uint32_t)0x00000080)
#define | SAI_SLOTACTIVE_8 ((uint32_t)0x00000100)
#define | SAI_SLOTACTIVE_9 ((uint32_t)0x00000200)
#define | SAI_SLOTACTIVE_10 ((uint32_t)0x00000400)
#define | SAI_SLOTACTIVE_11 ((uint32_t)0x00000800)
#define | SAI_SLOTACTIVE_12 ((uint32_t)0x00001000)
#define | SAI_SLOTACTIVE_13 ((uint32_t)0x00002000)
#define | SAI_SLOTACTIVE_14 ((uint32_t)0x00004000)
#define | SAI_SLOTACTIVE_15 ((uint32_t)0x00008000)
#define | SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFF)

Define Documentation

#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)

Definition at line 448 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001)

Definition at line 449 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002)

Definition at line 450 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400)

Definition at line 459 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800)

Definition at line 460 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000)

Definition at line 461 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000)

Definition at line 462 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000)

Definition at line 463 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000)

Definition at line 464 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004)

Definition at line 451 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008)

Definition at line 452 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010)

Definition at line 453 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020)

Definition at line 454 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040)

Definition at line 455 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080)

Definition at line 456 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100)

Definition at line 457 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200)

Definition at line 458 of file stm32f7xx_hal_sai.h.

#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFF)

Definition at line 465 of file stm32f7xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

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STM32F745xx HAL User Manual: SAI Mono Stereo Mode

Defines
SAI Mono Stereo Mode
SAI Exported Constants

Defines

#define | SAI_STEREOMODE ((uint32_t)0x00000000)
#define | SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)

Define Documentation

#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)

Definition at line 475 of file stm32f7xx_hal_sai.h.

#define SAI_STEREOMODE ((uint32_t)0x00000000)

Definition at line 474 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI TRIState Management

Defines
SAI TRIState Management
SAI Exported Constants

Defines

#define | SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)
#define | SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)

Define Documentation

#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)

Definition at line 484 of file stm32f7xx_hal_sai.h.

#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)

Definition at line 485 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Block Fifo Threshold

Defines
SAI Block Fifo Threshold
SAI Exported Constants

Defines

#define | SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)
#define | SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1)
#define | SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2)

Define Documentation

#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0)

Definition at line 495 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))

Definition at line 497 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)

Definition at line 494 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2)

Definition at line 498 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1)

Definition at line 496 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Block Companding Mode

Defines
SAI Block Companding Mode
SAI Exported Constants

Defines

#define | SAI_NOCOMPANDING ((uint32_t)0x00000000)
#define | SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1)
#define | SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define | SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define | SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))

Define Documentation

#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))

Definition at line 509 of file stm32f7xx_hal_sai.h.

#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))

Definition at line 511 of file stm32f7xx_hal_sai.h.

#define SAI_NOCOMPANDING ((uint32_t)0x00000000)

Definition at line 507 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1)

Definition at line 508 of file stm32f7xx_hal_sai.h.

#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))

Definition at line 510 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Block Mute Value

Defines
SAI Block Mute Value
SAI Exported Constants

Defines

#define | SAI_ZERO_VALUE ((uint32_t)0x00000000)
#define | SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)

Define Documentation

#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)

Definition at line 521 of file stm32f7xx_hal_sai.h.

#define SAI_ZERO_VALUE ((uint32_t)0x00000000)

Definition at line 520 of file stm32f7xx_hal_sai.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Interrupts Definition

Defines
SAI Block Interrupts Definition
SAI Exported Constants

Defines

#define | SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define | SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define | SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define | SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define | SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define | SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define | SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)

Define Documentation

#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)

Definition at line 536 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)

Definition at line 535 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)

Definition at line 534 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)

Definition at line 537 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)

Definition at line 532 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)

Definition at line 531 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)

Definition at line 533 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Flags Definition

Defines
SAI Block Flags Definition
SAI Exported Constants

Defines

#define | SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define | SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define | SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define | SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define | SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define | SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define | SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)

Define Documentation

#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)

Definition at line 551 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)

Definition at line 550 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)

Definition at line 549 of file stm32f7xx_hal_sai.h.

#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)

Definition at line 552 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)

Definition at line 547 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)

Definition at line 546 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)

Definition at line 548 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Block Fifo Status Level

Defines
SAI Block Fifo Status Level
SAI Exported Constants

Defines

#define | SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000)
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000)
#define | SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000)
#define | SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000)
#define | SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000)
#define | SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000)

Define Documentation

#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000)

Definition at line 563 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000)

Definition at line 565 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000)

Definition at line 561 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Receive().

#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000)

Definition at line 566 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Transmit(), and SAI_FillFifo().

#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000)

Definition at line 564 of file stm32f7xx_hal_sai.h.

#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000)

Definition at line 562 of file stm32f7xx_hal_sai.h.

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STM32F745xx HAL User Manual: SAI Exported Macros

Defines
SAI Exported Macros
SAI

macros to handle interrupts and specific configurations More...

Defines

#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified SAI interrupt source is enabled or disabled.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clears the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Detailed Description

macros to handle interrupts and specific configurations

Define Documentation

#define __HAL_SAI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clears the specified SAI pending flag.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SAI_FLAG_OVRUDR: Clear Overrun underrun
  • SAI_FLAG_MUTEDET: Clear Mute detection
  • SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
  • SAI_FLAG_FREQ: Clear FIFO request
  • SAI_FLAG_CNRDY: Clear Codec not ready
  • SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
  • SAI_FLAG_LFSDET: Clear Late frame synchronization detection
Return values:
None

Definition at line 647 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define __HAL_SAI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Definition at line 650 of file stm32f7xx_hal_sai.h.

Referenced by SAI_Disable().

#define __HAL_SAI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

Definition at line 604 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

#define __HAL_SAI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)

Definition at line 649 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_DMAResume(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable or disable the specified SAI interrupts.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
Return values:
None

Definition at line 603 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SAI flag is set or not.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SAI_FLAG_OVRUDR: Overrun underrun flag.
  • SAI_FLAG_MUTEDET: Mute detection flag.
  • SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
  • SAI_FLAG_FREQ: FIFO request flag.
  • SAI_FLAG_CNRDY: Codec not ready flag.
  • SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
  • SAI_FLAG_LFSDET: Late frame synchronization detection flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 631 of file stm32f7xx_hal_sai.h.

#define __HAL_SAI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check if the specified SAI interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the SAI Handle. This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
__INTERRUPT__,: specifies the SAI interrupt source to check. This parameter can be one of the following values:
  • SAI_IT_TXE: Tx buffer empty interrupt enable.
  • SAI_IT_RXNE: Rx buffer not empty interrupt enable.
  • SAI_IT_ERR: Error interrupt enable.
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 616 of file stm32f7xx_hal_sai.h.

#define __HAL_SAI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)

Reset SAI handle state.

Parameters:
__HANDLE__,: specifies the SAI Handle.
Return values:
None

Definition at line 587 of file stm32f7xx_hal_sai.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Private Types

SAI Private Types
SAI
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Private Variables

SAI Private Variables
SAI
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Private Functions

SAI Private Functions
SAI | SAIEx
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI_Private_Macros

Defines
SAI_Private_Macros
SAI

Defines

#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_CLK_SOURCE(SOURCE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_FIFO_STATUS(STATUS)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Define Documentation

#define IS_SAI_AUDIO_FREQUENCY ( AUDIO )
Value:
(((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

Definition at line 782 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_ACTIVE_FRAME ( LENGTH ) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Definition at line 874 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_CLOCK_STROBING ( CLOCK )
Value:
(((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

Definition at line 807 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_COMPANDING_MODE ( MODE )
Value:
(((MODE) == SAI_NOCOMPANDING)         || \
                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

Definition at line 833 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_DATASIZE_8)  || \
                                         ((DATASIZE) == SAI_DATASIZE_10) || \
                                         ((DATASIZE) == SAI_DATASIZE_16) || \
                                         ((DATASIZE) == SAI_DATASIZE_20) || \
                                         ((DATASIZE) == SAI_DATASIZE_24) || \
                                         ((DATASIZE) == SAI_DATASIZE_32))

Definition at line 797 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIFO_STATUS ( STATUS )
Value:
(((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \
                                          ((STATUS) == SAI_FIFOSTATUS_HALFFULL)          || \
                                          ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL)      || \
                                          ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL)     || \
                                          ((STATUS) == SAI_FIFOSTATUS_FULL)              || \
                                          ((STATUS) == SAI_FIFOSTATUS_EMPTY))

Definition at line 821 of file stm32f7xx_hal_sai.h.

#define IS_SAI_BLOCK_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

Definition at line 839 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRST_BIT ( BIT )
Value:
(((BIT) == SAI_FIRSTBIT_MSB) || \
                                     ((BIT) == SAI_FIRSTBIT_LSB))

Definition at line 804 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRSTBIT_OFFSET ( OFFSET ) ((OFFSET) <= 24)

Definition at line 859 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FRAME_LENGTH ( LENGTH ) ((8 <= (LENGTH)) && ((LENGTH) <= 256))

Definition at line 872 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_DEFINITION ( DEFINITION )
Value:
(((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

Definition at line 867 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_OFFSET ( OFFSET )
Value:
(((OFFSET) == SAI_FS_FIRSTBIT) || \
                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

Definition at line 861 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_POLARITY ( POLARITY )
Value:
(((POLARITY) == SAI_FS_ACTIVE_LOW) || \
                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

Definition at line 864 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MASTER_DIVIDER ( DIVIDER ) ((DIVIDER) <= 15)

Definition at line 870 of file stm32f7xx_hal_sai.h.

#define IS_SAI_BLOCK_MODE ( MODE )
Value:
(((MODE) == SAI_MODEMASTER_TX) || \
                                    ((MODE) == SAI_MODEMASTER_RX) || \
                                    ((MODE) == SAI_MODESLAVE_TX)  || \
                                    ((MODE) == SAI_MODESLAVE_RX))

Definition at line 788 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MUTE_COUNTER ( COUNTER ) ((COUNTER) <= 63)

Definition at line 828 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode().

#define IS_SAI_BLOCK_MUTE_VALUE ( VALUE )
Value:
(((VALUE) == SAI_ZERO_VALUE)     || \
                                           ((VALUE) == SAI_LAST_SENT_VALUE))

Definition at line 830 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_EnableTxMuteMode().

#define IS_SAI_BLOCK_NODIVIDER ( NODIVIDER )
Value:
(((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

Definition at line 818 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_OUTPUT_DRIVE ( DRIVE )
Value:
(((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

Definition at line 815 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

Definition at line 793 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_NUMBER ( NUMBER ) ((1 <= (NUMBER)) && ((NUMBER) <= 16))

Definition at line 853 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_SIZE ( SIZE )
Value:
(((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                      ((SIZE) == SAI_SLOTSIZE_32B))

Definition at line 855 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCEXT ( STATE )
Value:
(((STATE) == SAI_SYNCEXT_DISABLE)           ||\
                                       ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE)  ||\
                                       ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))

Definition at line 763 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCHRO ( SYNCHRO )
Value:
(((SYNCHRO) == SAI_ASYNCHRONOUS) || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS)  || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))

Definition at line 810 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT ( STATE )
Value:
(((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
                                                 ((STATE) == SAI_OUTPUT_RELEASED))

Definition at line 845 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
                                   ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
                                   ((SOURCE) == SAI_CLKSOURCE_EXT))

Definition at line 778 of file stm32f7xx_hal_sai.h.

#define IS_SAI_MONO_STEREO_MODE ( MODE )
Value:
(((MODE) == SAI_MONOMODE) ||\
                                       ((MODE) == SAI_STEREOMODE))

Definition at line 848 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PROTOCOL_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

Definition at line 773 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), SAI_InitI2S(), and SAI_InitPCM().

#define IS_SAI_SLOT_ACTIVE ( ACTIVE ) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

Definition at line 851 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_SUPPORTED_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_I2S_STANDARD)     ||\
                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
                                               ((PROTOCOL) == SAI_PCM_SHORT))

Definition at line 767 of file stm32f7xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI

Modules | Defines
SAI
STM32F7xx_HAL_Driver

SAI HAL module driver. More...

Modules

SAI Private Typedefs
SAI Private Constants
SAI Exported Functions
SAI Exported Types
SAI Exported Constants
SAI Exported Macros

macros to handle interrupts and specific configurations

SAI Private Types
SAI Private Variables
SAI Private Functions
SAI_Private_Macros

Defines

#define | CR1_CLEAR_MASK ((uint32_t)0xFF04C010)
#define | FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)
#define | SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)
#define | SAI_TIMEOUT_VALUE 10

Detailed Description

SAI HAL module driver.

Define Documentation

#define CR1_CLEAR_MASK ((uint32_t)0xFF04C010)

Definition at line 194 of file stm32f7xx_hal_sai.c.

#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)

Definition at line 195 of file stm32f7xx_hal_sai.c.

#define SAI_TIMEOUT_VALUE 10

Definition at line 198 of file stm32f7xx_hal_sai.c.

Referenced by SAI_Disable().

#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)

Definition at line 196 of file stm32f7xx_hal_sai.c.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extension features functions

Functions
Extension features functions
SAI Extended Exported Functions

Extension features functions. More...

Functions

void | SAI_BlockSynchroConfig (SAI_HandleTypeDef *hsai)
Configure SAI Block synchronization mode.
uint32_t | SAI_GetInputClock (SAI_HandleTypeDef *hsai)
Get SAI Input Clock based on SAI source clock selection.

Detailed Description

Extension features functions.

 ===============================================================================
                       ##### Extension features Functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the possible
    SAI clock sources.

Function Documentation

void SAI_BlockSynchroConfig ( SAI_HandleTypeDef * hsai )

Configure SAI Block synchronization mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
SAI Clock Input

Definition at line 107 of file stm32f7xx_hal_sai_ex.c.

References __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE, SAI_SYNCHRONOUS_EXT_SAI2, SAI_InitTypeDef::Synchro, and SAI_InitTypeDef::SynchroExt.

Referenced by HAL_SAI_Init().

uint32_t SAI_GetInputClock ( SAI_HandleTypeDef * hsai )

Get SAI Input Clock based on SAI source clock selection.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
SAI Clock Input

Definition at line 148 of file stm32f7xx_hal_sai_ex.c.

References HAL_RCCEx_GetPeriphCLKFreq(), __SAI_HandleTypeDef::Instance, RCC_PERIPHCLK_SAI1, and RCC_PERIPHCLK_SAI2.

Referenced by HAL_SAI_Init().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Functions

Functions
SD Private Functions
SD

Functions

static HAL_SD_ErrorTypedef | SD_Initialize_Cards (SD_HandleTypeDef *hsd)
Initializes all cards or single card as the case may be Card(s) come into standby state.
static HAL_SD_ErrorTypedef | SD_Select_Deselect (SD_HandleTypeDef *hsd, uint64_t addr)
Selects od Deselects the corresponding card.
static HAL_SD_ErrorTypedef | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static HAL_SD_ErrorTypedef | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static HAL_SD_ErrorTypedef | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static HAL_SD_CardStateTypedef | SD_GetState (SD_HandleTypeDef *hsd)
Returns the SD current state.
static HAL_SD_ErrorTypedef | SD_IsCardProgramming (SD_HandleTypeDef *hsd, uint8_t *pStatus)
Checks if the SD card is in programming state.
static HAL_SD_ErrorTypedef | SD_CmdError (SD_HandleTypeDef *hsd)
Checks for error conditions for CMD0.
static HAL_SD_ErrorTypedef | SD_CmdResp1Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD)
Checks for error conditions for R1 response.
static HAL_SD_ErrorTypedef | SD_CmdResp7Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R7 response.
static HAL_SD_ErrorTypedef | SD_CmdResp3Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R3 (OCR) response.
static HAL_SD_ErrorTypedef | SD_CmdResp2Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R2 (CID or CSD) response.
static HAL_SD_ErrorTypedef | SD_CmdResp6Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
Checks for error conditions for R6 (RCA) response.
static HAL_SD_ErrorTypedef | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static void | SD_DMA_RxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx callback.
static void | SD_DMA_RxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Rx callback.
static void | SD_DMA_TxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Tx callback.
static void | SD_DMA_TxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Tx callback.

Function Documentation

static HAL_SD_ErrorTypedef SD_CmdError ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for CMD0.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2609 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_CMD_RSP_TIMEOUT, SD_OK, SDMMC_CMD0TIMEOUT, and SDMMC_STATIC_FLAGS.

Referenced by SD_PowerON().

static HAL_SD_ErrorTypedef SD_CmdResp1Error | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t | SD_CMD
 | ) |  | [static]

Checks for error conditions for R1 response.

Parameters:
hsd,: SD handle
SD_CMD,: The sent command index
Return values:
SD Card error state

Definition at line 2685 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::Instance, SD_ADDR_MISALIGNED, SD_ADDR_OUT_OF_RANGE, SD_AKE_SEQ_ERROR, SD_ALLZERO, SD_BAD_ERASE_PARAM, SD_BLOCK_LEN_ERR, SD_CARD_ECC_DISABLED, SD_CARD_ECC_FAILED, SD_CC_ERROR, SD_CID_CSD_OVERWRITE, SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_COM_CRC_FAILED, SD_ERASE_RESET, SD_ERASE_SEQ_ERR, SD_GENERAL_UNKNOWN_ERROR, SD_ILLEGAL_CMD, SD_LOCK_UNLOCK_FAILED, SD_OCR_ADDR_MISALIGNED, SD_OCR_ADDR_OUT_OF_RANGE, SD_OCR_AKE_SEQ_ERROR, SD_OCR_BAD_ERASE_PARAM, SD_OCR_BLOCK_LEN_ERR, SD_OCR_CARD_ECC_DISABLED, SD_OCR_CARD_ECC_FAILED, SD_OCR_CC_ERROR, SD_OCR_CID_CSD_OVERWRITE, SD_OCR_COM_CRC_FAILED, SD_OCR_ERASE_RESET, SD_OCR_ERASE_SEQ_ERR, SD_OCR_ERRORBITS, SD_OCR_GENERAL_UNKNOWN_ERROR, SD_OCR_ILLEGAL_CMD, SD_OCR_LOCK_UNLOCK_FAILED, SD_OCR_STREAM_READ_UNDERRUN, SD_OCR_STREAM_WRITE_OVERRUN, SD_OCR_WP_ERASE_SKIP, SD_OCR_WRITE_PROT_VIOLATION, SD_OK, SD_STREAM_READ_UNDERRUN, SD_STREAM_WRITE_OVERRUN, SD_WP_ERASE_SKIP, SD_WRITE_PROT_VIOLATION, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_Erase(), HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_SendSDStatus(), HAL_SD_StopTransfer(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), SD_FindSCR(), SD_PowerON(), SD_Select_Deselect(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

static HAL_SD_ErrorTypedef SD_CmdResp2Error ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for R2 (CID or CSD) response.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2861 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_OK, and SDMMC_STATIC_FLAGS.

Referenced by SD_Initialize_Cards().

static HAL_SD_ErrorTypedef SD_CmdResp3Error ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for R3 (OCR) response.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2833 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_CMD_RSP_TIMEOUT, SD_OK, and SDMMC_STATIC_FLAGS.

Referenced by SD_PowerON().

static HAL_SD_ErrorTypedef SD_CmdResp6Error | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t | SD_CMD,
 |  | uint16_t * | pRCA
 | ) |  | [static]

Checks for error conditions for R6 (RCA) response.

Parameters:
hsd,: SD handle
SD_CMD,: The sent command index
pRCA,: Pointer to the variable that will contain the SD card relative address RCA
Return values:
SD Card error state

Definition at line 2904 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::Instance, SD_ALLZERO, SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_COM_CRC_FAILED, SD_GENERAL_UNKNOWN_ERROR, SD_ILLEGAL_CMD, SD_OK, SD_R6_COM_CRC_FAILED, SD_R6_GENERAL_UNKNOWN_ERROR, SD_R6_ILLEGAL_CMD, and SDMMC_STATIC_FLAGS.

Referenced by SD_Initialize_Cards().

static HAL_SD_ErrorTypedef SD_CmdResp7Error ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for R7 response.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2641 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_CMD_RSP_TIMEOUT, SD_ERROR, SD_OK, and SDMMC_CMD0TIMEOUT.

Referenced by SD_PowerON().

static void SD_DMA_RxCplt ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer complete Rx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2197 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::DmaTransferCplt, HAL_DMA_Abort(), HAL_SD_DMA_RxCpltCallback(), SD_HandleTypeDef::hdmarx, and SD_HandleTypeDef::SdTransferCplt.

Referenced by HAL_SD_ReadBlocks_DMA().

static void SD_DMA_RxError ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer Error Rx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2222 of file stm32f7xx_hal_sd.c.

References HAL_SD_DMA_RxErrorCallback(), and SD_HandleTypeDef::hdmarx.

Referenced by HAL_SD_ReadBlocks_DMA().

static void SD_DMA_TxCplt ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer complete Tx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2236 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::DmaTransferCplt, HAL_DMA_Abort(), HAL_SD_DMA_TxCpltCallback(), SD_HandleTypeDef::hdmatx, and SD_HandleTypeDef::SdTransferCplt.

Referenced by HAL_SD_WriteBlocks_DMA().

static void SD_DMA_TxError ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer Error Tx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2261 of file stm32f7xx_hal_sd.c.

References HAL_SD_DMA_TxErrorCallback(), and SD_HandleTypeDef::hdmatx.

Referenced by HAL_SD_WriteBlocks_DMA().

static HAL_SD_ErrorTypedef SD_FindSCR | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSCR
 | ) |  | [static]

Finds the SD card SCR register value.

Parameters:
hsd,: SD handle
pSCR,: pointer to the buffer that will contain the SCR value
Return values:
SD Card error state

Definition at line 3118 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_0TO7BITS, SD_16TO23BITS, SD_24TO31BITS, SD_8TO15BITS, SD_CMD_APP_CMD, SD_CMD_SD_APP_SEND_SCR, SD_CMD_SET_BLOCKLEN, SD_CmdResp1Error(), SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_OK, SD_RX_OVERRUN, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_HighSpeed(), SD_WideBus_Disable(), and SD_WideBus_Enable().

static HAL_SD_CardStateTypedef SD_GetState ( SD_HandleTypeDef * hsd ) [static]

Returns the SD current state.

Parameters:
hsd,: SD handle
Return values:
SD card current state

Definition at line 2274 of file stm32f7xx_hal_sd.c.

References SD_CARD_ERROR, SD_OK, and SD_SendStatus().

Referenced by HAL_SD_GetStatus().

static HAL_SD_ErrorTypedef SD_Initialize_Cards ( SD_HandleTypeDef * hsd ) [static]

Initializes all cards or single card as the case may be Card(s) come into standby state.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2294 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::CardType, SD_HandleTypeDef::CID, SD_HandleTypeDef::CSD, HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_CMD_ALL_SEND_CID, SD_CMD_SEND_CSD, SD_CMD_SET_REL_ADDR, SD_CmdResp2Error(), SD_CmdResp6Error(), SD_OK, SD_REQUEST_NOT_APPLICABLE, SECURE_DIGITAL_IO_CARD, SECURE_DIGITAL_IO_COMBO_CARD, STD_CAPACITY_SD_CARD_V1_1, and STD_CAPACITY_SD_CARD_V2_0.

Referenced by HAL_SD_Init().

static HAL_SD_ErrorTypedef SD_IsCardProgramming | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pStatus
 | ) |  | [static]

Checks if the SD card is in programming state.

Parameters:
hsd,: SD handle
pStatus,: pointer to the variable that will contain the SD card state
Return values:
SD Card error state

Definition at line 3232 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_ADDR_MISALIGNED, SD_ADDR_OUT_OF_RANGE, SD_AKE_SEQ_ERROR, SD_ALLZERO, SD_BAD_ERASE_PARAM, SD_BLOCK_LEN_ERR, SD_CARD_ECC_DISABLED, SD_CARD_ECC_FAILED, SD_CC_ERROR, SD_CID_CSD_OVERWRITE, SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_CMD_SEND_STATUS, SD_COM_CRC_FAILED, SD_ERASE_RESET, SD_ERASE_SEQ_ERR, SD_GENERAL_UNKNOWN_ERROR, SD_ILLEGAL_CMD, SD_LOCK_UNLOCK_FAILED, SD_OCR_ADDR_MISALIGNED, SD_OCR_ADDR_OUT_OF_RANGE, SD_OCR_AKE_SEQ_ERROR, SD_OCR_BAD_ERASE_PARAM, SD_OCR_BLOCK_LEN_ERR, SD_OCR_CARD_ECC_DISABLED, SD_OCR_CARD_ECC_FAILED, SD_OCR_CC_ERROR, SD_OCR_CID_CSD_OVERWRITE, SD_OCR_COM_CRC_FAILED, SD_OCR_ERASE_RESET, SD_OCR_ERASE_SEQ_ERR, SD_OCR_ERRORBITS, SD_OCR_GENERAL_UNKNOWN_ERROR, SD_OCR_ILLEGAL_CMD, SD_OCR_LOCK_UNLOCK_FAILED, SD_OCR_STREAM_READ_UNDERRUN, SD_OCR_STREAM_WRITE_OVERRUN, SD_OCR_WP_ERASE_SKIP, SD_OCR_WRITE_PROT_VIOLATION, SD_OK, SD_STREAM_READ_UNDERRUN, SD_STREAM_WRITE_OVERRUN, SD_WP_ERASE_SKIP, SD_WRITE_PROT_VIOLATION, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_Erase(), and HAL_SD_WriteBlocks().

static HAL_SD_ErrorTypedef SD_PowerOFF ( SD_HandleTypeDef * hsd ) [static]

Turns the SDMMC output signals off.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2553 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, and SD_OK.

Referenced by HAL_SD_DeInit().

static HAL_SD_ErrorTypedef SD_PowerON ( SD_HandleTypeDef * hsd ) [static]

Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2412 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_DISABLE, __HAL_SD_SDMMC_ENABLE, SD_HandleTypeDef::CardType, HAL_Delay(), HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_CHECK_PATTERN, SD_CMD_APP_CMD, SD_CMD_GO_IDLE_STATE, SD_CMD_SD_APP_OP_COND, SD_CmdError(), SD_CmdResp1Error(), SD_CmdResp3Error(), SD_CmdResp7Error(), SD_HIGH_CAPACITY, SD_INVALID_VOLTRANGE, SD_MAX_VOLT_TRIAL, SD_OK, SD_SDMMC_SEND_IF_COND, SD_STD_CAPACITY, SD_VOLTAGE_WINDOW_SD, and STD_CAPACITY_SD_CARD_V2_0.

Referenced by HAL_SD_Init().

static HAL_SD_ErrorTypedef SD_Select_Deselect | ( | SD_HandleTypeDef * | hsd,
 |  | uint64_t | addr
 | ) |  | [static]

Selects od Deselects the corresponding card.

Parameters:
hsd,: SD handle
addr,: Address of the card to be selected
Return values:
SD Card error state

Definition at line 2386 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, SD_CMD_SEL_DESEL_CARD, SD_CmdResp1Error(), and SD_OK.

Referenced by HAL_SD_Init().

static HAL_SD_ErrorTypedef SD_SendStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pCardStatus
 | ) |  | [static]

Returns the current card's status.

Parameters:
hsd,: SD handle
pCardStatus,: pointer to the buffer that will contain the SD card status (Card Status register)
Return values:
SD Card error state

Definition at line 2570 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_CMD_SEND_STATUS, SD_CmdResp1Error(), SD_INVALID_PARAMETER, and SD_OK.

Referenced by SD_GetState().

static HAL_SD_ErrorTypedef SD_WideBus_Disable ( SD_HandleTypeDef * hsd ) [static]

Disables the SDMMC wide bus mode.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 3047 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_ALLZERO, SD_CARD_LOCKED, SD_CMD_APP_CMD, SD_CMD_APP_SD_SET_BUSWIDTH, SD_CmdResp1Error(), SD_FindSCR(), SD_LOCK_UNLOCK_FAILED, SD_OK, SD_REQUEST_NOT_APPLICABLE, and SD_SINGLE_BUS_SUPPORT.

Referenced by HAL_SD_WideBusOperation_Config().

static HAL_SD_ErrorTypedef SD_WideBus_Enable ( SD_HandleTypeDef * hsd ) [static]

Enables the SDMMC wide bus mode.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2978 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_ALLZERO, SD_CARD_LOCKED, SD_CMD_APP_CMD, SD_CMD_APP_SD_SET_BUSWIDTH, SD_CmdResp1Error(), SD_FindSCR(), SD_LOCK_UNLOCK_FAILED, SD_OK, SD_REQUEST_NOT_APPLICABLE, and SD_WIDE_BUS_SUPPORT.

Referenced by HAL_SD_WideBusOperation_Config().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Handle Structure definition

Data Structures | Defines
SD Handle Structure definition
SD Exported Types

Data Structures

struct | SD_HandleTypeDef

Defines

#define | SD_InitTypeDef SDMMC_InitTypeDef
#define | SD_TypeDef SDMMC_TypeDef

Define Documentation

#define SD_InitTypeDef SDMMC_InitTypeDef

Definition at line 66 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Init().

#define SD_TypeDef SDMMC_TypeDef

Definition at line 67 of file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SD_HandleTypeDef Struct Reference
SD Handle Structure definition

#include <stm32f7xx_hal_sd.h>

Data Fields

SD_TypeDef * Instance
SD_InitTypeDef Init
HAL_LockTypeDef | Lock
uint32_t | CardType
uint32_t | RCA
uint32_t | CSD [4]
uint32_t | CID [4]
__IO uint32_t | SdTransferCplt
__IO uint32_t | SdTransferErr
__IO uint32_t | DmaTransferCplt
__IO uint32_t | SdOperation
DMA_HandleTypeDef * hdmarx
DMA_HandleTypeDef * hdmatx

Detailed Description

Definition at line 69 of file stm32f7xx_hal_sd.h.

Field Documentation

uint32_t SD_HandleTypeDef::CardType

SD card type

Definition at line 77 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_Get_CardInfo(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WideBusOperation_Config(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), SD_Initialize_Cards(), and SD_PowerON().

uint32_t SD_HandleTypeDef::CID[4]

SD card identification number table

Definition at line 83 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo(), and SD_Initialize_Cards().

uint32_t SD_HandleTypeDef::CSD[4]

SD card specific data table

Definition at line 81 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_Get_CardInfo(), and SD_Initialize_Cards().

__IO uint32_t SD_HandleTypeDef::DmaTransferCplt

SD DMA transfer complete flag

Definition at line 89 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), SD_DMA_RxCplt(), and SD_DMA_TxCplt().

DMA_HandleTypeDef* SD_HandleTypeDef::hdmarx

SD Rx DMA handle parameters

Definition at line 93 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), SD_DMA_RxCplt(), and SD_DMA_RxError().

DMA_HandleTypeDef* SD_HandleTypeDef::hdmatx

SD Tx DMA handle parameters

Definition at line 95 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks_DMA(), SD_DMA_TxCplt(), and SD_DMA_TxError().

SD_InitTypeDef SD_HandleTypeDef::Init

SD required parameters

Definition at line 73 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Init(), and HAL_SD_WideBusOperation_Config().

SD_TypeDef* SD_HandleTypeDef::Instance

SDMMC register base address

Definition at line 71 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_HighSpeed(), HAL_SD_Init(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_SendSDStatus(), HAL_SD_StopTransfer(), HAL_SD_WideBusOperation_Config(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), SD_CmdResp1Error(), SD_CmdResp6Error(), SD_FindSCR(), SD_Initialize_Cards(), SD_IsCardProgramming(), SD_PowerOFF(), SD_PowerON(), SD_Select_Deselect(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

HAL_LockTypeDef SD_HandleTypeDef::Lock

SD locking object

Definition at line 75 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Init().

uint32_t SD_HandleTypeDef::RCA

SD relative card address

Definition at line 79 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo(), HAL_SD_SendSDStatus(), SD_FindSCR(), SD_Initialize_Cards(), SD_IsCardProgramming(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

__IO uint32_t SD_HandleTypeDef::SdOperation

SD transfer operation (read/write)

Definition at line 91 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

__IO uint32_t SD_HandleTypeDef::SdTransferCplt

SD transfer complete flag in non blocking mode

Definition at line 85 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), SD_DMA_RxCplt(), and SD_DMA_TxCplt().

__IO uint32_t SD_HandleTypeDef::SdTransferErr

SD transfer error flag in non blocking mode

Definition at line 87 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL_SD_CSDTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CSDTypedef Struct Reference
Card Specific Data: CSD Register

#include <stm32f7xx_hal_sd.h>

Data Fields

__IO uint8_t | CSDStruct
__IO uint8_t | SysSpecVersion
__IO uint8_t | Reserved1
__IO uint8_t | TAAC
__IO uint8_t | NSAC
__IO uint8_t | MaxBusClkFrec
__IO uint16_t | CardComdClasses
__IO uint8_t | RdBlockLen
__IO uint8_t | PartBlockRead
__IO uint8_t | WrBlockMisalign
__IO uint8_t | RdBlockMisalign
__IO uint8_t | DSRImpl
__IO uint8_t | Reserved2
__IO uint32_t | DeviceSize
__IO uint8_t | MaxRdCurrentVDDMin
__IO uint8_t | MaxRdCurrentVDDMax
__IO uint8_t | MaxWrCurrentVDDMin
__IO uint8_t | MaxWrCurrentVDDMax
__IO uint8_t | DeviceSizeMul
__IO uint8_t | EraseGrSize
__IO uint8_t | EraseGrMul
__IO uint8_t | WrProtectGrSize
__IO uint8_t | WrProtectGrEnable
__IO uint8_t | ManDeflECC
__IO uint8_t | WrSpeedFact
__IO uint8_t | MaxWrBlockLen
__IO uint8_t | WriteBlockPaPartial
__IO uint8_t | Reserved3
__IO uint8_t | ContentProtectAppli
__IO uint8_t | FileFormatGrouop
__IO uint8_t | CopyFlag
__IO uint8_t | PermWrProtect
__IO uint8_t | TempWrProtect
__IO uint8_t | FileFormat
__IO uint8_t | ECC
__IO uint8_t | CSD_CRC
__IO uint8_t | Reserved4

Detailed Description

Definition at line 105 of file stm32f7xx_hal_sd.h.

Field Documentation

__IO uint16_t HAL_SD_CSDTypedef::CardComdClasses

Card command classes

Definition at line 113 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::ContentProtectAppli

Content protection application

Definition at line 135 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::CopyFlag

Copy flag (OTP)

Definition at line 137 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::CSD_CRC

CSD CRC

Definition at line 142 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::CSDStruct

CSD structure

Definition at line 107 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint32_t HAL_SD_CSDTypedef::DeviceSize

Device Size

Definition at line 120 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::DeviceSizeMul

Device size multiplier

Definition at line 125 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::DSRImpl

DSR implemented

Definition at line 118 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::ECC

ECC code

Definition at line 141 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::EraseGrMul

Erase group size multiplier

Definition at line 127 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::EraseGrSize

Erase group size

Definition at line 126 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::FileFormat

File format

Definition at line 140 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::FileFormatGrouop

File format group

Definition at line 136 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::ManDeflECC

Manufacturer default ECC

Definition at line 130 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::MaxBusClkFrec

Max. bus clock frequency

Definition at line 112 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::MaxRdCurrentVDDMax

Max. read current @ VDD max

Definition at line 122 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::MaxRdCurrentVDDMin

Max. read current @ VDD min

Definition at line 121 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::MaxWrBlockLen

Max. write data block length

Definition at line 132 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::MaxWrCurrentVDDMax

Max. write current @ VDD max

Definition at line 124 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::MaxWrCurrentVDDMin

Max. write current @ VDD min

Definition at line 123 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::NSAC

Data read access time 2 in CLK cycles

Definition at line 111 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::PartBlockRead

Partial blocks for read allowed

Definition at line 115 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::PermWrProtect

Permanent write protection

Definition at line 138 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::RdBlockLen

Max. read data block length

Definition at line 114 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::RdBlockMisalign

Read block misalignment

Definition at line 117 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::Reserved1

Reserved

Definition at line 109 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::Reserved2

Reserved

Definition at line 119 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::Reserved3

Reserved

Definition at line 134 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::Reserved4

Always 1

Definition at line 143 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::SysSpecVersion

System specification version

Definition at line 108 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::TAAC

Data read access time 1

Definition at line 110 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::TempWrProtect

Temporary write protection

Definition at line 139 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::WrBlockMisalign

Write block misalignment

Definition at line 116 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::WriteBlockPaPartial

Partial blocks for write allowed

Definition at line 133 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::WrProtectGrEnable

Write protect group enable

Definition at line 129 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::WrProtectGrSize

Write protect group size

Definition at line 128 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CSDTypedef::WrSpeedFact

Write speed factor

Definition at line 131 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL_SD_CIDTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CIDTypedef Struct Reference
Card Identification Data: CID Register

#include <stm32f7xx_hal_sd.h>

Data Fields

__IO uint8_t | ManufacturerID
__IO uint16_t | OEM_AppliID
__IO uint32_t | ProdName1
__IO uint8_t | ProdName2
__IO uint8_t | ProdRev
__IO uint32_t | ProdSN
__IO uint8_t | Reserved1
__IO uint16_t | ManufactDate
__IO uint8_t | CID_CRC
__IO uint8_t | Reserved2

Detailed Description

Definition at line 153 of file stm32f7xx_hal_sd.h.

Field Documentation

__IO uint8_t HAL_SD_CIDTypedef::CID_CRC

CID CRC

Definition at line 163 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint16_t HAL_SD_CIDTypedef::ManufactDate

Manufacturing Date

Definition at line 162 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CIDTypedef::ManufacturerID

Manufacturer ID

Definition at line 155 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint16_t HAL_SD_CIDTypedef::OEM_AppliID

OEM/Application ID

Definition at line 156 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint32_t HAL_SD_CIDTypedef::ProdName1

Product Name part1

Definition at line 157 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CIDTypedef::ProdName2

Product Name part2

Definition at line 158 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CIDTypedef::ProdRev

Product Revision

Definition at line 159 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint32_t HAL_SD_CIDTypedef::ProdSN

Product Serial Number

Definition at line 160 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CIDTypedef::Reserved1

Reserved1

Definition at line 161 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

__IO uint8_t HAL_SD_CIDTypedef::Reserved2

Always 1

Definition at line 164 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL_SD_CardStatusTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardStatusTypedef Struct Reference
SD Card Status returned by ACMD13

#include <stm32f7xx_hal_sd.h>

Data Fields

__IO uint8_t | DAT_BUS_WIDTH
__IO uint8_t | SECURED_MODE
__IO uint16_t | SD_CARD_TYPE
__IO uint32_t | SIZE_OF_PROTECTED_AREA
__IO uint8_t | SPEED_CLASS
__IO uint8_t | PERFORMANCE_MOVE
__IO uint8_t | AU_SIZE
__IO uint16_t | ERASE_SIZE
__IO uint8_t | ERASE_TIMEOUT
__IO uint8_t | ERASE_OFFSET

Detailed Description

Definition at line 174 of file stm32f7xx_hal_sd.h.

Field Documentation

__IO uint8_t HAL_SD_CardStatusTypedef::AU_SIZE

Carries information about the card's allocation unit size

Definition at line 182 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::DAT_BUS_WIDTH

Shows the currently defined data bus width

Definition at line 176 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::ERASE_OFFSET

Carries information about the erase offset

Definition at line 185 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint16_t HAL_SD_CardStatusTypedef::ERASE_SIZE

Determines the number of AUs to be erased in one operation

Definition at line 183 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::ERASE_TIMEOUT

Determines the timeout for any number of AU erase

Definition at line 184 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::PERFORMANCE_MOVE

Carries information about the card's performance move

Definition at line 181 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint16_t HAL_SD_CardStatusTypedef::SD_CARD_TYPE

Carries information about card type

Definition at line 178 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::SECURED_MODE

Card is in secured mode of operation

Definition at line 177 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint32_t HAL_SD_CardStatusTypedef::SIZE_OF_PROTECTED_AREA

Carries information about the capacity of protected area

Definition at line 179 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

__IO uint8_t HAL_SD_CardStatusTypedef::SPEED_CLASS

Carries information about the speed class of the card

Definition at line 180 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_GetCardStatus().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HAL_SD_CardInfoTypedef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_SD_CardInfoTypedef Struct Reference
SD Card information structure

#include <stm32f7xx_hal_sd.h>

Data Fields

HAL_SD_CSDTypedef SD_csd
HAL_SD_CIDTypedef SD_cid
uint64_t | CardCapacity
uint32_t | CardBlockSize
uint16_t | RCA
uint8_t | CardType

Detailed Description

Definition at line 195 of file stm32f7xx_hal_sd.h.

Field Documentation

uint32_t HAL_SD_CardInfoTypedef::CardBlockSize

Card block size

Definition at line 200 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

uint64_t HAL_SD_CardInfoTypedef::CardCapacity

Card capacity

Definition at line 199 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

uint8_t HAL_SD_CardInfoTypedef::CardType

SD card type

Definition at line 202 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

uint16_t HAL_SD_CardInfoTypedef::RCA

SD relative card address

Definition at line 201 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo(), and HAL_SD_Init().

HAL_SD_CIDTypedef HAL_SD_CardInfoTypedef::SD_cid

SD card identification number register

Definition at line 198 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

HAL_SD_CSDTypedef HAL_SD_CardInfoTypedef::SD_csd

SD card specific data register

Definition at line 197 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Get_CardInfo().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Error status enumeration Structure definition

Enumerations
SD Error status enumeration Structure definition
SD Exported Types

Enumerations

enum HAL_SD_ErrorTypedef {
SD_CMD_CRC_FAIL = (1), SD_DATA_CRC_FAIL = (2), SD_CMD_RSP_TIMEOUT = (3), SD_DATA_TIMEOUT = (4),
SD_TX_UNDERRUN = (5), SD_RX_OVERRUN = (6), SD_START_BIT_ERR = (7), SD_CMD_OUT_OF_RANGE = (8),
SD_ADDR_MISALIGNED = (9), SD_BLOCK_LEN_ERR = (10), SD_ERASE_SEQ_ERR = (11), SD_BAD_ERASE_PARAM = (12),
SD_WRITE_PROT_VIOLATION = (13), SD_LOCK_UNLOCK_FAILED = (14), SD_COM_CRC_FAILED = (15), SD_ILLEGAL_CMD = (16),
SD_CARD_ECC_FAILED = (17), SD_CC_ERROR = (18), SD_GENERAL_UNKNOWN_ERROR = (19), SD_STREAM_READ_UNDERRUN = (20),
SD_STREAM_WRITE_OVERRUN = (21), SD_CID_CSD_OVERWRITE = (22), SD_WP_ERASE_SKIP = (23), SD_CARD_ECC_DISABLED = (24),
SD_ERASE_RESET = (25), SD_AKE_SEQ_ERROR = (26), SD_INVALID_VOLTRANGE = (27), SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29), SD_SDMMC_DISABLED = (30), SD_SDMMC_FUNCTION_BUSY = (31), SD_SDMMC_FUNCTION_FAILED = (32),
SD_SDMMC_UNKNOWN_FUNCTION = (33), SD_INTERNAL_ERROR = (34), SD_NOT_CONFIGURED = (35), SD_REQUEST_PENDING = (36),
SD_REQUEST_NOT_APPLICABLE = (37), SD_INVALID_PARAMETER = (38), SD_UNSUPPORTED_FEATURE = (39), SD_UNSUPPORTED_HW = (40),
SD_ERROR = (41), SD_OK = (0)
}

Enumeration Type Documentation

enum HAL_SD_ErrorTypedef
Enumerator:
SD_CMD_CRC_FAIL

SD specific error defines.

Command response received (but CRC check failed)

SD_DATA_CRC_FAIL

Data block sent/received (CRC check failed)

SD_CMD_RSP_TIMEOUT

Command response timeout

SD_DATA_TIMEOUT

Data timeout

SD_TX_UNDERRUN

Transmit FIFO underrun

SD_RX_OVERRUN

Receive FIFO overrun

SD_START_BIT_ERR

Start bit not detected on all data signals in wide bus mode

SD_CMD_OUT_OF_RANGE

Command's argument was out of range.

SD_ADDR_MISALIGNED

Misaligned address

SD_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

SD_ERASE_SEQ_ERR

An error in the sequence of erase command occurs.

SD_BAD_ERASE_PARAM

An invalid selection for erase groups

SD_WRITE_PROT_VIOLATION

Attempt to program a write protect block

SD_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

SD_COM_CRC_FAILED

CRC check of the previous command failed

SD_ILLEGAL_CMD

Command is not legal for the card state

SD_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

SD_CC_ERROR

Internal card controller error

SD_GENERAL_UNKNOWN_ERROR

General or unknown error

SD_STREAM_READ_UNDERRUN

The card could not sustain data transfer in stream read operation.

SD_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

SD_CID_CSD_OVERWRITE

CID/CSD overwrite error

SD_WP_ERASE_SKIP

Only partial address space was erased

SD_CARD_ECC_DISABLED

Command has been executed without using internal ECC

SD_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

SD_AKE_SEQ_ERROR

Error in sequence of authentication.

SD_INVALID_VOLTRANGE
SD_ADDR_OUT_OF_RANGE
SD_SWITCH_ERROR
SD_SDMMC_DISABLED
SD_SDMMC_FUNCTION_BUSY
SD_SDMMC_FUNCTION_FAILED
SD_SDMMC_UNKNOWN_FUNCTION
SD_INTERNAL_ERROR

Standard error defines.

SD_NOT_CONFIGURED
SD_REQUEST_PENDING
SD_REQUEST_NOT_APPLICABLE
SD_INVALID_PARAMETER
SD_UNSUPPORTED_FEATURE
SD_UNSUPPORTED_HW
SD_ERROR
SD_OK

Definition at line 212 of file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Transfer state enumeration structure

Enumerations
SD Transfer state enumeration structure
SD Exported Types

Enumerations

enum HAL_SD_TransferStateTypedef { SD_TRANSFER_OK = 0, SD_TRANSFER_BUSY = 1, SD_TRANSFER_ERROR = 2 }

Enumeration Type Documentation

enum HAL_SD_TransferStateTypedef
Enumerator:
SD_TRANSFER_OK

Transfer success

SD_TRANSFER_BUSY

Transfer is occurring

SD_TRANSFER_ERROR

Transfer failed

Definition at line 272 of file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Card State enumeration structure

Enumerations
SD Card State enumeration structure
SD Exported Types

Enumerations

enum HAL_SD_CardStateTypedef {
SD_CARD_READY = ((uint32_t)0x00000001), SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), SD_CARD_STANDBY = ((uint32_t)0x00000003), SD_CARD_TRANSFER = ((uint32_t)0x00000004),
SD_CARD_SENDING = ((uint32_t)0x00000005), SD_CARD_RECEIVING = ((uint32_t)0x00000006), SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), SD_CARD_DISCONNECTED = ((uint32_t)0x00000008),
SD_CARD_ERROR = ((uint32_t)0x000000FF)
}

Enumeration Type Documentation

enum HAL_SD_CardStateTypedef
Enumerator:
SD_CARD_READY

Card state is ready

SD_CARD_IDENTIFICATION

Card is in identification state

SD_CARD_STANDBY

Card is in standby state

SD_CARD_TRANSFER

Card is in transfer state

SD_CARD_SENDING

Card is sending an operation

SD_CARD_RECEIVING

Card is receiving operation information

SD_CARD_PROGRAMMING

Card is in programming state

SD_CARD_DISCONNECTED

Card is disconnected

SD_CARD_ERROR

Card is in error state

Definition at line 286 of file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Operation enumeration structure

Enumerations
SD Operation enumeration structure
SD Exported Types

Enumerations

enum HAL_SD_OperationTypedef { SD_READ_SINGLE_BLOCK = 0, SD_READ_MULTIPLE_BLOCK = 1, SD_WRITE_SINGLE_BLOCK = 2, SD_WRITE_MULTIPLE_BLOCK = 3 }

Enumeration Type Documentation

enum HAL_SD_OperationTypedef
Enumerator:
SD_READ_SINGLE_BLOCK

Read single block operation

SD_READ_MULTIPLE_BLOCK

Read multiple blocks operation

SD_WRITE_SINGLE_BLOCK

Write single block operation

SD_WRITE_MULTIPLE_BLOCK

Write multiple blocks operation

Definition at line 306 of file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Exported Constants

Defines
SD Exported Constants
SD

Defines

#define | SD_CMD_GO_IDLE_STATE ((uint8_t)0)
SD Commands Index.
#define | SD_CMD_SEND_OP_COND ((uint8_t)1)
#define | SD_CMD_ALL_SEND_CID ((uint8_t)2)
#define | SD_CMD_SET_REL_ADDR ((uint8_t)3)
#define | SD_CMD_SET_DSR ((uint8_t)4)
#define | SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5)
#define | SD_CMD_HS_SWITCH ((uint8_t)6)
#define | SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
#define | SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)
#define | SD_CMD_SEND_CSD ((uint8_t)9)
#define | SD_CMD_SEND_CID ((uint8_t)10)
#define | SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11)
#define | SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
#define | SD_CMD_SEND_STATUS ((uint8_t)13)
#define | SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
#define | SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)
#define | SD_CMD_SET_BLOCKLEN ((uint8_t)16)
#define | SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
#define | SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
#define | SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)
#define | SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20)
#define | SD_CMD_SET_BLOCK_COUNT ((uint8_t)23)
#define | SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
#define | SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
#define | SD_CMD_PROG_CID ((uint8_t)26)
#define | SD_CMD_PROG_CSD ((uint8_t)27)
#define | SD_CMD_SET_WRITE_PROT ((uint8_t)28)
#define | SD_CMD_CLR_WRITE_PROT ((uint8_t)29)
#define | SD_CMD_SEND_WRITE_PROT ((uint8_t)30)
#define | SD_CMD_SD_ERASE_GRP_START ((uint8_t)32)
#define | SD_CMD_SD_ERASE_GRP_END ((uint8_t)33)
#define | SD_CMD_ERASE_GRP_START ((uint8_t)35)
#define | SD_CMD_ERASE_GRP_END ((uint8_t)36)
#define | SD_CMD_ERASE ((uint8_t)38)
#define | SD_CMD_FAST_IO ((uint8_t)39)
#define | SD_CMD_GO_IRQ_STATE ((uint8_t)40)
#define | SD_CMD_LOCK_UNLOCK ((uint8_t)42)
#define | SD_CMD_APP_CMD ((uint8_t)55)
#define | SD_CMD_GEN_CMD ((uint8_t)56)
#define | SD_CMD_NO_CMD ((uint8_t)64)
#define | SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)
Following commands are SD Card Specific commands.
#define | SD_CMD_SD_APP_STATUS ((uint8_t)13)
#define | SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)
#define | SD_CMD_SD_APP_OP_COND ((uint8_t)41)
#define | SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)
#define | SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)
#define | SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52)
#define | SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53)
#define | SD_CMD_SD_APP_GET_MKB ((uint8_t)43)
Following commands are SD Card Specific security commands.
#define | SD_CMD_SD_APP_GET_MID ((uint8_t)44)
#define | SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
#define | SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
#define | SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
#define | SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
#define | SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
#define | SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
#define | SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
#define | SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
#define | SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
#define | STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
Supported SD Memory Cards.
#define | STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
#define | HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
#define | MULTIMEDIA_CARD ((uint32_t)0x00000003)
#define | SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
#define | HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
#define | SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
#define | HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)

Define Documentation

#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)

Definition at line 425 of file stm32f7xx_hal_sd.h.

#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)

Definition at line 420 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_Get_CardInfo(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WideBusOperation_Config(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), SD_Initialize_Cards(), and SD_PowerON().

#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)

Definition at line 423 of file stm32f7xx_hal_sd.h.

#define MULTIMEDIA_CARD ((uint32_t)0x00000003)

Definition at line 421 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_WideBusOperation_Config().

#define SD_CMD_ALL_SEND_CID ((uint8_t)2)

Asks any card connected to the host to send the CID numbers on the CMD line.

Definition at line 332 of file stm32f7xx_hal_sd.h.

Referenced by SD_Initialize_Cards().

#define SD_CMD_APP_CMD ((uint8_t)55)

Indicates to the card that the next command is an application specific command rather than a standard command.

Definition at line 377 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_SendSDStatus(), SD_FindSCR(), SD_PowerON(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)

Following commands are SD Card Specific commands.

SDMMC_APP_CMD should be sent before sending these commands. (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register.

Definition at line 387 of file stm32f7xx_hal_sd.h.

Referenced by SD_WideBus_Disable(), and SD_WideBus_Enable().

#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29)

Clears the write protection bit of the addressed group.

Definition at line 364 of file stm32f7xx_hal_sd.h.

#define SD_CMD_ERASE ((uint8_t)38)

Reserved for SD security applications.

Definition at line 372 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase().

#define SD_CMD_ERASE_GRP_END ((uint8_t)36)

Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6).

Definition at line 370 of file stm32f7xx_hal_sd.h.

#define SD_CMD_ERASE_GRP_START ((uint8_t)35)

Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6).

Definition at line 368 of file stm32f7xx_hal_sd.h.

#define SD_CMD_FAST_IO ((uint8_t)39)

SD card doesn't support it (Reserved).

Definition at line 373 of file stm32f7xx_hal_sd.h.

#define SD_CMD_GEN_CMD ((uint8_t)56)

Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands.

Definition at line 379 of file stm32f7xx_hal_sd.h.

#define SD_CMD_GO_IDLE_STATE ((uint8_t)0)

SD Commands Index.

Resets the SD memory card.

Definition at line 330 of file stm32f7xx_hal_sd.h.

Referenced by SD_PowerON().

#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)

Sends an addressed card into the inactive state.

Definition at line 347 of file stm32f7xx_hal_sd.h.

#define SD_CMD_GO_IRQ_STATE ((uint8_t)40)

SD card doesn't support it (Reserved).

Definition at line 374 of file stm32f7xx_hal_sd.h.

#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)

Definition at line 346 of file stm32f7xx_hal_sd.h.

#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)

64 bytes tuning pattern is sent for SDR50 and SDR104.

Definition at line 355 of file stm32f7xx_hal_sd.h.

#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)

Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage.

Definition at line 339 of file stm32f7xx_hal_sd.h.

#define SD_CMD_HS_SWITCH ((uint8_t)6)

Checks switchable function (mode 0) and switch card function (mode 1).

Definition at line 337 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_HighSpeed().

#define SD_CMD_LOCK_UNLOCK ((uint8_t)42)

Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.

Definition at line 375 of file stm32f7xx_hal_sd.h.

#define SD_CMD_NO_CMD ((uint8_t)64)

Definition at line 381 of file stm32f7xx_hal_sd.h.

#define SD_CMD_PROG_CID ((uint8_t)26)

Reserved for manufacturers.

Definition at line 361 of file stm32f7xx_hal_sd.h.

#define SD_CMD_PROG_CSD ((uint8_t)27)

Programming of the programmable bits of the CSD.

Definition at line 362 of file stm32f7xx_hal_sd.h.

#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11)

SD card doesn't support it.

Definition at line 343 of file stm32f7xx_hal_sd.h.

#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18)

Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command.

Definition at line 353 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), and HAL_SD_ReadBlocks_DMA().

#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)

Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.

Definition at line 351 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks(), and HAL_SD_ReadBlocks_DMA().

#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)

For SD card only

Definition at line 412 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)

For SD card only

Definition at line 408 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)

For SD card only

Definition at line 406 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_GET_MID ((uint8_t)44)

For SD card only

Definition at line 404 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43)

Following commands are SD Card Specific security commands.

SD_CMD_APP_CMD should be sent before sending these commands. For SD card only

Definition at line 403 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_OP_COND ((uint8_t)41)

(ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.

Definition at line 392 of file stm32f7xx_hal_sd.h.

Referenced by SD_PowerON().

#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)

For SD card only

Definition at line 411 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)

For SD card only

Definition at line 409 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)

For SD card only

Definition at line 413 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)

For SD card only

Definition at line 410 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)

(ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.

Definition at line 390 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)

Reads the SD Configuration Register (SCR).

Definition at line 395 of file stm32f7xx_hal_sd.h.

Referenced by SD_FindSCR().

#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)

For SD card only

Definition at line 407 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)

For SD card only

Definition at line 405 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)

(ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card.

Definition at line 394 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SD_APP_STATUS ((uint8_t)13)

(ACMD13) Sends the SD status.

Definition at line 389 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_SendSDStatus().

#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33)

Sets the address of the last write block of the continuous range to be erased.

Definition at line 367 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase().

#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32)

Sets the address of the first write block to be erased. (For SD card only).

Definition at line 366 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase().

#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52)

For SD I/O card only, reserved for security specification.

Definition at line 396 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53)

For SD I/O card only, reserved for security specification.

Definition at line 397 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5)

Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.

Definition at line 335 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7)

Selects the card by its own relative address and gets deselected by any other address

Definition at line 338 of file stm32f7xx_hal_sd.h.

Referenced by SD_Select_Deselect().

#define SD_CMD_SEND_CID ((uint8_t)10)

Addressed card sends its card identification (CID) on the CMD line.

Definition at line 342 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SEND_CSD ((uint8_t)9)

Addressed card sends its card specific data (CSD) on the CMD line.

Definition at line 341 of file stm32f7xx_hal_sd.h.

Referenced by SD_Initialize_Cards().

#define SD_CMD_SEND_OP_COND ((uint8_t)1)

Sends host capacity support information and activates the card's initialization process.

Definition at line 331 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SEND_STATUS ((uint8_t)13)

Addressed card sends its status register.

Definition at line 345 of file stm32f7xx_hal_sd.h.

Referenced by SD_IsCardProgramming(), and SD_SendStatus().

#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30)

Asks the card to send the status of the write protection bits.

Definition at line 365 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23)

Specify block count for CMD18 and CMD25.

Definition at line 357 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SET_BLOCKLEN ((uint8_t)16)

Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC.

Definition at line 348 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), and SD_FindSCR().

#define SD_CMD_SET_DSR ((uint8_t)4)

Programs the DSR of all cards.

Definition at line 334 of file stm32f7xx_hal_sd.h.

#define SD_CMD_SET_REL_ADDR ((uint8_t)3)

Asks the card to publish a new relative address (RCA).

Definition at line 333 of file stm32f7xx_hal_sd.h.

Referenced by SD_Initialize_Cards().

#define SD_CMD_SET_WRITE_PROT ((uint8_t)28)

Sets the write protection bit of the addressed group.

Definition at line 363 of file stm32f7xx_hal_sd.h.

#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12)

Forces the card to stop transmission.

Definition at line 344 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_StopTransfer().

#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20)

Speed class control command.

Definition at line 356 of file stm32f7xx_hal_sd.h.

#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)

Continuously writes blocks of data until a STOP_TRANSMISSION follows.

Definition at line 360 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks(), and HAL_SD_WriteBlocks_DMA().

#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)

Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.

Definition at line 358 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_WriteBlocks(), and HAL_SD_WriteBlocks_DMA().

#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)

Definition at line 422 of file stm32f7xx_hal_sd.h.

Referenced by SD_Initialize_Cards().

#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)

Definition at line 424 of file stm32f7xx_hal_sd.h.

Referenced by SD_Initialize_Cards().

#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)

Supported SD Memory Cards.

Definition at line 418 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_Get_CardInfo(), HAL_SD_ReadBlocks(), HAL_SD_WideBusOperation_Config(), HAL_SD_WriteBlocks(), and SD_Initialize_Cards().

#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)

Definition at line 419 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_Erase(), HAL_SD_Get_CardInfo(), HAL_SD_ReadBlocks(), HAL_SD_WideBusOperation_Config(), HAL_SD_WriteBlocks(), SD_Initialize_Cards(), and SD_PowerON().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Exported Macros

Defines
SD Exported Macros
SD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
Enable the SD device.
#define | __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
Disable the SD device.
#define | __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
Enable the SDMMC DMA transfer.
#define | __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
Disable the SDMMC DMA transfer.
#define | __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the SD device interrupt.
#define | __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the SD device interrupt.
#define | __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified SD flag is set or not.
#define | __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the SD's pending flags.
#define | __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified SD interrupt has occurred or not.
#define | __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the SD's interrupt pending bits.

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_SD_SDMMC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

Clear the SD's pending flags.

Parameters:
__HANDLE__,: SD Handle
__FLAG__,: specifies the flag to clear. This parameter can be one or a combination of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_SDIOIT: SD I/O interrupt received
Return values:
None

Definition at line 571 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_HighSpeed(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), SD_CmdError(), SD_CmdResp1Error(), SD_CmdResp2Error(), SD_CmdResp3Error(), SD_CmdResp6Error(), SD_CmdResp7Error(), SD_FindSCR(), and SD_IsCardProgramming().

#define __HAL_SD_SDMMC_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Clear the SD's interrupt pending bits.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
Return values:
None

Definition at line 621 of file stm32f7xx_hal_sd.h.

#define __HAL_SD_SDMMC_DISABLE ( __HANDLE__ ) __SDMMC_DISABLE((__HANDLE__)->Instance)

Disable the SD device.

Return values:
None

Definition at line 446 of file stm32f7xx_hal_sd.h.

Referenced by SD_PowerON().

#define __HAL_SD_SDMMC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Disable the SD device interrupt.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be disabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_CMDACT: Command transfer in progress interrupt
  • SDMMC_IT_TXACT: Data transmit in progress interrupt
  • SDMMC_IT_RXACT: Data receive in progress interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
Return values:
None

Definition at line 520 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_IRQHandler().

#define __HAL_SD_SDMMC_DMA_DISABLE ( __HANDLE__ ) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)

Disable the SDMMC DMA transfer.

Return values:
None

Definition at line 458 of file stm32f7xx_hal_sd.h.

#define __HAL_SD_SDMMC_DMA_ENABLE ( __HANDLE__ ) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)

Enable the SDMMC DMA transfer.

Return values:
None

Definition at line 452 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

#define __HAL_SD_SDMMC_ENABLE ( __HANDLE__ ) __SDMMC_ENABLE((__HANDLE__)->Instance)

Enable the SD device.

Return values:
None

Definition at line 440 of file stm32f7xx_hal_sd.h.

Referenced by SD_PowerON().

#define __HAL_SD_SDMMC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Enable the SD device interrupt.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt sources to be enabled. This parameter can be one or a combination of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_CMDACT: Command transfer in progress interrupt
  • SDMMC_IT_TXACT: Data transmit in progress interrupt
  • SDMMC_IT_RXACT: Data receive in progress interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
Return values:
None

Definition at line 489 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

#define __HAL_SD_SDMMC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

Check whether the specified SD flag is set or not.

Parameters:
__HANDLE__,: SD Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDMMC_FLAG_CTIMEOUT: Command response timeout
  • SDMMC_FLAG_DTIMEOUT: Data timeout
  • SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDMMC_FLAG_RXOVERR: Received FIFO overrun error
  • SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
  • SDMMC_FLAG_CMDSENT: Command sent (no response required)
  • SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
  • SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDMMC_FLAG_CMDACT: Command transfer in progress
  • SDMMC_FLAG_TXACT: Data transmit in progress
  • SDMMC_FLAG_RXACT: Data receive in progress
  • SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDMMC_FLAG_TXFIFOF: Transmit FIFO full
  • SDMMC_FLAG_RXFIFOF: Receive FIFO full
  • SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
  • SDMMC_FLAG_RXFIFOE: Receive FIFO empty
  • SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
  • SDMMC_FLAG_RXDAVL: Data available in receive FIFO
  • SDMMC_FLAG_SDIOIT: SD I/O interrupt received
Return values:
The new state of SD FLAG (SET or RESET).

Definition at line 551 of file stm32f7xx_hal_sd.h.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_HighSpeed(), HAL_SD_IRQHandler(), HAL_SD_ReadBlocks(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), SD_CmdError(), SD_CmdResp1Error(), SD_CmdResp2Error(), SD_CmdResp3Error(), SD_CmdResp6Error(), SD_CmdResp7Error(), SD_FindSCR(), and SD_IsCardProgramming().

#define __HAL_SD_SDMMC_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

Check whether the specified SD interrupt has occurred or not.

Parameters:
__HANDLE__,: SD Handle
__INTERRUPT__,: specifies the SDMMC interrupt source to check. This parameter can be one of the following values:
  • SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDMMC_IT_CTIMEOUT: Command response timeout interrupt
  • SDMMC_IT_DTIMEOUT: Data timeout interrupt
  • SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
  • SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDMMC_IT_CMDACT: Command transfer in progress interrupt
  • SDMMC_IT_TXACT: Data transmit in progress interrupt
  • SDMMC_IT_RXACT: Data receive in progress interrupt
  • SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
  • SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
Return values:
The new state of SD IT (SET or RESET).

Definition at line 602 of file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SD Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_Init (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize the SD
    card device to be ready for use.

Function Documentation

HAL_StatusTypeDef HAL_SD_DeInit ( SD_HandleTypeDef * hsd )

De-Initializes the SD card.

Parameters:
hsd,: SD handle
Return values:
HAL status

Definition at line 396 of file stm32f7xx_hal_sd.c.

References HAL_SD_MspDeInit(), and SD_PowerOFF().

HAL_SD_ErrorTypedef HAL_SD_Init | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypedef * | SDCardInfo
 | ) |  |

Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and create the associated handle.

Parameters:
hsd,: SD handle
SDCardInfo,: HAL_SD_CardInfoTypedef structure for SD card information
Return values:
HAL SD error state

Definition at line 338 of file stm32f7xx_hal_sd.c.

References HAL_SD_Get_CardInfo(), HAL_SD_MspInit(), SD_HandleTypeDef::Init, SD_HandleTypeDef::Instance, SD_HandleTypeDef::Lock, HAL_SD_CardInfoTypedef::RCA, SD_Initialize_Cards(), SD_InitTypeDef, SD_OK, SD_PowerON(), and SD_Select_Deselect().

void HAL_SD_MspDeInit ( SD_HandleTypeDef * hsd )

De-Initialize SD MSP.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 429 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_DeInit().

void HAL_SD_MspInit ( SD_HandleTypeDef * hsd )

Initializes the SD MSP.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 414 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_Init().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
SD Exported Functions

Data transfer functions. More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Allows to write block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_CheckReadOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data read transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_CheckWriteOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data write transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_XferCpltCallback (SD_HandleTypeDef *hsd)
SD end of transfer callback.
__weak void | HAL_SD_XferErrorCallback (SD_HandleTypeDef *hsd)
SD Transfer Error callback.
__weak void | HAL_SD_DMA_RxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Rx callback in non blocking mode.
__weak void | HAL_SD_DMA_RxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx error callback.
__weak void | HAL_SD_DMA_TxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Tx callback in non blocking mode.
__weak void | HAL_SD_DMA_TxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete error Tx callback.

Detailed Description

Data transfer functions.

  ==============================================================================
                        ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the data
    transfer from/to SD card.

Function Documentation

HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | Timeout
 | ) |  |

This function waits until the SD DMA data read transfer is finished.

This API should be called after HAL_SD_ReadBlocks_DMA() function to insure that all data sent by the card is already transferred by the DMA controller.

Parameters:
hsd,: SD handle
Timeout,: Timeout duration
Return values:
SD Card error state

Definition at line 1086 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::DmaTransferCplt, HAL_SD_StopTransfer(), SD_DATA_TIMEOUT, SD_OK, SD_READ_MULTIPLE_BLOCK, SDMMC_STATIC_FLAGS, SD_HandleTypeDef::SdOperation, SD_HandleTypeDef::SdTransferCplt, and SD_HandleTypeDef::SdTransferErr.

HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | Timeout
 | ) |  |

This function waits until the SD DMA data write transfer is finished.

This API should be called after HAL_SD_WriteBlocks_DMA() function to insure that all data sent by the card is already transferred by the DMA controller.

Parameters:
hsd,: SD handle
Timeout,: Timeout duration
Return values:
SD Card error state

Definition at line 1146 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::DmaTransferCplt, HAL_SD_GetStatus(), HAL_SD_StopTransfer(), SD_DATA_TIMEOUT, SD_OK, SD_TRANSFER_OK, SD_WRITE_MULTIPLE_BLOCK, SDMMC_STATIC_FLAGS, SD_HandleTypeDef::SdOperation, SD_HandleTypeDef::SdTransferCplt, and SD_HandleTypeDef::SdTransferErr.

void HAL_SD_DMA_RxCpltCallback ( DMA_HandleTypeDef * hdma )

SD Transfer complete Rx callback in non blocking mode.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1409 of file stm32f7xx_hal_sd.c.

Referenced by SD_DMA_RxCplt().

void HAL_SD_DMA_RxErrorCallback ( DMA_HandleTypeDef * hdma )

SD DMA transfer complete Rx error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1425 of file stm32f7xx_hal_sd.c.

Referenced by SD_DMA_RxError().

void HAL_SD_DMA_TxCpltCallback ( DMA_HandleTypeDef * hdma )

SD Transfer complete Tx callback in non blocking mode.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1441 of file stm32f7xx_hal_sd.c.

Referenced by SD_DMA_TxCplt().

void HAL_SD_DMA_TxErrorCallback ( DMA_HandleTypeDef * hdma )

SD DMA transfer complete error Tx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1457 of file stm32f7xx_hal_sd.c.

Referenced by SD_DMA_TxError().

HAL_SD_ErrorTypedef HAL_SD_Erase | ( | SD_HandleTypeDef * | hsd,
 |  | uint64_t | startaddr,
 |  | uint64_t | endaddr
 | ) |  |

Erases the specified memory area of the given SD card.

Parameters:
hsd,: SD handle
startaddr,: Start byte address
endaddr,: End byte address
Return values:
SD Card error state

Definition at line 1209 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::CardType, SD_HandleTypeDef::CSD, HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_CARD_LOCKED, SD_CARD_PROGRAMMING, SD_CARD_RECEIVING, SD_CCCC_ERASE, SD_CMD_ERASE, SD_CMD_SD_ERASE_GRP_END, SD_CMD_SD_ERASE_GRP_START, SD_CmdResp1Error(), SD_DATATIMEOUT, SD_IsCardProgramming(), SD_LOCK_UNLOCK_FAILED, SD_OK, SD_REQUEST_NOT_APPLICABLE, STD_CAPACITY_SD_CARD_V1_1, and STD_CAPACITY_SD_CARD_V2_0.

void HAL_SD_IRQHandler ( SD_HandleTypeDef * hsd )

This function handles SD card interrupt request.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 1313 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_DISABLE_IT, __HAL_SD_SDMMC_GET_FLAG, HAL_SD_XferCpltCallback(), HAL_SD_XferErrorCallback(), SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_OK, SD_RX_OVERRUN, SD_TX_UNDERRUN, SD_HandleTypeDef::SdTransferCplt, and SD_HandleTypeDef::SdTransferErr.

HAL_SD_ErrorTypedef HAL_SD_ReadBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pReadBuffer,
 |  | uint64_t | ReadAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by polling mode.

Parameters:
hsd,: SD handle
pReadBuffer,: pointer to the buffer that will contain the received data
ReadAddr,: Address from where data is to be read
BlockSize,: SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of SD blocks to read
Return values:
SD Card error state

Definition at line 469 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::CardType, DATA_BLOCK_SIZE, HAL_SD_StopTransfer(), HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_CMD_READ_MULT_BLOCK, SD_CMD_READ_SINGLE_BLOCK, SD_CMD_SET_BLOCKLEN, SD_CmdResp1Error(), SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_OK, SD_RX_OVERRUN, SDMMC_STATIC_FLAGS, STD_CAPACITY_SD_CARD_V1_1, and STD_CAPACITY_SD_CARD_V2_0.

HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pReadBuffer,
 |  | uint64_t | ReadAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by the function HAL_SD_CheckReadOperation() to check the completion of the read process
Parameters:
hsd,: SD handle
pReadBuffer,: Pointer to the buffer that will contain the received data
ReadAddr,: Address from where data is to be read
BlockSize,: SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of blocks to read.
Return values:
SD Card error state

Definition at line 855 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_DMA_ENABLE, __HAL_SD_SDMMC_ENABLE_IT, SD_HandleTypeDef::CardType, SD_HandleTypeDef::DmaTransferCplt, HAL_DMA_Start_IT(), SD_HandleTypeDef::hdmarx, HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_CMD_READ_MULT_BLOCK, SD_CMD_READ_SINGLE_BLOCK, SD_CMD_SET_BLOCKLEN, SD_CmdResp1Error(), SD_DATATIMEOUT, SD_DMA_RxCplt(), SD_DMA_RxError(), SD_OK, SD_READ_MULTIPLE_BLOCK, SD_READ_SINGLE_BLOCK, SD_HandleTypeDef::SdOperation, SD_HandleTypeDef::SdTransferCplt, SD_HandleTypeDef::SdTransferErr, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_SD_ErrorTypedef HAL_SD_WriteBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pWriteBuffer,
 |  | uint64_t | WriteAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to write block(s) to a specified address in a card.

The Data transfer is managed by polling mode.

Parameters:
hsd,: SD handle
pWriteBuffer,: pointer to the buffer that will contain the data to transmit
WriteAddr,: Address from where data is to be written
BlockSize,: SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of SD blocks to write
Return values:
SD Card error state

Definition at line 645 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::CardType, HAL_SD_StopTransfer(), HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_CARD_PROGRAMMING, SD_CARD_RECEIVING, SD_CMD_SET_BLOCKLEN, SD_CMD_WRITE_MULT_BLOCK, SD_CMD_WRITE_SINGLE_BLOCK, SD_CmdResp1Error(), SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_IsCardProgramming(), SD_OK, SD_TX_UNDERRUN, SDMMC_STATIC_FLAGS, STD_CAPACITY_SD_CARD_V1_1, and STD_CAPACITY_SD_CARD_V2_0.

HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pWriteBuffer,
 |  | uint64_t | WriteAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by the function HAL_SD_CheckWriteOperation() to check the completion of the write process (by SD current status polling).
Parameters:
hsd,: SD handle
pWriteBuffer,: pointer to the buffer that will contain the data to transmit
WriteAddr,: Address from where data is to be read
BlockSize,: the SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of blocks to write
Return values:
SD Card error state

Definition at line 971 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_DMA_ENABLE, __HAL_SD_SDMMC_ENABLE_IT, SD_HandleTypeDef::CardType, SD_HandleTypeDef::DmaTransferCplt, HAL_DMA_Start_IT(), SD_HandleTypeDef::hdmatx, HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Instance, SD_CMD_SET_BLOCKLEN, SD_CMD_WRITE_MULT_BLOCK, SD_CMD_WRITE_SINGLE_BLOCK, SD_CmdResp1Error(), SD_DATATIMEOUT, SD_DMA_TxCplt(), SD_DMA_TxError(), SD_OK, SD_WRITE_MULTIPLE_BLOCK, SD_WRITE_SINGLE_BLOCK, SD_HandleTypeDef::SdOperation, SD_HandleTypeDef::SdTransferCplt, SD_HandleTypeDef::SdTransferErr, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

void HAL_SD_XferCpltCallback ( SD_HandleTypeDef * hsd )

SD end of transfer callback.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 1378 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

void HAL_SD_XferErrorCallback ( SD_HandleTypeDef * hsd )

SD Transfer Error callback.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 1393 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SD Exported Functions

management functions More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_Get_CardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
Returns information about specific card.
HAL_SD_ErrorTypedef | HAL_SD_WideBusOperation_Config (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_ErrorTypedef | HAL_SD_StopTransfer (SD_HandleTypeDef *hsd)
Aborts an ongoing data transfer.
HAL_SD_ErrorTypedef | HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.

Detailed Description

management functions

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the SD card
    operations.

Function Documentation

HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypedef * | pCardInfo
 | ) |  |

Returns information about specific card.

Parameters:
hsd,: SD handle
pCardInfo,: Pointer to a HAL_SD_CardInfoTypedef structure that contains all SD cardinformation
Return values:
SD Card error state

< Reserved

Definition at line 1493 of file stm32f7xx_hal_sd.c.

References HAL_SD_CardInfoTypedef::CardBlockSize, HAL_SD_CardInfoTypedef::CardCapacity, HAL_SD_CSDTypedef::CardComdClasses, SD_HandleTypeDef::CardType, HAL_SD_CardInfoTypedef::CardType, SD_HandleTypeDef::CID, HAL_SD_CIDTypedef::CID_CRC, HAL_SD_CSDTypedef::ContentProtectAppli, HAL_SD_CSDTypedef::CopyFlag, SD_HandleTypeDef::CSD, HAL_SD_CSDTypedef::CSD_CRC, HAL_SD_CSDTypedef::CSDStruct, HAL_SD_CSDTypedef::DeviceSize, HAL_SD_CSDTypedef::DeviceSizeMul, HAL_SD_CSDTypedef::DSRImpl, HAL_SD_CSDTypedef::ECC, HAL_SD_CSDTypedef::EraseGrMul, HAL_SD_CSDTypedef::EraseGrSize, HAL_SD_CSDTypedef::FileFormat, HAL_SD_CSDTypedef::FileFormatGrouop, HIGH_CAPACITY_SD_CARD, HAL_SD_CSDTypedef::ManDeflECC, HAL_SD_CIDTypedef::ManufactDate, HAL_SD_CIDTypedef::ManufacturerID, HAL_SD_CSDTypedef::MaxBusClkFrec, HAL_SD_CSDTypedef::MaxRdCurrentVDDMax, HAL_SD_CSDTypedef::MaxRdCurrentVDDMin, HAL_SD_CSDTypedef::MaxWrBlockLen, HAL_SD_CSDTypedef::MaxWrCurrentVDDMax, HAL_SD_CSDTypedef::MaxWrCurrentVDDMin, HAL_SD_CSDTypedef::NSAC, HAL_SD_CIDTypedef::OEM_AppliID, HAL_SD_CSDTypedef::PartBlockRead, HAL_SD_CSDTypedef::PermWrProtect, HAL_SD_CIDTypedef::ProdName1, HAL_SD_CIDTypedef::ProdName2, HAL_SD_CIDTypedef::ProdRev, HAL_SD_CIDTypedef::ProdSN, SD_HandleTypeDef::RCA, HAL_SD_CardInfoTypedef::RCA, HAL_SD_CSDTypedef::RdBlockLen, HAL_SD_CSDTypedef::RdBlockMisalign, HAL_SD_CSDTypedef::Reserved1, HAL_SD_CIDTypedef::Reserved1, HAL_SD_CSDTypedef::Reserved2, HAL_SD_CIDTypedef::Reserved2, HAL_SD_CSDTypedef::Reserved3, HAL_SD_CSDTypedef::Reserved4, HAL_SD_CardInfoTypedef::SD_cid, HAL_SD_CardInfoTypedef::SD_csd, SD_ERROR, SD_OK, STD_CAPACITY_SD_CARD_V1_1, STD_CAPACITY_SD_CARD_V2_0, HAL_SD_CSDTypedef::SysSpecVersion, HAL_SD_CSDTypedef::TAAC, HAL_SD_CSDTypedef::TempWrProtect, HAL_SD_CSDTypedef::WrBlockMisalign, HAL_SD_CSDTypedef::WriteBlockPaPartial, HAL_SD_CSDTypedef::WrProtectGrEnable, HAL_SD_CSDTypedef::WrProtectGrSize, and HAL_SD_CSDTypedef::WrSpeedFact.

Referenced by HAL_SD_Init().

HAL_SD_ErrorTypedef HAL_SD_HighSpeed ( SD_HandleTypeDef * hsd )

Switches the SD card to High Speed mode.

This API must be used after "Transfer State"

Note:
This operation should be followed by the configuration of PLL to have SDMMCCK clock between 67 and 75 MHz
Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 1790 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::Instance, SD_ALLZERO, SD_CMD_HS_SWITCH, SD_CMD_SET_BLOCKLEN, SD_CmdResp1Error(), SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_FindSCR(), SD_OK, SD_RX_OVERRUN, SD_UNSUPPORTED_FEATURE, and SDMMC_STATIC_FLAGS.

HAL_SD_ErrorTypedef HAL_SD_StopTransfer ( SD_HandleTypeDef * hsd )

Aborts an ongoing data transfer.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 1763 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::Instance, SD_CMD_STOP_TRANSMISSION, SD_CmdResp1Error(), and SD_OK.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_ReadBlocks(), and HAL_SD_WriteBlocks().

HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | WideMode
 | ) |  |

Enables wide bus operation for the requested card if supported by card.

Parameters:
hsd,: SD handle
WideMode,: Specifies the SD card wide bus mode This parameter can be one of the following values:
  • SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
  • SDMMC_BUS_WIDE_4B: 4-bit data transfer
  • SDMMC_BUS_WIDE_1B: 1-bit data transfer
Return values:
SD Card error state

Definition at line 1709 of file stm32f7xx_hal_sd.c.

References SD_HandleTypeDef::CardType, HIGH_CAPACITY_SD_CARD, SD_HandleTypeDef::Init, SD_HandleTypeDef::Instance, MULTIMEDIA_CARD, SD_INVALID_PARAMETER, SD_OK, SD_UNSUPPORTED_FEATURE, SD_WideBus_Disable(), SD_WideBus_Enable(), STD_CAPACITY_SD_CARD_V1_1, and STD_CAPACITY_SD_CARD_V2_0.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SD Exported Functions

Peripheral State functions. More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Returns the current SD card's status.
HAL_SD_TransferStateTypedef | HAL_SD_GetStatus (SD_HandleTypeDef *hsd)
Gets the current sd card data status.
HAL_SD_ErrorTypedef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
Gets the SD card status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in runtime the status of the peripheral
    and the data flow.

Function Documentation

HAL_SD_ErrorTypedef HAL_SD_GetCardStatus | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardStatusTypedef * | pCardStatus
 | ) |  |

Gets the SD card status.

Parameters:
hsd,: SD handle
pCardStatus,: Pointer to the HAL_SD_CardStatusTypedef structure that will contain the SD card status information
Return values:
SD Card error state

Definition at line 2102 of file stm32f7xx_hal_sd.c.

References HAL_SD_CardStatusTypedef::AU_SIZE, HAL_SD_CardStatusTypedef::DAT_BUS_WIDTH, HAL_SD_CardStatusTypedef::ERASE_OFFSET, HAL_SD_CardStatusTypedef::ERASE_SIZE, HAL_SD_CardStatusTypedef::ERASE_TIMEOUT, HAL_SD_SendSDStatus(), HAL_SD_CardStatusTypedef::PERFORMANCE_MOVE, HAL_SD_CardStatusTypedef::SD_CARD_TYPE, SD_OK, HAL_SD_CardStatusTypedef::SECURED_MODE, HAL_SD_CardStatusTypedef::SIZE_OF_PROTECTED_AREA, and HAL_SD_CardStatusTypedef::SPEED_CLASS.

HAL_SD_TransferStateTypedef HAL_SD_GetStatus ( SD_HandleTypeDef * hsd )

Gets the current sd card data status.

Parameters:
hsd,: SD handle
Return values:
Data Transfer state

Definition at line 2073 of file stm32f7xx_hal_sd.c.

References SD_CARD_ERROR, SD_CARD_TRANSFER, SD_GetState(), SD_TRANSFER_BUSY, SD_TRANSFER_ERROR, and SD_TRANSFER_OK.

Referenced by HAL_SD_CheckWriteOperation().

HAL_SD_ErrorTypedef HAL_SD_SendSDStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSDstatus
 | ) |  |

Returns the current SD card's status.

Parameters:
hsd,: SD handle
pSDstatus,: Pointer to the buffer that will contain the SD card status SD Status register)
Return values:
SD Card error state

Definition at line 1945 of file stm32f7xx_hal_sd.c.

References __HAL_SD_SDMMC_CLEAR_FLAG, __HAL_SD_SDMMC_GET_FLAG, SD_HandleTypeDef::Instance, SD_HandleTypeDef::RCA, SD_CARD_LOCKED, SD_CMD_APP_CMD, SD_CMD_SD_APP_STATUS, SD_CMD_SET_BLOCKLEN, SD_CmdResp1Error(), SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_LOCK_UNLOCK_FAILED, SD_OK, SD_RX_OVERRUN, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_GetCardStatus().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Types

SD Private Types
SD
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Defines

Defines
SD Private Defines
SD

Defines

#define | DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
SDMMC Data block size.
#define | SDMMC_STATIC_FLAGS
SDMMC Static flags, Timeout, FIFO Address.
#define | SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)
#define | SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
Mask for errors Card Status R1 (OCR Register)
#define | SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define | SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define | SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define | SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define | SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define | SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define | SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define | SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define | SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define | SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define | SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define | SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define | SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define | SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define | SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define | SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define | SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define | SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define | SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define | SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
Masks for R6 Response.
#define | SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define | SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define | SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define | SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define | SD_STD_CAPACITY ((uint32_t)0x00000000)
#define | SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define | SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define | SD_ALLZERO ((uint32_t)0x00000000)
#define | SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define | SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define | SD_CARD_LOCKED ((uint32_t)0x02000000)
#define | SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define | SD_0TO7BITS ((uint32_t)0x000000FF)
#define | SD_8TO15BITS ((uint32_t)0x0000FF00)
#define | SD_16TO23BITS ((uint32_t)0x00FF0000)
#define | SD_24TO31BITS ((uint32_t)0xFF000000)
#define | SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define | SD_HALFFIFO ((uint32_t)0x00000008)
#define | SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define | SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
Command Class Supported.
#define | SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define | SD_CCCC_ERASE ((uint32_t)0x00000020)
#define | SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
Following commands are SD Card Specific commands.

Define Documentation

#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))

SDMMC Data block size.

Definition at line 200 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_ReadBlocks().

#define SD_0TO7BITS ((uint32_t)0x000000FF)

Definition at line 255 of file stm32f7xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_16TO23BITS ((uint32_t)0x00FF0000)

Definition at line 257 of file stm32f7xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_24TO31BITS ((uint32_t)0xFF000000)

Definition at line 258 of file stm32f7xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_8TO15BITS ((uint32_t)0x0000FF00)

Definition at line 256 of file stm32f7xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_ALLZERO ((uint32_t)0x00000000)

Definition at line 248 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_HighSpeed(), SD_CmdResp1Error(), SD_CmdResp6Error(), SD_IsCardProgramming(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define SD_CARD_LOCKED ((uint32_t)0x02000000)

Definition at line 252 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_Erase(), HAL_SD_SendSDStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define SD_CCCC_ERASE ((uint32_t)0x00000020)

Definition at line 269 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_Erase().

#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)

Command Class Supported.

Definition at line 267 of file stm32f7xx_hal_sd.c.

#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)

Definition at line 268 of file stm32f7xx_hal_sd.c.

#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)

Definition at line 245 of file stm32f7xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)

Definition at line 254 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_Erase(), HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), and SD_FindSCR().

#define SD_HALFFIFO ((uint32_t)0x00000008)

Definition at line 261 of file stm32f7xx_hal_sd.c.

#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)

Definition at line 262 of file stm32f7xx_hal_sd.c.

#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)

Definition at line 243 of file stm32f7xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)

Definition at line 259 of file stm32f7xx_hal_sd.c.

#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)

Definition at line 247 of file stm32f7xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)

Definition at line 215 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)

Mask for errors Card Status R1 (OCR Register)

Definition at line 214 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)

Definition at line 232 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)

Definition at line 218 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)

Definition at line 216 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)

Definition at line 230 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)

Definition at line 223 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)

Definition at line 224 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)

Definition at line 228 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)

Definition at line 221 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)

Definition at line 231 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)

Definition at line 217 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)

Definition at line 233 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)

Definition at line 225 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)

Definition at line 222 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)

Definition at line 220 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)

Definition at line 226 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)

Definition at line 227 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)

Definition at line 229 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)

Definition at line 219 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)

Definition at line 240 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp6Error().

#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)

Masks for R6 Response.

Definition at line 238 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp6Error().

#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)

Definition at line 239 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdResp6Error().

#define SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)

Following commands are SD Card Specific commands.

SDMMC_APP_CMD should be sent before sending these commands.

Definition at line 275 of file stm32f7xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)

Definition at line 251 of file stm32f7xx_hal_sd.c.

Referenced by SD_WideBus_Disable().

#define SD_STD_CAPACITY ((uint32_t)0x00000000)

Definition at line 244 of file stm32f7xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)

Definition at line 242 of file stm32f7xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)

Definition at line 250 of file stm32f7xx_hal_sd.c.

Referenced by SD_WideBus_Enable().

#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)

Definition at line 209 of file stm32f7xx_hal_sd.c.

Referenced by SD_CmdError(), and SD_CmdResp7Error().

#define SDMMC_STATIC_FLAGS
Value:
((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
                                                    SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
                                                    SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
                                                    SDMMC_FLAG_DBCKEND))

SDMMC Static flags, Timeout, FIFO Address.

Definition at line 204 of file stm32f7xx_hal_sd.c.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), SD_CmdError(), SD_CmdResp1Error(), SD_CmdResp2Error(), SD_CmdResp3Error(), SD_CmdResp6Error(), SD_FindSCR(), and SD_IsCardProgramming().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Variables

SD Private Variables
SD
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Constants

SD Private Constants
SD
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Macros

SD Private Macros
SD
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Private Functions Prototypes

SD Private Functions Prototypes
SD
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SDRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SDRAM Initialization and de_initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the SDRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SDRAM_DeInit ( SDRAM_HandleTypeDef * hsdram )

Perform the SDRAM device initialization sequence.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 175 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_MspDeInit(), HAL_SDRAM_STATE_RESET, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

void HAL_SDRAM_DMA_XferCpltCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 265 of file stm32f7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

void HAL_SDRAM_DMA_XferErrorCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 280 of file stm32f7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

HAL_StatusTypeDef HAL_SDRAM_Init | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | FMC_SDRAM_TimingTypeDef * | Timing
 | ) |  |

Performs the SDRAM device initialization sequence.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Timing,: Pointer to SDRAM control timing structure
Return values:
HAL status

Definition at line 138 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_MspInit(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, HAL_SDRAM_STATE_RESET, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, SDRAM_HandleTypeDef::Lock, and SDRAM_HandleTypeDef::State.

void HAL_SDRAM_IRQHandler ( SDRAM_HandleTypeDef * hsdram )

This function handles SDRAM refresh error interrupt request.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 230 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_RefreshErrorCallback(), and SDRAM_HandleTypeDef::Instance.

void HAL_SDRAM_MspDeInit ( SDRAM_HandleTypeDef * hsdram )

SDRAM MSP DeInit.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 214 of file stm32f7xx_hal_sdram.c.

Referenced by HAL_SDRAM_DeInit().

void HAL_SDRAM_MspInit ( SDRAM_HandleTypeDef * hsdram )

SDRAM MSP Init.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 198 of file stm32f7xx_hal_sdram.c.

Referenced by HAL_SDRAM_Init().

void HAL_SDRAM_RefreshErrorCallback ( SDRAM_HandleTypeDef * hsdram )

SDRAM Refresh error callback.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
None

Definition at line 249 of file stm32f7xx_hal_sdram.c.

Referenced by HAL_SDRAM_IRQHandler().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
SDRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### SDRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SDRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SDRAM_Read_16b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 16-bit data buffer from the SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 402 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_32b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 32-bit data buffer from the SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 485 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_8b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 8-bit data buffer from the SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 317 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Read_DMA | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads a Words data from the SDRAM memory using DMA transfer.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 568 of file stm32f7xx_hal_sdram.c.

References HAL_DMA_Start_IT(), HAL_SDRAM_DMA_XferCpltCallback(), HAL_SDRAM_DMA_XferErrorCallback(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, SDRAM_HandleTypeDef::hdma, SDRAM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SDRAM_Write_16b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 16-bit data buffer to SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 442 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_32b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 32-bit data buffer to SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 525 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_8b | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 8-bit data buffer to SDRAM memory.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 358 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_Write_DMA | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes a Words data buffer to SDRAM memory using DMA transfer.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 609 of file stm32f7xx_hal_sdram.c.

References HAL_DMA_Start_IT(), HAL_SDRAM_DMA_XferCpltCallback(), HAL_SDRAM_DMA_XferErrorCallback(), HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_WRITE_PROTECTED, SDRAM_HandleTypeDef::hdma, SDRAM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Control functions

Functions
Control functions
SDRAM Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.

Detailed Description

management functions

  ==============================================================================
                         ##### SDRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SDRAM interface.

Function Documentation

uint32_t HAL_SDRAM_GetModeStatus ( SDRAM_HandleTypeDef * hsdram )

Returns the SDRAM memory current mode.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
The SDRAM memory mode.

Definition at line 807 of file stm32f7xx_hal_sdram.c.

References SDRAM_HandleTypeDef::Init, and SDRAM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t | RefreshRate
 | ) |  |

Programs the SDRAM Memory Refresh rate.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
RefreshRate,: The SDRAM refresh rate value
Return values:
HAL status

Definition at line 754 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_SendCommand | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | FMC_SDRAM_CommandTypeDef * | Command,
 |  | uint32_t | Timeout
 | ) |  |

Sends Command to the SDRAM bank.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Command,: SDRAM command structure
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 720 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_PRECHARGED, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber | ( | SDRAM_HandleTypeDef * | hsdram,
 |  | uint32_t | AutoRefreshNumber
 | ) |  |

Sets the Number of consecutive SDRAM Memory auto Refresh commands.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
AutoRefreshNumber,: The SDRAM auto Refresh number
Return values:
HAL status

Definition at line 781 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable ( SDRAM_HandleTypeDef * hsdram )

Disables dynamically SDRAM write protection.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 692 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_READY, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable ( SDRAM_HandleTypeDef * hsdram )

Enables dynamically SDRAM write protection.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL status

Definition at line 666 of file stm32f7xx_hal_sdram.c.

References HAL_SDRAM_STATE_BUSY, HAL_SDRAM_STATE_WRITE_PROTECTED, SDRAM_HandleTypeDef::Init, SDRAM_HandleTypeDef::Instance, and SDRAM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: State functions

Functions
State functions
SDRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SDRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SDRAM controller
    and the data flow.

Function Documentation

HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState ( SDRAM_HandleTypeDef * hsdram )

Returns the SDRAM state.

Parameters:
hsdram,: pointer to a SDRAM_HandleTypeDef structure that contains the configuration information for SDRAM module.
Return values:
HAL state

Definition at line 838 of file stm32f7xx_hal_sdram.c.

References SDRAM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SDRAM Exported Types

Data Structures | Enumerations
SDRAM Exported Types
SDRAM

Data Structures

struct SDRAM_HandleTypeDef
SDRAM handle Structure definition. More...

Enumerations

enum HAL_SDRAM_StateTypeDef {
HAL_SDRAM_STATE_RESET = 0x00, HAL_SDRAM_STATE_READY = 0x01, HAL_SDRAM_STATE_BUSY = 0x02, HAL_SDRAM_STATE_ERROR = 0x03,
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, HAL_SDRAM_STATE_PRECHARGED = 0x05
}
HAL SDRAM State structure definition. More...

Enumeration Type Documentation

enum HAL_SDRAM_StateTypeDef

HAL SDRAM State structure definition.

Enumerator:
HAL_SDRAM_STATE_RESET

SDRAM not yet initialized or disabled

HAL_SDRAM_STATE_READY

SDRAM initialized and ready for use

HAL_SDRAM_STATE_BUSY

SDRAM internal process is ongoing

HAL_SDRAM_STATE_ERROR

SDRAM error state

HAL_SDRAM_STATE_WRITE_PROTECTED

SDRAM device write protected

HAL_SDRAM_STATE_PRECHARGED

SDRAM device precharged

Definition at line 66 of file stm32f7xx_hal_sdram.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SDRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SDRAM_HandleTypeDef Struct Reference
SDRAM Exported Types

SDRAM handle Structure definition. More...

#include <stm32f7xx_hal_sdram.h>

Data Fields

FMC_SDRAM_TypeDef * | Instance
FMC_SDRAM_InitTypeDef | Init
__IO HAL_SDRAM_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * hdma

Detailed Description

SDRAM handle Structure definition.

Definition at line 80 of file stm32f7xx_hal_sdram.h.

Field Documentation

DMA_HandleTypeDef* SDRAM_HandleTypeDef::hdma

Pointer DMA handler

Definition at line 90 of file stm32f7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Read_DMA(), and HAL_SDRAM_Write_DMA().

FMC_SDRAM_InitTypeDef SDRAM_HandleTypeDef::Init

SDRAM device configuration parameters

Definition at line 84 of file stm32f7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetModeStatus(), HAL_SDRAM_Init(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

FMC_SDRAM_TypeDef* SDRAM_HandleTypeDef::Instance

Register base address

Definition at line 82 of file stm32f7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetModeStatus(), HAL_SDRAM_Init(), HAL_SDRAM_IRQHandler(), HAL_SDRAM_ProgramRefreshRate(), HAL_SDRAM_SendCommand(), HAL_SDRAM_SetAutoRefreshNumber(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

HAL_LockTypeDef SDRAM_HandleTypeDef::Lock

SDRAM locking object

Definition at line 88 of file stm32f7xx_hal_sdram.h.

Referenced by HAL_SDRAM_Init().

__IO HAL_SDRAM_StateTypeDef SDRAM_HandleTypeDef::State

SDRAM access state

Definition at line 86 of file stm32f7xx_hal_sdram.h.

Referenced by HAL_SDRAM_DeInit(), HAL_SDRAM_GetState(), HAL_SDRAM_Init(), HAL_SDRAM_ProgramRefreshRate(), HAL_SDRAM_Read_16b(), HAL_SDRAM_Read_32b(), HAL_SDRAM_Read_8b(), HAL_SDRAM_Read_DMA(), HAL_SDRAM_SendCommand(), HAL_SDRAM_SetAutoRefreshNumber(), HAL_SDRAM_Write_16b(), HAL_SDRAM_Write_32b(), HAL_SDRAM_Write_8b(), HAL_SDRAM_Write_DMA(), HAL_SDRAM_WriteProtection_Disable(), and HAL_SDRAM_WriteProtection_Enable().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sdram.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SDRAM Exported Macros

Defines
SDRAM Exported Macros
SDRAM

Defines

#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
Reset SDRAM handle state.

Define Documentation

#define __HAL_SDRAM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)

Reset SDRAM handle state.

Parameters:
__HANDLE__,: specifies the SDRAM handle.
Return values:
None

Definition at line 108 of file stm32f7xx_hal_sdram.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | TEACK_REACK_TIMEOUT 1000
#define | HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
#define | IS_SMARTCARD_PARITY(__PARITY__)
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
#define | IS_SMARTCARD_NACK(__NACK__)
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
#define | IS_SMARTCARD_ADVFEATURE_INIT(INIT)
#define | IS_SMARTCARD_ADVFEATURE_TXINV(TXINV)
#define | IS_SMARTCARD_ADVFEATURE_RXINV(RXINV)
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV)
#define | IS_SMARTCARD_ADVFEATURE_SWAP(SWAP)
#define | IS_SMARTCARD_OVERRUN(OVERRUN)
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA)
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST)
#define | IS_SMARTCARD_REQUEST_PARAMETER(PARAM)

Define Documentation

#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000

Definition at line 107 of file stm32f7xx_hal_smartcard.c.

Referenced by SMARTCARD_DMATransmitCplt().

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( DATAINV )
Value:
(((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                             ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Definition at line 788 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( DMA )
Value:
(((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Definition at line 794 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( INIT )
Value:
((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
                                                            SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
                                                            SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
                                                            SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
                                                            SMARTCARD_ADVFEATURE_SWAP_INIT | \
                                                            SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
                                                            SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT   | \
                                                            SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Definition at line 776 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( MSBFIRST )
Value:
(((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                               ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Definition at line 800 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( RXINV )
Value:
(((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                         ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Definition at line 786 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( SWAP )
Value:
(((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                       ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Definition at line 790 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( TXINV )
Value:
(((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                         ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Definition at line 784 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7)

Definition at line 799 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 4500001)

Definition at line 796 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFF)

Definition at line 797 of file stm32f7xx_hal_smartcard.h.

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Definition at line 768 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))

Definition at line 765 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Definition at line 772 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Definition at line 770 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( OVERRUN )
Value:
(((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Definition at line 792 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Definition at line 763 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Definition at line 767 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ ) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Definition at line 766 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( PARAM )
Value:
(((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                               ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Definition at line 802 of file stm32f7xx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ ) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)

Definition at line 762 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Definition at line 774 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFF)

Definition at line 798 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Definition at line 761 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define TEACK_REACK_TIMEOUT 1000

Definition at line 106 of file stm32f7xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))

Definition at line 108 of file stm32f7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))

Definition at line 110 of file stm32f7xx_hal_smartcard.c.

#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))

Definition at line 111 of file stm32f7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

Definition at line 112 of file stm32f7xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SmartCard Initialization and de-initialization functions

Functions
SmartCard Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SMARTCARD mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USART
  associated to the SmartCard.
      (+) These parameters can be configured:
        (++) Baud Rate
        (++) Parity: parity should be enabled,
             Frame Length is fixed to 8 bits plus parity:
             the USART frame format is given in the following table:

        (+++) +---------------------------------------------------------------+
        (+++) | M1M0 bits |  PCE bit  |            USART frame                |
        (+++) |-----------------------|---------------------------------------|
        (+++) |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
        (+++) +---------------------------------------------------------------+

        (++) Receiver/transmitter modes
        (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
        (++) Prescaler value
        (++) Guard bit time
        (++) NACK enabling or disabling on transmission error

      (+) The following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) Time out enabling (and if activated, timeout value)
        (++) Block length
        (++) Auto-retry counter

    [..]
    The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures
    (details for the procedures are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsc )

DeInitializes the SMARTCARD peripheral.

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 245 of file stm32f7xx_hal_smartcard.c.

References assert_param, SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsc )

Initializes the SMARTCARD mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 192 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE, __HAL_SMARTCARD_ENABLE, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::Lock, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_SetConfig(), and SMARTCARD_HandleTypeDef::State.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD MSP DeInit.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 290 of file stm32f7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD MSP Init.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 275 of file stm32f7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD interrupt requests handling.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

    (#) There are two modes of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (+) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
           will be executed respectively at the end of the Transmit or Receive process
           The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_SMARTCARD_Transmit()
        (+) HAL_SMARTCARD_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_SMARTCARD_Transmit_IT()
        (+) HAL_SMARTCARD_Receive_IT()
        (+) HAL_SMARTCARD_IRQHandler()
        (+) SMARTCARD_Transmit_IT()
        (+) SMARTCARD_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (+) HAL_SMARTCARD_Transmit_DMA()
        (+) HAL_SMARTCARD_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (+) HAL_SMARTCARD_TxCpltCallback()
        (+) HAL_SMARTCARD_RxCpltCallback()
        (+) HAL_SMARTCARD_ErrorCallback()

Function Documentation

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD error callbacks.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 829 of file stm32f7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAError(), and SMARTCARD_DMATransmitCplt().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD interrupt requests handling.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 716 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, __HAL_SMARTCARD_SEND_REQ, SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_IT_EOB, SMARTCARD_IT_ERR, SMARTCARD_IT_FE, SMARTCARD_IT_NE, SMARTCARD_IT_ORE, SMARTCARD_IT_PE, SMARTCARD_IT_RTO, SMARTCARD_IT_RXNE, SMARTCARD_IT_TC, SMARTCARD_Receive_IT(), SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_Transmit_IT(), and SMARTCARD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsc,: SMARTCARD handle
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 423 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, SMARTCARD_WaitOnFlagUntilTimeout(), and SMARTCARD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsc,: SMARTCARD handle
pData,: pointer to data buffer
Size,: amount of data to be received
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position)
Return values:
HAL status

Definition at line 658 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hsc,: SMARTCARD handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 538 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, SMARTCARD_IT_RXNE, and SMARTCARD_HandleTypeDef::State.

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

Rx Transfer completed callbacks.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 814 of file stm32f7xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hsc,: SMARTCARD handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 358 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FLAG_TC, SMARTCARD_FLAG_TXE, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::State, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsc,: SMARTCARD handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 592 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_FLAG_TC, SMARTCARD_HandleTypeDef::State, SMARTCARD_HandleTypeDef::TxXferCount, SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hsc,: SMARTCARD handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 487 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_ERR, SMARTCARD_IT_TC, SMARTCARD_HandleTypeDef::State, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

Tx Transfer completed callbacks.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 799 of file stm32f7xx_hal_smartcard.c.

Referenced by SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SMARTCARD Exported Functions

SMARTCARD State functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

SMARTCARD State functions.

 ===============================================================================
                ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral
     (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral
     (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsc )

Return the SMARTCARD error code.

Parameters:
hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD.
Return values:
SMARTCARD Error Code

Definition at line 877 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsc )

return the SMARTCARD state

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL state

Definition at line 866 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Exported Functions

Modules | Functions
SMARTCARD Exported Functions
SMARTCARD

Modules

SmartCard Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State functions

SMARTCARD State functions.

Functions

static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc)
Receive an amount of data in non blocking mode.
static void | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD associated USART peripheral.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsc)
Check the SMARTCARD Idle State.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles SMARTCARD Communication Timeout.
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsc ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 1124 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsc ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 1085 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::State, and TEACK_REACK_TIMEOUT.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1317 of file stm32f7xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::State, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1290 of file stm32f7xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::State.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1253 of file stm32f7xx_hal_smartcard.c.

References HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_TIMEOUT, HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_TXDMA_TIMEOUTVALUE, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FLAG_TC, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::State, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static HAL_StatusTypeDef SMARTCARD_Receive_IT ( SMARTCARD_HandleTypeDef * hsc ) [static]

Receive an amount of data in non blocking mode.

Parameters:
hsc,: SMARTCARD handle. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
Return values:
HAL status

Definition at line 940 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_FLAG_RXNE, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, SMARTCARD_IT_RXNE, and SMARTCARD_HandleTypeDef::State.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsc ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsc,: SMARTCARD handle
Return values:
None

Definition at line 986 of file stm32f7xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKState, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, SMARTCARD_InitTypeDef::Prescaler, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PCLK1, SMARTCARD_CLOCKSOURCE_PCLK2, SMARTCARD_CLOCKSOURCE_SYSCLK, SMARTCARD_CR3_SCARCNT_LSB_POS, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_GTPR_GT_LSB_POS, SMARTCARD_MODE_TX, SMARTCARD_NACK_ENABLE, SMARTCARD_RTOR_BLEN_LSB_POS, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_Transmit_IT ( SMARTCARD_HandleTypeDef * hsc ) [static]

Send an amount of data in non blocking mode.

Parameters:
hsc,: SMARTCARD handle. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
Return values:
HAL status

Definition at line 893 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_BUSY_TX_RX, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_ERR, SMARTCARD_IT_TC, SMARTCARD_HandleTypeDef::State, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles SMARTCARD Communication Timeout.

Parameters:
hsc,: SMARTCARD handle
Flag,: specifies the SMARTCARD flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1187 of file stm32f7xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_GET_FLAG, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, SMARTCARD_IT_RXNE, SMARTCARD_IT_TXE, and SMARTCARD_HandleTypeDef::State.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), SMARTCARD_CheckIdleState(), and SMARTCARD_DMATransmitCplt().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Exported Types

Data Structures | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00, HAL_SMARTCARD_STATE_READY = 0x01, HAL_SMARTCARD_STATE_BUSY = 0x02, HAL_SMARTCARD_STATE_BUSY_TX = 0x12,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, HAL_SMARTCARD_STATE_TIMEOUT = 0x03, HAL_SMARTCARD_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_HSI = 0x02, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04,
SMARTCARD_CLOCKSOURCE_LSE = 0x08
}
SMARTCARD clock sources definition. More...

Enumeration Type Documentation

enum HAL_SMARTCARD_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SMARTCARD_STATE_RESET

Peripheral is not yet Initialized

HAL_SMARTCARD_STATE_READY

Peripheral Initialized and ready for use

HAL_SMARTCARD_STATE_BUSY

an internal process is ongoing

HAL_SMARTCARD_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SMARTCARD_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SMARTCARD_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SMARTCARD_STATE_TIMEOUT

Timeout state

HAL_SMARTCARD_STATE_ERROR

Error

Definition at line 160 of file stm32f7xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources definition.

Enumerator:
SMARTCARD_CLOCKSOURCE_PCLK1

PCLK1 clock source

SMARTCARD_CLOCKSOURCE_PCLK2

PCLK2 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_SYSCLK

SYSCLK clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

Definition at line 176 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32f7xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | OneBitSampling
uint32_t | Prescaler
uint32_t | GuardTime
uint32_t | NACKState
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint32_t | BlockLength
uint32_t | AutoRetryCount

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 65 of file stm32f7xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 118 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hsc->Init.BaudRate)))

Definition at line 67 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 115 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 92 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 89 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 86 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time

Definition at line 102 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Mode

Definition at line 83 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::NACKState

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK State

Definition at line 104 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD OneBit Sampling

Definition at line 96 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 77 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler

Definition at line 100 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits SMARTCARD Number of Stop Bits. Only 1.5 stop bits are authorized in SmartCard mode.

Definition at line 74 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 108 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 111 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 71 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_smartcard.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initalization structure definition. More...

#include <stm32f7xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst

Detailed Description

SMARTCARD advanced features initalization structure definition.

Definition at line 128 of file stm32f7xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD Advanced Features Initialization Type

Definition at line 130 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD Data Inv

Definition at line 140 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD DMA Disable on Rx Error

Definition at line 150 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD MSB First

Definition at line 153 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD Overrun Disable

Definition at line 147 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD Rx Inv

Definition at line 137 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD Rx Tx Swap

Definition at line 144 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD Tx Inv

Definition at line 134 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_smartcard.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32f7xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 188 of file stm32f7xx_hal_smartcard.h.

Field Documentation

SMARTCARD_AdvFeatureInitTypeDef SMARTCARD_HandleTypeDef::AdvancedInit

Definition at line 194 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

__IO uint32_t SMARTCARD_HandleTypeDef::ErrorCode

Definition at line 216 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), and SMARTCARD_DMAError().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmarx

Definition at line 210 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmatx

Definition at line 208 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

SMARTCARD_InitTypeDef SMARTCARD_HandleTypeDef::Init

Definition at line 192 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

USART_TypeDef* SMARTCARD_HandleTypeDef::Instance

Definition at line 190 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_Receive_IT(), SMARTCARD_SetConfig(), and SMARTCARD_Transmit_IT().

HAL_LockTypeDef SMARTCARD_HandleTypeDef::Lock

Definition at line 212 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint8_t* SMARTCARD_HandleTypeDef::pRxBuffPtr

Definition at line 202 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

uint8_t* SMARTCARD_HandleTypeDef::pTxBuffPtr

Definition at line 196 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferCount

Definition at line 206 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferSize

Definition at line 204 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::State

Definition at line 214 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

uint16_t SMARTCARD_HandleTypeDef::TxXferCount

Definition at line 200 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferSize

Definition at line 198 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_smartcard.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Error Code

Defines
SMARTCARD Error Code
SMARTCARD Exported constants

SMARTCARD Error Code. More...

Defines

#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10)
#define | HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20)

Detailed Description

SMARTCARD Error Code.

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10)

DMA transfer error

Definition at line 236 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04)

frame error

Definition at line 234 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02)

Noise error

Definition at line 233 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00)

No error

Definition at line 231 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_CheckIdleState().

#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08)

Overrun error

Definition at line 235 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01)

Parity error

Definition at line 232 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20)

Receiver TimeOut error

Definition at line 237 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported constants

Defines

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Define Documentation

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Definition at line 245 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported constants

Defines

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))

Define Documentation

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))

Definition at line 253 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 261 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 262 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Mode

Defines
SMARTCARD Mode
SMARTCARD Exported constants

Defines

#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 270 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 271 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 272 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported constants

Defines

#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x0000)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Definition at line 281 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000)

Definition at line 280 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000)

Definition at line 289 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Definition at line 290 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000)

Definition at line 298 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Definition at line 299 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD OneBit Sampling

Defines
SMARTCARD OneBit Sampling
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000)

Definition at line 307 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Definition at line 308 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD NACK State

Defines
SMARTCARD NACK State
SMARTCARD Exported constants

Defines

#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x0000)

Define Documentation

#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000)

Definition at line 318 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

Definition at line 317 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

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STM32F745xx HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)

Definition at line 326 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Definition at line 327 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

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STM32F745xx HAL User Manual: SMARTCARD DMA requests

Defines
SMARTCARD DMA requests
SMARTCARD Exported constants

Defines

#define | SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define | SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)

Definition at line 337 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)

Definition at line 336 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD Advanced Features Initialization Type

Defines
SMARTCARD Advanced Features Initialization Type
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)

Definition at line 349 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)

Definition at line 352 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Definition at line 353 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)

Definition at line 346 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)

Definition at line 348 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)

Definition at line 351 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)

Definition at line 350 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)

Definition at line 347 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

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STM32F745xx HAL User Manual: SMARTCARD Tx Inv

Defines
SMARTCARD Tx Inv
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)

Definition at line 361 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Definition at line 362 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD Rx Inv

Defines
SMARTCARD Rx Inv
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)

Definition at line 370 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Definition at line 371 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD Data Inv

Defines
SMARTCARD Data Inv
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)

Definition at line 379 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Definition at line 380 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Rx Tx Swap

Defines
SMARTCARD Rx Tx Swap
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)

Definition at line 388 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Definition at line 389 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD Overrun Disable

Defines
SMARTCARD Overrun Disable
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Definition at line 398 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)

Definition at line 397 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD DMA Disable on Rx Error

Defines
SMARTCARD DMA Disable on Rx Error
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Definition at line 407 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)

Definition at line 406 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD MSB First

Defines
SMARTCARD MSB First
SMARTCARD Exported constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)

Definition at line 415 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Definition at line 416 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
#define | SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
#define | SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
#define | SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
#define | SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
#define | SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
#define | SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
#define | SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
#define | SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
#define | SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
#define | SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
#define | SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
#define | SMARTCARD_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)

Definition at line 428 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)

Definition at line 429 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)

Definition at line 437 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)

Definition at line 434 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)

Definition at line 436 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)

Definition at line 435 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)

Definition at line 438 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)

Definition at line 426 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)

Definition at line 430 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)

Definition at line 433 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), and SMARTCARD_Receive_IT().

#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)

Definition at line 432 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and SMARTCARD_DMATransmitCplt().

#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)

Definition at line 427 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)

Definition at line 431 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit().

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STM32F745xx HAL User Manual: SMARTCARD Interrupt definition

Defines
SMARTCARD Interrupt definition
SMARTCARD Exported constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE ((uint16_t)0x0028)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3A)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)

Definition at line 464 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_ERR ((uint16_t)0x0060)

Definition at line 459 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define SMARTCARD_IT_FE ((uint16_t)0x0100)

Definition at line 462 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_IDLE ((uint16_t)0x0424)

Definition at line 458 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_IT_NE ((uint16_t)0x0200)

Definition at line 461 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_ORE ((uint16_t)0x0300)

Definition at line 460 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_PE ((uint16_t)0x0028)

Definition at line 454 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)

Definition at line 465 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)

Definition at line 457 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define SMARTCARD_IT_TC ((uint16_t)0x0626)

Definition at line 456 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

#define SMARTCARD_IT_TXE ((uint16_t)0x0727)

Definition at line 455 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

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STM32F745xx HAL User Manual: SMARTCARD IT CLEAR Flags

Defines
SMARTCARD IT CLEAR Flags
SMARTCARD Exported constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

End Of Block Clear Flag

Definition at line 481 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 475 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

Idle line detected clear Flag

Definition at line 478 of file stm32f7xx_hal_smartcard.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 476 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 477 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 474 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

Receiver Time Out Clear Flag

Definition at line 480 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 479 of file stm32f7xx_hal_smartcard.h.

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STM32F745xx HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 489 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 490 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD CR3 SCAR CNT LSB POS

Defines
SMARTCARD CR3 SCAR CNT LSB POS
SMARTCARD Exported constants

Defines

#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)

Define Documentation

#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)

Definition at line 499 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD GTPR GT LSBPOS

Defines
SMARTCARD GTPR GT LSBPOS
SMARTCARD Exported constants

Defines

#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)

Define Documentation

#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)

Definition at line 507 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD RTOR BLEN LSBPOS

Defines
SMARTCARD RTOR BLEN LSBPOS
SMARTCARD Exported constants

Defines

#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)

Define Documentation

#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)

Definition at line 515 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_BlockLength_Config(), and SMARTCARD_SetConfig().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Interruption Mask

Defines
SMARTCARD Interruption Mask
SMARTCARD Exported constants

Defines

#define SMARTCARD_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define SMARTCARD_IT_MASK ((uint16_t)0x001F)

Definition at line 523 of file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
Reset SMARTCARD handle state.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))
Flush the Smartcard DR register.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Checks whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Checks whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified SmartCard interrupt interrupt source is enabled.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
Macros to enable or disable the SmartCard DMA request.
#define | __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))

Define Documentation

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • USART_CLEAR_PEF: Parity Error Clear Flag
  • USART_CLEAR_FEF: Framing Error Clear Flag
  • USART_CLEAR_NEF: Noise detected Clear Flag
  • USART_CLEAR_OREF: OverRun Error Clear Flag
  • USART_CLEAR_TCF: Transmission Complete Clear Flag
  • USART_CLEAR_RTOF: Receiver Time Out Clear Flag
  • USART_CLEAR_EOBF: End Of Block Clear Flag
Return values:
None

Definition at line 661 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), and HAL_SMARTCARD_Transmit_DMA().

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
Return values:
None

Definition at line 687 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                        ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disables the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__INTERRUPT__,: specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOBF: End Of Block interrupt
  • SMARTCARD_IT_RTOF: Receive TimeOut interrupt
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
  • SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 603 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE | ( | __HANDLE__,
 |  | __REQUEST__
 | ) | ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))

Definition at line 698 of file stm32f7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE | ( | __HANDLE__,
 |  | __REQUEST__
 | ) | ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))

Macros to enable or disable the SmartCard DMA request.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__REQUEST__,: specifies the SmartCard DMA request. This parameter can be one of the following values:
  • SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
  • SMARTCARD_DMAREQ_RX: SmartCard DMA receive request

Definition at line 697 of file stm32f7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
Return values:
None

Definition at line 680 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                        ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                        ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enables the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__INTERRUPT__,: specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOBF: End Of Block interrupt
  • SMARTCARD_IT_RTOF: Receive TimeOut interrupt
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
  • SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 586 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), and HAL_SMARTCARD_Transmit_IT().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ ) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))

Flush the Smartcard DR register.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
Return values:
None

Definition at line 549 of file stm32f7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Checks whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY: Busy flag
  • SMARTCARD_FLAG_EOBF: End of block flag
  • SMARTCARD_FLAG_RTOF: Receiver timeout flag
  • SMARTCARD_FLAG_TXE: Transmit data register empty flag
  • SMARTCARD_FLAG_TC: Transmission Complete flag
  • SMARTCARD_FLAG_RXNE: Receive data register not empty flag
  • SMARTCARD_FLAG_ORE: OverRun Error flag
  • SMARTCARD_FLAG_NE: Noise Error flag
  • SMARTCARD_FLAG_FE: Framing Error flag
  • SMARTCARD_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 570 of file stm32f7xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Checks whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__IT__,: specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOBF: End Of Block interrupt
  • SMARTCARD_IT_RTOF: Receive TimeOut interrupt
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_ORE: OverRun Error interrupt
  • SMARTCARD_IT_NE: Noise Error interrupt
  • SMARTCARD_IT_FE: Framing Error interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 623 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
                                                               (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
                                                               (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))

Checks whether the specified SmartCard interrupt interrupt source is enabled.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__IT__,: specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOBF: End Of Block interrupt
  • SMARTCARD_IT_RTOF: Receive TimeOut interrupt
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_ORE: OverRun Error interrupt
  • SMARTCARD_IT_NE: Noise Error interrupt
  • SMARTCARD_IT_FE: Framing Error interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 641 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)

Reset SMARTCARD handle state.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2
Return values:
None

Definition at line 542 of file stm32f7xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. The Handle Instance which can be USART1 or USART2.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
Return values:
None

Definition at line 673 of file stm32f7xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Private Functions

SMARTCARD Private Functions
SMARTCARD
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARDEx Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsc,: SMARTCARD handle
BlockLength,: SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 103 of file stm32f7xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_RTOR_BLEN_LSB_POS.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsc )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 149 of file stm32f7xx_hal_smartcard_ex.c.

References HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsc )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 126 of file stm32f7xx_hal_smartcard_ex.c.

References HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::State.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsc,: SMARTCARD handle
TimeOutValue,: receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 115 of file stm32f7xx_hal_smartcard_ex.c.

References assert_param, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARDEx

Modules | Defines | Functions
SMARTCARDEx
STM32F7xx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARDEx Exported Functions

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the SMARTCARD clock source.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

SMARTCARD Extended HAL module driver.

Define Documentation

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Reports the SMARTCARD clock source.

Parameters:
__HANDLE__,: specifies the USART Handle
__CLOCKSOURCE__ : output variable
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 66 of file stm32f7xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_SetConfig().

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsc,: SMARTCARD handle
BlockLength,: SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 103 of file stm32f7xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_RTOR_BLEN_LSB_POS.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsc )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 149 of file stm32f7xx_hal_smartcard_ex.c.

References HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsc )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsc,: SMARTCARD handle
Return values:
HAL status

Definition at line 126 of file stm32f7xx_hal_smartcard_ex.c.

References HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::State.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsc,: SMARTCARD handle
TimeOutValue,: receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 115 of file stm32f7xx_hal_smartcard_ex.c.

References assert_param, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPDIFRX Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
  ##### Initialization and de-initialization functions #####
  ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
  de-initialize the SPDIFRX peripheral:

  (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
  all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

  (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
  the selected configuration:
  (++) Input Selection (IN0, IN1,...)
  (++) Maximum allowed re-tries during synchronization phase
  (++) Wait for activity on SPDIF selected input
  (++) Channel status selection (from channel A or B)
  (++) Data format (LSB, MSB, ...)
  (++) Stereo mode
  (++) User bits masking (PT,C,U,V,...)

  (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
  of the selected SPDIFRXx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPDIFRX_DeInit ( SPDIFRX_HandleTypeDef * hspdif )

DeInitializes the SPDIFRX peripheral.

Parameters:
hspdif,: SPDIFRX handle
Return values:
HAL status

Definition at line 270 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_IDLE, assert_param, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_MspDeInit(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_RESET, SPDIFRX_HandleTypeDef::Instance, and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_Init ( SPDIFRX_HandleTypeDef * hspdif )

Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.

Parameters:
hspdif,: SPDIFRX handle
Return values:
HAL status

Definition at line 199 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_IDLE, assert_param, SPDIFRX_InitTypeDef::ChannelSelection, SPDIFRX_InitTypeDef::ChannelStatusMask, SPDIFRX_InitTypeDef::DataFormat, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_MspInit(), HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, HAL_SPDIFRX_STATE_RESET, SPDIFRX_HandleTypeDef::Init, SPDIFRX_InitTypeDef::InputSelection, SPDIFRX_HandleTypeDef::Instance, IS_CHANNEL_STATUS_MASK, IS_PARITY_ERROR_MASK, IS_PREAMBLE_TYPE_MASK, IS_SPDIFRX_CHANNEL, IS_SPDIFRX_DATA_FORMAT, IS_SPDIFRX_INPUT_SELECT, IS_SPDIFRX_MAX_RETRIES, IS_SPDIFRX_WAIT_FOR_ACTIVITY, IS_STEREO_MODE, IS_VALIDITY_MASK, SPDIFRX_HandleTypeDef::Lock, SPDIFRX_InitTypeDef::ParityErrorMask, SPDIFRX_InitTypeDef::PreambleTypeMask, SPDIFRX_InitTypeDef::Retries, SPDIFRX_HandleTypeDef::State, SPDIFRX_InitTypeDef::StereoMode, SPDIFRX_InitTypeDef::ValidityBitMask, and SPDIFRX_InitTypeDef::WaitForActivity.

void HAL_SPDIFRX_MspDeInit ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX MSP DeInit.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 320 of file stm32f7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_DeInit().

void HAL_SPDIFRX_MspInit ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX MSP Init.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 305 of file stm32f7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_Init().

HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | SPDIFRX_SetDataFormatTypeDef | sDataFormat
 | ) |  |

Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.

Parameters:
hspdif,: SPDIFRX handle
sDataFormat,: SPDIFRX data format
Return values:
HAL status

Definition at line 337 of file stm32f7xx_hal_spdifrx.c.

References assert_param, SPDIFRX_SetDataFormatTypeDef::ChannelStatusMask, SPDIFRX_SetDataFormatTypeDef::DataFormat, SPDIFRX_HandleTypeDef::Instance, IS_CHANNEL_STATUS_MASK, IS_PARITY_ERROR_MASK, IS_PREAMBLE_TYPE_MASK, IS_SPDIFRX_DATA_FORMAT, IS_STEREO_MODE, IS_VALIDITY_MASK, SPDIFRX_SetDataFormatTypeDef::ParityErrorMask, SPDIFRX_SetDataFormatTypeDef::PreambleTypeMask, SPDIFRX_STATE_RCV, SPDIFRX_SetDataFormatTypeDef::StereoMode, and SPDIFRX_SetDataFormatTypeDef::ValidityBitMask.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPDIFRX Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.

Detailed Description

Data transfers functions.

===============================================================================
                     ##### IO operation functions #####
===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SPDIFRX data
    transfers.

    (#) There is two mode of transfer:
        (++) Blocking mode : The communication is performed in the polling mode.
             The status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode : The communication is performed using Interrupts
             or DMA. These functions return the status of the transfer start-up.
             The end of the data processing will be indicated through the
             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_SPDIFRX_ReceiveDataFlow()
        (++) HAL_SPDIFRX_ReceiveControlFlow()
                (+@) Do not use blocking mode to receive both control and data flow at the same time.

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
        (++) HAL_SPDIFRX_ReceiveDataFlow_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
        (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (++) HAL_SPDIFRX_RxCpltCallback()
        (++) HAL_SPDIFRX_ErrorCallback()

Function Documentation

void HAL_SPDIFRX_CxCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Control flow) completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 943 of file stm32f7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

void HAL_SPDIFRX_CxHalfCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx (Control flow) Transfer half completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 928 of file stm32f7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMACxHalfCplt().

HAL_StatusTypeDef HAL_SPDIFRX_DMAStop ( SPDIFRX_HandleTypeDef * hspdif )

stop the audio stream receive from the Media.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 822 of file stm32f7xx_hal_spdifrx.c.

References __HAL_DMA_DISABLE, __HAL_SPDIFRX_IDLE, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::hdmaCsRx, SPDIFRX_HandleTypeDef::hdmaDrRx, SPDIFRX_HandleTypeDef::Instance, and SPDIFRX_HandleTypeDef::State.

void HAL_SPDIFRX_ErrorCallback ( SPDIFRX_HandleTypeDef * hspdif )

SPDIFRX error callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 958 of file stm32f7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_IRQHandler(), and SPDIFRX_DMAError().

void HAL_SPDIFRX_IRQHandler ( SPDIFRX_HandleTypeDef * hspdif )

This function handles SPDIFRX interrupt request.

Parameters:
hspdif,: SPDIFRX handle
Return values:
HAL status

Definition at line 851 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_CLEAR_IT, __HAL_SPDIFRX_GET_FLAG, __HAL_SPDIFRX_GET_IT_SOURCE, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_OVR, HAL_SPDIFRX_ERROR_PE, HAL_SPDIFRX_ErrorCallback(), SPDIFRX_FLAG_CSRNE, SPDIFRX_FLAG_OVR, SPDIFRX_FLAG_PERR, SPDIFRX_FLAG_RXNE, SPDIFRX_IT_CSRNE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data (Control Flow) in blocking mode.

Parameters:
hspdif,: pointer to a SPDIFRX_HandleTypeDef structure that contains the configuration information for SPDIFRX module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 500 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_CSRNE, SPDIFRX_FLAG_SYNCD, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Control Flow) with DMA.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data (Control Flow) sample to be received :
Return values:
HAL status

Definition at line 756 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::CsXferCount, SPDIFRX_HandleTypeDef::CsXferSize, SPDIFRX_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::hdmaCsRx, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_DMACxCplt(), SPDIFRX_DMACxHalfCplt(), SPDIFRX_DMAError(), SPDIFRX_FLAG_SYNCD, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), SPDIFRX_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Control Flow) with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data sample (Control Flow) to be received :
Return values:
HAL status

Definition at line 624 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_ENABLE_IT, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::CsXferCount, SPDIFRX_HandleTypeDef::CsXferSize, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_CSRNE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data (Data Flow) in blocking mode.

Parameters:
hspdif,: pointer to SPDIFRX_HandleTypeDef structure that contains the configuration information for SPDIFRX module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 437 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, HAL_SPDIFRX_STATE_BUSY, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_FLAG_RXNE, SPDIFRX_FLAG_SYNCD, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Data Flow) mode with DMA.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data sample to be received :
Return values:
HAL status

Definition at line 688 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::hdmaDrRx, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pRxBuffPtr, SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_HandleTypeDef::RxXferSize, SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_DMARxHalfCplt(), SPDIFRX_FLAG_SYNCD, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), SPDIFRX_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
pData,: a 32-bit pointer to the Receive data buffer.
Size,: number of data sample to be received .
Return values:
HAL status

Definition at line 560 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_ENABLE_IT, __HAL_SPDIFRX_RCV, __HAL_SPDIFRX_SYNC, SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_NONE, HAL_SPDIFRX_STATE_BUSY_CX, HAL_SPDIFRX_STATE_BUSY_RX, HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::pRxBuffPtr, SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_HandleTypeDef::RxXferSize, SPDIFRX_FLAG_SYNCD, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_STATE_SYNC, SPDIFRX_TIMEOUT_VALUE, SPDIFRX_WaitOnFlagUntilTimeout(), and SPDIFRX_HandleTypeDef::State.

void HAL_SPDIFRX_RxCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Data flow) completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 913 of file stm32f7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

void HAL_SPDIFRX_RxHalfCpltCallback ( SPDIFRX_HandleTypeDef * hspdif )

Rx Transfer (Data flow) half completed callbacks.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 898 of file stm32f7xx_hal_spdifrx.c.

Referenced by SPDIFRX_DMARxHalfCplt().

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STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPDIFRX Exported Functions

Peripheral State functions. More...

Functions

HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX error code.

Detailed Description

Peripheral State functions.

===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.

Function Documentation

uint32_t HAL_SPDIFRX_GetError ( SPDIFRX_HandleTypeDef * hspdif )

Return the SPDIFRX error code.

Parameters:
hspdif : SPDIFRX handle
Return values:
SPDIFRX Error Code

Definition at line 1002 of file stm32f7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::ErrorCode.

HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState ( SPDIFRX_HandleTypeDef * hspdif )

Return the SPDIFRX state.

Parameters:
hspdif : SPDIFRX handle
Return values:
HAL state

Definition at line 992 of file stm32f7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX Exported Functions

Modules | Functions
SPDIFRX Exported Functions
SPDIFRX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Functions

static void | SPDIFRX_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) complete callback.
static void | SPDIFRX_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) half complete callback.
static void | SPDIFRX_DMACxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) complete callback.
static void | SPDIFRX_DMACxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) half complete callback.
static void | SPDIFRX_DMAError (DMA_HandleTypeDef *hdma)
DMA SPDIFRX communication error callback.
static void | SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Data Flow) with Interrupt.
static void | SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Control Flow) with Interrupt.
static HAL_StatusTypeDef | SPDIFRX_WaitOnFlagUntilTimeout (SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles SPDIFRX Communication Timeout.

Function Documentation

static void SPDIFRX_DMACxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Control flow) complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1048 of file stm32f7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::CsXferCount, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA().

static void SPDIFRX_DMACxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Control flow) half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1065 of file stm32f7xx_hal_spdifrx.c.

References HAL_SPDIFRX_CxHalfCpltCallback().

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA().

static void SPDIFRX_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX communication error callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1077 of file stm32f7xx_hal_spdifrx.c.

References SPDIFRX_HandleTypeDef::ErrorCode, HAL_SPDIFRX_ERROR_DMA, HAL_SPDIFRX_ErrorCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::RxXferCount, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Data flow) complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1016 of file stm32f7xx_hal_spdifrx.c.

References HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::RxXferCount, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPDIFRX receive process (Data flow) half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1035 of file stm32f7xx_hal_spdifrx.c.

References HAL_SPDIFRX_RxHalfCpltCallback().

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA().

static void SPDIFRX_ReceiveControlFlow_IT ( SPDIFRX_HandleTypeDef * hspdif ) [static]

Receive an amount of data (Control Flow) with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 1123 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, SPDIFRX_HandleTypeDef::CsXferCount, HAL_SPDIFRX_CxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pCsBuffPtr, SPDIFRX_IT_CSRNE, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_IRQHandler().

static void SPDIFRX_ReceiveDataFlow_IT ( SPDIFRX_HandleTypeDef * hspdif ) [static]

Receive an amount of data (Data Flow) with Interrupt.

Parameters:
hspdif,: SPDIFRX handle
Return values:
None

Definition at line 1098 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_STATE_READY, SPDIFRX_HandleTypeDef::Instance, SPDIFRX_HandleTypeDef::pRxBuffPtr, SPDIFRX_HandleTypeDef::RxXferCount, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_IRQHandler().

static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout | ( | SPDIFRX_HandleTypeDef * | hspdif,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles SPDIFRX Communication Timeout.

Parameters:
hspdif,: SPDIFRX handle
Flag,: Flag checked
Status,: Value of the flag expected
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 1151 of file stm32f7xx_hal_spdifrx.c.

References __HAL_SPDIFRX_DISABLE_IT, __HAL_SPDIFRX_GET_FLAG, HAL_GetTick(), HAL_SPDIFRX_STATE_READY, SPDIFRX_IT_CSRNE, SPDIFRX_IT_IFEIE, SPDIFRX_IT_OVRIE, SPDIFRX_IT_PERRIE, SPDIFRX_IT_RXNE, SPDIFRX_IT_SBLKIE, SPDIFRX_IT_SYNCDIE, and SPDIFRX_HandleTypeDef::State.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX Exported Types

Data Structures | Enumerations
SPDIFRX Exported Types
SPDIFRX

Data Structures

struct | SPDIFRX_InitTypeDef
SPDIFRX Init structure definition. More...
struct | SPDIFRX_SetDataFormatTypeDef
SPDIFRX SetDataFormat structure definition. More...
struct | SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition. More...

Enumerations

enum HAL_SPDIFRX_StateTypeDef {
HAL_SPDIFRX_STATE_RESET = 0x00, HAL_SPDIFRX_STATE_READY = 0x01, HAL_SPDIFRX_STATE_BUSY = 0x02, HAL_SPDIFRX_STATE_BUSY_RX = 0x03,
HAL_SPDIFRX_STATE_BUSY_CX = 0x04, HAL_SPDIFRX_STATE_ERROR = 0x07
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_SPDIFRX_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SPDIFRX_STATE_RESET

SPDIFRX not yet initialized or disabled

HAL_SPDIFRX_STATE_READY

SPDIFRX initialized and ready for use

HAL_SPDIFRX_STATE_BUSY

SPDIFRX internal process is ongoing

HAL_SPDIFRX_STATE_BUSY_RX

SPDIFRX internal Data Flow RX process is ongoing

HAL_SPDIFRX_STATE_BUSY_CX

SPDIFRX internal Control Flow RX process is ongoing

HAL_SPDIFRX_STATE_ERROR

SPDIFRX error state

Definition at line 127 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_InitTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX Init structure definition. More...

#include <stm32f7xx_hal_spdifrx.h>

Data Fields

uint32_t | InputSelection
uint32_t | Retries
uint32_t | WaitForActivity
uint32_t | ChannelSelection
uint32_t | DataFormat
uint32_t | StereoMode
uint32_t | PreambleTypeMask
uint32_t | ChannelStatusMask
uint32_t | ValidityBitMask
uint32_t | ParityErrorMask

Detailed Description

SPDIFRX Init structure definition.

Definition at line 65 of file stm32f7xx_hal_spdifrx.h.

Field Documentation

uint32_t SPDIFRX_InitTypeDef::ChannelSelection

Specifies whether the control flow will take the channel status from channel A or B. This parameter can be a value of SPDIFRX Channel Selection

Definition at line 76 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ChannelStatusMask

Specifies whether the channel status and user bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Channel Status Mask

Definition at line 88 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::DataFormat

Specifies the Data samples format (LSB, MSB, ...). This parameter can be a value of SPDIFRX Data Format

Definition at line 79 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::InputSelection

Specifies the SPDIF input selection. This parameter can be a value of SPDIFRX Input Selection

Definition at line 67 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ParityErrorMask

Specifies whether the parity error bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Parity Error Mask

Definition at line 94 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::PreambleTypeMask

Specifies whether The preamble type bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Preamble Type Mask

Definition at line 85 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::Retries

Specifies the Maximum allowed re-tries during synchronization phase. This parameter can be a value of SPDIFRX Maximum Retries

Definition at line 70 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::StereoMode

Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of SPDIFRX Stereo Mode

Definition at line 82 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::ValidityBitMask

Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Validity Mask

Definition at line 91 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t SPDIFRX_InitTypeDef::WaitForActivity

Specifies the wait for activity on SPDIF selected input. This parameter can be a value of SPDIFRX Wait For Activity.

Definition at line 73 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_spdifrx.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX_SetDataFormatTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_SetDataFormatTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX SetDataFormat structure definition. More...

#include <stm32f7xx_hal_spdifrx.h>

Data Fields

uint32_t | DataFormat
uint32_t | StereoMode
uint32_t | PreambleTypeMask
uint32_t | ChannelStatusMask
uint32_t | ValidityBitMask
uint32_t | ParityErrorMask

Detailed Description

SPDIFRX SetDataFormat structure definition.

Definition at line 102 of file stm32f7xx_hal_spdifrx.h.

Field Documentation

uint32_t SPDIFRX_SetDataFormatTypeDef::ChannelStatusMask

Specifies whether the channel status and user bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Channel Status Mask

Definition at line 113 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::DataFormat

Specifies the Data samples format (LSB, MSB, ...). This parameter can be a value of SPDIFRX Data Format

Definition at line 104 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::ParityErrorMask

Specifies whether the parity error bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Parity Error Mask

Definition at line 119 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::PreambleTypeMask

Specifies whether The preamble type bits are copied or not into the received frame. This parameter can be a value of SPDIFRX Preamble Type Mask

Definition at line 110 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::StereoMode

Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of SPDIFRX Stereo Mode

Definition at line 107 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

uint32_t SPDIFRX_SetDataFormatTypeDef::ValidityBitMask

Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of SPDIFRX Validity Mask

Definition at line 116 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_spdifrx.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPDIFRX_HandleTypeDef Struct Reference
SPDIFRX Exported Types

SPDIFRX handle Structure definition. More...

#include <stm32f7xx_hal_spdifrx.h>

Data Fields

SPDIFRX_TypeDef * | Instance
SPDIFRX_InitTypeDef Init
uint32_t * | pRxBuffPtr
uint32_t * | pCsBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
__IO uint16_t | CsXferSize
__IO uint16_t | CsXferCount
DMA_HandleTypeDef * hdmaCsRx
DMA_HandleTypeDef * hdmaDrRx
__IO HAL_LockTypeDef | Lock
__IO HAL_SPDIFRX_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPDIFRX handle Structure definition.

Definition at line 140 of file stm32f7xx_hal_spdifrx.h.

Field Documentation

__IO uint16_t SPDIFRX_HandleTypeDef::CsXferCount

Definition at line 161 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_DMACxCplt(), and SPDIFRX_ReceiveControlFlow_IT().

__IO uint16_t SPDIFRX_HandleTypeDef::CsXferSize

Definition at line 159 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), and HAL_SPDIFRX_ReceiveControlFlow_IT().

__IO uint32_t SPDIFRX_HandleTypeDef::ErrorCode

Definition at line 176 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_GetError(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_DMAError().

DMA_HandleTypeDef* SPDIFRX_HandleTypeDef::hdmaCsRx

Definition at line 168 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_ReceiveControlFlow_DMA().

DMA_HandleTypeDef* SPDIFRX_HandleTypeDef::hdmaDrRx

Definition at line 170 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_ReceiveDataFlow_DMA().

SPDIFRX_InitTypeDef SPDIFRX_HandleTypeDef::Init

Definition at line 144 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

SPDIFRX_TypeDef* SPDIFRX_HandleTypeDef::Instance

Definition at line 142 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_SetDataFormat(), SPDIFRX_DMACxCplt(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

__IO HAL_LockTypeDef SPDIFRX_HandleTypeDef::Lock

Definition at line 172 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

uint32_t* SPDIFRX_HandleTypeDef::pCsBuffPtr

Definition at line 148 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_ReceiveControlFlow_IT().

uint32_t* SPDIFRX_HandleTypeDef::pRxBuffPtr

Definition at line 146 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_ReceiveDataFlow_IT().

__IO uint16_t SPDIFRX_HandleTypeDef::RxXferCount

Definition at line 152 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), and SPDIFRX_ReceiveDataFlow_IT().

__IO uint16_t SPDIFRX_HandleTypeDef::RxXferSize

Definition at line 150 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

__IO HAL_SPDIFRX_StateTypeDef SPDIFRX_HandleTypeDef::State

Definition at line 174 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), HAL_SPDIFRX_GetState(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_DMACxCplt(), SPDIFRX_DMAError(), SPDIFRX_DMARxCplt(), SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_spdifrx.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX Error Code

Defines
SPDIFRX Error Code
SPDIFRX Exported Constants

Defines

#define | HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002)
#define | HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004)
#define | HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008)
#define | HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010)

Define Documentation

#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008)

DMA transfer error

Definition at line 194 of file stm32f7xx_hal_spdifrx.h.

Referenced by SPDIFRX_DMAError().

#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 190 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002)

OVR error

Definition at line 192 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004)

Parity error

Definition at line 193 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001)

Timeout error

Definition at line 191 of file stm32f7xx_hal_spdifrx.h.

#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010)

Unknown Error error

Definition at line 195 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Input Selection

Defines
SPDIFRX Input Selection
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)
#define | SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000)
#define | SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)
#define | SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)

Define Documentation

#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)

Definition at line 203 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000)

Definition at line 204 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)

Definition at line 205 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)

Definition at line 206 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Maximum Retries

Defines
SPDIFRX Maximum Retries
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)
#define | SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000)
#define | SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)
#define | SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)

Define Documentation

#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)

Definition at line 216 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000)

Definition at line 215 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)

Definition at line 217 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)

Definition at line 214 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Wait For Activity

Defines
SPDIFRX Wait For Activity
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)

Define Documentation

#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)

Definition at line 225 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)

Definition at line 226 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Preamble Type Mask

Defines
SPDIFRX Preamble Type Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)

Define Documentation

#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)

Definition at line 234 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)

Definition at line 235 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Channel Status Mask

Defines
SPDIFRX Channel Status Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */
#define | SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

Define Documentation

#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */

Definition at line 243 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

Definition at line 244 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Validity Mask

Defines
SPDIFRX Validity Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)

Define Documentation

#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)

Definition at line 252 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)

Definition at line 253 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Parity Error Mask

Defines
SPDIFRX Parity Error Mask
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)

Define Documentation

#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)

Definition at line 261 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)

Definition at line 262 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Channel Selection

Defines
SPDIFRX Channel Selection
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)
#define | SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)

Define Documentation

#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)

Definition at line 270 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)

Definition at line 271 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Data Format

Defines
SPDIFRX Data Format
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)
#define | SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)
#define | SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)

Define Documentation

#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)

Definition at line 281 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)

Definition at line 279 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)

Definition at line 280 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Stereo Mode

Defines
SPDIFRX Stereo Mode
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)
#define | SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)

Define Documentation

#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)

Definition at line 289 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)

Definition at line 290 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX State

Defines
SPDIFRX State
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)
#define | SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
#define | SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)

Define Documentation

#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)

Definition at line 299 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)

Definition at line 301 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_SetDataFormat().

#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)

Definition at line 300 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

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STM32F745xx HAL User Manual: SPDIFRX Interrupts Definition

Defines
SPDIFRX Interrupts Definition
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define | SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define | SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define | SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define | SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define | SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define | SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )

Define Documentation

#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)

Definition at line 310 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveControlFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )

Definition at line 315 of file stm32f7xx_hal_spdifrx.h.

Referenced by SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)

Definition at line 312 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)

Definition at line 311 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)

Definition at line 309 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), HAL_SPDIFRX_ReceiveDataFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)

Definition at line 313 of file stm32f7xx_hal_spdifrx.h.

Referenced by SPDIFRX_WaitOnFlagUntilTimeout().

#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)

Definition at line 314 of file stm32f7xx_hal_spdifrx.h.

Referenced by SPDIFRX_WaitOnFlagUntilTimeout().

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STM32F745xx HAL User Manual: SPDIFRX Flags Definition

Defines
SPDIFRX Flags Definition
SPDIFRX Exported Constants

Defines

#define | SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define | SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define | SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define | SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define | SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define | SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define | SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define | SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define | SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)

Define Documentation

#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)

Definition at line 324 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and HAL_SPDIFRX_ReceiveControlFlow().

#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)

Definition at line 329 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)

Definition at line 326 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)

Definition at line 325 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)

Definition at line 323 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and HAL_SPDIFRX_ReceiveDataFlow().

#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)

Definition at line 327 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)

Definition at line 330 of file stm32f7xx_hal_spdifrx.h.

#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)

Definition at line 328 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)

Definition at line 331 of file stm32f7xx_hal_spdifrx.h.

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STM32F745xx HAL User Manual: SPDIFRX Exported Macros

Defines
SPDIFRX Exported Macros
SPDIFRX

Defines

#define | __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
Reset SPDIFRX handle state.
#define | __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
Disable the specified SPDIFRX peripheral (IDLE State).
#define | __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
Enable the specified SPDIFRX peripheral (SYNC State).
#define | __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
Enable the specified SPDIFRX peripheral (RCV State).
#define | __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SPDIFRX interrupts.
#define | __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPDIFRX interrupt source is enabled or disabled.
#define | __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified SPDIFRX flag is set or not.
#define | __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

Define Documentation

#define __HAL_SPDIFRX_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))

Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • SPDIFRX_FLAG_PERR
  • SPDIFRX_FLAG_OVR
  • SPDIFRX_SR_SBD
  • SPDIFRX_SR_SYNCD
Return values:
None

Definition at line 430 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define __HAL_SPDIFRX_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))

Definition at line 385 of file stm32f7xx_hal_spdifrx.h.

Referenced by SPDIFRX_ReceiveControlFlow_IT(), SPDIFRX_ReceiveDataFlow_IT(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define __HAL_SPDIFRX_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable or disable the specified SPDIFRX interrupts.

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPDIFRX_IT_RXNE
  • SPDIFRX_IT_CSRNE
  • SPDIFRX_IT_PERRIE
  • SPDIFRX_IT_OVRIE
  • SPDIFRX_IT_SBLKIE
  • SPDIFRX_IT_SYNCDIE
  • SPDIFRX_IT_IFEIE
Return values:
None

Definition at line 384 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_IT(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define __HAL_SPDIFRX_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified SPDIFRX flag is set or not.

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPDIFRX_FLAG_RXNE
  • SPDIFRX_FLAG_CSRNE
  • SPDIFRX_FLAG_PERR
  • SPDIFRX_FLAG_OVR
  • SPDIFRX_FLAG_SBD
  • SPDIFRX_FLAG_SYNCD
  • SPDIFRX_FLAG_FERR
  • SPDIFRX_FLAG_SERR
  • SPDIFRX_FLAG_TERR
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 417 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler(), and SPDIFRX_WaitOnFlagUntilTimeout().

#define __HAL_SPDIFRX_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified SPDIFRX interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
__INTERRUPT__,: specifies the SPDIFRX interrupt source to check. This parameter can be one of the following values:
  • SPDIFRX_IT_RXNE
  • SPDIFRX_IT_CSRNE
  • SPDIFRX_IT_PERRIE
  • SPDIFRX_IT_OVRIE
  • SPDIFRX_IT_SBLKIE
  • SPDIFRX_IT_SYNCDIE
  • SPDIFRX_IT_IFEIE
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 400 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_IRQHandler().

#define __HAL_SPDIFRX_IDLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)

Disable the specified SPDIFRX peripheral (IDLE State).

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
Return values:
None

Definition at line 355 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_DMAStop(), and HAL_SPDIFRX_Init().

#define __HAL_SPDIFRX_RCV ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)

Enable the specified SPDIFRX peripheral (RCV State).

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
Return values:
None

Definition at line 368 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

#define __HAL_SPDIFRX_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)

Reset SPDIFRX handle state.

Parameters:
__HANDLE__,: SPDIFRX handle.
Return values:
None

Definition at line 349 of file stm32f7xx_hal_spdifrx.h.

#define __HAL_SPDIFRX_SYNC ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)

Enable the specified SPDIFRX peripheral (SYNC State).

Parameters:
__HANDLE__,: specifies the SPDIFRX Handle.
Return values:
None

Definition at line 361 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_ReceiveControlFlow(), HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

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STM32F745xx HAL User Manual: SPDIFRX Private Macros

Defines
SPDIFRX Private Macros
SPDIFRX

Defines

#define | IS_SPDIFRX_INPUT_SELECT(INPUT)
#define | IS_SPDIFRX_MAX_RETRIES(RET)
#define | IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)
#define | IS_PREAMBLE_TYPE_MASK(VAL)
#define | IS_VALIDITY_MASK(VAL)
#define | IS_PARITY_ERROR_MASK(VAL)
#define | IS_SPDIFRX_CHANNEL(CHANNEL)
#define | IS_SPDIFRX_DATA_FORMAT(FORMAT)
#define | IS_STEREO_MODE(MODE)
#define | IS_CHANNEL_STATUS_MASK(VAL)

Define Documentation

#define IS_CHANNEL_STATUS_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
                                              ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))

Definition at line 527 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_PARITY_ERROR_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))

Definition at line 517 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_PREAMBLE_TYPE_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))

Definition at line 513 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SPDIFRX_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == SPDIFRX_CHANNEL_A) || \
                                       ((CHANNEL) == SPDIFRX_CHANNEL_B))

Definition at line 519 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))

Definition at line 521 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_SPDIFRX_INPUT_SELECT ( INPUT )
Value:
(((INPUT) == SPDIFRX_INPUT_IN1) || \
                                         ((INPUT) == SPDIFRX_INPUT_IN2) || \
                                         ((INPUT) == SPDIFRX_INPUT_IN3)  || \
                                         ((INPUT) == SPDIFRX_INPUT_IN0))

Definition at line 503 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_MAX_RETRIES ( RET )
Value:
(((RET) == SPDIFRX_MAXRETRIES_NONE) || \
                                      ((RET) == SPDIFRX_MAXRETRIES_3)  || \
                                      ((RET) == SPDIFRX_MAXRETRIES_15) || \
                                      ((RET) == SPDIFRX_MAXRETRIES_63))

Definition at line 507 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_SPDIFRX_WAIT_FOR_ACTIVITY ( VAL )
Value:
(((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
                                               ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))

Definition at line 511 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init().

#define IS_STEREO_MODE ( MODE )
Value:
(((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))

Definition at line 524 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

#define IS_VALIDITY_MASK ( VAL )
Value:
(((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))

Definition at line 515 of file stm32f7xx_hal_spdifrx.h.

Referenced by HAL_SPDIFRX_Init(), and HAL_SPDIFRX_SetDataFormat().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX Private Functions

SPDIFRX Private Functions
SPDIFRX
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX

Modules | Defines
SPDIFRX
STM32F7xx_HAL_Driver

SPDIFRX HAL module driver. More...

Modules

SPDIFRX Exported Functions
SPDIFRX Exported Types
SPDIFRX Exported Constants
SPDIFRX Exported Macros
SPDIFRX Private Macros
SPDIFRX Private Functions

Defines

#define SPDIFRX_TIMEOUT_VALUE 0xFFFF

Detailed Description

SPDIFRX HAL module driver.

Define Documentation

#define SPDIFRX_TIMEOUT_VALUE 0xFFFF

Definition at line 139 of file stm32f7xx_hal_spdifrx.c.

Referenced by HAL_SPDIFRX_ReceiveControlFlow_DMA(), HAL_SPDIFRX_ReceiveControlFlow_IT(), HAL_SPDIFRX_ReceiveDataFlow_DMA(), and HAL_SPDIFRX_ReceiveDataFlow_IT().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 50

Define Documentation

#define SPI_DEFAULT_TIMEOUT 50

Definition at line 104 of file stm32f7xx_hal_spi.c.

Referenced by HAL_SPI_DeInit(), SPI_CloseRx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initializes the SPI according to the specified parameters in the SPI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
DeInitializes the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
SPI MSP Init.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
SPI MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

DeInitializes the SPI peripheral.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 297 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FLAG_FTLVL, SPI_FRLVL_EMPTY, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initializes the SPI according to the specified parameters in the SPI_InitTypeDef and create the associated handle.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 193 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_ERROR_NONE, HAL_SPI_MspInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_8BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_RXFIFO_THRESHOLD_HF, SPI_RXFIFO_THRESHOLD_QF, __SPI_HandleTypeDef::State, and SPI_InitTypeDef::TIMode.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

SPI MSP DeInit.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 351 of file stm32f7xx_hal_spi.c.

Referenced by HAL_SPI_DeInit().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

SPI MSP Init.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 335 of file stm32f7xx_hal_spi.c.

Referenced by HAL_SPI_Init().

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STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stops the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
This function handles SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callbacks.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the HAL status.
           The end of the data processing will be indicated through the
           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pauses the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1597 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resumes the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1617 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stops the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1637 of file stm32f7xx_hal_spi.c.

References HAL_DMA_Abort(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1826 of file stm32f7xx_hal_spi.c.

Referenced by HAL_SPI_IRQHandler(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

This function handles SPI interrupt request.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 1668 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __HAL_SPI_GET_IT_SOURCE, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxISR.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 551 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in no-blocking mode with DMA.

Parameters:
hspi,: SPI handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1344 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_ENABLE, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in no-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1051 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callbacks.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1746 of file stm32f7xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1794 of file stm32f7xx_hal_spi.c.

Referenced by SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 406 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_TXE, SPI_RESET_CRC, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in no-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1254 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, DMA_InitTypeDef::MemDataAlignment, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in no-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 971 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 745 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in no-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1448 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in no-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Return values:
HAL status

Definition at line 1157 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1730 of file stm32f7xx_hal_spi.c.

Referenced by SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1778 of file stm32f7xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1762 of file stm32f7xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1810 of file stm32f7xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitReceiveCplt().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI | SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 1879 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI state.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 1868 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00, HAL_SPI_STATE_READY = 0x01, HAL_SPI_STATE_BUSY = 0x02, HAL_SPI_STATE_BUSY_TX = 0x03,
HAL_SPI_STATE_BUSY_RX = 0x04, HAL_SPI_STATE_BUSY_TX_RX = 0x05, HAL_SPI_STATE_ERROR = 0x06
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

Definition at line 119 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32f7xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode

Detailed Description

SPI Configuration Structure definition.

Definition at line 65 of file stm32f7xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 86 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 79 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 76 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 98 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 104 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535

Definition at line 101 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 73 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 70 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB transmission

Definition at line 92 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 67 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select management

Definition at line 82 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Definition at line 108 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not . This parameter can be a value of SPI TI mode

Definition at line 95 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_spi.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32f7xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
HAL_SPI_StateTypeDef State
uint32_t | ErrorCode

Detailed Description

SPI handle Structure definition.

Definition at line 133 of file stm32f7xx_hal_spi.h.

Field Documentation

uint32_t __SPI_HandleTypeDef::CRCSize

Definition at line 151 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BITCRC(), and SPI_RxISR_8BITCRC().

uint32_t __SPI_HandleTypeDef::ErrorCode

Definition at line 165 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

Definition at line 159 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

Definition at line 157 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

Definition at line 137 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

Definition at line 135 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Definition at line 161 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Definition at line 145 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Definition at line 139 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

Definition at line 153 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferCount

Definition at line 149 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

Definition at line 147 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

Definition at line 163 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

Definition at line 155 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

uint16_t __SPI_HandleTypeDef::TxXferCount

Definition at line 143 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

Definition at line 141 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_spi.h
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (uint32_t)0x00000000
#define | HAL_SPI_ERROR_MODF (uint32_t)0x00000001
#define | HAL_SPI_ERROR_CRC (uint32_t)0x00000002
#define | HAL_SPI_ERROR_OVR (uint32_t)0x00000004
#define | HAL_SPI_ERROR_FRE (uint32_t)0x00000008
#define | HAL_SPI_ERROR_DMA (uint32_t)0x00000010
#define | HAL_SPI_ERROR_FLAG (uint32_t)0x00000020
#define | HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040

Define Documentation

#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002

CRC error

Definition at line 184 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010

DMA transfer error

Definition at line 187 of file stm32f7xx_hal_spi.h.

Referenced by SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020

Error on BSY/TXE/FTLVL/FRLVL Flag

Definition at line 188 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008

FRE error

Definition at line 186 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001

MODF error

Definition at line 183 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000

No error

Definition at line 182 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004

OVR error

Definition at line 185 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040

Unknow Error error

Definition at line 189 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 199 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE ((uint32_t)0x00000000)

Definition at line 198 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 209 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)

Definition at line 207 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 208 of file stm32f7xx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT ((uint32_t)0x0300)
#define | SPI_DATASIZE_5BIT ((uint32_t)0x0400)
#define | SPI_DATASIZE_6BIT ((uint32_t)0x0500)
#define | SPI_DATASIZE_7BIT ((uint32_t)0x0600)
#define | SPI_DATASIZE_8BIT ((uint32_t)0x0700)
#define | SPI_DATASIZE_9BIT ((uint32_t)0x0800)
#define | SPI_DATASIZE_10BIT ((uint32_t)0x0900)
#define | SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
#define | SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
#define | SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
#define | SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
#define | SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
#define | SPI_DATASIZE_16BIT ((uint32_t)0x0F00)

Define Documentation

#define SPI_DATASIZE_10BIT ((uint32_t)0x0900)

Definition at line 223 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)

Definition at line 224 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)

Definition at line 225 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)

Definition at line 226 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)

Definition at line 227 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)

Definition at line 228 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)

Definition at line 229 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_4BIT ((uint32_t)0x0300)

Definition at line 217 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_5BIT ((uint32_t)0x0400)

Definition at line 218 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_6BIT ((uint32_t)0x0500)

Definition at line 219 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_7BIT ((uint32_t)0x0600)

Definition at line 220 of file stm32f7xx_hal_spi.h.

#define SPI_DATASIZE_8BIT ((uint32_t)0x0700)

Definition at line 221 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_DATASIZE_9BIT ((uint32_t)0x0800)

Definition at line 222 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 238 of file stm32f7xx_hal_spi.h.

#define SPI_POLARITY_LOW ((uint32_t)0x00000000)

Definition at line 237 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)

Definition at line 246 of file stm32f7xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 247 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Slave Select management

Defines
SPI Slave Select management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)

Define Documentation

#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)

Definition at line 256 of file stm32f7xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)

Definition at line 257 of file stm32f7xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 255 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)

Definition at line 266 of file stm32f7xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP

Definition at line 265 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)

Definition at line 280 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)

Definition at line 277 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)

Definition at line 274 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)

Definition at line 281 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)

Definition at line 278 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)

Definition at line 275 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)

Definition at line 279 of file stm32f7xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)

Definition at line 276 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI MSB LSB transmission

Defines
SPI MSB LSB transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 290 of file stm32f7xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)

Definition at line 289 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI TI mode

Defines
SPI TI mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)

Definition at line 298 of file stm32f7xx_hal_spi.h.

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 299 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)

Definition at line 307 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 308 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit. More...

Defines

#define | SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
#define | SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
#define | SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)

Detailed Description

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

Define Documentation

#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)

Definition at line 322 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), and SPI_DMAReceiveCplt().

#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)

Definition at line 321 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and SPI_DMATransmitReceiveCplt().

#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)

Definition at line 320 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI FIFO Reception Threshold

Defines
SPI FIFO Reception Threshold
SPI Exported Constants

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits). More...

Defines

#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)

Detailed Description

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits).

SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO level is greater or equal to 1/4(8 bits).

Define Documentation

#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH

Definition at line 335 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_2linesRxISR_8BIT().

#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)

Definition at line 337 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH

Definition at line 336 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Interrupt configuration definition

Defines
SPI Interrupt configuration definition
SPI Exported Constants

SPI Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Detailed Description

SPI Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 351 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 350 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 349 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Flag definition

Defines
SPI Flag definition
SPI Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXX : Flag register Index
  • YYYY : Flag mask

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 366 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 367 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 370 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Definition at line 372 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */

Definition at line 371 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 368 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 369 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 364 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and SPI_DMAReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 365 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Transmission FIFO Status Level

Defines
SPI Transmission FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FTLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
#define | SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
#define | SPI_FTLVL_FULL ((uint32_t)0x1800)

Define Documentation

#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)

Definition at line 380 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), and SPI_EndRxTxTransaction().

#define SPI_FTLVL_FULL ((uint32_t)0x1800)

Definition at line 383 of file stm32f7xx_hal_spi.h.

#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)

Definition at line 382 of file stm32f7xx_hal_spi.h.

#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)

Definition at line 381 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
#define | SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
#define | SPI_FRLVL_FULL ((uint32_t)0x0600)

Define Documentation

#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)

Definition at line 392 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), and SPI_WaitFifoStateUntilTimeout().

#define SPI_FRLVL_FULL ((uint32_t)0x0600)

Definition at line 395 of file stm32f7xx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)

Definition at line 394 of file stm32f7xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)

Definition at line 393 of file stm32f7xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enables or disables the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPI interrupt source is enabled or disabled.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clears the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clears the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clears the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clears the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enables the SPI.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disables the SPI.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clears the SPI CRCERR pending flag.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 463 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
   __IO uint32_t tmpreg = 0x00;                          \
     tmpreg = (__HANDLE__)->Instance->SR;           \
     UNUSED(tmpreg);                                \
   } while(0)

Clears the SPI FRE pending flag.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 499 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                              \
   __IO uint32_t tmpreg = 0x00;                          \
     tmpreg = (__HANDLE__)->Instance->SR;           \
     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
     UNUSED(tmpreg);                                \
   } while(0)

Clears the SPI MODF pending flag.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 471 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
   __IO uint32_t tmpreg = 0x00;                          \
     tmpreg = (__HANDLE__)->Instance->DR;           \
     tmpreg = (__HANDLE__)->Instance->SR;           \
     UNUSED(tmpreg);                                \
   } while(0)

Clears the SPI OVR pending flag.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 485 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))

Disables the SPI.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 518 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

Definition at line 426 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)

Enables the SPI.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 511 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enables or disables the specified SPI interrupts.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ : specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 425 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified SPI flag is set or not.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__ : specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 456 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified SPI interrupt source is enabled or disabled.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ : specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 438 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

Reset SPI handle state.

Parameters:
__HANDLE__,: SPI handle.
Return values:
None

Definition at line 413 of file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Sets the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Sets the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Resets the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 590 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                           ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 580 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                           ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 577 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 605 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( LENGTH )
Value:
(((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))

Definition at line 608 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))

Definition at line 612 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_4BIT))

Definition at line 563 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES) || \
                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
                                  ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 554 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 558 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)|| \
                                                 ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 560 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                               ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 599 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                           ((MODE) == SPI_MODE_MASTER))

Definition at line 551 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT) || \
                         ((NSS) == SPI_NSS_HARD_INPUT) || \
                         ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 583 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( NSSP )
Value:
(((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                           ((NSSP) == SPI_NSS_PULSE_DISABLE))

Definition at line 587 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( MODE )
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
                             ((MODE) == SPI_TIMODE_ENABLE))

Definition at line 602 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))

Sets the SPI receive-only mode.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 541 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)

Sets the SPI transmit-only mode.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 534 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)

Resets the CRC calculation of the SPI.

Parameters:
__HANDLE__ : specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 548 of file stm32f7xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
STM32F7xx_HAL_Driver | SPI

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI Half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
This function handles SPI Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8Bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16Bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive in Interrupt context.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC receive in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16Bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16Bit Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
This function handles the close of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
This function handles the close of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
This function handles the close of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
This function handles the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
This function handles the check of the RXTX or TX transaction complete.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16Bit Handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2258 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2289 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), and SPI_IT_RXNE.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx Handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2144 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, SPI_RXFIFO_THRESHOLD, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx Handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2191 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx Handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2307 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx Handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2219 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

This function handles the close of the RX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2684 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

This function handles the close of the RXTX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2642 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), SPI_FLAG_CRCERR, SPI_IT_ERR, and __SPI_HandleTypeDef::State.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

This function handles the close of the TX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2720 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2126 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2100 of file stm32f7xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback().

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2087 of file stm32f7xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback().

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Half transmit receive process complete callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2113 of file stm32f7xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback().

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1936 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1902 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SPI_DIRECTION_2LINES, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2018 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_8BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_FRLVL_QUARTER_FULL, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles the check of the RX transaction complete.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout : Timeout duration
Return values:
None

Definition at line 2589 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_MODE_MASTER, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles the check of the RXTX or TX transaction complete.

Parameters:
hspi,: SPI handle
Timeout : Timeout duration

Definition at line 2615 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FLAG_FTLVL, SPI_FRLVL_EMPTY, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), and SPI_DMATransmitReceiveCplt().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16Bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2404 of file stm32f7xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2385 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, and SPI_IT_RXNE.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2357 of file stm32f7xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2337 of file stm32f7xx_hal_spi.c.

References __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, and SPI_CloseRx_ISR().

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16Bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2455 of file stm32f7xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8Bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2433 of file stm32f7xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo | : Fifo to check
State | : Fifo state to check
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 2533 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_DeInit(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag | : SPI flag to check
State | : flag state to check
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 2482 of file stm32f7xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_DMAReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
__weak void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SRAM Initialization and de_initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to initialize/de-initialize
          the SRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SRAM_DeInit ( SRAM_HandleTypeDef * hsram )

Performs the SRAM device De-initialization sequence.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 176 of file stm32f7xx_hal_sram.c.

References SRAM_HandleTypeDef::Extended, HAL_SRAM_MspDeInit(), HAL_SRAM_STATE_RESET, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

__weak void HAL_SRAM_DMA_XferCpltCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 230 of file stm32f7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

__weak void HAL_SRAM_DMA_XferErrorCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete error callback.

Parameters:
hdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 246 of file stm32f7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

HAL_StatusTypeDef HAL_SRAM_Init | ( | SRAM_HandleTypeDef * | hsram,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Performs the SRAM device initialization sequence.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Timing,: Pointer to SRAM control timing structure
ExtTiming,: Pointer to SRAM extended mode timing structure
Return values:
HAL status

Definition at line 139 of file stm32f7xx_hal_sram.c.

References SRAM_HandleTypeDef::Extended, HAL_SRAM_MspInit(), HAL_SRAM_STATE_RESET, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, SRAM_HandleTypeDef::Lock, and SRAM_HandleTypeDef::State.

void HAL_SRAM_MspDeInit ( SRAM_HandleTypeDef * hsram )

SRAM MSP DeInit.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 214 of file stm32f7xx_hal_sram.c.

Referenced by HAL_SRAM_DeInit().

void HAL_SRAM_MspInit ( SRAM_HandleTypeDef * hsram )

SRAM MSP Init.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 198 of file stm32f7xx_hal_sram.c.

Referenced by HAL_SRAM_Init().

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Input Output and memory control functions

Functions
Input Output and memory control functions
SRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                  ##### SRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SRAM memory

Function Documentation

void HAL_SRAM_DMA_XferCpltCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 230 of file stm32f7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

void HAL_SRAM_DMA_XferErrorCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete error callback.

Parameters:
hdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 246 of file stm32f7xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

HAL_StatusTypeDef HAL_SRAM_Read_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 16-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 361 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 32-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 439 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads 8-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 283 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Reads a Words data from the SRAM memory using DMA transfer.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 513 of file stm32f7xx_hal_sram.c.

References HAL_DMA_Start_IT(), HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::hdma, SRAM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SRAM_Write_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 16-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 397 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 32-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 473 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes 8-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 319 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Writes a Words data buffer to SRAM memory using DMA transfer.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 546 of file stm32f7xx_hal_sram.c.

References HAL_DMA_Start_IT(), HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::hdma, SRAM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Control functions

Functions
Control functions
SRAM Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.

Detailed Description

Control functions.

  ==============================================================================
                        ##### SRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SRAM interface.

Function Documentation

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable ( SRAM_HandleTypeDef * hsram )

Disables dynamically SRAM write operation.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 624 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable ( SRAM_HandleTypeDef * hsram )

Enables dynamically SRAM write operation.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 601 of file stm32f7xx_hal_sram.c.

References HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SRAM_StateTypeDef HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SRAM controller
    and the data flow.

Function Documentation

HAL_SRAM_StateTypeDef HAL_SRAM_GetState ( SRAM_HandleTypeDef * hsram )

Returns the SRAM controller state.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL state

Definition at line 669 of file stm32f7xx_hal_sram.c.

References SRAM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SRAM Exported Types

Data Structures | Enumerations
SRAM Exported Types
SRAM

Data Structures

struct SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00, HAL_SRAM_STATE_READY = 0x01, HAL_SRAM_STATE_BUSY = 0x02, HAL_SRAM_STATE_ERROR = 0x03,
HAL_SRAM_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...

Enumeration Type Documentation

enum HAL_SRAM_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_SRAM_STATE_RESET

SRAM not yet initialized or disabled

HAL_SRAM_STATE_READY

SRAM initialized and ready for use

HAL_SRAM_STATE_BUSY

SRAM internal process is ongoing

HAL_SRAM_STATE_ERROR

SRAM error state

HAL_SRAM_STATE_PROTECTED

SRAM peripheral NORSRAM device write protected

Definition at line 64 of file stm32f7xx_hal_sram.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SRAM_HandleTypeDef Struct Reference
SRAM Exported Types

SRAM handle Structure definition. More...

#include <stm32f7xx_hal_sram.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_SRAM_StateTypeDef | State
DMA_HandleTypeDef * hdma

Detailed Description

SRAM handle Structure definition.

Definition at line 77 of file stm32f7xx_hal_sram.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* SRAM_HandleTypeDef::Extended

Extended mode register base address

Definition at line 81 of file stm32f7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), and HAL_SRAM_Init().

DMA_HandleTypeDef* SRAM_HandleTypeDef::hdma

Pointer DMA handler

Definition at line 89 of file stm32f7xx_hal_sram.h.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

FMC_NORSRAM_InitTypeDef SRAM_HandleTypeDef::Init

SRAM device control configuration parameters

Definition at line 83 of file stm32f7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* SRAM_HandleTypeDef::Instance

Register base address

Definition at line 79 of file stm32f7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

HAL_LockTypeDef SRAM_HandleTypeDef::Lock

SRAM locking object

Definition at line 85 of file stm32f7xx_hal_sram.h.

Referenced by HAL_SRAM_Init().

__IO HAL_SRAM_StateTypeDef SRAM_HandleTypeDef::State

SRAM device access state

Definition at line 87 of file stm32f7xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_GetState(), HAL_SRAM_Init(), HAL_SRAM_Read_16b(), HAL_SRAM_Read_32b(), HAL_SRAM_Read_8b(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_16b(), HAL_SRAM_Write_32b(), HAL_SRAM_Write_8b(), HAL_SRAM_Write_DMA(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_sram.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SRAM Exported Macros

Defines
SRAM Exported Macros
SRAM

Defines

#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
Reset SRAM handle state.

Define Documentation

#define __HAL_SRAM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)

Reset SRAM handle state.

Parameters:
__HANDLE__,: SRAM handle
Return values:
None

Definition at line 108 of file stm32f7xx_hal_sram.h.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Time Base functions

Functions
Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 238 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 201 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 282 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 266 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 298 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 389 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAPeriodElapsedCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 346 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 322 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 434 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 367 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Time Output Compare functions

Functions
Time Output Compare functions
TIM Exported Functions

Time Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

Time Output Compare functions.

  ==============================================================================
                  ##### Time Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the Time Output Compare.
    (+) Stop the Time Output Compare.
    (+) Start the Time Output Compare and enable interrupt.
    (+) Stop the Time Output Compare and disable interrupt.
    (+) Start the Time Output Compare and enable DMA transfer.
    (+) Stop the Time Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 523 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 484 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 567 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 551 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 589 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 791 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 655 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 622 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 909 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 722 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Time PWM functions

Functions
Time PWM functions
TIM Exported Functions

Time PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

Time PWM functions.

  ==============================================================================
                          ##### Time PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM OPWM.
    (+) De-initialize the TIM PWM.
    (+) Start the Time PWM.
    (+) Stop the Time PWM.
    (+) Start the Time PWM and enable interrupt.
    (+) Stop the Time PWM and disable interrupt.
    (+) Start the Time PWM and enable DMA transfer.
    (+) Stop the Time PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1038 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 999 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1082 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1066 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1104 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1309 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1173 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1137 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1427 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1240 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Time Input Capture functions

Functions
Time Input Capture functions
TIM Exported Functions

Time Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.

Detailed Description

Time Input Capture functions.

  ==============================================================================
              ##### Time Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the Time Input Capture.
   (+) Stop the Time Input Capture.
   (+) Start the Time Input Capture and enable interrupt.
   (+) Stop the Time Input Capture and disable interrupt.
   (+) Start the Time Input Capture and enable DMA transfer.
   (+) Stop the Time Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1556 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1517 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1600 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM INput Capture MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1584 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1622 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement on in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 1799 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1676 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1649 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement on in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1913 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1736 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Time One Pulse functions

Functions
Time One Pulse functions
TIM Exported Functions

Time One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

Time One Pulse functions.

  ==============================================================================
                        ##### Time One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the Time One Pulse.
    (+) Stop the Time One Pulse.
    (+) Start the Time One Pulse and enable interrupt.
    (+) Stop the Time One Pulse and disable interrupt.
    (+) Start the Time One Pulse and enable DMA transfer.
    (+) Stop the Time One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 2047 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OnePulseMode,: Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 2001 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2091 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2075 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2111 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2179 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be disable. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2145 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2219 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Time Encoder functions

Functions
Time Encoder functions
TIM Exported Functions

Time Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

Time Encoder functions.

  ==============================================================================
                          ##### Time Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the Time Encoder.
    (+) Stop the Time Encoder.
    (+) Start the Time Encoder and enable interrupt.
    (+) Stop the Time Encoder and disable interrupt.
    (+) Start the Time Encoder and enable DMA transfer.
    (+) Stop the Time Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 2369 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2280 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_ENCODER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2413 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2397 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2434 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1,: The destination Buffer address for IC1.
pData2,: The destination Buffer address for IC2.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2625 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2521 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2477 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2743 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, and TIM_DMA_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2570 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2806 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutationCallback(), TIM_HandleTypeDef::Instance, TIM_FLAG_BREAK, TIM_FLAG_BREAK2, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, and TIM_IT_UPDATE.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
__weak HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
   (+) Configure External Clock source.
   (+) Configure Complementary channels, break features and dead time.
   (+) Configure Master and the Slave synchronization.
   (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sClockSourceConfig,: pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 3960 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sClearInputConfig,: pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel,: specifies the TIM Channel. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3856 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CLEARINPUTSOURCE_ETR, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
TI1_Selection,: Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4116 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data read. This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources. This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3611 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIMEx_DMACommutationCplt(), TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstRequestSrc,: TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 3744 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data write. This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources. This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3386 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIMEx_DMACommutationCplt(), TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstRequestSrc,: TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 3518 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
EventSource,: specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Note:
TIM6 and TIM7 can only generate an update event.
TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
Return values:
HAL status

Definition at line 3818 of file stm32f7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Input Capture configuration structure
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3051 of file stm32f7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Output Compare configuration structure
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2981 of file stm32f7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM One Pulse configuration structure
OutputChannel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 3249 of file stm32f7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM PWM configuration structure
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3148 of file stm32f7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4335 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4149 of file stm32f7xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim,: TIM handle.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4296 of file stm32f7xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) Timer Period elapsed callback
   (+) Timer Output Compare callback
   (+) Timer Input capture callback
   (+) Timer Trigger callback
   (+) Timer Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4502 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_DMAError().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4454 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_DMACaptureCplt(), and HAL_TIM_IRQHandler().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4439 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4423 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMAPeriodElapsedCplt().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4470 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_DMADelayPulseCplt(), and HAL_TIM_IRQHandler().

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4486 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMATriggerCplt().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
TIM Exported Functions

Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4537 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4592 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4570 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4548 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4581 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4559 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Exported Functions

Modules | Functions
TIM Exported Functions
TIM

Modules

Time Base functions

Time Base functions.

Time Output Compare functions

Time Output Compare functions.

Time PWM functions

Time PWM functions.

Time Input Capture functions

Time Input Capture functions.

Time One Pulse functions

Time One Pulse functions.

Time Encoder functions

Time Encoder functions.

TIM IRQ handler management

IRQ handler management.

Peripheral Control functions

Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

Peripheral State functions

Peripheral State functions.

Functions

void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 4 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Time Output Compare 4 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
Selects the Input Trigger source.

Function Documentation

void HAL_TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4655 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void HAL_TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4622 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void HAL_TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4607 of file stm32f7xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM peripheral
Structure,: pointer on TIM Time Base required parameters
Return values:
None

Definition at line 4720 of file stm32f7xx_hal_tim.c.

References TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5491 of file stm32f7xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4690 of file stm32f7xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4705 of file stm32f7xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5461 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ITRx
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
TIM_ITRx,: The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 5430 of file stm32f7xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 1 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4765 of file stm32f7xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4830 of file stm32f7xx_hal_tim.c.

References assert_param, IS_TIM_OCN_POLARITY, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 3 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4897 of file stm32f7xx_hal_tim.c.

References assert_param, IS_TIM_OCN_POLARITY, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 4 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4963 of file stm32f7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Time Output Compare 4 configuration.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: The slave configuration structure
Return values:
None

Definition at line 5021 of file stm32f7xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchronization_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5213 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5166 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5296 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5256 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5339 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5387 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Exported Types

Data Structures | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00, HAL_TIM_STATE_READY = 0x01, HAL_TIM_STATE_BUSY = 0x02, HAL_TIM_STATE_TIMEOUT = 0x03,
HAL_TIM_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00
}
HAL Active channel structures definition. More...

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 277 of file stm32f7xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 265 of file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 65 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 77 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 70 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 73 of file stm32f7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 67 of file stm32f7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
    Note:
    This parameter is valid only for TIM1 and TIM8.

Definition at line 80 of file stm32f7xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 94 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 109 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 114 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIMEx Output Compare and PWM Modes

Definition at line 96 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare N Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 118 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 105 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 102 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 99 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 126 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 155 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 149 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 152 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 141 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIMEx Output Compare and PWM Modes

Definition at line 128 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare N Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 145 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 137 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 134 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 131 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 164 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 175 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 166 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 172 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 169 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 183 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 185 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 197 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 188 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 194 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 191 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 209 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 200 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 206 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 203 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 216 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 224 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity. This parameter can be a value of TIM Clock Polarity

Definition at line 220 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler. This parameter can be a value of TIM Clock Prescaler

Definition at line 222 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources. This parameter can be a value of TIM Clock Source

Definition at line 218 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

Clear Input Configuration Handle Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

Clear Input Configuration Handle Structure definition.

Definition at line 231 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 241 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity. This parameter can be a value of TIM Clear Input Polarity

Definition at line 237 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler. This parameter can be a value of TIM Clear Input Prescaler

Definition at line 239 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources. This parameter can be a value of TIMEx Clear Input Source

Definition at line 235 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state. This parameter can be ENABLE or DISABLE

Definition at line 233 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 248 of file stm32f7xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 251 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIMEx Slave mode

Definition at line 249 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 257 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 253 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 255 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32f7xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 289 of file stm32f7xx_hal_tim.h.

Field Documentation

HAL_TIM_ActiveChannel TIM_HandleTypeDef::Channel

Active channel

Definition at line 293 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), and HAL_TIM_IRQHandler().

DMA_HandleTypeDef* TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a DMA Handle index

Definition at line 294 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

TIM_Base_InitTypeDef TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 292 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* TIM_HandleTypeDef::Instance

Register base address

Definition at line 291 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef TIM_HandleTypeDef::Lock

Locking object

Definition at line 296 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), and HAL_TIM_PWM_Init().

__IO HAL_TIM_StateTypeDef TIM_HandleTypeDef::State

TIM operation state

Definition at line 297 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_DMACommutationCplt(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_RemapConfig(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Input Channel Polarity

Defines
TIM Input Channel Polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 313 of file stm32f7xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)

Polarity for TIx source

Definition at line 312 of file stm32f7xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000)

Polarity for TIx source

Definition at line 311 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000)

Define Documentation

#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)

Polarity for ETR source

Definition at line 321 of file stm32f7xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000)

Polarity for ETR source

Definition at line 322 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

Define Documentation

#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000)

No prescaler is used

Definition at line 330 of file stm32f7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)

ETR input source is divided by 2

Definition at line 331 of file stm32f7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)

ETR input source is divided by 4

Definition at line 332 of file stm32f7xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

ETR input source is divided by 8

Definition at line 333 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Definition at line 343 of file stm32f7xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Definition at line 344 of file stm32f7xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Definition at line 345 of file stm32f7xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Definition at line 342 of file stm32f7xx_hal_tim.h.

#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)

Definition at line 341 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)

Definition at line 353 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)

Definition at line 354 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Definition at line 355 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)

Definition at line 363 of file stm32f7xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Definition at line 364 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE ((uint32_t)0x0000)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Define Documentation

#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)

Definition at line 373 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Definition at line 374 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)

Definition at line 382 of file stm32f7xx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)

Definition at line 383 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Define Documentation

#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)

Definition at line 391 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Definition at line 392 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Define Documentation

#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)

Definition at line 400 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Definition at line 401 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)

Define Documentation

#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)

Definition at line 410 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)

Definition at line 409 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Output Compare N Idle State

Defines
TIM Output Compare N Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)

Define Documentation

#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)

Definition at line 419 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)

Definition at line 418 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Definition at line 429 of file stm32f7xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Definition at line 428 of file stm32f7xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Definition at line 427 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

Define Documentation

#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 437 of file stm32f7xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 439 of file stm32f7xx_hal_tim.h.

#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 441 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32F745xx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 ((uint32_t)0x0000)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Define Documentation

#define TIM_ICPSC_DIV1 ((uint32_t)0x0000)

Capture performed each time an edge is detected on the capture input

Definition at line 450 of file stm32f7xx_hal_tim.h.

#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)

Capture performed once every 2 events

Definition at line 451 of file stm32f7xx_hal_tim.h.

#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)

Capture performed once every 4 events

Definition at line 452 of file stm32f7xx_hal_tim.h.

#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Capture performed once every 8 events

Definition at line 453 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)

Define Documentation

#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)

Definition at line 462 of file stm32f7xx_hal_tim.h.

#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)

Definition at line 461 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)

Definition at line 470 of file stm32f7xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Definition at line 472 of file stm32f7xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)

Definition at line 471 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Interrupt definition

Defines
TIM Interrupt definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)

Define Documentation

#define TIM_IT_BREAK (TIM_DIER_BIE)

Definition at line 488 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 (TIM_DIER_CC1IE)

Definition at line 482 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 (TIM_DIER_CC2IE)

Definition at line 483 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 (TIM_DIER_CC3IE)

Definition at line 484 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 (TIM_DIER_CC4IE)

Definition at line 485 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_COM (TIM_DIER_COMIE)

Definition at line 486 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define TIM_IT_TRIGGER (TIM_DIER_TIE)

Definition at line 487 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_IT_UPDATE (TIM_DIER_UIE)

Definition at line 481 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

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STM32F745xx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)

Define Documentation

#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)

Definition at line 497 of file stm32f7xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)

Definition at line 496 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM DMA sources

Defines
TIM DMA sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)

Define Documentation

#define TIM_DMA_CC1 (TIM_DIER_CC1DE)

Definition at line 506 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 (TIM_DIER_CC2DE)

Definition at line 507 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 (TIM_DIER_CC3DE)

Definition at line 508 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 (TIM_DIER_CC4DE)

Definition at line 509 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_COM (TIM_DIER_COMDE)

Definition at line 510 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_TRIGGER (TIM_DIER_TDE)

Definition at line 511 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_DMA_UPDATE (TIM_DIER_UDE)

Definition at line 505 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

Definition at line 526 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Definition at line 527 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

Definition at line 520 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

Definition at line 521 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

Definition at line 522 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

Definition at line 523 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

Definition at line 524 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

Definition at line 525 of file stm32f7xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Definition at line 519 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Flag definition

Defines
TIM Flag definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_BREAK2 (TIM_SR_B2IF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Define Documentation

#define TIM_FLAG_BREAK (TIM_SR_BIF)

Definition at line 542 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)

Definition at line 543 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 (TIM_SR_CC1IF)

Definition at line 536 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)

Definition at line 544 of file stm32f7xx_hal_tim.h.

#define TIM_FLAG_CC2 (TIM_SR_CC2IF)

Definition at line 537 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)

Definition at line 545 of file stm32f7xx_hal_tim.h.

#define TIM_FLAG_CC3 (TIM_SR_CC3IF)

Definition at line 538 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)

Definition at line 546 of file stm32f7xx_hal_tim.h.

#define TIM_FLAG_CC4 (TIM_SR_CC4IF)

Definition at line 539 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Definition at line 547 of file stm32f7xx_hal_tim.h.

#define TIM_FLAG_COM (TIM_SR_COMIF)

Definition at line 540 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_TRIGGER (TIM_SR_TIF)

Definition at line 541 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE (TIM_SR_UIF)

Definition at line 535 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Definition at line 564 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)

Definition at line 555 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)

Definition at line 556 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)

Definition at line 557 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)

Definition at line 558 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)

Definition at line 559 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Definition at line 560 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Definition at line 562 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)

Definition at line 561 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 563 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

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STM32F745xx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 576 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 575 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 572 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 573 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 574 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 584 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 585 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 586 of file stm32f7xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 587 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 595 of file stm32f7xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 596 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 604 of file stm32f7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 605 of file stm32f7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 606 of file stm32f7xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 607 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_OSSR_DISABLE ((uint32_t)0x0000)

Definition at line 616 of file stm32f7xx_hal_tim.h.

#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)

Definition at line 615 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_OSSI_DISABLE ((uint32_t)0x0000)

Definition at line 625 of file stm32f7xx_hal_tim.h.

#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)

Definition at line 624 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Define Documentation

#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)

Definition at line 634 of file stm32f7xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)

Definition at line 635 of file stm32f7xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Definition at line 636 of file stm32f7xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)

Definition at line 633 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Break Input State

Defines
TIM Break Input State
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_BREAK_DISABLE ((uint32_t)0x0000)

Definition at line 644 of file stm32f7xx_hal_tim.h.

#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)

Definition at line 643 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Break Polarity

Defines
TIM Break Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Define Documentation

#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Definition at line 653 of file stm32f7xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)

Definition at line 652 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM AOE Bit State

Defines
TIM AOE Bit State
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)

Definition at line 662 of file stm32f7xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)

Definition at line 661 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET ((uint32_t)0x0000)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Define Documentation

#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)

Definition at line 671 of file stm32f7xx_hal_tim.h.

#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 673 of file stm32f7xx_hal_tim.h.

#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)

Definition at line 674 of file stm32f7xx_hal_tim.h.

#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))

Definition at line 675 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))

Definition at line 676 of file stm32f7xx_hal_tim.h.

#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 677 of file stm32f7xx_hal_tim.h.

#define TIM_TRGO_RESET ((uint32_t)0x0000)

Definition at line 670 of file stm32f7xx_hal_tim.h.

#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)

Definition at line 672 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Master Slave Mode

Defines
TIM Master Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)

Definition at line 686 of file stm32f7xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)

Definition at line 685 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 ((uint32_t)0x0000)
#define | TIM_TS_ITR1 ((uint32_t)0x0010)
#define | TIM_TS_ITR2 ((uint32_t)0x0020)
#define | TIM_TS_ITR3 ((uint32_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint32_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint32_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define | TIM_TS_ETRF ((uint32_t)0x0070)
#define | TIM_TS_NONE ((uint32_t)0xFFFF)

Define Documentation

#define TIM_TS_ETRF ((uint32_t)0x0070)

Definition at line 701 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 ((uint32_t)0x0000)

Definition at line 694 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 ((uint32_t)0x0010)

Definition at line 695 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 ((uint32_t)0x0020)

Definition at line 696 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 ((uint32_t)0x0030)

Definition at line 697 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE ((uint32_t)0xFFFF)

Definition at line 702 of file stm32f7xx_hal_tim.h.

#define TIM_TS_TI1F_ED ((uint32_t)0x0040)

Definition at line 698 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 ((uint32_t)0x0050)

Definition at line 699 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 ((uint32_t)0x0060)

Definition at line 700 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 714 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 713 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 710 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 711 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 712 of file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 722 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 723 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 724 of file stm32f7xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 725 of file stm32f7xx_hal_tim.h.

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STM32F745xx HAL User Manual: TIM TI1 Selection

Defines
TIM TI1 Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Define Documentation

#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)

Definition at line 734 of file stm32f7xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Definition at line 735 of file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM DMA Base address

Defines
TIM DMA Base address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 (0x00000000)
#define | TIM_DMABASE_CR2 (0x00000001)
#define | TIM_DMABASE_SMCR (0x00000002)
#define | TIM_DMABASE_DIER (0x00000003)
#define | TIM_DMABASE_SR (0x00000004)
#define | TIM_DMABASE_EGR (0x00000005)
#define | TIM_DMABASE_CCMR1 (0x00000006)
#define | TIM_DMABASE_CCMR2 (0x00000007)
#define | TIM_DMABASE_CCER (0x00000008)
#define | TIM_DMABASE_CNT (0x00000009)
#define | TIM_DMABASE_PSC (0x0000000A)
#define | TIM_DMABASE_ARR (0x0000000B)
#define | TIM_DMABASE_RCR (0x0000000C)
#define | TIM_DMABASE_CCR1 (0x0000000D)
#define | TIM_DMABASE_CCR2 (0x0000000E)
#define | TIM_DMABASE_CCR3 (0x0000000F)
#define | TIM_DMABASE_CCR4 (0x00000010)
#define | TIM_DMABASE_BDTR (0x00000011)
#define | TIM_DMABASE_DCR (0x00000012)
#define | TIM_DMABASE_OR (0x00000013)

Define Documentation

#define TIM_DMABASE_ARR (0x0000000B)

Definition at line 754 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_BDTR (0x00000011)

Definition at line 760 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCER (0x00000008)

Definition at line 751 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 (0x00000006)

Definition at line 749 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 (0x00000007)

Definition at line 750 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCR1 (0x0000000D)

Definition at line 756 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCR2 (0x0000000E)

Definition at line 757 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCR3 (0x0000000F)

Definition at line 758 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CCR4 (0x00000010)

Definition at line 759 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CNT (0x00000009)

Definition at line 752 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CR1 (0x00000000)

Definition at line 743 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_CR2 (0x00000001)

Definition at line 744 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_DCR (0x00000012)

Definition at line 761 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_DIER (0x00000003)

Definition at line 746 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_EGR (0x00000005)

Definition at line 748 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_OR (0x00000013)

Definition at line 762 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_PSC (0x0000000A)

Definition at line 753 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_RCR (0x0000000C)

Definition at line 755 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_SMCR (0x00000002)

Definition at line 745 of file stm32f7xx_hal_tim.h.

#define TIM_DMABASE_SR (0x00000004)

Definition at line 747 of file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)

Definition at line 779 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)

Definition at line 780 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)

Definition at line 781 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)

Definition at line 782 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)

Definition at line 783 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)

Definition at line 784 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)

Definition at line 785 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)

Definition at line 786 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)

Definition at line 787 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)

Definition at line 770 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)

Definition at line 771 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)

Definition at line 772 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)

Definition at line 773 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)

Definition at line 774 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)

Definition at line 775 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)

Definition at line 776 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)

Definition at line 777 of file stm32f7xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)

Definition at line 778 of file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMA Handle index

Defines
DMA Handle index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x1)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 796 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x2)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 797 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x3)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 798 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x4)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 799 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5)

Index of the DMA handle used for Commutation DMA requests

Definition at line 800 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6)

Index of the DMA handle used for Trigger DMA requests

Definition at line 801 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0)

Index of the DMA handle used for Update DMA requests

Definition at line 795 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Channel CC State

Defines
Channel CC State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE ((uint32_t)0x0001)
#define | TIM_CCx_DISABLE ((uint32_t)0x0000)
#define | TIM_CCxN_ENABLE ((uint32_t)0x0004)
#define | TIM_CCxN_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_CCx_DISABLE ((uint32_t)0x0000)

Definition at line 810 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE ((uint32_t)0x0001)

Definition at line 809 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE ((uint32_t)0x0000)

Definition at line 812 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE ((uint32_t)0x0004)

Definition at line 811 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
Enable the TIM update source request.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Disable the TIM update source request.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
#define | __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Definition at line 905 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Definition at line 908 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
                            { \
                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
                            } \
                          } \
                        } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 863 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Definition at line 903 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Definition at line 902 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 836 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Definition at line 901 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Definition at line 900 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Gets the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 969 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Gets the TIM Clock Division value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 993 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Gets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 950 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Definition at line 904 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)

Gets the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
None

Definition at line 1030 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Definition at line 907 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Definition at line 910 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
                            { \
                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
                            } \
                          } \
                        } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 889 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 850 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

Reset TIM handle state.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 829 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                  \
                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
                          } while(0)

Sets the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__AUTORELOAD__,: specifies the Counter register new value.
Return values:
None

Definition at line 959 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                            \
                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
                         }while(0)

Sets the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__,: Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Note:
The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Return values:
None

Definition at line 1052 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                             \
                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
                          } while(0)

Sets the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__CKD__,: specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1
  • TIM_CLOCKDIVISION_DIV2
  • TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 982 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Sets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__COUNTER__,: specifies the Counter register new value.
Return values:
None

Definition at line 943 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
                          } while(0)

Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1013 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))

Definition at line 911 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))

Disable the TIM update source request.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 879 of file stm32f7xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))

Enable the TIM update source request.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 843 of file stm32f7xx_hal_tim.h.

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 855 of file stm32f7xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 856 of file stm32f7xx_hal_tim.h.

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))

Definition at line 931 of file stm32f7xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))

Definition at line 919 of file stm32f7xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))

Definition at line 925 of file stm32f7xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))

Definition at line 913 of file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Private macros to check input parameters

Defines
TIM Private macros to check input parameters
TIM Private Macros

Defines

#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OUTPUT_STATE(STATE)
#define | IS_TIM_OUTPUTN_STATE(STATE)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))
#define | IS_TIM_GET_IT(__IT__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_FLAG(__FLAG__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1410 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1407 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                       ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 1404 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xF)

Definition at line 1391 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                    ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1383 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1386 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1284 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xF)

Definition at line 1381 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1370 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1376 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1359 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                       ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1278 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1) || \
                                   ((__BASE__) == TIM_DMABASE_CR2) || \
                                   ((__BASE__) == TIM_DMABASE_SMCR) || \
                                   ((__BASE__) == TIM_DMABASE_DIER) || \
                                   ((__BASE__) == TIM_DMABASE_SR) || \
                                   ((__BASE__) == TIM_DMABASE_EGR) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER) || \
                                   ((__BASE__) == TIM_DMABASE_CNT) || \
                                   ((__BASE__) == TIM_DMABASE_PSC) || \
                                   ((__BASE__) == TIM_DMABASE_ARR) || \
                                   ((__BASE__) == TIM_DMABASE_RCR) || \
                                   ((__BASE__) == TIM_DMABASE_CCR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR4) || \
                                   ((__BASE__) == TIM_DMABASE_BDTR) || \
                                   ((__BASE__) == TIM_DMABASE_DCR) || \
                                   ((__BASE__) == TIM_DMABASE_OR))

Definition at line 1461 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1482 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))

Definition at line 1341 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
                                       ((__MODE__) == TIM_ENCODERMODE_TI2) || \
                                       ((__MODE__) == TIM_ENCODERMODE_TI12))

Definition at line 1325 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))

Definition at line 1343 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                      ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1288 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_FLAG ( __FLAG__ )
Value:
(((__FLAG__) == TIM_FLAG_UPDATE) || \
                               ((__FLAG__) == TIM_FLAG_CC1)     || \
                               ((__FLAG__) == TIM_FLAG_CC2)     || \
                               ((__FLAG__) == TIM_FLAG_CC3)     || \
                               ((__FLAG__) == TIM_FLAG_CC4)     || \
                               ((__FLAG__) == TIM_FLAG_COM)     || \
                               ((__FLAG__) == TIM_FLAG_TRIGGER) || \
                               ((__FLAG__) == TIM_FLAG_BREAK)   || \
                               ((__FLAG__) == TIM_FLAG_BREAK2)  || \
                               ((__FLAG__) == TIM_FLAG_CC1OF)   || \
                               ((__FLAG__) == TIM_FLAG_CC2OF)   || \
                               ((__FLAG__) == TIM_FLAG_CC3OF)   || \
                               ((__FLAG__) == TIM_FLAG_CC4OF))

Definition at line 1345 of file stm32f7xx_hal_tim.h.

#define IS_TIM_GET_IT ( __IT__ )
Value:
(((__IT__) == TIM_IT_UPDATE)  || \
                               ((__IT__) == TIM_IT_CC1)     || \
                               ((__IT__) == TIM_IT_CC2)     || \
                               ((__IT__) == TIM_IT_CC3)     || \
                               ((__IT__) == TIM_IT_CC4)     || \
                               ((__IT__) == TIM_IT_COM)     || \
                               ((__IT__) == TIM_IT_TRIGGER) || \
                               ((__IT__) == TIM_IT_BREAK))

Definition at line 1332 of file stm32f7xx_hal_tim.h.

#define IS_TIM_IC_FILTER ( ICFILTER ) ((ICFILTER) <= 0xF)

Definition at line 1501 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                          ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                          ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1309 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1317 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1313 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                                      ((SELECTION) == TIM_TS_ITR1) || \
                                                      ((SELECTION) == TIM_TS_ITR2) || \
                                                      ((SELECTION) == TIM_TS_ITR3))

Definition at line 1434 of file stm32f7xx_hal_tim.h.

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
                                                               ((__SELECTION__) == TIM_TS_NONE))

Definition at line 1439 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define IS_TIM_IT ( __IT__ ) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))

Definition at line 1329 of file stm32f7xx_hal_tim.h.

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                      ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
                                      ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
                                      ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 1399 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                     ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1422 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                          ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1297 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                        ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1303 of file stm32f7xx_hal_tim.h.

Referenced by TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                           ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1300 of file stm32f7xx_hal_tim.h.

Referenced by TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                         ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1306 of file stm32f7xx_hal_tim.h.

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                   ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1322 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                      ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 1396 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                      ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 1393 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))

Definition at line 1291 of file stm32f7xx_hal_tim.h.

#define IS_TIM_OUTPUTN_STATE ( STATE )
Value:
(((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
                                     ((STATE) == TIM_OUTPUTNSTATE_ENABLE))

Definition at line 1294 of file stm32f7xx_hal_tim.h.

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1458 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET) || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

Definition at line 1413 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
                                                 ((__SELECTION__) == TIM_TS_ETRF))

Definition at line 1425 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xF)

Definition at line 1456 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1445 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1451 of file stm32f7xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 4 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Function Documentation

void HAL_TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4655 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void HAL_TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4622 of file stm32f7xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void HAL_TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4607 of file stm32f7xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM peripheral
Structure,: pointer on TIM Time Base required parameters
Return values:
None

Definition at line 4720 of file stm32f7xx_hal_tim.c.

References TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5491 of file stm32f7xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5461 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_SlaveConfigSynchronization(), and TIM_SlaveTimer_SetConfig().

void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 1 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4765 of file stm32f7xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4830 of file stm32f7xx_hal_tim.c.

References assert_param, IS_TIM_OCN_POLARITY, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 3 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4897 of file stm32f7xx_hal_tim.c.

References assert_param, IS_TIM_OCN_POLARITY, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 4 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4963 of file stm32f7xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5166 of file stm32f7xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIMEx Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 239 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 166 of file stm32f7xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIMEx_HallSensor_MspInit(), TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 283 of file stm32f7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 267 of file stm32f7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 299 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 395 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMACaptureCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 343 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 321 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 443 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_DMA_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 368 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIMEx Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 500 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 706 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 562 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 531 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 822 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 630 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIMEx Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 923 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1128 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_DMADelayPulseCplt(), HAL_TIM_DMAError(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 984 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 953 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1244 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1052 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIMEx Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complemetary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1332 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1388 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1358 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1420 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIMEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t OCRef)
Group channel 5 and channel 1, 2 or 3.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
    (+) Configure External Clock source.
    (+) Configure Complementary channels, break features and dead time.
    (+) Configure Master and the Slave synchronization.
    (+) Configure the commutation event in case of use of the Hall sensor interface.
    (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim,: TIM handle
sClearInputConfig,: pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
  • TIM_Channel_5: TIM Channel 5
  • TIM_Channel_6: TIM Channel 6
Return values:
None

Definition at line 1892 of file stm32f7xx_hal_tim_ex.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, TIM_CLEARINPUTSOURCE_OCREFCLR, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: TIM Output Compare handle
sConfig,: TIM Output Compare configuration structure
Channel : TIM Channels to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
  • TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
Return values:
HAL status

Definition at line 1646 of file stm32f7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: TIM PWM handle
sConfig,: TIM PWM configuration structure
Channel : TIM Channels to be configured This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
  • TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
Return values:
HAL status

Definition at line 1747 of file stm32f7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sBreakDeadTimeConfig,: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
HAL status

Definition at line 2112 of file stm32f7xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, BDTR_BK2F_SHIFT, BDTR_BKF_SHIFT, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, HAL_TIM_STATE_BUSY, TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
InputTrigger,: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource,: the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1490 of file stm32f7xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
: The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
InputTrigger,: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource,: the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1594 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_TIM_DMAError(), HAL_TIMEx_DMACommutationCplt(), TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
InputTrigger,: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource,: the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1540 of file stm32f7xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OCRef
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim,: TIM handle.
OCRef,: specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 2216 of file stm32f7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sMasterConfig,: pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 2051 of file stm32f7xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, and TIM_MasterConfigTypeDef::MasterSlaveMode.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Remap,: specifies the TIM input remapping source. This parameter can be one of the following values:
  • TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
  • TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
  • TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
  • TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
  • TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
  • TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
  • TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
  • TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
  • TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
  • TIM_TIM11_SPDIF: SPDIF Frame synchronous
  • TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock (HSE divided by a programmable prescaler)
  • TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
Return values:
HAL status

Definition at line 2187 of file stm32f7xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_REMAP, and TIM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIMEx Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extension Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extension TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2282 of file stm32f7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_CommutationCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2266 of file stm32f7xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_DMACommutationCplt().

void HAL_TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2332 of file stm32f7xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIMEx Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extension Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 2317 of file stm32f7xx_hal_tim_ex.c.

References TIM_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Exported Functions

Modules | Functions
TIMEx Exported Functions
TIMEx

Modules

Extended Timer Hall Sensor functions

Timer Hall Sensor functions.

Extended Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Extended Timer Complementary PWM functions

Timer Complementary PWM functions.

Extended Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

Functions

void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.

Function Documentation

void HAL_TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2332 of file stm32f7xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
ChannelNState,: specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2353 of file stm32f7xx_hal_tim_ex.c.

References assert_param, and IS_TIM_COMPLEMENTARY_CHANNELS.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 5 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 2376 of file stm32f7xx_hal_tim_ex.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 6 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 2428 of file stm32f7xx_hal_tim_ex.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32f7xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 66 of file stm32f7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 77 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 75 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 69 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 72 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32f7xx_hal_tim_ex.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Definition at line 84 of file stm32f7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection. This parameter can be a value of TIM Master Mode Selection

Definition at line 85 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIMEx Master Mode Selection 2 (TRGO2)

Definition at line 87 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection. This parameter can be a value of TIM Master Slave Mode

Definition at line 89 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32f7xx_hal_tim_ex.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 98 of file stm32f7xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM AOE Bit State

Definition at line 120 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 118 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity This parameter can be a value of TIMEx Break2 Polarity

Definition at line 116 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State This parameter can be a value of TIMEx Break input 2 Enable

Definition at line 114 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 112 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity. This parameter can be a value of TIM Break Polarity

Definition at line 110 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State. This parameter can be a value of TIM Break Input State

Definition at line 108 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 106 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level. This parameter can be a value of TIM Lock level

Definition at line 104 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode. This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 102 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode. This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 100 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_tim_ex.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Channel

Defines
TIMEx Channel
TIMEx Exported Constants

Defines

#define | TIM_CHANNEL_1 ((uint32_t)0x0000)
#define | TIM_CHANNEL_2 ((uint32_t)0x0004)
#define | TIM_CHANNEL_3 ((uint32_t)0x0008)
#define | TIM_CHANNEL_4 ((uint32_t)0x000C)
#define | TIM_CHANNEL_5 ((uint32_t)0x0010)
#define | TIM_CHANNEL_6 ((uint32_t)0x0014)
#define | TIM_CHANNEL_ALL ((uint32_t)0x003C)

Define Documentation

#define TIM_CHANNEL_1 ((uint32_t)0x0000)

Definition at line 136 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_2 ((uint32_t)0x0004)

Definition at line 137 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_3 ((uint32_t)0x0008)

Definition at line 138 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_4 ((uint32_t)0x000C)

Definition at line 139 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_5 ((uint32_t)0x0010)

Definition at line 140 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 ((uint32_t)0x0014)

Definition at line 141 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL ((uint32_t)0x003C)

Definition at line 142 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Output Compare and PWM Modes

Defines
TIMEx Output Compare and PWM Modes
TIMEx Exported Constants

Defines

#define | TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)

Definition at line 152 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Definition at line 164 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Definition at line 165 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Definition at line 162 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Definition at line 163 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Definition at line 157 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)

Definition at line 158 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)

Definition at line 153 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

Definition at line 155 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Definition at line 156 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)

Definition at line 160 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Definition at line 161 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_TIMING ((uint32_t)0x0000)

Definition at line 151 of file stm32f7xx_hal_tim_ex.h.

#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Definition at line 154 of file stm32f7xx_hal_tim_ex.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Remap

Defines
TIMEx Remap
TIMEx Exported Constants

Defines

#define | TIM_TIM2_TIM8_TRGO (0x00000000)
#define | TIM_TIM2_ETH_PTP (0x00000400)
#define | TIM_TIM2_USBFS_SOF (0x00000800)
#define | TIM_TIM2_USBHS_SOF (0x00000C00)
#define | TIM_TIM5_GPIO (0x00000000)
#define | TIM_TIM5_LSI (0x00000040)
#define | TIM_TIM5_LSE (0x00000080)
#define | TIM_TIM5_RTC (0x000000C0)
#define | TIM_TIM11_GPIO (0x00000000)
#define | TIM_TIM11_SPDIFRX (0x00000001)
#define | TIM_TIM11_HSE (0x00000002)
#define | TIM_TIM11_MCO1 (0x00000003)

Define Documentation

#define TIM_TIM11_GPIO (0x00000000)

Definition at line 181 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM11_HSE (0x00000002)

Definition at line 183 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM11_MCO1 (0x00000003)

Definition at line 184 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM11_SPDIFRX (0x00000001)

Definition at line 182 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM2_ETH_PTP (0x00000400)

Definition at line 174 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM2_TIM8_TRGO (0x00000000)

Definition at line 173 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM2_USBFS_SOF (0x00000800)

Definition at line 175 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM2_USBHS_SOF (0x00000C00)

Definition at line 176 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM5_GPIO (0x00000000)

Definition at line 177 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM5_LSE (0x00000080)

Definition at line 179 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM5_LSI (0x00000040)

Definition at line 178 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TIM5_RTC (0x000000C0)

Definition at line 180 of file stm32f7xx_hal_tim_ex.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Clear Input Source

Defines
TIMEx Clear Input Source
TIMEx Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define | TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)

Definition at line 192 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)

Definition at line 194 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)

Definition at line 193 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Break input 2 Enable

Defines
TIMEx Break input 2 Enable
TIMEx Exported Constants

Defines

#define | TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
#define | TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)

Define Documentation

#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)

Definition at line 202 of file stm32f7xx_hal_tim_ex.h.

#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)

Definition at line 203 of file stm32f7xx_hal_tim_ex.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Break2 Polarity

Defines
TIMEx Break2 Polarity
TIMEx Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
#define | TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)

Define Documentation

#define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)

Definition at line 212 of file stm32f7xx_hal_tim_ex.h.

#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)

Definition at line 211 of file stm32f7xx_hal_tim_ex.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Group Channel 5 and Channel 1, 2 or 3

Defines
TIMEx Group Channel 5 and Channel 1, 2 or 3
TIMEx Exported Constants

Defines

#define | TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Define Documentation

#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

Definition at line 220 of file stm32f7xx_hal_tim_ex.h.

#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */

Definition at line 221 of file stm32f7xx_hal_tim_ex.h.

#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */

Definition at line 222 of file stm32f7xx_hal_tim_ex.h.

#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Definition at line 223 of file stm32f7xx_hal_tim_ex.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Master Mode Selection 2 (TRGO2)

Defines
TIMEx Master Mode Selection 2 (TRGO2)
TIMEx Exported Constants

Defines

#define | TIM_TRGO2_RESET ((uint32_t)0x00000000)
#define | TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define | TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
#define | TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Define Documentation

#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))

Definition at line 232 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 234 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))

Definition at line 235 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))

Definition at line 236 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))

Definition at line 237 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 238 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))

Definition at line 244 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))

Definition at line 243 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))

Definition at line 241 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))

Definition at line 239 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 246 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))

Definition at line 245 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))

Definition at line 240 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 242 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_RESET ((uint32_t)0x00000000)

Definition at line 231 of file stm32f7xx_hal_tim_ex.h.

#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))

Definition at line 233 of file stm32f7xx_hal_tim_ex.h.

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STM32F745xx HAL User Manual: TIMEx Slave mode

Defines
TIMEx Slave mode
TIMEx Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))

Define Documentation

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))

Definition at line 259 of file stm32f7xx_hal_tim_ex.h.

#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)

Definition at line 254 of file stm32f7xx_hal_tim_ex.h.

#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))

Definition at line 258 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))

Definition at line 256 of file stm32f7xx_hal_tim_ex.h.

#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))

Definition at line 255 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))

Definition at line 257 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Exported Macros

Defines
TIMEx Exported Macros
TIMEx

Defines

#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Gets the TIM Capture Compare Register value on runtime.

Define Documentation

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
 ((__HANDLE__)->Instance->CCR6))

Gets the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
None

Definition at line 309 of file stm32f7xx_hal_tim_ex.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__,: specifies the Capture Compare register new value.
Return values:
None

Definition at line 288 of file stm32f7xx_hal_tim_ex.h.

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STM32F745xx HAL User Manual: TIMEx Private Macros

Defines
TIMEx Private Macros
TIMEx

Defines

#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_PWMI_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_REMAP(__TIM_REMAP__)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
#define | IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
#define | IS_TIM_CLEARINPUT_SOURCE(MODE)
#define | IS_TIM_BREAK2_STATE(STATE)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
#define | IS_TIM_TRGO2_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)

Define Documentation

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 498 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( STATE )
Value:
(((STATE) == TIM_BREAK2_ENABLE) || \
                                    ((STATE) == TIM_BREAK2_DISABLE))

Definition at line 496 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __FILTER__ ) ((__FILTER__) <= 0xF)

Definition at line 492 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                  ((CHANNEL) == TIM_CHANNEL_2) || \
                                  ((CHANNEL) == TIM_CHANNEL_3) || \
                                  ((CHANNEL) == TIM_CHANNEL_4) || \
                                  ((CHANNEL) == TIM_CHANNEL_5) || \
                                  ((CHANNEL) == TIM_CHANNEL_6) || \
                                  ((CHANNEL) == TIM_CHANNEL_ALL))

Definition at line 447 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_SOURCE ( MODE )
Value:
(((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                        ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR)  || \
                                        ((MODE) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 493 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                                ((CHANNEL) == TIM_CHANNEL_2) || \
                                                ((CHANNEL) == TIM_CHANNEL_3))

Definition at line 461 of file stm32f7xx_hal_tim_ex.h.

Referenced by TIM_CCxNChannelCmd().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFF)

Definition at line 491 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_GROUPCH5 ( OCREF ) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))

Definition at line 500 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_OC_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_TIMING)             || \
                             ((MODE) == TIM_OCMODE_ACTIVE)             || \
                             ((MODE) == TIM_OCMODE_INACTIVE)           || \
                             ((MODE) == TIM_OCMODE_TOGGLE)             || \
                             ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \
                             ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \
                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))

Definition at line 471 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OPM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                      ((CHANNEL) == TIM_CHANNEL_2))

Definition at line 458 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_PWM_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_PWM1)               || \
                               ((MODE) == TIM_OCMODE_PWM2)               || \
                               ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \
                               ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \
                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 464 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_PWMI_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                       ((CHANNEL) == TIM_CHANNEL_2))

Definition at line 455 of file stm32f7xx_hal_tim_ex.h.

#define IS_TIM_REMAP ( __TIM_REMAP__ )
Value:
(((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
                                      ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
                                      ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
                                      ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
                                      ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
                                      ((__TIM_REMAP__) == TIM_TIM5_LSI)||\
                                      ((__TIM_REMAP__) == TIM_TIM5_LSE)||\
                                      ((__TIM_REMAP__) == TIM_TIM5_RTC)||\
                                      ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
                                      ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
                                      ((__TIM_REMAP__) == TIM_TIM11_HSE)||\
                                      ((__TIM_REMAP__) == TIM_TIM11_MCO1))

Definition at line 479 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_SLAVE_MODE ( MODE )
Value:
(((MODE) == TIM_SLAVEMODE_DISABLE)   || \
                                 ((MODE) == TIM_SLAVEMODE_RESET)     || \
                                 ((MODE) == TIM_SLAVEMODE_GATED)     || \
                                 ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \
                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
                                 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 518 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRGO2_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TRGO2_RESET)                        || \
                                     ((SOURCE) == TIM_TRGO2_ENABLE)                       || \
                                     ((SOURCE) == TIM_TRGO2_UPDATE)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC1)                          || \
                                     ((SOURCE) == TIM_TRGO2_OC1REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC2REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC4REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC5REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC6REF)                       || \
                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                     ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 501 of file stm32f7xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx Private Functions

TIMEx Private Functions
TIMEx
Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIMEx

Modules | Defines
TIMEx
STM32F7xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIMEx Exported Functions
TIM Exported Types
TIMEx Exported Constants
TIMEx Exported Macros
TIMEx Private Macros
TIMEx Private Functions

Defines

#define | BDTR_BKF_SHIFT (16)
#define | BDTR_BK2F_SHIFT (20)

Detailed Description

TIM Extended HAL module driver.

Define Documentation

#define BDTR_BK2F_SHIFT (20)

Definition at line 119 of file stm32f7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define BDTR_BKF_SHIFT (16)

Definition at line 118 of file stm32f7xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M bit (8-bits or 9-bits),
             please refer to Reference manual for possible UART frame formats.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
    configuration procedures (details for the procedures are available in reference manual (RM0329)).

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .

Parameters:
huart,: UART handle
Return values:
HAL status

Definition at line 290 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_HandleTypeDef::State, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .

Parameters:
huart,: uart handle
BreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
Return values:
HAL status

Definition at line 349 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_LIN_WORD_LENGTH, IS_UART_LIN_BREAK_DETECT_LENGTH, UART_HandleTypeDef::Lock, UART_HandleTypeDef::State, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initializes the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart,: UART handle
Address,: UART node address (4-, 6-, 7- or 8-bit long)
WakeUpMethod,: specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection
Return values:
HAL status

Definition at line 423 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, UART_HandleTypeDef::Lock, UART_HandleTypeDef::State, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitializes the UART peripheral.

Parameters:
huart,: uart handle
Return values:
HAL status

Definition at line 488 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .

Parameters:
huart,: uart handle
Return values:
HAL status

Definition at line 227 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_HandleTypeDef::State, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

UART MSP DeInit.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 540 of file stm32f7xx_hal_uart.c.

Referenced by HAL_UART_DeInit().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

UART MSP Init.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 525 of file stm32f7xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles UART Communication Timeout.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode Function called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT()
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode Function called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (+) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()
        (+) UART_Transmit_IT()
        (+) UART_Receive_IT()

    (#) No-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pauses the DMA Transfer.

Parameters:
huart,: UART handle
Return values:
None

Definition at line 1015 of file stm32f7xx_hal_uart.c.

References HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resumes the DMA Transfer.

Parameters:
huart,: UART handle
Return values:
None

Definition at line 1049 of file stm32f7xx_hal_uart.c.

References __HAL_UART_CLEAR_IT, __HAL_UART_ENABLE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, UART_HandleTypeDef::Instance, UART_HandleTypeDef::State, and UART_CLEAR_OREF.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stops the DMA Transfer.

Parameters:
huart,: UART handle
Return values:
None

Definition at line 1094 of file stm32f7xx_hal_uart.c.

References HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::State.

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callbacks.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1431 of file stm32f7xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), and UART_DMAError().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

This function handles UART interrupt request.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1128 of file stm32f7xx_hal_uart.c.

References __HAL_UART_CLEAR_FEFLAG, __HAL_UART_CLEAR_NEFLAG, __HAL_UART_CLEAR_OREFLAG, __HAL_UART_CLEAR_PEFLAG, __HAL_UART_GET_IT, __HAL_UART_GET_IT_SOURCE, __HAL_UART_SEND_REQ, UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::State, UART_EndTransmit_IT(), UART_IT_ERR, UART_IT_FE, UART_IT_NE, UART_IT_ORE, UART_IT_PE, UART_IT_RXNE, UART_IT_TC, UART_IT_TXE, UART_Receive_IT(), UART_RXDATA_FLUSH_REQUEST, and UART_Transmit_IT().

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
huart,: uart handle
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout : Timeout duration
Return values:
HAL status

Definition at line 696 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_HandleTypeDef::State, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
huart,: uart handle
pData,: pointer to data buffer
Size,: amount of data to be received
Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position)
Return values:
HAL status

Definition at line 954 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxXferSize, UART_HandleTypeDef::State, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
huart,: uart handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 827 of file stm32f7xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_HandleTypeDef::State, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, and UART_MASK_COMPUTATION.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callbacks.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1401 of file stm32f7xx_hal_uart.c.

Referenced by UART_DMAReceiveCplt(), and UART_Receive_IT().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callbacks.

Parameters:
huart,: UART handle
Return values:
None

Definition at line 1416 of file stm32f7xx_hal_uart.c.

Referenced by UART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
huart,: uart handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout : Timeout duration
Return values:
HAL status

Definition at line 618 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::State, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
huart,: uart handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 884 of file stm32f7xx_hal_uart.c.

References __HAL_UART_CLEAR_IT, UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::State, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), UART_FLAG_TC, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
huart,: uart handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 776 of file stm32f7xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::State, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_IT_ERR, and UART_IT_TXE.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callbacks.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1371 of file stm32f7xx_hal_uart.c.

Referenced by UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_Transmit_IT().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callbacks.

Parameters:
huart,: UART handle
Return values:
None

Definition at line 1386 of file stm32f7xx_hal_uart.c.

Referenced by UART_DMATxHalfCplt().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1356 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::State, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1313 of file stm32f7xx_hal_uart.c.

References HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxXferCount, and UART_HandleTypeDef::State.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1344 of file stm32f7xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback().

Referenced by HAL_UART_Receive_DMA().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1273 of file stm32f7xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, and UART_IT_TC.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1301 of file stm32f7xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback().

Referenced by HAL_UART_Transmit_DMA().

static HAL_StatusTypeDef UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1510 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), UART_HandleTypeDef::State, and UART_IT_TC.

Referenced by HAL_UART_IRQHandler().

static HAL_StatusTypeDef UART_Receive_IT ( UART_HandleTypeDef * huart ) [static]

Receive an amount of data in interrupt mode Function called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()

Parameters:
huart,: UART handle
Return values:
HAL status

Definition at line 1537 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::State, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

static HAL_StatusTypeDef UART_Transmit_IT ( UART_HandleTypeDef * huart ) [static]

Send an amount of data in interrupt mode Function called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT()

Parameters:
huart,: UART handle
Return values:
HAL status

Definition at line 1448 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_BUSY_TX_RX, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, HAL_UART_TxCpltCallback(), UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::State, UART_HandleTypeDef::TxXferCount, UART_FLAG_TC, UART_IT_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  |

This function handles UART Communication Timeout.

Parameters:
huart,: UART handle
Flag,: specifies the UART flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1208 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, __HAL_UART_GET_FLAG, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::State, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, and UART_IT_TXE.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_CheckIdleState(), and UART_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (doesn't mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (doesn't mean it actually wakes up the software, as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
return the UART state
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enables the UART receiver and disables the UART transmitter.

Parameters:
huart,: UART handle
Return values:
HAL status

Definition at line 1948 of file stm32f7xx_hal_uart.c.

References HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enables the UART transmitter and disables the UART receiver.

Parameters:
huart,: UART handle
Return values:
HAL status
None

Definition at line 1925 of file stm32f7xx_hal_uart.c.

References HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmits break characters.

Parameters:
huart,: UART handle
Return values:
HAL status

Definition at line 1972 of file stm32f7xx_hal_uart.c.

References assert_param, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::State, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (doesn't mean it actually wakes up the software, as it may not have been in mute mode at this very moment).

Parameters:
huart,: uart handle
Return values:
HAL status

Definition at line 1644 of file stm32f7xx_hal_uart.c.

References HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::State, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (doesn't mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)

Parameters:
huart,: UART handle
Return values:
HAL status

Definition at line 1623 of file stm32f7xx_hal_uart.c.

References HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::State, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.

Parameters:
huart,: uart handle
Return values:
HAL status

Definition at line 1665 of file stm32f7xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART error code.

Parameters:
huart : pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 1688 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

return the UART state

Parameters:
huart,: uart handle
Return values:
HAL state

Definition at line 1677 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::State.

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1809 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart,: uart handle
Return values:
HAL status

Definition at line 1884 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, UART_HandleTypeDef::State, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1698 of file stm32f7xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_PARITY, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LSE_VALUE, UART_InitTypeDef::Mode, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, UART_InitTypeDef::StopBits, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_PCLK2, UART_CLOCKSOURCE_SYSCLK, UART_CLOCKSOURCE_UNDEFINED, UART_CR1_FIELDS, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GETCLOCKSOURCE, UART_OVERSAMPLING_8, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
return the UART state
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART error code.

Parameters:
huart : pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 1688 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

return the UART state

Parameters:
huart,: uart handle
Return values:
HAL state

Definition at line 1677 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Exported Types

Data Structures | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00, HAL_UART_STATE_READY = 0x01, HAL_UART_STATE_BUSY = 0x02, HAL_UART_STATE_BUSY_TX = 0x12,
HAL_UART_STATE_BUSY_RX = 0x22, HAL_UART_STATE_BUSY_TX_RX = 0x32, HAL_UART_STATE_TIMEOUT = 0x03, HAL_UART_STATE_ERROR = 0x04
}
HAL UART State structures definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00, UART_CLOCKSOURCE_PCLK2 = 0x01, UART_CLOCKSOURCE_HSI = 0x02, UART_CLOCKSOURCE_SYSCLK = 0x04,
UART_CLOCKSOURCE_LSE = 0x08, UART_CLOCKSOURCE_UNDEFINED = 0x10
}
UART clock sources definition. More...

Enumeration Type Documentation

enum HAL_UART_StateTypeDef

HAL UART State structures definition.

Enumerator:
HAL_UART_STATE_RESET

Peripheral is not initialized

HAL_UART_STATE_READY

Peripheral Initialized and ready for use

HAL_UART_STATE_BUSY

an internal process is ongoing

HAL_UART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_UART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_UART_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_UART_STATE_TIMEOUT

Timeout state

HAL_UART_STATE_ERROR

Error

Definition at line 148 of file stm32f7xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_PCLK1

PCLK1 clock source

UART_CLOCKSOURCE_PCLK2

PCLK2 clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 163 of file stm32f7xx_hal_uart.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32f7xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling

Detailed Description

UART Init Structure definition.

Definition at line 65 of file stm32f7xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula:

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1

Definition at line 67 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control

Definition at line 92 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode

Definition at line 89 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method

Definition at line 99 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). This parameter can be a value of UART Over Sampling

Definition at line 96 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 82 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits

Definition at line 79 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UARTEx Word Length

Definition at line 76 of file stm32f7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_uart.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initialization structure definition. More...

#include <stm32f7xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initialization structure definition.

Definition at line 107 of file stm32f7xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type

Definition at line 109 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable

Definition at line 132 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode

Definition at line 135 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion

Definition at line 119 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error

Definition at line 129 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First

Definition at line 139 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable

Definition at line 126 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion

Definition at line 116 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap

Definition at line 123 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion

Definition at line 113 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_uart.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32f7xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 176 of file stm32f7xx_hal_uart.h.

Field Documentation

UART_AdvFeatureInitTypeDef UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 182 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

__IO uint32_t UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 206 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), and UART_DMAError().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 200 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_DMAStop(), and HAL_UART_Receive_DMA().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 198 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_DMAStop(), and HAL_UART_Transmit_DMA().

UART_InitTypeDef UART_HandleTypeDef::Init

UART communication parameters

Definition at line 180 of file stm32f7xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

USART_TypeDef* UART_HandleTypeDef::Instance

UART registers base address

Definition at line 178 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

HAL_LockTypeDef UART_HandleTypeDef::Lock

Locking object

Definition at line 202 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

uint16_t UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 196 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 190 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 184 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 194 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAError(), UART_DMAReceiveCplt(), and UART_Receive_IT().

uint16_t UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 192 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::State

UART communication state

Definition at line 204 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

uint16_t UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 188 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_DMATransmitCplt(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 186 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_uart.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Error Definition

Defines
UART Error Definition
UART Exported Constants

Defines

#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010)

Define Documentation

#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 226 of file stm32f7xx_hal_uart.h.

Referenced by UART_DMAError().

#define HAL_UART_ERROR_FE ((uint32_t)0x00000004)

frame error

Definition at line 224 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NE ((uint32_t)0x00000002)

Noise error

Definition at line 223 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 221 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_CheckIdleState().

#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008)

Overrun error

Definition at line 225 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE ((uint32_t)0x00000001)

Parity error

Definition at line 222 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_1 ((uint32_t)0x0000)
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Define Documentation

#define UART_STOPBITS_1 ((uint32_t)0x0000)

Definition at line 233 of file stm32f7xx_hal_uart.h.

#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Definition at line 234 of file stm32f7xx_hal_uart.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE ((uint32_t)0x00000000)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 243 of file stm32f7xx_hal_uart.h.

#define UART_PARITY_NONE ((uint32_t)0x00000000)

Definition at line 242 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 244 of file stm32f7xx_hal_uart.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Define Documentation

#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)

Definition at line 254 of file stm32f7xx_hal_uart.h.

#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)

Definition at line 252 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)

Definition at line 253 of file stm32f7xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Definition at line 255 of file stm32f7xx_hal_uart.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define UART_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 263 of file stm32f7xx_hal_uart.h.

#define UART_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 264 of file stm32f7xx_hal_uart.h.

#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 265 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE ((uint32_t)0x00000000)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define UART_STATE_DISABLE ((uint32_t)0x00000000)

Definition at line 273 of file stm32f7xx_hal_uart.h.

#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Definition at line 274 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)

Definition at line 282 of file stm32f7xx_hal_uart.h.

#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Definition at line 283 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

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STM32F745xx HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

Definition at line 291 of file stm32f7xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Definition at line 292 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Definition at line 303 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)

Definition at line 302 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)

Definition at line 301 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)

Definition at line 300 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Receiver TimeOut

Defines
UART Receiver TimeOut
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)

Definition at line 311 of file stm32f7xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Definition at line 312 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE ((uint32_t)0x00000000)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Define Documentation

#define UART_LIN_DISABLE ((uint32_t)0x00000000)

Definition at line 320 of file stm32f7xx_hal_uart.h.

#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Definition at line 321 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)

Definition at line 329 of file stm32f7xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Definition at line 330 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000)

Definition at line 338 of file stm32f7xx_hal_uart.h.

#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Definition at line 339 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE ((uint32_t)0x0000)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define UART_DMA_RX_DISABLE ((uint32_t)0x0000)

Definition at line 347 of file stm32f7xx_hal_uart.h.

#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Definition at line 348 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

Define Documentation

#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000)

Definition at line 356 of file stm32f7xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

Definition at line 357 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Definition at line 366 of file stm32f7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)

Definition at line 365 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 374 of file stm32f7xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)

Mute Mode Request

Definition at line 376 of file stm32f7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 377 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)

Send Break Request

Definition at line 375 of file stm32f7xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 378 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)
#define | UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)

Definition at line 393 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)

Definition at line 389 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)

Definition at line 392 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Definition at line 394 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)

Definition at line 386 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)

Definition at line 388 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)

Definition at line 391 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)

Definition at line 390 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)

Definition at line 387 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32F745xx HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)

Definition at line 402 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Definition at line 403 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)

Definition at line 411 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Definition at line 412 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)

Definition at line 420 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Definition at line 421 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)

Definition at line 429 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Definition at line 430 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Definition at line 439 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)

Definition at line 438 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)

Definition at line 447 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

Definition at line 448 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32F745xx HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Definition at line 457 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)

Definition at line 456 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)

Definition at line 465 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Definition at line 466 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)

Definition at line 474 of file stm32f7xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

Definition at line 475 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)

Definition at line 483 of file stm32f7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

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STM32F745xx HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Define Documentation

#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)

Definition at line 491 of file stm32f7xx_hal_uart.h.

#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Definition at line 492 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)

Definition at line 500 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)

Definition at line 508 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK ((uint32_t)0x001F)

Define Documentation

#define UART_IT_MASK ((uint32_t)0x001F)

Definition at line 516 of file stm32f7xx_hal_uart.h.

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STM32F745xx HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF

Definition at line 524 of file stm32f7xx_hal_uart.h.

Referenced by UART_CheckIdleState(), and UART_Transmit_IT().

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STM32F745xx HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_TEACK ((uint32_t)0x00200000)
#define | UART_FLAG_SBKF ((uint32_t)0x00040000)
#define | UART_FLAG_CMF ((uint32_t)0x00020000)
#define | UART_FLAG_BUSY ((uint32_t)0x00010000)
#define | UART_FLAG_ABRF ((uint32_t)0x00008000)
#define | UART_FLAG_ABRE ((uint32_t)0x00004000)
#define | UART_FLAG_EOBF ((uint32_t)0x00001000)
#define | UART_FLAG_RTOF ((uint32_t)0x00000800)
#define | UART_FLAG_CTS ((uint32_t)0x00000400)
#define | UART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | UART_FLAG_LBDF ((uint32_t)0x00000100)
#define | UART_FLAG_TXE ((uint32_t)0x00000080)
#define | UART_FLAG_TC ((uint32_t)0x00000040)
#define | UART_FLAG_RXNE ((uint32_t)0x00000020)
#define | UART_FLAG_IDLE ((uint32_t)0x00000010)
#define | UART_FLAG_ORE ((uint32_t)0x00000008)
#define | UART_FLAG_NE ((uint32_t)0x00000004)
#define | UART_FLAG_FE ((uint32_t)0x00000002)
#define | UART_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE ((uint32_t)0x00004000)

Definition at line 539 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_ABRF ((uint32_t)0x00008000)

Definition at line 538 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_BUSY ((uint32_t)0x00010000)

Definition at line 537 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_CMF ((uint32_t)0x00020000)

Definition at line 536 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_CTS ((uint32_t)0x00000400)

Definition at line 542 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_CTSIF ((uint32_t)0x00000200)

Definition at line 543 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_EOBF ((uint32_t)0x00001000)

Definition at line 540 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_FE ((uint32_t)0x00000002)

Definition at line 551 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_IDLE ((uint32_t)0x00000010)

Definition at line 548 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_LBDF ((uint32_t)0x00000100)

Definition at line 544 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_NE ((uint32_t)0x00000004)

Definition at line 550 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_ORE ((uint32_t)0x00000008)

Definition at line 549 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_PE ((uint32_t)0x00000001)

Definition at line 552 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_RTOF ((uint32_t)0x00000800)

Definition at line 541 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_RXNE ((uint32_t)0x00000020)

Definition at line 547 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_SBKF ((uint32_t)0x00040000)

Definition at line 535 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_TC ((uint32_t)0x00000040)

Definition at line 546 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and UART_Transmit_IT().

#define UART_FLAG_TEACK ((uint32_t)0x00200000)

Definition at line 534 of file stm32f7xx_hal_uart.h.

#define UART_FLAG_TXE ((uint32_t)0x00000080)

Definition at line 545 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE ((uint32_t)0x0028)
#define | UART_IT_TXE ((uint32_t)0x0727)
#define | UART_IT_TC ((uint32_t)0x0626)
#define | UART_IT_RXNE ((uint32_t)0x0525)
#define | UART_IT_IDLE ((uint32_t)0x0424)
#define | UART_IT_LBD ((uint32_t)0x0846)
#define | UART_IT_CTS ((uint32_t)0x096A)
#define | UART_IT_CM ((uint32_t)0x112E)
#define | UART_IT_ERR ((uint32_t)0x0060)
Elements values convention: 000000000XXYYYYYb.
#define | UART_IT_ORE ((uint32_t)0x0300)
Elements values convention: 0000ZZZZ00000000b.
#define | UART_IT_NE ((uint32_t)0x0200)
#define | UART_IT_FE ((uint32_t)0x0100)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define UART_IT_CM ((uint32_t)0x112E)

Definition at line 574 of file stm32f7xx_hal_uart.h.

#define UART_IT_CTS ((uint32_t)0x096A)

Definition at line 573 of file stm32f7xx_hal_uart.h.

#define UART_IT_ERR ((uint32_t)0x0060)

Elements values convention: 000000000XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Definition at line 583 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

#define UART_IT_FE ((uint32_t)0x0100)

Definition at line 590 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_IT_IDLE ((uint32_t)0x0424)

Definition at line 571 of file stm32f7xx_hal_uart.h.

#define UART_IT_LBD ((uint32_t)0x0846)

Definition at line 572 of file stm32f7xx_hal_uart.h.

#define UART_IT_NE ((uint32_t)0x0200)

Definition at line 589 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_IT_ORE ((uint32_t)0x0300)

Elements values convention: 0000ZZZZ00000000b.

  • ZZZZ : Flag position in the ISR register(4bits)

Definition at line 588 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_IT_PE ((uint32_t)0x0028)

Definition at line 567 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

#define UART_IT_RXNE ((uint32_t)0x0525)

Definition at line 570 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

#define UART_IT_TC ((uint32_t)0x0626)

Definition at line 569 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_DMATransmitCplt(), and UART_EndTransmit_IT().

#define UART_IT_TXE ((uint32_t)0x0727)

Definition at line 568 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Transmit_IT(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_EOBF USART_ICR_EOBCF
#define | UART_CLEAR_CMF USART_ICR_CMCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 608 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 605 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_EOBF USART_ICR_EOBCF

End Of Block Clear Flag

Definition at line 607 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 599 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 602 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 604 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 600 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 601 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_DMAResume().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 598 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_RTOF USART_ICR_RTOCF

Receiver Time Out Clear Flag

Definition at line 606 of file stm32f7xx_hal_uart.h.

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 603 of file stm32f7xx_hal_uart.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
Reset UART handle state.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
Clears the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Checks whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Checks whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified UART interrupt source is enabled.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enables the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disables the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 668 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 686 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))

Clears the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__FLAG__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF: Parity Error Clear Flag
  • UART_CLEAR_FEF: Framing Error Clear Flag
  • UART_CLEAR_NEF: Noise detected Clear Flag
  • UART_CLEAR_OREF: OverRun Error Clear Flag
  • UART_CLEAR_IDLEF: IDLE line detected Clear Flag
  • UART_CLEAR_TCF: Transmission Complete Clear Flag
  • UART_CLEAR_LBDF: LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF: CTS Interrupt Clear Flag
  • UART_CLEAR_RTOF: Receiver Time Out Clear Flag
  • UART_CLEAR_EOBF: End Of Block Clear Flag
  • UART_CLEAR_CMF: Character Match Clear Flag
Return values:
None

Definition at line 656 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), and HAL_UART_Transmit_DMA().

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 674 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 680 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 662 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 830 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), and HAL_UART_Init().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Disables the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle.
__INTERRUPT__,: specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_CM: Character match interrupt
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 753 of file stm32f7xx_hal_uart.h.

Referenced by UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 824 of file stm32f7xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_DMAResume(), and HAL_UART_Init().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Enables the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle.
__INTERRUPT__,: specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_WUF: Wakeup from stop mode interrupt
  • UART_IT_CM: Character match interrupt
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 733 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), and UART_DMATransmitCplt().

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
    }  while(0)

Flush the UART Data registers.

Parameters:
__HANDLE__,: specifies the UART Handle.

Definition at line 632 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Checks whether the specified UART flag is set or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_REACK: Receive enable acknowledge flag
  • UART_FLAG_TEACK: Transmit enable acknowledge flag
  • UART_FLAG_WUF: Wake up from stop mode flag
  • UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode)
  • UART_FLAG_SBKF: Send Break flag
  • UART_FLAG_CMF: Character match flag
  • UART_FLAG_BUSY: Busy flag
  • UART_FLAG_ABRF: Auto Baud rate detection flag
  • UART_FLAG_ABRE: Auto Baud rate detection error flag
  • UART_FLAG_EOBF: End of block flag
  • UART_FLAG_RTOF: Receiver timeout flag
  • UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
  • UART_FLAG_LBD: LIN Break detection flag
  • UART_FLAG_TXE: Transmit data register empty flag
  • UART_FLAG_TC: Transmission Complete flag
  • UART_FLAG_RXNE: Receive data register not empty flag
  • UART_FLAG_IDLE: Idle Line detection flag
  • UART_FLAG_ORE: OverRun Error flag
  • UART_FLAG_NE: Noise Error flag
  • UART_FLAG_FE: Framing Error flag
  • UART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 715 of file stm32f7xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Checks whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT__,: specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_CM: Character match interrupt
  • UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_ORE: OverRun Error interrupt
  • UART_IT_NE: Noise Error interrupt
  • UART_IT_FE: Framing Error interrupt
  • UART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 774 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))

Checks whether the specified UART interrupt source is enabled.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT__,: specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_ORE: OverRun Error interrupt
  • UART_IT_NE: Noise Error interrupt
  • UART_IT_FE: Framing Error interrupt
  • UART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 792 of file stm32f7xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0)

Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 864 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0)

Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 845 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0)

Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 902 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0)

Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 883 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disables the UART one bit sample method.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 818 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enables the UART one bit sample method.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 812 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_UART_STATE_RESET)

Reset UART handle state.

Parameters:
__HANDLE__,: UART handle.
Return values:
None

Definition at line 627 of file stm32f7xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST: Send Break Request
  • UART_MUTE_MODE_REQUEST: Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
Return values:
None

Definition at line 806 of file stm32f7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode(), and HAL_UART_IRQHandler().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_)))
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_)))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_)))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
Check UART deassertion time.
#define | IS_UART_STOPBITS(STOPBITS)
#define | IS_UART_PARITY(PARITY)
#define | IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
#define | IS_UART_STATE(STATE)
#define | IS_UART_OVERSAMPLING(SAMPLING)
#define | IS_UART_ONE_BIT_SAMPLE(ONEBIT)
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE)
#define | IS_UART_RECEIVER_TIMEOUT(TIMEOUT)
#define | IS_UART_LIN(LIN)
#define | IS_UART_WAKEUPMETHOD(WAKEUP)
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_UART_DMA_TX(DMATX)
#define | IS_UART_DMA_RX(DMARX)
#define | IS_UART_HALF_DUPLEX(HDSEL)
#define | IS_UART_REQUEST_PARAMETER(PARAM)
#define | IS_UART_ADVFEATURE_INIT(INIT)
#define | IS_UART_ADVFEATURE_TXINV(TXINV)
#define | IS_UART_ADVFEATURE_RXINV(RXINV)
#define | IS_UART_ADVFEATURE_DATAINV(DATAINV)
#define | IS_UART_ADVFEATURE_SWAP(SWAP)
#define | IS_UART_OVERRUN(OVERRUN)
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE)
#define | IS_UART_ADVFEATURE_DMAONRXERROR(DMA)
#define | IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST)
#define | IS_UART_MUTE_MODE(MUTE)
#define | IS_UART_DE_POLARITY(POLARITY)

Define Documentation

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( AUTOBAUDRATE )
Value:
(((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                        ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Definition at line 1038 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( MODE )
Value:
(((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Definition at line 981 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( DATAINV )
Value:
(((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                             ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))

Definition at line 1029 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( DMA )
Value:
(((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Definition at line 1041 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( INIT )
Value:
((INIT) <= (UART_ADVFEATURE_NO_INIT | \
                                                            UART_ADVFEATURE_TXINVERT_INIT | \
                                                            UART_ADVFEATURE_RXINVERT_INIT | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT | \
                                                            UART_ADVFEATURE_SWAP_INIT | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT   | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Definition at line 1013 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( MSBFIRST )
Value:
(((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                               ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Definition at line 1044 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( RXINV )
Value:
(((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                         ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))

Definition at line 1026 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_SWAP ( SWAP )
Value:
(((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                       ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))

Definition at line 1032 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( TXINV )
Value:
(((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                         ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))

Definition at line 1023 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( TIME ) ((TIME) <= 0x1F)

Check UART assertion time.

Parameters:
TIME,: 5-bit value assertion time
Return values:
Test result (TRUE or FALSE).

Definition at line 949 of file stm32f7xx_hal_uart.h.

#define IS_UART_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 9000001)

Check UART Baud rate.

Parameters:
BAUDRATE,: Baudrate specified by the user The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
Test result (TRUE or FALSE).

Definition at line 943 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( POLARITY )
Value:
(((POLARITY) == UART_DE_POLARITY_HIGH) || \
                                          ((POLARITY) == UART_DE_POLARITY_LOW))

Definition at line 1050 of file stm32f7xx_hal_uart.h.

#define IS_UART_DEASSERTIONTIME ( TIME ) ((TIME) <= 0x1F)

Check UART deassertion time.

Parameters:
TIME,: 5-bit value deassertion time
Return values:
Test result (TRUE or FALSE).

Definition at line 955 of file stm32f7xx_hal_uart.h.

#define IS_UART_DMA_RX ( DMARX )
Value:
(((DMARX) == UART_DMA_RX_DISABLE) || \
                                       ((DMARX) == UART_DMA_RX_ENABLE))

Definition at line 1001 of file stm32f7xx_hal_uart.h.

#define IS_UART_DMA_TX ( DMATX )
Value:
(((DMATX) == UART_DMA_TX_DISABLE) || \
                                       ((DMATX) == UART_DMA_TX_ENABLE))

Definition at line 998 of file stm32f7xx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( HDSEL )
Value:
(((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((HDSEL) == UART_HALF_DUPLEX_ENABLE))

Definition at line 1004 of file stm32f7xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == UART_HWCONTROL_NONE) || \
                               ((CONTROL) == UART_HWCONTROL_RTS) || \
                               ((CONTROL) == UART_HWCONTROL_CTS) || \
                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))

Definition at line 964 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( LIN )
Value:
(((LIN) == UART_LIN_DISABLE) || \
                                     ((LIN) == UART_LIN_ENABLE))

Definition at line 989 of file stm32f7xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( LENGTH )
Value:
(((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))

Definition at line 995 of file stm32f7xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( MODE ) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))

Definition at line 970 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( MUTE )
Value:
(((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Definition at line 1047 of file stm32f7xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( ONEBIT )
Value:
(((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                        ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))

Definition at line 978 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( OVERRUN )
Value:
(((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))

Definition at line 1035 of file stm32f7xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( SAMPLING )
Value:
(((SAMPLING) == UART_OVERSAMPLING_16) || \
                                        ((SAMPLING) == UART_OVERSAMPLING_8))

Definition at line 975 of file stm32f7xx_hal_uart.h.

#define IS_UART_PARITY ( PARITY )
Value:
(((PARITY) == UART_PARITY_NONE) || \
                                ((PARITY) == UART_PARITY_EVEN) || \
                                ((PARITY) == UART_PARITY_ODD))

Definition at line 960 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( TIMEOUT )
Value:
(((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                           ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))

Definition at line 986 of file stm32f7xx_hal_uart.h.

#define IS_UART_REQUEST_PARAMETER ( PARAM )
Value:
(((PARAM) == UART_AUTOBAUD_REQUEST) || \
                                          ((PARAM) == UART_SENDBREAK_REQUEST) || \
                                          ((PARAM) == UART_MUTE_MODE_REQUEST) || \
                                          ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
                                          ((PARAM) == UART_TXDATA_FLUSH_REQUEST))

Definition at line 1007 of file stm32f7xx_hal_uart.h.

#define IS_UART_STATE ( STATE )
Value:
(((STATE) == UART_STATE_DISABLE) || \
                              ((STATE) == UART_STATE_ENABLE))

Definition at line 972 of file stm32f7xx_hal_uart.h.

#define IS_UART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == UART_STOPBITS_1) || \
                                    ((STOPBITS) == UART_STOPBITS_2))

Definition at line 957 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUPMETHOD ( WAKEUP )
Value:
(((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))

Definition at line 992 of file stm32f7xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*256)/((_BAUD_)))

BRR division operation to set BRR register with LPUART.

Parameters:
_PCLK_,: LPUART clock
_BAUD_,: Baud rate set by the user
Return values:
Division result

Definition at line 921 of file stm32f7xx_hal_uart.h.

#define UART_DIV_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_))/((_BAUD_)))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
_PCLK_,: UART clock
_BAUD_,: Baud rate set by the user
Return values:
Division result

Definition at line 935 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*2)/((_BAUD_)))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
_PCLK_,: UART clock
_BAUD_,: Baud rate set by the user
Return values:
Division result

Definition at line 928 of file stm32f7xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1809 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart,: uart handle
Return values:
HAL status

Definition at line 1884 of file stm32f7xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, UART_HandleTypeDef::State, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart,: uart handle
Return values:
None

Definition at line 1698 of file stm32f7xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_PARITY, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LSE_VALUE, UART_InitTypeDef::Mode, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, UART_InitTypeDef::StopBits, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_PCLK2, UART_CLOCKSOURCE_SYSCLK, UART_CLOCKSOURCE_UNDEFINED, UART_CR1_FIELDS, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GETCLOCKSOURCE, UART_OVERSAMPLING_8, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  |

This function handles UART Communication Timeout.

Parameters:
huart,: UART handle
Flag,: specifies the UART flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1208 of file stm32f7xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, __HAL_UART_GET_FLAG, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::State, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, and UART_IT_TXE.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_CheckIdleState(), and UART_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UART

Modules | Defines
UART
STM32F7xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Exported Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros
UART Private Functions

Defines

#define | HAL_UART_TXDMA_TIMEOUTVALUE 22000
#define | UART_CR1_FIELDS

Detailed Description

HAL UART module driver.

Define Documentation

#define HAL_UART_TXDMA_TIMEOUTVALUE 22000

Definition at line 171 of file stm32f7xx_hal_uart.c.

#define UART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))

Definition at line 172 of file stm32f7xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Initialization and de-initialization functions

Functions
USART Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_CheckIdleState (USART_HandleTypeDef *husart)

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M1 and M0 bits (7-bit,
             8-bit or 9-bit), the possible USART frame formats are as listed in the
             following table:

   (+++) +---------------------------------------------------------------+
   (+++) | M1M0 bits |  PCE bit  |            USART frame                |
   (+++) |-----------------------|---------------------------------------|
   (+++) |     10    |     0     |    | SB | 7-bit data | STB |          |
   (+++) |-----------|-----------|---------------------------------------|
   (+++) |     10    |     1     |    | SB | 6-bit data | PB | STB |     |
   (+++) +---------------------------------------------------------------+

        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_USART_CheckIdleState ( USART_HandleTypeDef * husart )
HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitializes the USART peripheral.

Parameters:
husart,: USART handle
Return values:
HAL status

Definition at line 236 of file stm32f7xx_hal_usart.c.

References assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.

Parameters:
husart,: USART handle
Return values:
HAL status

Definition at line 188 of file stm32f7xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Lock, USART_HandleTypeDef::State, USART_CheckIdleState(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

USART MSP DeInit.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 285 of file stm32f7xx_hal_usart.c.

Referenced by HAL_USART_DeInit().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

USART MSP Init.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 270 of file stm32f7xx_hal_usart.c.

Referenced by HAL_USART_Init().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in blocking mode To receive synchronous data, dummy data are simultaneously transmitted.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    (#) There are two mode of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit()in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT()in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT()in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_USART_Transmit_DMA()in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pauses the DMA Transfer.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 963 of file stm32f7xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resumes the DMA Transfer.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 997 of file stm32f7xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_CLEAR_OREF.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stops the DMA Transfer.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1038 of file stm32f7xx_hal_usart.c.

References HAL_DMA_Abort(), HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callbacks.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1231 of file stm32f7xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), and USART_DMAError().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

This function handles USART interrupt request.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1072 of file stm32f7xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, __HAL_USART_GET_IT, __HAL_USART_GET_IT_SOURCE, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::State, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_EndTransmit_IT(), USART_IT_ERR, USART_IT_FE, USART_IT_NE, USART_IT_ORE, USART_IT_PE, USART_IT_RXNE, USART_IT_TC, USART_IT_TXE, USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted
Parameters:
husart,: USART handle
pRxData,: pointer to data buffer
Size,: amount of data to be received
Timeout : Timeout duration
Return values:
HAL status

Definition at line 431 of file stm32f7xx_hal_usart.c.

References __HAL_USART_MASK_COMPUTATION, DUMMY_DATA, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_FLAG_RXNE, USART_FLAG_TC, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
husart,: USART handle
pRxData,: pointer to data buffer
Size,: amount of data to be received
Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position)
Return values:
HAL status
Note:
The USART DMA transmit stream must be configured in order to generate the clock for the slave.

Definition at line 820 of file stm32f7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in blocking mode To receive synchronous data, dummy data are simultaneously transmitted.

Parameters:
husart,: USART handle
pRxData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 643 of file stm32f7xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, __HAL_USART_MASK_COMPUTATION, DUMMY_DATA, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callbacks.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1186 of file stm32f7xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_Receive_IT().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callbacks.

Parameters:
husart,: usart handle
Return values:
None

Definition at line 1201 of file stm32f7xx_hal_usart.c.

Referenced by USART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex Send an amount of data in blocking mode.

Parameters:
husart,: USART handle
pTxData,: pointer to data buffer
Size,: amount of data to be sent
Timeout : Timeout duration
Return values:
HAL status

Definition at line 364 of file stm32f7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_TC, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
husart,: USART handle
pTxData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 758 of file stm32f7xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_FLAG_TC, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
husart,: USART handle
pTxData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 596 of file stm32f7xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_IT_TXE.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Parameters:
husart,: USART handle
pTxData,: pointer to TX data buffer
pRxData,: pointer to RX data buffer
Size,: amount of data to be sent (same amount to be received)
Timeout : Timeout duration
Return values:
HAL status

Definition at line 510 of file stm32f7xx_hal_usart.c.

References __HAL_USART_MASK_COMPUTATION, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TC, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non blocking mode.

Parameters:
husart,: USART handle
pTxData,: pointer to TX data buffer
pRxData,: pointer to RX data buffer
Size,: amount of data to be received/sent
Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 889 of file stm32f7xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_FLAG_TC, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Parameters:
husart,: USART handle
pTxData,: pointer to TX data buffer
pRxData,: pointer to RX data buffer
Size,: amount of data to be sent (same amount to be received)
Return values:
HAL status

Definition at line 702 of file stm32f7xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, __HAL_USART_MASK_COMPUTATION, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, and USART_IT_TXE.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callbacks.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1156 of file stm32f7xx_hal_usart.c.

Referenced by USART_DMATransmitCplt(), and USART_EndTransmit_IT().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callbacks.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1171 of file stm32f7xx_hal_usart.c.

Referenced by USART_DMATxHalfCplt().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1216 of file stm32f7xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_TransmitReceive_IT().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
USART Exported Functions

USART State and Errors functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
return the USART state
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of
    USART communication
    process, return Peripheral Errors occurred during communication process
     (+) HAL_USART_GetState() API can be helpful to check in run-time the state
         of the USART peripheral.
     (+) HAL_USART_GetError() check in run-time errors that could be occurred during
         communication.

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART Error Code

Definition at line 1280 of file stm32f7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

return the USART state

Parameters:
husart,: USART handle
Return values:
HAL state

Definition at line 1269 of file stm32f7xx_hal_usart.c.

References USART_HandleTypeDef::State.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Exported Functions

Modules | Functions
USART Exported Functions
USART

Modules

USART Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Errors functions

USART State and Errors functions.

Functions

static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles USART Communication Timeout.
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart,: USART handle
Return values:
HAL status

Definition at line 1772 of file stm32f7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, HAL_USART_STATE_TIMEOUT, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1673 of file stm32f7xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1614 of file stm32f7xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1661 of file stm32f7xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback().

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1567 of file stm32f7xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1602 of file stm32f7xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback().

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static HAL_StatusTypeDef USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1345 of file stm32f7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::State, USART_IT_ERR, and USART_IT_TC.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_Receive_IT ( USART_HandleTypeDef * husart ) [static]

Simplex Receive an amount of data in non-blocking mode.

Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT()

Parameters:
husart,: USART handle
Return values:
HAL status

Definition at line 1367 of file stm32f7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, DUMMY_DATA, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart,: USART handle
Return values:
None

Definition at line 1690 of file stm32f7xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_OVERSAMPLING, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, USART_InitTypeDef::OverSampling, USART_InitTypeDef::Parity, USART_InitTypeDef::StopBits, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PCLK1, USART_CLOCKSOURCE_PCLK2, USART_CLOCKSOURCE_SYSCLK, USART_CLOCKSOURCE_UNDEFINED, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static HAL_StatusTypeDef USART_Transmit_IT ( USART_HandleTypeDef * husart ) [static]

Simplex Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
Parameters:
husart,: USART handle
Return values:
HAL status
Note:
The USART errors are not managed to avoid the overrun error.

Definition at line 1298 of file stm32f7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_IT_TC, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_TransmitReceive_IT ( USART_HandleTypeDef * husart ) [static]

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Function called under interruption only, once interruptions have been enabled by HAL_USART_TransmitReceive_IT()

Parameters:
husart,: USART handle
Return values:
HAL status

Definition at line 1420 of file stm32f7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_FLAG_RXNE, USART_FLAG_TXE, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles USART Communication Timeout.

Parameters:
husart,: USART handle
Flag,: specifies the USART flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1503 of file stm32f7xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, and USART_IT_TXE.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Exported Types

Data Structures | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00, HAL_USART_STATE_READY = 0x01, HAL_USART_STATE_BUSY = 0x02, HAL_USART_STATE_BUSY_TX = 0x12,
HAL_USART_STATE_BUSY_RX = 0x22, HAL_USART_STATE_BUSY_TX_RX = 0x32, HAL_USART_STATE_TIMEOUT = 0x03, HAL_USART_STATE_ERROR = 0x04
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00, USART_CLOCKSOURCE_PCLK2 = 0x01, USART_CLOCKSOURCE_HSI = 0x02, USART_CLOCKSOURCE_SYSCLK = 0x04,
USART_CLOCKSOURCE_LSE = 0x08, USART_CLOCKSOURCE_UNDEFINED = 0x10
}
USART clock sources definitions. More...

Enumeration Type Documentation

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 104 of file stm32f7xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_PCLK1

PCLK1 clock source

USART_CLOCKSOURCE_PCLK2

PCLK2 clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 120 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32f7xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | OverSampling
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit

Detailed Description

USART Init Structure definition.

Definition at line 65 of file stm32f7xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))

Definition at line 67 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit

Definition at line 96 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase

Definition at line 93 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity

Definition at line 90 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode

Definition at line 84 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). This parameter can be a value of USART Over Sampling

Definition at line 87 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 77 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits

Definition at line 74 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length

Definition at line 71 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_usart.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32f7xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
HAL_USART_StateTypeDef State
__IO uint32_t | ErrorCode

Detailed Description

USART handle Structure definition.

Definition at line 134 of file stm32f7xx_hal_usart.h.

Field Documentation

__IO uint32_t USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 162 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), and USART_DMAError().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 156 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 154 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

USART_InitTypeDef USART_HandleTypeDef::Init

USART communication parameters

Definition at line 138 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

USART_TypeDef* USART_HandleTypeDef::Instance

USART registers base address

Definition at line 136 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

HAL_LockTypeDef USART_HandleTypeDef::Lock

Locking object

Definition at line 158 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 152 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 146 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 140 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 150 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMAReceiveCplt(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 148 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

HAL_USART_StateTypeDef USART_HandleTypeDef::State

USART communication state

Definition at line 160 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

uint16_t USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 144 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMATransmitCplt(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 142 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_usart.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Error Code

Defines
USART Error Code
USART Exported Constants

USART Error Code. More...

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010)

Detailed Description

USART Error Code.

Define Documentation

#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 183 of file stm32f7xx_hal_usart.h.

Referenced by USART_DMAError().

#define HAL_USART_ERROR_FE ((uint32_t)0x00000004)

Frame error

Definition at line 181 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NE ((uint32_t)0x00000002)

Noise error

Definition at line 180 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 178 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_CheckIdleState().

#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008)

Overrun error

Definition at line 182 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE ((uint32_t)0x00000001)

Parity error

Definition at line 179 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_1 ((uint32_t)0x0000)
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define USART_STOPBITS_1 ((uint32_t)0x0000)

Definition at line 191 of file stm32f7xx_hal_usart.h.

#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Definition at line 193 of file stm32f7xx_hal_usart.h.

#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Definition at line 192 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE ((uint32_t)0x0000)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 202 of file stm32f7xx_hal_usart.h.

#define USART_PARITY_NONE ((uint32_t)0x0000)

Definition at line 201 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 203 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define USART_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 211 of file stm32f7xx_hal_usart.h.

#define USART_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 212 of file stm32f7xx_hal_usart.h.

#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 213 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Over Sampling

Defines
USART Over Sampling
USART Exported Constants

Defines

#define | USART_OVERSAMPLING_16 ((uint32_t)0x0000)
#define | USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define USART_OVERSAMPLING_16 ((uint32_t)0x0000)

Definition at line 221 of file stm32f7xx_hal_usart.h.

#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Definition at line 222 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE ((uint32_t)0x0000)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Define Documentation

#define USART_CLOCK_DISABLE ((uint32_t)0x0000)

Definition at line 229 of file stm32f7xx_hal_usart.h.

#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Definition at line 230 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW ((uint32_t)0x0000)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Definition at line 239 of file stm32f7xx_hal_usart.h.

#define USART_POLARITY_LOW ((uint32_t)0x0000)

Definition at line 238 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE ((uint32_t)0x0000)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define USART_PHASE_1EDGE ((uint32_t)0x0000)

Definition at line 247 of file stm32f7xx_hal_usart.h.

#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Definition at line 248 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE ((uint32_t)0x0000)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define USART_LASTBIT_DISABLE ((uint32_t)0x0000)

Definition at line 256 of file stm32f7xx_hal_usart.h.

#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Definition at line 257 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 265 of file stm32f7xx_hal_usart.h.

#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 266 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_REACK ((uint32_t)0x00400000)
#define | USART_FLAG_TEACK ((uint32_t)0x00200000)
#define | USART_FLAG_BUSY ((uint32_t)0x00010000)
#define | USART_FLAG_CTS ((uint32_t)0x00000400)
#define | USART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | USART_FLAG_LBDF ((uint32_t)0x00000100)
#define | USART_FLAG_TXE ((uint32_t)0x00000080)
#define | USART_FLAG_TC ((uint32_t)0x00000040)
#define | USART_FLAG_RXNE ((uint32_t)0x00000020)
#define | USART_FLAG_IDLE ((uint32_t)0x00000010)
#define | USART_FLAG_ORE ((uint32_t)0x00000008)
#define | USART_FLAG_NE ((uint32_t)0x00000004)
#define | USART_FLAG_FE ((uint32_t)0x00000002)
#define | USART_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY ((uint32_t)0x00010000)

Definition at line 278 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_CTS ((uint32_t)0x00000400)

Definition at line 279 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_CTSIF ((uint32_t)0x00000200)

Definition at line 280 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_FE ((uint32_t)0x00000002)

Definition at line 288 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_IDLE ((uint32_t)0x00000010)

Definition at line 285 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_LBDF ((uint32_t)0x00000100)

Definition at line 281 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_NE ((uint32_t)0x00000004)

Definition at line 287 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_ORE ((uint32_t)0x00000008)

Definition at line 286 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_PE ((uint32_t)0x00000001)

Definition at line 289 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_REACK ((uint32_t)0x00400000)

Definition at line 276 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_RXNE ((uint32_t)0x00000020)

Definition at line 284 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TC ((uint32_t)0x00000040)

Definition at line 283 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_DMA().

#define USART_FLAG_TEACK ((uint32_t)0x00200000)

Definition at line 277 of file stm32f7xx_hal_usart.h.

#define USART_FLAG_TXE ((uint32_t)0x00000080)

Definition at line 282 of file stm32f7xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_TXE ((uint16_t)0x0727)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_ORE ((uint16_t)0x0300)
#define | USART_IT_NE ((uint16_t)0x0200)
#define | USART_IT_FE ((uint16_t)0x0100)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR ((uint16_t)0x0060)

Definition at line 310 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_FE ((uint16_t)0x0100)

Definition at line 314 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_IT_IDLE ((uint16_t)0x0424)

Definition at line 309 of file stm32f7xx_hal_usart.h.

#define USART_IT_NE ((uint16_t)0x0200)

Definition at line 313 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_IT_ORE ((uint16_t)0x0300)

Definition at line 312 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_IT_PE ((uint16_t)0x0028)

Definition at line 305 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_RXNE ((uint16_t)0x0525)

Definition at line 308 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_TC ((uint16_t)0x0626)

Definition at line 307 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_Transmit_IT().

#define USART_IT_TXE ((uint16_t)0x0727)

Definition at line 306 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_CTSF USART_ICR_CTSCF

Define Documentation

#define USART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 328 of file stm32f7xx_hal_usart.h.

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 323 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 326 of file stm32f7xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 324 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 325 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), and HAL_USART_IRQHandler().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 322 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 327 of file stm32f7xx_hal_usart.h.

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STM32F745xx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Checks whether the specified USART flag is set or not.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Checks whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified USART interrupt source is enabled.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clears the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clears the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • USART_CLEAR_PEF: Parity Error Clear Flag
  • USART_CLEAR_FEF: Framing Error Clear Flag
  • USART_CLEAR_NEF: Noise detected Clear Flag
  • USART_CLEAR_OREF: OverRun Error Clear Flag
  • USART_CLEAR_IDLEF: IDLE line detected Clear Flag
  • USART_CLEAR_TCF: Transmission Complete Clear Flag
  • USART_CLEAR_CTSF: CTS Interrupt Clear Flag
Return values:
None

Definition at line 451 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_IRQHandler(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 474 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disables the specified USART interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle.
__INTERRUPT__,: specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 397 of file stm32f7xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 468 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enables the specified USART interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle
__INTERRUPT__,: specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 381 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_DMATransmitCplt(), and USART_Transmit_IT().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Checks whether the specified USART flag is set or not.

Parameters:
__HANDLE__,: specifies the USART Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_REACK: Receive enable acknowledge flag
  • USART_FLAG_TEACK: Transmit enable acknowledge flag
  • USART_FLAG_BUSY: Busy flag
  • USART_FLAG_CTS: CTS Change flag
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: OverRun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 366 of file stm32f7xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Checks whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the USART Handle
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE: OverRun Error interrupt
  • USART_IT_NE: Noise Error interrupt
  • USART_IT_FE: Framing Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 416 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))

Checks whether the specified USART interrupt source is enabled.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE: OverRun Error interrupt
  • USART_IT_NE: Noise Error interrupt
  • USART_IT_FE: Framing Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 432 of file stm32f7xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_USART_STATE_RESET)

Reset USART handle state.

Parameters:
__HANDLE__,: USART handle.
Return values:
None

Definition at line 346 of file stm32f7xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
Return values:
None

Definition at line 462 of file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | DUMMY_DATA ((uint16_t) 0xFFFF)
#define | TEACK_REACK_TIMEOUT ((uint32_t) 1000)
#define | USART_TXDMA_TIMEOUTVALUE 22000
#define | USART_TIMEOUT_VALUE 22000
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_IT_MASK ((uint16_t)0x001F)
USART interruptions flag mask.

Define Documentation

#define DUMMY_DATA ((uint16_t) 0xFFFF)

Definition at line 101 of file stm32f7xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define TEACK_REACK_TIMEOUT ((uint32_t) 1000)

Definition at line 102 of file stm32f7xx_hal_usart.c.

Referenced by USART_CheckIdleState().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                     USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))

Definition at line 105 of file stm32f7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
                            USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))

Definition at line 107 of file stm32f7xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_IT_MASK ((uint16_t)0x001F)

USART interruptions flag mask.

Definition at line 551 of file stm32f7xx_hal_usart.h.

#define USART_TIMEOUT_VALUE 22000

Definition at line 104 of file stm32f7xx_hal_usart.c.

#define USART_TXDMA_TIMEOUTVALUE 22000

Definition at line 103 of file stm32f7xx_hal_usart.c.

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STM32F745xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the USART clock source.
#define | IS_USART_STOPBITS(__STOPBITS__)
#define | IS_USART_PARITY(__PARITY__)
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
#define | IS_USART_CLOCK(__CLOCK__)
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
#define | IS_USART_LASTBIT(__LASTBIT__)
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 9000001)

Definition at line 667 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__)== USART_CLOCK_DISABLE) || \
                                       ((__CLOCK__)== USART_CLOCK_ENABLE))

Definition at line 659 of file stm32f7xx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Definition at line 663 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))

Definition at line 656 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == USART_OVERSAMPLING_16) || \
                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

Definition at line 657 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Definition at line 653 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Definition at line 662 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Definition at line 661 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Definition at line 665 of file stm32f7xx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_1) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Definition at line 650 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Reports the USART clock source.

Parameters:
__HANDLE__,: specifies the USART Handle
__CLOCKSOURCE__ : output variable
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 565 of file stm32f7xx_hal_usart.h.

Referenced by USART_SetConfig().

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STM32F745xx HAL User Manual: USART Private Functions

USART Private Functions
USART
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_WWDG_DeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG peripheral.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG MSP.
__weak void | HAL_WWDG_MspDeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG MSP.
void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize the WWDG according to the specified parameters
        in the WWDG_InitTypeDef and create the associated handle
    (+) DeInitialize the WWDG peripheral
    (+) Initialize the WWDG MSP
    (+) DeInitialize the WWDG MSP

Function Documentation

HAL_StatusTypeDef HAL_WWDG_DeInit ( WWDG_HandleTypeDef * hwwdg )

DeInitializes the WWDG peripheral.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 193 of file stm32f7xx_hal_wwdg.c.

References assert_param, HAL_WWDG_MspDeInit(), HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_RESET, WWDG_HandleTypeDef::Instance, and WWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 150 of file stm32f7xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, HAL_WWDG_MspInit(), HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_READY, HAL_WWDG_STATE_RESET, WWDG_HandleTypeDef::Init, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, WWDG_HandleTypeDef::Lock, WWDG_InitTypeDef::Prescaler, WWDG_HandleTypeDef::State, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspDeInit ( WWDG_HandleTypeDef * hwwdg )

DeInitializes the WWDG MSP.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 251 of file stm32f7xx_hal_wwdg.c.

Referenced by HAL_WWDG_DeInit().

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initializes the WWDG MSP.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 235 of file stm32f7xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init().

void HAL_WWDG_WakeupCallback ( WWDG_HandleTypeDef * hwwdg )

Early Wakeup WWDG callback.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 406 of file stm32f7xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

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STM32F745xx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Start (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG.
HAL_StatusTypeDef | HAL_WWDG_Start_IT (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG with interrupt enabled.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
Refreshes the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handles WWDG interrupt request.
__weak void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.

Detailed Description

IO operation functions.

  ==============================================================================
                       ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the WWDG.
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request.

Function Documentation

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handles WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 377 of file stm32f7xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, HAL_WWDG_STATE_READY, HAL_WWDG_WakeupCallback(), WWDG_HandleTypeDef::State, WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | uint32_t | Counter
 | ) |  |

Refreshes the WWDG.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Counter,: value of counter to put in WWDG counter
Return values:
HAL status

Definition at line 340 of file stm32f7xx_hal_wwdg.c.

References assert_param, HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_READY, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, and WWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_WWDG_Start ( WWDG_HandleTypeDef * hwwdg )

Starts the WWDG.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 288 of file stm32f7xx_hal_wwdg.c.

References __HAL_WWDG_ENABLE, HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_READY, and WWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_WWDG_Start_IT ( WWDG_HandleTypeDef * hwwdg )

Starts the WWDG with interrupt enabled.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 315 of file stm32f7xx_hal_wwdg.c.

References __HAL_WWDG_ENABLE, __HAL_WWDG_ENABLE_IT, HAL_WWDG_STATE_BUSY, WWDG_HandleTypeDef::State, and WWDG_IT_EWI.

__weak void HAL_WWDG_WakeupCallback ( WWDG_HandleTypeDef * hwwdg )

Early Wakeup WWDG callback.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 406 of file stm32f7xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

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STM32F745xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
WWDG Exported Functions

Peripheral State functions. More...

Functions

HAL_WWDG_StateTypeDef HAL_WWDG_GetState (WWDG_HandleTypeDef *hwwdg)
Returns the WWDG state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_WWDG_StateTypeDef HAL_WWDG_GetState ( WWDG_HandleTypeDef * hwwdg )

Returns the WWDG state.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL state

Definition at line 441 of file stm32f7xx_hal_wwdg.c.

References WWDG_HandleTypeDef::State.

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STM32F745xx HAL User Manual: WWDG Exported Types

Data Structures | Enumerations
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Enumerations

enum HAL_WWDG_StateTypeDef {
HAL_WWDG_STATE_RESET = 0x00, HAL_WWDG_STATE_READY = 0x01, HAL_WWDG_STATE_BUSY = 0x02, HAL_WWDG_STATE_TIMEOUT = 0x03,
HAL_WWDG_STATE_ERROR = 0x04
}
WWDG HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_WWDG_StateTypeDef

WWDG HAL State Structure definition.

Enumerator:
HAL_WWDG_STATE_RESET

WWDG not yet initialized or disabled

HAL_WWDG_STATE_READY

WWDG initialized and ready for use

HAL_WWDG_STATE_BUSY

WWDG internal process is ongoing

HAL_WWDG_STATE_TIMEOUT

WWDG timeout state

HAL_WWDG_STATE_ERROR

WWDG error state

Definition at line 65 of file stm32f7xx_hal_wwdg.h.

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STM32F745xx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32f7xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter

Detailed Description

WWDG Init structure definition.

Definition at line 77 of file stm32f7xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 85 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 79 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number lower than Max_Data = 0x80

Definition at line 82 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_wwdg.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32f7xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * | Instance
WWDG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_WWDG_StateTypeDef | State

Detailed Description

WWDG handle Structure definition.

Definition at line 93 of file stm32f7xx_hal_wwdg.h.

Field Documentation

WWDG_InitTypeDef WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 97 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

WWDG_TypeDef* WWDG_HandleTypeDef::Instance

Register base address

Definition at line 95 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_DeInit(), HAL_WWDG_Init(), and HAL_WWDG_Refresh().

HAL_LockTypeDef WWDG_HandleTypeDef::Lock

WWDG locking object

Definition at line 99 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

__IO HAL_WWDG_StateTypeDef WWDG_HandleTypeDef::State

WWDG communication state

Definition at line 101 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_DeInit(), HAL_WWDG_GetState(), HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), HAL_WWDG_Refresh(), HAL_WWDG_Start(), and HAL_WWDG_Start_IT().

The documentation for this struct was generated from the following file:
  • stm32f7xx_hal_wwdg.h
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 116 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler(), and HAL_WWDG_Start_IT().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 125 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 ((uint32_t)0x00000000)
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 ((uint32_t)0x00000000)

WWDG counter clock = (PCLK1/4096)/1

Definition at line 133 of file stm32f7xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 134 of file stm32f7xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 135 of file stm32f7xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/8

Definition at line 136 of file stm32f7xx_hal_wwdg.h.

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STM32F745xx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
Reset WWDG handle state.
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enables the WWDG peripheral.
#define | __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
Disables the WWDG peripheral.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Gets the selected WWDG's it status.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
Disables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected WWDG's flag status.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clears the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified WWDG interrupt source is enabled or disabled.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__FLAG__))

Clears the WWDG's pending flags.

Parameters:
__HANDLE__,: WWDG handle
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 232 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 189 of file stm32f7xx_hal_wwdg.h.

#define __HAL_WWDG_DISABLE ( __HANDLE__ ) /* dummy macro */

Disables the WWDG peripheral.

Parameters:
__HANDLE__,: WWDG handle
Note:
WARNING: This is a dummy macro for HAL code alignment. Once enable, WWDG Peripheral cannot be disabled except by a system reset.
Return values:
None

Definition at line 170 of file stm32f7xx_hal_wwdg.h.

#define __HAL_WWDG_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | /* dummy macro */

Disables the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt to disable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
WARNING: This is a dummy macro for HAL code alignment. Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 212 of file stm32f7xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enables the WWDG peripheral.

Parameters:
__HANDLE__,: WWDG handle
Return values:
None

Definition at line 161 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Start(), and HAL_WWDG_Start_IT().

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enables the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 200 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Start_IT().

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Gets the selected WWDG's flag status.

Parameters:
__HANDLE__,: WWDG handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 222 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Gets the selected WWDG's it status.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 180 of file stm32f7xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified WWDG interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: WWDG Handle.
__INTERRUPT__,: specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 241 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)

Reset WWDG handle state.

Parameters:
__HANDLE__,: WWDG handle
Return values:
None

Definition at line 154 of file stm32f7xx_hal_wwdg.h.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Private Constants

WWDG Private Constants
WWDG
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))

Definition at line 310 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1) || \
                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
                                          ((__PRESCALER__) == WWDG_PRESCALER_8))

Definition at line 305 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= 0x7F)

Definition at line 309 of file stm32f7xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

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STM32F745xx HAL User Manual: WWDG Private Functions

WWDG Private Functions
WWDG
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDAEx Word Length

Defines
IRDAEx Word Length
IRDAEx Extended Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Define Documentation

#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)

Definition at line 66 of file stm32f7xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)

Definition at line 67 of file stm32f7xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Definition at line 68 of file stm32f7xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Reports the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(LENGTH)

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Reports the IRDA clock source.

Parameters:
__HANDLE__,: specifies the IRDA Handle
__CLOCKSOURCE__ : output variable
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 90 of file stm32f7xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Reports the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__,: specifies the IRDA Handle
Return values:
mask to apply to USART RDR register value.

Definition at line 179 of file stm32f7xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == IRDA_WORDLENGTH_7B) || \
                                     ((LENGTH) == IRDA_WORDLENGTH_8B) || \
                                     ((LENGTH) == IRDA_WORDLENGTH_9B))

Definition at line 216 of file stm32f7xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UARTEx Word Length

Defines
UARTEx Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define | UART_WORDLENGTH_8B ((uint32_t)0x0000)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
#define | IS_UART_WORD_LENGTH(__LENGTH__)
#define | IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))

Define Documentation

#define IS_LIN_WORD_LENGTH ( LENGTH ) (((LENGTH) == UART_WORDLENGTH_8B))

Definition at line 72 of file stm32f7xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Definition at line 69 of file stm32f7xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)

Definition at line 66 of file stm32f7xx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B ((uint32_t)0x0000)

Definition at line 67 of file stm32f7xx_hal_uart_ex.h.

#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Definition at line 68 of file stm32f7xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UARTEx WakeUp Address Length

Defines
UARTEx WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Definition at line 83 of file stm32f7xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)

Definition at line 81 of file stm32f7xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

Definition at line 82 of file stm32f7xx_hal_uart_ex.h.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UARTEx Exported Macros

Defines
UARTEx Exported Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Reports the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Define Documentation

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Reports the UART clock source.

Parameters:
__HANDLE__,: specifies the UART Handle
__CLOCKSOURCE__,: output variable
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 105 of file stm32f7xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Reports the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.

Parameters:
__HANDLE__,: specifies the UART Handle
Return values:
mask to apply to UART RDR register value.

Definition at line 278 of file stm32f7xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), and HAL_UART_Receive_IT().

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Define Documentation

#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)

Definition at line 66 of file stm32f7xx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)

Definition at line 67 of file stm32f7xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)

Definition at line 68 of file stm32f7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | __HAL_USART_MASK_COMPUTATION(__HANDLE__)
Computes the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)

Define Documentation

#define __HAL_USART_MASK_COMPUTATION ( __HANDLE__ )

Computes the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.

Parameters:
__HANDLE__,: specifies the USART Handle
Return values:
none

Definition at line 93 of file stm32f7xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Definition at line 130 of file stm32f7xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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  • r
  • s
  • t
  • u
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  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • ABOM : CAN_InitTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef
  • AddressAlignedBeats : ETH_DMAInitTypeDef
  • AddressingMode : I2C_InitTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • AlphaMode : DMA2D_LayerCfgTypeDef
  • Alternate : GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AU_SIZE : HAL_SD_CardStatusTypedef
  • AudioFreq : I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
  • AutomaticPadCRCStrip : ETH_MACInitTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • AutoNegotiation : ETH_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AWUM : CAN_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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  • g
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  • u
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  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • BackOffLimit : ETH_MACInitTypeDef
  • BankNumber : CAN_FilterConfTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BaudRate : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BESL : PCD_HandleTypeDef
  • Block : NAND_AddressTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : NAND_InfoTypeDef
  • BlockSize : NAND_InfoTypeDef
  • Blue : DMA2D_ColorTypeDef
  • BootAddr0 : FLASH_OBProgramInitTypeDef
  • BootAddr1 : FLASH_OBProgramInitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastFramesReception : ETH_MACInitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
  • buffer : ETH_DMARxFrameInfos
  • Buffer1Addr : ETH_DMADescTypeDef
  • Buffer2NextDescAddr : ETH_DMADescTypeDef
  • ByteSelectMode : DCMI_InitTypeDef
  • ByteSelectStart : DCMI_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
  • c
  • d
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  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CaptureRate : DCMI_InitTypeDef
  • CardBlockSize : HAL_SD_CardInfoTypedef
  • CardCapacity : HAL_SD_CardInfoTypedef
  • CardComdClasses : HAL_SD_CSDTypedef
  • CardType : SD_HandleTypeDef , HAL_SD_CardInfoTypedef
  • CarrierSense : ETH_MACInitTypeDef
  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • Channel : TIM_HandleTypeDef , ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , DMA_InitTypeDef
  • ChannelSelection : SPDIFRX_InitTypeDef
  • ChannelStatusMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • ChecksumMode : ETH_InitTypeDef
  • ChecksumOffload : ETH_MACInitTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • CID : SD_HandleTypeDef
  • CID_CRC : HAL_SD_CIDTypedef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • Clk48ClockSelection : RCC_PeriphCLKInitTypeDef
  • CLKLastBit : USART_InitTypeDef , SMARTCARD_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef
  • ClockPrescaler : ADC_InitTypeDef , QSPI_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , I2S_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CLUTColorMode : DMA2D_CLUTCfgTypeDef
  • ColorMode : DMA2D_InitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CompandingMode : SAI_InitTypeDef
  • ContentProtectAppli : HAL_SD_CSDTypedef
  • ContinuousConvMode : ADC_InitTypeDef
  • ControlBufferSize : ETH_DMADescTypeDef
  • CopyFlag : HAL_SD_CSDTypedef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : SPI_InitTypeDef
  • CRCLength : SPI_InitTypeDef , CRC_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CSD : SD_HandleTypeDef
  • CSD_CRC : HAL_SD_CSDTypedef
  • CSDStruct : HAL_SD_CSDTypedef
  • CsXferCount : SPDIFRX_HandleTypeDef
  • CsXferSize : SPDIFRX_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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  • r
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  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAT_BUS_WIDTH : HAL_SD_CardStatusTypedef
  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataFormat : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef , I2S_InitTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • Date : RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrHoldHalfCycle : QSPI_CommandTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DeferralCheck : ETH_MACInitTypeDef
  • DescriptorSkipLength : ETH_DMAInitTypeDef
  • DestinationAddrFilter : ETH_MACInitTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • DeviceSize : HAL_SD_CSDTypedef
  • DeviceSizeMul : HAL_SD_CSDTypedef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DLC : CanRxMsgTypeDef , CanTxMsgTypeDef
  • DMA_Handle : ADC_HandleTypeDef , DCMI_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DMAArbitration : ETH_DMAInitTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DmaTransferCplt : SD_HandleTypeDef
  • DropTCPIPChecksumErrorFrame : ETH_DMAInitTypeDef
  • DSRImpl : HAL_SD_CSDTypedef
  • DualAddressMode : I2C_InitTypeDef
  • DualFlash : QSPI_InitTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • DuplexMode : ETH_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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  • t
  • u
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  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ECC : HAL_SD_CSDTypedef
  • Enable : MPU_Region_InitTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef
  • EnhancedDescriptorFormat : ETH_DMAInitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ERASE_OFFSET : HAL_SD_CardStatusTypedef
  • ERASE_SIZE : HAL_SD_CardStatusTypedef
  • ERASE_TIMEOUT : HAL_SD_CardStatusTypedef
  • EraseGrMul : HAL_SD_CSDTypedef
  • EraseGrSize : HAL_SD_CSDTypedef
  • ErrorCode : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , FLASH_ProcessTypeDef , I2C_HandleTypeDef , __SAI_HandleTypeDef , QSPI_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , SMARTCARD_HandleTypeDef , SPDIFRX_HandleTypeDef , DCMI_HandleTypeDef , USART_HandleTypeDef , CEC_HandleTypeDef , DAC_HandleTypeDef
  • Extended : SRAM_HandleTypeDef , NOR_HandleTypeDef
  • ExtendedDataMode : DCMI_InitTypeDef
  • ExtendedStatus : ETH_DMADescTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtId : CanRxMsgTypeDef , CanTxMsgTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
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  • b
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  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FIFOMode : DMA_InitTypeDef
  • FIFONumber : CanRxMsgTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • FifoThreshold : QSPI_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef
  • FileFormat : HAL_SD_CSDTypedef
  • FileFormatGrouop : HAL_SD_CSDTypedef
  • Filter : RTC_TamperTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FixedBurst : ETH_DMAInitTypeDef
  • FlashID : QSPI_InitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FlushReceivedFrame : ETH_DMAInitTypeDef
  • FMI : CanRxMsgTypeDef
  • ForwardErrorFrames : ETH_DMAInitTypeDef
  • ForwardUndersizedGoodFrames : ETH_DMAInitTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FrameEndCode : DCMI_CodesInitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FrameStartCode : DCMI_CodesInitTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • FSRxDesc : ETH_DMARxFrameInfos
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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  • t
  • u
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  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GeneralCallMode : I2C_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • Green : DMA2D_ColorTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HashTableHigh : ETH_MACInitTypeDef
  • HashTableLow : ETH_MACInitTypeDef
  • hc : HCD_HandleTypeDef
  • hdma : QSPI_HandleTypeDef , SDRAM_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef
  • hdmaCsRx : SPDIFRX_HandleTypeDef
  • hdmaDrRx : SPDIFRX_HandleTypeDef
  • hdmarx : __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SD_HandleTypeDef , SMARTCARD_HandleTypeDef
  • hdmatx : SD_HandleTypeDef , USART_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HSPolarity : DCMI_InitTypeDef
  • HwFlowCtl : UART_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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  • r
  • s
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c4ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2sClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IFCR : DMA_Base_Registers
  • IN_ep : PCD_HandleTypeDef
  • Info : NAND_HandleTypeDef
  • Init : CRC_HandleTypeDef , DCMI_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_HandleTypeDef , HCD_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , PCD_HandleTypeDef , QSPI_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , SD_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , ADC_HandleTypeDef , WWDG_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef
  • InitiatorAddress : CEC_InitTypeDef
  • InitValue : CRC_InitTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InputAlpha : DMA2D_LayerCfgTypeDef
  • InputColorMode : DMA2D_LayerCfgTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputOffset : DMA2D_LayerCfgTypeDef
  • InputSelection : SPDIFRX_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : LPTIM_HandleTypeDef , ETH_HandleTypeDef , SDRAM_HandleTypeDef , SPDIFRX_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef , TIM_HandleTypeDef , SRAM_HandleTypeDef , RTC_HandleTypeDef , ADC_HandleTypeDef , NOR_HandleTypeDef , RNG_HandleTypeDef , UART_HandleTypeDef , IWDG_HandleTypeDef , I2S_HandleTypeDef , CAN_HandleTypeDef , __DMA_HandleTypeDef , NAND_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , SD_HandleTypeDef , CRC_HandleTypeDef , DCMI_HandleTypeDef , __DMA2D_HandleTypeDef , I2C_HandleTypeDef , CEC_HandleTypeDef , DAC_HandleTypeDef , __SAI_HandleTypeDef , QSPI_HandleTypeDef , WWDG_HandleTypeDef , HCD_HandleTypeDef , PCD_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • InterFrameGap : ETH_MACInitTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • ISR : DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
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  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- j -

  • Jabber : ETH_MACInitTypeDef
  • JPEGMode : DCMI_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LayerCfg : __DMA2D_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • length : ETH_DMARxFrameInfos
  • LineEndCode : DCMI_CodesInitTypeDef
  • LineSelectMode : DCMI_InitTypeDef
  • LineSelectStart : DCMI_InitTypeDef
  • LineStartCode : DCMI_CodesInitTypeDef
  • LinkStatus : ETH_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : __DMA_HandleTypeDef , WWDG_HandleTypeDef , USART_HandleTypeDef , __SAI_HandleTypeDef , TIM_HandleTypeDef , SRAM_HandleTypeDef , __SPI_HandleTypeDef , SD_HandleTypeDef , __DMA2D_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , ETH_HandleTypeDef , RTC_HandleTypeDef , RNG_HandleTypeDef , QSPI_HandleTypeDef , SPDIFRX_HandleTypeDef , NOR_HandleTypeDef , NAND_HandleTypeDef , FLASH_ProcessTypeDef , ADC_HandleTypeDef , IRDA_HandleTypeDef , I2S_HandleTypeDef , HCD_HandleTypeDef , UART_HandleTypeDef , I2C_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef , IWDG_HandleTypeDef , DCMI_HandleTypeDef , PCD_HandleTypeDef , LPTIM_HandleTypeDef , CRC_HandleTypeDef , DAC_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LoopbackMode : ETH_MACInitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : PCD_HandleTypeDef
  • LPM_State : PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
  • LSRxDesc : ETH_DMARxFrameInfos
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
  • c
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  • y
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MACAddr : ETH_InitTypeDef
  • Maker_Id : NAND_IDTypeDef
  • ManDeflECC : HAL_SD_CSDTypedef
  • ManufactDate : HAL_SD_CIDTypedef
  • Manufacturer_Code : NOR_IDTypeDef
  • ManufacturerID : HAL_SD_CIDTypedef
  • Mask : QSPI_AutoPollingTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxBusClkFrec : HAL_SD_CSDTypedef
  • MaxRdCurrentVDDMax : HAL_SD_CSDTypedef
  • MaxRdCurrentVDDMin : HAL_SD_CSDTypedef
  • MaxWrBlockLen : HAL_SD_CSDTypedef
  • MaxWrCurrentVDDMax : HAL_SD_CSDTypedef
  • MaxWrCurrentVDDMin : HAL_SD_CSDTypedef
  • Mckdiv : SAI_InitTypeDef
  • MCLKOutput : I2S_InitTypeDef
  • MediaInterface : ETH_InitTypeDef
  • MemBurst : DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef
  • Mode : DMA2D_InitTypeDef , CAN_InitTypeDef , SMARTCARD_InitTypeDef , DMA_InitTypeDef , ADC_MultiModeTypeDef , GPIO_InitTypeDef , IRDA_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , PWR_PVDTypeDef , I2S_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef
  • MSBFirst : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • MulticastFramesFilter : ETH_MACInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • x
  • y
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKState : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : QSPI_CommandTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfCurrentConversionRank : ADC_HandleTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbSectors : FLASH_EraseInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NoStretchMode : I2C_InitTypeDef
  • NSAC : HAL_SD_CSDTypedef
  • NSS : SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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  • u
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OEM_AppliID : HAL_SD_CIDTypedef
  • Offset : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputOffset : DMA2D_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OverrunDisable : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • OverSampling : UART_InitTypeDef , USART_InitTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • a
  • b
  • c
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  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • Page : NAND_AddressTypeDef
  • PageSize : NAND_InfoTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ParityErrorMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PartBlockRead : HAL_SD_CSDTypedef
  • PassControlFrames : ETH_MACInitTypeDef
  • PauseLowThreshold : ETH_MACInitTypeDef
  • PauseTime : ETH_MACInitTypeDef
  • pBuffPtr : __SAI_HandleTypeDef , DCMI_HandleTypeDef , I2C_HandleTypeDef
  • PCKPolarity : DCMI_InitTypeDef
  • pCLUT : DMA2D_CLUTCfgTypeDef
  • pCsBuffPtr : SPDIFRX_HandleTypeDef
  • pData : HCD_HandleTypeDef , PCD_HandleTypeDef
  • PERFORMANCE_MOVE : HAL_SD_CardStatusTypedef
  • Period : TIM_Base_InitTypeDef
  • PeriphBurst : DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PermWrProtect : HAL_SD_CSDTypedef
  • PhyAddress : ETH_InitTypeDef
  • Pin : GPIO_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLI2S : RCC_PeriphCLKInitTypeDef
  • PLLI2SDivQ : RCC_PeriphCLKInitTypeDef
  • PLLI2SN : RCC_PLLI2SInitTypeDef
  • PLLI2SP : RCC_PLLI2SInitTypeDef
  • PLLI2SQ : RCC_PLLI2SInitTypeDef
  • PLLI2SR : RCC_PLLI2SInitTypeDef
  • PLLM : RCC_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLSAI : RCC_PeriphCLKInitTypeDef
  • PLLSAIDivQ : RCC_PeriphCLKInitTypeDef
  • PLLSAIDivR : RCC_PeriphCLKInitTypeDef
  • PLLSAIN : RCC_PLLSAIInitTypeDef
  • PLLSAIP : RCC_PLLSAIInitTypeDef
  • PLLSAIQ : RCC_PLLSAIInitTypeDef
  • PLLSAIR : RCC_PLLSAIInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : LPTIM_ULPClockConfigTypeDef
  • PowerMode : IRDA_InitTypeDef
  • PreambleTypeMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : LPTIM_ClockConfigTypeDef , CAN_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef , WWDG_InitTypeDef
  • Priority : DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProdName1 : HAL_SD_CIDTypedef
  • ProdName2 : HAL_SD_CIDTypedef
  • ProdRev : HAL_SD_CIDTypedef
  • ProdSN : HAL_SD_CIDTypedef
  • PromiscuousMode : ETH_MACInitTypeDef
  • Protocol : SAI_InitTypeDef
  • pRxBuffPtr : I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , CEC_HandleTypeDef , SPDIFRX_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : IRDA_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , CEC_HandleTypeDef , QSPI_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • RCA : HAL_SD_CardInfoTypedef , SD_HandleTypeDef
  • RdBlockLen : HAL_SD_CSDTypedef
  • RdBlockMisalign : HAL_SD_CSDTypedef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReceiveAll : ETH_MACInitTypeDef
  • ReceiveFlowControl : ETH_MACInitTypeDef
  • ReceiveOwn : ETH_MACInitTypeDef
  • ReceiveStoreForward : ETH_DMAInitTypeDef
  • ReceiveThresholdControl : ETH_DMAInitTypeDef
  • Red : DMA2D_ColorTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef
  • Reserved0 : DMA_Base_Registers
  • Reserved1 : ETH_DMADescTypeDef , HAL_SD_CSDTypedef , HAL_SD_CIDTypedef
  • Reserved2 : HAL_SD_CSDTypedef , HAL_SD_CIDTypedef
  • Reserved3 : HAL_SD_CSDTypedef
  • Reserved4 : HAL_SD_CSDTypedef
  • Resolution : ADC_InitTypeDef
  • Retries : SPDIFRX_InitTypeDef
  • RetryTransmission : ETH_MACInitTypeDef
  • RFLM : CAN_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxDesc : ETH_HandleTypeDef
  • RxDMABurstLength : ETH_DMAInitTypeDef
  • RxFrameInfos : ETH_HandleTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxMode : ETH_InitTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxXferCount : I2S_HandleTypeDef , USART_HandleTypeDef , SPDIFRX_HandleTypeDef , IRDA_HandleTypeDef , QSPI_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • RxXferSize : __SPI_HandleTypeDef , SPDIFRX_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , QSPI_HandleTypeDef , CEC_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
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  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SD_CARD_TYPE : HAL_SD_CardStatusTypedef
  • SD_cid : HAL_SD_CardInfoTypedef
  • SD_csd : HAL_SD_CardInfoTypedef
  • Sdmmc1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SdOperation : SD_HandleTypeDef
  • SdTransferCplt : SD_HandleTypeDef
  • SdTransferErr : SD_HandleTypeDef
  • SecondFrameOperate : ETH_DMAInitTypeDef
  • Seconds : RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • SECURED_MODE : HAL_SD_CardStatusTypedef
  • SegCount : ETH_DMARxFrameInfos
  • Setup : PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • Size : MPU_Region_InitTypeDef , DMA2D_CLUTCfgTypeDef
  • SIZE_OF_PROTECTED_AREA : HAL_SD_CardStatusTypedef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SourceAddrFilter : ETH_MACInitTypeDef
  • SpareAreaSize : NAND_InfoTypeDef
  • Speed : ETH_InitTypeDef , GPIO_InitTypeDef
  • SPEED_CLASS : HAL_SD_CardStatusTypedef
  • Standard : I2S_InitTypeDef
  • State : __SAI_HandleTypeDef , IRDA_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , SPDIFRX_HandleTypeDef , ETH_HandleTypeDef , __SPI_HandleTypeDef , TIM_HandleTypeDef , RNG_HandleTypeDef , DAC_HandleTypeDef , USART_HandleTypeDef , RTC_HandleTypeDef , NOR_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef , CRC_HandleTypeDef , WWDG_HandleTypeDef , DCMI_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , HCD_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , SRAM_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , PCD_HandleTypeDef
  • Status : LPTIM_HandleTypeDef , ETH_DMADescTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StdId : CanRxMsgTypeDef , CanTxMsgTypeDef
  • StereoMode : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • StopBits : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroMode : DCMI_InitTypeDef
  • SyncroCode : DCMI_InitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
  • SysSpecVersion : HAL_SD_CSDTypedef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • TAAC : HAL_SD_CSDTypedef
  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TempWrProtect : HAL_SD_CSDTypedef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef
  • Timeout : QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampHigh : ETH_DMADescTypeDef
  • TimeStampLow : ETH_DMADescTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • Tolerance : CEC_InitTypeDef
  • TransmitFlowControl : ETH_MACInitTypeDef
  • TransmitStoreForward : ETH_DMAInitTypeDef
  • TransmitThresholdControl : ETH_DMAInitTypeDef
  • Trigger : LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriState : SAI_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxDesc : ETH_HandleTypeDef
  • TxDMABurstLength : ETH_DMAInitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxXferCount : CEC_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef
  • TxXferSize : SMARTCARD_HandleTypeDef , QSPI_HandleTypeDef , IRDA_HandleTypeDef , I2S_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart5ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart7ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart8ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UnicastFramesFilter : ETH_MACInitTypeDef
  • UnicastPauseFrameDetect : ETH_MACInitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart6ClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • ValidityBitMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • VLANTagComparison : ETH_MACInitTypeDef
  • VLANTagIdentifier : ETH_MACInitTypeDef
  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
  • VSPolarity : DCMI_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WaitForActivity : SPDIFRX_InitTypeDef
  • Watchdog : ETH_MACInitTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WordLength : IRDA_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • WrBlockMisalign : HAL_SD_CSDTypedef
  • WriteBlockPaPartial : HAL_SD_CSDTypedef
  • WrProtectGrEnable : HAL_SD_CSDTypedef
  • WrProtectGrSize : HAL_SD_CSDTypedef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
  • WrSpeedFact : HAL_SD_CSDTypedef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferCount : DCMI_HandleTypeDef , I2C_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferSize : I2C_HandleTypeDef , DCMI_HandleTypeDef , __SAI_HandleTypeDef
  • XferTransferNumber : DCMI_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- z -

  • ZeroQuantaPause : ETH_MACInitTypeDef
  • Zone : NAND_AddressTypeDef
  • ZoneSize : NAND_InfoTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- a -

  • ABOM : CAN_InitTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef
  • AddressAlignedBeats : ETH_DMAInitTypeDef
  • AddressingMode : I2C_InitTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • AlphaMode : DMA2D_LayerCfgTypeDef
  • Alternate : GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AU_SIZE : HAL_SD_CardStatusTypedef
  • AudioFreq : I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
  • AutomaticPadCRCStrip : ETH_MACInitTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • AutoNegotiation : ETH_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • AWUM : CAN_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- b -

  • BackOffLimit : ETH_MACInitTypeDef
  • BankNumber : CAN_FilterConfTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BaudRate : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BESL : PCD_HandleTypeDef
  • Block : NAND_AddressTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : NAND_InfoTypeDef
  • BlockSize : NAND_InfoTypeDef
  • Blue : DMA2D_ColorTypeDef
  • BootAddr0 : FLASH_OBProgramInitTypeDef
  • BootAddr1 : FLASH_OBProgramInitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastFramesReception : ETH_MACInitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
  • buffer : ETH_DMARxFrameInfos
  • Buffer1Addr : ETH_DMADescTypeDef
  • Buffer2NextDescAddr : ETH_DMADescTypeDef
  • ByteSelectMode : DCMI_InitTypeDef
  • ByteSelectStart : DCMI_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- c -

  • CaptureRate : DCMI_InitTypeDef
  • CardBlockSize : HAL_SD_CardInfoTypedef
  • CardCapacity : HAL_SD_CardInfoTypedef
  • CardComdClasses : HAL_SD_CSDTypedef
  • CardType : SD_HandleTypeDef , HAL_SD_CardInfoTypedef
  • CarrierSense : ETH_MACInitTypeDef
  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • Channel : TIM_HandleTypeDef , ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , DMA_InitTypeDef
  • ChannelSelection : SPDIFRX_InitTypeDef
  • ChannelStatusMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • ChecksumMode : ETH_InitTypeDef
  • ChecksumOffload : ETH_MACInitTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • CID : SD_HandleTypeDef
  • CID_CRC : HAL_SD_CIDTypedef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • Clk48ClockSelection : RCC_PeriphCLKInitTypeDef
  • CLKLastBit : USART_InitTypeDef , SMARTCARD_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef
  • ClockPrescaler : ADC_InitTypeDef , QSPI_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , I2S_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CLUTColorMode : DMA2D_CLUTCfgTypeDef
  • ColorMode : DMA2D_InitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CompandingMode : SAI_InitTypeDef
  • ContentProtectAppli : HAL_SD_CSDTypedef
  • ContinuousConvMode : ADC_InitTypeDef
  • ControlBufferSize : ETH_DMADescTypeDef
  • CopyFlag : HAL_SD_CSDTypedef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : SPI_InitTypeDef
  • CRCLength : SPI_InitTypeDef , CRC_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CSD : SD_HandleTypeDef
  • CSD_CRC : HAL_SD_CSDTypedef
  • CSDStruct : HAL_SD_CSDTypedef
  • CsXferCount : SPDIFRX_HandleTypeDef
  • CsXferSize : SPDIFRX_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- d -

  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAT_BUS_WIDTH : HAL_SD_CardStatusTypedef
  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataFormat : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef , I2S_InitTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • Date : RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrHoldHalfCycle : QSPI_CommandTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DeferralCheck : ETH_MACInitTypeDef
  • DescriptorSkipLength : ETH_DMAInitTypeDef
  • DestinationAddrFilter : ETH_MACInitTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • DeviceSize : HAL_SD_CSDTypedef
  • DeviceSizeMul : HAL_SD_CSDTypedef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DLC : CanRxMsgTypeDef , CanTxMsgTypeDef
  • DMA_Handle : ADC_HandleTypeDef , DCMI_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DMAArbitration : ETH_DMAInitTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DmaTransferCplt : SD_HandleTypeDef
  • DropTCPIPChecksumErrorFrame : ETH_DMAInitTypeDef
  • DSRImpl : HAL_SD_CSDTypedef
  • DualAddressMode : I2C_InitTypeDef
  • DualFlash : QSPI_InitTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • DuplexMode : ETH_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- e -

  • ECC : HAL_SD_CSDTypedef
  • Enable : MPU_Region_InitTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef
  • EnhancedDescriptorFormat : ETH_DMAInitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ERASE_OFFSET : HAL_SD_CardStatusTypedef
  • ERASE_SIZE : HAL_SD_CardStatusTypedef
  • ERASE_TIMEOUT : HAL_SD_CardStatusTypedef
  • EraseGrMul : HAL_SD_CSDTypedef
  • EraseGrSize : HAL_SD_CSDTypedef
  • ErrorCode : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , FLASH_ProcessTypeDef , I2C_HandleTypeDef , __SAI_HandleTypeDef , QSPI_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , SMARTCARD_HandleTypeDef , SPDIFRX_HandleTypeDef , DCMI_HandleTypeDef , USART_HandleTypeDef , CEC_HandleTypeDef , DAC_HandleTypeDef
  • Extended : SRAM_HandleTypeDef , NOR_HandleTypeDef
  • ExtendedDataMode : DCMI_InitTypeDef
  • ExtendedStatus : ETH_DMADescTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtId : CanRxMsgTypeDef , CanTxMsgTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- f -

  • FIFOMode : DMA_InitTypeDef
  • FIFONumber : CanRxMsgTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • FifoThreshold : QSPI_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef
  • FileFormat : HAL_SD_CSDTypedef
  • FileFormatGrouop : HAL_SD_CSDTypedef
  • Filter : RTC_TamperTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FixedBurst : ETH_DMAInitTypeDef
  • FlashID : QSPI_InitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FlushReceivedFrame : ETH_DMAInitTypeDef
  • FMI : CanRxMsgTypeDef
  • ForwardErrorFrames : ETH_DMAInitTypeDef
  • ForwardUndersizedGoodFrames : ETH_DMAInitTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FrameEndCode : DCMI_CodesInitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FrameStartCode : DCMI_CodesInitTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • FSRxDesc : ETH_DMARxFrameInfos
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- g -

  • GeneralCallMode : I2C_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • Green : DMA2D_ColorTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- h -

  • HashTableHigh : ETH_MACInitTypeDef
  • HashTableLow : ETH_MACInitTypeDef
  • hc : HCD_HandleTypeDef
  • hdma : QSPI_HandleTypeDef , SDRAM_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef
  • hdmaCsRx : SPDIFRX_HandleTypeDef
  • hdmaDrRx : SPDIFRX_HandleTypeDef
  • hdmarx : __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SD_HandleTypeDef , SMARTCARD_HandleTypeDef
  • hdmatx : SD_HandleTypeDef , USART_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HSPolarity : DCMI_InitTypeDef
  • HwFlowCtl : UART_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c4ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2sClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IFCR : DMA_Base_Registers
  • IN_ep : PCD_HandleTypeDef
  • Info : NAND_HandleTypeDef
  • Init : CRC_HandleTypeDef , DCMI_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , ETH_HandleTypeDef , HCD_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , PCD_HandleTypeDef , QSPI_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , SD_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , SPDIFRX_HandleTypeDef , __SPI_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , ADC_HandleTypeDef , WWDG_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef
  • InitiatorAddress : CEC_InitTypeDef
  • InitValue : CRC_InitTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InputAlpha : DMA2D_LayerCfgTypeDef
  • InputColorMode : DMA2D_LayerCfgTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputOffset : DMA2D_LayerCfgTypeDef
  • InputSelection : SPDIFRX_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : LPTIM_HandleTypeDef , ETH_HandleTypeDef , SDRAM_HandleTypeDef , SPDIFRX_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef , TIM_HandleTypeDef , SRAM_HandleTypeDef , RTC_HandleTypeDef , ADC_HandleTypeDef , NOR_HandleTypeDef , RNG_HandleTypeDef , UART_HandleTypeDef , IWDG_HandleTypeDef , I2S_HandleTypeDef , CAN_HandleTypeDef , __DMA_HandleTypeDef , NAND_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , SD_HandleTypeDef , CRC_HandleTypeDef , DCMI_HandleTypeDef , __DMA2D_HandleTypeDef , I2C_HandleTypeDef , CEC_HandleTypeDef , DAC_HandleTypeDef , __SAI_HandleTypeDef , QSPI_HandleTypeDef , WWDG_HandleTypeDef , HCD_HandleTypeDef , PCD_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • InterFrameGap : ETH_MACInitTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • ISR : DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- j -

  • Jabber : ETH_MACInitTypeDef
  • JPEGMode : DCMI_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- l -

  • LayerCfg : __DMA2D_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • length : ETH_DMARxFrameInfos
  • LineEndCode : DCMI_CodesInitTypeDef
  • LineSelectMode : DCMI_InitTypeDef
  • LineSelectStart : DCMI_InitTypeDef
  • LineStartCode : DCMI_CodesInitTypeDef
  • LinkStatus : ETH_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : __DMA_HandleTypeDef , WWDG_HandleTypeDef , USART_HandleTypeDef , __SAI_HandleTypeDef , TIM_HandleTypeDef , SRAM_HandleTypeDef , __SPI_HandleTypeDef , SD_HandleTypeDef , __DMA2D_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , ETH_HandleTypeDef , RTC_HandleTypeDef , RNG_HandleTypeDef , QSPI_HandleTypeDef , SPDIFRX_HandleTypeDef , NOR_HandleTypeDef , NAND_HandleTypeDef , FLASH_ProcessTypeDef , ADC_HandleTypeDef , IRDA_HandleTypeDef , I2S_HandleTypeDef , HCD_HandleTypeDef , UART_HandleTypeDef , I2C_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef , IWDG_HandleTypeDef , DCMI_HandleTypeDef , PCD_HandleTypeDef , LPTIM_HandleTypeDef , CRC_HandleTypeDef , DAC_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LoopbackMode : ETH_MACInitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : PCD_HandleTypeDef
  • LPM_State : PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
  • LSRxDesc : ETH_DMARxFrameInfos
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- m -

  • MACAddr : ETH_InitTypeDef
  • Maker_Id : NAND_IDTypeDef
  • ManDeflECC : HAL_SD_CSDTypedef
  • ManufactDate : HAL_SD_CIDTypedef
  • Manufacturer_Code : NOR_IDTypeDef
  • ManufacturerID : HAL_SD_CIDTypedef
  • Mask : QSPI_AutoPollingTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxBusClkFrec : HAL_SD_CSDTypedef
  • MaxRdCurrentVDDMax : HAL_SD_CSDTypedef
  • MaxRdCurrentVDDMin : HAL_SD_CSDTypedef
  • MaxWrBlockLen : HAL_SD_CSDTypedef
  • MaxWrCurrentVDDMax : HAL_SD_CSDTypedef
  • MaxWrCurrentVDDMin : HAL_SD_CSDTypedef
  • Mckdiv : SAI_InitTypeDef
  • MCLKOutput : I2S_InitTypeDef
  • MediaInterface : ETH_InitTypeDef
  • MemBurst : DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef
  • Mode : DMA2D_InitTypeDef , CAN_InitTypeDef , SMARTCARD_InitTypeDef , DMA_InitTypeDef , ADC_MultiModeTypeDef , GPIO_InitTypeDef , IRDA_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , PWR_PVDTypeDef , I2S_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef
  • MSBFirst : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • MulticastFramesFilter : ETH_MACInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- n -

  • NACKState : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : QSPI_CommandTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfCurrentConversionRank : ADC_HandleTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbSectors : FLASH_EraseInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NoStretchMode : I2C_InitTypeDef
  • NSAC : HAL_SD_CSDTypedef
  • NSS : SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OEM_AppliID : HAL_SD_CIDTypedef
  • Offset : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputOffset : DMA2D_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OverrunDisable : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • OverSampling : UART_InitTypeDef , USART_InitTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- p -

  • Page : NAND_AddressTypeDef
  • PageSize : NAND_InfoTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ParityErrorMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PartBlockRead : HAL_SD_CSDTypedef
  • PassControlFrames : ETH_MACInitTypeDef
  • PauseLowThreshold : ETH_MACInitTypeDef
  • PauseTime : ETH_MACInitTypeDef
  • pBuffPtr : __SAI_HandleTypeDef , DCMI_HandleTypeDef , I2C_HandleTypeDef
  • PCKPolarity : DCMI_InitTypeDef
  • pCLUT : DMA2D_CLUTCfgTypeDef
  • pCsBuffPtr : SPDIFRX_HandleTypeDef
  • pData : HCD_HandleTypeDef , PCD_HandleTypeDef
  • PERFORMANCE_MOVE : HAL_SD_CardStatusTypedef
  • Period : TIM_Base_InitTypeDef
  • PeriphBurst : DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PermWrProtect : HAL_SD_CSDTypedef
  • PhyAddress : ETH_InitTypeDef
  • Pin : GPIO_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLI2S : RCC_PeriphCLKInitTypeDef
  • PLLI2SDivQ : RCC_PeriphCLKInitTypeDef
  • PLLI2SN : RCC_PLLI2SInitTypeDef
  • PLLI2SP : RCC_PLLI2SInitTypeDef
  • PLLI2SQ : RCC_PLLI2SInitTypeDef
  • PLLI2SR : RCC_PLLI2SInitTypeDef
  • PLLM : RCC_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLSAI : RCC_PeriphCLKInitTypeDef
  • PLLSAIDivQ : RCC_PeriphCLKInitTypeDef
  • PLLSAIDivR : RCC_PeriphCLKInitTypeDef
  • PLLSAIN : RCC_PLLSAIInitTypeDef
  • PLLSAIP : RCC_PLLSAIInitTypeDef
  • PLLSAIQ : RCC_PLLSAIInitTypeDef
  • PLLSAIR : RCC_PLLSAIInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : LPTIM_ULPClockConfigTypeDef
  • PowerMode : IRDA_InitTypeDef
  • PreambleTypeMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : LPTIM_ClockConfigTypeDef , CAN_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef , WWDG_InitTypeDef
  • Priority : DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProdName1 : HAL_SD_CIDTypedef
  • ProdName2 : HAL_SD_CIDTypedef
  • ProdRev : HAL_SD_CIDTypedef
  • ProdSN : HAL_SD_CIDTypedef
  • PromiscuousMode : ETH_MACInitTypeDef
  • Protocol : SAI_InitTypeDef
  • pRxBuffPtr : I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , CEC_HandleTypeDef , SPDIFRX_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : IRDA_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , CEC_HandleTypeDef , QSPI_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • RCA : HAL_SD_CardInfoTypedef , SD_HandleTypeDef
  • RdBlockLen : HAL_SD_CSDTypedef
  • RdBlockMisalign : HAL_SD_CSDTypedef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReceiveAll : ETH_MACInitTypeDef
  • ReceiveFlowControl : ETH_MACInitTypeDef
  • ReceiveOwn : ETH_MACInitTypeDef
  • ReceiveStoreForward : ETH_DMAInitTypeDef
  • ReceiveThresholdControl : ETH_DMAInitTypeDef
  • Red : DMA2D_ColorTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef
  • Reserved0 : DMA_Base_Registers
  • Reserved1 : ETH_DMADescTypeDef , HAL_SD_CSDTypedef , HAL_SD_CIDTypedef
  • Reserved2 : HAL_SD_CSDTypedef , HAL_SD_CIDTypedef
  • Reserved3 : HAL_SD_CSDTypedef
  • Reserved4 : HAL_SD_CSDTypedef
  • Resolution : ADC_InitTypeDef
  • Retries : SPDIFRX_InitTypeDef
  • RetryTransmission : ETH_MACInitTypeDef
  • RFLM : CAN_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxDesc : ETH_HandleTypeDef
  • RxDMABurstLength : ETH_DMAInitTypeDef
  • RxFrameInfos : ETH_HandleTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxMode : ETH_InitTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxXferCount : I2S_HandleTypeDef , USART_HandleTypeDef , SPDIFRX_HandleTypeDef , IRDA_HandleTypeDef , QSPI_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • RxXferSize : __SPI_HandleTypeDef , SPDIFRX_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , QSPI_HandleTypeDef , CEC_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SD_CARD_TYPE : HAL_SD_CardStatusTypedef
  • SD_cid : HAL_SD_CardInfoTypedef
  • SD_csd : HAL_SD_CardInfoTypedef
  • Sdmmc1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SdOperation : SD_HandleTypeDef
  • SdTransferCplt : SD_HandleTypeDef
  • SdTransferErr : SD_HandleTypeDef
  • SecondFrameOperate : ETH_DMAInitTypeDef
  • Seconds : RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • SECURED_MODE : HAL_SD_CardStatusTypedef
  • SegCount : ETH_DMARxFrameInfos
  • Setup : PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • Size : MPU_Region_InitTypeDef , DMA2D_CLUTCfgTypeDef
  • SIZE_OF_PROTECTED_AREA : HAL_SD_CardStatusTypedef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SourceAddrFilter : ETH_MACInitTypeDef
  • SpareAreaSize : NAND_InfoTypeDef
  • Speed : ETH_InitTypeDef , GPIO_InitTypeDef
  • SPEED_CLASS : HAL_SD_CardStatusTypedef
  • Standard : I2S_InitTypeDef
  • State : __SAI_HandleTypeDef , IRDA_HandleTypeDef , SDRAM_HandleTypeDef , SMARTCARD_HandleTypeDef , SPDIFRX_HandleTypeDef , ETH_HandleTypeDef , __SPI_HandleTypeDef , TIM_HandleTypeDef , RNG_HandleTypeDef , DAC_HandleTypeDef , USART_HandleTypeDef , RTC_HandleTypeDef , NOR_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , CEC_HandleTypeDef , CRC_HandleTypeDef , WWDG_HandleTypeDef , DCMI_HandleTypeDef , __DMA_HandleTypeDef , __DMA2D_HandleTypeDef , HCD_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , SRAM_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , PCD_HandleTypeDef
  • Status : LPTIM_HandleTypeDef , ETH_DMADescTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StdId : CanRxMsgTypeDef , CanTxMsgTypeDef
  • StereoMode : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • StopBits : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroMode : DCMI_InitTypeDef
  • SyncroCode : DCMI_InitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
  • SysSpecVersion : HAL_SD_CSDTypedef
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STM32F745xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- t -

  • TAAC : HAL_SD_CSDTypedef
  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TempWrProtect : HAL_SD_CSDTypedef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef
  • Timeout : QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampHigh : ETH_DMADescTypeDef
  • TimeStampLow : ETH_DMADescTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • Tolerance : CEC_InitTypeDef
  • TransmitFlowControl : ETH_MACInitTypeDef
  • TransmitStoreForward : ETH_DMAInitTypeDef
  • TransmitThresholdControl : ETH_DMAInitTypeDef
  • Trigger : LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriState : SAI_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxDesc : ETH_HandleTypeDef
  • TxDMABurstLength : ETH_DMAInitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxXferCount : CEC_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef
  • TxXferSize : SMARTCARD_HandleTypeDef , QSPI_HandleTypeDef , IRDA_HandleTypeDef , I2S_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
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STM32F745xx HAL User Manual: Data Fields - Variables

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- u -

  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart5ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart7ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart8ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UnicastFramesFilter : ETH_MACInitTypeDef
  • UnicastPauseFrameDetect : ETH_MACInitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart6ClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
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STM32F745xx HAL User Manual: Data Fields - Variables

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- v -

  • ValidityBitMask : SPDIFRX_InitTypeDef , SPDIFRX_SetDataFormatTypeDef
  • VLANTagComparison : ETH_MACInitTypeDef
  • VLANTagIdentifier : ETH_MACInitTypeDef
  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
  • VSPolarity : DCMI_InitTypeDef
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STM32F745xx HAL User Manual: Data Fields - Variables

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  • WaitForActivity : SPDIFRX_InitTypeDef
  • Watchdog : ETH_MACInitTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WordLength : IRDA_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • WrBlockMisalign : HAL_SD_CSDTypedef
  • WriteBlockPaPartial : HAL_SD_CSDTypedef
  • WrProtectGrEnable : HAL_SD_CSDTypedef
  • WrProtectGrSize : HAL_SD_CSDTypedef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
  • WrSpeedFact : HAL_SD_CSDTypedef
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STM32F745xx HAL User Manual: Data Fields - Variables

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  • XferCount : DCMI_HandleTypeDef , I2C_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef , __DMA2D_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferSize : I2C_HandleTypeDef , DCMI_HandleTypeDef , __SAI_HandleTypeDef
  • XferTransferNumber : DCMI_HandleTypeDef
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STM32F745xx HAL User Manual: Data Fields - Variables

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- y -

  • Year : RTC_DateTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Fields - Variables

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  • ZeroQuantaPause : ETH_MACInitTypeDef
  • Zone : NAND_AddressTypeDef
  • ZoneSize : NAND_InfoTypeDef
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32f7xx_hal_conf.h File Reference
#include "stm32f7xx_hal_rcc.h"
#include "stm32f7xx_hal_gpio.h"
#include "stm32f7xx_hal_dma.h"
#include "stm32f7xx_hal_cortex.h"
#include "stm32f7xx_hal_adc.h"
#include "stm32f7xx_hal_can.h"
#include "stm32f7xx_hal_cec.h"
#include "stm32f7xx_hal_crc.h"
#include "stm32f7xx_hal_cryp.h"
#include "stm32f7xx_hal_dma2d.h"
#include "stm32f7xx_hal_dac.h"
#include "stm32f7xx_hal_dcmi.h"
#include "stm32f7xx_hal_eth.h"
#include "stm32f7xx_hal_flash.h"
#include "stm32f7xx_hal_sram.h"
#include "stm32f7xx_hal_nor.h"
#include "stm32f7xx_hal_nand.h"
#include "stm32f7xx_hal_sdram.h"
#include "stm32f7xx_hal_hash.h"
#include "stm32f7xx_hal_i2c.h"
#include "stm32f7xx_hal_i2s.h"
#include "stm32f7xx_hal_iwdg.h"
#include "stm32f7xx_hal_lptim.h"
#include "stm32f7xx_hal_ltdc.h"
#include "stm32f7xx_hal_pwr.h"
#include "stm32f7xx_hal_qspi.h"
#include "stm32f7xx_hal_rng.h"
#include "stm32f7xx_hal_rtc.h"
#include "stm32f7xx_hal_sai.h"
#include "stm32f7xx_hal_sd.h"
#include "stm32f7xx_hal_spdifrx.h"
#include "stm32f7xx_hal_spi.h"
#include "stm32f7xx_hal_tim.h"
#include "stm32f7xx_hal_uart.h"
#include "stm32f7xx_hal_usart.h"
#include "stm32f7xx_hal_irda.h"
#include "stm32f7xx_hal_smartcard.h"
#include "stm32f7xx_hal_wwdg.h"
#include "stm32f7xx_hal_pcd.h"
#include "stm32f7xx_hal_hcd.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CAN_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DCMI_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_DMA2D_MODULE_ENABLED
#define | HAL_ETH_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_SDRAM_MODULE_ENABLED
#define | HAL_HASH_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_LTDC_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SD_MODULE_ENABLED
#define | HAL_SPDIFRX_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HSE_VALUE ((uint32_t)25000000)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT ((uint32_t)500)
#define | HSI_VALUE ((uint32_t)16000000)
Internal High Speed oscillator (HSI) value.
#define | LSI_VALUE ((uint32_t)32000)
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE ((uint32_t)32768)
External Low Speed oscillator (LSE) value.
#define | EXTERNAL_CLOCK_VALUE ((uint32_t)12288000)
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.
#define | VDD_VALUE ((uint32_t)3300)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((uint32_t)0x0F)
#define | USE_RTOS 0
#define | PREFETCH_ENABLE 1
#define | ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
#define | MAC_ADDR0 2
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
#define | MAC_ADDR1 0
#define | MAC_ADDR2 0
#define | MAC_ADDR3 0
#define | MAC_ADDR4 0
#define | MAC_ADDR5 0
#define | ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define | ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define | ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define | ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define | DP83848_PHY_ADDRESS 0x01
#define | PHY_RESET_DELAY ((uint32_t)0x000000FF)
#define | PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define | PHY_READ_TO ((uint32_t)0x0000FFFF)
#define | PHY_WRITE_TO ((uint32_t)0x0000FFFF)
#define | PHY_BCR ((uint16_t)0x00)
#define | PHY_BSR ((uint16_t)0x01)
#define | PHY_RESET ((uint16_t)0x8000)
#define | PHY_LOOPBACK ((uint16_t)0x4000)
#define | PHY_FULLDUPLEX_100M ((uint16_t)0x2100)
#define | PHY_HALFDUPLEX_100M ((uint16_t)0x2000)
#define | PHY_FULLDUPLEX_10M ((uint16_t)0x0100)
#define | PHY_HALFDUPLEX_10M ((uint16_t)0x0000)
#define | PHY_AUTONEGOTIATION ((uint16_t)0x1000)
#define | PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)
#define | PHY_POWERDOWN ((uint16_t)0x0800)
#define | PHY_ISOLATE ((uint16_t)0x0400)
#define | PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)
#define | PHY_LINKED_STATUS ((uint16_t)0x0004)
#define | PHY_JABBER_DETECTION ((uint16_t)0x0002)
#define | PHY_SR ((uint16_t)0x10)
#define | PHY_MICR ((uint16_t)0x11)
#define | PHY_MISR ((uint16_t)0x12)
#define | PHY_LINK_STATUS ((uint16_t)0x0001)
#define | PHY_SPEED_STATUS ((uint16_t)0x0002)
#define | PHY_DUPLEX_STATUS ((uint16_t)0x0004)
#define | PHY_MICR_INT_EN ((uint16_t)0x0002)
#define | PHY_MICR_INT_OE ((uint16_t)0x0001)
#define | PHY_MISR_LINK_INT_EN ((uint16_t)0x0020)
#define | PHY_LINK_INTERRUPT ((uint16_t)0x2000)
#define | assert_param(expr) ((void)0)
Include module's header file.

Define Documentation

#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */

Definition at line 156 of file stm32f7xx_hal_conf.h.

#define assert_param ( expr ) ((void)0)

Include module's header file.

Definition at line 410 of file stm32f7xx_hal_conf.h.

Referenced by ADC_Init(), ETH_MACAddressConfig(), FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_BootAddressConfig(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), FLASH_Program_Word(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_CAN_ConfigFilter(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_Receive(), HAL_CEC_Transmit(), HAL_CEC_Transmit_IT(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_TriangleWaveGenerate(), HAL_DCMI_ConfigCROP(), HAL_DCMI_Init(), HAL_DCMI_Start_DMA(), HAL_DMA2D_BlendingStart(), HAL_DMA2D_BlendingStart_IT(), HAL_DMA2D_ConfigCLUT(), HAL_DMA2D_ConfigLayer(), HAL_DMA2D_DisableCLUT(), HAL_DMA2D_EnableCLUT(), HAL_DMA2D_Init(), HAL_DMA2D_ProgramLineEvent(), HAL_DMA2D_Start(), HAL_DMA2D_Start_IT(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_ETH_ConfigDMA(), HAL_ETH_ConfigMAC(), HAL_ETH_Init(), HAL_ETH_ReadPHYRegister(), HAL_ETH_WritePHYRegister(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HCD_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_PCD_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_EnterUnderDriveSTOPMode(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_RCC_ClockConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_InitProtocol(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SPDIFRX_DeInit(), HAL_SPDIFRX_Init(), HAL_SPDIFRX_SetDataFormat(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WWDG_DeInit(), HAL_WWDG_Init(), HAL_WWDG_Refresh(), I2C_TransferConfig(), IRDA_SetConfig(), QSPI_Config(), SAI_InitI2S(), SAI_InitPCM(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), TIM_CCxChannelCmd(), TIM_CCxNChannelCmd(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), and USART_SetConfig().

#define DP83848_PHY_ADDRESS 0x01

Definition at line 186 of file stm32f7xx_hal_conf.h.

#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */

Definition at line 178 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_DMARxDescListInit().

#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */

Definition at line 180 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_GetReceivedFrame_IT().

#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */

Definition at line 179 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_DMATxDescListInit(), and HAL_ETH_TransmitFrame().

#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */

Definition at line 181 of file stm32f7xx_hal_conf.h.

#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000)

External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.

Value of the Internal oscillator in Hz

Definition at line 142 of file stm32f7xx_hal_conf.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKFreq(), and I2S_GetClockFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 56 of file stm32f7xx_hal_conf.h.

#define HAL_CAN_MODULE_ENABLED

Definition at line 57 of file stm32f7xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 58 of file stm32f7xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 93 of file stm32f7xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 59 of file stm32f7xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 60 of file stm32f7xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 61 of file stm32f7xx_hal_conf.h.

#define HAL_DCMI_MODULE_ENABLED

Definition at line 62 of file stm32f7xx_hal_conf.h.

#define HAL_DMA2D_MODULE_ENABLED

Definition at line 64 of file stm32f7xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 63 of file stm32f7xx_hal_conf.h.

#define HAL_ETH_MODULE_ENABLED

Definition at line 65 of file stm32f7xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 66 of file stm32f7xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 72 of file stm32f7xx_hal_conf.h.

#define HAL_HASH_MODULE_ENABLED

Definition at line 71 of file stm32f7xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 95 of file stm32f7xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 73 of file stm32f7xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 74 of file stm32f7xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 90 of file stm32f7xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 75 of file stm32f7xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 76 of file stm32f7xx_hal_conf.h.

#define HAL_LTDC_MODULE_ENABLED

Definition at line 77 of file stm32f7xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 55 of file stm32f7xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 67 of file stm32f7xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 68 of file stm32f7xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 94 of file stm32f7xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 78 of file stm32f7xx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 79 of file stm32f7xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 80 of file stm32f7xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 81 of file stm32f7xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 82 of file stm32f7xx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 83 of file stm32f7xx_hal_conf.h.

#define HAL_SD_MODULE_ENABLED

Definition at line 84 of file stm32f7xx_hal_conf.h.

#define HAL_SDRAM_MODULE_ENABLED

Definition at line 70 of file stm32f7xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 91 of file stm32f7xx_hal_conf.h.

#define HAL_SPDIFRX_MODULE_ENABLED

Definition at line 85 of file stm32f7xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 86 of file stm32f7xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 69 of file stm32f7xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 87 of file stm32f7xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 88 of file stm32f7xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 89 of file stm32f7xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 92 of file stm32f7xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT ((uint32_t)500)

Time out for HSE start up, in ms

Definition at line 109 of file stm32f7xx_hal_conf.h.

#define HSE_VALUE ((uint32_t)25000000)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 105 of file stm32f7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), and I2S_GetClockFreq().

#define HSI_VALUE ((uint32_t)16000000)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 118 of file stm32f7xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), I2S_GetClockFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSE_VALUE ((uint32_t)32768)

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. Value of the External Low Speed oscillator in Hz

Definition at line 133 of file stm32f7xx_hal_conf.h.

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI_VALUE ((uint32_t)32000)

Internal Low Speed oscillator (LSI) value.

LSI Typical Value in Hz

Definition at line 125 of file stm32f7xx_hal_conf.h.

#define MAC_ADDR0 2

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Definition at line 170 of file stm32f7xx_hal_conf.h.

#define MAC_ADDR1 0

Definition at line 171 of file stm32f7xx_hal_conf.h.

#define MAC_ADDR2 0

Definition at line 172 of file stm32f7xx_hal_conf.h.

#define MAC_ADDR3 0

Definition at line 173 of file stm32f7xx_hal_conf.h.

#define MAC_ADDR4 0

Definition at line 174 of file stm32f7xx_hal_conf.h.

#define MAC_ADDR5 0

Definition at line 175 of file stm32f7xx_hal_conf.h.

#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)

Auto-Negotiation process completed

Definition at line 211 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_AUTONEGOTIATION ((uint16_t)0x1000)

Enable auto-negotiation function

Definition at line 206 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_BCR ((uint16_t)0x00)

Transceiver Basic Control Register

Definition at line 197 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_BSR ((uint16_t)0x01)

Transceiver Basic Status Register

Definition at line 198 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)

Definition at line 190 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_DUPLEX_STATUS ((uint16_t)0x0004)

PHY Duplex mask

Definition at line 223 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100)

Set the full-duplex mode at 100 Mb/s

Definition at line 202 of file stm32f7xx_hal_conf.h.

#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100)

Set the full-duplex mode at 10 Mb/s

Definition at line 204 of file stm32f7xx_hal_conf.h.

#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000)

Set the half-duplex mode at 100 Mb/s

Definition at line 203 of file stm32f7xx_hal_conf.h.

#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000)

Set the half-duplex mode at 10 Mb/s

Definition at line 205 of file stm32f7xx_hal_conf.h.

#define PHY_ISOLATE ((uint16_t)0x0400)

Isolate PHY from MII

Definition at line 209 of file stm32f7xx_hal_conf.h.

#define PHY_JABBER_DETECTION ((uint16_t)0x0002)

Jabber condition detected

Definition at line 213 of file stm32f7xx_hal_conf.h.

#define PHY_LINK_INTERRUPT ((uint16_t)0x2000)

PHY link status interrupt mask

Definition at line 229 of file stm32f7xx_hal_conf.h.

#define PHY_LINK_STATUS ((uint16_t)0x0001)

PHY Link mask

Definition at line 221 of file stm32f7xx_hal_conf.h.

#define PHY_LINKED_STATUS ((uint16_t)0x0004)

Valid link established

Definition at line 212 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_LOOPBACK ((uint16_t)0x4000)

Select loop-back mode

Definition at line 201 of file stm32f7xx_hal_conf.h.

#define PHY_MICR ((uint16_t)0x11)

MII Interrupt Control Register

Definition at line 218 of file stm32f7xx_hal_conf.h.

#define PHY_MICR_INT_EN ((uint16_t)0x0002)

PHY Enable interrupts

Definition at line 225 of file stm32f7xx_hal_conf.h.

#define PHY_MICR_INT_OE ((uint16_t)0x0001)

PHY Enable output interrupt events

Definition at line 226 of file stm32f7xx_hal_conf.h.

#define PHY_MISR ((uint16_t)0x12)

MII Interrupt Status and Misc. Control Register

Definition at line 219 of file stm32f7xx_hal_conf.h.

#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020)

Enable Interrupt on change of link status

Definition at line 228 of file stm32f7xx_hal_conf.h.

#define PHY_POWERDOWN ((uint16_t)0x0800)

Select the power down mode

Definition at line 208 of file stm32f7xx_hal_conf.h.

#define PHY_READ_TO ((uint32_t)0x0000FFFF)

Definition at line 192 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_ReadPHYRegister().

#define PHY_RESET ((uint16_t)0x8000)

PHY Reset

Definition at line 200 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_RESET_DELAY ((uint32_t)0x000000FF)

Definition at line 188 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)

Restart auto-negotiation function

Definition at line 207 of file stm32f7xx_hal_conf.h.

#define PHY_SPEED_STATUS ((uint16_t)0x0002)

PHY Speed mask

Definition at line 222 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_SR ((uint16_t)0x10)

PHY status register Offset

Definition at line 217 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_Init().

#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)

Definition at line 193 of file stm32f7xx_hal_conf.h.

Referenced by HAL_ETH_WritePHYRegister().

#define PREFETCH_ENABLE 1

Definition at line 155 of file stm32f7xx_hal_conf.h.

#define TICK_INT_PRIORITY ((uint32_t)0x0F)

tick interrupt priority

Definition at line 153 of file stm32f7xx_hal_conf.h.

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

#define USE_RTOS 0

Definition at line 154 of file stm32f7xx_hal_conf.h.

#define VDD_VALUE ((uint32_t)3300)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 152 of file stm32f7xx_hal_conf.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp.c File Reference

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stm32f7xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
         (##) The encryption/decryption key. It's size depends on the algorithm
              used for encryption/decryption
         (##) The initialization vector (counter). It is not used ECB mode.

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_AESCBC_Encrypt()
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is initialized and processes the buffer in input.
         At second call, the processing function performs an append of the already
         processed buffer.
         When a new data block is to be processed, call HAL_CRYP_Init() then the
         processing function.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cryp.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp.h File Reference

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stm32f7xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cryp.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp_ex.c File Reference

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stm32f7xx_hal_cryp_ex.c File Reference

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Detailed Description

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The CRYP Extension HAL driver can be used as follows:
    (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
        (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
        (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
            (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
        (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++) Configure and enable two DMA streams one for managing data transfer from
                memory to peripheral (input stream) and another stream for managing data
                transfer from peripheral to memory (output stream)
            (+++) Associate the initialized DMA handle to the CRYP DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the two DMA Streams. The output stream should have higher
                priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
    (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
        (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
        (##) The encryption/decryption key. Its size depends on the algorithm
                used for encryption/decryption
        (##) The initialization vector (counter). It is not used ECB mode.
    (#)Three processing (encryption/decryption) functions are available:
        (##) Polling mode: encryption and decryption APIs are blocking functions
             i.e. they process the data and wait till the processing is finished
             e.g. HAL_CRYPEx_AESGCM_Encrypt()
        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
                i.e. they process the data under interrupt
                e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
        (##) DMA mode: encryption and decryption APIs are not blocking functions
                i.e. the data transfer is ensured by DMA
                e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
    (#)When the processing function is called at first time after HAL_CRYP_Init()
       the CRYP peripheral is initialized and processes the buffer in input.
       At second call, the processing function performs an append of the already
       processed buffer.
       When a new data block is to be processed, call HAL_CRYP_Init() then the
       processing function.
    (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
       which provide authentication messages.
       HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
       authentication messages.
       Call those functions after the processing ones (polling, interrupt or DMA).
       e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
            then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
    -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
    -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
        (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
    (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cryp_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp_ex.h File Reference

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stm32f7xx_hal_cryp_ex.h File Reference

Header file of CRYP HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of CRYP HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cryp_ex.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash.c File Reference

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stm32f7xx_hal_hash.c File Reference

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Detailed Description

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The HASH HAL driver can be used as follows:
    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++) Configure and enable one DMA stream one for managing data transfer from
                memory to peripheral (input stream). Managing data transfer from
                peripheral to memory can be performed only using CPU
            (+++) Associate the initialized DMA handle to the HASH DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
        (##) For HMAC, the encryption key.
        (##) For HMAC, the key size used for encryption.
    (#)Three processing functions are available:
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished
             e.g. HAL_HASH_SHA1_Start()
        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
                i.e. they process the data under interrupt
                e.g. HAL_HASH_SHA1_Start_IT()
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA
                e.g. HAL_HASH_SHA1_Start_DMA()
    (#)When the processing function is called at first time after HAL_HASH_Init()
       the HASH peripheral is initialized and processes the buffer in input.
       After that, the digest computation is started.
       When processing multi-buffer use the accumulate function to write the
       data in the peripheral without starting the digest computation. In last
       buffer use the start function to input the last buffer ans start the digest
       computation.
       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
       (##) write (n-1)th data buffer in the peripheral without starting the digest computation
       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
       After that, call the finish function in order to get the digest value
       e.g. HAL_HASH_SHA1_Finish()
    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_hash.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash.h File Reference

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stm32f7xx_hal_hash.h File Reference

Header file of HASH HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of HASH HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_hash.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash_ex.c File Reference

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stm32f7xx_hal_hash_ex.c File Reference

HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Detailed Description

HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The HASH HAL driver can be used as follows:
    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
        (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++) Configure and enable one DMA stream one for managing data transfer from
                memory to peripheral (input stream). Managing data transfer from
                peripheral to memory can be performed only using CPU
            (+++) Associate the initialized DMA handle to the HASH DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
        (##) For HMAC, the encryption key.
        (##) For HMAC, the key size used for encryption.
    (#)Three processing functions are available:
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished
             e.g. HAL_HASHEx_SHA224_Start()
        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
                i.e. they process the data under interrupt
                e.g. HAL_HASHEx_SHA224_Start_IT()
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA
                e.g. HAL_HASHEx_SHA224_Start_DMA()
    (#)When the processing function is called at first time after HAL_HASH_Init()
       the HASH peripheral is initialized and processes the buffer in input.
       After that, the digest computation is started.
       When processing multi-buffer use the accumulate function to write the
       data in the peripheral without starting the digest computation. In last
       buffer use the start function to input the last buffer ans start the digest
       computation.
       (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
       (##)  write (n-1)th data buffer in the peripheral without starting the digest computation
       (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
       After that, call the finish function in order to get the digest value
       e.g. HAL_HASHEx_SHA224_Finish()
    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_hash_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash_ex.h File Reference

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stm32f7xx_hal_hash_ex.h File Reference

Header file of HASH HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of HASH HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_hash_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_ltdc.c File Reference

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stm32f7xx_hal_ltdc.c File Reference

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Detailed Description

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Program the required configuration through the following parameters:
         the LTDC timing, the horizontal and vertical polarity,
         the pixel clock polarity, Data Enable polarity and the LTDC background color value
         using HAL_LTDC_Init() function

     (#) Program the required configuration through the following parameters:
         the pixel format, the blending factors, input alpha value, the window size
         and the image size using HAL_LTDC_ConfigLayer() function for foreground
         or/and background layer.

     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
         HAL_LTDC_EnableCLUT functions.

     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().

     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
         and HAL_LTDC_EnableColorKeying functions.

     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
         function

     (#) If needed, reconfigure and change the pixel format value, the alpha value
         value, the window size, the window position and the layer start address
         for foreground or/and background layer using respectively the following
         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
         HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.

     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()

     *** LTDC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in LTDC HAL driver.

      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
      (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.
      (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
      (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.
      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.

     [..]
       (@) You can refer to the LTDC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_ltdc.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_ltdc.h File Reference

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stm32f7xx_hal_ltdc.h File Reference

Header file of LTDC HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of LTDC HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_ltdc.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __HAL_ADC_CLEAR_FLAG : stm32f7xx_hal_adc.h
  • __HAL_ADC_DISABLE : stm32f7xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32f7xx_hal_adc.h
  • __HAL_ADC_ENABLE : stm32f7xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32f7xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32f7xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f7xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f7xx_hal_adc.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32f7xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32f7xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32f7xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32f7xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32f7xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32f7xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32f7xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32f7xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32f7xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32f7xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32f7xx_hal_can.h
  • __HAL_CEC_CLEAR_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32f7xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32f7xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32f7xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32f7xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32f7xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32f7xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32f7xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32f7xx_hal_cec.h
  • __HAL_CRC_DR_RESET : stm32f7xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f7xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32f7xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32f7xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32f7xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32f7xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f7xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f7xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32f7xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32f7xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32f7xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32f7xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32f7xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32f7xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32f7xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32f7xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_CAN2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM10 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM11 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM9 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM10 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM11 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM12 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM13 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM9 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f7xx_hal.h
  • __HAL_DCMI_CLEAR_FLAG : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE_IT : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE_IT : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_GET_FLAG : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_GET_IT_SOURCE : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_RESET_HANDLE_STATE : stm32f7xx_hal_dcmi.h
  • __HAL_DMA2D_CLEAR_FLAG : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_DISABLE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_DISABLE_IT : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE_IT : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_FLAG : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_IT_SOURCE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_RESET_HANDLE_STATE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA_CLEAR_FLAG : stm32f7xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32f7xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f7xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f7xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f7xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32f7xx_hal_dma.h
  • __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_CLEAR_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_CLEAR_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_SET_OWN_BIT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_CRC_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_CRC_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_SET_OWN_BIT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_GET_DMA_OVERFLOW_STATUS : stm32f7xx_hal_eth.h
  • __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS : stm32f7xx_hal_eth.h
  • __HAL_ETH_GET_PMT_FLAG_STATUS : stm32f7xx_hal_eth.h
  • __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAC_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAC_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAC_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_FULL_PRESET : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_HALF_PRESET : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTERS_RESET : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_RX_IT_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_RX_IT_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_TX_IT_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_TX_IT_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_POWER_DOWN_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_POWER_DOWN_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_RESET_HANDLE_STATE : stm32f7xx_hal_eth.h
  • __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_FLASH_ART_DISABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_ART_ENABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_ART_RESET : stm32f7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32f7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32f7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32f7xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32f7xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f7xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f7xx_hal_gpio.h
  • __HAL_HCD_CLEAR_FLAG : stm32f7xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32f7xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32f7xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32f7xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_I2C_CLEAR_FLAG : stm32f7xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f7xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f7xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f7xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f7xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f7xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f7xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f7xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32f7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32f7xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32f7xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32f7xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32f7xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32f7xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32f7xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32f7xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32f7xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f7xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32f7xx_hal_irda.h
  • __HAL_IWDG_GET_FLAG : stm32f7xx_hal_iwdg.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f7xx_hal_iwdg.h
  • __HAL_IWDG_RESET_HANDLE_STATE : stm32f7xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f7xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_StateTypeDef : stm32f7xx_hal_lptim.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32f7xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32f7xx_hal_nor.h
  • __HAL_PCD_CLEAR_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32f7xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32f7xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32f7xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32f7xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32f7xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32f7xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_CLEAR_ODRUDR_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_CLEAR_WAKEUP_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_GET_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_GET_ODRUDR_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_GET_WAKEUP_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVE_DISABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVE_ENABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVESWITCHING_DISABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVESWITCHING_ENABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_UNDERDRIVE_DISABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_UNDERDRIVE_ENABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32f7xx_hal_pwr.h
  • __HAL_QSPI_CLEAR_FLAG : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32f7xx_hal_qspi.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_AXI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AXI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_BKPSRAM_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CLEAR_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CLK48_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DAC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ENABLE_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_ETH_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETH_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETH_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETH_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CLK48_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C4_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2SCLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART7_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART8_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART6_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f7xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2S_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_MCO2_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLI2S_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_CLEAR_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_DISABLE_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_ENABLE_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_GET_FLAG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_GET_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32f7xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_TIM10_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32f7xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32f7xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32f7xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32f7xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32f7xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f7xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32f7xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32f7xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32f7xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32f7xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32f7xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32f7xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32f7xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32f7xx_hal_sai.h
  • __HAL_SD_SDMMC_CLEAR_FLAG : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_CLEAR_IT : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DISABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DISABLE_IT : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DMA_DISABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DMA_ENABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_ENABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_ENABLE_IT : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_GET_FLAG : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_GET_IT : stm32f7xx_hal_sd.h
  • __HAL_SDRAM_RESET_HANDLE_STATE : stm32f7xx_hal_sdram.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_DISABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_ENABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32f7xx_hal_smartcard.h
  • __HAL_SPDIFRX_CLEAR_IT : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_DISABLE_IT : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_ENABLE_IT : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_FLAG : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_IT_SOURCE : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_IDLE : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RCV : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RESET_HANDLE_STATE : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_SYNC : stm32f7xx_hal_spdifrx.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f7xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f7xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f7xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f7xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f7xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f7xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32f7xx_hal_sram.h
  • __HAL_SYSCFG_REMAPMEMORY_FMC : stm32f7xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM : stm32f7xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32f7xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f7xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f7xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f7xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f7xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f7xx_hal_tim_ex.h
  • __HAL_TIM_GET_COUNTER : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f7xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f7xx_hal_tim_ex.h
  • __HAL_TIM_SET_COUNTER : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f7xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f7xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f7xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f7xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32f7xx_hal_uart.h
  • __HAL_USART_CLEAR_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f7xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f7xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f7xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f7xx_hal_usart.h
  • __HAL_USART_MASK_COMPUTATION : stm32f7xx_hal_usart_ex.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f7xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32f7xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_RESET_HANDLE_STATE : stm32f7xx_hal_wwdg.h
  • __STM32F7xx_HAL_VERSION : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_MAIN : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_RC : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_SUB1 : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_SUB2 : stm32f7xx_hal.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC_ALL_CHANNELS : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f7xx_hal_adc.h
  • ADC_AWD_EVENT : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_0 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_1 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_11 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_12 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_13 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_14 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_15 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_16 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_17 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_18 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_2 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_3 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_4 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_5 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_6 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_7 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_8 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_9 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f7xx_hal_adc_ex.h
  • ADC_CHANNEL_VBAT : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32f7xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV6 : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV8 : stm32f7xx_hal_adc.h
  • ADC_CR1_DISCONTINUOUS : stm32f7xx_hal_adc.h
  • ADC_CR1_SCANCONV : stm32f7xx_hal_adc.h
  • ADC_CR2_CONTINUOUS : stm32f7xx_hal_adc.h
  • ADC_CR2_DMAContReq : stm32f7xx_hal_adc.h
  • ADC_CR2_EOCSelection : stm32f7xx_hal_adc.h
  • ADC_DATAALIGN_LEFT : stm32f7xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32f7xx_hal_adc.h
  • ADC_DMAACCESSMODE_1 : stm32f7xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_2 : stm32f7xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_3 : stm32f7xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32f7xx_hal_adc_ex.h
  • ADC_DMAConvCplt() : stm32f7xx_hal_adc.c
  • ADC_DMAError() : stm32f7xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32f7xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32f7xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32f7xx_hal_adc.h
  • ADC_EOC_SINGLE_SEQ_CONV : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_EXT_IT11 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC1 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC3 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_TRGO2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T3_CC4 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T4_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T6_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_TRGO2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGINJECCONV_T1_CC4 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC1 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC3 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T5_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T6_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC4 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_FALLING : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_NONE : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISING : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING : stm32f7xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f7xx_hal_adc.h
  • ADC_FLAG_EOC : stm32f7xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32f7xx_hal_adc.h
  • ADC_FLAG_JSTRT : stm32f7xx_hal_adc.h
  • ADC_FLAG_OVR : stm32f7xx_hal_adc.h
  • ADC_FLAG_STRT : stm32f7xx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32f7xx_hal_adc.h
  • ADC_Init() : stm32f7xx_hal_adc.c
  • ADC_INJECTED_CHANNELS : stm32f7xx_hal_adc.h
  • ADC_INJECTED_RANK_1 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f7xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f7xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f7xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f7xx_hal_adc.h
  • ADC_IT_AWD : stm32f7xx_hal_adc.h
  • ADC_IT_EOC : stm32f7xx_hal_adc.h
  • ADC_IT_JEOC : stm32f7xx_hal_adc.h
  • ADC_IT_OVR : stm32f7xx_hal_adc.h
  • ADC_JSQR : stm32f7xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32f7xx_hal_adc_ex.h
  • ADC_MultiModeDMAConvCplt() : stm32f7xx_hal_adc_ex.c
  • ADC_MultiModeDMAError() : stm32f7xx_hal_adc_ex.c
  • ADC_MultiModeDMAHalfConvCplt() : stm32f7xx_hal_adc_ex.c
  • ADC_OVR_EVENT : stm32f7xx_hal_adc.h
  • ADC_REGULAR_CHANNELS : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_112CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_144CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_15CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_480CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_56CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_84CYCLES : stm32f7xx_hal_adc.h
  • ADC_SMPR1 : stm32f7xx_hal_adc.h
  • ADC_SMPR2 : stm32f7xx_hal_adc.h
  • ADC_SOFTWARE_START : stm32f7xx_hal_adc.h
  • ADC_SQR1 : stm32f7xx_hal_adc.h
  • ADC_SQR1_RK : stm32f7xx_hal_adc.h
  • ADC_SQR2_RK : stm32f7xx_hal_adc.h
  • ADC_SQR3_RK : stm32f7xx_hal_adc.h
  • ADC_STAB_DELAY_US : stm32f7xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32f7xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f7xx_hal_adc.h
  • ADC_TRIPLEMODE_ALTERTRIG : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INTERL : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_AlterTrig : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_13CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_14CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_15CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_16CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_17CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_18CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_19CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_20CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32f7xx_hal_adc.h
  • ADDR_1ST_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_AREA : stm32f7xx_hal_nand.h
  • APBAHBPrescTable : stm32f7xx_hal_rcc.c
  • ARRAY_ADDRESS : stm32f7xx_hal_nand.h
  • ART_ACCLERATOR_ENABLE : stm32f7xx_hal_conf.h
  • assert_param : stm32f7xx_hal_conf.h
  • AUTONEGO_COMPLETED_TIMEOUT_VALUE : stm32f7xx_hal_eth.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
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  • l
  • m
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDTR_BK2F_SHIFT : stm32f7xx_hal_tim_ex.c
  • BDTR_BKF_SHIFT : stm32f7xx_hal_tim_ex.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN_BS1_10TQ : stm32f7xx_hal_can.h
  • CAN_BS1_11TQ : stm32f7xx_hal_can.h
  • CAN_BS1_12TQ : stm32f7xx_hal_can.h
  • CAN_BS1_13TQ : stm32f7xx_hal_can.h
  • CAN_BS1_14TQ : stm32f7xx_hal_can.h
  • CAN_BS1_15TQ : stm32f7xx_hal_can.h
  • CAN_BS1_16TQ : stm32f7xx_hal_can.h
  • CAN_BS1_1TQ : stm32f7xx_hal_can.h
  • CAN_BS1_2TQ : stm32f7xx_hal_can.h
  • CAN_BS1_3TQ : stm32f7xx_hal_can.h
  • CAN_BS1_4TQ : stm32f7xx_hal_can.h
  • CAN_BS1_5TQ : stm32f7xx_hal_can.h
  • CAN_BS1_6TQ : stm32f7xx_hal_can.h
  • CAN_BS1_7TQ : stm32f7xx_hal_can.h
  • CAN_BS1_8TQ : stm32f7xx_hal_can.h
  • CAN_BS1_9TQ : stm32f7xx_hal_can.h
  • CAN_BS2_1TQ : stm32f7xx_hal_can.h
  • CAN_BS2_2TQ : stm32f7xx_hal_can.h
  • CAN_BS2_3TQ : stm32f7xx_hal_can.h
  • CAN_BS2_4TQ : stm32f7xx_hal_can.h
  • CAN_BS2_5TQ : stm32f7xx_hal_can.h
  • CAN_BS2_6TQ : stm32f7xx_hal_can.h
  • CAN_BS2_7TQ : stm32f7xx_hal_can.h
  • CAN_BS2_8TQ : stm32f7xx_hal_can.h
  • CAN_FIFO0 : stm32f7xx_hal_can.h
  • CAN_FIFO1 : stm32f7xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32f7xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32f7xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32f7xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32f7xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32f7xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32f7xx_hal_can.h
  • CAN_FLAG_BOF : stm32f7xx_hal_can.h
  • CAN_FLAG_EPV : stm32f7xx_hal_can.h
  • CAN_FLAG_EWG : stm32f7xx_hal_can.h
  • CAN_FLAG_FF0 : stm32f7xx_hal_can.h
  • CAN_FLAG_FF1 : stm32f7xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32f7xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32f7xx_hal_can.h
  • CAN_FLAG_MASK : stm32f7xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32f7xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32f7xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32f7xx_hal_can.h
  • CAN_FLAG_SLAK : stm32f7xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32f7xx_hal_can.h
  • CAN_FLAG_TME0 : stm32f7xx_hal_can.h
  • CAN_FLAG_TME1 : stm32f7xx_hal_can.h
  • CAN_FLAG_TME2 : stm32f7xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32f7xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32f7xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32f7xx_hal_can.h
  • CAN_FLAG_WKU : stm32f7xx_hal_can.h
  • CAN_ID_EXT : stm32f7xx_hal_can.h
  • CAN_ID_STD : stm32f7xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32f7xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32f7xx_hal_can.h
  • CAN_IT_BOF : stm32f7xx_hal_can.h
  • CAN_IT_EPV : stm32f7xx_hal_can.h
  • CAN_IT_ERR : stm32f7xx_hal_can.h
  • CAN_IT_EWG : stm32f7xx_hal_can.h
  • CAN_IT_FF0 : stm32f7xx_hal_can.h
  • CAN_IT_FF1 : stm32f7xx_hal_can.h
  • CAN_IT_FMP0 : stm32f7xx_hal_can.h
  • CAN_IT_FMP1 : stm32f7xx_hal_can.h
  • CAN_IT_FOV0 : stm32f7xx_hal_can.h
  • CAN_IT_FOV1 : stm32f7xx_hal_can.h
  • CAN_IT_LEC : stm32f7xx_hal_can.h
  • CAN_IT_SLK : stm32f7xx_hal_can.h
  • CAN_IT_TME : stm32f7xx_hal_can.h
  • CAN_IT_WKU : stm32f7xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32f7xx_hal_can.h
  • CAN_MODE_NORMAL : stm32f7xx_hal_can.h
  • CAN_MODE_SILENT : stm32f7xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32f7xx_hal_can.h
  • CAN_Receive_IT() : stm32f7xx_hal_can.c
  • CAN_RTR_DATA : stm32f7xx_hal_can.h
  • CAN_RTR_REMOTE : stm32f7xx_hal_can.h
  • CAN_SJW_1TQ : stm32f7xx_hal_can.h
  • CAN_SJW_2TQ : stm32f7xx_hal_can.h
  • CAN_SJW_3TQ : stm32f7xx_hal_can.h
  • CAN_SJW_4TQ : stm32f7xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32f7xx_hal_can.c
  • CAN_Transmit_IT() : stm32f7xx_hal_can.c
  • CAN_TXMAILBOX_0 : stm32f7xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32f7xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32f7xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32f7xx_hal_can.h
  • CEC_0_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32f7xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_CFGR_FIELDS : stm32f7xx_hal_cec.c
  • CEC_CFGR_OAR_LSB_POS : stm32f7xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32f7xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32f7xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32f7xx_hal_cec.h
  • CEC_FLAG_BRE : stm32f7xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32f7xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32f7xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32f7xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32f7xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32f7xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32f7xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32f7xx_hal_cec.h
  • CEC_IT_ARBLST : stm32f7xx_hal_cec.h
  • CEC_IT_BRE : stm32f7xx_hal_cec.h
  • CEC_IT_LBPE : stm32f7xx_hal_cec.h
  • CEC_IT_RXACKE : stm32f7xx_hal_cec.h
  • CEC_IT_RXBR : stm32f7xx_hal_cec.h
  • CEC_IT_RXEND : stm32f7xx_hal_cec.h
  • CEC_IT_RXOVR : stm32f7xx_hal_cec.h
  • CEC_IT_SBPE : stm32f7xx_hal_cec.h
  • CEC_IT_TXACKE : stm32f7xx_hal_cec.h
  • CEC_IT_TXBR : stm32f7xx_hal_cec.h
  • CEC_IT_TXEND : stm32f7xx_hal_cec.h
  • CEC_IT_TXERR : stm32f7xx_hal_cec.h
  • CEC_IT_TXUDR : stm32f7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32f7xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32f7xx_hal_cec.h
  • CEC_Receive_IT() : stm32f7xx_hal_cec.c
  • CEC_REDUCED_LISTENING_MODE : stm32f7xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32f7xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32f7xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32f7xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32f7xx_hal_cec.h
  • CEC_Transmit_IT() : stm32f7xx_hal_cec.c
  • CFI1_ADDRESS : stm32f7xx_hal_nor.h
  • CFI2_ADDRESS : stm32f7xx_hal_nor.h
  • CFI3_ADDRESS : stm32f7xx_hal_nor.h
  • CFI4_ADDRESS : stm32f7xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • CM_A4 : stm32f7xx_hal_dma2d.h
  • CM_A8 : stm32f7xx_hal_dma2d.h
  • CM_AL44 : stm32f7xx_hal_dma2d.h
  • CM_AL88 : stm32f7xx_hal_dma2d.h
  • CM_ARGB1555 : stm32f7xx_hal_dma2d.h
  • CM_ARGB4444 : stm32f7xx_hal_dma2d.h
  • CM_ARGB8888 : stm32f7xx_hal_dma2d.h
  • CM_L4 : stm32f7xx_hal_dma2d.h
  • CM_L8 : stm32f7xx_hal_dma2d.h
  • CM_RGB565 : stm32f7xx_hal_dma2d.h
  • CM_RGB888 : stm32f7xx_hal_dma2d.h
  • CMD_AREA : stm32f7xx_hal_nand.h
  • COLOR_VALUE : stm32f7xx_hal_dma2d.h
  • CR1_CLEAR_MASK : stm32f7xx_hal_sai.c
  • CR_PSIZE_MASK : stm32f7xx_hal_flash.h
  • CRC_Handle_16() : stm32f7xx_hal_crc.c
  • CRC_Handle_8() : stm32f7xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32f7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32f7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32f7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32f7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32f7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32f7xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32f7xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32f7xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32f7xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32f7xx_hal_crc.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32f7xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32f7xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32f7xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32f7xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32f7xx_hal_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32f7xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32f7xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32f7xx_hal_dac.h
  • DAC_DMAConvCpltCh1() : stm32f7xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • DAC_DMAErrorCh1() : stm32f7xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • DAC_DMAHalfConvCpltCh1() : stm32f7xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • DAC_FLAG_DMAUDR1 : stm32f7xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32f7xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32f7xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32f7xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32f7xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32f7xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32f7xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32f7xx_hal_dac.h
  • DATA_BLOCK_SIZE : stm32f7xx_hal_sd.c
  • DCMI_BSM_ALL : stm32f7xx_hal_dcmi_ex.h
  • DCMI_BSM_ALTERNATE_2 : stm32f7xx_hal_dcmi_ex.h
  • DCMI_BSM_ALTERNATE_4 : stm32f7xx_hal_dcmi_ex.h
  • DCMI_BSM_OTHER : stm32f7xx_hal_dcmi_ex.h
  • DCMI_CR_ALL_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_2_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_4_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_DMAConvCplt() : stm32f7xx_hal_dcmi.c
  • DCMI_DMAError() : stm32f7xx_hal_dcmi.c
  • DCMI_EXTEND_DATA_10B : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_12B : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_14B : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_8B : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_ERRMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_ERRRI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_FNE : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMEMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMERI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_HSYNC : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_LINEMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_LINERI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_OVFMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_OVFRI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNC : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCRI : stm32f7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_HIGH : stm32f7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_LOW : stm32f7xx_hal_dcmi.h
  • DCMI_IT_ERR : stm32f7xx_hal_dcmi.h
  • DCMI_IT_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_IT_LINE : stm32f7xx_hal_dcmi.h
  • DCMI_IT_OVF : stm32f7xx_hal_dcmi.h
  • DCMI_IT_VSYNC : stm32f7xx_hal_dcmi.h
  • DCMI_JPEG_DISABLE : stm32f7xx_hal_dcmi.h
  • DCMI_JPEG_ENABLE : stm32f7xx_hal_dcmi.h
  • DCMI_LSM_ALL : stm32f7xx_hal_dcmi_ex.h
  • DCMI_LSM_ALTERNATE_2 : stm32f7xx_hal_dcmi_ex.h
  • DCMI_MODE_CONTINUOUS : stm32f7xx_hal_dcmi.h
  • DCMI_MODE_SNAPSHOT : stm32f7xx_hal_dcmi.h
  • DCMI_OEBS_EVEN : stm32f7xx_hal_dcmi_ex.h
  • DCMI_OEBS_ODD : stm32f7xx_hal_dcmi_ex.h
  • DCMI_OELS_EVEN : stm32f7xx_hal_dcmi_ex.h
  • DCMI_OELS_ODD : stm32f7xx_hal_dcmi_ex.h
  • DCMI_PCKPOLARITY_FALLING : stm32f7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_RISING : stm32f7xx_hal_dcmi.h
  • DCMI_SYNCHRO_EMBEDDED : stm32f7xx_hal_dcmi.h
  • DCMI_SYNCHRO_HARDWARE : stm32f7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_HIGH : stm32f7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_LOW : stm32f7xx_hal_dcmi.h
  • DCMI_WINDOW_COORDINATE : stm32f7xx_hal_dcmi.h
  • DCMI_WINDOW_HEIGHT : stm32f7xx_hal_dcmi.h
  • DEFAULT_CRC32_POLY : stm32f7xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32f7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32f7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32f7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32f7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32f7xx_hal_crc.h
  • DEVICE_CODE1_ADDR : stm32f7xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32f7xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32f7xx_hal_nor.h
  • DMA2D_ARGB1555 : stm32f7xx_hal_dma2d.h
  • DMA2D_ARGB4444 : stm32f7xx_hal_dma2d.h
  • DMA2D_ARGB8888 : stm32f7xx_hal_dma2d.h
  • DMA2D_CCM_ARGB8888 : stm32f7xx_hal_dma2d.h
  • DMA2D_CCM_RGB888 : stm32f7xx_hal_dma2d.h
  • DMA2D_CLUT_SIZE : stm32f7xx_hal_dma2d.h
  • DMA2D_COMBINE_ALPHA : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_CAE : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_CE : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_CTC : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_TC : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_TE : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_TW : stm32f7xx_hal_dma2d.h
  • DMA2D_HandleTypeDef : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_CAE : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_CE : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_CTC : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_TC : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_TE : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_TW : stm32f7xx_hal_dma2d.h
  • DMA2D_LINE : stm32f7xx_hal_dma2d.h
  • DMA2D_M2M : stm32f7xx_hal_dma2d.h
  • DMA2D_M2M_BLEND : stm32f7xx_hal_dma2d.h
  • DMA2D_M2M_PFC : stm32f7xx_hal_dma2d.h
  • DMA2D_NO_MODIF_ALPHA : stm32f7xx_hal_dma2d.h
  • DMA2D_OFFSET : stm32f7xx_hal_dma2d.h
  • DMA2D_PIXEL : stm32f7xx_hal_dma2d.h
  • DMA2D_R2M : stm32f7xx_hal_dma2d.h
  • DMA2D_REPLACE_ALPHA : stm32f7xx_hal_dma2d.h
  • DMA2D_RGB565 : stm32f7xx_hal_dma2d.h
  • DMA2D_RGB888 : stm32f7xx_hal_dma2d.h
  • DMA2D_SetConfig() : stm32f7xx_hal_dma2d.c
  • DMA_CalcBaseAndBitshift() : stm32f7xx_hal_dma.c
  • DMA_CHANNEL_0 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_1 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_2 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_3 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_4 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_5 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_6 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_7 : stm32f7xx_hal_dma.h
  • DMA_CIRCULAR : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32f7xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32f7xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32f7xx_hal_dma.h
  • DMA_HandleTypeDef : stm32f7xx_hal_dma.h
  • DMA_IT_DME : stm32f7xx_hal_dma.h
  • DMA_IT_FE : stm32f7xx_hal_dma.h
  • DMA_IT_HT : stm32f7xx_hal_dma.h
  • DMA_IT_TC : stm32f7xx_hal_dma.h
  • DMA_IT_TE : stm32f7xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32f7xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32f7xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32f7xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32f7xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f7xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f7xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f7xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f7xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f7xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f7xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f7xx_hal_dma.h
  • DMA_MultiBufferSetConfig() : stm32f7xx_hal_dma_ex.c
  • DMA_NORMAL : stm32f7xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32f7xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32f7xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32f7xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32f7xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f7xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f7xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f7xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f7xx_hal_dma.h
  • DMA_PFCTRL : stm32f7xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f7xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f7xx_hal_dma.h
  • DMA_SetConfig() : stm32f7xx_hal_dma.c
  • DP83848_PHY_ADDRESS : stm32f7xx_hal_conf.h
  • DUMMY_DATA : stm32f7xx_hal_usart.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • ETH_ADDRESSALIGNEDBEATS_DISABLE : stm32f7xx_hal_eth.h
  • ETH_ADDRESSALIGNEDBEATS_ENABLE : stm32f7xx_hal_eth.h
  • ETH_AUTOMATICPADCRCSTRIP_DISABLE : stm32f7xx_hal_eth.h
  • ETH_AUTOMATICPADCRCSTRIP_ENABLE : stm32f7xx_hal_eth.h
  • ETH_AUTONEGOTIATION_DISABLE : stm32f7xx_hal_eth.h
  • ETH_AUTONEGOTIATION_ENABLE : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_1 : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_10 : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_4 : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_8 : stm32f7xx_hal_eth.h
  • ETH_BROADCASTFRAMESRECEPTION_DISABLE : stm32f7xx_hal_eth.h
  • ETH_BROADCASTFRAMESRECEPTION_ENABLE : stm32f7xx_hal_eth.h
  • ETH_CARRIERSENCE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_CARRIERSENCE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUM_BY_HARDWARE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUM_BY_SOFTWARE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUMOFFLAOD_DISABLE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUMOFFLAOD_ENABLE : stm32f7xx_hal_eth.h
  • ETH_CRC : stm32f7xx_hal_eth.h
  • ETH_DEFFERRALCHECK_DISABLE : stm32f7xx_hal_eth.h
  • ETH_DEFFERRALCHECK_ENABLE : stm32f7xx_hal_eth.h
  • ETH_DESTINATIONADDRFILTER_INVERSE : stm32f7xx_hal_eth.h
  • ETH_DESTINATIONADDRFILTER_NORMAL : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_ACCESSERROR : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_AIS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_DATATRANSFERERROR : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_ER : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_ET : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_FBE : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_MMC : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_NIS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_PMT : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_R : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RBU : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_READWRITEERROR : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RO : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RPS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RWT : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_T : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TBU : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TJT : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TPS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TST : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TU : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_AIS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_ER : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_ET : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_FBE : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_MMC : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_NIS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_PMT : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_R : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RBU : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RO : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RPS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RWT : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_T : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TBU : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TJT : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TPS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TST : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TU : stm32f7xx_hal_eth.h
  • ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : stm32f7xx_hal_eth.h
  • ETH_DMA_OVERFLOW_RXFIFOCOUNTER : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_CLOSING : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_FETCHING : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_QUEUING : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_STOPPED : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_SUSPENDED : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_WAITING : stm32f7xx_hal_eth.h
  • ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_CLOSING : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_FETCHING : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_READING : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_STOPPED : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_SUSPENDED : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_WAITING : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_RXPRIORTX : stm32f7xx_hal_eth.h
  • ETH_DMAENHANCEDDESCRIPTOR_DISABLE : stm32f7xx_hal_eth.h
  • ETH_DMAENHANCEDDESCRIPTOR_ENABLE : stm32f7xx_hal_eth.h
  • ETH_DMAOMR_CLEAR_MASK : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPCB : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPHE : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPE : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT_ICMP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT_TCP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT_UDP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPV4PR : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPV6PR : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPFT : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_DELAYREQ : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_DELAYRESP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_SYNC : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPV : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_RTSH : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_RTSL : stm32f7xx_hal_eth.h
  • ETH_DMAPTPTXDESC_TTSH : stm32f7xx_hal_eth.h
  • ETH_DMAPTPTXDESC_TTSL : stm32f7xx_hal_eth.h
  • ETH_DMAReceptionDisable() : stm32f7xx_hal_eth.c
  • ETH_DMAReceptionEnable() : stm32f7xx_hal_eth.c
  • ETH_DMARXDESC_AFM : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_B1AP : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_B2AP : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_BUFFER1 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_BUFFER2 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_BUFFER2_SIZESHIFT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_CE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_DBE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_DE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_DIC : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_ES : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FL : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FRAME_LENGTHSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FRAMELENGTHSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FS : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_IPV4HCE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_LC : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_LE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_LS : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_MAMPCE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_OE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_OWN : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RBS1 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RBS2 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RCH : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RER : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RWT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_SAF : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_VLAN : stm32f7xx_hal_eth.h
  • ETH_DMATransmissionDisable() : stm32f7xx_hal_eth.c
  • ETH_DMATransmissionEnable() : stm32f7xx_hal_eth.c
  • ETH_DMATXDESC_B1AP : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_B2AP : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_BUFFER2_SIZESHIFT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMBYPASS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMIPV4HEADER : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_BYPASS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_IPV4HEADER : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_TCPUDPICMP_FULL : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_COLLISION_COUNTSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_DB : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_DC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_DP : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_EC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_ED : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_ES : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_FF : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_FIRSTSEGMENT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_FS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_IC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_IHE : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_JT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LASTSEGMENTS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LCA : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LCO : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_NC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_OWN : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_PCE : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TBS1 : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TBS2 : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TCH : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TER : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TTSE : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TTSS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_UF : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_VF : stm32f7xx_hal_eth.h
  • ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE : stm32f7xx_hal_eth.h
  • ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE : stm32f7xx_hal_eth.h
  • ETH_ERROR : stm32f7xx_hal_eth.h
  • ETH_EXTI_LINE_WAKEUP : stm32f7xx_hal_eth.h
  • ETH_EXTRA : stm32f7xx_hal_eth.h
  • ETH_FIXEDBURST_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FIXEDBURST_ENABLE : stm32f7xx_hal_eth.h
  • ETH_FLUSHRECEIVEDFRAME_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FLUSHRECEIVEDFRAME_ENABLE : stm32f7xx_hal_eth.h
  • ETH_FlushTransmitFIFO() : stm32f7xx_hal_eth.c
  • ETH_FORWARDERRORFRAMES_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDERRORFRAMES_ENABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE : stm32f7xx_hal_eth.h
  • ETH_HEADER : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_40BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_48BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_56BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_64BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_72BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_80BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_88BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_96BIT : stm32f7xx_hal_eth.h
  • ETH_JABBER_DISABLE : stm32f7xx_hal_eth.h
  • ETH_JABBER_ENABLE : stm32f7xx_hal_eth.h
  • ETH_JUMBO_FRAME_PAYLOAD : stm32f7xx_hal_eth.h
  • ETH_LOOPBACKMODE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_LOOPBACKMODE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDR_HBASE : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDR_LBASE : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS0 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS1 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS2 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS3 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSFILTER_DA : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSFILTER_SA : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE1 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE2 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE3 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE4 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE5 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE6 : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_MMC : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_MMCR : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_MMCT : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_PMT : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_TST : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_MMC : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_MMCR : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_MMCT : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_PMT : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_TST : stm32f7xx_hal_eth.h
  • ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_MII_TRANSMIT_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_FLUSHING : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_IDLE : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_READING_DATA : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_READING_STATUS : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_ABOVE_THRESHOLD : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_BELOW_THRESHOLD : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_EMPTY : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_FULL : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_WRITE_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_NOTACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_READ_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_RW_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_WRITE_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMISSION_PAUSE : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_FULL : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_IDLE : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_READ : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_WAITING : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_WRITE_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_WRITING : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFONOT_EMPTY : stm32f7xx_hal_eth.h
  • ETH_MACAddressConfig() : stm32f7xx_hal_eth.c
  • ETH_MACCR_CLEAR_MASK : stm32f7xx_hal_eth.h
  • ETH_MACDMAConfig() : stm32f7xx_hal_eth.c
  • ETH_MACFCR_CLEAR_MASK : stm32f7xx_hal_eth.h
  • ETH_MACMIIAR_CR_MASK : stm32f7xx_hal_eth.h
  • ETH_MACReceptionDisable() : stm32f7xx_hal_eth.c
  • ETH_MACReceptionEnable() : stm32f7xx_hal_eth.c
  • ETH_MACTransmissionDisable() : stm32f7xx_hal_eth.c
  • ETH_MACTransmissionEnable() : stm32f7xx_hal_eth.c
  • ETH_MAX_ETH_PAYLOAD : stm32f7xx_hal_eth.h
  • ETH_MAX_PACKET_SIZE : stm32f7xx_hal_eth.h
  • ETH_MEDIA_INTERFACE_MII : stm32f7xx_hal_eth.h
  • ETH_MEDIA_INTERFACE_RMII : stm32f7xx_hal_eth.h
  • ETH_MIN_ETH_PAYLOAD : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_RFAE : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_RFCE : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_RGUF : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_TGF : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_TGFMSC : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_TGFSC : stm32f7xx_hal_eth.h
  • ETH_MODE_FULLDUPLEX : stm32f7xx_hal_eth.h
  • ETH_MODE_HALFDUPLEX : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_HASHTABLE : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_NONE : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_PERFECT : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE : stm32f7xx_hal_eth.h
  • ETH_PASSCONTROLFRAMES_BLOCKALL : stm32f7xx_hal_eth.h
  • ETH_PASSCONTROLFRAMES_FORWARDALL : stm32f7xx_hal_eth.h
  • ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS144 : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS256 : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS28 : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS4 : stm32f7xx_hal_eth.h
  • ETH_PMT_FLAG_MPR : stm32f7xx_hal_eth.h
  • ETH_PMT_FLAG_WUFFRPR : stm32f7xx_hal_eth.h
  • ETH_PMT_FLAG_WUFR : stm32f7xx_hal_eth.h
  • ETH_PROMISCUOUS_MODE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_PROMISCUOUS_MODE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEAll_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEALL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEFLOWCONTROL_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEFLOWCONTROL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEOWN_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEOWN_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVESTOREFORWARD_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVESTOREFORWARD_ENABLE : stm32f7xx_hal_eth.h
  • ETH_REG_WRITE_DELAY : stm32f7xx_hal_eth.h
  • ETH_RETRYTRANSMISSION_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RETRYTRANSMISSION_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RX_BUF_SIZE : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_RXBUFNB : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_RXDMABURSTLENGTH_16BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_1BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_2BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_32BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_128BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_16BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_32BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_4BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_64BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_8BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_8BEAT : stm32f7xx_hal_eth.h
  • ETH_RXINTERRUPT_MODE : stm32f7xx_hal_eth.h
  • ETH_RXPOLLING_MODE : stm32f7xx_hal_eth.h
  • ETH_SECONDFRAMEOPERARTE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_SECONDFRAMEOPERARTE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_SOURCEADDRFILTER_DISABLE : stm32f7xx_hal_eth.h
  • ETH_SOURCEADDRFILTER_INVERSE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_SOURCEADDRFILTER_NORMAL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_SPEED_100M : stm32f7xx_hal_eth.h
  • ETH_SPEED_10M : stm32f7xx_hal_eth.h
  • ETH_SUCCESS : stm32f7xx_hal_eth.h
  • ETH_TRANSMITFLOWCONTROL_DISABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITFLOWCONTROL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITSTOREFORWARD_DISABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITSTOREFORWARD_ENABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_128BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_16BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_192BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_24BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_256BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_32BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_40BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_64BYTES : stm32f7xx_hal_eth.h
  • ETH_TX_BUF_SIZE : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_TXBUFNB : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_TXDMABURSTLENGTH_16BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_1BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_2BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_32BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_128BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_16BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_32BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_4BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_64BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_8BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_8BEAT : stm32f7xx_hal_eth.h
  • ETH_UNICASTFRAMESFILTER_HASHTABLE : stm32f7xx_hal_eth.h
  • ETH_UNICASTFRAMESFILTER_PERFECT : stm32f7xx_hal_eth.h
  • ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE : stm32f7xx_hal_eth.h
  • ETH_UNICASTPAUSEFRAMEDETECT_DISABLE : stm32f7xx_hal_eth.h
  • ETH_UNICASTPAUSEFRAMEDETECT_ENABLE : stm32f7xx_hal_eth.h
  • ETH_VLAN_TAG : stm32f7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_12BIT : stm32f7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_16BIT : stm32f7xx_hal_eth.h
  • ETH_WAKEUP_REGISTER_LENGTH : stm32f7xx_hal_eth.h
  • ETH_WATCHDOG_DISABLE : stm32f7xx_hal_eth.h
  • ETH_WATCHDOG_ENABLE : stm32f7xx_hal_eth.h
  • ETH_ZEROQUANTAPAUSE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_ZEROQUANTAPAUSE_ENABLE : stm32f7xx_hal_eth.h
  • EXTERNAL_CLOCK_VALUE : stm32f7xx_hal_conf.h
  • EXTI_MODE : stm32f7xx_hal_gpio.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32f7xx_hal_gpio.c
  • FLASH_Erase_Sector() : stm32f7xx_hal_flash_ex.c , stm32f7xx_hal_flash_ex.h
  • FLASH_FLAG_BSY : stm32f7xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32f7xx_hal_flash.h
  • FLASH_FLAG_ERSERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_PGPERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32f7xx_hal_flash.h
  • FLASH_IT_EOP : stm32f7xx_hal_flash.h
  • FLASH_IT_ERR : stm32f7xx_hal_flash.h
  • FLASH_KEY1 : stm32f7xx_hal_flash.h
  • FLASH_KEY2 : stm32f7xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_10 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_11 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_12 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_13 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_14 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_15 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_8 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_9 : stm32f7xx_hal_flash_ex.h
  • FLASH_MassErase() : stm32f7xx_hal_flash_ex.c
  • FLASH_MER_BIT : stm32f7xx_hal_flash_ex.h
  • FLASH_OB_BootAddressConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetBootAddress() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OPT_KEY1 : stm32f7xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32f7xx_hal_flash.h
  • FLASH_PROC_MASSERASE : stm32f7xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f7xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32f7xx_hal_flash.h
  • FLASH_PROC_SECTERASE : stm32f7xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32f7xx_hal_flash.h
  • FLASH_Program_Byte() : stm32f7xx_hal_flash.c
  • FLASH_Program_DoubleWord() : stm32f7xx_hal_flash.c
  • FLASH_Program_HalfWord() : stm32f7xx_hal_flash.c
  • FLASH_Program_Word() : stm32f7xx_hal_flash.c
  • FLASH_PSIZE_BYTE : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_DOUBLE_WORD : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_HALF_WORD : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_WORD : stm32f7xx_hal_flash.h
  • FLASH_SECTOR_0 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_1 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_2 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_3 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_4 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_5 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_6 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_7 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_TOTAL : stm32f7xx_hal_flash_ex.h
  • FLASH_SetErrorCode() : stm32f7xx_hal_flash.c
  • FLASH_TIMEOUT_VALUE : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c
  • FLASH_TYPEERASE_MASSERASE : stm32f7xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32f7xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_BYTE : stm32f7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f7xx_hal_flash.h
  • FLASH_VOLTAGE_RANGE_1 : stm32f7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_2 : stm32f7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_3 : stm32f7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_4 : stm32f7xx_hal_flash_ex.h
  • FLASH_WaitForLastOperation() : stm32f7xx_hal_flash_ex.c , stm32f7xx_hal_flash.c , stm32f7xx_hal_flash.h
  • FRCR_CLEAR_MASK : stm32f7xx_hal_sai.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_MCO : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG_FS : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG_HS : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF11_ETH : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF12_OTG_HS_FS : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF12_SDMMC1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF13_DCMI : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_CEC : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM10 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM11 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM9 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_CEC : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI6 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_SPDIFRX : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_UART5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_SPDIFRX : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART7 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART8 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_USART6 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_CAN1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_CAN2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_QUADSPI : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM12 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32f7xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32f7xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f7xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32f7xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f7xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f7xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f7xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f7xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f7xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f7xx_hal_gpio.h
  • GPIO_NOPULL : stm32f7xx_hal_gpio.h
  • GPIO_NUMBER : stm32f7xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f7xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_All : stm32f7xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f7xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32f7xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f7xx_hal_gpio.h
  • GPIO_PinState : stm32f7xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f7xx_hal_gpio.h
  • GPIO_PULLUP : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32f7xx_hal_gpio.h
  • GPIOA_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOB_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOC_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOD_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOE_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOF_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOG_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOH_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOI_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOJ_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOK_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f7xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32f7xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f7xx_hal_adc.c
  • HAL_ADC_ERROR_DMA : stm32f7xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32f7xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32f7xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32f7xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f7xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f7xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f7xx_hal_adc.c
  • HAL_ADC_Init() : stm32f7xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32f7xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32f7xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f7xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f7xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32f7xx_hal_adc.c
  • HAL_ADC_Start() : stm32f7xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f7xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32f7xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f7xx_hal_adc.h
  • HAL_ADC_Stop() : stm32f7xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f7xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32f7xx_hal_adc.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32f7xx_hal_adc_ex.c
  • HAL_CAN_ConfigFilter() : stm32f7xx_hal_can.c
  • HAL_CAN_DeInit() : stm32f7xx_hal_can.c
  • HAL_CAN_ERROR_ACK : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32f7xx_hal_can.h
  • HAL_CAN_ErrorCallback() : stm32f7xx_hal_can.c
  • HAL_CAN_GetError() : stm32f7xx_hal_can.c
  • HAL_CAN_GetState() : stm32f7xx_hal_can.c
  • HAL_CAN_Init() : stm32f7xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32f7xx_hal_can.c
  • HAL_CAN_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CAN_MspDeInit() : stm32f7xx_hal_can.c
  • HAL_CAN_MspInit() : stm32f7xx_hal_can.c
  • HAL_CAN_Receive() : stm32f7xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32f7xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32f7xx_hal_can.c
  • HAL_CAN_Sleep() : stm32f7xx_hal_can.c
  • HAL_CAN_STATE_BUSY : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32f7xx_hal_can.h
  • HAL_CAN_StateTypeDef : stm32f7xx_hal_can.h
  • HAL_CAN_Transmit() : stm32f7xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32f7xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32f7xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32f7xx_hal_can.c
  • HAL_CEC_DeInit() : stm32f7xx_hal_cec.c
  • HAL_CEC_ERROR_ARBLST : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32f7xx_hal_cec.h
  • HAL_CEC_ErrorCallback() : stm32f7xx_hal_cec.c
  • HAL_CEC_GetError() : stm32f7xx_hal_cec.c
  • HAL_CEC_GetReceivedFrameSize() : stm32f7xx_hal_cec.c
  • HAL_CEC_GetState() : stm32f7xx_hal_cec.c
  • HAL_CEC_Init() : stm32f7xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32f7xx_hal_cec.c
  • HAL_CEC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CEC_MspDeInit() : stm32f7xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32f7xx_hal_cec.c
  • HAL_CEC_Receive() : stm32f7xx_hal_cec.c
  • HAL_CEC_Receive_IT() : stm32f7xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32f7xx_hal_cec.c
  • HAL_CEC_STATE_BUSY : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_STANDBY_RX : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_TIMEOUT : stm32f7xx_hal_cec.h
  • HAL_CEC_StateTypeDef : stm32f7xx_hal_cec.h
  • HAL_CEC_Transmit() : stm32f7xx_hal_cec.c
  • HAL_CEC_Transmit_IT() : stm32f7xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32f7xx_hal_cec.c
  • HAL_CORTEX_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_Calculate() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_DeInit() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_GetState() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_Init() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_Input_Data_Reverse : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32f7xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_MspInit() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_Output_Data_Reverse : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_BUSY : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f7xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32f7xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32f7xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32f7xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32f7xx_hal_crc_ex.c
  • HAL_CRYP_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DAC_ConfigChannel() : stm32f7xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_DeInit() : stm32f7xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_DMA : stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32f7xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_GetError() : stm32f7xx_hal_dac.c
  • HAL_DAC_GetState() : stm32f7xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32f7xx_hal_dac.c
  • HAL_DAC_Init() : stm32f7xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32f7xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32f7xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32f7xx_hal_dac.c
  • HAL_DAC_Start() : stm32f7xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32f7xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32f7xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32f7xx_hal_dac.h
  • HAL_DAC_Stop() : stm32f7xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32f7xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_DualGetValue() : stm32f7xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32f7xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32f7xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32f7xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f7xx_hal.c
  • HAL_DCMI_ConfigCROP() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_DeInit() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_DisableCROP() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_EnableCROP() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_ERROR_NONE : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_OVF : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_SYNC : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_TIMEOUT : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ErrorCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_FrameEventCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_GetError() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_GetState() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_Init() : stm32f7xx_hal_dcmi.c , stm32f7xx_hal_dcmi_ex.c
  • HAL_DCMI_IRQHandler() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_LineEventCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DCMI_MspDeInit() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_MspInit() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_Start_DMA() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_STATE_BUSY : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_ERROR : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_READY : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_RESET : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_TIMEOUT : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_StateTypeDef : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_Stop() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_VsyncEventCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DeInit() : stm32f7xx_hal.c
  • HAL_Delay() : stm32f7xx_hal.c
  • HAL_DisableCompensationCell() : stm32f7xx_hal.c
  • HAL_DisableFMCMemorySwapping() : stm32f7xx_hal.c
  • HAL_DMA2D_Abort() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_BlendingStart() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_BlendingStart_IT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ConfigCLUT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ConfigLayer() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_DeInit() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_DisableCLUT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_EnableCLUT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_CE : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_NONE : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TE : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TIMEOUT : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_GetError() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_GetState() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Init() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_IRQHandler() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DMA2D_MspDeInit() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_MspInit() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_PollForTransfer() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ProgramLineEvent() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Resume() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Start() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Start_IT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_BUSY : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_ERROR : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_READY : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_RESET : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_SUSPEND : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_TIMEOUT : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_StateTypeDef : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Suspend() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA_Abort() : stm32f7xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32f7xx_hal_dma.c
  • HAL_DMA_ERROR_DME : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f7xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32f7xx_hal_dma.h
  • HAL_DMA_GetError() : stm32f7xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f7xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32f7xx_hal_dma.h
  • HAL_DMA_Init() : stm32f7xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f7xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32f7xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32f7xx_hal_dma_ex.h
  • HAL_DMA_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32f7xx_hal_dma.c
  • HAL_DMA_Start() : stm32f7xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f7xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM0 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM1 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM0 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM1 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM0 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM1 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f7xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32f7xx_hal_dma.h
  • HAL_DMAEx_ChangeMemory() : stm32f7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32f7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32f7xx_hal_dma_ex.c
  • HAL_EnableCompensationCell() : stm32f7xx_hal.c
  • HAL_EnableFMCMemorySwapping() : stm32f7xx_hal.c
  • HAL_ETH_ConfigDMA() : stm32f7xx_hal_eth.c
  • HAL_ETH_ConfigMAC() : stm32f7xx_hal_eth.c
  • HAL_ETH_DeInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_DMARxDescListInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_DMATxDescListInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_ErrorCallback() : stm32f7xx_hal_eth.c
  • HAL_ETH_GetReceivedFrame() : stm32f7xx_hal_eth.c
  • HAL_ETH_GetReceivedFrame_IT() : stm32f7xx_hal_eth.c
  • HAL_ETH_GetState() : stm32f7xx_hal_eth.c
  • HAL_ETH_Init() : stm32f7xx_hal_eth.c
  • HAL_ETH_IRQHandler() : stm32f7xx_hal_eth.c
  • HAL_ETH_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_ETH_MspDeInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_MspInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_ReadPHYRegister() : stm32f7xx_hal_eth.c
  • HAL_ETH_RxCpltCallback() : stm32f7xx_hal_eth.c
  • HAL_ETH_Start() : stm32f7xx_hal_eth.c
  • HAL_ETH_STATE_BUSY : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_RD : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_RX : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_TX : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_TX_RX : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_WR : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_ERROR : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_READY : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_RESET : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_TIMEOUT : stm32f7xx_hal_eth.h
  • HAL_ETH_StateTypeDef : stm32f7xx_hal_eth.h
  • HAL_ETH_Stop() : stm32f7xx_hal_eth.c
  • HAL_ETH_TransmitFrame() : stm32f7xx_hal_eth.c
  • HAL_ETH_TxCpltCallback() : stm32f7xx_hal_eth.c
  • HAL_ETH_WritePHYRegister() : stm32f7xx_hal_eth.c
  • HAL_FLASH_EndOfOperationCallback() : stm32f7xx_hal_flash.c
  • HAL_FLASH_ERROR_ERS : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPERATION : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGP : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f7xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32f7xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f7xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f7xx_hal_flash.c
  • HAL_FLASHEx_Erase() : stm32f7xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f7xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32f7xx_hal.c
  • HAL_GetHalVersion() : stm32f7xx_hal.c
  • HAL_GetREVID() : stm32f7xx_hal.c
  • HAL_GetTick() : stm32f7xx_hal.c
  • HAL_GPIO_DeInit() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f7xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f7xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f7xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f7xx_hal_uart.c
  • HAL_HASH_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_HCD_Connect_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32f7xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32f7xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Init() : stm32f7xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32f7xx_hal_hcd.c
  • HAL_HCD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_HCD_MspDeInit() : stm32f7xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32f7xx_hal_hcd.c
  • HAL_HCD_ResetPort() : stm32f7xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Start() : stm32f7xx_hal_hcd.c
  • HAL_HCD_STATE_BUSY : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32f7xx_hal_hcd.h
  • HAL_HCD_Stop() : stm32f7xx_hal_hcd.c
  • HAL_I2C_DeInit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f7xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f7xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f7xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f7xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f7xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_STATE_BUSY : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MASTER_BUSY_RX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MASTER_BUSY_TX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MEM_BUSY_RX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MEM_BUSY_TX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_SLAVE_BUSY_RX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_SLAVE_BUSY_TX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f7xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f7xx_hal_i2c.h
  • HAL_I2CEx_ConfigAnalogFilter() : stm32f7xx_hal_i2c_ex.c , stm32f7xx_hal_i2c_ex.h
  • HAL_I2CEx_ConfigDigitalFilter() : stm32f7xx_hal_i2c_ex.c , stm32f7xx_hal_i2c_ex.h
  • HAL_I2S_DeInit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32f7xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32f7xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32f7xx_hal_i2s.c
  • HAL_I2S_ERROR_DMA : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_UNKNOW : stm32f7xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32f7xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Init() : stm32f7xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32f7xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32f7xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32f7xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32f7xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32f7xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_IncTick() : stm32f7xx_hal.c
  • HAL_Init() : stm32f7xx_hal.c
  • HAL_InitTick() : stm32f7xx_hal.c
  • HAL_IRDA_DeInit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f7xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f7xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f7xx_hal_irda.c
  • HAL_IRDA_ERROR_DMA : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f7xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f7xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f7xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f7xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f7xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32f7xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f7xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_GetState() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_IWDG_MspInit() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_Start() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_STATE_BUSY : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_ERROR : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_READY : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_RESET : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_TIMEOUT : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_StateTypeDef : stm32f7xx_hal_iwdg.h
  • HAL_LIN_Init() : stm32f7xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f7xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LTDC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32f7xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32f7xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32f7xx_hal_cortex.h
  • HAL_MspDeInit() : stm32f7xx_hal.c
  • HAL_MspInit() : stm32f7xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32f7xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32f7xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f7xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f7xx_hal_uart.c
  • HAL_NAND_Address_Inc() : stm32f7xx_hal_nand.c
  • HAL_NAND_DeInit() : stm32f7xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32f7xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32f7xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32f7xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32f7xx_hal_nand.c
  • HAL_NAND_GetState() : stm32f7xx_hal_nand.c
  • HAL_NAND_Init() : stm32f7xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32f7xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32f7xx_hal_nand.c
  • HAL_NAND_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_NAND_MspDeInit() : stm32f7xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_Page() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32f7xx_hal_nand.c , stm32f7xx_hal_nand.h
  • HAL_NAND_Reset() : stm32f7xx_hal_nand.c
  • HAL_NAND_STATE_BUSY : stm32f7xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32f7xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32f7xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32f7xx_hal_nand.h
  • HAL_NAND_StateTypeDef : stm32f7xx_hal_nand.h
  • HAL_NAND_Write_Page() : stm32f7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea() : stm32f7xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32f7xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32f7xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32f7xx_hal_nor.c
  • HAL_NOR_GetState() : stm32f7xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32f7xx_hal_nor.c
  • HAL_NOR_Init() : stm32f7xx_hal_nor.c
  • HAL_NOR_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_NOR_MspDeInit() : stm32f7xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32f7xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32f7xx_hal_nor.c
  • HAL_NOR_Program() : stm32f7xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32f7xx_hal_nor.c
  • HAL_NOR_Read() : stm32f7xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32f7xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32f7xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32f7xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32f7xx_hal_nor.c
  • HAL_NOR_STATE_BUSY : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32f7xx_hal_nor.h
  • HAL_NOR_StateTypeDef : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32f7xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32f7xx_hal_nor.h
  • HAL_NOR_WriteOperation_Disable() : stm32f7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32f7xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f7xx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32f7xx_hal_pcd.c
  • HAL_PCD_Init() : stm32f7xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_Start() : stm32f7xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32f7xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCDEx_ActivateLPM() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32f7xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f7xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_PWR_PVD_IRQHandler() : stm32f7xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32f7xx_hal_pwr.c
  • HAL_PWREx_ControlVoltageScaling() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMainRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableOverDrive() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMainRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableOverDrive() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterUnderDriveSTOPMode() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32f7xx_hal_pwr_ex.c
  • HAL_QPSI_TIMEOUT_DEFAULT_VALUE : stm32f7xx_hal_qspi.h
  • HAL_QSPI_Abort() : stm32f7xx_hal_qspi.h , stm32f7xx_hal_qspi.c
  • HAL_QSPI_AutoPolling() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_AutoPolling_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_CmdCpltCallback() : stm32f7xx_hal_qspi.h , stm32f7xx_hal_qspi.c
  • HAL_QSPI_Command() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Command_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_DeInit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_ERROR_DMA : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ErrorCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_GetError() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_GetState() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_Init() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_IRQHandler() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_MemoryMapped() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_QSPI_MspDeInit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_MspInit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Receive() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Receive_DMA() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Receive_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_RxCpltCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_RxHalfCpltCallback() : stm32f7xx_hal_qspi.h , stm32f7xx_hal_qspi.c
  • HAL_QSPI_SetTimeout() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32f7xx_hal_qspi.h
  • HAL_QSPI_StateTypeDef : stm32f7xx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_TimeOutCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_Transmit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Transmit_DMA() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Transmit_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_TxCpltCallback() : stm32f7xx_hal_qspi.h , stm32f7xx_hal_qspi.c
  • HAL_QSPI_TxHalfCpltCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_RCC_ClockConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f7xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f7xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32f7xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32f7xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32f7xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f7xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f7xx_hal.c
  • HAL_RNG_DeInit() : stm32f7xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32f7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32f7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32f7xx_hal_rng.c
  • HAL_RNG_GetRandomNumber() : stm32f7xx_hal_rng.c
  • HAL_RNG_GetRandomNumber_IT() : stm32f7xx_hal_rng.c
  • HAL_RNG_GetState() : stm32f7xx_hal_rng.c
  • HAL_RNG_Init() : stm32f7xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32f7xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32f7xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32f7xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32f7xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32f7xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32f7xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32f7xx_hal_rng.h
  • HAL_RTC_AlarmAEventCallback() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_AlarmIRQHandler() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_DeactivateAlarm() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_DeInit() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_GetAlarm() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_GetDate() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_GetState() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_GetTime() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_Init() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_MspInit() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_SetAlarm() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_SetDate() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_SetTime() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_BUSY : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f7xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTCEx_AlarmBEventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_BKUPRead() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_BKUPWrite() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateRefClock() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateTamper() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DisableBypassShadow() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_EnableBypassShadow() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_GetTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_GetWakeUpTimer() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForAlarmBEvent() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForTamper1Event() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForTamper2Event() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForTamper3Event() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForTimeStampEvent() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetCalibrationOutPut() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetInternalTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetRefClock() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetSmoothCalib() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetSynchroShift() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTamper() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTamper_IT() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTimeStamp_IT() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetWakeUpTimer() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_Tamper1EventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_Tamper2EventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_Tamper3EventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCStateTypeDef : stm32f7xx_hal_rtc.h
  • HAL_SAI_Abort() : stm32f7xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32f7xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32f7xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32f7xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32f7xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_ERROR_AFSDET : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32f7xx_hal_sai.h
  • HAL_SAI_ErrorCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_GetError() : stm32f7xx_hal_sai.c
  • HAL_SAI_GetState() : stm32f7xx_hal_sai.c
  • HAL_SAI_Init() : stm32f7xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32f7xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32f7xx_hal_sai.c
  • HAL_SAI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SAI_MspDeInit() : stm32f7xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32f7xx_hal_sai.c
  • HAL_SAI_Receive() : stm32f7xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32f7xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32f7xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_STATE_BUSY : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_ERROR : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_TIMEOUT : stm32f7xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32f7xx_hal_sai.h
  • HAL_SAI_Transmit() : stm32f7xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32f7xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32f7xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SD_CardStateTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_CheckReadOperation() : stm32f7xx_hal_sd.c
  • HAL_SD_CheckWriteOperation() : stm32f7xx_hal_sd.c
  • HAL_SD_DeInit() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_RxCpltCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_RxErrorCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_TxCpltCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_TxErrorCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_Erase() : stm32f7xx_hal_sd.c
  • HAL_SD_ErrorTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_Get_CardInfo() : stm32f7xx_hal_sd.c
  • HAL_SD_GetCardStatus() : stm32f7xx_hal_sd.c
  • HAL_SD_GetStatus() : stm32f7xx_hal_sd.c
  • HAL_SD_HighSpeed() : stm32f7xx_hal_sd.c
  • HAL_SD_Init() : stm32f7xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32f7xx_hal_sd.c
  • HAL_SD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SD_MspDeInit() : stm32f7xx_hal_sd.c
  • HAL_SD_MspInit() : stm32f7xx_hal_sd.c
  • HAL_SD_OperationTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_ReadBlocks() : stm32f7xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32f7xx_hal_sd.c
  • HAL_SD_SendSDStatus() : stm32f7xx_hal_sd.c
  • HAL_SD_StopTransfer() : stm32f7xx_hal_sd.c
  • HAL_SD_TransferStateTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_WideBusOperation_Config() : stm32f7xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32f7xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32f7xx_hal_sd.c
  • HAL_SD_XferCpltCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_XferErrorCallback() : stm32f7xx_hal_sd.c
  • HAL_SDRAM_DeInit() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferCpltCallback() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferErrorCallback() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_GetModeStatus() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_GetState() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Init() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_IRQHandler() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SDRAM_MspDeInit() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_MspInit() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_ProgramRefreshRate() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_16b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_32b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_8b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_DMA() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_RefreshErrorCallback() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_SendCommand() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_SetAutoRefreshNumber() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_STATE_BUSY : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_ERROR : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_PRECHARGED : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_READY : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_RESET : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_WRITE_PROTECTED : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_StateTypeDef : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_Write_16b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_32b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_8b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_DMA() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Disable() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Enable() : stm32f7xx_hal_sdram.c
  • HAL_SMARTCARD_DeInit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_DMA : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32f7xx_hal_smartcard_ex.c , stm32f7xx_hal_smartcard_ex.h
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SPDIFRX_CxCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_CxHalfCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DeInit() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DMAStop() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ERROR_DMA : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_NONE : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_OVR : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_PE : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_TIMEOUT : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_UNKNOWN : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ErrorCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetError() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetState() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_Init() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_IRQHandler() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SPDIFRX_MspDeInit() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspInit() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_DMA() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_IT() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_DMA() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_IT() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxHalfCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_SetDataFormat() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_STATE_BUSY : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_CX : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_RX : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_ERROR : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_READY : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_RESET : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_StateTypeDef : stm32f7xx_hal_spdifrx.h
  • HAL_SPI_DeInit() : stm32f7xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f7xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f7xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f7xx_hal_spi.c
  • HAL_SPI_ERROR_CRC : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32f7xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f7xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f7xx_hal_spi.c
  • HAL_SPI_Init() : stm32f7xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f7xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32f7xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f7xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f7xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f7xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f7xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_STATE_BUSY : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f7xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32f7xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32f7xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f7xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f7xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SRAM_DeInit() : stm32f7xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32f7xx_hal_sram.h , stm32f7xx_hal_sram.c
  • HAL_SRAM_DMA_XferErrorCallback() : stm32f7xx_hal_sram.c , stm32f7xx_hal_sram.h
  • HAL_SRAM_GetState() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Init() : stm32f7xx_hal_sram.c
  • HAL_SRAM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SRAM_MspDeInit() : stm32f7xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32f7xx_hal_sram.c
  • HAL_SRAM_STATE_BUSY : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32f7xx_hal_sram.h
  • HAL_SRAM_StateTypeDef : stm32f7xx_hal_sram.h
  • HAL_SRAM_Write_16b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32f7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32f7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32f7xx_hal_sram.c
  • HAL_SuspendTick() : stm32f7xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f7xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f7xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f7xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f7xx_hal_cortex.c
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f7xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32f7xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f7xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim_ex.c
  • HAL_TIM_ConfigTI1Input() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMACaptureCplt() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • HAL_TIM_DMADelayPulseCplt() : stm32f7xx_hal_tim.h , stm32f7xx_hal_tim.c
  • HAL_TIM_DMAError() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • HAL_TIM_Encoder_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f7xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32f7xx_hal_tim_ex.c , stm32f7xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim_ex.c
  • HAL_TIM_PWM_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f7xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f7xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32f7xx_hal_tim.c
  • HAL_TIMEOUT_DCMI_STOP : stm32f7xx_hal_dcmi.c
  • HAL_TIMEOUT_DMA2D_ABORT : stm32f7xx_hal_dma2d.c
  • HAL_TIMEOUT_DMA2D_SUSPEND : stm32f7xx_hal_dma2d.c
  • HAL_TIMEOUT_DMA_ABORT : stm32f7xx_hal_dma.c
  • HAL_TIMEx_BreakCallback() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_DMACommutationCplt() : stm32f7xx_hal_tim_ex.h , stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32f7xx_hal_tim_ex.c
  • HAL_UART_DeInit() : stm32f7xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f7xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f7xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f7xx_hal_uart.c
  • HAL_UART_ERROR_DMA : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f7xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_GetError() : stm32f7xx_hal_uart.h , stm32f7xx_hal_uart.c
  • HAL_UART_GetState() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • HAL_UART_Init() : stm32f7xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f7xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32f7xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f7xx_hal_uart.c
  • HAL_UART_Receive() : stm32f7xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f7xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f7xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f7xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32f7xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32f7xx_hal_uart.h
  • HAL_UART_Transmit() : stm32f7xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f7xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f7xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_USART_CheckIdleState() : stm32f7xx_hal_usart.h
  • HAL_USART_DeInit() : stm32f7xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f7xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f7xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f7xx_hal_usart.c
  • HAL_USART_ERROR_DMA : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f7xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_GetError() : stm32f7xx_hal_usart.c
  • HAL_USART_GetState() : stm32f7xx_hal_usart.c
  • HAL_USART_Init() : stm32f7xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f7xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32f7xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f7xx_hal_usart.c
  • HAL_USART_Receive() : stm32f7xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f7xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f7xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f7xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32f7xx_hal_usart.h
  • HAL_USART_Transmit() : stm32f7xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f7xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f7xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f7xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f7xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f7xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_WWDG_DeInit() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_GetState() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_WWDG_MspDeInit() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Start() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Start_IT() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_STATE_BUSY : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_ERROR : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_READY : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_RESET : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_TIMEOUT : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_StateTypeDef : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_WakeupCallback() : stm32f7xx_hal_wwdg.c , stm32f7xx_hal_wwdg.h
  • HCD_HC_IN_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_HCStateTypeDef : stm32f7xx_hal_hcd.h
  • HCD_HCTypeDef : stm32f7xx_hal_hcd.h
  • HCD_InitTypeDef : stm32f7xx_hal_hcd.h
  • HCD_PHY_EMBEDDED : stm32f7xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32f7xx_hal_hcd.h
  • HCD_Port_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_SPEED_FULL : stm32f7xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32f7xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32f7xx_hal_hcd.h
  • HCD_StateTypeDef : stm32f7xx_hal_hcd.h
  • HCD_TypeDef : stm32f7xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32f7xx_hal_hcd.h
  • HIGH_CAPACITY_MMC_CARD : stm32f7xx_hal_sd.h
  • HIGH_CAPACITY_SD_CARD : stm32f7xx_hal_sd.h
  • HIGH_SPEED_MULTIMEDIA_CARD : stm32f7xx_hal_sd.h
  • HSE_STARTUP_TIMEOUT : stm32f7xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • HSE_VALUE : stm32f7xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • HSI_VALUE : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32f7xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f7xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32f7xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32f7xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32f7xx_hal_i2c.h
  • I2C_DMAError() : stm32f7xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMAMemReceiveCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMAMemTransmitCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32f7xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32f7xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f7xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f7xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32f7xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f7xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f7xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32f7xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f7xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TC : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32f7xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32f7xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_START : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32f7xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32f7xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32f7xx_hal_i2c.h
  • I2C_IT_ERRI : stm32f7xx_hal_i2c.h
  • I2C_IT_NACKI : stm32f7xx_hal_i2c.h
  • I2C_IT_RXI : stm32f7xx_hal_i2c.h
  • I2C_IT_STOPI : stm32f7xx_hal_i2c.h
  • I2C_IT_TCI : stm32f7xx_hal_i2c.h
  • I2C_IT_TXI : stm32f7xx_hal_i2c.h
  • I2C_MasterReceive_ISR() : stm32f7xx_hal_i2c.c
  • I2C_MasterTransmit_ISR() : stm32f7xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32f7xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f7xx_hal_i2c.h
  • I2C_NO_STARTSTOP : stm32f7xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32f7xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32f7xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32f7xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32f7xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32f7xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f7xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32f7xx_hal_i2c.h
  • I2C_SlaveReceive_ISR() : stm32f7xx_hal_i2c.c
  • I2C_SlaveTransmit_ISR() : stm32f7xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32f7xx_hal_i2c.h
  • I2C_TIMEOUT_ADDR : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32f7xx_hal_i2c.c
  • I2C_TransferConfig() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32f7xx_hal_i2s.h
  • I2S_CLOCK_EXTERNAL : stm32f7xx_hal_i2s.h
  • I2S_CLOCK_SYSCLK : stm32f7xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32f7xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32f7xx_hal_i2s.h
  • I2S_DMAError() : stm32f7xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32f7xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32f7xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32f7xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32f7xx_hal_i2s.c
  • I2S_FLAG_BSY : stm32f7xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32f7xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32f7xx_hal_i2s.h
  • I2S_GetClockFreq() : stm32f7xx_hal_i2s.c
  • I2S_IT_ERR : stm32f7xx_hal_i2s.h
  • I2S_IT_RXNE : stm32f7xx_hal_i2s.h
  • I2S_IT_TXE : stm32f7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32f7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32f7xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32f7xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32f7xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32f7xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32f7xx_hal_i2s.h
  • I2S_Receive_IT() : stm32f7xx_hal_i2s.c
  • I2S_STANDARD_LSB : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32f7xx_hal_i2s.h
  • I2S_Transmit_IT() : stm32f7xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32f7xx_hal_i2s.c
  • IDCODE_DEVID_MASK : stm32f7xx_hal.c
  • IRDA_AUTOBAUD_REQUEST : stm32f7xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32f7xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32f7xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32f7xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_DMAError() : stm32f7xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f7xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f7xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f7xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f7xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f7xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32f7xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32f7xx_hal_irda.h
  • IRDA_FLAG_FE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32f7xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f7xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32f7xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f7xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32f7xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32f7xx_hal_irda.h
  • IRDA_IT_FE : stm32f7xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f7xx_hal_irda.h
  • IRDA_IT_MASK : stm32f7xx_hal_irda.h
  • IRDA_IT_NE : stm32f7xx_hal_irda.h
  • IRDA_IT_ORE : stm32f7xx_hal_irda.h
  • IRDA_IT_PE : stm32f7xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f7xx_hal_irda.h
  • IRDA_IT_TC : stm32f7xx_hal_irda.h
  • IRDA_IT_TXE : stm32f7xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32f7xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_MODE_RX : stm32f7xx_hal_irda.h
  • IRDA_MODE_TX : stm32f7xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f7xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f7xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f7xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f7xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f7xx_hal_irda.h
  • IRDA_Receive_IT() : stm32f7xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_irda.h
  • IRDA_SetConfig() : stm32f7xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_Transmit_IT() : stm32f7xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32f7xx_hal_irda.c
  • IRDA_WORDLENGTH_7B : stm32f7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32f7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32f7xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG : stm32f7xx_hal_adc.h
  • IS_ADC_CHANNEL : stm32f7xx_hal_adc_ex.h
  • IS_ADC_CHANNELS_TYPE : stm32f7xx_hal_adc.h
  • IS_ADC_CLOCKPRESCALER : stm32f7xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32f7xx_hal_adc.h
  • IS_ADC_DMA_ACCESS_MODE : stm32f7xx_hal_adc_ex.h
  • IS_ADC_EOCSelection : stm32f7xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32f7xx_hal_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32f7xx_hal_adc_ex.h
  • IS_ADC_EXT_INJEC_TRIG_EDGE : stm32f7xx_hal_adc_ex.h
  • IS_ADC_EXT_TRIG : stm32f7xx_hal_adc.h
  • IS_ADC_EXT_TRIG_EDGE : stm32f7xx_hal_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32f7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f7xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32f7xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f7xx_hal_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32f7xx_hal_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32f7xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32f7xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32f7xx_hal_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f7xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32f7xx_hal_adc.h
  • IS_ADC_THRESHOLD : stm32f7xx_hal_adc.h
  • IS_CAN_BANKNUMBER : stm32f7xx_hal_can.h
  • IS_CAN_BS1 : stm32f7xx_hal_can.h
  • IS_CAN_BS2 : stm32f7xx_hal_can.h
  • IS_CAN_DLC : stm32f7xx_hal_can.h
  • IS_CAN_EXTID : stm32f7xx_hal_can.h
  • IS_CAN_FIFO : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_SCALE : stm32f7xx_hal_can.h
  • IS_CAN_IDTYPE : stm32f7xx_hal_can.h
  • IS_CAN_MODE : stm32f7xx_hal_can.h
  • IS_CAN_PRESCALER : stm32f7xx_hal_can.h
  • IS_CAN_RTR : stm32f7xx_hal_can.h
  • IS_CAN_SJW : stm32f7xx_hal_can.h
  • IS_CAN_STDID : stm32f7xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f7xx_hal_can.h
  • IS_CEC_ADDRESS : stm32f7xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32f7xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32f7xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32f7xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32f7xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32f7xx_hal_cec.h
  • IS_CEC_OAR_ADDRESS : stm32f7xx_hal_cec.h
  • IS_CEC_SFTOP : stm32f7xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32f7xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32f7xx_hal_cec.h
  • IS_CHANNEL_STATUS_MASK : stm32f7xx_hal_spdifrx.h
  • IS_CRC_INPUTDATA_FORMAT : stm32f7xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32f7xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32f7xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32f7xx_hal_crc.h
  • IS_DAC_ALIGN : stm32f7xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32f7xx_hal_dac.h
  • IS_DAC_DATA : stm32f7xx_hal_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f7xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f7xx_hal_dac.h
  • IS_DAC_TRIGGER : stm32f7xx_hal_dac.h
  • IS_DCMI_BYTE_SELECT_MODE : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_BYTE_SELECT_START : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_CAPTURE_MODE : stm32f7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_RATE : stm32f7xx_hal_dcmi.h
  • IS_DCMI_EXTENDED_DATA : stm32f7xx_hal_dcmi.h
  • IS_DCMI_HSPOLARITY : stm32f7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_MODE : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_LINE_SELECT_START : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_MODE_JPEG : stm32f7xx_hal_dcmi.h
  • IS_DCMI_PCKPOLARITY : stm32f7xx_hal_dcmi.h
  • IS_DCMI_SYNCHRO : stm32f7xx_hal_dcmi.h
  • IS_DCMI_VSPOLARITY : stm32f7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_COORDINATE : stm32f7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_HEIGHT : stm32f7xx_hal_dcmi.h
  • IS_DEFAULT_INIT_VALUE : stm32f7xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32f7xx_hal_crc.h
  • IS_DMA2D_ALPHA_MODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_CM : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_SIZE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_CMODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_COLOR : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_GET_FLAG : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_INPUT_COLOR_MODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_IT : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_LAYER : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_LINE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_LineWatermark : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_MODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_OFFSET : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_PIXEL : stm32f7xx_hal_dma2d.h
  • IS_DMA_BUFFER_SIZE : stm32f7xx_hal_dma.h
  • IS_DMA_CHANNEL : stm32f7xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f7xx_hal_dma.h
  • IS_DMA_FIFO_MODE_STATE : stm32f7xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32f7xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32f7xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f7xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f7xx_hal_dma.h
  • IS_DMA_MODE : stm32f7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32f7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f7xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f7xx_hal_dma.h
  • IS_ETH_ADDRESS_ALIGNED_BEATS : stm32f7xx_hal_eth.h
  • IS_ETH_AUTOMATIC_PADCRC_STRIP : stm32f7xx_hal_eth.h
  • IS_ETH_AUTONEGOTIATION : stm32f7xx_hal_eth.h
  • IS_ETH_BACKOFF_LIMIT : stm32f7xx_hal_eth.h
  • IS_ETH_BROADCAST_FRAMES_RECEPTION : stm32f7xx_hal_eth.h
  • IS_ETH_CARRIER_SENSE : stm32f7xx_hal_eth.h
  • IS_ETH_CHECKSUM_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_CHECKSUM_OFFLOAD : stm32f7xx_hal_eth.h
  • IS_ETH_CONTROL_FRAMES : stm32f7xx_hal_eth.h
  • IS_ETH_DEFERRAL_CHECK : stm32f7xx_hal_eth.h
  • IS_ETH_DESTINATION_ADDR_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_DESC_SKIP_LENGTH : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_GET_IT : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_GET_OVERFLOW : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_IT : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_RXDESC_BUFFER : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_TXDESC_CHECKSUM : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_TXDESC_SEGMENT : stm32f7xx_hal_eth.h
  • IS_ETH_DMARXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DMATXDESC_BUFFER_SIZE : stm32f7xx_hal_eth.h
  • IS_ETH_DMATXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DROP_TCPIP_CHECKSUM_FRAME : stm32f7xx_hal_eth.h
  • IS_ETH_DUPLEX_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_ENHANCED_DESCRIPTOR_FORMAT : stm32f7xx_hal_eth.h
  • IS_ETH_FIXED_BURST : stm32f7xx_hal_eth.h
  • IS_ETH_FLUSH_RECEIVE_FRAME : stm32f7xx_hal_eth.h
  • IS_ETH_FORWARD_ERROR_FRAMES : stm32f7xx_hal_eth.h
  • IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES : stm32f7xx_hal_eth.h
  • IS_ETH_INTER_FRAME_GAP : stm32f7xx_hal_eth.h
  • IS_ETH_JABBER : stm32f7xx_hal_eth.h
  • IS_ETH_LOOPBACK_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS0123 : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS123 : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS_MASK : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_GET_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MEDIA_INTERFACE : stm32f7xx_hal_eth.h
  • IS_ETH_MMC_GET_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MMC_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MULTICAST_FRAMES_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_PAUSE_LOW_THRESHOLD : stm32f7xx_hal_eth.h
  • IS_ETH_PAUSE_TIME : stm32f7xx_hal_eth.h
  • IS_ETH_PHY_ADDRESS : stm32f7xx_hal_eth.h
  • IS_ETH_PMT_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_PROMISCUOUS_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_ALL : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_FLOWCONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_OWN : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_STORE_FORWARD : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_THRESHOLD_CONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_RETRY_TRANSMISSION : stm32f7xx_hal_eth.h
  • IS_ETH_RX_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_RXDMA_BURST_LENGTH : stm32f7xx_hal_eth.h
  • IS_ETH_SECOND_FRAME_OPERATE : stm32f7xx_hal_eth.h
  • IS_ETH_SOURCE_ADDR_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_SPEED : stm32f7xx_hal_eth.h
  • IS_ETH_TRANSMIT_FLOWCONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_TRANSMIT_STORE_FORWARD : stm32f7xx_hal_eth.h
  • IS_ETH_TRANSMIT_THRESHOLD_CONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_TXDMA_BURST_LENGTH : stm32f7xx_hal_eth.h
  • IS_ETH_UNICAST_FRAMES_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_UNICAST_PAUSE_FRAME_DETECT : stm32f7xx_hal_eth.h
  • IS_ETH_VLAN_TAG_COMPARISON : stm32f7xx_hal_eth.h
  • IS_ETH_VLAN_TAG_IDENTIFIER : stm32f7xx_hal_eth.h
  • IS_ETH_WATCHDOG : stm32f7xx_hal_eth.h
  • IS_ETH_ZEROQUANTA_PAUSE : stm32f7xx_hal_eth.h
  • IS_FLASH_ADDRESS : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_LATENCY : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_NBSECTORS : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_SECTOR : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f7xx_hal_flash.h
  • IS_GPIO_AF : stm32f7xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32f7xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f7xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f7xx_hal_gpio.h
  • IS_GPIO_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • IS_GPIO_PULL : stm32f7xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f7xx_hal_gpio.h
  • IS_HCD_ALL_INSTANCE : stm32f7xx_hal_hcd.h
  • IS_I2C_ADDRESSING_MODE : stm32f7xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32f7xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32f7xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32f7xx_hal_i2c.h
  • IS_I2C_GENERAL_CALL : stm32f7xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f7xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32f7xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f7xx_hal_i2s.h
  • IS_I2S_CLOCKSOURCE : stm32f7xx_hal_i2s.h
  • IS_I2S_CPOL : stm32f7xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32f7xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32f7xx_hal_i2s.h
  • IS_I2S_MODE : stm32f7xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32f7xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32f7xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32f7xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32f7xx_hal_irda.h
  • IS_IRDA_MODE : stm32f7xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32f7xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f7xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f7xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32f7xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32f7xx_hal_irda.h
  • IS_IRDA_STATE : stm32f7xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32f7xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f7xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32f7xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f7xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32f7xx_hal_iwdg.h
  • IS_LIN_WORD_LENGTH : stm32f7xx_hal_uart_ex.h
  • IS_LPTIM_AUTORELOAD : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32f7xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32f7xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32f7xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32f7xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32f7xx_hal_lptim.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32f7xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32f7xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32f7xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f7xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f7xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f7xx_hal_cortex.h
  • IS_OB_BOOT_ADDRESS : stm32f7xx_hal_flash_ex.h
  • IS_OB_BOR_LEVEL : stm32f7xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OB_IWDG_STDBY_FREEZE : stm32f7xx_hal_flash_ex.h
  • IS_OB_IWDG_STOP_FREEZE : stm32f7xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f7xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32f7xx_hal_flash_ex.h
  • IS_OB_WWDG_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f7xx_hal_flash_ex.h
  • IS_PARITY_ERROR_MASK : stm32f7xx_hal_spdifrx.h
  • IS_PCD_ALL_INSTANCE : stm32f7xx_hal_pcd.h
  • IS_PREAMBLE_TYPE_MASK : stm32f7xx_hal_spdifrx.h
  • IS_PWR_PVD_LEVEL : stm32f7xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32f7xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32f7xx_hal_pwr.h
  • IS_PWR_REGULATOR_UNDERDRIVE : stm32f7xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR_VOLTAGE : stm32f7xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32f7xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f7xx_hal_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32f7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_POLARITY : stm32f7xx_hal_pwr.h
  • IS_QSPI_ADDRESS_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32f7xx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32f7xx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32f7xx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_DDR_HHC : stm32f7xx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_DUAL_FLASH_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32f7xx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32f7xx_hal_qspi.h
  • IS_QSPI_FLASH_ID : stm32f7xx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32f7xx_hal_qspi.c
  • IS_QSPI_GET_FLAG : stm32f7xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION : stm32f7xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32f7xx_hal_qspi.h
  • IS_QSPI_IT : stm32f7xx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32f7xx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32f7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32f7xx_hal_qspi.h
  • IS_RCC_CALIBRATION_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_CLK48SOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32f7xx_hal_rcc.h
  • IS_RCC_HCLK : stm32f7xx_hal_rcc.h
  • IS_RCC_HSE : stm32f7xx_hal_rcc.h
  • IS_RCC_HSI : stm32f7xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2C4CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2SCLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32f7xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32f7xx_hal_rcc.h
  • IS_RCC_LSI : stm32f7xx_hal_rcc.h
  • IS_RCC_MCO : stm32f7xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32f7xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32f7xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f7xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLI2S_DIVQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SN_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SP_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SR_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLM_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLSAI_DIVQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI_DIVR_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIN_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIP_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIR_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_RTCCLKSOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_SAI1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_SAI2CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_SDMMC1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_TIMPRES : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART4CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART7CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART8CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART6CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RNG_FLAG : stm32f7xx_hal_rng.h
  • IS_RNG_IT : stm32f7xx_hal_rng.h
  • IS_RTC_ALARM : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32f7xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f7xx_hal_rtc.h
  • IS_RTC_BKP : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32f7xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32f7xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f7xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32f7xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f7xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32f7xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32f7xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f7xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f7xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32f7xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32f7xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f7xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32f7xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32f7xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32f7xx_hal_rtc.h
  • IS_RTC_YEAR : stm32f7xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_STATUS : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32f7xx_hal_sai.h
  • IS_SAI_CLK_SOURCE : stm32f7xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32f7xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32f7xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32f7xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32f7xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f7xx_hal_smartcard.h
  • IS_SPDIFRX_CHANNEL : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_DATA_FORMAT : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_INPUT_SELECT : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_MAX_RETRIES : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_WAIT_FOR_ACTIVITY : stm32f7xx_hal_spdifrx.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f7xx_hal_spi.h
  • IS_SPI_CPHA : stm32f7xx_hal_spi.h
  • IS_SPI_CPOL : stm32f7xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f7xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32f7xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f7xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f7xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f7xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f7xx_hal_spi.h
  • IS_SPI_MODE : stm32f7xx_hal_spi.h
  • IS_SPI_NSS : stm32f7xx_hal_spi.h
  • IS_SPI_NSSP : stm32f7xx_hal_spi.h
  • IS_SPI_TIMODE : stm32f7xx_hal_spi.h
  • IS_STEREO_MODE : stm32f7xx_hal_spdifrx.h
  • IS_SYSTICK_CLK_SOURCE : stm32f7xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32f7xx_hal_tim_ex.h
  • IS_TIM_BREAK2_STATE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_BREAK_FILTER : stm32f7xx_hal_tim_ex.h
  • IS_TIM_BREAK_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_COUNTER_MODE : stm32f7xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f7xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f7xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f7xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f7xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_FLAG : stm32f7xx_hal_tim.h
  • IS_TIM_GET_IT : stm32f7xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32f7xx_hal_tim_ex.h
  • IS_TIM_IC_FILTER : stm32f7xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f7xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGER_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_IT : stm32f7xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f7xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_OC_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_OPM_MODE : stm32f7xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OUTPUT_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OUTPUTN_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_PWMI_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_REMAP : stm32f7xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_TI1SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_TRGO2_SOURCE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_TRGO_SOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f7xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32f7xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32f7xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32f7xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32f7xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32f7xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32f7xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f7xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32f7xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32f7xx_hal_uart.h
  • IS_UART_DMA_RX : stm32f7xx_hal_uart.h
  • IS_UART_DMA_TX : stm32f7xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32f7xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f7xx_hal_uart.h
  • IS_UART_LIN : stm32f7xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f7xx_hal_uart.h
  • IS_UART_MODE : stm32f7xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32f7xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32f7xx_hal_uart.h
  • IS_UART_OVERRUN : stm32f7xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32f7xx_hal_uart.h
  • IS_UART_PARITY : stm32f7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32f7xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32f7xx_hal_uart.h
  • IS_UART_STATE : stm32f7xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f7xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f7xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f7xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32f7xx_hal_usart.h
  • IS_USART_CLOCK : stm32f7xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f7xx_hal_usart.h
  • IS_USART_MODE : stm32f7xx_hal_usart.h
  • IS_USART_OVERSAMPLING : stm32f7xx_hal_usart.h
  • IS_USART_PARITY : stm32f7xx_hal_usart.h
  • IS_USART_PHASE : stm32f7xx_hal_usart.h
  • IS_USART_POLARITY : stm32f7xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32f7xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f7xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f7xx_hal_usart_ex.h
  • IS_VALIDITY_MASK : stm32f7xx_hal_spdifrx.h
  • IS_VOLTAGERANGE : stm32f7xx_hal_flash_ex.h
  • IS_WRPSTATE : stm32f7xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f7xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f7xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f7xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f7xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f7xx_hal_iwdg.h
  • IWDG_FLAG_PVU : stm32f7xx_hal_iwdg.h
  • IWDG_FLAG_RVU : stm32f7xx_hal_iwdg.h
  • IWDG_FLAG_WVU : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f7xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32f7xx_hal_iwdg.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LINE_WATERMARK : stm32f7xx_hal_dma2d.h
  • LINKED_STATE_TIMEOUT_VALUE : stm32f7xx_hal_eth.c
  • LPM_L0 : stm32f7xx_hal_pcd.h
  • LPM_L1 : stm32f7xx_hal_pcd.h
  • LPM_L2 : stm32f7xx_hal_pcd.h
  • LPM_L3 : stm32f7xx_hal_pcd.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32f7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32f7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32f7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32f7xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32f7xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32f7xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32f7xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32f7xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32f7xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32f7xx_hal_lptim.h
  • LPTIM_IT_UP : stm32f7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32f7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32f7xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32f7xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32f7xx_hal_lptim.h
  • LSE_VALUE : stm32f7xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • LSI_VALUE : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAC_ADDR0 : stm32f7xx_hal_conf.h
  • MAC_ADDR1 : stm32f7xx_hal_conf.h
  • MAC_ADDR2 : stm32f7xx_hal_conf.h
  • MAC_ADDR3 : stm32f7xx_hal_conf.h
  • MAC_ADDR4 : stm32f7xx_hal_conf.h
  • MAC_ADDR5 : stm32f7xx_hal_conf.h
  • MAX_DMA2D_LAYER : stm32f7xx_hal_dma2d.h
  • MC_ADDRESS : stm32f7xx_hal_nor.h
  • MCO1_CLK_ENABLE : stm32f7xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32f7xx_hal_rcc.c
  • MCO1_PIN : stm32f7xx_hal_rcc.c
  • MCO2_CLK_ENABLE : stm32f7xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32f7xx_hal_rcc.c
  • MCO2_PIN : stm32f7xx_hal_rcc.c
  • MEMORY0 : stm32f7xx_hal_dma_ex.h
  • MEMORY1 : stm32f7xx_hal_dma_ex.h
  • MPU_ACCESS_BUFFERABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32f7xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32f7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32f7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32f7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32f7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32f7xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32f7xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32f7xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32f7xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32f7xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32f7xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32f7xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32f7xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32f7xx_hal_cortex.h
  • MULTIMEDIA_CARD : stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NAND_BUSY : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32f7xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32f7xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32f7xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32f7xx_hal_nand.h
  • NAND_CMD_READID : stm32f7xx_hal_nand.h
  • NAND_CMD_RESET : stm32f7xx_hal_nand.h
  • NAND_CMD_STATUS : stm32f7xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32f7xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32f7xx_hal_nand.h
  • NAND_DEVICE : stm32f7xx_hal_nand.h
  • NAND_ERROR : stm32f7xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32f7xx_hal_nand.h
  • NAND_READY : stm32f7xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32f7xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32f7xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32f7xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32f7xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32f7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32f7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32f7xx_hal_nor.c
  • NOR_MEMORY_16B : stm32f7xx_hal_nor.h
  • NOR_MEMORY_8B : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32f7xx_hal_nor.h
  • NOR_TMEOUT : stm32f7xx_hal_nor.h
  • NOR_WRITE : stm32f7xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f7xx_hal_cortex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOOTADDR_AXIM_FLASH : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_DTCM_RAM : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_FLASH : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_RAM : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM1 : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM2 : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_SYSTEM : stm32f7xx_hal_flash_ex.h
  • OB_BOR_LEVEL1 : stm32f7xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32f7xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32f7xx_hal_flash_ex.h
  • OB_BOR_OFF : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_ACTIVE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_FREEZE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STOP_ACTIVE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STOP_FREEZE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32f7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f7xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f7xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f7xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_1 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_2 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_3 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_5 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_6 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_7 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_All : stm32f7xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f7xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f7xx_hal_flash_ex.h
  • OB_WWDG_HW : stm32f7xx_hal_flash_ex.h
  • OB_WWDG_SW : stm32f7xx_hal_flash_ex.h
  • OPTCR_BYTE1_ADDRESS : stm32f7xx_hal_flash.h
  • OPTIONBYTE_BOOTADDR_0 : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_BOOTADDR_1 : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_BOR : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f7xx_hal_flash_ex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PCD_EPTypeDef : stm32f7xx_hal_pcd.h
  • PCD_InitTypeDef : stm32f7xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32f7xx_hal_pcd_ex.h
  • PCD_LPM_L1_ACTIVE : stm32f7xx_hal_pcd_ex.h
  • PCD_LPM_MsgTypeDef : stm32f7xx_hal_pcd_ex.h
  • PCD_LPM_StateTypeDef : stm32f7xx_hal_pcd.h
  • PCD_MAX : stm32f7xx_hal_pcd.c
  • PCD_MIN : stm32f7xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32f7xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32f7xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32f7xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32f7xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32f7xx_hal_pcd.h
  • PCD_StateTypeDef : stm32f7xx_hal_pcd.h
  • PCD_TypeDef : stm32f7xx_hal_pcd.h
  • PCD_WriteEmptyTxFifo() : stm32f7xx_hal_pcd.c
  • pFlash : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c
  • PHY_AUTONEGO_COMPLETE : stm32f7xx_hal_conf.h
  • PHY_AUTONEGOTIATION : stm32f7xx_hal_conf.h
  • PHY_BCR : stm32f7xx_hal_conf.h
  • PHY_BSR : stm32f7xx_hal_conf.h
  • PHY_CONFIG_DELAY : stm32f7xx_hal_conf.h
  • PHY_DUPLEX_STATUS : stm32f7xx_hal_conf.h
  • PHY_FULLDUPLEX_100M : stm32f7xx_hal_conf.h
  • PHY_FULLDUPLEX_10M : stm32f7xx_hal_conf.h
  • PHY_HALFDUPLEX_100M : stm32f7xx_hal_conf.h
  • PHY_HALFDUPLEX_10M : stm32f7xx_hal_conf.h
  • PHY_ISOLATE : stm32f7xx_hal_conf.h
  • PHY_JABBER_DETECTION : stm32f7xx_hal_conf.h
  • PHY_LINK_INTERRUPT : stm32f7xx_hal_conf.h
  • PHY_LINK_STATUS : stm32f7xx_hal_conf.h
  • PHY_LINKED_STATUS : stm32f7xx_hal_conf.h
  • PHY_LOOPBACK : stm32f7xx_hal_conf.h
  • PHY_MICR : stm32f7xx_hal_conf.h
  • PHY_MICR_INT_EN : stm32f7xx_hal_conf.h
  • PHY_MICR_INT_OE : stm32f7xx_hal_conf.h
  • PHY_MISR : stm32f7xx_hal_conf.h
  • PHY_MISR_LINK_INT_EN : stm32f7xx_hal_conf.h
  • PHY_POWERDOWN : stm32f7xx_hal_conf.h
  • PHY_READ_TO : stm32f7xx_hal_conf.h
  • PHY_RESET : stm32f7xx_hal_conf.h
  • PHY_RESET_DELAY : stm32f7xx_hal_conf.h
  • PHY_RESTART_AUTONEGOTIATION : stm32f7xx_hal_conf.h
  • PHY_SPEED_STATUS : stm32f7xx_hal_conf.h
  • PHY_SR : stm32f7xx_hal_conf.h
  • PHY_WRITE_TO : stm32f7xx_hal_conf.h
  • PLL_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • PLLI2S_TIMEOUT_VALUE : stm32f7xx_hal_rcc_ex.c
  • PLLSAI_TIMEOUT_VALUE : stm32f7xx_hal_rcc_ex.c
  • PREFETCH_ENABLE : stm32f7xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f7xx_hal_pwr.c
  • PVD_MODE_EVT : stm32f7xx_hal_pwr.c
  • PVD_MODE_IT : stm32f7xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32f7xx_hal_pwr.c
  • PWR_BKPREG_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_EWUP_MASK : stm32f7xx_hal_pwr.c
  • PWR_EXTI_LINE_PVD : stm32f7xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32f7xx_hal_pwr.h
  • PWR_FLAG_ODRDY : stm32f7xx_hal_pwr_ex.h
  • PWR_FLAG_ODSWRDY : stm32f7xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32f7xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f7xx_hal_pwr.h
  • PWR_FLAG_UDRDY : stm32f7xx_hal_pwr_ex.h
  • PWR_FLAG_VOSRDY : stm32f7xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f7xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f7xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON : stm32f7xx_hal_pwr_ex.h
  • PWR_MAINREGULATOR_ON : stm32f7xx_hal_pwr.h
  • PWR_MAINREGULATOR_UNDERDRIVE_ON : stm32f7xx_hal_pwr_ex.h
  • PWR_OVERDRIVE_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32f7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32f7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32f7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32f7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32f7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f7xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f7xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f7xx_hal_pwr.h
  • PWR_UDERDRIVE_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_VOSRDY_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_WAKEUP_PIN1 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG1 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG2 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG3 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG4 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG5 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG6 : stm32f7xx_hal_pwr_ex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- q -

  • QSPI_ADDRESS_16_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32f7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32f7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32f7xx_hal_qspi.h
  • QSPI_Config() : stm32f7xx_hal_qspi.c
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_DATA_NONE : stm32f7xx_hal_qspi.h
  • QSPI_DDR_HHC_ANALOG_DELAY : stm32f7xx_hal_qspi.h
  • QSPI_DDR_HHC_HALF_CLK_DELAY : stm32f7xx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_DMAError() : stm32f7xx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DMARxHalfCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DMATxHalfCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DUALFLASH_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_DUALFLASH_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_BUSY : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_FT : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_SM : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_TC : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_TE : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_TO : stm32f7xx_hal_qspi.h
  • QSPI_FLASH_ID_1 : stm32f7xx_hal_qspi.h
  • QSPI_FLASH_ID_2 : stm32f7xx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32f7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32f7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32f7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32f7xx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32f7xx_hal_qspi.h
  • QSPI_IT_FT : stm32f7xx_hal_qspi.h
  • QSPI_IT_SM : stm32f7xx_hal_qspi.h
  • QSPI_IT_TC : stm32f7xx_hal_qspi.h
  • QSPI_IT_TE : stm32f7xx_hal_qspi.h
  • QSPI_IT_TO : stm32f7xx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32f7xx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32f7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32f7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32f7xx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32f7xx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32f7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_WaitFlagStateUntilTimeout() : stm32f7xx_hal_qspi.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_CECCLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_CIR_BYTE1_ADDRESS : stm32f7xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f7xx_hal_rcc.h
  • RCC_CLK48SOURCE_PLL : stm32f7xx_hal_rcc_ex.h
  • RCC_CLK48SOURCE_PLLSAIP : stm32f7xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_HCLK : stm32f7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f7xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f7xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • RCC_FLAG_BORRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PLLI2SRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PLLSAIRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f7xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f7xx_hal_rcc.h
  • RCC_HSE_ON : stm32f7xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f7xx_hal_rcc.h
  • RCC_HSI_ON : stm32f7xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_EXT : stm32f7xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32f7xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f7xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f7xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_PLLI2SRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_PLLSAIRDY : stm32f7xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32f7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32f7xx_hal_rcc.h
  • RCC_LSE_OFF : stm32f7xx_hal_rcc.h
  • RCC_LSE_ON : stm32f7xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32f7xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f7xx_hal_rcc.h
  • RCC_LSI_ON : stm32f7xx_hal_rcc.h
  • RCC_MCO1 : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_MCO2 : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLI2SCLK : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f7xx_hal_rcc.h
  • RCC_PERIPHCLK_CEC : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CLK48 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPDIFRX : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART7 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART6 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32f7xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f7xx_hal_rcc.h
  • RCC_PLL_ON : stm32f7xx_hal_rcc.h
  • RCC_PLLI2SP_DIV2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLI2SP_DIV4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLI2SP_DIV6 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLI2SP_DIV8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLP_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32f7xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_PLLSAIDIVR_16 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIDIVR_2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIDIVR_4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIDIVR_8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV6 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f7xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_PIN : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PIN : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLSAI : stm32f7xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_CLK48 : stm32f7xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_TIMPRES_ACTIVATED : stm32f7xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PCLK2 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RISING_EDGE : stm32f7xx_hal_gpio.c
  • RNG_FLAG_CECS : stm32f7xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32f7xx_hal_rng.h
  • RNG_FLAG_SECS : stm32f7xx_hal_rng.h
  • RNG_IT_CEI : stm32f7xx_hal_rng.h
  • RNG_IT_DRDY : stm32f7xx_hal_rng.h
  • RNG_IT_SEI : stm32f7xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32f7xx_hal_rng.c
  • RTC_ALARM_A : stm32f7xx_hal_rtc.h
  • RTC_ALARM_B : stm32f7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32f7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32f7xx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_Bcd2ToByte() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • RTC_BKP_DR0 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f7xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • RTC_CALIBOUTPUT_1HZ : stm32f7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32f7xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32f7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32f7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32f7xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32f7xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f7xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32f7xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f7xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32f7xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f7xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32f7xx_hal_rtc.h
  • RTC_INIT_MASK : stm32f7xx_hal_rtc.h
  • RTC_IT_ALRA : stm32f7xx_hal_rtc.h
  • RTC_IT_ALRB : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32f7xx_hal_rtc.h
  • RTC_IT_TS : stm32f7xx_hal_rtc.h
  • RTC_IT_WUT : stm32f7xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f7xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f7xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f7xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f7xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f7xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f7xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f7xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_ALARMA : stm32f7xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32f7xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32f7xx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32f7xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32f7xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32f7xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32f7xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32f7xx_hal_rtc.h
  • RTC_TAMPCR_TAMPXE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPCR_TAMPXIE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER1_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f7xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_POS1 : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_POS2 : stm32f7xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32f7xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32f7xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SAI_AC97_PROTOCOL : stm32f7xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32f7xx_hal_sai.h
  • SAI_BlockSynchroConfig() : stm32f7xx_hal_sai_ex.c
  • SAI_CLKSOURCE_EXT : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_NA : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_PLLI2S : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_PLLSAI : stm32f7xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32f7xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32f7xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32f7xx_hal_sai.c
  • SAI_Disable() : stm32f7xx_hal_sai.c
  • SAI_DMAError() : stm32f7xx_hal_sai.c
  • SAI_DMARxCplt() : stm32f7xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32f7xx_hal_sai.c
  • SAI_DMATxCplt() : stm32f7xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32f7xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32f7xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32f7xx_hal_sai.h
  • SAI_FillFifo() : stm32f7xx_hal_sai.c
  • SAI_FIRSTBIT_LSB : stm32f7xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32f7xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32f7xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32f7xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32f7xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32f7xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32f7xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32f7xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32f7xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32f7xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32f7xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32f7xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32f7xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32f7xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32f7xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32f7xx_hal_sai.h
  • SAI_GetInputClock() : stm32f7xx_hal_sai_ex.c
  • SAI_HandleTypeDef : stm32f7xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32f7xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32f7xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32f7xx_hal_sai.h
  • SAI_InitI2S() : stm32f7xx_hal_sai.c
  • SAI_InitPCM() : stm32f7xx_hal_sai.c
  • SAI_InterruptFlag() : stm32f7xx_hal_sai.c
  • SAI_IT_AFSDET : stm32f7xx_hal_sai.h
  • SAI_IT_CNRDY : stm32f7xx_hal_sai.h
  • SAI_IT_FREQ : stm32f7xx_hal_sai.h
  • SAI_IT_LFSDET : stm32f7xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32f7xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32f7xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32f7xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32f7xx_hal_sai.h
  • SAI_MASTERDIVIDER_DISABLE : stm32f7xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32f7xx_hal_sai.h
  • SAI_MODE_DMA : stm32f7xx_hal_sai.c
  • SAI_MODE_IT : stm32f7xx_hal_sai.c
  • SAI_MODEMASTER_RX : stm32f7xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32f7xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32f7xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32f7xx_hal_sai.h
  • SAI_ModeTypedef : stm32f7xx_hal_sai.c
  • SAI_MONOMODE : stm32f7xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32f7xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32f7xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32f7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32f7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32f7xx_hal_sai.h
  • SAI_PCM_LONG : stm32f7xx_hal_sai.h
  • SAI_PCM_SHORT : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32f7xx_hal_sai.h
  • SAI_Receive_IT16Bit() : stm32f7xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32f7xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32f7xx_hal_sai.c
  • SAI_SLOT_NOTACTIVE : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32f7xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32f7xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32f7xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32f7xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32f7xx_hal_sai.h
  • SAI_STEREOMODE : stm32f7xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32f7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32f7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32f7xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32f7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32f7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32f7xx_hal_sai.h
  • SAI_TIMEOUT_VALUE : stm32f7xx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32f7xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32f7xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32f7xx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_xCR2_MUTECNT_OFFSET : stm32f7xx_hal_sai.c
  • SAI_ZERO_VALUE : stm32f7xx_hal_sai.h
  • SAIcallback : stm32f7xx_hal_sai.h
  • SD_0TO7BITS : stm32f7xx_hal_sd.c
  • SD_16TO23BITS : stm32f7xx_hal_sd.c
  • SD_24TO31BITS : stm32f7xx_hal_sd.c
  • SD_8TO15BITS : stm32f7xx_hal_sd.c
  • SD_ADDR_MISALIGNED : stm32f7xx_hal_sd.h
  • SD_ADDR_OUT_OF_RANGE : stm32f7xx_hal_sd.h
  • SD_AKE_SEQ_ERROR : stm32f7xx_hal_sd.h
  • SD_ALLZERO : stm32f7xx_hal_sd.c
  • SD_BAD_ERASE_PARAM : stm32f7xx_hal_sd.h
  • SD_BLOCK_LEN_ERR : stm32f7xx_hal_sd.h
  • SD_CARD_DISCONNECTED : stm32f7xx_hal_sd.h
  • SD_CARD_ECC_DISABLED : stm32f7xx_hal_sd.h
  • SD_CARD_ECC_FAILED : stm32f7xx_hal_sd.h
  • SD_CARD_ERROR : stm32f7xx_hal_sd.h
  • SD_CARD_IDENTIFICATION : stm32f7xx_hal_sd.h
  • SD_CARD_LOCKED : stm32f7xx_hal_sd.c
  • SD_CARD_PROGRAMMING : stm32f7xx_hal_sd.h
  • SD_CARD_READY : stm32f7xx_hal_sd.h
  • SD_CARD_RECEIVING : stm32f7xx_hal_sd.h
  • SD_CARD_SENDING : stm32f7xx_hal_sd.h
  • SD_CARD_STANDBY : stm32f7xx_hal_sd.h
  • SD_CARD_TRANSFER : stm32f7xx_hal_sd.h
  • SD_CC_ERROR : stm32f7xx_hal_sd.h
  • SD_CCCC_ERASE : stm32f7xx_hal_sd.c
  • SD_CCCC_LOCK_UNLOCK : stm32f7xx_hal_sd.c
  • SD_CCCC_WRITE_PROT : stm32f7xx_hal_sd.c
  • SD_CHECK_PATTERN : stm32f7xx_hal_sd.c
  • SD_CID_CSD_OVERWRITE : stm32f7xx_hal_sd.h
  • SD_CMD_ALL_SEND_CID : stm32f7xx_hal_sd.h
  • SD_CMD_APP_CMD : stm32f7xx_hal_sd.h
  • SD_CMD_APP_SD_SET_BUSWIDTH : stm32f7xx_hal_sd.h
  • SD_CMD_CLR_WRITE_PROT : stm32f7xx_hal_sd.h
  • SD_CMD_CRC_FAIL : stm32f7xx_hal_sd.h
  • SD_CMD_ERASE : stm32f7xx_hal_sd.h
  • SD_CMD_ERASE_GRP_END : stm32f7xx_hal_sd.h
  • SD_CMD_ERASE_GRP_START : stm32f7xx_hal_sd.h
  • SD_CMD_FAST_IO : stm32f7xx_hal_sd.h
  • SD_CMD_GEN_CMD : stm32f7xx_hal_sd.h
  • SD_CMD_GO_IDLE_STATE : stm32f7xx_hal_sd.h
  • SD_CMD_GO_INACTIVE_STATE : stm32f7xx_hal_sd.h
  • SD_CMD_GO_IRQ_STATE : stm32f7xx_hal_sd.h
  • SD_CMD_HS_BUSTEST_READ : stm32f7xx_hal_sd.h
  • SD_CMD_HS_BUSTEST_WRITE : stm32f7xx_hal_sd.h
  • SD_CMD_HS_SEND_EXT_CSD : stm32f7xx_hal_sd.h
  • SD_CMD_HS_SWITCH : stm32f7xx_hal_sd.h
  • SD_CMD_LOCK_UNLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_NO_CMD : stm32f7xx_hal_sd.h
  • SD_CMD_OUT_OF_RANGE : stm32f7xx_hal_sd.h
  • SD_CMD_PROG_CID : stm32f7xx_hal_sd.h
  • SD_CMD_PROG_CSD : stm32f7xx_hal_sd.h
  • SD_CMD_READ_DAT_UNTIL_STOP : stm32f7xx_hal_sd.h
  • SD_CMD_READ_MULT_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_READ_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_RSP_TIMEOUT : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_CHANGE_SECURE_AREA : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_CER_RES1 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_CER_RN2 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_MID : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_MKB : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_OP_COND : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_ERASE : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MKB : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SEND_SCR : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SET_CER_RES2 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SET_CER_RN1 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SET_CLR_CARD_DETECT : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_STATUS : stm32f7xx_hal_sd.h
  • SD_CMD_SD_ERASE_GRP_END : stm32f7xx_hal_sd.h
  • SD_CMD_SD_ERASE_GRP_START : stm32f7xx_hal_sd.h
  • SD_CMD_SDMMC_RW_DIRECT : stm32f7xx_hal_sd.h
  • SD_CMD_SDMMC_RW_EXTENDED : stm32f7xx_hal_sd.h
  • SD_CMD_SDMMC_SEN_OP_COND : stm32f7xx_hal_sd.h
  • SD_CMD_SEL_DESEL_CARD : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_CID : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_CSD : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_OP_COND : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_STATUS : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_WRITE_PROT : stm32f7xx_hal_sd.h
  • SD_CMD_SET_BLOCK_COUNT : stm32f7xx_hal_sd.h
  • SD_CMD_SET_BLOCKLEN : stm32f7xx_hal_sd.h
  • SD_CMD_SET_DSR : stm32f7xx_hal_sd.h
  • SD_CMD_SET_REL_ADDR : stm32f7xx_hal_sd.h
  • SD_CMD_SET_WRITE_PROT : stm32f7xx_hal_sd.h
  • SD_CMD_STOP_TRANSMISSION : stm32f7xx_hal_sd.h
  • SD_CMD_WRITE_DAT_UNTIL_STOP : stm32f7xx_hal_sd.h
  • SD_CMD_WRITE_MULT_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_WRITE_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CmdError() : stm32f7xx_hal_sd.c
  • SD_CmdResp1Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp2Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp3Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp6Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp7Error() : stm32f7xx_hal_sd.c
  • SD_COM_CRC_FAILED : stm32f7xx_hal_sd.h
  • SD_DATA_CRC_FAIL : stm32f7xx_hal_sd.h
  • SD_DATA_TIMEOUT : stm32f7xx_hal_sd.h
  • SD_DATATIMEOUT : stm32f7xx_hal_sd.c
  • SD_DMA_RxCplt() : stm32f7xx_hal_sd.c
  • SD_DMA_RxError() : stm32f7xx_hal_sd.c
  • SD_DMA_TxCplt() : stm32f7xx_hal_sd.c
  • SD_DMA_TxError() : stm32f7xx_hal_sd.c
  • SD_ERASE_RESET : stm32f7xx_hal_sd.h
  • SD_ERASE_SEQ_ERR : stm32f7xx_hal_sd.h
  • SD_ERROR : stm32f7xx_hal_sd.h
  • SD_FindSCR() : stm32f7xx_hal_sd.c
  • SD_GENERAL_UNKNOWN_ERROR : stm32f7xx_hal_sd.h
  • SD_GetState() : stm32f7xx_hal_sd.c
  • SD_HALFFIFO : stm32f7xx_hal_sd.c
  • SD_HALFFIFOBYTES : stm32f7xx_hal_sd.c
  • SD_HIGH_CAPACITY : stm32f7xx_hal_sd.c
  • SD_ILLEGAL_CMD : stm32f7xx_hal_sd.h
  • SD_Initialize_Cards() : stm32f7xx_hal_sd.c
  • SD_InitTypeDef : stm32f7xx_hal_sd.h
  • SD_INTERNAL_ERROR : stm32f7xx_hal_sd.h
  • SD_INVALID_PARAMETER : stm32f7xx_hal_sd.h
  • SD_INVALID_VOLTRANGE : stm32f7xx_hal_sd.h
  • SD_IsCardProgramming() : stm32f7xx_hal_sd.c
  • SD_LOCK_UNLOCK_FAILED : stm32f7xx_hal_sd.h
  • SD_MAX_DATA_LENGTH : stm32f7xx_hal_sd.c
  • SD_MAX_VOLT_TRIAL : stm32f7xx_hal_sd.c
  • SD_NOT_CONFIGURED : stm32f7xx_hal_sd.h
  • SD_OCR_ADDR_MISALIGNED : stm32f7xx_hal_sd.c
  • SD_OCR_ADDR_OUT_OF_RANGE : stm32f7xx_hal_sd.c
  • SD_OCR_AKE_SEQ_ERROR : stm32f7xx_hal_sd.c
  • SD_OCR_BAD_ERASE_PARAM : stm32f7xx_hal_sd.c
  • SD_OCR_BLOCK_LEN_ERR : stm32f7xx_hal_sd.c
  • SD_OCR_CARD_ECC_DISABLED : stm32f7xx_hal_sd.c
  • SD_OCR_CARD_ECC_FAILED : stm32f7xx_hal_sd.c
  • SD_OCR_CC_ERROR : stm32f7xx_hal_sd.c
  • SD_OCR_CID_CSD_OVERWRITE : stm32f7xx_hal_sd.c
  • SD_OCR_COM_CRC_FAILED : stm32f7xx_hal_sd.c
  • SD_OCR_ERASE_RESET : stm32f7xx_hal_sd.c
  • SD_OCR_ERASE_SEQ_ERR : stm32f7xx_hal_sd.c
  • SD_OCR_ERRORBITS : stm32f7xx_hal_sd.c
  • SD_OCR_GENERAL_UNKNOWN_ERROR : stm32f7xx_hal_sd.c
  • SD_OCR_ILLEGAL_CMD : stm32f7xx_hal_sd.c
  • SD_OCR_LOCK_UNLOCK_FAILED : stm32f7xx_hal_sd.c
  • SD_OCR_STREAM_READ_UNDERRUN : stm32f7xx_hal_sd.c
  • SD_OCR_STREAM_WRITE_OVERRUN : stm32f7xx_hal_sd.c
  • SD_OCR_WP_ERASE_SKIP : stm32f7xx_hal_sd.c
  • SD_OCR_WRITE_PROT_VIOLATION : stm32f7xx_hal_sd.c
  • SD_OK : stm32f7xx_hal_sd.h
  • SD_PowerOFF() : stm32f7xx_hal_sd.c
  • SD_PowerON() : stm32f7xx_hal_sd.c
  • SD_R6_COM_CRC_FAILED : stm32f7xx_hal_sd.c
  • SD_R6_GENERAL_UNKNOWN_ERROR : stm32f7xx_hal_sd.c
  • SD_R6_ILLEGAL_CMD : stm32f7xx_hal_sd.c
  • SD_READ_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_READ_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_REQUEST_NOT_APPLICABLE : stm32f7xx_hal_sd.h
  • SD_REQUEST_PENDING : stm32f7xx_hal_sd.h
  • SD_RX_OVERRUN : stm32f7xx_hal_sd.h
  • SD_SDMMC_DISABLED : stm32f7xx_hal_sd.h
  • SD_SDMMC_FUNCTION_BUSY : stm32f7xx_hal_sd.h
  • SD_SDMMC_FUNCTION_FAILED : stm32f7xx_hal_sd.h
  • SD_SDMMC_SEND_IF_COND : stm32f7xx_hal_sd.c
  • SD_SDMMC_UNKNOWN_FUNCTION : stm32f7xx_hal_sd.h
  • SD_Select_Deselect() : stm32f7xx_hal_sd.c
  • SD_SendStatus() : stm32f7xx_hal_sd.c
  • SD_SINGLE_BUS_SUPPORT : stm32f7xx_hal_sd.c
  • SD_START_BIT_ERR : stm32f7xx_hal_sd.h
  • SD_STD_CAPACITY : stm32f7xx_hal_sd.c
  • SD_STREAM_READ_UNDERRUN : stm32f7xx_hal_sd.h
  • SD_STREAM_WRITE_OVERRUN : stm32f7xx_hal_sd.h
  • SD_SWITCH_ERROR : stm32f7xx_hal_sd.h
  • SD_TRANSFER_BUSY : stm32f7xx_hal_sd.h
  • SD_TRANSFER_ERROR : stm32f7xx_hal_sd.h
  • SD_TRANSFER_OK : stm32f7xx_hal_sd.h
  • SD_TX_UNDERRUN : stm32f7xx_hal_sd.h
  • SD_TypeDef : stm32f7xx_hal_sd.h
  • SD_UNSUPPORTED_FEATURE : stm32f7xx_hal_sd.h
  • SD_UNSUPPORTED_HW : stm32f7xx_hal_sd.h
  • SD_VOLTAGE_WINDOW_SD : stm32f7xx_hal_sd.c
  • SD_WIDE_BUS_SUPPORT : stm32f7xx_hal_sd.c
  • SD_WideBus_Disable() : stm32f7xx_hal_sd.c
  • SD_WideBus_Enable() : stm32f7xx_hal_sd.c
  • SD_WP_ERASE_SKIP : stm32f7xx_hal_sd.h
  • SD_WRITE_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_WRITE_PROT_VIOLATION : stm32f7xx_hal_sd.h
  • SD_WRITE_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SDMMC_CMD0TIMEOUT : stm32f7xx_hal_sd.c
  • SDMMC_STATIC_FLAGS : stm32f7xx_hal_sd.c
  • SECTOR_MASK : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c
  • SECURE_DIGITAL_IO_CARD : stm32f7xx_hal_sd.h
  • SECURE_DIGITAL_IO_COMBO_CARD : stm32f7xx_hal_sd.h
  • SLOTR_CLEAR_MASK : stm32f7xx_hal_sai.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_AdvFeatureConfig() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_FEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_IDLEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_NEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_OREF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_PEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_RTOF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_TCF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32f7xx_hal_smartcard.h
  • SMARTCARD_DMAError() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_DMAREQ_RX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_TX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_DMATransmitCplt() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_FLAG_BUSY : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_EOBF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_FE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_REACK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_RTOF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_TEACK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_GETCLOCKSOURCE : stm32f7xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_FE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_ORE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_RTO : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f7xx_hal_smartcard.h
  • SMARTCARD_Receive_IT() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32f7xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_smartcard.h
  • SMARTCARD_SetConfig() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_1_5 : stm32f7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_Transmit_IT() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_smartcard.h
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32f7xx_hal_smartcard.h
  • SPDIFRX_CHANNEL_A : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_CHANNEL_B : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_32BITS : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_LSB : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_MSB : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DMACxCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMACxHalfCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMAError() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMARxCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMARxHalfCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_FLAG_CSRNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_FERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_OVR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_PERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_RXNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SBD : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SYNCD : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_TERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN0 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN1 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN2 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN3 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_CSRNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_IFEIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_OVRIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_PERRIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_RXNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_SBLKIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_SYNCDIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_15 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_3 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_63 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_NONE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_ReceiveControlFlow_IT() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveDataFlow_IT() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_STATE_IDLE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STATE_RCV : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STATE_SYNC : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_DISABLE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_ENABLE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_TIMEOUT_VALUE : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_VALIDITYMASK_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_VALIDITYMASK_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_WaitOnFlagUntilTimeout() : stm32f7xx_hal_spdifrx.c
  • SPI_1LINE_RX : stm32f7xx_hal_spi.h
  • SPI_1LINE_TX : stm32f7xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32f7xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32f7xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f7xx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32f7xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f7xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f7xx_hal_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32f7xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32f7xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32f7xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32f7xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32f7xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f7xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f7xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f7xx_hal_spi.h
  • SPI_DMAError() : stm32f7xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f7xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f7xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32f7xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32f7xx_hal_spi.c
  • SPI_FIRSTBIT_LSB : stm32f7xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f7xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f7xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f7xx_hal_spi.h
  • SPI_FLAG_FRE : stm32f7xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32f7xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32f7xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f7xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f7xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f7xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f7xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32f7xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32f7xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32f7xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32f7xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32f7xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32f7xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32f7xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32f7xx_hal_spi.h
  • SPI_HandleTypeDef : stm32f7xx_hal_spi.h
  • SPI_IT_ERR : stm32f7xx_hal_spi.h
  • SPI_IT_RXNE : stm32f7xx_hal_spi.h
  • SPI_IT_TXE : stm32f7xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f7xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f7xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f7xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f7xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32f7xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32f7xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f7xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f7xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f7xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f7xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f7xx_hal_spi.h
  • SPI_RESET_CRC : stm32f7xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32f7xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32f7xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32f7xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32f7xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32f7xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32f7xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32f7xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32f7xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f7xx_hal_spi.c
  • STD_CAPACITY_SD_CARD_V1_1 : stm32f7xx_hal_sd.h
  • STD_CAPACITY_SD_CARD_V2_0 : stm32f7xx_hal_sd.h
  • SYSTICK_CLKSOURCE_HCLK : stm32f7xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f7xx_hal_cortex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TEACK_REACK_TIMEOUT : stm32f7xx_hal_irda.c , stm32f7xx_hal_smartcard.c , stm32f7xx_hal_usart.c
  • TICK_INT_PRIORITY : stm32f7xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f7xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f7xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32f7xx_hal_tim.h , stm32f7xx_hal_tim.c
  • TIM_BREAK2_DISABLE : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK2_ENABLE : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_HIGH : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_LOW : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK_DISABLE : stm32f7xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f7xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f7xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f7xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32f7xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f7xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f7xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f7xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32f7xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f7xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32f7xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_2 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_3 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_4 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_5 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_6 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_ALL : stm32f7xx_hal_tim_ex.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_OCREFCLR : stm32f7xx_hal_tim_ex.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f7xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f7xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f7xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f7xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f7xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f7xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f7xx_hal_tim.h
  • TIM_DMA_COM : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f7xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f7xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32f7xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_OR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32f7xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_SR : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMAPeriodElapsedCplt() : stm32f7xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f7xx_hal_tim.c
  • TIM_ENCODERMODE_TI1 : stm32f7xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f7xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f7xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32f7xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32f7xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_COM : stm32f7xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f7xx_hal_tim.h
  • TIM_GROUPCH5_NONE : stm32f7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC1REFC : stm32f7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC2REFC : stm32f7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC3REFC : stm32f7xx_hal_tim_ex.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f7xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f7xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f7xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_IT_BREAK : stm32f7xx_hal_tim.h
  • TIM_IT_CC1 : stm32f7xx_hal_tim.h
  • TIM_IT_CC2 : stm32f7xx_hal_tim.h
  • TIM_IT_CC3 : stm32f7xx_hal_tim.h
  • TIM_IT_CC4 : stm32f7xx_hal_tim.h
  • TIM_IT_COM : stm32f7xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f7xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC2_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC4_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC5_SetConfig() : stm32f7xx_hal_tim_ex.c
  • TIM_OC6_SetConfig() : stm32f7xx_hal_tim_ex.c
  • TIM_OCFAST_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f7xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f7xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_INACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_TIMING : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_TOGGLE : stm32f7xx_hal_tim_ex.h
  • TIM_OCNIDLESTATE_RESET : stm32f7xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f7xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f7xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f7xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f7xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f7xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f7xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f7xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32f7xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f7xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f7xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f7xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f7xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_DISABLE : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_GATED : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_RESET : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_TRIGGER : stm32f7xx_hal_tim_ex.h
  • TIM_SlaveTimer_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f7xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32f7xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f7xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32f7xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TIM11_GPIO : stm32f7xx_hal_tim_ex.h
  • TIM_TIM11_HSE : stm32f7xx_hal_tim_ex.h
  • TIM_TIM11_MCO1 : stm32f7xx_hal_tim_ex.h
  • TIM_TIM11_SPDIFRX : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_ETH_PTP : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_TIM8_TRGO : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_USBFS_SOF : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_USBHS_SOF : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_GPIO : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_LSE : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_LSI : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_RTC : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC1 : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC1REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC2REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC3REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC5REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC6REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_RESET : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_UPDATE : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO_ENABLE : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f7xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_TS_ETRF : stm32f7xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f7xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f7xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f7xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f7xx_hal_tim.h
  • TIM_TS_NONE : stm32f7xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f7xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f7xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f7xx_hal_tim.h
  • TIMING_CLEAR_MASK : stm32f7xx_hal_i2c.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
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  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32f7xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32f7xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32f7xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32f7xx_hal_uart.h
  • UART_CheckIdleState() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • UART_CLEAR_CMF : stm32f7xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32f7xx_hal_uart.h
  • UART_CLEAR_EOBF : stm32f7xx_hal_uart.h
  • UART_CLEAR_FEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32f7xx_hal_uart.h
  • UART_CLEAR_NEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_OREF : stm32f7xx_hal_uart.h
  • UART_CLEAR_PEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32f7xx_hal_uart.h
  • UART_CLEAR_TCF : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32f7xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32f7xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32f7xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32f7xx_hal_uart.h
  • UART_CR1_FIELDS : stm32f7xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32f7xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32f7xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32f7xx_hal_uart.h
  • UART_DIV_LPUART : stm32f7xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f7xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f7xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32f7xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32f7xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32f7xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32f7xx_hal_uart.h
  • UART_DMAError() : stm32f7xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f7xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f7xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f7xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f7xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f7xx_hal_uart.c
  • UART_FLAG_ABRE : stm32f7xx_hal_uart.h
  • UART_FLAG_ABRF : stm32f7xx_hal_uart.h
  • UART_FLAG_BUSY : stm32f7xx_hal_uart.h
  • UART_FLAG_CMF : stm32f7xx_hal_uart.h
  • UART_FLAG_CTS : stm32f7xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32f7xx_hal_uart.h
  • UART_FLAG_EOBF : stm32f7xx_hal_uart.h
  • UART_FLAG_FE : stm32f7xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f7xx_hal_uart.h
  • UART_FLAG_LBDF : stm32f7xx_hal_uart.h
  • UART_FLAG_NE : stm32f7xx_hal_uart.h
  • UART_FLAG_ORE : stm32f7xx_hal_uart.h
  • UART_FLAG_PE : stm32f7xx_hal_uart.h
  • UART_FLAG_RTOF : stm32f7xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f7xx_hal_uart.h
  • UART_FLAG_SBKF : stm32f7xx_hal_uart.h
  • UART_FLAG_TC : stm32f7xx_hal_uart.h
  • UART_FLAG_TEACK : stm32f7xx_hal_uart.h
  • UART_FLAG_TXE : stm32f7xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32f7xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32f7xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f7xx_hal_uart.h
  • UART_IT_CM : stm32f7xx_hal_uart.h
  • UART_IT_CTS : stm32f7xx_hal_uart.h
  • UART_IT_ERR : stm32f7xx_hal_uart.h
  • UART_IT_FE : stm32f7xx_hal_uart.h
  • UART_IT_IDLE : stm32f7xx_hal_uart.h
  • UART_IT_LBD : stm32f7xx_hal_uart.h
  • UART_IT_MASK : stm32f7xx_hal_uart.h
  • UART_IT_NE : stm32f7xx_hal_uart.h
  • UART_IT_ORE : stm32f7xx_hal_uart.h
  • UART_IT_PE : stm32f7xx_hal_uart.h
  • UART_IT_RXNE : stm32f7xx_hal_uart.h
  • UART_IT_TC : stm32f7xx_hal_uart.h
  • UART_IT_TXE : stm32f7xx_hal_uart.h
  • UART_LIN_DISABLE : stm32f7xx_hal_uart.h
  • UART_LIN_ENABLE : stm32f7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f7xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32f7xx_hal_uart_ex.h
  • UART_MODE_RX : stm32f7xx_hal_uart.h
  • UART_MODE_TX : stm32f7xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f7xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32f7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f7xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32f7xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f7xx_hal_uart.h
  • UART_PARITY_NONE : stm32f7xx_hal_uart.h
  • UART_PARITY_ODD : stm32f7xx_hal_uart.h
  • UART_Receive_IT() : stm32f7xx_hal_uart.c
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32f7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32f7xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32f7xx_hal_uart.h
  • UART_SetConfig() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • UART_STATE_DISABLE : stm32f7xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f7xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f7xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f7xx_hal_uart.h
  • UART_Transmit_IT() : stm32f7xx_hal_uart.c
  • UART_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_uart.h
  • UART_WaitOnFlagUntilTimeout() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f7xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f7xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32f7xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32f7xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32f7xx_hal_uart_ex.h
  • USART_CheckIdleState() : stm32f7xx_hal_usart.c
  • USART_CLEAR_CTSF : stm32f7xx_hal_usart.h
  • USART_CLEAR_FEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_NEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_OREF : stm32f7xx_hal_usart.h
  • USART_CLEAR_PEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_TCF : stm32f7xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f7xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32f7xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32f7xx_hal_usart.h
  • USART_CR1_FIELDS : stm32f7xx_hal_usart.c , stm32f7xx_hal_smartcard.c
  • USART_CR2_CLK_FIELDS : stm32f7xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32f7xx_hal_smartcard.c , stm32f7xx_hal_usart.c
  • USART_CR3_FIELDS : stm32f7xx_hal_smartcard.c
  • USART_DMAError() : stm32f7xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f7xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f7xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f7xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f7xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f7xx_hal_usart.c
  • USART_FLAG_BUSY : stm32f7xx_hal_usart.h
  • USART_FLAG_CTS : stm32f7xx_hal_usart.h
  • USART_FLAG_CTSIF : stm32f7xx_hal_usart.h
  • USART_FLAG_FE : stm32f7xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f7xx_hal_usart.h
  • USART_FLAG_LBDF : stm32f7xx_hal_usart.h
  • USART_FLAG_NE : stm32f7xx_hal_usart.h
  • USART_FLAG_ORE : stm32f7xx_hal_usart.h
  • USART_FLAG_PE : stm32f7xx_hal_usart.h
  • USART_FLAG_REACK : stm32f7xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f7xx_hal_usart.h
  • USART_FLAG_TC : stm32f7xx_hal_usart.h
  • USART_FLAG_TEACK : stm32f7xx_hal_usart.h
  • USART_FLAG_TXE : stm32f7xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32f7xx_hal_usart.h
  • USART_IT_ERR : stm32f7xx_hal_usart.h
  • USART_IT_FE : stm32f7xx_hal_usart.h
  • USART_IT_IDLE : stm32f7xx_hal_usart.h
  • USART_IT_MASK : stm32f7xx_hal_usart.h
  • USART_IT_NE : stm32f7xx_hal_usart.h
  • USART_IT_ORE : stm32f7xx_hal_usart.h
  • USART_IT_PE : stm32f7xx_hal_usart.h
  • USART_IT_RXNE : stm32f7xx_hal_usart.h
  • USART_IT_TC : stm32f7xx_hal_usart.h
  • USART_IT_TXE : stm32f7xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f7xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f7xx_hal_usart.h
  • USART_MODE_RX : stm32f7xx_hal_usart.h
  • USART_MODE_TX : stm32f7xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f7xx_hal_usart.h
  • USART_OVERSAMPLING_16 : stm32f7xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32f7xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f7xx_hal_usart.h
  • USART_PARITY_NONE : stm32f7xx_hal_usart.h
  • USART_PARITY_ODD : stm32f7xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f7xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f7xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f7xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f7xx_hal_usart.h
  • USART_Receive_IT() : stm32f7xx_hal_usart.c
  • USART_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_usart.h
  • USART_SetConfig() : stm32f7xx_hal_usart.c
  • USART_STOPBITS_1 : stm32f7xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f7xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f7xx_hal_usart.h
  • USART_TIMEOUT_VALUE : stm32f7xx_hal_usart.c
  • USART_Transmit_IT() : stm32f7xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f7xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_usart.h
  • USART_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f7xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32f7xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32f7xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32f7xx_hal_usart_ex.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32f7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_LINE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32f7xx_hal_pcd.h
  • USBD_HS_TRDT_VALUE : stm32f7xx_hal_pcd.h
  • USE_RTOS : stm32f7xx_hal_conf.h
  • uwTick : stm32f7xx_hal.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_FLAG_EWIF : stm32f7xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f7xx_hal_wwdg.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- a -

  • ADC_DMAConvCplt() : stm32f7xx_hal_adc.c
  • ADC_DMAError() : stm32f7xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32f7xx_hal_adc.c
  • ADC_Init() : stm32f7xx_hal_adc.c
  • ADC_MultiModeDMAConvCplt() : stm32f7xx_hal_adc_ex.c
  • ADC_MultiModeDMAError() : stm32f7xx_hal_adc_ex.c
  • ADC_MultiModeDMAHalfConvCplt() : stm32f7xx_hal_adc_ex.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- c -

  • CAN_Receive_IT() : stm32f7xx_hal_can.c
  • CAN_Transmit_IT() : stm32f7xx_hal_can.c
  • CEC_Receive_IT() : stm32f7xx_hal_cec.c
  • CEC_Transmit_IT() : stm32f7xx_hal_cec.c
  • CRC_Handle_16() : stm32f7xx_hal_crc.c
  • CRC_Handle_8() : stm32f7xx_hal_crc.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- d -

  • DAC_DMAConvCpltCh1() : stm32f7xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • DAC_DMAErrorCh1() : stm32f7xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • DAC_DMAHalfConvCpltCh1() : stm32f7xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • DCMI_DMAConvCplt() : stm32f7xx_hal_dcmi.c
  • DCMI_DMAError() : stm32f7xx_hal_dcmi.c
  • DMA2D_SetConfig() : stm32f7xx_hal_dma2d.c
  • DMA_CalcBaseAndBitshift() : stm32f7xx_hal_dma.c
  • DMA_MultiBufferSetConfig() : stm32f7xx_hal_dma_ex.c
  • DMA_SetConfig() : stm32f7xx_hal_dma.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- e -

  • ETH_DMAReceptionDisable() : stm32f7xx_hal_eth.c
  • ETH_DMAReceptionEnable() : stm32f7xx_hal_eth.c
  • ETH_DMATransmissionDisable() : stm32f7xx_hal_eth.c
  • ETH_DMATransmissionEnable() : stm32f7xx_hal_eth.c
  • ETH_FlushTransmitFIFO() : stm32f7xx_hal_eth.c
  • ETH_MACAddressConfig() : stm32f7xx_hal_eth.c
  • ETH_MACDMAConfig() : stm32f7xx_hal_eth.c
  • ETH_MACReceptionDisable() : stm32f7xx_hal_eth.c
  • ETH_MACReceptionEnable() : stm32f7xx_hal_eth.c
  • ETH_MACTransmissionDisable() : stm32f7xx_hal_eth.c
  • ETH_MACTransmissionEnable() : stm32f7xx_hal_eth.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- f -

  • FLASH_Erase_Sector() : stm32f7xx_hal_flash_ex.c , stm32f7xx_hal_flash_ex.h
  • FLASH_MassErase() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_BootAddressConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetBootAddress() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f7xx_hal_flash_ex.c
  • FLASH_Program_Byte() : stm32f7xx_hal_flash.c
  • FLASH_Program_DoubleWord() : stm32f7xx_hal_flash.c
  • FLASH_Program_HalfWord() : stm32f7xx_hal_flash.c
  • FLASH_Program_Word() : stm32f7xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32f7xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c , stm32f7xx_hal_flash.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f7xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32f7xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f7xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f7xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f7xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f7xx_hal_adc.c
  • HAL_ADC_Init() : stm32f7xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32f7xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f7xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32f7xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f7xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f7xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32f7xx_hal_adc.c
  • HAL_ADC_Start() : stm32f7xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f7xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32f7xx_hal_adc.c
  • HAL_ADC_Stop() : stm32f7xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f7xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32f7xx_hal_adc.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32f7xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32f7xx_hal_adc_ex.c
  • HAL_CAN_ConfigFilter() : stm32f7xx_hal_can.c
  • HAL_CAN_DeInit() : stm32f7xx_hal_can.c
  • HAL_CAN_ErrorCallback() : stm32f7xx_hal_can.c
  • HAL_CAN_GetError() : stm32f7xx_hal_can.c
  • HAL_CAN_GetState() : stm32f7xx_hal_can.c
  • HAL_CAN_Init() : stm32f7xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32f7xx_hal_can.c
  • HAL_CAN_MspDeInit() : stm32f7xx_hal_can.c
  • HAL_CAN_MspInit() : stm32f7xx_hal_can.c
  • HAL_CAN_Receive() : stm32f7xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32f7xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32f7xx_hal_can.c
  • HAL_CAN_Sleep() : stm32f7xx_hal_can.c
  • HAL_CAN_Transmit() : stm32f7xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32f7xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32f7xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32f7xx_hal_can.c
  • HAL_CEC_DeInit() : stm32f7xx_hal_cec.c
  • HAL_CEC_ErrorCallback() : stm32f7xx_hal_cec.c
  • HAL_CEC_GetError() : stm32f7xx_hal_cec.c
  • HAL_CEC_GetReceivedFrameSize() : stm32f7xx_hal_cec.c
  • HAL_CEC_GetState() : stm32f7xx_hal_cec.c
  • HAL_CEC_Init() : stm32f7xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32f7xx_hal_cec.c
  • HAL_CEC_MspDeInit() : stm32f7xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32f7xx_hal_cec.c
  • HAL_CEC_Receive() : stm32f7xx_hal_cec.c
  • HAL_CEC_Receive_IT() : stm32f7xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32f7xx_hal_cec.c
  • HAL_CEC_Transmit() : stm32f7xx_hal_cec.c
  • HAL_CEC_Transmit_IT() : stm32f7xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32f7xx_hal_cec.c
  • HAL_CRC_Accumulate() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_Calculate() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_DeInit() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_GetState() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_Init() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_MspDeInit() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRC_MspInit() : stm32f7xx_hal_crc.c , stm32f7xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32f7xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32f7xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32f7xx_hal_crc_ex.c
  • HAL_DAC_ConfigChannel() : stm32f7xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_DeInit() : stm32f7xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_GetError() : stm32f7xx_hal_dac.c
  • HAL_DAC_GetState() : stm32f7xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32f7xx_hal_dac.c
  • HAL_DAC_Init() : stm32f7xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32f7xx_hal_dac.c , stm32f7xx_hal_dac.h
  • HAL_DAC_MspDeInit() : stm32f7xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32f7xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32f7xx_hal_dac.c
  • HAL_DAC_Start() : stm32f7xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32f7xx_hal_dac.c
  • HAL_DAC_Stop() : stm32f7xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32f7xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_DualGetValue() : stm32f7xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32f7xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32f7xx_hal_dac_ex.c , stm32f7xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32f7xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32f7xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f7xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f7xx_hal.c
  • HAL_DCMI_ConfigCROP() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_DeInit() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_DisableCROP() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_EnableCROP() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_ErrorCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_FrameEventCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_GetError() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_GetState() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_Init() : stm32f7xx_hal_dcmi.c , stm32f7xx_hal_dcmi_ex.c
  • HAL_DCMI_IRQHandler() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_LineEventCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_MspDeInit() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_MspInit() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_Start_DMA() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_Stop() : stm32f7xx_hal_dcmi.c
  • HAL_DCMI_VsyncEventCallback() : stm32f7xx_hal_dcmi.c
  • HAL_DeInit() : stm32f7xx_hal.c
  • HAL_Delay() : stm32f7xx_hal.c
  • HAL_DisableCompensationCell() : stm32f7xx_hal.c
  • HAL_DisableFMCMemorySwapping() : stm32f7xx_hal.c
  • HAL_DMA2D_Abort() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_BlendingStart() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_BlendingStart_IT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ConfigCLUT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ConfigLayer() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_DeInit() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_DisableCLUT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_EnableCLUT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_GetError() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_GetState() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Init() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_IRQHandler() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_MspDeInit() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_MspInit() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_PollForTransfer() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ProgramLineEvent() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Resume() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Start() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Start_IT() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_Suspend() : stm32f7xx_hal_dma2d.c , stm32f7xx_hal_dma2d.h
  • HAL_DMA_Abort() : stm32f7xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32f7xx_hal_dma.c
  • HAL_DMA_GetError() : stm32f7xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f7xx_hal_dma.c
  • HAL_DMA_Init() : stm32f7xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f7xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32f7xx_hal_dma.c
  • HAL_DMA_Start() : stm32f7xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f7xx_hal_dma.c
  • HAL_DMAEx_ChangeMemory() : stm32f7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32f7xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32f7xx_hal_dma_ex.c
  • HAL_EnableCompensationCell() : stm32f7xx_hal.c
  • HAL_EnableFMCMemorySwapping() : stm32f7xx_hal.c
  • HAL_ETH_ConfigDMA() : stm32f7xx_hal_eth.c
  • HAL_ETH_ConfigMAC() : stm32f7xx_hal_eth.c
  • HAL_ETH_DeInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_DMARxDescListInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_DMATxDescListInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_ErrorCallback() : stm32f7xx_hal_eth.c
  • HAL_ETH_GetReceivedFrame() : stm32f7xx_hal_eth.c
  • HAL_ETH_GetReceivedFrame_IT() : stm32f7xx_hal_eth.c
  • HAL_ETH_GetState() : stm32f7xx_hal_eth.c
  • HAL_ETH_Init() : stm32f7xx_hal_eth.c
  • HAL_ETH_IRQHandler() : stm32f7xx_hal_eth.c
  • HAL_ETH_MspDeInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_MspInit() : stm32f7xx_hal_eth.c
  • HAL_ETH_ReadPHYRegister() : stm32f7xx_hal_eth.c
  • HAL_ETH_RxCpltCallback() : stm32f7xx_hal_eth.c
  • HAL_ETH_Start() : stm32f7xx_hal_eth.c
  • HAL_ETH_Stop() : stm32f7xx_hal_eth.c
  • HAL_ETH_TransmitFrame() : stm32f7xx_hal_eth.c
  • HAL_ETH_TxCpltCallback() : stm32f7xx_hal_eth.c
  • HAL_ETH_WritePHYRegister() : stm32f7xx_hal_eth.c
  • HAL_FLASH_EndOfOperationCallback() : stm32f7xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32f7xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f7xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f7xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f7xx_hal_flash.c
  • HAL_FLASHEx_Erase() : stm32f7xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f7xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f7xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32f7xx_hal.c
  • HAL_GetHalVersion() : stm32f7xx_hal.c
  • HAL_GetREVID() : stm32f7xx_hal.c
  • HAL_GetTick() : stm32f7xx_hal.c
  • HAL_GPIO_DeInit() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f7xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f7xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f7xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f7xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f7xx_hal_uart.c
  • HAL_HCD_Connect_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32f7xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32f7xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Init() : stm32f7xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32f7xx_hal_hcd.c
  • HAL_HCD_MspDeInit() : stm32f7xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32f7xx_hal_hcd.c
  • HAL_HCD_ResetPort() : stm32f7xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Start() : stm32f7xx_hal_hcd.c
  • HAL_HCD_Stop() : stm32f7xx_hal_hcd.c
  • HAL_I2C_DeInit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f7xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f7xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f7xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f7xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f7xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f7xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f7xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32f7xx_hal_i2c_ex.c , stm32f7xx_hal_i2c_ex.h
  • HAL_I2CEx_ConfigDigitalFilter() : stm32f7xx_hal_i2c_ex.c , stm32f7xx_hal_i2c_ex.h
  • HAL_I2S_DeInit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32f7xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32f7xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32f7xx_hal_i2s.c
  • HAL_I2S_ErrorCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32f7xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Init() : stm32f7xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32f7xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32f7xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32f7xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32f7xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32f7xx_hal_i2s.c
  • HAL_IncTick() : stm32f7xx_hal.c
  • HAL_Init() : stm32f7xx_hal.c
  • HAL_InitTick() : stm32f7xx_hal.c
  • HAL_IRDA_DeInit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f7xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f7xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f7xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f7xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f7xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f7xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f7xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f7xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f7xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f7xx_hal_irda.c
  • HAL_IWDG_GetState() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_MspInit() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_Start() : stm32f7xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32f7xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f7xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_MspDeInit() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32f7xx_hal_lptim.c , stm32f7xx_hal_lptim.h
  • HAL_MPU_ConfigRegion() : stm32f7xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32f7xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32f7xx_hal_cortex.h
  • HAL_MspDeInit() : stm32f7xx_hal.c
  • HAL_MspInit() : stm32f7xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32f7xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32f7xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f7xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f7xx_hal_uart.c
  • HAL_NAND_Address_Inc() : stm32f7xx_hal_nand.c
  • HAL_NAND_DeInit() : stm32f7xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32f7xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32f7xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32f7xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32f7xx_hal_nand.c
  • HAL_NAND_GetState() : stm32f7xx_hal_nand.c
  • HAL_NAND_Init() : stm32f7xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32f7xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32f7xx_hal_nand.c
  • HAL_NAND_MspDeInit() : stm32f7xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_Page() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_SpareArea() : stm32f7xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32f7xx_hal_nand.c , stm32f7xx_hal_nand.h
  • HAL_NAND_Reset() : stm32f7xx_hal_nand.c
  • HAL_NAND_Write_Page() : stm32f7xx_hal_nand.c
  • HAL_NAND_Write_SpareArea() : stm32f7xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32f7xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32f7xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32f7xx_hal_nor.c
  • HAL_NOR_GetState() : stm32f7xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32f7xx_hal_nor.c
  • HAL_NOR_Init() : stm32f7xx_hal_nor.c
  • HAL_NOR_MspDeInit() : stm32f7xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32f7xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32f7xx_hal_nor.c
  • HAL_NOR_Program() : stm32f7xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32f7xx_hal_nor.c
  • HAL_NOR_Read() : stm32f7xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32f7xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32f7xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32f7xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32f7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Disable() : stm32f7xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32f7xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f7xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f7xx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32f7xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32f7xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32f7xx_hal_pcd.c
  • HAL_PCD_Init() : stm32f7xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCD_Start() : stm32f7xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32f7xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32f7xx_hal_pcd.c
  • HAL_PCDEx_ActivateLPM() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32f7xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32f7xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f7xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f7xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f7xx_hal_pwr.c
  • HAL_PWR_PVD_IRQHandler() : stm32f7xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32f7xx_hal_pwr.c
  • HAL_PWREx_ControlVoltageScaling() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMainRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_DisableOverDrive() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMainRegulatorLowVoltage() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnableOverDrive() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_EnterUnderDriveSTOPMode() : stm32f7xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32f7xx_hal_pwr_ex.c
  • HAL_QSPI_Abort() : stm32f7xx_hal_qspi.h , stm32f7xx_hal_qspi.c
  • HAL_QSPI_AutoPolling() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_AutoPolling_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_CmdCpltCallback() : stm32f7xx_hal_qspi.h , stm32f7xx_hal_qspi.c
  • HAL_QSPI_Command() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Command_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_DeInit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_ErrorCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_GetError() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_GetState() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_Init() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_IRQHandler() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_MemoryMapped() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_MspDeInit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_MspInit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Receive() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Receive_DMA() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Receive_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_RxCpltCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_RxHalfCpltCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_SetTimeout() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_TimeOutCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_Transmit() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Transmit_DMA() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_Transmit_IT() : stm32f7xx_hal_qspi.c
  • HAL_QSPI_TxCpltCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_QSPI_TxHalfCpltCallback() : stm32f7xx_hal_qspi.c , stm32f7xx_hal_qspi.h
  • HAL_RCC_ClockConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f7xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f7xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32f7xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f7xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32f7xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f7xx_hal_rcc.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f7xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32f7xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f7xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f7xx_hal.c
  • HAL_RNG_DeInit() : stm32f7xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32f7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32f7xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32f7xx_hal_rng.c
  • HAL_RNG_GetRandomNumber() : stm32f7xx_hal_rng.c
  • HAL_RNG_GetRandomNumber_IT() : stm32f7xx_hal_rng.c
  • HAL_RNG_GetState() : stm32f7xx_hal_rng.c
  • HAL_RNG_Init() : stm32f7xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32f7xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32f7xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32f7xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32f7xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32f7xx_hal_rng.c
  • HAL_RTC_AlarmAEventCallback() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_DeactivateAlarm() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_DeInit() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_GetAlarm() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_GetState() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_Init() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_MspInit() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_PollForAlarmAEvent() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_SetAlarm() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_SetDate() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_BKUPRead() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_BKUPWrite() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateRefClock() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DeactivateTimeStamp() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_DisableBypassShadow() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_EnableBypassShadow() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_GetTimeStamp() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForAlarmBEvent() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForTamper2Event() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForTimeStampEvent() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetCalibrationOutPut() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetRefClock() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetSynchroShift() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTamper_IT() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTimeStamp() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetTimeStamp_IT() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_Tamper1EventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_Tamper2EventCallback() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_TimeStampEventCallback() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32f7xx_hal_rtc_ex.h , stm32f7xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32f7xx_hal_rtc_ex.c , stm32f7xx_hal_rtc_ex.h
  • HAL_SAI_Abort() : stm32f7xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32f7xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32f7xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32f7xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32f7xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32f7xx_hal_sai.c
  • HAL_SAI_ErrorCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_GetError() : stm32f7xx_hal_sai.c
  • HAL_SAI_GetState() : stm32f7xx_hal_sai.c
  • HAL_SAI_Init() : stm32f7xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32f7xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32f7xx_hal_sai.c
  • HAL_SAI_MspDeInit() : stm32f7xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32f7xx_hal_sai.c
  • HAL_SAI_Receive() : stm32f7xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32f7xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32f7xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_Transmit() : stm32f7xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32f7xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32f7xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32f7xx_hal_sai.c
  • HAL_SD_CheckReadOperation() : stm32f7xx_hal_sd.c
  • HAL_SD_CheckWriteOperation() : stm32f7xx_hal_sd.c
  • HAL_SD_DeInit() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_RxCpltCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_RxErrorCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_TxCpltCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_DMA_TxErrorCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_Erase() : stm32f7xx_hal_sd.c
  • HAL_SD_Get_CardInfo() : stm32f7xx_hal_sd.c
  • HAL_SD_GetCardStatus() : stm32f7xx_hal_sd.c
  • HAL_SD_GetStatus() : stm32f7xx_hal_sd.c
  • HAL_SD_HighSpeed() : stm32f7xx_hal_sd.c
  • HAL_SD_Init() : stm32f7xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32f7xx_hal_sd.c
  • HAL_SD_MspDeInit() : stm32f7xx_hal_sd.c
  • HAL_SD_MspInit() : stm32f7xx_hal_sd.c
  • HAL_SD_ReadBlocks() : stm32f7xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32f7xx_hal_sd.c
  • HAL_SD_SendSDStatus() : stm32f7xx_hal_sd.c
  • HAL_SD_StopTransfer() : stm32f7xx_hal_sd.c
  • HAL_SD_WideBusOperation_Config() : stm32f7xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32f7xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32f7xx_hal_sd.c
  • HAL_SD_XferCpltCallback() : stm32f7xx_hal_sd.c
  • HAL_SD_XferErrorCallback() : stm32f7xx_hal_sd.c
  • HAL_SDRAM_DeInit() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferCpltCallback() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_DMA_XferErrorCallback() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_GetModeStatus() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_GetState() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Init() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_IRQHandler() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_MspDeInit() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_MspInit() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_ProgramRefreshRate() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_16b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_32b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_8b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Read_DMA() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_RefreshErrorCallback() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_SendCommand() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_SetAutoRefreshNumber() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_16b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_32b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_8b() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_Write_DMA() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Disable() : stm32f7xx_hal_sdram.c
  • HAL_SDRAM_WriteProtection_Enable() : stm32f7xx_hal_sdram.c
  • HAL_SMARTCARD_DeInit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f7xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32f7xx_hal_smartcard_ex.h , stm32f7xx_hal_smartcard_ex.c
  • HAL_SPDIFRX_CxCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_CxHalfCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DeInit() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_DMAStop() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ErrorCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetError() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_GetState() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_Init() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_IRQHandler() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspDeInit() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_MspInit() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_DMA() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveControlFlow_IT() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_DMA() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_ReceiveDataFlow_IT() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_RxHalfCpltCallback() : stm32f7xx_hal_spdifrx.c
  • HAL_SPDIFRX_SetDataFormat() : stm32f7xx_hal_spdifrx.c
  • HAL_SPI_DeInit() : stm32f7xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f7xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f7xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f7xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f7xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f7xx_hal_spi.c
  • HAL_SPI_Init() : stm32f7xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f7xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32f7xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f7xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f7xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f7xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f7xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32f7xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f7xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f7xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f7xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f7xx_hal_spi.c
  • HAL_SRAM_DeInit() : stm32f7xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32f7xx_hal_sram.c , stm32f7xx_hal_sram.h
  • HAL_SRAM_DMA_XferErrorCallback() : stm32f7xx_hal_sram.h , stm32f7xx_hal_sram.c
  • HAL_SRAM_GetState() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Init() : stm32f7xx_hal_sram.c
  • HAL_SRAM_MspDeInit() : stm32f7xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_16b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32f7xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32f7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32f7xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32f7xx_hal_sram.c
  • HAL_SuspendTick() : stm32f7xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f7xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f7xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f7xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f7xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f7xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim_ex.c
  • HAL_TIM_ConfigTI1Input() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f7xx_hal_tim.c
  • HAL_TIM_DMACaptureCplt() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • HAL_TIM_DMADelayPulseCplt() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • HAL_TIM_DMAError() : stm32f7xx_hal_tim.h , stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32f7xx_hal_tim_ex.c , stm32f7xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim_ex.c
  • HAL_TIM_PWM_DeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f7xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f7xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f7xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32f7xx_hal_tim.c
  • HAL_TIMEx_BreakCallback() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_DMACommutationCplt() : stm32f7xx_hal_tim_ex.h , stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f7xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32f7xx_hal_tim_ex.c
  • HAL_UART_DeInit() : stm32f7xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f7xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f7xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f7xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_GetError() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • HAL_UART_GetState() : stm32f7xx_hal_uart.h , stm32f7xx_hal_uart.c
  • HAL_UART_Init() : stm32f7xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f7xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32f7xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f7xx_hal_uart.c
  • HAL_UART_Receive() : stm32f7xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f7xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f7xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_Transmit() : stm32f7xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f7xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f7xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f7xx_hal_uart.c
  • HAL_USART_CheckIdleState() : stm32f7xx_hal_usart.h
  • HAL_USART_DeInit() : stm32f7xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f7xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f7xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f7xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_GetError() : stm32f7xx_hal_usart.c
  • HAL_USART_GetState() : stm32f7xx_hal_usart.c
  • HAL_USART_Init() : stm32f7xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f7xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32f7xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f7xx_hal_usart.c
  • HAL_USART_Receive() : stm32f7xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f7xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f7xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_Transmit() : stm32f7xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f7xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f7xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f7xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f7xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f7xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f7xx_hal_usart.c
  • HAL_WWDG_DeInit() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_GetState() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_MspDeInit() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Start() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_Start_IT() : stm32f7xx_hal_wwdg.c
  • HAL_WWDG_WakeupCallback() : stm32f7xx_hal_wwdg.c , stm32f7xx_hal_wwdg.h
  • HCD_HC_IN_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_Port_IRQHandler() : stm32f7xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32f7xx_hal_hcd.c
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STM32F745xx HAL User Manual: Globals

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- i -

  • I2C_DMAError() : stm32f7xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMAMemReceiveCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMAMemTransmitCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32f7xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32f7xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32f7xx_hal_i2c.c
  • I2C_MasterReceive_ISR() : stm32f7xx_hal_i2c.c
  • I2C_MasterTransmit_ISR() : stm32f7xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32f7xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f7xx_hal_i2c.c
  • I2C_SlaveReceive_ISR() : stm32f7xx_hal_i2c.c
  • I2C_SlaveTransmit_ISR() : stm32f7xx_hal_i2c.c
  • I2C_TransferConfig() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32f7xx_hal_i2c.c
  • I2S_DMAError() : stm32f7xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32f7xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32f7xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32f7xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32f7xx_hal_i2s.c
  • I2S_GetClockFreq() : stm32f7xx_hal_i2s.c
  • I2S_Receive_IT() : stm32f7xx_hal_i2s.c
  • I2S_Transmit_IT() : stm32f7xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32f7xx_hal_i2s.c
  • IRDA_CheckIdleState() : stm32f7xx_hal_irda.c
  • IRDA_DMAError() : stm32f7xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f7xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f7xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f7xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f7xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f7xx_hal_irda.c
  • IRDA_Receive_IT() : stm32f7xx_hal_irda.c
  • IRDA_SetConfig() : stm32f7xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f7xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32f7xx_hal_irda.c
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STM32F745xx HAL User Manual: Globals

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- p -

  • PCD_WriteEmptyTxFifo() : stm32f7xx_hal_pcd.c
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STM32F745xx HAL User Manual: Globals

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- q -

  • QSPI_Config() : stm32f7xx_hal_qspi.c
  • QSPI_DMAError() : stm32f7xx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DMARxHalfCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32f7xx_hal_qspi.c
  • QSPI_DMATxHalfCplt() : stm32f7xx_hal_qspi.c
  • QSPI_WaitFlagStateUntilTimeout() : stm32f7xx_hal_qspi.c
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STM32F745xx HAL User Manual: Globals

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- r -

  • RTC_Bcd2ToByte() : stm32f7xx_hal_rtc.c , stm32f7xx_hal_rtc.h
  • RTC_ByteToBcd2() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32f7xx_hal_rtc.h , stm32f7xx_hal_rtc.c
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STM32F745xx HAL User Manual: Globals

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- s -

  • SAI_BlockSynchroConfig() : stm32f7xx_hal_sai_ex.c
  • SAI_Disable() : stm32f7xx_hal_sai.c
  • SAI_DMAError() : stm32f7xx_hal_sai.c
  • SAI_DMARxCplt() : stm32f7xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32f7xx_hal_sai.c
  • SAI_DMATxCplt() : stm32f7xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32f7xx_hal_sai.c
  • SAI_FillFifo() : stm32f7xx_hal_sai.c
  • SAI_GetInputClock() : stm32f7xx_hal_sai_ex.c
  • SAI_InitI2S() : stm32f7xx_hal_sai.c
  • SAI_InitPCM() : stm32f7xx_hal_sai.c
  • SAI_InterruptFlag() : stm32f7xx_hal_sai.c
  • SAI_Receive_IT16Bit() : stm32f7xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32f7xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32f7xx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32f7xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32f7xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32f7xx_hal_sai.c
  • SD_CmdError() : stm32f7xx_hal_sd.c
  • SD_CmdResp1Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp2Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp3Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp6Error() : stm32f7xx_hal_sd.c
  • SD_CmdResp7Error() : stm32f7xx_hal_sd.c
  • SD_DMA_RxCplt() : stm32f7xx_hal_sd.c
  • SD_DMA_RxError() : stm32f7xx_hal_sd.c
  • SD_DMA_TxCplt() : stm32f7xx_hal_sd.c
  • SD_DMA_TxError() : stm32f7xx_hal_sd.c
  • SD_FindSCR() : stm32f7xx_hal_sd.c
  • SD_GetState() : stm32f7xx_hal_sd.c
  • SD_Initialize_Cards() : stm32f7xx_hal_sd.c
  • SD_IsCardProgramming() : stm32f7xx_hal_sd.c
  • SD_PowerOFF() : stm32f7xx_hal_sd.c
  • SD_PowerON() : stm32f7xx_hal_sd.c
  • SD_Select_Deselect() : stm32f7xx_hal_sd.c
  • SD_SendStatus() : stm32f7xx_hal_sd.c
  • SD_WideBus_Disable() : stm32f7xx_hal_sd.c
  • SD_WideBus_Enable() : stm32f7xx_hal_sd.c
  • SMARTCARD_AdvFeatureConfig() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_Receive_IT() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_Transmit_IT() : stm32f7xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f7xx_hal_smartcard.c
  • SPDIFRX_DMACxCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMACxHalfCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMAError() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMARxCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_DMARxHalfCplt() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveControlFlow_IT() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_ReceiveDataFlow_IT() : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_WaitOnFlagUntilTimeout() : stm32f7xx_hal_spdifrx.c
  • SPI_2linesRxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32f7xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32f7xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32f7xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f7xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f7xx_hal_spi.c
  • SPI_DMAError() : stm32f7xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f7xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f7xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f7xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32f7xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32f7xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32f7xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32f7xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32f7xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f7xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32f7xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f7xx_hal_spi.c
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- t -

  • TIM_Base_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32f7xx_hal_tim.h , stm32f7xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32f7xx_hal_tim_ex.c
  • TIM_DMAPeriodElapsedCplt() : stm32f7xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f7xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC2_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32f7xx_hal_tim.h , stm32f7xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_OC5_SetConfig() : stm32f7xx_hal_tim_ex.c
  • TIM_OC6_SetConfig() : stm32f7xx_hal_tim_ex.c
  • TIM_SlaveTimer_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f7xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f7xx_hal_tim.c , stm32f7xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32f7xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f7xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f7xx_hal_tim.c
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  • i
  • p
  • q
  • r
  • s
  • t
  • u

- u -

  • UART_AdvFeatureConfig() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • UART_CheckIdleState() : stm32f7xx_hal_uart.h , stm32f7xx_hal_uart.c
  • UART_DMAError() : stm32f7xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f7xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f7xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f7xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f7xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f7xx_hal_uart.c
  • UART_Receive_IT() : stm32f7xx_hal_uart.c
  • UART_SetConfig() : stm32f7xx_hal_uart.c , stm32f7xx_hal_uart.h
  • UART_Transmit_IT() : stm32f7xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32f7xx_hal_uart.h , stm32f7xx_hal_uart.c
  • USART_CheckIdleState() : stm32f7xx_hal_usart.c
  • USART_DMAError() : stm32f7xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f7xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f7xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f7xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f7xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f7xx_hal_usart.c
  • USART_Receive_IT() : stm32f7xx_hal_usart.c
  • USART_SetConfig() : stm32f7xx_hal_usart.c
  • USART_Transmit_IT() : stm32f7xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f7xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f7xx_hal_usart.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • APBAHBPrescTable : stm32f7xx_hal_rcc.c
  • pFlash : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c
  • uwTick : stm32f7xx_hal.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • DMA2D_HandleTypeDef : stm32f7xx_hal_dma2d.h
  • DMA_HandleTypeDef : stm32f7xx_hal_dma.h
  • HAL_LPTIM_StateTypeDef : stm32f7xx_hal_lptim.h
  • HCD_HCStateTypeDef : stm32f7xx_hal_hcd.h
  • HCD_HCTypeDef : stm32f7xx_hal_hcd.h
  • HCD_InitTypeDef : stm32f7xx_hal_hcd.h
  • HCD_TypeDef : stm32f7xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32f7xx_hal_hcd.h
  • PCD_EPTypeDef : stm32f7xx_hal_pcd.h
  • PCD_InitTypeDef : stm32f7xx_hal_pcd.h
  • PCD_TypeDef : stm32f7xx_hal_pcd.h
  • SAI_HandleTypeDef : stm32f7xx_hal_sai.h
  • SAIcallback : stm32f7xx_hal_sai.h
  • SPI_HandleTypeDef : stm32f7xx_hal_spi.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • f
  • g
  • h
  • i
  • p
  • s
  • u

- _ -

  • __HAL_LPTIM_StateTypeDef : stm32f7xx_hal_lptim.h

- f -

  • FLASH_ProcedureTypeDef : stm32f7xx_hal_flash.h

- g -

  • GPIO_PinState : stm32f7xx_hal_gpio.h

- h -

  • HAL_CAN_StateTypeDef : stm32f7xx_hal_can.h
  • HAL_CEC_StateTypeDef : stm32f7xx_hal_cec.h
  • HAL_CRC_StateTypeDef : stm32f7xx_hal_crc.h
  • HAL_DAC_StateTypeDef : stm32f7xx_hal_dac.h
  • HAL_DCMI_StateTypeDef : stm32f7xx_hal_dcmi.h
  • HAL_DMA2D_StateTypeDef : stm32f7xx_hal_dma2d.h
  • HAL_DMA_LevelCompleteTypeDef : stm32f7xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32f7xx_hal_dma_ex.h
  • HAL_DMA_StateTypeDef : stm32f7xx_hal_dma.h
  • HAL_ETH_StateTypeDef : stm32f7xx_hal_eth.h
  • HAL_I2C_StateTypeDef : stm32f7xx_hal_i2c.h
  • HAL_I2S_StateTypeDef : stm32f7xx_hal_i2s.h
  • HAL_IRDA_StateTypeDef : stm32f7xx_hal_irda.h
  • HAL_IWDG_StateTypeDef : stm32f7xx_hal_iwdg.h
  • HAL_NAND_StateTypeDef : stm32f7xx_hal_nand.h
  • HAL_NOR_StateTypeDef : stm32f7xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32f7xx_hal_nor.h
  • HAL_QSPI_StateTypeDef : stm32f7xx_hal_qspi.h
  • HAL_RNG_StateTypeDef : stm32f7xx_hal_rng.h
  • HAL_RTCStateTypeDef : stm32f7xx_hal_rtc.h
  • HAL_SAI_StateTypeDef : stm32f7xx_hal_sai.h
  • HAL_SD_CardStateTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_ErrorTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_OperationTypedef : stm32f7xx_hal_sd.h
  • HAL_SD_TransferStateTypedef : stm32f7xx_hal_sd.h
  • HAL_SDRAM_StateTypeDef : stm32f7xx_hal_sdram.h
  • HAL_SMARTCARD_StateTypeDef : stm32f7xx_hal_smartcard.h
  • HAL_SPDIFRX_StateTypeDef : stm32f7xx_hal_spdifrx.h
  • HAL_SPI_StateTypeDef : stm32f7xx_hal_spi.h
  • HAL_SRAM_StateTypeDef : stm32f7xx_hal_sram.h
  • HAL_TIM_ActiveChannel : stm32f7xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f7xx_hal_tim.h
  • HAL_UART_StateTypeDef : stm32f7xx_hal_uart.h
  • HAL_USART_StateTypeDef : stm32f7xx_hal_usart.h
  • HAL_WWDG_StateTypeDef : stm32f7xx_hal_wwdg.h
  • HCD_StateTypeDef : stm32f7xx_hal_hcd.h

- i -

  • IRDA_ClockSourceTypeDef : stm32f7xx_hal_irda.h

- p -

  • PCD_LPM_MsgTypeDef : stm32f7xx_hal_pcd_ex.h
  • PCD_LPM_StateTypeDef : stm32f7xx_hal_pcd.h
  • PCD_StateTypeDef : stm32f7xx_hal_pcd.h

- s -

  • SAI_ModeTypedef : stm32f7xx_hal_sai.c
  • SMARTCARD_ClockSourceTypeDef : stm32f7xx_hal_smartcard.h

- u -

  • UART_ClockSourceTypeDef : stm32f7xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32f7xx_hal_usart.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
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  • i
  • l
  • m
  • p
  • s
  • u

- f -

  • FLASH_PROC_MASSERASE : stm32f7xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f7xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32f7xx_hal_flash.h
  • FLASH_PROC_SECTERASE : stm32f7xx_hal_flash.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- g -

  • GPIO_PIN_RESET : stm32f7xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f7xx_hal_gpio.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • m
  • p
  • s
  • u

- h -

  • HAL_CAN_STATE_BUSY : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32f7xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32f7xx_hal_can.h
  • HAL_CEC_STATE_BUSY : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_STANDBY_RX : stm32f7xx_hal_cec.h
  • HAL_CEC_STATE_TIMEOUT : stm32f7xx_hal_cec.h
  • HAL_CRC_STATE_BUSY : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f7xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f7xx_hal_crc.h
  • HAL_DAC_STATE_BUSY : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32f7xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32f7xx_hal_dac.h
  • HAL_DCMI_STATE_BUSY : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_ERROR : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_READY : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_RESET : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_STATE_TIMEOUT : stm32f7xx_hal_dcmi.h
  • HAL_DMA2D_STATE_BUSY : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_ERROR : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_READY : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_RESET : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_SUSPEND : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_STATE_TIMEOUT : stm32f7xx_hal_dma2d.h
  • HAL_DMA_FULL_TRANSFER : stm32f7xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM0 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM1 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM0 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM1 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM0 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM1 : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f7xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f7xx_hal_dma.h
  • HAL_ETH_STATE_BUSY : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_RD : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_RX : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_TX : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_TX_RX : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_BUSY_WR : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_ERROR : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_READY : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_RESET : stm32f7xx_hal_eth.h
  • HAL_ETH_STATE_TIMEOUT : stm32f7xx_hal_eth.h
  • HAL_HCD_STATE_BUSY : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32f7xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32f7xx_hal_hcd.h
  • HAL_I2C_STATE_BUSY : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MASTER_BUSY_RX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MASTER_BUSY_TX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MEM_BUSY_RX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_MEM_BUSY_TX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_SLAVE_BUSY_RX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_SLAVE_BUSY_TX : stm32f7xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f7xx_hal_i2c.h
  • HAL_I2S_STATE_BUSY : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32f7xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32f7xx_hal_i2s.h
  • HAL_IRDA_STATE_BUSY : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f7xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f7xx_hal_irda.h
  • HAL_IWDG_STATE_BUSY : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_ERROR : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_READY : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_RESET : stm32f7xx_hal_iwdg.h
  • HAL_IWDG_STATE_TIMEOUT : stm32f7xx_hal_iwdg.h
  • HAL_LPTIM_STATE_BUSY : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32f7xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32f7xx_hal_lptim.h
  • HAL_NAND_STATE_BUSY : stm32f7xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32f7xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32f7xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32f7xx_hal_nand.h
  • HAL_NOR_STATE_BUSY : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32f7xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32f7xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32f7xx_hal_nor.h
  • HAL_PCD_STATE_BUSY : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32f7xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32f7xx_hal_pcd.h
  • HAL_QSPI_STATE_BUSY : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32f7xx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32f7xx_hal_qspi.h
  • HAL_RNG_STATE_BUSY : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32f7xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32f7xx_hal_rng.h
  • HAL_RTC_STATE_BUSY : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f7xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f7xx_hal_rtc.h
  • HAL_SAI_STATE_BUSY : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_ERROR : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32f7xx_hal_sai.h
  • HAL_SAI_STATE_TIMEOUT : stm32f7xx_hal_sai.h
  • HAL_SDRAM_STATE_BUSY : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_ERROR : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_PRECHARGED : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_READY : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_RESET : stm32f7xx_hal_sdram.h
  • HAL_SDRAM_STATE_WRITE_PROTECTED : stm32f7xx_hal_sdram.h
  • HAL_SMARTCARD_STATE_BUSY : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f7xx_hal_smartcard.h
  • HAL_SPDIFRX_STATE_BUSY : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_CX : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_BUSY_RX : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_ERROR : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_READY : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_STATE_RESET : stm32f7xx_hal_spdifrx.h
  • HAL_SPI_STATE_BUSY : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f7xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f7xx_hal_spi.h
  • HAL_SRAM_STATE_BUSY : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32f7xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32f7xx_hal_sram.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f7xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f7xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f7xx_hal_tim.h
  • HAL_UART_STATE_BUSY : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f7xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f7xx_hal_uart.h
  • HAL_USART_STATE_BUSY : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f7xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f7xx_hal_usart.h
  • HAL_WWDG_STATE_BUSY : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_ERROR : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_READY : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_RESET : stm32f7xx_hal_wwdg.h
  • HAL_WWDG_STATE_TIMEOUT : stm32f7xx_hal_wwdg.h
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STM32F745xx HAL User Manual: Globals

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- i -

  • IRDA_CLOCKSOURCE_HSI : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_irda.h
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- l -

  • LPM_L0 : stm32f7xx_hal_pcd.h
  • LPM_L1 : stm32f7xx_hal_pcd.h
  • LPM_L2 : stm32f7xx_hal_pcd.h
  • LPM_L3 : stm32f7xx_hal_pcd.h
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STM32F745xx HAL User Manual: Globals

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- m -

  • MEMORY0 : stm32f7xx_hal_dma_ex.h
  • MEMORY1 : stm32f7xx_hal_dma_ex.h
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STM32F745xx HAL User Manual: Globals

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- p -

  • PCD_LPM_L0_ACTIVE : stm32f7xx_hal_pcd_ex.h
  • PCD_LPM_L1_ACTIVE : stm32f7xx_hal_pcd_ex.h
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STM32F745xx HAL User Manual: Globals

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- s -

  • SAI_MODE_DMA : stm32f7xx_hal_sai.c
  • SAI_MODE_IT : stm32f7xx_hal_sai.c
  • SD_ADDR_MISALIGNED : stm32f7xx_hal_sd.h
  • SD_ADDR_OUT_OF_RANGE : stm32f7xx_hal_sd.h
  • SD_AKE_SEQ_ERROR : stm32f7xx_hal_sd.h
  • SD_BAD_ERASE_PARAM : stm32f7xx_hal_sd.h
  • SD_BLOCK_LEN_ERR : stm32f7xx_hal_sd.h
  • SD_CARD_DISCONNECTED : stm32f7xx_hal_sd.h
  • SD_CARD_ECC_DISABLED : stm32f7xx_hal_sd.h
  • SD_CARD_ECC_FAILED : stm32f7xx_hal_sd.h
  • SD_CARD_ERROR : stm32f7xx_hal_sd.h
  • SD_CARD_IDENTIFICATION : stm32f7xx_hal_sd.h
  • SD_CARD_PROGRAMMING : stm32f7xx_hal_sd.h
  • SD_CARD_READY : stm32f7xx_hal_sd.h
  • SD_CARD_RECEIVING : stm32f7xx_hal_sd.h
  • SD_CARD_SENDING : stm32f7xx_hal_sd.h
  • SD_CARD_STANDBY : stm32f7xx_hal_sd.h
  • SD_CARD_TRANSFER : stm32f7xx_hal_sd.h
  • SD_CC_ERROR : stm32f7xx_hal_sd.h
  • SD_CID_CSD_OVERWRITE : stm32f7xx_hal_sd.h
  • SD_CMD_CRC_FAIL : stm32f7xx_hal_sd.h
  • SD_CMD_OUT_OF_RANGE : stm32f7xx_hal_sd.h
  • SD_CMD_RSP_TIMEOUT : stm32f7xx_hal_sd.h
  • SD_COM_CRC_FAILED : stm32f7xx_hal_sd.h
  • SD_DATA_CRC_FAIL : stm32f7xx_hal_sd.h
  • SD_DATA_TIMEOUT : stm32f7xx_hal_sd.h
  • SD_ERASE_RESET : stm32f7xx_hal_sd.h
  • SD_ERASE_SEQ_ERR : stm32f7xx_hal_sd.h
  • SD_ERROR : stm32f7xx_hal_sd.h
  • SD_GENERAL_UNKNOWN_ERROR : stm32f7xx_hal_sd.h
  • SD_ILLEGAL_CMD : stm32f7xx_hal_sd.h
  • SD_INTERNAL_ERROR : stm32f7xx_hal_sd.h
  • SD_INVALID_PARAMETER : stm32f7xx_hal_sd.h
  • SD_INVALID_VOLTRANGE : stm32f7xx_hal_sd.h
  • SD_LOCK_UNLOCK_FAILED : stm32f7xx_hal_sd.h
  • SD_NOT_CONFIGURED : stm32f7xx_hal_sd.h
  • SD_OK : stm32f7xx_hal_sd.h
  • SD_READ_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_READ_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_REQUEST_NOT_APPLICABLE : stm32f7xx_hal_sd.h
  • SD_REQUEST_PENDING : stm32f7xx_hal_sd.h
  • SD_RX_OVERRUN : stm32f7xx_hal_sd.h
  • SD_SDMMC_DISABLED : stm32f7xx_hal_sd.h
  • SD_SDMMC_FUNCTION_BUSY : stm32f7xx_hal_sd.h
  • SD_SDMMC_FUNCTION_FAILED : stm32f7xx_hal_sd.h
  • SD_SDMMC_UNKNOWN_FUNCTION : stm32f7xx_hal_sd.h
  • SD_START_BIT_ERR : stm32f7xx_hal_sd.h
  • SD_STREAM_READ_UNDERRUN : stm32f7xx_hal_sd.h
  • SD_STREAM_WRITE_OVERRUN : stm32f7xx_hal_sd.h
  • SD_SWITCH_ERROR : stm32f7xx_hal_sd.h
  • SD_TRANSFER_BUSY : stm32f7xx_hal_sd.h
  • SD_TRANSFER_ERROR : stm32f7xx_hal_sd.h
  • SD_TRANSFER_OK : stm32f7xx_hal_sd.h
  • SD_TX_UNDERRUN : stm32f7xx_hal_sd.h
  • SD_UNSUPPORTED_FEATURE : stm32f7xx_hal_sd.h
  • SD_UNSUPPORTED_HW : stm32f7xx_hal_sd.h
  • SD_WP_ERASE_SKIP : stm32f7xx_hal_sd.h
  • SD_WRITE_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_WRITE_PROT_VIOLATION : stm32f7xx_hal_sd.h
  • SD_WRITE_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_smartcard.h
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STM32F745xx HAL User Manual: Globals

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- u -

  • UART_CLOCKSOURCE_HSI : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32f7xx_hal_uart.h
  • USART_CLOCKSOURCE_HSI : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32f7xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32f7xx_hal_usart.h
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STM32F745xx HAL User Manual: Globals

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- _ -

  • __HAL_ADC_CLEAR_FLAG : stm32f7xx_hal_adc.h
  • __HAL_ADC_DISABLE : stm32f7xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32f7xx_hal_adc.h
  • __HAL_ADC_ENABLE : stm32f7xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32f7xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32f7xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f7xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f7xx_hal_adc.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32f7xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32f7xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32f7xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32f7xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32f7xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32f7xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32f7xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32f7xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32f7xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32f7xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32f7xx_hal_can.h
  • __HAL_CEC_CLEAR_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32f7xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32f7xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32f7xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32f7xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32f7xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32f7xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32f7xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32f7xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32f7xx_hal_cec.h
  • __HAL_CRC_DR_RESET : stm32f7xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f7xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32f7xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32f7xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32f7xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32f7xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f7xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f7xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32f7xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32f7xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32f7xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32f7xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32f7xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32f7xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32f7xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32f7xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_CAN2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM10 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM11 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM9 : stm32f7xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM10 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM11 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM12 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM13 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM9 : stm32f7xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f7xx_hal.h
  • __HAL_DCMI_CLEAR_FLAG : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_DISABLE_IT : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_ENABLE_IT : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_GET_FLAG : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_GET_IT_SOURCE : stm32f7xx_hal_dcmi.h
  • __HAL_DCMI_RESET_HANDLE_STATE : stm32f7xx_hal_dcmi.h
  • __HAL_DMA2D_CLEAR_FLAG : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_DISABLE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_DISABLE_IT : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_ENABLE_IT : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_FLAG : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_GET_IT_SOURCE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA2D_RESET_HANDLE_STATE : stm32f7xx_hal_dma2d.h
  • __HAL_DMA_CLEAR_FLAG : stm32f7xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32f7xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f7xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f7xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f7xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f7xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32f7xx_hal_dma.h
  • __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_CLEAR_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_CLEAR_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMA_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMARXDESC_SET_OWN_BIT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_CRC_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_CRC_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_SET_OWN_BIT : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_GET_DMA_OVERFLOW_STATUS : stm32f7xx_hal_eth.h
  • __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS : stm32f7xx_hal_eth.h
  • __HAL_ETH_GET_PMT_FLAG_STATUS : stm32f7xx_hal_eth.h
  • __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAC_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAC_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAC_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_FULL_PRESET : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTER_HALF_PRESET : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_COUNTERS_RESET : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_RX_IT_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_RX_IT_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_TX_IT_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_MMC_TX_IT_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_POWER_DOWN_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_POWER_DOWN_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_RESET_HANDLE_STATE : stm32f7xx_hal_eth.h
  • __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_IT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_EXTI_GET_FLAG : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE : stm32f7xx_hal_eth.h
  • __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE : stm32f7xx_hal_eth.h
  • __HAL_FLASH_ART_DISABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_ART_ENABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_ART_RESET : stm32f7xx_hal_flash.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f7xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32f7xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32f7xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32f7xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32f7xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f7xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f7xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f7xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f7xx_hal_gpio.h
  • __HAL_HCD_CLEAR_FLAG : stm32f7xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32f7xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32f7xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32f7xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32f7xx_hal_hcd.h
  • __HAL_I2C_CLEAR_FLAG : stm32f7xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f7xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f7xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f7xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f7xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f7xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f7xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f7xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32f7xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32f7xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32f7xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32f7xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32f7xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32f7xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32f7xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32f7xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32f7xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f7xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32f7xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f7xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32f7xx_hal_irda.h
  • __HAL_IWDG_GET_FLAG : stm32f7xx_hal_iwdg.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f7xx_hal_iwdg.h
  • __HAL_IWDG_RESET_HANDLE_STATE : stm32f7xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f7xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32f7xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32f7xx_hal_lptim.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32f7xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32f7xx_hal_nor.h
  • __HAL_PCD_CLEAR_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32f7xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32f7xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32f7xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32f7xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32f7xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32f7xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_CLEAR_ODRUDR_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_CLEAR_WAKEUP_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_GET_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_GET_ODRUDR_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_GET_WAKEUP_FLAG : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVE_DISABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVE_ENABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVESWITCHING_DISABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_OVERDRIVESWITCHING_ENABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f7xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f7xx_hal_pwr.h
  • __HAL_PWR_UNDERDRIVE_DISABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_UNDERDRIVE_ENABLE : stm32f7xx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32f7xx_hal_pwr.h
  • __HAL_QSPI_CLEAR_FLAG : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32f7xx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32f7xx_hal_qspi.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_AXI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AXI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_BKPSRAM_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CAN2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CLEAR_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CLK48_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DAC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DCMI_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DMA2D_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ENABLE_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_ETH_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETH_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETH_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETH_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMAC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CLK48_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C4_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2SCLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART7_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART8_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART6_SOURCE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOI_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOJ_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOK_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f7xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2C4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_I2S_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_MCO2_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLI2S_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_CLEAR_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_DISABLE_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_ENABLE_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_GET_FLAG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_GET_IT : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_QSPI_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32f7xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPDIFRX_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SPI6_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f7xx_hal_rcc.h
  • __HAL_RCC_TIM10_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM10_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM11_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM12_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM13_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART7_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_UART8_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_CONFIG : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_FORCE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_RELEASE_RESET : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc_ex.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32f7xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f7xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32f7xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32f7xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32f7xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32f7xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32f7xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32f7xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32f7xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f7xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f7xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32f7xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32f7xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32f7xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32f7xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32f7xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32f7xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32f7xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32f7xx_hal_sai.h
  • __HAL_SD_SDMMC_CLEAR_FLAG : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_CLEAR_IT : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DISABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DISABLE_IT : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DMA_DISABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_DMA_ENABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_ENABLE : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_ENABLE_IT : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_GET_FLAG : stm32f7xx_hal_sd.h
  • __HAL_SD_SDMMC_GET_IT : stm32f7xx_hal_sd.h
  • __HAL_SDRAM_RESET_HANDLE_STATE : stm32f7xx_hal_sdram.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_DISABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_ENABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f7xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32f7xx_hal_smartcard.h
  • __HAL_SPDIFRX_CLEAR_IT : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_DISABLE_IT : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_ENABLE_IT : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_FLAG : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_GET_IT_SOURCE : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_IDLE : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RCV : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_RESET_HANDLE_STATE : stm32f7xx_hal_spdifrx.h
  • __HAL_SPDIFRX_SYNC : stm32f7xx_hal_spdifrx.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f7xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f7xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f7xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f7xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f7xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f7xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f7xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32f7xx_hal_sram.h
  • __HAL_SYSCFG_REMAPMEMORY_FMC : stm32f7xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM : stm32f7xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32f7xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f7xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f7xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f7xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f7xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f7xx_hal_tim_ex.h
  • __HAL_TIM_GET_COUNTER : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f7xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f7xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f7xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f7xx_hal_tim_ex.h
  • __HAL_TIM_SET_COUNTER : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f7xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f7xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f7xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f7xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f7xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f7xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32f7xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f7xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32f7xx_hal_uart.h
  • __HAL_USART_CLEAR_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f7xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f7xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f7xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32f7xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f7xx_hal_usart.h
  • __HAL_USART_MASK_COMPUTATION : stm32f7xx_hal_usart_ex.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f7xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32f7xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT : stm32f7xx_hal_pcd.h
  • __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG : stm32f7xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f7xx_hal_wwdg.h
  • __HAL_WWDG_RESET_HANDLE_STATE : stm32f7xx_hal_wwdg.h
  • __STM32F7xx_HAL_VERSION : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_MAIN : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_RC : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_SUB1 : stm32f7xx_hal.c
  • __STM32F7xx_HAL_VERSION_SUB2 : stm32f7xx_hal.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- a -

  • ADC_ALL_CHANNELS : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f7xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f7xx_hal_adc.h
  • ADC_AWD_EVENT : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_0 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_1 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_11 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_12 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_13 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_14 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_15 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_16 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_17 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_18 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_2 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_3 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_4 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_5 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_6 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_7 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_8 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_9 : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f7xx_hal_adc_ex.h
  • ADC_CHANNEL_VBAT : stm32f7xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32f7xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV6 : stm32f7xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV8 : stm32f7xx_hal_adc.h
  • ADC_CR1_DISCONTINUOUS : stm32f7xx_hal_adc.h
  • ADC_CR1_SCANCONV : stm32f7xx_hal_adc.h
  • ADC_CR2_CONTINUOUS : stm32f7xx_hal_adc.h
  • ADC_CR2_DMAContReq : stm32f7xx_hal_adc.h
  • ADC_CR2_EOCSelection : stm32f7xx_hal_adc.h
  • ADC_DATAALIGN_LEFT : stm32f7xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32f7xx_hal_adc.h
  • ADC_DMAACCESSMODE_1 : stm32f7xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_2 : stm32f7xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_3 : stm32f7xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_ALTERTRIG : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32f7xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32f7xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32f7xx_hal_adc.h
  • ADC_EOC_SINGLE_SEQ_CONV : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_EXT_IT11 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC1 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC3 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_TRGO2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T3_CC4 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T4_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T6_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_TRGO : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_TRGO2 : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32f7xx_hal_adc.h
  • ADC_EXTERNALTRIGINJECCONV_T1_CC4 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC1 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC3 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T5_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T6_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC4 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_TRGO : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_FALLING : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_NONE : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISING : stm32f7xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING : stm32f7xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f7xx_hal_adc.h
  • ADC_FLAG_EOC : stm32f7xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32f7xx_hal_adc.h
  • ADC_FLAG_JSTRT : stm32f7xx_hal_adc.h
  • ADC_FLAG_OVR : stm32f7xx_hal_adc.h
  • ADC_FLAG_STRT : stm32f7xx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32f7xx_hal_adc.h
  • ADC_INJECTED_CHANNELS : stm32f7xx_hal_adc.h
  • ADC_INJECTED_RANK_1 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f7xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f7xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f7xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f7xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f7xx_hal_adc.h
  • ADC_IT_AWD : stm32f7xx_hal_adc.h
  • ADC_IT_EOC : stm32f7xx_hal_adc.h
  • ADC_IT_JEOC : stm32f7xx_hal_adc.h
  • ADC_IT_OVR : stm32f7xx_hal_adc.h
  • ADC_JSQR : stm32f7xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32f7xx_hal_adc_ex.h
  • ADC_OVR_EVENT : stm32f7xx_hal_adc.h
  • ADC_REGULAR_CHANNELS : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32f7xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_112CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_144CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_15CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_480CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_56CYCLES : stm32f7xx_hal_adc.h
  • ADC_SAMPLETIME_84CYCLES : stm32f7xx_hal_adc.h
  • ADC_SMPR1 : stm32f7xx_hal_adc.h
  • ADC_SMPR2 : stm32f7xx_hal_adc.h
  • ADC_SOFTWARE_START : stm32f7xx_hal_adc.h
  • ADC_SQR1 : stm32f7xx_hal_adc.h
  • ADC_SQR1_RK : stm32f7xx_hal_adc.h
  • ADC_SQR2_RK : stm32f7xx_hal_adc.h
  • ADC_SQR3_RK : stm32f7xx_hal_adc.h
  • ADC_STAB_DELAY_US : stm32f7xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32f7xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f7xx_hal_adc.h
  • ADC_TRIPLEMODE_ALTERTRIG : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INTERL : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_AlterTrig : stm32f7xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT : stm32f7xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_13CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_14CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_15CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_16CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_17CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_18CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_19CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_20CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32f7xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32f7xx_hal_adc.h
  • ADDR_1ST_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32f7xx_hal_nand.h
  • ADDR_AREA : stm32f7xx_hal_nand.h
  • ARRAY_ADDRESS : stm32f7xx_hal_nand.h
  • ART_ACCLERATOR_ENABLE : stm32f7xx_hal_conf.h
  • assert_param : stm32f7xx_hal_conf.h
  • AUTONEGO_COMPLETED_TIMEOUT_VALUE : stm32f7xx_hal_eth.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- b -

  • BDTR_BK2F_SHIFT : stm32f7xx_hal_tim_ex.c
  • BDTR_BKF_SHIFT : stm32f7xx_hal_tim_ex.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
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- c -

  • CAN_BS1_10TQ : stm32f7xx_hal_can.h
  • CAN_BS1_11TQ : stm32f7xx_hal_can.h
  • CAN_BS1_12TQ : stm32f7xx_hal_can.h
  • CAN_BS1_13TQ : stm32f7xx_hal_can.h
  • CAN_BS1_14TQ : stm32f7xx_hal_can.h
  • CAN_BS1_15TQ : stm32f7xx_hal_can.h
  • CAN_BS1_16TQ : stm32f7xx_hal_can.h
  • CAN_BS1_1TQ : stm32f7xx_hal_can.h
  • CAN_BS1_2TQ : stm32f7xx_hal_can.h
  • CAN_BS1_3TQ : stm32f7xx_hal_can.h
  • CAN_BS1_4TQ : stm32f7xx_hal_can.h
  • CAN_BS1_5TQ : stm32f7xx_hal_can.h
  • CAN_BS1_6TQ : stm32f7xx_hal_can.h
  • CAN_BS1_7TQ : stm32f7xx_hal_can.h
  • CAN_BS1_8TQ : stm32f7xx_hal_can.h
  • CAN_BS1_9TQ : stm32f7xx_hal_can.h
  • CAN_BS2_1TQ : stm32f7xx_hal_can.h
  • CAN_BS2_2TQ : stm32f7xx_hal_can.h
  • CAN_BS2_3TQ : stm32f7xx_hal_can.h
  • CAN_BS2_4TQ : stm32f7xx_hal_can.h
  • CAN_BS2_5TQ : stm32f7xx_hal_can.h
  • CAN_BS2_6TQ : stm32f7xx_hal_can.h
  • CAN_BS2_7TQ : stm32f7xx_hal_can.h
  • CAN_BS2_8TQ : stm32f7xx_hal_can.h
  • CAN_FIFO0 : stm32f7xx_hal_can.h
  • CAN_FIFO1 : stm32f7xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32f7xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32f7xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32f7xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32f7xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32f7xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32f7xx_hal_can.h
  • CAN_FLAG_BOF : stm32f7xx_hal_can.h
  • CAN_FLAG_EPV : stm32f7xx_hal_can.h
  • CAN_FLAG_EWG : stm32f7xx_hal_can.h
  • CAN_FLAG_FF0 : stm32f7xx_hal_can.h
  • CAN_FLAG_FF1 : stm32f7xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32f7xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32f7xx_hal_can.h
  • CAN_FLAG_MASK : stm32f7xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32f7xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32f7xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32f7xx_hal_can.h
  • CAN_FLAG_SLAK : stm32f7xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32f7xx_hal_can.h
  • CAN_FLAG_TME0 : stm32f7xx_hal_can.h
  • CAN_FLAG_TME1 : stm32f7xx_hal_can.h
  • CAN_FLAG_TME2 : stm32f7xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32f7xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32f7xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32f7xx_hal_can.h
  • CAN_FLAG_WKU : stm32f7xx_hal_can.h
  • CAN_ID_EXT : stm32f7xx_hal_can.h
  • CAN_ID_STD : stm32f7xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32f7xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32f7xx_hal_can.h
  • CAN_IT_BOF : stm32f7xx_hal_can.h
  • CAN_IT_EPV : stm32f7xx_hal_can.h
  • CAN_IT_ERR : stm32f7xx_hal_can.h
  • CAN_IT_EWG : stm32f7xx_hal_can.h
  • CAN_IT_FF0 : stm32f7xx_hal_can.h
  • CAN_IT_FF1 : stm32f7xx_hal_can.h
  • CAN_IT_FMP0 : stm32f7xx_hal_can.h
  • CAN_IT_FMP1 : stm32f7xx_hal_can.h
  • CAN_IT_FOV0 : stm32f7xx_hal_can.h
  • CAN_IT_FOV1 : stm32f7xx_hal_can.h
  • CAN_IT_LEC : stm32f7xx_hal_can.h
  • CAN_IT_SLK : stm32f7xx_hal_can.h
  • CAN_IT_TME : stm32f7xx_hal_can.h
  • CAN_IT_WKU : stm32f7xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32f7xx_hal_can.h
  • CAN_MODE_NORMAL : stm32f7xx_hal_can.h
  • CAN_MODE_SILENT : stm32f7xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32f7xx_hal_can.h
  • CAN_RTR_DATA : stm32f7xx_hal_can.h
  • CAN_RTR_REMOTE : stm32f7xx_hal_can.h
  • CAN_SJW_1TQ : stm32f7xx_hal_can.h
  • CAN_SJW_2TQ : stm32f7xx_hal_can.h
  • CAN_SJW_3TQ : stm32f7xx_hal_can.h
  • CAN_SJW_4TQ : stm32f7xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32f7xx_hal_can.c
  • CAN_TXMAILBOX_0 : stm32f7xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32f7xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32f7xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32f7xx_hal_can.h
  • CEC_0_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32f7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32f7xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_CFGR_FIELDS : stm32f7xx_hal_cec.c
  • CEC_CFGR_OAR_LSB_POS : stm32f7xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32f7xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32f7xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32f7xx_hal_cec.h
  • CEC_FLAG_BRE : stm32f7xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32f7xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32f7xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32f7xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32f7xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32f7xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32f7xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32f7xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32f7xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32f7xx_hal_cec.h
  • CEC_IT_ARBLST : stm32f7xx_hal_cec.h
  • CEC_IT_BRE : stm32f7xx_hal_cec.h
  • CEC_IT_LBPE : stm32f7xx_hal_cec.h
  • CEC_IT_RXACKE : stm32f7xx_hal_cec.h
  • CEC_IT_RXBR : stm32f7xx_hal_cec.h
  • CEC_IT_RXEND : stm32f7xx_hal_cec.h
  • CEC_IT_RXOVR : stm32f7xx_hal_cec.h
  • CEC_IT_SBPE : stm32f7xx_hal_cec.h
  • CEC_IT_TXACKE : stm32f7xx_hal_cec.h
  • CEC_IT_TXBR : stm32f7xx_hal_cec.h
  • CEC_IT_TXEND : stm32f7xx_hal_cec.h
  • CEC_IT_TXERR : stm32f7xx_hal_cec.h
  • CEC_IT_TXUDR : stm32f7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32f7xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32f7xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32f7xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32f7xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32f7xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32f7xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32f7xx_hal_cec.h
  • CFI1_ADDRESS : stm32f7xx_hal_nor.h
  • CFI2_ADDRESS : stm32f7xx_hal_nor.h
  • CFI3_ADDRESS : stm32f7xx_hal_nor.h
  • CFI4_ADDRESS : stm32f7xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • CM_A4 : stm32f7xx_hal_dma2d.h
  • CM_A8 : stm32f7xx_hal_dma2d.h
  • CM_AL44 : stm32f7xx_hal_dma2d.h
  • CM_AL88 : stm32f7xx_hal_dma2d.h
  • CM_ARGB1555 : stm32f7xx_hal_dma2d.h
  • CM_ARGB4444 : stm32f7xx_hal_dma2d.h
  • CM_ARGB8888 : stm32f7xx_hal_dma2d.h
  • CM_L4 : stm32f7xx_hal_dma2d.h
  • CM_L8 : stm32f7xx_hal_dma2d.h
  • CM_RGB565 : stm32f7xx_hal_dma2d.h
  • CM_RGB888 : stm32f7xx_hal_dma2d.h
  • CMD_AREA : stm32f7xx_hal_nand.h
  • COLOR_VALUE : stm32f7xx_hal_dma2d.h
  • CR1_CLEAR_MASK : stm32f7xx_hal_sai.c
  • CR_PSIZE_MASK : stm32f7xx_hal_flash.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32f7xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32f7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32f7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32f7xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32f7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32f7xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32f7xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32f7xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32f7xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32f7xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32f7xx_hal_crc.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- d -

  • DAC_ALIGN_12B_L : stm32f7xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32f7xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32f7xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32f7xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32f7xx_hal_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32f7xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32f7xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32f7xx_hal_dac.h
  • DAC_FLAG_DMAUDR1 : stm32f7xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32f7xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32f7xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32f7xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32f7xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32f7xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32f7xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32f7xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32f7xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32f7xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32f7xx_hal_dac.h
  • DATA_BLOCK_SIZE : stm32f7xx_hal_sd.c
  • DCMI_BSM_ALL : stm32f7xx_hal_dcmi_ex.h
  • DCMI_BSM_ALTERNATE_2 : stm32f7xx_hal_dcmi_ex.h
  • DCMI_BSM_ALTERNATE_4 : stm32f7xx_hal_dcmi_ex.h
  • DCMI_BSM_OTHER : stm32f7xx_hal_dcmi_ex.h
  • DCMI_CR_ALL_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_2_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_CR_ALTERNATE_4_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_10B : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_12B : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_14B : stm32f7xx_hal_dcmi.h
  • DCMI_EXTEND_DATA_8B : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_ERRMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_ERRRI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_FNE : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMEMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_FRAMERI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_HSYNC : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_LINEMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_LINERI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_OVFMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_OVFRI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNC : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCMI : stm32f7xx_hal_dcmi.h
  • DCMI_FLAG_VSYNCRI : stm32f7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_HIGH : stm32f7xx_hal_dcmi.h
  • DCMI_HSPOLARITY_LOW : stm32f7xx_hal_dcmi.h
  • DCMI_IT_ERR : stm32f7xx_hal_dcmi.h
  • DCMI_IT_FRAME : stm32f7xx_hal_dcmi.h
  • DCMI_IT_LINE : stm32f7xx_hal_dcmi.h
  • DCMI_IT_OVF : stm32f7xx_hal_dcmi.h
  • DCMI_IT_VSYNC : stm32f7xx_hal_dcmi.h
  • DCMI_JPEG_DISABLE : stm32f7xx_hal_dcmi.h
  • DCMI_JPEG_ENABLE : stm32f7xx_hal_dcmi.h
  • DCMI_LSM_ALL : stm32f7xx_hal_dcmi_ex.h
  • DCMI_LSM_ALTERNATE_2 : stm32f7xx_hal_dcmi_ex.h
  • DCMI_MODE_CONTINUOUS : stm32f7xx_hal_dcmi.h
  • DCMI_MODE_SNAPSHOT : stm32f7xx_hal_dcmi.h
  • DCMI_OEBS_EVEN : stm32f7xx_hal_dcmi_ex.h
  • DCMI_OEBS_ODD : stm32f7xx_hal_dcmi_ex.h
  • DCMI_OELS_EVEN : stm32f7xx_hal_dcmi_ex.h
  • DCMI_OELS_ODD : stm32f7xx_hal_dcmi_ex.h
  • DCMI_PCKPOLARITY_FALLING : stm32f7xx_hal_dcmi.h
  • DCMI_PCKPOLARITY_RISING : stm32f7xx_hal_dcmi.h
  • DCMI_SYNCHRO_EMBEDDED : stm32f7xx_hal_dcmi.h
  • DCMI_SYNCHRO_HARDWARE : stm32f7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_HIGH : stm32f7xx_hal_dcmi.h
  • DCMI_VSPOLARITY_LOW : stm32f7xx_hal_dcmi.h
  • DCMI_WINDOW_COORDINATE : stm32f7xx_hal_dcmi.h
  • DCMI_WINDOW_HEIGHT : stm32f7xx_hal_dcmi.h
  • DEFAULT_CRC32_POLY : stm32f7xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32f7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32f7xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32f7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32f7xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32f7xx_hal_crc.h
  • DEVICE_CODE1_ADDR : stm32f7xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32f7xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32f7xx_hal_nor.h
  • DMA2D_ARGB1555 : stm32f7xx_hal_dma2d.h
  • DMA2D_ARGB4444 : stm32f7xx_hal_dma2d.h
  • DMA2D_ARGB8888 : stm32f7xx_hal_dma2d.h
  • DMA2D_CCM_ARGB8888 : stm32f7xx_hal_dma2d.h
  • DMA2D_CCM_RGB888 : stm32f7xx_hal_dma2d.h
  • DMA2D_CLUT_SIZE : stm32f7xx_hal_dma2d.h
  • DMA2D_COMBINE_ALPHA : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_CAE : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_CE : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_CTC : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_TC : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_TE : stm32f7xx_hal_dma2d.h
  • DMA2D_FLAG_TW : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_CAE : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_CE : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_CTC : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_TC : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_TE : stm32f7xx_hal_dma2d.h
  • DMA2D_IT_TW : stm32f7xx_hal_dma2d.h
  • DMA2D_LINE : stm32f7xx_hal_dma2d.h
  • DMA2D_M2M : stm32f7xx_hal_dma2d.h
  • DMA2D_M2M_BLEND : stm32f7xx_hal_dma2d.h
  • DMA2D_M2M_PFC : stm32f7xx_hal_dma2d.h
  • DMA2D_NO_MODIF_ALPHA : stm32f7xx_hal_dma2d.h
  • DMA2D_OFFSET : stm32f7xx_hal_dma2d.h
  • DMA2D_PIXEL : stm32f7xx_hal_dma2d.h
  • DMA2D_R2M : stm32f7xx_hal_dma2d.h
  • DMA2D_REPLACE_ALPHA : stm32f7xx_hal_dma2d.h
  • DMA2D_RGB565 : stm32f7xx_hal_dma2d.h
  • DMA2D_RGB888 : stm32f7xx_hal_dma2d.h
  • DMA_CHANNEL_0 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_1 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_2 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_3 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_4 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_5 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_6 : stm32f7xx_hal_dma.h
  • DMA_CHANNEL_7 : stm32f7xx_hal_dma.h
  • DMA_CIRCULAR : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32f7xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32f7xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32f7xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32f7xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32f7xx_hal_dma.h
  • DMA_IT_DME : stm32f7xx_hal_dma.h
  • DMA_IT_FE : stm32f7xx_hal_dma.h
  • DMA_IT_HT : stm32f7xx_hal_dma.h
  • DMA_IT_TC : stm32f7xx_hal_dma.h
  • DMA_IT_TE : stm32f7xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32f7xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32f7xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32f7xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32f7xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f7xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f7xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f7xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f7xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f7xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f7xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f7xx_hal_dma.h
  • DMA_NORMAL : stm32f7xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32f7xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32f7xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32f7xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32f7xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f7xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f7xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f7xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f7xx_hal_dma.h
  • DMA_PFCTRL : stm32f7xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f7xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f7xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f7xx_hal_dma.h
  • DP83848_PHY_ADDRESS : stm32f7xx_hal_conf.h
  • DUMMY_DATA : stm32f7xx_hal_usart.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- e -

  • ETH_ADDRESSALIGNEDBEATS_DISABLE : stm32f7xx_hal_eth.h
  • ETH_ADDRESSALIGNEDBEATS_ENABLE : stm32f7xx_hal_eth.h
  • ETH_AUTOMATICPADCRCSTRIP_DISABLE : stm32f7xx_hal_eth.h
  • ETH_AUTOMATICPADCRCSTRIP_ENABLE : stm32f7xx_hal_eth.h
  • ETH_AUTONEGOTIATION_DISABLE : stm32f7xx_hal_eth.h
  • ETH_AUTONEGOTIATION_ENABLE : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_1 : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_10 : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_4 : stm32f7xx_hal_eth.h
  • ETH_BACKOFFLIMIT_8 : stm32f7xx_hal_eth.h
  • ETH_BROADCASTFRAMESRECEPTION_DISABLE : stm32f7xx_hal_eth.h
  • ETH_BROADCASTFRAMESRECEPTION_ENABLE : stm32f7xx_hal_eth.h
  • ETH_CARRIERSENCE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_CARRIERSENCE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUM_BY_HARDWARE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUM_BY_SOFTWARE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUMOFFLAOD_DISABLE : stm32f7xx_hal_eth.h
  • ETH_CHECKSUMOFFLAOD_ENABLE : stm32f7xx_hal_eth.h
  • ETH_CRC : stm32f7xx_hal_eth.h
  • ETH_DEFFERRALCHECK_DISABLE : stm32f7xx_hal_eth.h
  • ETH_DEFFERRALCHECK_ENABLE : stm32f7xx_hal_eth.h
  • ETH_DESTINATIONADDRFILTER_INVERSE : stm32f7xx_hal_eth.h
  • ETH_DESTINATIONADDRFILTER_NORMAL : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_ACCESSERROR : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_AIS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_DATATRANSFERERROR : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_ER : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_ET : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_FBE : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_MMC : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_NIS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_PMT : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_R : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RBU : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_READWRITEERROR : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RO : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RPS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_RWT : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_T : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TBU : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TJT : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TPS : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TST : stm32f7xx_hal_eth.h
  • ETH_DMA_FLAG_TU : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_AIS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_ER : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_ET : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_FBE : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_MMC : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_NIS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_PMT : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_R : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RBU : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RO : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RPS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_RWT : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_T : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TBU : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TJT : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TPS : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TST : stm32f7xx_hal_eth.h
  • ETH_DMA_IT_TU : stm32f7xx_hal_eth.h
  • ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : stm32f7xx_hal_eth.h
  • ETH_DMA_OVERFLOW_RXFIFOCOUNTER : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_CLOSING : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_FETCHING : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_QUEUING : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_STOPPED : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_SUSPENDED : stm32f7xx_hal_eth.h
  • ETH_DMA_RECEIVEPROCESS_WAITING : stm32f7xx_hal_eth.h
  • ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_CLOSING : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_FETCHING : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_READING : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_STOPPED : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_SUSPENDED : stm32f7xx_hal_eth.h
  • ETH_DMA_TRANSMITPROCESS_WAITING : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 : stm32f7xx_hal_eth.h
  • ETH_DMAARBITRATION_RXPRIORTX : stm32f7xx_hal_eth.h
  • ETH_DMAENHANCEDDESCRIPTOR_DISABLE : stm32f7xx_hal_eth.h
  • ETH_DMAENHANCEDDESCRIPTOR_ENABLE : stm32f7xx_hal_eth.h
  • ETH_DMAOMR_CLEAR_MASK : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPCB : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPHE : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPE : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT_ICMP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT_TCP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPPT_UDP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPV4PR : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_IPV6PR : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPFT : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_DELAYREQ : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_DELAYRESP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPMT_SYNC : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_PTPV : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_RTSH : stm32f7xx_hal_eth.h
  • ETH_DMAPTPRXDESC_RTSL : stm32f7xx_hal_eth.h
  • ETH_DMAPTPTXDESC_TTSH : stm32f7xx_hal_eth.h
  • ETH_DMAPTPTXDESC_TTSL : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_AFM : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_B1AP : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_B2AP : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_BUFFER1 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_BUFFER2 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_BUFFER2_SIZESHIFT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_CE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_DBE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_DE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_DIC : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_ES : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FL : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FRAME_LENGTHSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FRAMELENGTHSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FS : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_FT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_IPV4HCE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_LC : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_LE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_LS : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_MAMPCE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_OE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_OWN : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RBS1 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RBS2 : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RCH : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RE : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RER : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_RWT : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_SAF : stm32f7xx_hal_eth.h
  • ETH_DMARXDESC_VLAN : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_B1AP : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_B2AP : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_BUFFER2_SIZESHIFT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMBYPASS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMIPV4HEADER : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_BYPASS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_IPV4HEADER : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_TCPUDPICMP_FULL : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_COLLISION_COUNTSHIFT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_DB : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_DC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_DP : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_EC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_ED : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_ES : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_FF : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_FIRSTSEGMENT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_FS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_IC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_IHE : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_JT : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LASTSEGMENTS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LCA : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LCO : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_LS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_NC : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_OWN : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_PCE : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TBS1 : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TBS2 : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TCH : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TER : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TTSE : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_TTSS : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_UF : stm32f7xx_hal_eth.h
  • ETH_DMATXDESC_VF : stm32f7xx_hal_eth.h
  • ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE : stm32f7xx_hal_eth.h
  • ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE : stm32f7xx_hal_eth.h
  • ETH_ERROR : stm32f7xx_hal_eth.h
  • ETH_EXTI_LINE_WAKEUP : stm32f7xx_hal_eth.h
  • ETH_EXTRA : stm32f7xx_hal_eth.h
  • ETH_FIXEDBURST_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FIXEDBURST_ENABLE : stm32f7xx_hal_eth.h
  • ETH_FLUSHRECEIVEDFRAME_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FLUSHRECEIVEDFRAME_ENABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDERRORFRAMES_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDERRORFRAMES_ENABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE : stm32f7xx_hal_eth.h
  • ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE : stm32f7xx_hal_eth.h
  • ETH_HEADER : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_40BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_48BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_56BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_64BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_72BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_80BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_88BIT : stm32f7xx_hal_eth.h
  • ETH_INTERFRAMEGAP_96BIT : stm32f7xx_hal_eth.h
  • ETH_JABBER_DISABLE : stm32f7xx_hal_eth.h
  • ETH_JABBER_ENABLE : stm32f7xx_hal_eth.h
  • ETH_JUMBO_FRAME_PAYLOAD : stm32f7xx_hal_eth.h
  • ETH_LOOPBACKMODE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_LOOPBACKMODE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDR_HBASE : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDR_LBASE : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS0 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS1 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS2 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESS3 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSFILTER_DA : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSFILTER_SA : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE1 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE2 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE3 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE4 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE5 : stm32f7xx_hal_eth.h
  • ETH_MAC_ADDRESSMASK_BYTE6 : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_MMC : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_MMCR : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_MMCT : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_PMT : stm32f7xx_hal_eth.h
  • ETH_MAC_FLAG_TST : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_MMC : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_MMCR : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_MMCT : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_PMT : stm32f7xx_hal_eth.h
  • ETH_MAC_IT_TST : stm32f7xx_hal_eth.h
  • ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_MII_TRANSMIT_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_FLUSHING : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_IDLE : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_READING_DATA : stm32f7xx_hal_eth.h
  • ETH_MAC_READCONTROLLER_READING_STATUS : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_ABOVE_THRESHOLD : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_BELOW_THRESHOLD : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_EMPTY : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_FULL : stm32f7xx_hal_eth.h
  • ETH_MAC_RXFIFO_WRITE_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_NOTACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_READ_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_RW_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_SMALL_FIFO_WRITE_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMISSION_PAUSE : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING : stm32f7xx_hal_eth.h
  • ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_FULL : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_IDLE : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_READ : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_WAITING : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_WRITE_ACTIVE : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFO_WRITING : stm32f7xx_hal_eth.h
  • ETH_MAC_TXFIFONOT_EMPTY : stm32f7xx_hal_eth.h
  • ETH_MACCR_CLEAR_MASK : stm32f7xx_hal_eth.h
  • ETH_MACFCR_CLEAR_MASK : stm32f7xx_hal_eth.h
  • ETH_MACMIIAR_CR_MASK : stm32f7xx_hal_eth.h
  • ETH_MAX_ETH_PAYLOAD : stm32f7xx_hal_eth.h
  • ETH_MAX_PACKET_SIZE : stm32f7xx_hal_eth.h
  • ETH_MEDIA_INTERFACE_MII : stm32f7xx_hal_eth.h
  • ETH_MEDIA_INTERFACE_RMII : stm32f7xx_hal_eth.h
  • ETH_MIN_ETH_PAYLOAD : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_RFAE : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_RFCE : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_RGUF : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_TGF : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_TGFMSC : stm32f7xx_hal_eth.h
  • ETH_MMC_IT_TGFSC : stm32f7xx_hal_eth.h
  • ETH_MODE_FULLDUPLEX : stm32f7xx_hal_eth.h
  • ETH_MODE_HALFDUPLEX : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_HASHTABLE : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_NONE : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_PERFECT : stm32f7xx_hal_eth.h
  • ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE : stm32f7xx_hal_eth.h
  • ETH_PASSCONTROLFRAMES_BLOCKALL : stm32f7xx_hal_eth.h
  • ETH_PASSCONTROLFRAMES_FORWARDALL : stm32f7xx_hal_eth.h
  • ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS144 : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS256 : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS28 : stm32f7xx_hal_eth.h
  • ETH_PAUSELOWTHRESHOLD_MINUS4 : stm32f7xx_hal_eth.h
  • ETH_PMT_FLAG_MPR : stm32f7xx_hal_eth.h
  • ETH_PMT_FLAG_WUFFRPR : stm32f7xx_hal_eth.h
  • ETH_PMT_FLAG_WUFR : stm32f7xx_hal_eth.h
  • ETH_PROMISCUOUS_MODE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_PROMISCUOUS_MODE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEAll_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEALL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES : stm32f7xx_hal_eth.h
  • ETH_RECEIVEFLOWCONTROL_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEFLOWCONTROL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEOWN_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVEOWN_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVESTOREFORWARD_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RECEIVESTOREFORWARD_ENABLE : stm32f7xx_hal_eth.h
  • ETH_REG_WRITE_DELAY : stm32f7xx_hal_eth.h
  • ETH_RETRYTRANSMISSION_DISABLE : stm32f7xx_hal_eth.h
  • ETH_RETRYTRANSMISSION_ENABLE : stm32f7xx_hal_eth.h
  • ETH_RX_BUF_SIZE : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_RXBUFNB : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_RXDMABURSTLENGTH_16BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_1BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_2BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_32BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_128BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_16BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_32BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_4BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_64BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_4XPBL_8BEAT : stm32f7xx_hal_eth.h
  • ETH_RXDMABURSTLENGTH_8BEAT : stm32f7xx_hal_eth.h
  • ETH_RXINTERRUPT_MODE : stm32f7xx_hal_eth.h
  • ETH_RXPOLLING_MODE : stm32f7xx_hal_eth.h
  • ETH_SECONDFRAMEOPERARTE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_SECONDFRAMEOPERARTE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_SOURCEADDRFILTER_DISABLE : stm32f7xx_hal_eth.h
  • ETH_SOURCEADDRFILTER_INVERSE_ENABLE : stm32f7xx_hal_eth.h
  • ETH_SOURCEADDRFILTER_NORMAL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_SPEED_100M : stm32f7xx_hal_eth.h
  • ETH_SPEED_10M : stm32f7xx_hal_eth.h
  • ETH_SUCCESS : stm32f7xx_hal_eth.h
  • ETH_TRANSMITFLOWCONTROL_DISABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITFLOWCONTROL_ENABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITSTOREFORWARD_DISABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITSTOREFORWARD_ENABLE : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_128BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_16BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_192BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_24BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_256BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_32BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_40BYTES : stm32f7xx_hal_eth.h
  • ETH_TRANSMITTHRESHOLDCONTROL_64BYTES : stm32f7xx_hal_eth.h
  • ETH_TX_BUF_SIZE : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_TXBUFNB : stm32f7xx_hal_eth.h , stm32f7xx_hal_conf.h
  • ETH_TXDMABURSTLENGTH_16BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_1BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_2BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_32BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_128BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_16BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_32BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_4BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_64BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_4XPBL_8BEAT : stm32f7xx_hal_eth.h
  • ETH_TXDMABURSTLENGTH_8BEAT : stm32f7xx_hal_eth.h
  • ETH_UNICASTFRAMESFILTER_HASHTABLE : stm32f7xx_hal_eth.h
  • ETH_UNICASTFRAMESFILTER_PERFECT : stm32f7xx_hal_eth.h
  • ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE : stm32f7xx_hal_eth.h
  • ETH_UNICASTPAUSEFRAMEDETECT_DISABLE : stm32f7xx_hal_eth.h
  • ETH_UNICASTPAUSEFRAMEDETECT_ENABLE : stm32f7xx_hal_eth.h
  • ETH_VLAN_TAG : stm32f7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_12BIT : stm32f7xx_hal_eth.h
  • ETH_VLANTAGCOMPARISON_16BIT : stm32f7xx_hal_eth.h
  • ETH_WAKEUP_REGISTER_LENGTH : stm32f7xx_hal_eth.h
  • ETH_WATCHDOG_DISABLE : stm32f7xx_hal_eth.h
  • ETH_WATCHDOG_ENABLE : stm32f7xx_hal_eth.h
  • ETH_ZEROQUANTAPAUSE_DISABLE : stm32f7xx_hal_eth.h
  • ETH_ZEROQUANTAPAUSE_ENABLE : stm32f7xx_hal_eth.h
  • EXTERNAL_CLOCK_VALUE : stm32f7xx_hal_conf.h
  • EXTI_MODE : stm32f7xx_hal_gpio.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
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- f -

  • FALLING_EDGE : stm32f7xx_hal_gpio.c
  • FLASH_FLAG_BSY : stm32f7xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32f7xx_hal_flash.h
  • FLASH_FLAG_ERSERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_PGPERR : stm32f7xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32f7xx_hal_flash.h
  • FLASH_IT_EOP : stm32f7xx_hal_flash.h
  • FLASH_IT_ERR : stm32f7xx_hal_flash.h
  • FLASH_KEY1 : stm32f7xx_hal_flash.h
  • FLASH_KEY2 : stm32f7xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_10 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_11 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_12 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_13 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_14 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_15 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_8 : stm32f7xx_hal_flash_ex.h
  • FLASH_LATENCY_9 : stm32f7xx_hal_flash_ex.h
  • FLASH_MER_BIT : stm32f7xx_hal_flash_ex.h
  • FLASH_OPT_KEY1 : stm32f7xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_BYTE : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_DOUBLE_WORD : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_HALF_WORD : stm32f7xx_hal_flash.h
  • FLASH_PSIZE_WORD : stm32f7xx_hal_flash.h
  • FLASH_SECTOR_0 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_1 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_2 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_3 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_4 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_5 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_6 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_7 : stm32f7xx_hal_flash_ex.h
  • FLASH_SECTOR_TOTAL : stm32f7xx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c
  • FLASH_TYPEERASE_MASSERASE : stm32f7xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32f7xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_BYTE : stm32f7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f7xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f7xx_hal_flash.h
  • FLASH_VOLTAGE_RANGE_1 : stm32f7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_2 : stm32f7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_3 : stm32f7xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_4 : stm32f7xx_hal_flash_ex.h
  • FRCR_CLEAR_MASK : stm32f7xx_hal_sai.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • d
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  • f
  • g
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- g -

  • GPIO_AF0_MCO : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG_FS : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_OTG_HS : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF10_SAI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF11_ETH : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF12_OTG_HS_FS : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF12_SDMMC1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF13_DCMI : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_CEC : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_LPTIM1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM10 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM11 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF3_TIM9 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_CEC : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF4_I2C4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF5_SPI6 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF6_SAI1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_SPDIFRX : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_SPI3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_UART5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_SAI2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_SPDIFRX : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART7 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_UART8 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF8_USART6 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_CAN1 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_CAN2 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_QUADSPI : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM12 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM13 : stm32f7xx_hal_gpio_ex.h
  • GPIO_AF9_TIM14 : stm32f7xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32f7xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f7xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32f7xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f7xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f7xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f7xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f7xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f7xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f7xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f7xx_hal_gpio.h
  • GPIO_NOPULL : stm32f7xx_hal_gpio.h
  • GPIO_NUMBER : stm32f7xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f7xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f7xx_hal_gpio.h
  • GPIO_PIN_All : stm32f7xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f7xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f7xx_hal_gpio.h
  • GPIO_PULLUP : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f7xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32f7xx_hal_gpio.h
  • GPIOA_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOB_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOC_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOD_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOE_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOF_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOG_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOH_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOI_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOJ_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • GPIOK_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
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- h -

  • HAL_ADC_ERROR_DMA : stm32f7xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32f7xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32f7xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32f7xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f7xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f7xx_hal_adc.h
  • HAL_CAN_ERROR_ACK : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32f7xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32f7xx_hal_can.h
  • HAL_CAN_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CEC_ERROR_ARBLST : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32f7xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32f7xx_hal_cec.h
  • HAL_CEC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CRC_Input_Data_Reverse : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32f7xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32f7xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_CRC_Output_Data_Reverse : stm32f7xx_hal_crc.h
  • HAL_CRYP_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DAC_ERROR_DMA : stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32f7xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32f7xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DCMI_ERROR_NONE : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_OVF : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_SYNC : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_ERROR_TIMEOUT : stm32f7xx_hal_dcmi.h
  • HAL_DCMI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DMA2D_ERROR_CE : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_NONE : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TE : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_ERROR_TIMEOUT : stm32f7xx_hal_dma2d.h
  • HAL_DMA2D_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_DMA_ERROR_DME : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f7xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f7xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_ETH_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_FLASH_ERROR_ERS : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_OPERATION : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_PGP : stm32f7xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f7xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_HASH_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_HCD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32f7xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f7xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_I2S_ERROR_DMA : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32f7xx_hal_i2s.h
  • HAL_I2S_ERROR_UNKNOW : stm32f7xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_IRDA_ERROR_DMA : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f7xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f7xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_IRDA_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32f7xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_LTDC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_QPSI_TIMEOUT_DEFAULT_VALUE : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_DMA : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32f7xx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32f7xx_hal_qspi.h
  • HAL_QSPI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_RNG_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SAI_ERROR_AFSDET : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32f7xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32f7xx_hal_sai.h
  • HAL_SAI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SDRAM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32f7xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SMARTCARD_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_smartcard.c
  • HAL_SPDIFRX_ERROR_DMA : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_NONE : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_OVR : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_PE : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_TIMEOUT : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_ERROR_UNKNOWN : stm32f7xx_hal_spdifrx.h
  • HAL_SPDIFRX_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SPI_ERROR_CRC : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f7xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32f7xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_TIM_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_TIMEOUT_DCMI_STOP : stm32f7xx_hal_dcmi.c
  • HAL_TIMEOUT_DMA2D_ABORT : stm32f7xx_hal_dma2d.c
  • HAL_TIMEOUT_DMA2D_SUSPEND : stm32f7xx_hal_dma2d.c
  • HAL_TIMEOUT_DMA_ABORT : stm32f7xx_hal_dma.c
  • HAL_UART_ERROR_DMA : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f7xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f7xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_UART_TIMEOUT_VALUE : stm32f7xx_hal_uart.h
  • HAL_UART_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_uart.c
  • HAL_USART_ERROR_DMA : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f7xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f7xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32f7xx_hal_conf.h
  • HCD_PHY_EMBEDDED : stm32f7xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32f7xx_hal_hcd.h
  • HCD_SPEED_FULL : stm32f7xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32f7xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32f7xx_hal_hcd.h
  • HIGH_CAPACITY_MMC_CARD : stm32f7xx_hal_sd.h
  • HIGH_CAPACITY_SD_CARD : stm32f7xx_hal_sd.h
  • HIGH_SPEED_MULTIMEDIA_CARD : stm32f7xx_hal_sd.h
  • HSE_STARTUP_TIMEOUT : stm32f7xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • HSE_VALUE : stm32f7xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • HSI_VALUE : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • d
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  • f
  • g
  • h
  • i
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  • t
  • u
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  • w

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32f7xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f7xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32f7xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32f7xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32f7xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32f7xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f7xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f7xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32f7xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f7xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f7xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32f7xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f7xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TC : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f7xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32f7xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32f7xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_START : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32f7xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32f7xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32f7xx_hal_i2c.h
  • I2C_IT_ERRI : stm32f7xx_hal_i2c.h
  • I2C_IT_NACKI : stm32f7xx_hal_i2c.h
  • I2C_IT_RXI : stm32f7xx_hal_i2c.h
  • I2C_IT_STOPI : stm32f7xx_hal_i2c.h
  • I2C_IT_TCI : stm32f7xx_hal_i2c.h
  • I2C_IT_TXI : stm32f7xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32f7xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f7xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f7xx_hal_i2c.h
  • I2C_NO_STARTSTOP : stm32f7xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32f7xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32f7xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32f7xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32f7xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32f7xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32f7xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32f7xx_hal_i2c.h
  • I2C_TIMEOUT_ADDR : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32f7xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32f7xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32f7xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32f7xx_hal_i2s.h
  • I2S_CLOCK_EXTERNAL : stm32f7xx_hal_i2s.h
  • I2S_CLOCK_SYSCLK : stm32f7xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32f7xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32f7xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32f7xx_hal_i2s.h
  • I2S_FLAG_BSY : stm32f7xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32f7xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32f7xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32f7xx_hal_i2s.h
  • I2S_IT_ERR : stm32f7xx_hal_i2s.h
  • I2S_IT_RXNE : stm32f7xx_hal_i2s.h
  • I2S_IT_TXE : stm32f7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32f7xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32f7xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32f7xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32f7xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32f7xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32f7xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32f7xx_hal_i2s.h
  • IDCODE_DEVID_MASK : stm32f7xx_hal.c
  • IRDA_AUTOBAUD_REQUEST : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32f7xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32f7xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32f7xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32f7xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32f7xx_hal_irda.h
  • IRDA_FLAG_FE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32f7xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f7xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f7xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32f7xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f7xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32f7xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32f7xx_hal_irda.h
  • IRDA_IT_FE : stm32f7xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f7xx_hal_irda.h
  • IRDA_IT_MASK : stm32f7xx_hal_irda.h
  • IRDA_IT_NE : stm32f7xx_hal_irda.h
  • IRDA_IT_ORE : stm32f7xx_hal_irda.h
  • IRDA_IT_PE : stm32f7xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f7xx_hal_irda.h
  • IRDA_IT_TC : stm32f7xx_hal_irda.h
  • IRDA_IT_TXE : stm32f7xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32f7xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_MODE_RX : stm32f7xx_hal_irda.h
  • IRDA_MODE_TX : stm32f7xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f7xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f7xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f7xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f7xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f7xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32f7xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32f7xx_hal_irda.h
  • IRDA_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32f7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32f7xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32f7xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG : stm32f7xx_hal_adc.h
  • IS_ADC_CHANNEL : stm32f7xx_hal_adc_ex.h
  • IS_ADC_CHANNELS_TYPE : stm32f7xx_hal_adc.h
  • IS_ADC_CLOCKPRESCALER : stm32f7xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32f7xx_hal_adc.h
  • IS_ADC_DMA_ACCESS_MODE : stm32f7xx_hal_adc_ex.h
  • IS_ADC_EOCSelection : stm32f7xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32f7xx_hal_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32f7xx_hal_adc_ex.h
  • IS_ADC_EXT_INJEC_TRIG_EDGE : stm32f7xx_hal_adc_ex.h
  • IS_ADC_EXT_TRIG : stm32f7xx_hal_adc.h
  • IS_ADC_EXT_TRIG_EDGE : stm32f7xx_hal_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32f7xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f7xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32f7xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f7xx_hal_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32f7xx_hal_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32f7xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32f7xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32f7xx_hal_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f7xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32f7xx_hal_adc.h
  • IS_ADC_THRESHOLD : stm32f7xx_hal_adc.h
  • IS_CAN_BANKNUMBER : stm32f7xx_hal_can.h
  • IS_CAN_BS1 : stm32f7xx_hal_can.h
  • IS_CAN_BS2 : stm32f7xx_hal_can.h
  • IS_CAN_DLC : stm32f7xx_hal_can.h
  • IS_CAN_EXTID : stm32f7xx_hal_can.h
  • IS_CAN_FIFO : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32f7xx_hal_can.h
  • IS_CAN_FILTER_SCALE : stm32f7xx_hal_can.h
  • IS_CAN_IDTYPE : stm32f7xx_hal_can.h
  • IS_CAN_MODE : stm32f7xx_hal_can.h
  • IS_CAN_PRESCALER : stm32f7xx_hal_can.h
  • IS_CAN_RTR : stm32f7xx_hal_can.h
  • IS_CAN_SJW : stm32f7xx_hal_can.h
  • IS_CAN_STDID : stm32f7xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f7xx_hal_can.h
  • IS_CEC_ADDRESS : stm32f7xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32f7xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32f7xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32f7xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32f7xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32f7xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32f7xx_hal_cec.h
  • IS_CEC_OAR_ADDRESS : stm32f7xx_hal_cec.h
  • IS_CEC_SFTOP : stm32f7xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32f7xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32f7xx_hal_cec.h
  • IS_CHANNEL_STATUS_MASK : stm32f7xx_hal_spdifrx.h
  • IS_CRC_INPUTDATA_FORMAT : stm32f7xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32f7xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32f7xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32f7xx_hal_crc.h
  • IS_DAC_ALIGN : stm32f7xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32f7xx_hal_dac.h
  • IS_DAC_DATA : stm32f7xx_hal_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f7xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f7xx_hal_dac.h
  • IS_DAC_TRIGGER : stm32f7xx_hal_dac.h
  • IS_DCMI_BYTE_SELECT_MODE : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_BYTE_SELECT_START : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_CAPTURE_MODE : stm32f7xx_hal_dcmi.h
  • IS_DCMI_CAPTURE_RATE : stm32f7xx_hal_dcmi.h
  • IS_DCMI_EXTENDED_DATA : stm32f7xx_hal_dcmi.h
  • IS_DCMI_HSPOLARITY : stm32f7xx_hal_dcmi.h
  • IS_DCMI_LINE_SELECT_MODE : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_LINE_SELECT_START : stm32f7xx_hal_dcmi_ex.h
  • IS_DCMI_MODE_JPEG : stm32f7xx_hal_dcmi.h
  • IS_DCMI_PCKPOLARITY : stm32f7xx_hal_dcmi.h
  • IS_DCMI_SYNCHRO : stm32f7xx_hal_dcmi.h
  • IS_DCMI_VSPOLARITY : stm32f7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_COORDINATE : stm32f7xx_hal_dcmi.h
  • IS_DCMI_WINDOW_HEIGHT : stm32f7xx_hal_dcmi.h
  • IS_DEFAULT_INIT_VALUE : stm32f7xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32f7xx_hal_crc.h
  • IS_DMA2D_ALPHA_MODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_CM : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_CLUT_SIZE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_CMODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_COLOR : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_GET_FLAG : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_INPUT_COLOR_MODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_IT : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_LAYER : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_LINE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_LineWatermark : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_MODE : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_OFFSET : stm32f7xx_hal_dma2d.h
  • IS_DMA2D_PIXEL : stm32f7xx_hal_dma2d.h
  • IS_DMA_BUFFER_SIZE : stm32f7xx_hal_dma.h
  • IS_DMA_CHANNEL : stm32f7xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f7xx_hal_dma.h
  • IS_DMA_FIFO_MODE_STATE : stm32f7xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32f7xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32f7xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f7xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f7xx_hal_dma.h
  • IS_DMA_MODE : stm32f7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32f7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f7xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f7xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f7xx_hal_dma.h
  • IS_ETH_ADDRESS_ALIGNED_BEATS : stm32f7xx_hal_eth.h
  • IS_ETH_AUTOMATIC_PADCRC_STRIP : stm32f7xx_hal_eth.h
  • IS_ETH_AUTONEGOTIATION : stm32f7xx_hal_eth.h
  • IS_ETH_BACKOFF_LIMIT : stm32f7xx_hal_eth.h
  • IS_ETH_BROADCAST_FRAMES_RECEPTION : stm32f7xx_hal_eth.h
  • IS_ETH_CARRIER_SENSE : stm32f7xx_hal_eth.h
  • IS_ETH_CHECKSUM_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_CHECKSUM_OFFLOAD : stm32f7xx_hal_eth.h
  • IS_ETH_CONTROL_FRAMES : stm32f7xx_hal_eth.h
  • IS_ETH_DEFERRAL_CHECK : stm32f7xx_hal_eth.h
  • IS_ETH_DESTINATION_ADDR_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_DESC_SKIP_LENGTH : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_GET_IT : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_GET_OVERFLOW : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_IT : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_RXDESC_BUFFER : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_TXDESC_CHECKSUM : stm32f7xx_hal_eth.h
  • IS_ETH_DMA_TXDESC_SEGMENT : stm32f7xx_hal_eth.h
  • IS_ETH_DMARXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DMATXDESC_BUFFER_SIZE : stm32f7xx_hal_eth.h
  • IS_ETH_DMATXDESC_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_DROP_TCPIP_CHECKSUM_FRAME : stm32f7xx_hal_eth.h
  • IS_ETH_DUPLEX_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_ENHANCED_DESCRIPTOR_FORMAT : stm32f7xx_hal_eth.h
  • IS_ETH_FIXED_BURST : stm32f7xx_hal_eth.h
  • IS_ETH_FLUSH_RECEIVE_FRAME : stm32f7xx_hal_eth.h
  • IS_ETH_FORWARD_ERROR_FRAMES : stm32f7xx_hal_eth.h
  • IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES : stm32f7xx_hal_eth.h
  • IS_ETH_INTER_FRAME_GAP : stm32f7xx_hal_eth.h
  • IS_ETH_JABBER : stm32f7xx_hal_eth.h
  • IS_ETH_LOOPBACK_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS0123 : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS123 : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_ADDRESS_MASK : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_GET_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MAC_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MEDIA_INTERFACE : stm32f7xx_hal_eth.h
  • IS_ETH_MMC_GET_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MMC_IT : stm32f7xx_hal_eth.h
  • IS_ETH_MULTICAST_FRAMES_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_PAUSE_LOW_THRESHOLD : stm32f7xx_hal_eth.h
  • IS_ETH_PAUSE_TIME : stm32f7xx_hal_eth.h
  • IS_ETH_PHY_ADDRESS : stm32f7xx_hal_eth.h
  • IS_ETH_PMT_GET_FLAG : stm32f7xx_hal_eth.h
  • IS_ETH_PROMISCUOUS_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_ALL : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_FLOWCONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_OWN : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_STORE_FORWARD : stm32f7xx_hal_eth.h
  • IS_ETH_RECEIVE_THRESHOLD_CONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_RETRY_TRANSMISSION : stm32f7xx_hal_eth.h
  • IS_ETH_RX_MODE : stm32f7xx_hal_eth.h
  • IS_ETH_RXDMA_BURST_LENGTH : stm32f7xx_hal_eth.h
  • IS_ETH_SECOND_FRAME_OPERATE : stm32f7xx_hal_eth.h
  • IS_ETH_SOURCE_ADDR_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_SPEED : stm32f7xx_hal_eth.h
  • IS_ETH_TRANSMIT_FLOWCONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_TRANSMIT_STORE_FORWARD : stm32f7xx_hal_eth.h
  • IS_ETH_TRANSMIT_THRESHOLD_CONTROL : stm32f7xx_hal_eth.h
  • IS_ETH_TXDMA_BURST_LENGTH : stm32f7xx_hal_eth.h
  • IS_ETH_UNICAST_FRAMES_FILTER : stm32f7xx_hal_eth.h
  • IS_ETH_UNICAST_PAUSE_FRAME_DETECT : stm32f7xx_hal_eth.h
  • IS_ETH_VLAN_TAG_COMPARISON : stm32f7xx_hal_eth.h
  • IS_ETH_VLAN_TAG_IDENTIFIER : stm32f7xx_hal_eth.h
  • IS_ETH_WATCHDOG : stm32f7xx_hal_eth.h
  • IS_ETH_ZEROQUANTA_PAUSE : stm32f7xx_hal_eth.h
  • IS_FLASH_ADDRESS : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_LATENCY : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_NBSECTORS : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_SECTOR : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f7xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f7xx_hal_flash.h
  • IS_GPIO_AF : stm32f7xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32f7xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f7xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f7xx_hal_gpio.h
  • IS_GPIO_PIN_AVAILABLE : stm32f7xx_hal_gpio_ex.h
  • IS_GPIO_PULL : stm32f7xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f7xx_hal_gpio.h
  • IS_HCD_ALL_INSTANCE : stm32f7xx_hal_hcd.h
  • IS_I2C_ADDRESSING_MODE : stm32f7xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32f7xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32f7xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32f7xx_hal_i2c.h
  • IS_I2C_GENERAL_CALL : stm32f7xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f7xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f7xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32f7xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f7xx_hal_i2s.h
  • IS_I2S_CLOCKSOURCE : stm32f7xx_hal_i2s.h
  • IS_I2S_CPOL : stm32f7xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32f7xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32f7xx_hal_i2s.h
  • IS_I2S_MODE : stm32f7xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32f7xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32f7xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32f7xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32f7xx_hal_irda.h
  • IS_IRDA_MODE : stm32f7xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32f7xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f7xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f7xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32f7xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32f7xx_hal_irda.h
  • IS_IRDA_STATE : stm32f7xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32f7xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f7xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32f7xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f7xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32f7xx_hal_iwdg.h
  • IS_LIN_WORD_LENGTH : stm32f7xx_hal_uart_ex.h
  • IS_LPTIM_AUTORELOAD : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32f7xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32f7xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32f7xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32f7xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32f7xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32f7xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32f7xx_hal_lptim.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32f7xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32f7xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32f7xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32f7xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32f7xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f7xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f7xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f7xx_hal_cortex.h
  • IS_OB_BOOT_ADDRESS : stm32f7xx_hal_flash_ex.h
  • IS_OB_BOR_LEVEL : stm32f7xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OB_IWDG_STDBY_FREEZE : stm32f7xx_hal_flash_ex.h
  • IS_OB_IWDG_STOP_FREEZE : stm32f7xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f7xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32f7xx_hal_flash_ex.h
  • IS_OB_WWDG_SOURCE : stm32f7xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f7xx_hal_flash_ex.h
  • IS_PARITY_ERROR_MASK : stm32f7xx_hal_spdifrx.h
  • IS_PCD_ALL_INSTANCE : stm32f7xx_hal_pcd.h
  • IS_PREAMBLE_TYPE_MASK : stm32f7xx_hal_spdifrx.h
  • IS_PWR_PVD_LEVEL : stm32f7xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32f7xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32f7xx_hal_pwr.h
  • IS_PWR_REGULATOR_UNDERDRIVE : stm32f7xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR_VOLTAGE : stm32f7xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32f7xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f7xx_hal_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32f7xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_POLARITY : stm32f7xx_hal_pwr.h
  • IS_QSPI_ADDRESS_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32f7xx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32f7xx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32f7xx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_DDR_HHC : stm32f7xx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_DUAL_FLASH_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32f7xx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32f7xx_hal_qspi.h
  • IS_QSPI_FLASH_ID : stm32f7xx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32f7xx_hal_qspi.c
  • IS_QSPI_GET_FLAG : stm32f7xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION : stm32f7xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32f7xx_hal_qspi.h
  • IS_QSPI_IT : stm32f7xx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32f7xx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32f7xx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32f7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32f7xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32f7xx_hal_qspi.h
  • IS_RCC_CALIBRATION_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_CECCLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_CLK48SOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32f7xx_hal_rcc.h
  • IS_RCC_HCLK : stm32f7xx_hal_rcc.h
  • IS_RCC_HSE : stm32f7xx_hal_rcc.h
  • IS_RCC_HSI : stm32f7xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2C4CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_I2SCLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32f7xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32f7xx_hal_rcc.h
  • IS_RCC_LSI : stm32f7xx_hal_rcc.h
  • IS_RCC_MCO : stm32f7xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32f7xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32f7xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f7xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLI2S_DIVQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SN_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SP_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SR_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLM_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32f7xx_hal_rcc.h
  • IS_RCC_PLLSAI_DIVQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI_DIVR_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIN_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIP_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIQ_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSAIR_VALUE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_RTCCLKSOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_SAI1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_SAI2CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_SDMMC1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32f7xx_hal_rcc.h
  • IS_RCC_TIMPRES : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART4CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART7CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_UART8CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RCC_USART6CLKSOURCE : stm32f7xx_hal_rcc_ex.h
  • IS_RNG_FLAG : stm32f7xx_hal_rng.h
  • IS_RNG_IT : stm32f7xx_hal_rng.h
  • IS_RTC_ALARM : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32f7xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32f7xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f7xx_hal_rtc.h
  • IS_RTC_BKP : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32f7xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32f7xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f7xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32f7xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f7xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32f7xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32f7xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f7xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f7xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32f7xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32f7xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f7xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32f7xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32f7xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32f7xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32f7xx_hal_rtc.h
  • IS_RTC_YEAR : stm32f7xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_STATUS : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32f7xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32f7xx_hal_sai.h
  • IS_SAI_CLK_SOURCE : stm32f7xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32f7xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32f7xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32f7xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32f7xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32f7xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f7xx_hal_smartcard.h
  • IS_SPDIFRX_CHANNEL : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_DATA_FORMAT : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_INPUT_SELECT : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_MAX_RETRIES : stm32f7xx_hal_spdifrx.h
  • IS_SPDIFRX_WAIT_FOR_ACTIVITY : stm32f7xx_hal_spdifrx.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f7xx_hal_spi.h
  • IS_SPI_CPHA : stm32f7xx_hal_spi.h
  • IS_SPI_CPOL : stm32f7xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f7xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32f7xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f7xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f7xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f7xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f7xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f7xx_hal_spi.h
  • IS_SPI_MODE : stm32f7xx_hal_spi.h
  • IS_SPI_NSS : stm32f7xx_hal_spi.h
  • IS_SPI_NSSP : stm32f7xx_hal_spi.h
  • IS_SPI_TIMODE : stm32f7xx_hal_spi.h
  • IS_STEREO_MODE : stm32f7xx_hal_spdifrx.h
  • IS_SYSTICK_CLK_SOURCE : stm32f7xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32f7xx_hal_tim_ex.h
  • IS_TIM_BREAK2_STATE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_BREAK_FILTER : stm32f7xx_hal_tim_ex.h
  • IS_TIM_BREAK_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f7xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f7xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_COUNTER_MODE : stm32f7xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f7xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f7xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f7xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f7xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_FLAG : stm32f7xx_hal_tim.h
  • IS_TIM_GET_IT : stm32f7xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32f7xx_hal_tim_ex.h
  • IS_TIM_IC_FILTER : stm32f7xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f7xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGER_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_IT : stm32f7xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f7xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_OC_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_OPM_MODE : stm32f7xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OUTPUT_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_OUTPUTN_STATE : stm32f7xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_PWMI_CHANNELS : stm32f7xx_hal_tim_ex.h
  • IS_TIM_REMAP : stm32f7xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_TI1SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_TRGO2_SOURCE : stm32f7xx_hal_tim_ex.h
  • IS_TIM_TRGO_SOURCE : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f7xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f7xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32f7xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32f7xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32f7xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32f7xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32f7xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32f7xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32f7xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f7xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32f7xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32f7xx_hal_uart.h
  • IS_UART_DMA_RX : stm32f7xx_hal_uart.h
  • IS_UART_DMA_TX : stm32f7xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32f7xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f7xx_hal_uart.h
  • IS_UART_LIN : stm32f7xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f7xx_hal_uart.h
  • IS_UART_MODE : stm32f7xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32f7xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32f7xx_hal_uart.h
  • IS_UART_OVERRUN : stm32f7xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32f7xx_hal_uart.h
  • IS_UART_PARITY : stm32f7xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32f7xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32f7xx_hal_uart.h
  • IS_UART_STATE : stm32f7xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f7xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f7xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f7xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32f7xx_hal_usart.h
  • IS_USART_CLOCK : stm32f7xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f7xx_hal_usart.h
  • IS_USART_MODE : stm32f7xx_hal_usart.h
  • IS_USART_OVERSAMPLING : stm32f7xx_hal_usart.h
  • IS_USART_PARITY : stm32f7xx_hal_usart.h
  • IS_USART_PHASE : stm32f7xx_hal_usart.h
  • IS_USART_POLARITY : stm32f7xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32f7xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f7xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f7xx_hal_usart_ex.h
  • IS_VALIDITY_MASK : stm32f7xx_hal_spdifrx.h
  • IS_VOLTAGERANGE : stm32f7xx_hal_flash_ex.h
  • IS_WRPSTATE : stm32f7xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f7xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f7xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f7xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f7xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f7xx_hal_iwdg.h
  • IWDG_FLAG_PVU : stm32f7xx_hal_iwdg.h
  • IWDG_FLAG_RVU : stm32f7xx_hal_iwdg.h
  • IWDG_FLAG_WVU : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f7xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f7xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f7xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32f7xx_hal_iwdg.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- l -

  • LINE_WATERMARK : stm32f7xx_hal_dma2d.h
  • LINKED_STATE_TIMEOUT_VALUE : stm32f7xx_hal_eth.c
  • LPTIM_ACTIVEEDGE_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32f7xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32f7xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32f7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32f7xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32f7xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32f7xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32f7xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32f7xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32f7xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32f7xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32f7xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32f7xx_hal_lptim.h
  • LPTIM_IT_UP : stm32f7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32f7xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32f7xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32f7xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32f7xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32f7xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32f7xx_hal_lptim.h
  • LSE_VALUE : stm32f7xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • LSI_VALUE : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- m -

  • MAC_ADDR0 : stm32f7xx_hal_conf.h
  • MAC_ADDR1 : stm32f7xx_hal_conf.h
  • MAC_ADDR2 : stm32f7xx_hal_conf.h
  • MAC_ADDR3 : stm32f7xx_hal_conf.h
  • MAC_ADDR4 : stm32f7xx_hal_conf.h
  • MAC_ADDR5 : stm32f7xx_hal_conf.h
  • MAX_DMA2D_LAYER : stm32f7xx_hal_dma2d.h
  • MC_ADDRESS : stm32f7xx_hal_nor.h
  • MCO1_CLK_ENABLE : stm32f7xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32f7xx_hal_rcc.c
  • MCO1_PIN : stm32f7xx_hal_rcc.c
  • MCO2_CLK_ENABLE : stm32f7xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32f7xx_hal_rcc.c
  • MCO2_PIN : stm32f7xx_hal_rcc.c
  • MPU_ACCESS_BUFFERABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32f7xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32f7xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32f7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32f7xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32f7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32f7xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32f7xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32f7xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32f7xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32f7xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32f7xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32f7xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32f7xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32f7xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32f7xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32f7xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32f7xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32f7xx_hal_cortex.h
  • MULTIMEDIA_CARD : stm32f7xx_hal_sd.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- n -

  • NAND_BUSY : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32f7xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32f7xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32f7xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32f7xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32f7xx_hal_nand.h
  • NAND_CMD_READID : stm32f7xx_hal_nand.h
  • NAND_CMD_RESET : stm32f7xx_hal_nand.h
  • NAND_CMD_STATUS : stm32f7xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32f7xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32f7xx_hal_nand.h
  • NAND_DEVICE : stm32f7xx_hal_nand.h
  • NAND_ERROR : stm32f7xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32f7xx_hal_nand.h
  • NAND_READY : stm32f7xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32f7xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32f7xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32f7xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32f7xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32f7xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32f7xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32f7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32f7xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32f7xx_hal_nor.c
  • NOR_MEMORY_16B : stm32f7xx_hal_nor.h
  • NOR_MEMORY_8B : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32f7xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32f7xx_hal_nor.h
  • NOR_TMEOUT : stm32f7xx_hal_nor.h
  • NOR_WRITE : stm32f7xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f7xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f7xx_hal_cortex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- o -

  • OB_BOOTADDR_AXIM_FLASH : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_DTCM_RAM : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_FLASH : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_ITCM_RAM : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM1 : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_SRAM2 : stm32f7xx_hal_flash_ex.h
  • OB_BOOTADDR_SYSTEM : stm32f7xx_hal_flash_ex.h
  • OB_BOR_LEVEL1 : stm32f7xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32f7xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32f7xx_hal_flash_ex.h
  • OB_BOR_OFF : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_ACTIVE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STDBY_FREEZE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STOP_ACTIVE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_STOP_FREEZE : stm32f7xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f7xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32f7xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f7xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f7xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f7xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_1 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_2 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_3 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_5 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_6 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_7 : stm32f7xx_hal_flash_ex.h
  • OB_WRP_SECTOR_All : stm32f7xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f7xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f7xx_hal_flash_ex.h
  • OB_WWDG_HW : stm32f7xx_hal_flash_ex.h
  • OB_WWDG_SW : stm32f7xx_hal_flash_ex.h
  • OPTCR_BYTE1_ADDRESS : stm32f7xx_hal_flash.h
  • OPTIONBYTE_BOOTADDR_0 : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_BOOTADDR_1 : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_BOR : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f7xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f7xx_hal_flash_ex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- p -

  • PCD_MAX : stm32f7xx_hal_pcd.c
  • PCD_MIN : stm32f7xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32f7xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32f7xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32f7xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32f7xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32f7xx_hal_pcd.h
  • PHY_AUTONEGO_COMPLETE : stm32f7xx_hal_conf.h
  • PHY_AUTONEGOTIATION : stm32f7xx_hal_conf.h
  • PHY_BCR : stm32f7xx_hal_conf.h
  • PHY_BSR : stm32f7xx_hal_conf.h
  • PHY_CONFIG_DELAY : stm32f7xx_hal_conf.h
  • PHY_DUPLEX_STATUS : stm32f7xx_hal_conf.h
  • PHY_FULLDUPLEX_100M : stm32f7xx_hal_conf.h
  • PHY_FULLDUPLEX_10M : stm32f7xx_hal_conf.h
  • PHY_HALFDUPLEX_100M : stm32f7xx_hal_conf.h
  • PHY_HALFDUPLEX_10M : stm32f7xx_hal_conf.h
  • PHY_ISOLATE : stm32f7xx_hal_conf.h
  • PHY_JABBER_DETECTION : stm32f7xx_hal_conf.h
  • PHY_LINK_INTERRUPT : stm32f7xx_hal_conf.h
  • PHY_LINK_STATUS : stm32f7xx_hal_conf.h
  • PHY_LINKED_STATUS : stm32f7xx_hal_conf.h
  • PHY_LOOPBACK : stm32f7xx_hal_conf.h
  • PHY_MICR : stm32f7xx_hal_conf.h
  • PHY_MICR_INT_EN : stm32f7xx_hal_conf.h
  • PHY_MICR_INT_OE : stm32f7xx_hal_conf.h
  • PHY_MISR : stm32f7xx_hal_conf.h
  • PHY_MISR_LINK_INT_EN : stm32f7xx_hal_conf.h
  • PHY_POWERDOWN : stm32f7xx_hal_conf.h
  • PHY_READ_TO : stm32f7xx_hal_conf.h
  • PHY_RESET : stm32f7xx_hal_conf.h
  • PHY_RESET_DELAY : stm32f7xx_hal_conf.h
  • PHY_RESTART_AUTONEGOTIATION : stm32f7xx_hal_conf.h
  • PHY_SPEED_STATUS : stm32f7xx_hal_conf.h
  • PHY_SR : stm32f7xx_hal_conf.h
  • PHY_WRITE_TO : stm32f7xx_hal_conf.h
  • PLL_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • PLLI2S_TIMEOUT_VALUE : stm32f7xx_hal_rcc_ex.c
  • PLLSAI_TIMEOUT_VALUE : stm32f7xx_hal_rcc_ex.c
  • PREFETCH_ENABLE : stm32f7xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f7xx_hal_pwr.c
  • PVD_MODE_EVT : stm32f7xx_hal_pwr.c
  • PVD_MODE_IT : stm32f7xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32f7xx_hal_pwr.c
  • PWR_BKPREG_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_EWUP_MASK : stm32f7xx_hal_pwr.c
  • PWR_EXTI_LINE_PVD : stm32f7xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32f7xx_hal_pwr.h
  • PWR_FLAG_ODRDY : stm32f7xx_hal_pwr_ex.h
  • PWR_FLAG_ODSWRDY : stm32f7xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32f7xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f7xx_hal_pwr.h
  • PWR_FLAG_UDRDY : stm32f7xx_hal_pwr_ex.h
  • PWR_FLAG_VOSRDY : stm32f7xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f7xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f7xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON : stm32f7xx_hal_pwr_ex.h
  • PWR_MAINREGULATOR_ON : stm32f7xx_hal_pwr.h
  • PWR_MAINREGULATOR_UNDERDRIVE_ON : stm32f7xx_hal_pwr_ex.h
  • PWR_OVERDRIVE_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f7xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32f7xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32f7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32f7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32f7xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32f7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32f7xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f7xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f7xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f7xx_hal_pwr.h
  • PWR_UDERDRIVE_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_VOSRDY_TIMEOUT_VALUE : stm32f7xx_hal_pwr_ex.c
  • PWR_WAKEUP_PIN1 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_HIGH : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN6_LOW : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG1 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG2 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG3 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG4 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG5 : stm32f7xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN_FLAG6 : stm32f7xx_hal_pwr_ex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- q -

  • QSPI_ADDRESS_16_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32f7xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32f7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32f7xx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32f7xx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_DATA_NONE : stm32f7xx_hal_qspi.h
  • QSPI_DDR_HHC_ANALOG_DELAY : stm32f7xx_hal_qspi.h
  • QSPI_DDR_HHC_HALF_CLK_DELAY : stm32f7xx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_DUALFLASH_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_DUALFLASH_ENABLE : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_BUSY : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_FT : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_SM : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_TC : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_TE : stm32f7xx_hal_qspi.h
  • QSPI_FLAG_TO : stm32f7xx_hal_qspi.h
  • QSPI_FLASH_ID_1 : stm32f7xx_hal_qspi.h
  • QSPI_FLASH_ID_2 : stm32f7xx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32f7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32f7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32f7xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32f7xx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32f7xx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32f7xx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32f7xx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32f7xx_hal_qspi.h
  • QSPI_IT_FT : stm32f7xx_hal_qspi.h
  • QSPI_IT_SM : stm32f7xx_hal_qspi.h
  • QSPI_IT_TC : stm32f7xx_hal_qspi.h
  • QSPI_IT_TE : stm32f7xx_hal_qspi.h
  • QSPI_IT_TO : stm32f7xx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32f7xx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32f7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32f7xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32f7xx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32f7xx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32f7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32f7xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32f7xx_hal_qspi.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- r -

  • RCC_CECCLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_CIR_BYTE1_ADDRESS : stm32f7xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f7xx_hal_rcc.h
  • RCC_CLK48SOURCE_PLL : stm32f7xx_hal_rcc_ex.h
  • RCC_CLK48SOURCE_PLLSAIP : stm32f7xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_HCLK : stm32f7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f7xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f7xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f7xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • RCC_FLAG_BORRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PLLI2SRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PLLSAIRDY : stm32f7xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f7xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f7xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f7xx_hal_rcc.h
  • RCC_HSE_ON : stm32f7xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f7xx_hal_rcc.h
  • RCC_HSI_ON : stm32f7xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_I2C4CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_EXT : stm32f7xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32f7xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f7xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f7xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_PLLI2SRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f7xx_hal_rcc.h
  • RCC_IT_PLLSAIRDY : stm32f7xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32f7xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32f7xx_hal_rcc.h
  • RCC_LSE_OFF : stm32f7xx_hal_rcc.h
  • RCC_LSE_ON : stm32f7xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32f7xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32f7xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f7xx_hal_rcc.h
  • RCC_LSI_ON : stm32f7xx_hal_rcc.h
  • RCC_MCO1 : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32f7xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_MCO2 : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLI2SCLK : stm32f7xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32f7xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f7xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f7xx_hal_rcc.h
  • RCC_PERIPHCLK_CEC : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CLK48 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SPDIFRX : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART7 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32f7xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART6 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32f7xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f7xx_hal_rcc.h
  • RCC_PLL_ON : stm32f7xx_hal_rcc.h
  • RCC_PLLI2SP_DIV2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLI2SP_DIV4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLI2SP_DIV6 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLI2SP_DIV8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLP_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32f7xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_PLLSAIDIVR_16 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIDIVR_2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIDIVR_4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIDIVR_8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV2 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV4 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV6 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSAIP_DIV8 : stm32f7xx_hal_rcc_ex.h
  • RCC_PLLSOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f7xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f7xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_PIN : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PIN : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLI2S : stm32f7xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLSAI : stm32f7xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_CLK48 : stm32f7xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f7xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f7xx_hal_rcc.h
  • RCC_TIMPRES_ACTIVATED : stm32f7xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART7CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_UART8CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_HSI : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_LSE : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_PCLK2 : stm32f7xx_hal_rcc_ex.h
  • RCC_USART6CLKSOURCE_SYSCLK : stm32f7xx_hal_rcc_ex.h
  • RISING_EDGE : stm32f7xx_hal_gpio.c
  • RNG_FLAG_CECS : stm32f7xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32f7xx_hal_rng.h
  • RNG_FLAG_SECS : stm32f7xx_hal_rng.h
  • RNG_IT_CEI : stm32f7xx_hal_rng.h
  • RNG_IT_DRDY : stm32f7xx_hal_rng.h
  • RNG_IT_SEI : stm32f7xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32f7xx_hal_rng.c
  • RTC_ALARM_A : stm32f7xx_hal_rtc.h
  • RTC_ALARM_B : stm32f7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32f7xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32f7xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32f7xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32f7xx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR0 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f7xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32f7xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32f7xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32f7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32f7xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32f7xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32f7xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f7xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32f7xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f7xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32f7xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32f7xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32f7xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f7xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32f7xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32f7xx_hal_rtc.h
  • RTC_INIT_MASK : stm32f7xx_hal_rtc.h
  • RTC_IT_ALRA : stm32f7xx_hal_rtc.h
  • RTC_IT_ALRB : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32f7xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32f7xx_hal_rtc.h
  • RTC_IT_TS : stm32f7xx_hal_rtc.h
  • RTC_IT_WUT : stm32f7xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f7xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f7xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f7xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f7xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f7xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f7xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f7xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f7xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_ALARMA : stm32f7xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32f7xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32f7xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32f7xx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32f7xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32f7xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32f7xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32f7xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32f7xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32f7xx_hal_rtc.h
  • RTC_TAMPCR_TAMPXE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPCR_TAMPXIE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER1_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f7xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f7xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_POS1 : stm32f7xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_POS2 : stm32f7xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32f7xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32f7xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32f7xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f7xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f7xx_hal_rtc.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- s -

  • SAI_AC97_PROTOCOL : stm32f7xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32f7xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_EXT : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_NA : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_PLLI2S : stm32f7xx_hal_sai.h
  • SAI_CLKSOURCE_PLLSAI : stm32f7xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32f7xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32f7xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32f7xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32f7xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32f7xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32f7xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32f7xx_hal_sai.h
  • SAI_FIRSTBIT_LSB : stm32f7xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32f7xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32f7xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32f7xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32f7xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32f7xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32f7xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32f7xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32f7xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32f7xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32f7xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32f7xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32f7xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32f7xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32f7xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32f7xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32f7xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32f7xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32f7xx_hal_sai.h
  • SAI_IT_AFSDET : stm32f7xx_hal_sai.h
  • SAI_IT_CNRDY : stm32f7xx_hal_sai.h
  • SAI_IT_FREQ : stm32f7xx_hal_sai.h
  • SAI_IT_LFSDET : stm32f7xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32f7xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32f7xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32f7xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32f7xx_hal_sai.h
  • SAI_MASTERDIVIDER_DISABLE : stm32f7xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32f7xx_hal_sai.h
  • SAI_MODEMASTER_RX : stm32f7xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32f7xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32f7xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32f7xx_hal_sai.h
  • SAI_MONOMODE : stm32f7xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32f7xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32f7xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32f7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32f7xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32f7xx_hal_sai.h
  • SAI_PCM_LONG : stm32f7xx_hal_sai.h
  • SAI_PCM_SHORT : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32f7xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32f7xx_hal_sai.h
  • SAI_SLOT_NOTACTIVE : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32f7xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32f7xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32f7xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32f7xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32f7xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32f7xx_hal_sai.h
  • SAI_STEREOMODE : stm32f7xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32f7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32f7xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32f7xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32f7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32f7xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32f7xx_hal_sai.h
  • SAI_TIMEOUT_VALUE : stm32f7xx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32f7xx_hal_sai.h
  • SAI_xCR2_MUTECNT_OFFSET : stm32f7xx_hal_sai.c
  • SAI_ZERO_VALUE : stm32f7xx_hal_sai.h
  • SD_0TO7BITS : stm32f7xx_hal_sd.c
  • SD_16TO23BITS : stm32f7xx_hal_sd.c
  • SD_24TO31BITS : stm32f7xx_hal_sd.c
  • SD_8TO15BITS : stm32f7xx_hal_sd.c
  • SD_ALLZERO : stm32f7xx_hal_sd.c
  • SD_CARD_LOCKED : stm32f7xx_hal_sd.c
  • SD_CCCC_ERASE : stm32f7xx_hal_sd.c
  • SD_CCCC_LOCK_UNLOCK : stm32f7xx_hal_sd.c
  • SD_CCCC_WRITE_PROT : stm32f7xx_hal_sd.c
  • SD_CHECK_PATTERN : stm32f7xx_hal_sd.c
  • SD_CMD_ALL_SEND_CID : stm32f7xx_hal_sd.h
  • SD_CMD_APP_CMD : stm32f7xx_hal_sd.h
  • SD_CMD_APP_SD_SET_BUSWIDTH : stm32f7xx_hal_sd.h
  • SD_CMD_CLR_WRITE_PROT : stm32f7xx_hal_sd.h
  • SD_CMD_ERASE : stm32f7xx_hal_sd.h
  • SD_CMD_ERASE_GRP_END : stm32f7xx_hal_sd.h
  • SD_CMD_ERASE_GRP_START : stm32f7xx_hal_sd.h
  • SD_CMD_FAST_IO : stm32f7xx_hal_sd.h
  • SD_CMD_GEN_CMD : stm32f7xx_hal_sd.h
  • SD_CMD_GO_IDLE_STATE : stm32f7xx_hal_sd.h
  • SD_CMD_GO_INACTIVE_STATE : stm32f7xx_hal_sd.h
  • SD_CMD_GO_IRQ_STATE : stm32f7xx_hal_sd.h
  • SD_CMD_HS_BUSTEST_READ : stm32f7xx_hal_sd.h
  • SD_CMD_HS_BUSTEST_WRITE : stm32f7xx_hal_sd.h
  • SD_CMD_HS_SEND_EXT_CSD : stm32f7xx_hal_sd.h
  • SD_CMD_HS_SWITCH : stm32f7xx_hal_sd.h
  • SD_CMD_LOCK_UNLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_NO_CMD : stm32f7xx_hal_sd.h
  • SD_CMD_PROG_CID : stm32f7xx_hal_sd.h
  • SD_CMD_PROG_CSD : stm32f7xx_hal_sd.h
  • SD_CMD_READ_DAT_UNTIL_STOP : stm32f7xx_hal_sd.h
  • SD_CMD_READ_MULT_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_READ_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_CHANGE_SECURE_AREA : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_CER_RES1 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_CER_RN2 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_MID : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_GET_MKB : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_OP_COND : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_ERASE : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MKB : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SEND_SCR : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SET_CER_RES2 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SET_CER_RN1 : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_SET_CLR_CARD_DETECT : stm32f7xx_hal_sd.h
  • SD_CMD_SD_APP_STATUS : stm32f7xx_hal_sd.h
  • SD_CMD_SD_ERASE_GRP_END : stm32f7xx_hal_sd.h
  • SD_CMD_SD_ERASE_GRP_START : stm32f7xx_hal_sd.h
  • SD_CMD_SDMMC_RW_DIRECT : stm32f7xx_hal_sd.h
  • SD_CMD_SDMMC_RW_EXTENDED : stm32f7xx_hal_sd.h
  • SD_CMD_SDMMC_SEN_OP_COND : stm32f7xx_hal_sd.h
  • SD_CMD_SEL_DESEL_CARD : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_CID : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_CSD : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_OP_COND : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_STATUS : stm32f7xx_hal_sd.h
  • SD_CMD_SEND_WRITE_PROT : stm32f7xx_hal_sd.h
  • SD_CMD_SET_BLOCK_COUNT : stm32f7xx_hal_sd.h
  • SD_CMD_SET_BLOCKLEN : stm32f7xx_hal_sd.h
  • SD_CMD_SET_DSR : stm32f7xx_hal_sd.h
  • SD_CMD_SET_REL_ADDR : stm32f7xx_hal_sd.h
  • SD_CMD_SET_WRITE_PROT : stm32f7xx_hal_sd.h
  • SD_CMD_STOP_TRANSMISSION : stm32f7xx_hal_sd.h
  • SD_CMD_WRITE_DAT_UNTIL_STOP : stm32f7xx_hal_sd.h
  • SD_CMD_WRITE_MULT_BLOCK : stm32f7xx_hal_sd.h
  • SD_CMD_WRITE_SINGLE_BLOCK : stm32f7xx_hal_sd.h
  • SD_DATATIMEOUT : stm32f7xx_hal_sd.c
  • SD_HALFFIFO : stm32f7xx_hal_sd.c
  • SD_HALFFIFOBYTES : stm32f7xx_hal_sd.c
  • SD_HIGH_CAPACITY : stm32f7xx_hal_sd.c
  • SD_InitTypeDef : stm32f7xx_hal_sd.h
  • SD_MAX_DATA_LENGTH : stm32f7xx_hal_sd.c
  • SD_MAX_VOLT_TRIAL : stm32f7xx_hal_sd.c
  • SD_OCR_ADDR_MISALIGNED : stm32f7xx_hal_sd.c
  • SD_OCR_ADDR_OUT_OF_RANGE : stm32f7xx_hal_sd.c
  • SD_OCR_AKE_SEQ_ERROR : stm32f7xx_hal_sd.c
  • SD_OCR_BAD_ERASE_PARAM : stm32f7xx_hal_sd.c
  • SD_OCR_BLOCK_LEN_ERR : stm32f7xx_hal_sd.c
  • SD_OCR_CARD_ECC_DISABLED : stm32f7xx_hal_sd.c
  • SD_OCR_CARD_ECC_FAILED : stm32f7xx_hal_sd.c
  • SD_OCR_CC_ERROR : stm32f7xx_hal_sd.c
  • SD_OCR_CID_CSD_OVERWRITE : stm32f7xx_hal_sd.c
  • SD_OCR_COM_CRC_FAILED : stm32f7xx_hal_sd.c
  • SD_OCR_ERASE_RESET : stm32f7xx_hal_sd.c
  • SD_OCR_ERASE_SEQ_ERR : stm32f7xx_hal_sd.c
  • SD_OCR_ERRORBITS : stm32f7xx_hal_sd.c
  • SD_OCR_GENERAL_UNKNOWN_ERROR : stm32f7xx_hal_sd.c
  • SD_OCR_ILLEGAL_CMD : stm32f7xx_hal_sd.c
  • SD_OCR_LOCK_UNLOCK_FAILED : stm32f7xx_hal_sd.c
  • SD_OCR_STREAM_READ_UNDERRUN : stm32f7xx_hal_sd.c
  • SD_OCR_STREAM_WRITE_OVERRUN : stm32f7xx_hal_sd.c
  • SD_OCR_WP_ERASE_SKIP : stm32f7xx_hal_sd.c
  • SD_OCR_WRITE_PROT_VIOLATION : stm32f7xx_hal_sd.c
  • SD_R6_COM_CRC_FAILED : stm32f7xx_hal_sd.c
  • SD_R6_GENERAL_UNKNOWN_ERROR : stm32f7xx_hal_sd.c
  • SD_R6_ILLEGAL_CMD : stm32f7xx_hal_sd.c
  • SD_SDMMC_SEND_IF_COND : stm32f7xx_hal_sd.c
  • SD_SINGLE_BUS_SUPPORT : stm32f7xx_hal_sd.c
  • SD_STD_CAPACITY : stm32f7xx_hal_sd.c
  • SD_TypeDef : stm32f7xx_hal_sd.h
  • SD_VOLTAGE_WINDOW_SD : stm32f7xx_hal_sd.c
  • SD_WIDE_BUS_SUPPORT : stm32f7xx_hal_sd.c
  • SDMMC_CMD0TIMEOUT : stm32f7xx_hal_sd.c
  • SDMMC_STATIC_FLAGS : stm32f7xx_hal_sd.c
  • SECTOR_MASK : stm32f7xx_hal_flash.c , stm32f7xx_hal_flash_ex.c
  • SECURE_DIGITAL_IO_CARD : stm32f7xx_hal_sd.h
  • SECURE_DIGITAL_IO_COMBO_CARD : stm32f7xx_hal_sd.h
  • SLOTR_CLEAR_MASK : stm32f7xx_hal_sai.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_EOBF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_FEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_IDLEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_NEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_OREF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_PEF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_RTOF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CLEAR_TCF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32f7xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_RX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_TX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_BUSY : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_EOBF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_FE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_REACK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_RTOF : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_TEACK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_GETCLOCKSOURCE : stm32f7xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_FE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_ORE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_RTO : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f7xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f7xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f7xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f7xx_hal_smartcard.h
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32f7xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_DISABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32f7xx_hal_smartcard.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_smartcard.h
  • SMARTCARD_WORDLENGTH_9B : stm32f7xx_hal_smartcard.h
  • SPDIFRX_CHANNEL_A : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_CHANNEL_B : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_CHANNELSTATUS_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_32BITS : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_LSB : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_DATAFORMAT_MSB : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_CSRNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_FERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_OVR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_PERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_RXNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SBD : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_SYNCD : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_FLAG_TERR : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN0 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN1 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN2 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_INPUT_IN3 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_CSRNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_IFEIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_OVRIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_PERRIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_RXNE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_SBLKIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_IT_SYNCDIE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_15 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_3 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_63 : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_MAXRETRIES_NONE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PARITYERRORMASK_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_PREAMBLETYPEMASK_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STATE_IDLE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STATE_RCV : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STATE_SYNC : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_DISABLE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_STEREOMODE_ENABLE : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_TIMEOUT_VALUE : stm32f7xx_hal_spdifrx.c
  • SPDIFRX_VALIDITYMASK_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_VALIDITYMASK_ON : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_OFF : stm32f7xx_hal_spdifrx.h
  • SPDIFRX_WAITFORACTIVITY_ON : stm32f7xx_hal_spdifrx.h
  • SPI_1LINE_RX : stm32f7xx_hal_spi.h
  • SPI_1LINE_TX : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f7xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f7xx_hal_spi.h
  • SPI_CRC_LENGTH_16BIT : stm32f7xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32f7xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32f7xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32f7xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f7xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32f7xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f7xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f7xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f7xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f7xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32f7xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f7xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f7xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f7xx_hal_spi.h
  • SPI_FLAG_FRE : stm32f7xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32f7xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32f7xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f7xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f7xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f7xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f7xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32f7xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32f7xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32f7xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32f7xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32f7xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32f7xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32f7xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32f7xx_hal_spi.h
  • SPI_IT_ERR : stm32f7xx_hal_spi.h
  • SPI_IT_RXNE : stm32f7xx_hal_spi.h
  • SPI_IT_TXE : stm32f7xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f7xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f7xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f7xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f7xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32f7xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32f7xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f7xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f7xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f7xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f7xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f7xx_hal_spi.h
  • SPI_RESET_CRC : stm32f7xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32f7xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32f7xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32f7xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32f7xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32f7xx_hal_spi.h
  • STD_CAPACITY_SD_CARD_V1_1 : stm32f7xx_hal_sd.h
  • STD_CAPACITY_SD_CARD_V2_0 : stm32f7xx_hal_sd.h
  • SYSTICK_CLKSOURCE_HCLK : stm32f7xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f7xx_hal_cortex.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- t -

  • TEACK_REACK_TIMEOUT : stm32f7xx_hal_irda.c , stm32f7xx_hal_smartcard.c , stm32f7xx_hal_usart.c
  • TICK_INT_PRIORITY : stm32f7xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f7xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f7xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK2_ENABLE : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_HIGH : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK2POLARITY_LOW : stm32f7xx_hal_tim_ex.h
  • TIM_BREAK_DISABLE : stm32f7xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f7xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f7xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f7xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32f7xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f7xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f7xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f7xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32f7xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f7xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_2 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_3 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_4 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_5 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_6 : stm32f7xx_hal_tim_ex.h
  • TIM_CHANNEL_ALL : stm32f7xx_hal_tim_ex.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f7xx_hal_tim_ex.h
  • TIM_CLEARINPUTSOURCE_OCREFCLR : stm32f7xx_hal_tim_ex.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f7xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f7xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f7xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f7xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f7xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f7xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f7xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f7xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f7xx_hal_tim.h
  • TIM_DMA_COM : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f7xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f7xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32f7xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32f7xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_OR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32f7xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32f7xx_hal_tim.h
  • TIM_DMABASE_SR : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f7xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32f7xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f7xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f7xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32f7xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32f7xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f7xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f7xx_hal_tim.h
  • TIM_FLAG_COM : stm32f7xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f7xx_hal_tim.h
  • TIM_GROUPCH5_NONE : stm32f7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC1REFC : stm32f7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC2REFC : stm32f7xx_hal_tim_ex.h
  • TIM_GROUPCH5_OC3REFC : stm32f7xx_hal_tim_ex.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f7xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f7xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f7xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f7xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_IT_BREAK : stm32f7xx_hal_tim.h
  • TIM_IT_CC1 : stm32f7xx_hal_tim.h
  • TIM_IT_CC2 : stm32f7xx_hal_tim.h
  • TIM_IT_CC3 : stm32f7xx_hal_tim.h
  • TIM_IT_CC4 : stm32f7xx_hal_tim.h
  • TIM_IT_COM : stm32f7xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f7xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f7xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f7xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f7xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f7xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_INACTIVE : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_PWM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_TIMING : stm32f7xx_hal_tim_ex.h
  • TIM_OCMODE_TOGGLE : stm32f7xx_hal_tim_ex.h
  • TIM_OCNIDLESTATE_RESET : stm32f7xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f7xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f7xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f7xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f7xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f7xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f7xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f7xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32f7xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32f7xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f7xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f7xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f7xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f7xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_DISABLE : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_GATED : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_RESET : stm32f7xx_hal_tim_ex.h
  • TIM_SLAVEMODE_TRIGGER : stm32f7xx_hal_tim_ex.h
  • TIM_TI1SELECTION_CH1 : stm32f7xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f7xx_hal_tim.h
  • TIM_TIM11_GPIO : stm32f7xx_hal_tim_ex.h
  • TIM_TIM11_HSE : stm32f7xx_hal_tim_ex.h
  • TIM_TIM11_MCO1 : stm32f7xx_hal_tim_ex.h
  • TIM_TIM11_SPDIFRX : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_ETH_PTP : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_TIM8_TRGO : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_USBFS_SOF : stm32f7xx_hal_tim_ex.h
  • TIM_TIM2_USBHS_SOF : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_GPIO : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_LSE : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_LSI : stm32f7xx_hal_tim_ex.h
  • TIM_TIM5_RTC : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC1 : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC1REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC2REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC3REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC5REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC6REF : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_RESET : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO2_UPDATE : stm32f7xx_hal_tim_ex.h
  • TIM_TRGO_ENABLE : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f7xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f7xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f7xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f7xx_hal_tim.h
  • TIM_TS_ETRF : stm32f7xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f7xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f7xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f7xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f7xx_hal_tim.h
  • TIM_TS_NONE : stm32f7xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f7xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f7xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f7xx_hal_tim.h
  • TIMING_CLEAR_MASK : stm32f7xx_hal_i2c.c
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- u -

  • UART_ADDRESS_DETECT_4B : stm32f7xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32f7xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32f7xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32f7xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32f7xx_hal_uart.h
  • UART_CLEAR_CMF : stm32f7xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32f7xx_hal_uart.h
  • UART_CLEAR_EOBF : stm32f7xx_hal_uart.h
  • UART_CLEAR_FEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32f7xx_hal_uart.h
  • UART_CLEAR_NEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_OREF : stm32f7xx_hal_uart.h
  • UART_CLEAR_PEF : stm32f7xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32f7xx_hal_uart.h
  • UART_CLEAR_TCF : stm32f7xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32f7xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32f7xx_hal_uart.h
  • UART_CR1_FIELDS : stm32f7xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32f7xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32f7xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32f7xx_hal_uart.h
  • UART_DIV_LPUART : stm32f7xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f7xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f7xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32f7xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32f7xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32f7xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32f7xx_hal_uart.h
  • UART_FLAG_ABRE : stm32f7xx_hal_uart.h
  • UART_FLAG_ABRF : stm32f7xx_hal_uart.h
  • UART_FLAG_BUSY : stm32f7xx_hal_uart.h
  • UART_FLAG_CMF : stm32f7xx_hal_uart.h
  • UART_FLAG_CTS : stm32f7xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32f7xx_hal_uart.h
  • UART_FLAG_EOBF : stm32f7xx_hal_uart.h
  • UART_FLAG_FE : stm32f7xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f7xx_hal_uart.h
  • UART_FLAG_LBDF : stm32f7xx_hal_uart.h
  • UART_FLAG_NE : stm32f7xx_hal_uart.h
  • UART_FLAG_ORE : stm32f7xx_hal_uart.h
  • UART_FLAG_PE : stm32f7xx_hal_uart.h
  • UART_FLAG_RTOF : stm32f7xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f7xx_hal_uart.h
  • UART_FLAG_SBKF : stm32f7xx_hal_uart.h
  • UART_FLAG_TC : stm32f7xx_hal_uart.h
  • UART_FLAG_TEACK : stm32f7xx_hal_uart.h
  • UART_FLAG_TXE : stm32f7xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32f7xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32f7xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f7xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f7xx_hal_uart.h
  • UART_IT_CM : stm32f7xx_hal_uart.h
  • UART_IT_CTS : stm32f7xx_hal_uart.h
  • UART_IT_ERR : stm32f7xx_hal_uart.h
  • UART_IT_FE : stm32f7xx_hal_uart.h
  • UART_IT_IDLE : stm32f7xx_hal_uart.h
  • UART_IT_LBD : stm32f7xx_hal_uart.h
  • UART_IT_MASK : stm32f7xx_hal_uart.h
  • UART_IT_NE : stm32f7xx_hal_uart.h
  • UART_IT_ORE : stm32f7xx_hal_uart.h
  • UART_IT_PE : stm32f7xx_hal_uart.h
  • UART_IT_RXNE : stm32f7xx_hal_uart.h
  • UART_IT_TC : stm32f7xx_hal_uart.h
  • UART_IT_TXE : stm32f7xx_hal_uart.h
  • UART_LIN_DISABLE : stm32f7xx_hal_uart.h
  • UART_LIN_ENABLE : stm32f7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f7xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f7xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32f7xx_hal_uart_ex.h
  • UART_MODE_RX : stm32f7xx_hal_uart.h
  • UART_MODE_TX : stm32f7xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f7xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32f7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32f7xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32f7xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f7xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32f7xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f7xx_hal_uart.h
  • UART_PARITY_NONE : stm32f7xx_hal_uart.h
  • UART_PARITY_ODD : stm32f7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32f7xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32f7xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32f7xx_hal_uart.h
  • UART_STATE_DISABLE : stm32f7xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f7xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f7xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f7xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f7xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f7xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32f7xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32f7xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32f7xx_hal_uart_ex.h
  • USART_CLEAR_CTSF : stm32f7xx_hal_usart.h
  • USART_CLEAR_FEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_NEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_OREF : stm32f7xx_hal_usart.h
  • USART_CLEAR_PEF : stm32f7xx_hal_usart.h
  • USART_CLEAR_TCF : stm32f7xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f7xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f7xx_hal_usart.h
  • USART_CR1_FIELDS : stm32f7xx_hal_smartcard.c , stm32f7xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32f7xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32f7xx_hal_smartcard.c , stm32f7xx_hal_usart.c
  • USART_CR3_FIELDS : stm32f7xx_hal_smartcard.c
  • USART_FLAG_BUSY : stm32f7xx_hal_usart.h
  • USART_FLAG_CTS : stm32f7xx_hal_usart.h
  • USART_FLAG_CTSIF : stm32f7xx_hal_usart.h
  • USART_FLAG_FE : stm32f7xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f7xx_hal_usart.h
  • USART_FLAG_LBDF : stm32f7xx_hal_usart.h
  • USART_FLAG_NE : stm32f7xx_hal_usart.h
  • USART_FLAG_ORE : stm32f7xx_hal_usart.h
  • USART_FLAG_PE : stm32f7xx_hal_usart.h
  • USART_FLAG_REACK : stm32f7xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f7xx_hal_usart.h
  • USART_FLAG_TC : stm32f7xx_hal_usart.h
  • USART_FLAG_TEACK : stm32f7xx_hal_usart.h
  • USART_FLAG_TXE : stm32f7xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32f7xx_hal_usart.h
  • USART_IT_ERR : stm32f7xx_hal_usart.h
  • USART_IT_FE : stm32f7xx_hal_usart.h
  • USART_IT_IDLE : stm32f7xx_hal_usart.h
  • USART_IT_MASK : stm32f7xx_hal_usart.h
  • USART_IT_NE : stm32f7xx_hal_usart.h
  • USART_IT_ORE : stm32f7xx_hal_usart.h
  • USART_IT_PE : stm32f7xx_hal_usart.h
  • USART_IT_RXNE : stm32f7xx_hal_usart.h
  • USART_IT_TC : stm32f7xx_hal_usart.h
  • USART_IT_TXE : stm32f7xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f7xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f7xx_hal_usart.h
  • USART_MODE_RX : stm32f7xx_hal_usart.h
  • USART_MODE_TX : stm32f7xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f7xx_hal_usart.h
  • USART_OVERSAMPLING_16 : stm32f7xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32f7xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f7xx_hal_usart.h
  • USART_PARITY_NONE : stm32f7xx_hal_usart.h
  • USART_PARITY_ODD : stm32f7xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f7xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f7xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f7xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f7xx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32f7xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f7xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f7xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f7xx_hal_usart.h
  • USART_TIMEOUT_VALUE : stm32f7xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32f7xx_hal_usart.h
  • USART_TXDMA_TIMEOUTVALUE : stm32f7xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32f7xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32f7xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32f7xx_hal_usart_ex.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32f7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_LINE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE : stm32f7xx_hal_pcd.h
  • USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32f7xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32f7xx_hal_pcd.h
  • USBD_HS_TRDT_VALUE : stm32f7xx_hal_pcd.h
  • USE_RTOS : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32f7xx_hal_conf.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Globals

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- w -

  • WWDG_FLAG_EWIF : stm32f7xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f7xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f7xx_hal_wwdg.h
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal.h File Reference

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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32f7xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000.
#define | __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()
FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000.

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, and instruction cache through ART accelerator.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_EnableFMCMemorySwapping (void)
Enables the FMC Memory Mapping Swapping.
void | HAL_DisableFMCMemorySwapping (void)
Disables the FMC Memory Mapping Swapping.

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc.h File Reference

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stm32f7xx_hal_adc.h File Reference

Header file of ADC HAL extension module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration multi-mode structure definition. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)
#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define | ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define | ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
#define | ADC_RESOLUTION_12B ((uint32_t)0x00000000)
#define | ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define | ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
#define | ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define | ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
#define | ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
#define | ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define | ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
#define | ADC_CHANNEL_0 ((uint32_t)0x00000000)
#define | ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define | ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
#define | ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
#define | ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define | ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define | ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
#define | ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define | ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
#define | ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
#define | ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
#define | ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002)
#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
#define | ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define | ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define | ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define | ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
#define | ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
#define | ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
#define | ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
#define | ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
#define | ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
#define | ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
#define | ADC_ALL_CHANNELS ((uint32_t)0x00000001)
#define | ADC_REGULAR_CHANNELS ((uint32_t)0x00000002)
#define | ADC_INJECTED_CHANNELS ((uint32_t)0x00000003)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Check if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clear the ADC's pending flags.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | ADC_STAB_DELAY_US ((uint32_t) 3)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_ADC_EXT_TRIG_EDGE(__EDGE__)
#define | IS_ADC_EXT_TRIG(__REGTRIG__)
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
#define | IS_ADC_SAMPLE_TIME(__TIME__)
#define | IS_ADC_EOCSelection(__EOCSelection__)
#define | IS_ADC_EVENT_TYPE(__EVENT__)
#define | IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__)
#define | IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE)
#define | IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
#define | IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
#define | IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
#define | IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)
#define | ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
Set ADC Regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
Enable ADC scan mode.
#define | ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
Enable the ADC end of conversion selection.
#define | ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
Enable the ADC DMA continuous request.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
Return resolution bits in CR1 register.

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitializes the ADCx peripheral registers to their default reset values.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for regular conversion complete.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Disables the interrupt and stop ADC conversion of regular channels.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Gets the converted value from data register of regular channel.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion half DMA transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
Error ADC callback.
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

Header file of ADC HAL extension module.

Header file of ADC HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_adc.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_adc_ex.h File Reference
#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_MultiModeTypeDef
ADC Configuration multi-mode structure definition. More...

Defines

#define | ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
#define | ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000)
#define | ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0)
#define | ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1)
#define | ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)
#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
#define | ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_MODE(__MODE__)
#define | IS_ADC_DMA_ACCESS_MODE(__MODE__)
#define | IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__)
#define | IS_ADC_EXT_INJEC_TRIG(__INJTRIG__)
#define | IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
#define | IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
#define | ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
Set the selected injected Channel rank.

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables the selected ADC software start conversion of the injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for injected conversion complete.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Gets the converted value from data register of injected channel.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Configures the ADC multi-mode.
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_can.h File Reference

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stm32f7xx_hal_can.h File Reference

Header file of CAN HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Defines

#define | HAL_CAN_ERROR_NONE 0x00
#define | HAL_CAN_ERROR_EWG 0x01
#define | HAL_CAN_ERROR_EPV 0x02
#define | HAL_CAN_ERROR_BOF 0x04
#define | HAL_CAN_ERROR_STF 0x08
#define | HAL_CAN_ERROR_FOR 0x10
#define | HAL_CAN_ERROR_ACK 0x20
#define | HAL_CAN_ERROR_BR 0x40
#define | HAL_CAN_ERROR_BD 0x80
#define | HAL_CAN_ERROR_CRC 0x100
#define | CAN_INITSTATUS_FAILED ((uint8_t)0x00)
#define | CAN_INITSTATUS_SUCCESS ((uint8_t)0x01)
#define | CAN_MODE_NORMAL ((uint32_t)0x00000000)
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))
#define | CAN_SJW_1TQ ((uint32_t)0x00000000)
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)
#define | CAN_BS1_1TQ ((uint32_t)0x00000000)
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)
#define | CAN_BS2_1TQ ((uint32_t)0x00000000)
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)
#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01)
#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01)
#define | CAN_FILTER_FIFO0 ((uint8_t)0x00)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01)
#define | CAN_ID_STD ((uint32_t)0x00000000)
#define | CAN_ID_EXT ((uint32_t)0x00000004)
#define | CAN_RTR_DATA ((uint32_t)0x00000000)
#define | CAN_RTR_REMOTE ((uint32_t)0x00000002)
#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)
#define | CAN_FLAG_RQCP0 ((uint32_t)0x00000500)
#define | CAN_FLAG_RQCP1 ((uint32_t)0x00000508)
#define | CAN_FLAG_RQCP2 ((uint32_t)0x00000510)
#define | CAN_FLAG_TXOK0 ((uint32_t)0x00000501)
#define | CAN_FLAG_TXOK1 ((uint32_t)0x00000509)
#define | CAN_FLAG_TXOK2 ((uint32_t)0x00000511)
#define | CAN_FLAG_TME0 ((uint32_t)0x0000051A)
#define | CAN_FLAG_TME1 ((uint32_t)0x0000051B)
#define | CAN_FLAG_TME2 ((uint32_t)0x0000051C)
#define | CAN_FLAG_FF0 ((uint32_t)0x00000203)
#define | CAN_FLAG_FOV0 ((uint32_t)0x00000204)
#define | CAN_FLAG_FF1 ((uint32_t)0x00000403)
#define | CAN_FLAG_FOV1 ((uint32_t)0x00000404)
#define | CAN_FLAG_WKU ((uint32_t)0x00000103)
#define | CAN_FLAG_SLAK ((uint32_t)0x00000101)
#define | CAN_FLAG_SLAKI ((uint32_t)0x00000104)
#define | CAN_FLAG_EWG ((uint32_t)0x00000300)
#define | CAN_FLAG_EPV ((uint32_t)0x00000301)
#define | CAN_FLAG_BOF ((uint32_t)0x00000302)
#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)
#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupts.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupts.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified CAN interrupt source is enabled or disabled.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disable the DBG Freeze for CAN.
#define | CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)
#define | CAN_FLAG_MASK ((uint32_t)0x000000FF)
#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define | IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00, HAL_CAN_STATE_READY = 0x01, HAL_CAN_STATE_BUSY = 0x02, HAL_CAN_STATE_BUSY_TX = 0x12,
HAL_CAN_STATE_BUSY_RX = 0x22, HAL_CAN_STATE_BUSY_TX_RX = 0x32, HAL_CAN_STATE_TIMEOUT = 0x03, HAL_CAN_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state

Detailed Description

Header file of CAN HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_can.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cec.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | CEC_HandleTypeDef
CEC handle Structure definition. More...

Defines

#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
#define | CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
#define | CEC_INITIATOR_LSB_POS ((uint32_t) 4)
#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE
#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR
#define | CEC_ISR_ALL_ERROR
#define | CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
#define | CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
Reset CEC handle state.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
Check CEC initiator or destination logical address setting.
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
Check CEC message size.

Enumerations

enum HAL_CEC_StateTypeDef {
HAL_CEC_STATE_RESET = 0x00, HAL_CEC_STATE_READY = 0x01, HAL_CEC_STATE_BUSY = 0x02, HAL_CEC_STATE_BUSY_TX = 0x03,
HAL_CEC_STATE_BUSY_RX = 0x04, HAL_CEC_STATE_STANDBY_RX = 0x05, HAL_CEC_STATE_TIMEOUT = 0x06, HAL_CEC_STATE_ERROR = 0x07
}
HAL CEC State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_Transmit (CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Send data in blocking mode.
HAL_StatusTypeDef | HAL_CEC_Receive (CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
Receive data in blocking mode.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
HAL_StatusTypeDef | HAL_CEC_Receive_IT (CEC_HandleTypeDef *hcec, uint8_t *pData)
Receive data in interrupt mode.
uint32_t | HAL_CEC_GetReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cec.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cortex.h File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
__STATIC_INLINE void | HAL_MPU_Disable (void)
Disables the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cortex.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc.h File Reference

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stm32f7xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
struct | CRC_HandleTypeDef

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFF
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
#define | CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
#define | HAL_CRC_LENGTH_32B 32
#define | HAL_CRC_LENGTH_16B 16
#define | HAL_CRC_LENGTH_8B 8
#define | HAL_CRC_LENGTH_7B 7
#define | CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define | CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
Stores a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 8-bit data stored in the Independent Data(ID) register.
#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
#define | IS_DEFAULT_POLYNOMIAL(__DEFAULT__)
#define | IS_DEFAULT_INIT_VALUE(__VALUE__)
#define | IS_CRC_POL_LENGTH(__LENGTH__)
#define | IS_CRC_INPUTDATA_FORMAT(__FORMAT__)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00, HAL_CRC_STATE_READY = 0x01, HAL_CRC_STATE_BUSY = 0x02, HAL_CRC_STATE_TIMEOUT = 0x03,
HAL_CRC_STATE_ERROR = 0x04
}

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_crc.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc_ex.h File Reference

  • File List
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  • Drivers
  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_crc_ex.h File Reference

Header file of CRC HAL extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define | IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)
#define | CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initializes the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_crc_ex.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac.h File Reference

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stm32f7xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04
#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))
#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
#define | DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010)
#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008)
#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))
Disable the DAC channel.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified DAC interrupt source is enabled or disabled.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
Set DHR12RD alignment.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00, HAL_DAC_STATE_READY = 0x01, HAL_DAC_STATE_BUSY = 0x02, HAL_DAC_STATE_TIMEOUT = 0x03,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitializes the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initializes the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitializes the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC state
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

Header file of DAC HAL module.

Header file of DAC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dac.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac_ex.h File Reference

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stm32f7xx_hal_dac_ex.h File Reference
#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi.h File Reference

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stm32f7xx_hal_dcmi.h File Reference

Header file of DCMI HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_dcmi_ex.h"

Go to the source code of this file.

Data Structures

struct | DCMI_HandleTypeDef
DCMI handle Structure definition. More...

Defines

#define | HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001)
#define | HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002)
#define | HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000)
#define | DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM)
#define | DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000)
#define | DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS)
#define | DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000)
#define | DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL)
#define | DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000)
#define | DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL)
#define | DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000)
#define | DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL)
#define | DCMI_JPEG_DISABLE ((uint32_t)0x00000000)
#define | DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG)
#define | DCMI_CR_ALL_FRAME ((uint32_t)0x00000000)
#define | DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0)
#define | DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1)
#define | DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000)
#define | DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0)
#define | DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1)
#define | DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))
#define | DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF)
#define | DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF)
#define | DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define | DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
#define | DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define | DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define | DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
#define | DCMI_FLAG_HSYNC ((uint32_t)0x2001)
DCMI SR register.
#define | DCMI_FLAG_VSYNC ((uint32_t)0x2002)
#define | DCMI_FLAG_FNE ((uint32_t)0x2004)
#define | DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)
DCMI RISR register.
#define | DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)
#define | DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)
#define | DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)
#define | DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)
#define | DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)
DCMI MISR register.
#define | DCMI_FLAG_OVFMI ((uint32_t)0x1002)
#define | DCMI_FLAG_ERRMI ((uint32_t)0x1004)
#define | DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
#define | DCMI_FLAG_LINEMI ((uint32_t)0x1010)
#define | __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
Reset DCMI handle state.
#define | __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
Enable the DCMI.
#define | __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
Disable the DCMI.
#define | __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)
Get the DCMI pending flags.
#define | __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the DCMI pending flags.
#define | __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified DCMI interrupts.
#define | __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
Disable the specified DCMI interrupts.
#define | __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
Check whether the specified DCMI interrupt has occurred or not.
#define | IS_DCMI_CAPTURE_MODE(MODE)
#define | IS_DCMI_SYNCHRO(MODE)
#define | IS_DCMI_PCKPOLARITY(POLARITY)
#define | IS_DCMI_VSPOLARITY(POLARITY)
#define | IS_DCMI_HSPOLARITY(POLARITY)
#define | IS_DCMI_MODE_JPEG(JPEG_MODE)
#define | IS_DCMI_CAPTURE_RATE(RATE)
#define | IS_DCMI_EXTENDED_DATA(DATA)
#define | IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define | IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)

Enumerations

enum HAL_DCMI_StateTypeDef {
HAL_DCMI_STATE_RESET = 0x00, HAL_DCMI_STATE_READY = 0x01, HAL_DCMI_STATE_BUSY = 0x02, HAL_DCMI_STATE_TIMEOUT = 0x03,
HAL_DCMI_STATE_ERROR = 0x04
}
HAL DCMI State structures definition. More...

Functions

__weak HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.
HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
HAL_StatusTypeDef | HAL_DCMI_ConfigCROP (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_EnableCROP (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_DisableCROP (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

Header file of DCMI HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dcmi.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi_ex.h File Reference

  • File List
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Data Structures | Defines
stm32f7xx_hal_dcmi_ex.h File Reference

Header file of DCMI Extension HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DCMI_CodesInitTypeDef
DCMIEx Embedded Synchronisation CODE Init structure definition. More...
struct | DCMI_InitTypeDef
DCMI Init structure definition. More...

Defines

#define | DCMI_BSM_ALL ((uint32_t)0x00000000)
#define | DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0)
#define | DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1)
#define | DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1))
#define | DCMI_OEBS_ODD ((uint32_t)0x00000000)
#define | DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS)
#define | DCMI_LSM_ALL ((uint32_t)0x00000000)
#define | DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM)
#define | DCMI_OELS_ODD ((uint32_t)0x00000000)
#define | DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS)
#define | IS_DCMI_BYTE_SELECT_MODE(MODE)
#define | IS_DCMI_BYTE_SELECT_START(POLARITY)
#define | IS_DCMI_LINE_SELECT_MODE(MODE)
#define | IS_DCMI_LINE_SELECT_START(POLARITY)

Detailed Description

Header file of DCMI Extension HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dcmi_ex.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f7xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001)
#define | HAL_DMA_ERROR_FE ((uint32_t)0x00000002)
#define | HAL_DMA_ERROR_DME ((uint32_t)0x00000004)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | DMA_CHANNEL_0 ((uint32_t)0x00000000)
#define | DMA_CHANNEL_1 ((uint32_t)0x02000000)
#define | DMA_CHANNEL_2 ((uint32_t)0x04000000)
#define | DMA_CHANNEL_3 ((uint32_t)0x06000000)
#define | DMA_CHANNEL_4 ((uint32_t)0x08000000)
#define | DMA_CHANNEL_5 ((uint32_t)0x0A000000)
#define | DMA_CHANNEL_6 ((uint32_t)0x0C000000)
#define | DMA_CHANNEL_7 ((uint32_t)0x0E000000)
#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000)
#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000)
#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
#define | DMA_NORMAL ((uint32_t)0x00000000)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080)
#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or not.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Returns the number of remaining data units in the current DMAy Streamx transfer.
#define | IS_DMA_CHANNEL(CHANNEL)
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00, HAL_DMA_STATE_READY = 0x01, HAL_DMA_STATE_READY_MEM0 = 0x11, HAL_DMA_STATE_READY_MEM1 = 0x21,
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, HAL_DMA_STATE_BUSY = 0x02, HAL_DMA_STATE_BUSY_MEM0 = 0x12,
HAL_DMA_STATE_BUSY_MEM1 = 0x22, HAL_DMA_STATE_TIMEOUT = 0x03, HAL_DMA_STATE_ERROR = 0x04
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00, HAL_DMA_HALF_TRANSFER = 0x01 }
HAL DMA Error Code structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dma.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma2d.h File Reference

  • File List
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  • Drivers
  • STM32F7xx_HAL_Driver
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stm32f7xx_hal_dma2d.h File Reference

Header file of DMA2D HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DMA2D_ColorTypeDef
DMA2D color Structure definition. More...
struct | DMA2D_CLUTCfgTypeDef
DMA2D CLUT Structure definition. More...
struct | DMA2D_InitTypeDef
DMA2D Init structure definition. More...
struct | DMA2D_LayerCfgTypeDef
DMA2D Layer structure definition. More...
struct | __DMA2D_HandleTypeDef
DMA2D handle Structure definition. More...

Defines

#define | MAX_DMA2D_LAYER 2
#define | HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001)
#define | HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002)
#define | HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | DMA2D_M2M ((uint32_t)0x00000000)
#define | DMA2D_M2M_PFC ((uint32_t)0x00010000)
#define | DMA2D_M2M_BLEND ((uint32_t)0x00020000)
#define | DMA2D_R2M ((uint32_t)0x00030000)
#define | DMA2D_ARGB8888 ((uint32_t)0x00000000)
#define | DMA2D_RGB888 ((uint32_t)0x00000001)
#define | DMA2D_RGB565 ((uint32_t)0x00000002)
#define | DMA2D_ARGB1555 ((uint32_t)0x00000003)
#define | DMA2D_ARGB4444 ((uint32_t)0x00000004)
#define | COLOR_VALUE ((uint32_t)0x000000FF)
#define | DMA2D_PIXEL (DMA2D_NLR_PL >> 16)
#define | DMA2D_LINE DMA2D_NLR_NL
#define | DMA2D_OFFSET DMA2D_FGOR_LO
#define | CM_ARGB8888 ((uint32_t)0x00000000)
#define | CM_RGB888 ((uint32_t)0x00000001)
#define | CM_RGB565 ((uint32_t)0x00000002)
#define | CM_ARGB1555 ((uint32_t)0x00000003)
#define | CM_ARGB4444 ((uint32_t)0x00000004)
#define | CM_L8 ((uint32_t)0x00000005)
#define | CM_AL44 ((uint32_t)0x00000006)
#define | CM_AL88 ((uint32_t)0x00000007)
#define | CM_L4 ((uint32_t)0x00000008)
#define | CM_A8 ((uint32_t)0x00000009)
#define | CM_A4 ((uint32_t)0x0000000A)
#define | DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000)
#define | DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001)
#define | DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002)
#define | DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000)
#define | DMA2D_CCM_RGB888 ((uint32_t)0x00000001)
#define | DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8)
#define | LINE_WATERMARK DMA2D_LWR_LW
#define | DMA2D_IT_CE DMA2D_CR_CEIE
#define | DMA2D_IT_CTC DMA2D_CR_CTCIE
#define | DMA2D_IT_CAE DMA2D_CR_CAEIE
#define | DMA2D_IT_TW DMA2D_CR_TWIE
#define | DMA2D_IT_TC DMA2D_CR_TCIE
#define | DMA2D_IT_TE DMA2D_CR_TEIE
#define | DMA2D_FLAG_CE DMA2D_ISR_CEIF
#define | DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
#define | DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
#define | DMA2D_FLAG_TW DMA2D_ISR_TWIF
#define | DMA2D_FLAG_TC DMA2D_ISR_TCIF
#define | DMA2D_FLAG_TE DMA2D_ISR_TEIF
#define | __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
Reset DMA2D handle state.
#define | __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
Enable the DMA2D.
#define | __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
Disable the DMA2D.
#define | __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Get the DMA2D pending flags.
#define | __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
Clears the DMA2D pending flags.
#define | __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enables the specified DMA2D interrupts.
#define | __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disables the specified DMA2D interrupts.
#define | __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Checks whether the specified DMA2D interrupt has occurred or not.
#define | IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define | IS_DMA2D_MODE(MODE)
#define | IS_DMA2D_CMODE(MODE_ARGB)
#define | IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
#define | IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define | IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define | IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define | IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)
#define | IS_DMA2D_ALPHA_MODE(AlphaMode)
#define | IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define | IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define | IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
#define | IS_DMA2D_IT(IT)
#define | IS_DMA2D_GET_FLAG(FLAG)

Typedefs

typedef struct
__DMA2D_HandleTypeDef 		DMA2D_HandleTypeDef
DMA2D handle Structure definition.

Enumerations

enum HAL_DMA2D_StateTypeDef {
HAL_DMA2D_STATE_RESET = 0x00, HAL_DMA2D_STATE_READY = 0x01, HAL_DMA2D_STATE_BUSY = 0x02, HAL_DMA2D_STATE_TIMEOUT = 0x03,
HAL_DMA2D_STATE_ERROR = 0x04, HAL_DMA2D_STATE_SUSPEND = 0x05
}
HAL DMA2D State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handles DMA2D interrupt request.
HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_DisableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Disable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Define the configuration of the line watermark .
HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

Header file of DMA2D HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dma2d.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
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stm32f7xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00, MEMORY1 = 0x01 }
HAL DMA Memory definition. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dma_ex.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_eth.h File Reference

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stm32f7xx_hal_eth.h File Reference

Header file of ETH HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ETH_InitTypeDef
ETH Init Structure definition. More...
struct | ETH_MACInitTypeDef
ETH MAC Configuration Structure definition. More...
struct | ETH_DMAInitTypeDef
ETH DMA Configuration Structure definition. More...
struct | ETH_DMADescTypeDef
ETH DMA Descriptors data structure definition. More...
struct | ETH_DMARxFrameInfos
Received Frame Informations structure definition. More...
struct | ETH_HandleTypeDef
ETH Handle Structure definition. More...

Defines

#define | IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
#define | IS_ETH_AUTONEGOTIATION(CMD)
#define | IS_ETH_SPEED(SPEED)
#define | IS_ETH_DUPLEX_MODE(MODE)
#define | IS_ETH_RX_MODE(MODE)
#define | IS_ETH_CHECKSUM_MODE(MODE)
#define | IS_ETH_MEDIA_INTERFACE(MODE)
#define | IS_ETH_WATCHDOG(CMD)
#define | IS_ETH_JABBER(CMD)
#define | IS_ETH_INTER_FRAME_GAP(GAP)
#define | IS_ETH_CARRIER_SENSE(CMD)
#define | IS_ETH_RECEIVE_OWN(CMD)
#define | IS_ETH_LOOPBACK_MODE(CMD)
#define | IS_ETH_CHECKSUM_OFFLOAD(CMD)
#define | IS_ETH_RETRY_TRANSMISSION(CMD)
#define | IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD)
#define | IS_ETH_BACKOFF_LIMIT(LIMIT)
#define | IS_ETH_DEFERRAL_CHECK(CMD)
#define | IS_ETH_RECEIVE_ALL(CMD)
#define | IS_ETH_SOURCE_ADDR_FILTER(CMD)
#define | IS_ETH_CONTROL_FRAMES(PASS)
#define | IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD)
#define | IS_ETH_DESTINATION_ADDR_FILTER(FILTER)
#define | IS_ETH_PROMISCUOUS_MODE(CMD)
#define | IS_ETH_MULTICAST_FRAMES_FILTER(FILTER)
#define | IS_ETH_UNICAST_FRAMES_FILTER(FILTER)
#define | IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
#define | IS_ETH_ZEROQUANTA_PAUSE(CMD)
#define | IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD)
#define | IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD)
#define | IS_ETH_RECEIVE_FLOWCONTROL(CMD)
#define | IS_ETH_TRANSMIT_FLOWCONTROL(CMD)
#define | IS_ETH_VLAN_TAG_COMPARISON(COMPARISON)
#define | IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
#define | IS_ETH_MAC_ADDRESS0123(ADDRESS)
#define | IS_ETH_MAC_ADDRESS123(ADDRESS)
#define | IS_ETH_MAC_ADDRESS_FILTER(FILTER)
#define | IS_ETH_MAC_ADDRESS_MASK(MASK)
#define | IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD)
#define | IS_ETH_RECEIVE_STORE_FORWARD(CMD)
#define | IS_ETH_FLUSH_RECEIVE_FRAME(CMD)
#define | IS_ETH_TRANSMIT_STORE_FORWARD(CMD)
#define | IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD)
#define | IS_ETH_FORWARD_ERROR_FRAMES(CMD)
#define | IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD)
#define | IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD)
#define | IS_ETH_SECOND_FRAME_OPERATE(CMD)
#define | IS_ETH_ADDRESS_ALIGNED_BEATS(CMD)
#define | IS_ETH_FIXED_BURST(CMD)
#define | IS_ETH_RXDMA_BURST_LENGTH(LENGTH)
#define | IS_ETH_TXDMA_BURST_LENGTH(LENGTH)
#define | IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
#define | IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO)
#define | IS_ETH_DMATXDESC_GET_FLAG(FLAG)
#define | IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT)
#define | IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM)
#define | IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
#define | IS_ETH_DMARXDESC_GET_FLAG(FLAG)
#define | IS_ETH_DMA_RXDESC_BUFFER(BUFFER)
#define | IS_ETH_PMT_GET_FLAG(FLAG)
#define | IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
#define | IS_ETH_DMA_GET_FLAG(FLAG)
#define | IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
#define | IS_ETH_MAC_GET_IT(IT)
#define | IS_ETH_MAC_GET_FLAG(FLAG)
#define | IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
#define | IS_ETH_DMA_GET_IT(IT)
#define | IS_ETH_DMA_GET_OVERFLOW(OVERFLOW)
#define | IS_ETH_MMC_IT(IT)
#define | IS_ETH_MMC_GET_IT(IT)
#define | IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD)
#define | ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
#define | ETH_SUCCESS ((uint32_t)0)
#define | ETH_ERROR ((uint32_t)1)
#define | ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
#define | ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
#define | ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
#define | ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
#define | ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
#define | ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
#define | ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
#define | ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
#define | ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
#define | ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
#define | ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
#define | ETH_WAKEUP_REGISTER_LENGTH 8
#define | ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
#define | ETH_MAX_PACKET_SIZE ((uint32_t)1524)
#define | ETH_HEADER ((uint32_t)14)
#define | ETH_CRC ((uint32_t)4)
#define | ETH_EXTRA ((uint32_t)2)
#define | ETH_VLAN_TAG ((uint32_t)4)
#define | ETH_MIN_ETH_PAYLOAD ((uint32_t)46)
#define | ETH_MAX_ETH_PAYLOAD ((uint32_t)1500)
#define | ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000)
#define | ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
#define | ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#define | ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
#define | ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#define | ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
Bit definition of TDES0 register: DMA Tx descriptor status register.
#define | ETH_DMATXDESC_IC ((uint32_t)0x40000000)
#define | ETH_DMATXDESC_LS ((uint32_t)0x20000000)
#define | ETH_DMATXDESC_FS ((uint32_t)0x10000000)
#define | ETH_DMATXDESC_DC ((uint32_t)0x08000000)
#define | ETH_DMATXDESC_DP ((uint32_t)0x04000000)
#define | ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)
#define | ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)
#define | ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
#define | ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)
#define | ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)
#define | ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)
#define | ETH_DMATXDESC_TER ((uint32_t)0x00200000)
#define | ETH_DMATXDESC_TCH ((uint32_t)0x00100000)
#define | ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
#define | ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
#define | ETH_DMATXDESC_ES ((uint32_t)0x00008000)
#define | ETH_DMATXDESC_JT ((uint32_t)0x00004000)
#define | ETH_DMATXDESC_FF ((uint32_t)0x00002000)
#define | ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
#define | ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
#define | ETH_DMATXDESC_NC ((uint32_t)0x00000400)
#define | ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
#define | ETH_DMATXDESC_EC ((uint32_t)0x00000100)
#define | ETH_DMATXDESC_VF ((uint32_t)0x00000080)
#define | ETH_DMATXDESC_CC ((uint32_t)0x00000078)
#define | ETH_DMATXDESC_ED ((uint32_t)0x00000004)
#define | ETH_DMATXDESC_UF ((uint32_t)0x00000002)
#define | ETH_DMATXDESC_DB ((uint32_t)0x00000001)
#define | ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000)
Bit definition of TDES1 register.
#define | ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF)
#define | ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES2 register.
#define | ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)
Bit definition of TDES3 register.
#define | ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
#define | ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
#define | ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
Bit definition of RDES0 register: DMA Rx descriptor status register.
#define | ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
#define | ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
#define | ETH_DMARXDESC_ES ((uint32_t)0x00008000)
#define | ETH_DMARXDESC_DE ((uint32_t)0x00004000)
#define | ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
#define | ETH_DMARXDESC_LE ((uint32_t)0x00001000)
#define | ETH_DMARXDESC_OE ((uint32_t)0x00000800)
#define | ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
#define | ETH_DMARXDESC_FS ((uint32_t)0x00000200)
#define | ETH_DMARXDESC_LS ((uint32_t)0x00000100)
#define | ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
#define | ETH_DMARXDESC_LC ((uint32_t)0x00000040)
#define | ETH_DMARXDESC_FT ((uint32_t)0x00000020)
#define | ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
#define | ETH_DMARXDESC_RE ((uint32_t)0x00000008)
#define | ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
#define | ETH_DMARXDESC_CE ((uint32_t)0x00000002)
#define | ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
#define | ETH_DMARXDESC_DIC ((uint32_t)0x80000000)
Bit definition of RDES1 register.
#define | ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000)
#define | ETH_DMARXDESC_RER ((uint32_t)0x00008000)
#define | ETH_DMARXDESC_RCH ((uint32_t)0x00004000)
#define | ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF)
#define | ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)
Bit definition of RDES2 register.
#define | ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)
Bit definition of RDES3 register.
#define | ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
#define | ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
#define | ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
#define | ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
#define | ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
#define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
#define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
#define | ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
#define | ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
#define | ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
#define | ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
#define | ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
#define | ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
#define | ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
#define | ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
#define | ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
#define | ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
#define | ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
#define | ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
#define | ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
#define | ETH_SPEED_10M ((uint32_t)0x00000000)
#define | ETH_SPEED_100M ((uint32_t)0x00004000)
#define | ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
#define | ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
#define | ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
#define | ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
#define | ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
#define | ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
#define | ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
#define | ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
#define | ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
#define | ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
#define | ETH_JABBER_ENABLE ((uint32_t)0x00000000)
#define | ETH_JABBER_DISABLE ((uint32_t)0x00400000)
#define | ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000)
#define | ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000)
#define | ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000)
#define | ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000)
#define | ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000)
#define | ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000)
#define | ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000)
#define | ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000)
#define | ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
#define | ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
#define | ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
#define | ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
#define | ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
#define | ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
#define | ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
#define | ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
#define | ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
#define | ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
#define | ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
#define | ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
#define | ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
#define | ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
#define | ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
#define | ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
#define | ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
#define | ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
#define | ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
#define | ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
#define | ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
#define | ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
#define | ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
#define | ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040)
#define | ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080)
#define | ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)
#define | ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
#define | ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
#define | ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
#define | ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
#define | ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
#define | ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
#define | ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
#define | ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
#define | ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
#define | ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
#define | ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
#define | ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
#define | ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
#define | ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
#define | ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
#define | ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000)
#define | ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010)
#define | ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020)
#define | ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030)
#define | ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
#define | ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
#define | ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
#define | ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
#define | ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
#define | ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
#define | ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
#define | ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
#define | ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
#define | ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
#define | ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
#define | ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
#define | ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
#define | ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
#define | ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000)
#define | ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000)
#define | ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000)
#define | ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000)
#define | ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000)
#define | ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000)
#define | ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define | ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define | ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define | ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define | ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define | ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define | ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define | ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define | ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define | ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define | ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define | ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define | ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#define | ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define | ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define | ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define | ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define | ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define | ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define | ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define | ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define | ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define | ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
#define | ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
#define | ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
#define | ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
#define | ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
#define | ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
#define | ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
#define | ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
#define | ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000)
#define | ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000)
#define | ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
#define | ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
#define | ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
#define | ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010)
#define | ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018)
#define | ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
#define | ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
#define | ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
#define | ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
#define | ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
#define | ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
#define | ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000)
#define | ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000)
#define | ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000)
#define | ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000)
#define | ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000)
#define | ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000)
#define | ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000)
#define | ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100)
#define | ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200)
#define | ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400)
#define | ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800)
#define | ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000)
#define | ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000)
#define | ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100)
#define | ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200)
#define | ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400)
#define | ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800)
#define | ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000)
#define | ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000)
#define | ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
#define | ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
#define | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
#define | ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
#define | ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000)
#define | ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000)
#define | ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000)
#define | ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000)
#define | ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000)
#define | ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000)
#define | ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000)
#define | ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001)
#define | ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000)
#define | ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040)
#define | ETH_PMT_FLAG_MPR ((uint32_t)0x00000020)
#define | ETH_MMC_IT_TGF ((uint32_t)0x00200000)
#define | ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000)
#define | ETH_MMC_IT_TGFSC ((uint32_t)0x00004000)
#define | ETH_MMC_IT_RGUF ((uint32_t)0x10020000)
#define | ETH_MMC_IT_RFAE ((uint32_t)0x10000040)
#define | ETH_MMC_IT_RFCE ((uint32_t)0x10000020)
#define | ETH_MAC_FLAG_TST ((uint32_t)0x00000200)
#define | ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040)
#define | ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020)
#define | ETH_MAC_FLAG_MMC ((uint32_t)0x00000010)
#define | ETH_MAC_FLAG_PMT ((uint32_t)0x00000008)
#define | ETH_DMA_FLAG_TST ((uint32_t)0x20000000)
#define | ETH_DMA_FLAG_PMT ((uint32_t)0x10000000)
#define | ETH_DMA_FLAG_MMC ((uint32_t)0x08000000)
#define | ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)
#define | ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000)
#define | ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000)
#define | ETH_DMA_FLAG_NIS ((uint32_t)0x00010000)
#define | ETH_DMA_FLAG_AIS ((uint32_t)0x00008000)
#define | ETH_DMA_FLAG_ER ((uint32_t)0x00004000)
#define | ETH_DMA_FLAG_FBE ((uint32_t)0x00002000)
#define | ETH_DMA_FLAG_ET ((uint32_t)0x00000400)
#define | ETH_DMA_FLAG_RWT ((uint32_t)0x00000200)
#define | ETH_DMA_FLAG_RPS ((uint32_t)0x00000100)
#define | ETH_DMA_FLAG_RBU ((uint32_t)0x00000080)
#define | ETH_DMA_FLAG_R ((uint32_t)0x00000040)
#define | ETH_DMA_FLAG_TU ((uint32_t)0x00000020)
#define | ETH_DMA_FLAG_RO ((uint32_t)0x00000010)
#define | ETH_DMA_FLAG_TJT ((uint32_t)0x00000008)
#define | ETH_DMA_FLAG_TBU ((uint32_t)0x00000004)
#define | ETH_DMA_FLAG_TPS ((uint32_t)0x00000002)
#define | ETH_DMA_FLAG_T ((uint32_t)0x00000001)
#define | ETH_MAC_IT_TST ((uint32_t)0x00000200)
#define | ETH_MAC_IT_MMCT ((uint32_t)0x00000040)
#define | ETH_MAC_IT_MMCR ((uint32_t)0x00000020)
#define | ETH_MAC_IT_MMC ((uint32_t)0x00000010)
#define | ETH_MAC_IT_PMT ((uint32_t)0x00000008)
#define | ETH_DMA_IT_TST ((uint32_t)0x20000000)
#define | ETH_DMA_IT_PMT ((uint32_t)0x10000000)
#define | ETH_DMA_IT_MMC ((uint32_t)0x08000000)
#define | ETH_DMA_IT_NIS ((uint32_t)0x00010000)
#define | ETH_DMA_IT_AIS ((uint32_t)0x00008000)
#define | ETH_DMA_IT_ER ((uint32_t)0x00004000)
#define | ETH_DMA_IT_FBE ((uint32_t)0x00002000)
#define | ETH_DMA_IT_ET ((uint32_t)0x00000400)
#define | ETH_DMA_IT_RWT ((uint32_t)0x00000200)
#define | ETH_DMA_IT_RPS ((uint32_t)0x00000100)
#define | ETH_DMA_IT_RBU ((uint32_t)0x00000080)
#define | ETH_DMA_IT_R ((uint32_t)0x00000040)
#define | ETH_DMA_IT_TU ((uint32_t)0x00000020)
#define | ETH_DMA_IT_RO ((uint32_t)0x00000010)
#define | ETH_DMA_IT_TJT ((uint32_t)0x00000008)
#define | ETH_DMA_IT_TBU ((uint32_t)0x00000004)
#define | ETH_DMA_IT_TPS ((uint32_t)0x00000002)
#define | ETH_DMA_IT_T ((uint32_t)0x00000001)
#define | ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000)
#define | ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000)
#define | ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000)
#define | ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000)
#define | ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000)
#define | ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000)
#define | ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000)
#define | ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000)
#define | ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000)
#define | ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000)
#define | ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000)
#define | ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000)
#define | ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000)
#define | ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)
#define | ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000)
#define | __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Reset ETH handle state.
#define | __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
#define | __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
#define | __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Enables the specified DMA Rx Desc receive interrupt.
#define | __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
Disables the specified DMA Rx Desc receive interrupt.
#define | __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
Set the specified DMA Rx Desc Own bit.
#define | __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Returns the specified ETHERNET DMA Tx Desc collision count.
#define | __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
Set the specified DMA Tx Desc Own bit.
#define | __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
Enables the specified DMA Tx Desc Transmit interrupt.
#define | __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Disables the specified DMA Tx Desc Transmit interrupt.
#define | __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
#define | __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Enables the DMA Tx Desc CRC.
#define | __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
Disables the DMA Tx Desc CRC.
#define | __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
#define | __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
#define | __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
Enables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Disables the specified ETHERNET MAC interrupts.
#define | __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
Initiate a Pause Control Frame (Full-duplex only).
#define | __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Checks whether the ETHERNET flow control busy bit is set or not.
#define | __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
Enables the MAC Back Pressure operation activation (Half-duplex only).
#define | __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Disables the MAC BackPressure operation activation (Half-duplex only).
#define | __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET MAC flag is set or not.
#define | __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
Enables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Disables the specified ETHERNET DMA interrupts.
#define | __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Clears the ETHERNET DMA IT pending bit.
#define | __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET DMA flag is set or not.
#define | __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Checks whether the specified ETHERNET DMA flag is set or not.
#define | __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Checks whether the specified ETHERNET DMA overflow flag is set or not.
#define | __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Set the DMA Receive status watchdog timer register value.
#define | __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
Enables any unicast packet filtered by the MAC address recognition to be a wake-up frame.
#define | __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Disables any unicast packet filtered by the MAC address recognition to be a wake-up frame.
#define | __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
Enables the MAC Wake-Up Frame Detection.
#define | __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Disables the MAC Wake-Up Frame Detection.
#define | __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
Enables the MAC Magic Packet Detection.
#define | __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Disables the MAC Magic Packet Detection.
#define | __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
Enables the MAC Power Down.
#define | __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Disables the MAC Power Down.
#define | __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Checks whether the specified ETHERNET PMT flag is set or not.
#define | __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
#define | __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)
Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
#define | __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
Enables the MMC Counter Freeze.
#define | __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Disables the MMC Counter Freeze.
#define | __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
Enables the MMC Reset On Read.
#define | __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Disables the MMC Reset On Read.
#define | __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Enables the MMC Counter Stop Rollover.
#define | __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
Disables the MMC Counter Stop Rollover.
#define | __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
Resets the MMC Counters.
#define | __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Enables the specified ETHERNET MMC Rx interrupts.
#define | __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
Disables the specified ETHERNET MMC Rx interrupts.
#define | __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Enables the specified ETHERNET MMC Tx interrupts.
#define | __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
Disables the specified ETHERNET MMC Tx interrupts.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
Enables the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Disables the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
Enable event on ETH External event line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Disable event on ETH External event line.
#define | __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Get flag of the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Clear flag of the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
Enables rising edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Disables the rising edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
Enables falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Disables falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()
Enables rising/falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
Disables rising/falling edge trigger to the ETH External interrupt line.
#define | __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
Generate a Software interrupt on selected EXTI line.

Enumerations

enum HAL_ETH_StateTypeDef {
HAL_ETH_STATE_RESET = 0x00, HAL_ETH_STATE_READY = 0x01, HAL_ETH_STATE_BUSY = 0x02, HAL_ETH_STATE_BUSY_TX = 0x12,
HAL_ETH_STATE_BUSY_RX = 0x22, HAL_ETH_STATE_BUSY_TX_RX = 0x32, HAL_ETH_STATE_BUSY_WR = 0x42, HAL_ETH_STATE_BUSY_RD = 0x82,
HAL_ETH_STATE_TIMEOUT = 0x03, HAL_ETH_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_ETH_Init (ETH_HandleTypeDef *heth)
Initializes the Ethernet MAC and DMA according to default parameters.
HAL_StatusTypeDef | HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
De-Initializes the ETH peripheral.
__weak void | HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
__weak void | HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
HAL_StatusTypeDef | HAL_ETH_DMATxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
Initializes the DMA Tx descriptors in chain mode.
HAL_StatusTypeDef | HAL_ETH_DMARxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
Initializes the DMA Rx descriptors in chain mode.
HAL_StatusTypeDef | HAL_ETH_TransmitFrame (ETH_HandleTypeDef *heth, uint32_t FrameLength)
Sends an Ethernet frame.
HAL_StatusTypeDef | HAL_ETH_GetReceivedFrame (ETH_HandleTypeDef *heth)
Checks for received frames.
HAL_StatusTypeDef | HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
Reads a PHY register.
HAL_StatusTypeDef | HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
Writes to a PHY register.
HAL_StatusTypeDef | HAL_ETH_GetReceivedFrame_IT (ETH_HandleTypeDef *heth)
Gets the Received frame in interrupt mode.
void | HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
__weak void | HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
__weak void | HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
__weak void | HAL_ETH_ErrorCallback (ETH_HandleTypeDef *heth)
Ethernet transfer error callbacks.
HAL_StatusTypeDef | HAL_ETH_Start (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_Stop (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_ConfigMAC (ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
Set ETH MAC Configuration.
HAL_StatusTypeDef | HAL_ETH_ConfigDMA (ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
Sets ETH DMA Configuration.
HAL_ETH_StateTypeDef | HAL_ETH_GetState (ETH_HandleTypeDef *heth)
Return the ETH HAL state.

Detailed Description

Header file of ETH HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_eth.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash.h File Reference

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stm32f7xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002)
#define | HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004)
#define | HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010)
#define | HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020)
#define | FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00)
#define | FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01)
#define | FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02)
#define | FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03)
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_PGPERR FLASH_SR_PGPERR
#define | FLASH_FLAG_ERSERR FLASH_SR_ERSERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR ((uint32_t)0x02000000)
#define | FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
#define | FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define | FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define | FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define | CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
#define | FLASH_KEY1 ((uint32_t)0x45670123)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define | FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
#define | FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
Enable the FLASH Adaptive Real-Time memory accelerator.
#define | __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
Disable the FLASH Adaptive Real-Time memory accelerator.
#define | __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)
Resets the FLASH Adaptive Real-Time memory accelerator.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
Clear the specified FLASH flag.
#define | OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
OPTCR register byte 1 (Bits[15:8]) base address.
#define | IS_FLASH_TYPEPROGRAM(VALUE)

Enumerations

enum | FLASH_ProcedureTypeDef { FLASH_PROC_NONE = 0, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM }
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_flash.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash_ex.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32f7xx_hal_flash_ex.h File Reference

Header file of FLASH HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...

Defines

#define | FLASH_TYPEERASE_SECTORS ((uint32_t)0x00)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)
#define | FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00)
#define | FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01)
#define | FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02)
#define | FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03)
#define | OB_WRPSTATE_DISABLE ((uint32_t)0x00)
#define | OB_WRPSTATE_ENABLE ((uint32_t)0x01)
#define | OPTIONBYTE_WRP ((uint32_t)0x01)
#define | OPTIONBYTE_RDP ((uint32_t)0x02)
#define | OPTIONBYTE_USER ((uint32_t)0x04)
#define | OPTIONBYTE_BOR ((uint32_t)0x08)
#define | OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10)
#define | OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20)
#define | OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define | OB_RDP_LEVEL_1 ((uint8_t)0x55)
#define | OB_RDP_LEVEL_2 ((uint8_t)0xCC)
#define | OB_WWDG_SW ((uint32_t)0x10)
#define | OB_WWDG_HW ((uint32_t)0x00)
#define | OB_IWDG_SW ((uint32_t)0x20)
#define | OB_IWDG_HW ((uint32_t)0x00)
#define | OB_STOP_NO_RST ((uint32_t)0x40)
#define | OB_STOP_RST ((uint32_t)0x00)
#define | OB_STDBY_NO_RST ((uint32_t)0x80)
#define | OB_STDBY_RST ((uint32_t)0x00)
#define | OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000)
#define | OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000)
#define | OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000)
#define | OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000)
#define | OB_BOR_LEVEL3 ((uint32_t)0x00)
#define | OB_BOR_LEVEL2 ((uint32_t)0x04)
#define | OB_BOR_LEVEL1 ((uint32_t)0x08)
#define | OB_BOR_OFF ((uint32_t)0x0C)
#define | OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000)
#define | OB_BOOTADDR_SYSTEM ((uint32_t)0x0040)
#define | OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080)
#define | OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000)
#define | OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000)
#define | OB_BOOTADDR_SRAM1 ((uint32_t)0x8004)
#define | OB_BOOTADDR_SRAM2 ((uint32_t)0x8013)
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
#define | FLASH_MER_BIT (FLASH_CR_MER)
#define | FLASH_SECTOR_0 ((uint32_t)0)
#define | FLASH_SECTOR_1 ((uint32_t)1)
#define | FLASH_SECTOR_2 ((uint32_t)2)
#define | FLASH_SECTOR_3 ((uint32_t)3)
#define | FLASH_SECTOR_4 ((uint32_t)4)
#define | FLASH_SECTOR_5 ((uint32_t)5)
#define | FLASH_SECTOR_6 ((uint32_t)6)
#define | FLASH_SECTOR_7 ((uint32_t)7)
#define | OB_WRP_SECTOR_0 ((uint32_t)0x00010000)
#define | OB_WRP_SECTOR_1 ((uint32_t)0x00020000)
#define | OB_WRP_SECTOR_2 ((uint32_t)0x00040000)
#define | OB_WRP_SECTOR_3 ((uint32_t)0x00080000)
#define | OB_WRP_SECTOR_4 ((uint32_t)0x00100000)
#define | OB_WRP_SECTOR_5 ((uint32_t)0x00200000)
#define | OB_WRP_SECTOR_6 ((uint32_t)0x00400000)
#define | OB_WRP_SECTOR_7 ((uint32_t)0x00800000)
#define | OB_WRP_SECTOR_All ((uint32_t)0x00FF0000)
#define | FLASH_SECTOR_TOTAL 8
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_VOLTAGERANGE(RANGE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE)
#define | IS_OB_BOOT_ADDRESS(ADDRESS)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define | IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define | IS_FLASH_SECTOR(SECTOR)
#define | IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.

Detailed Description

Header file of FLASH HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_flash_ex.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_gpio.h File Reference

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stm32f7xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT ((uint32_t)0x00000000)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x10110000)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x10210000)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x10120000)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000)
#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003)
#define | GPIO_NOPULL ((uint32_t)0x00000000)
#define | GPIO_PULLUP ((uint32_t)0x00000001)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_gpio.h.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_gpio_ex.h File Reference

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Defines
stm32f7xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
#define | GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
#define | GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
#define | GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define | GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define | GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
#define | GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define | GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define | GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
#define | GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */
#define | GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define | GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define | GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define | GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define | GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */
#define | GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define | GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define | GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define | GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define | GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define | GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
#define | GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define | GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define | GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | GPIOA_PIN_AVAILABLE GPIO_PIN_All
GPIO pin available on the platform.
#define | GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define | GPIOK_PIN_AVAILABLE
#define | GPIO_GET_INDEX(__GPIOx__)
#define | IS_GPIO_PIN_AVAILABLE(__INSTANCE__, __PIN__)
#define | IS_GPIO_AF(AF)

Detailed Description

Header file of GPIO HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_gpio_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hcd.h File Reference

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stm32f7xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

#include "stm32f7xx_ll_usb.h"

Go to the source code of this file.

Data Structures

struct | HCD_HandleTypeDef

Defines

#define | HCD_SPEED_HIGH 0
#define | HCD_SPEED_LOW 2
#define | HCD_SPEED_FULL 3
#define | HCD_PHY_ULPI 1
#define | HCD_PHY_EMBEDDED 2
#define | __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
#define | IS_HCD_ALL_INSTANCE(INSTANCE)

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_hcd.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c.h File Reference

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stm32f7xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_I2C_ERROR_BERR ((uint32_t)0x00000001)
#define | HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002)
#define | HAL_I2C_ERROR_AF ((uint32_t)0x00000004)
#define | HAL_I2C_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_I2C_ERROR_DMA ((uint32_t)0x00000010)
#define | HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040)
#define | I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define | I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
#define | I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00)
#define | I2C_OA2_MASK01 ((uint8_t)0x01)
#define | I2C_OA2_MASK02 ((uint8_t)0x02)
#define | I2C_OA2_MASK03 ((uint8_t)0x03)
#define | I2C_OA2_MASK04 ((uint8_t)0x04)
#define | I2C_OA2_MASK05 ((uint8_t)0x05)
#define | I2C_OA2_MASK06 ((uint8_t)0x06)
#define | I2C_OA2_MASK07 ((uint8_t)0x07)
#define | I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define | I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE ((uint32_t)0x00000000)
#define | I2C_NO_STARTSTOP ((uint32_t)0x00000000)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupts.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupts.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2C interrupt source is enabled or disabled.
#define | I2C_FLAG_MASK ((uint32_t)0x0001FFFF)
Checks whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))
Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00, HAL_I2C_STATE_READY = 0x01, HAL_I2C_STATE_BUSY = 0x02, HAL_I2C_STATE_MASTER_BUSY_TX = 0x12,
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, HAL_I2C_STATE_MEM_BUSY_TX = 0x52,
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, HAL_I2C_STATE_TIMEOUT = 0x03, HAL_I2C_STATE_ERROR = 0x04
}

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no-blocking mode with DMA from a specific memory address.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callbacks.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callbacks.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callbacks.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callbacks.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callbacks.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Returns the I2C state.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_i2c.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c_ex.h File Reference

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Defines | Functions
stm32f7xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configures I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configures I2C Digital noise filter.

Detailed Description

Header file of I2C HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_i2c_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2s.h File Reference

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stm32f7xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_I2S_ERROR_OVR ((uint32_t)0x00000002)
#define | HAL_I2S_ERROR_UDR ((uint32_t)0x00000004)
#define | HAL_I2S_ERROR_DMA ((uint32_t)0x00000008)
#define | HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010)
#define | I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
#define | I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)
#define | I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
#define | I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
#define | I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
#define | I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
#define | I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
#define | I2S_STANDARD_MSB ((uint32_t)0x00000010)
#define | I2S_STANDARD_LSB ((uint32_t)0x00000020)
#define | I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
#define | I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
#define | I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
#define | I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
#define | I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
#define | I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
#define | I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
#define | I2S_AUDIOFREQ_192K ((uint32_t)192000)
#define | I2S_AUDIOFREQ_96K ((uint32_t)96000)
#define | I2S_AUDIOFREQ_48K ((uint32_t)48000)
#define | I2S_AUDIOFREQ_44K ((uint32_t)44100)
#define | I2S_AUDIOFREQ_32K ((uint32_t)32000)
#define | I2S_AUDIOFREQ_22K ((uint32_t)22050)
#define | I2S_AUDIOFREQ_16K ((uint32_t)16000)
#define | I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define | I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define | I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
#define | I2S_CPOL_LOW ((uint32_t)0x00000000)
#define | I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE
#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
Enable or disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.
#define | IS_I2S_CLOCKSOURCE(CLOCK)
#define | IS_I2S_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_CPOL(CPOL)

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00, HAL_I2S_STATE_READY = 0x01, HAL_I2S_STATE_BUSY = 0x02, HAL_I2S_STATE_BUSY_TX = 0x03,
HAL_I2S_STATE_BUSY_RX = 0x04, HAL_I2S_STATE_BUSY_TX_RX = 0x05, HAL_I2S_STATE_TIMEOUT = 0x06, HAL_I2S_STATE_ERROR = 0x07
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio stream playing from the Media.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_i2s.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_irda.h File Reference

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stm32f7xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010)
#define | IRDA_PARITY_NONE ((uint32_t)0x0000)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x0000)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_STATE_DISABLE ((uint32_t)0x0000)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | IRDA_MODE_DISABLE ((uint32_t)0x0000)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
#define | IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | IRDA_DMA_RX_DISABLE ((uint32_t)0x0000)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define | IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define | IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define | IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define | IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001)
#define | IRDA_IT_PE ((uint16_t)0x0028)
#define | IRDA_IT_TXE ((uint16_t)0x0727)
#define | IRDA_IT_TC ((uint16_t)0x0626)
#define | IRDA_IT_RXNE ((uint16_t)0x0525)
#define | IRDA_IT_IDLE ((uint16_t)0x0424)
#define | IRDA_IT_ERR ((uint16_t)0x0060)
Elements values convention: 000000000XXYYYYYb.
#define | IRDA_IT_ORE ((uint16_t)0x0300)
Elements values convention: 0000ZZZZ00000000b.
#define | IRDA_IT_NE ((uint16_t)0x0200)
#define | IRDA_IT_FE ((uint16_t)0x0100)
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
Reset IRDA handle state.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IRDA_IT_MASK ((uint16_t)0x001F)
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
#define | IS_IRDA_POWERMODE(__MODE__)
#define | IS_IRDA_STATE(__STATE__)
#define | IS_IRDA_MODE(__STATE__)
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
#define | IS_IRDA_DMA_TX(__DMATX__)
#define | IS_IRDA_DMA_RX(__DMARX__)
#define | IS_IRDA_REQUEST_PARAMETER(PARAM)

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00, HAL_IRDA_STATE_READY = 0x01, HAL_IRDA_STATE_BUSY = 0x02, HAL_IRDA_STATE_BUSY_TX = 0x12,
HAL_IRDA_STATE_BUSY_RX = 0x22, HAL_IRDA_STATE_BUSY_TX_RX = 0x32, HAL_IRDA_STATE_TIMEOUT = 0x03, HAL_IRDA_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00, IRDA_CLOCKSOURCE_PCLK2 = 0x01, IRDA_CLOCKSOURCE_HSI = 0x02, IRDA_CLOCKSOURCE_SYSCLK = 0x04,
IRDA_CLOCKSOURCE_LSE = 0x08
}
IRDA clock sources definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_irda.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_irda_ex.h File Reference

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Defines
stm32f7xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Reports the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(LENGTH)

Detailed Description

Header file of IRDA HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_irda_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_iwdg.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 ((uint8_t)0x00)
#define | IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0))
#define | IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1))
#define | IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2))
#define | IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))
#define | IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)
#define | __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
Reset IWDG handle state.
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enables the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
#define | __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected IWDG's flag status.
#define | IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA)
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC)
#define | IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555)
#define | IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000)
#define | IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU)
IWDG Flag definition.
#define | IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU)
#define | IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU)
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)
Check IWDG window value.

Enumerations

enum HAL_IWDG_StateTypeDef {
HAL_IWDG_STATE_RESET = 0x00, HAL_IWDG_STATE_READY = 0x01, HAL_IWDG_STATE_BUSY = 0x02, HAL_IWDG_STATE_TIMEOUT = 0x03,
HAL_IWDG_STATE_ERROR = 0x04
}
IWDG HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.
__weak void | HAL_IWDG_MspInit (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG MSP.
HAL_StatusTypeDef | HAL_IWDG_Start (IWDG_HandleTypeDef *hiwdg)
Starts the IWDG.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refreshes the IWDG.
HAL_IWDG_StateTypeDef | HAL_IWDG_GetState (IWDG_HandleTypeDef *hiwdg)
Returns the IWDG state.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_iwdg.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_lptim.h File Reference

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stm32f7xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable/Disable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Starts the LPTIM peripheral in Continuous or in single mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Writes the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Writes the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Checks whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified LPTIM interrupt is set or not.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define | IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF)
#define | IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF)

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00, HAL_LPTIM_STATE_READY = 0x01, HAL_LPTIM_STATE_BUSY = 0x02, HAL_LPTIM_STATE_TIMEOUT = 0x03,
HAL_LPTIM_STATE_ERROR = 0x04
}
HAL LPTIM State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_lptim.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nand.h File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

#include "stm32f7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_InfoTypeDef
NAND Memory info Structure definition. More...
struct | NAND_HandleTypeDef
NAND handle Structure definition. More...

Defines

#define | __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
Reset NAND handle state.
#define | NAND_DEVICE ((uint32_t)0x80000000)
#define | NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
#define | CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00)
#define | NAND_CMD_AREA_B ((uint8_t)0x01)
#define | NAND_CMD_AREA_C ((uint8_t)0x50)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define | NAND_CMD_READID ((uint8_t)0x90)
#define | NAND_CMD_STATUS ((uint8_t)0x70)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define | NAND_CMD_RESET ((uint8_t)0xFF)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define | NAND_BUSY ((uint32_t)0x00000000)
#define | NAND_ERROR ((uint32_t)0x00000001)
#define | NAND_READY ((uint32_t)0x00000040)
#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00, HAL_NAND_STATE_READY = 0x01, HAL_NAND_STATE_BUSY = 0x02, HAL_NAND_STATE_ERROR = 0x03 }
HAL NAND State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Write_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory.
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory.
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_nand.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nor.h File Reference

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stm32f7xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

#include "stm32f7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | NOR_HandleTypeDef
NOR handle Structure definition. More...

Defines

#define | __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
Reset NOR handle state.
#define | MC_ADDRESS ((uint16_t)0x0000)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000F)
#define | CFI1_ADDRESS ((uint16_t)0x61)
#define | CFI2_ADDRESS ((uint16_t)0x62)
#define | CFI3_ADDRESS ((uint16_t)0x63)
#define | CFI4_ADDRESS ((uint16_t)0x64)
#define | NOR_TMEOUT ((uint16_t)0xFFFF)
#define | NOR_MEMORY_8B ((uint8_t)0x0)
#define | NOR_MEMORY_16B ((uint8_t)0x1)
#define | NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
#define | NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
#define | NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
#define | NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__)
NOR memory write data to specified address.

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00, HAL_NOR_STATE_READY = 0x01, HAL_NOR_STATE_BUSY = 0x02, HAL_NOR_STATE_ERROR = 0x03,
HAL_NOR_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_nor.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd.h File Reference

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  • STM32F7xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f7xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32f7xx_ll_usb.h"
#include "stm32f7xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_HIGH 0
#define | PCD_SPEED_HIGH_IN_FULL 1
#define | PCD_SPEED_FULL 2
#define | PCD_PHY_ULPI 1
#define | PCD_PHY_EMBEDDED 2
#define | USBD_HS_TRDT_VALUE 9
#define | USBD_FS_TRDT_VALUE 5
#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000)
#define | USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | IS_PCD_ALL_INSTANCE(INSTANCE)

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handle PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pcd.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd_ex.h File Reference

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stm32f7xx_hal_pcd_ex.h File Reference

Header file of PCD HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM Feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
DeActivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pcd_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr.h File Reference

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stm32f7xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define | PWR_PVDLEVEL_7
#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)
#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0
#define | PWR_FLAG_WU PWR_CSR1_WUIF
#define | PWR_FLAG_SB PWR_CSR1_SBF
#define | PWR_FLAG_PVDO PWR_CSR1_PVDO
#define | PWR_FLAG_BRR PWR_CSR1_BRR
#define | PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
macros configure the main internal regulator output voltage.
#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)
Clear the PWR's pending flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Enable the PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
checks whether the specified PVD Exti interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD Exti flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Generates a Software interrupt on PVD EXTI line.
#define | PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)
#define | IS_PWR_WAKEUP_POLARITY(POLARITY)
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define | IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pwr.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr_ex.h File Reference

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stm32f7xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5
#define | PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6
#define | PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5
#define | PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
#define | PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
#define | PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS
#define | PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
#define | PWR_FLAG_ODRDY PWR_CSR1_ODRDY
#define | PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
#define | PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY
#define | PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1
#define | PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2
#define | PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3
#define | PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4
#define | PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5
#define | PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6
#define | __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
Macros to enable or disable the Over drive mode.
#define | __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
#define | __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
Macros to enable or disable the Over drive switching.
#define | __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
#define | __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
Macros to enable or disable the Under drive mode.
#define | __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
#define | __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
Clear the Under-Drive Ready flag.
#define | __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
Check Wake Up flag is set or not.
#define | __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))
Clear the WakeUp pins flags.
#define | IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR)
#define | IS_PWR_WAKEUP_PIN(__PIN__)

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Returns Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configures the main internal regulator output voltage.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enables the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disables the Flash Power Down in Stop mode.
HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enables the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disables the Backup Regulator.
void | HAL_PWREx_EnableMainRegulatorLowVoltage (void)
Enables Main Regulator low voltage mode.
void | HAL_PWREx_DisableMainRegulatorLowVoltage (void)
Disables Main Regulator low voltage mode.
void | HAL_PWREx_EnableLowRegulatorLowVoltage (void)
Enables Low Power Regulator low voltage mode.
void | HAL_PWREx_DisableLowRegulatorLowVoltage (void)
Disables Low Power Regulator low voltage mode.
HAL_StatusTypeDef | HAL_PWREx_EnableOverDrive (void)
Activates the Over-Drive mode.
HAL_StatusTypeDef | HAL_PWREx_DisableOverDrive (void)
Deactivates the Over-Drive mode.
HAL_StatusTypeDef | HAL_PWREx_EnterUnderDriveSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters in Under-Drive STOP mode.

Detailed Description

Header file of PWR HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pwr_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_qspi.h File Reference

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stm32f7xx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Defines

#define | HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
#define | HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)
#define | QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000)
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
#define | QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000)
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
#define | QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
#define | QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
#define | QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
#define | QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define | QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
#define | QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
#define | QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
#define | QSPI_ADDRESS_NONE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
#define | QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
#define | QSPI_DATA_NONE ((uint32_t)0X00000000)
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
#define | QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
#define | QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)
#define | QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)
#define | QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
#define | QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
#define | QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
#define | QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF
#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE
#define | HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable QSPI.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable QSPI.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enables the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disables the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified QSPI interrupt source is enabled.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Get the selected QSPI's flag status.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_FLASH_ID(FLA)
#define | IS_QSPI_DUAL_FLASH_MODE(MODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_DDR_HHC(DDR_HHC)
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
#define | IS_QSPI_GET_FLAG(FLAG)
#define | IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00, HAL_QSPI_STATE_READY = 0x01, HAL_QSPI_STATE_BUSY = 0x02, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, HAL_QSPI_STATE_ERROR = 0x04
}
HAL QSPI State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initializes the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
DeInitializes the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
QSPI MSP Init.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
QSPI MSP DeInit.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
This function handles QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Sets the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Sets the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Sends an amount of data in non blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receives an amount of data in non blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callbacks.
void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callbacks.
void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callbacks.
void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callbacks.
void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callbacks.
void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callbacks.
void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callbacks.
void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callbacks.
void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callbacks.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_qspi.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc.h File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define | RCC_HSE_OFF ((uint32_t)0x00000000)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF ((uint32_t)0x00000000)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF ((uint32_t)0x00000000)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_LSI_OFF ((uint32_t)0x00000000)
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_PLL_NONE ((uint32_t)0x00000000)
#define | RCC_PLL_OFF ((uint32_t)0x00000001)
#define | RCC_PLL_ON ((uint32_t)0x00000002)
#define | RCC_PLLP_DIV2 ((uint32_t)0x00000002)
#define | RCC_PLLP_DIV4 ((uint32_t)0x00000004)
#define | RCC_PLLP_DIV6 ((uint32_t)0x00000006)
#define | RCC_PLLP_DIV8 ((uint32_t)0x00000008)
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
#define | RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
#define | RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
#define | RCC_MCO1 ((uint32_t)0x00000000)
#define | RCC_MCO2 ((uint32_t)0x00000001)
#define | RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
#define | RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define | RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
#define | RCC_MCODIV_1 ((uint32_t)0x00000000)
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_5 RCC_CFGR_MCO1PRE
#define | RCC_IT_LSIRDY ((uint8_t)0x01)
#define | RCC_IT_LSERDY ((uint8_t)0x02)
#define | RCC_IT_HSIRDY ((uint8_t)0x04)
#define | RCC_IT_HSERDY ((uint8_t)0x08)
#define | RCC_IT_PLLRDY ((uint8_t)0x10)
#define | RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define | RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define | RCC_IT_CSS ((uint8_t)0x80)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define | RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_BORRST ((uint8_t)0x79)
#define | RCC_FLAG_PINRST ((uint8_t)0x7A)
#define | RCC_FLAG_PORRST ((uint8_t)0x7B)
#define | RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define | RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
#define | __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (__HSE__).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.
#define | __HAL_RCC_I2S_CONFIG(__SOURCE__)
Macro to configure the I2S clock source (I2SCLK).
#define | __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
Macros to enable or disable the PLLI2S.
#define | __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Macro to configures the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO1 clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
Macro to configure the MCO2 clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define | LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define | PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
#define | RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
#define | IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define | IS_RCC_PLLP_VALUE(VALUE)
#define | IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
#define | IS_RCC_PCLK(PCLK)
#define | IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_RTCCLKSOURCE(SOURCE)
#define | IS_RCC_LSE_DRIVE(DRIVE)

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rcc.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition. More...
struct | RCC_PLLSAIInitTypeDef
PLLSAI Clock structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...

Defines

#define | RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
#define | RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
#define | RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
#define | RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
#define | RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
#define | RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
#define | RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
#define | RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
#define | RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
#define | RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
#define | RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
#define | RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
#define | RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
#define | RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
#define | RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
#define | RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
#define | RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
#define | RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
#define | RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
#define | RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
#define | RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)
#define | RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000)
#define | RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001)
#define | RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002)
#define | RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003)
#define | RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
#define | RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
#define | RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
#define | RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
#define | RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
#define | RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
#define | RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
#define | RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
#define | RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
#define | RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
#define | RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
#define | RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
#define | RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
#define | RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
#define | RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
#define | RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
#define | RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
#define | RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
#define | RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
#define | RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
#define | RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
#define | RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
#define | RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
#define | RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
#define | RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
#define | RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
#define | RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
#define | RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
#define | RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
#define | RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
#define | RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
#define | RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
#define | RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
#define | RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
#define | RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
#define | RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
#define | RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
#define | RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
#define | RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
#define | RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define | RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
#define | RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
#define | RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
#define | RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
#define | RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
#define | RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
#define | RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
#define | RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
#define | RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
#define | __HAL_RCC_BKPSRAM_CLK_ENABLE()
Enables or disables the AHB1 peripheral clock.
#define | __HAL_RCC_DTCMRAMEN_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_DMA2D_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_HS_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_GPIOI_CLK_ENABLE()
#define | __HAL_RCC_GPIOJ_CLK_ENABLE()
#define | __HAL_RCC_GPIOK_CLK_ENABLE()
#define | __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
#define | __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
#define | __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
#define | __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define | __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
#define | __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
#define | __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
#define | __HAL_RCC_ETHMAC_CLK_ENABLE()
Enable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_CLK_ENABLE()
#define | __HAL_RCC_ETHMACRX_CLK_ENABLE()
#define | __HAL_RCC_ETHMACPTP_CLK_ENABLE()
#define | __HAL_RCC_ETH_CLK_ENABLE()
#define | __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Disable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
#define | __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
#define | __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
#define | __HAL_RCC_ETH_CLK_DISABLE()
#define | __HAL_RCC_DCMI_CLK_ENABLE()
Enable or disable the AHB2 peripheral clock.
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
#define | __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
#define | __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
#define | __HAL_RCC_FMC_CLK_ENABLE()
Enables or disables the AHB3 peripheral clock.
#define | __HAL_RCC_QSPI_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
#define | __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
#define | __HAL_RCC_TIM2_CLK_ENABLE()
Enable or disable the Low Speed APB (APB1) peripheral clock.
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_TIM12_CLK_ENABLE()
#define | __HAL_RCC_TIM13_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_SPDIFRX_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_I2C4_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_CAN2_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_DAC_CLK_ENABLE()
#define | __HAL_RCC_UART7_CLK_ENABLE()
#define | __HAL_RCC_UART8_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define | __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#define | __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#define | __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
#define | __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#define | __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
#define | __HAL_RCC_TIM1_CLK_ENABLE()
Enable or disable the High Speed APB (APB2) peripheral clock.
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_ADC2_CLK_ENABLE()
#define | __HAL_RCC_ADC3_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SPI4_CLK_ENABLE()
#define | __HAL_RCC_TIM9_CLK_ENABLE()
#define | __HAL_RCC_TIM10_CLK_ENABLE()
#define | __HAL_RCC_TIM11_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_SPI6_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define | __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
#define | __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define | __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
#define | __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
#define | __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
#define | __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Get the enable or disable status of the AHB1 peripheral clock.
#define | __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
#define | __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
#define | __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
#define | __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Enable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
#define | __HAL_RCC_ETH_IS_CLK_ENABLED()
#define | __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Disable ETHERNET clock.
#define | __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
#define | __HAL_RCC_ETH_IS_CLK_DISABLED()
#define | __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Get the enable or disable status of the AHB2 peripheral clock.
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
#define | __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
#define | __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Get the enable or disable status of the AHB3 peripheral clock.
#define | __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
#define | __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Get the enable or disable status of the APB1 peripheral clock.
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define | __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define | __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
#define | __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define | __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
#define | __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define | __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
#define | __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define | __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#define | __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
#define | __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#define | __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#define | __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
#define | __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
#define | __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Get the enable or disable status of the APB2 peripheral clock.
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define | __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
#define | __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
#define | __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
#define | __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define | __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
#define | __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#define | __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
#define | __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
#define | __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
#define | __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
#define | __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
#define | __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Force or release AHB1 peripheral reset.
#define | __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
#define | __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
#define | __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
#define | __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
#define | __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
#define | __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
#define | __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
#define | __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
#define | __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
#define | __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
#define | __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
#define | __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Force or release AHB2 peripheral reset.
#define | __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
#define | __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
#define | __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
#define | __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
#define | __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Force or release AHB3 peripheral reset.
#define | __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define | __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
#define | __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Force or release APB1 peripheral reset.
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
#define | __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
#define | __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
#define | __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
#define | __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
#define | __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define | __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
#define | __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
#define | __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define | __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define | __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
#define | __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
#define | __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
#define | __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#define | __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
#define | __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Force or release APB2 peripheral reset.
#define | __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
#define | __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
#define | __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
#define | __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
#define | __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
#define | __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
#define | __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
#define | __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
#define | __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
#define | __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
#define | __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
#define | __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
#define | __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
#define | __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
#define | __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
#define | __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
#define | __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
#define | __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
#define | __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
#define | __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
#define | __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
#define | __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
#define | __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
#define | __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
#define | __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
#define | __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
#define | __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
#define | __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
#define | __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
#define | __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
#define | __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
#define | __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
#define | __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
#define | __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
#define | __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
#define | __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
#define | __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
#define | __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
#define | __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
#define | __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
#define | __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
#define | __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
#define | __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
#define | __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
#define | __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
#define | __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
#define | __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
#define | __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
#define | __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
#define | __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
#define | __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
#define | __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
#define | __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
#define | __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
#define | __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
#define | __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
#define | __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
#define | __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
#define | __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
#define | __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
#define | __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
#define | __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
#define | __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
#define | __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
#define | __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
#define | __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
#define | __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
#define | __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
#define | __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
#define | __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
#define | __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
#define | __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
#define | __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
#define | __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
#define | __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
#define | __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
#define | __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
#define | __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
#define | __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
#define | __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
#define | __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
#define | __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
#define | __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
#define | __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
#define | __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
#define | __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
#define | __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
#define | __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
Macros to Enable or Disable the PLLISAI.
#define | __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
#define | __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)
Macro to configure the PLLSAI clock multiplication and division factors.
#define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)
Macro to configure the PLLI2S clock multiplication and division factors.
#define | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Macro to configure the SAI clock Divider coming from PLLI2S.
#define | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Macro to configure the SAI clock Divider coming from PLLSAI.
#define | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
Macro to configure the LTDC clock Divider coming from PLLSAI.
#define | __HAL_RCC_SAI1_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
Macro to configure SAI1 clock source selection.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SAI2_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
Macro to configure SAI2 clock source selection.
#define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
Macro to get the SAI2 clock source.
#define | __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
Enable PLLSAI_RDY interrupt.
#define | __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Disable PLLSAI_RDY interrupt.
#define | __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
Clear the PLLSAI RDY interrupt pending bits.
#define | __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Check the PLLSAI RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Check PLLSAI RDY flag is set or not.
#define | __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
Macro to Get I2S clock source selection.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
macro to get the I2C3 clock source.
#define | __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
Macro to configure the I2C4 clock (I2C4CLK).
#define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
macro to get the I2C4 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
macro to get the UART5 clock source.
#define | __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
Macro to configure the USART6 clock (USART6CLK).
#define | __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
macro to get the USART6 clock source.
#define | __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
Macro to configure the UART7 clock (UART7CLK).
#define | __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
macro to get the UART7 clock source.
#define | __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
Macro to configure the UART8 clock (UART8CLK).
#define | __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
macro to get the UART8 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
macro to get the LPTIM1 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
macro to get the CEC clock source.
#define | __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
Macro to configure the CLK48 source (CLK48CLK).
#define | __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
macro to get the CLK48 source.
#define | __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Macro to configure the SDMMC1 clock (SDMMC1CLK).
#define | __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
macro to get the SDMMC1 clock source.
#define | IS_RCC_PERIPHCLOCK(SELECTION)
#define | IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define | IS_RCC_PLLI2SP_VALUE(VALUE)
#define | IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define | IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define | IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define | IS_RCC_PLLSAIP_VALUE(VALUE)
#define | IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define | IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define | IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define | IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define | IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
#define | IS_RCC_I2SCLKSOURCE(SOURCE)
#define | IS_RCC_SDMMC1CLKSOURCE(SOURCE)
#define | IS_RCC_CECCLKSOURCE(SOURCE)
#define | IS_RCC_USART1CLKSOURCE(SOURCE)
#define | IS_RCC_USART2CLKSOURCE(SOURCE)
#define | IS_RCC_USART3CLKSOURCE(SOURCE)
#define | IS_RCC_UART4CLKSOURCE(SOURCE)
#define | IS_RCC_UART5CLKSOURCE(SOURCE)
#define | IS_RCC_USART6CLKSOURCE(SOURCE)
#define | IS_RCC_UART7CLKSOURCE(SOURCE)
#define | IS_RCC_UART8CLKSOURCE(SOURCE)
#define | IS_RCC_I2C1CLKSOURCE(SOURCE)
#define | IS_RCC_I2C2CLKSOURCE(SOURCE)
#define | IS_RCC_I2C3CLKSOURCE(SOURCE)
#define | IS_RCC_I2C4CLKSOURCE(SOURCE)
#define | IS_RCC_LPTIM1CLK(SOURCE)
#define | IS_RCC_CLK48SOURCE(SOURCE)
#define | IS_RCC_TIMPRES(VALUE)
#define | IS_RCC_SAI1CLKSOURCE(SOURCE)
#define | IS_RCC_SAI2CLKSOURCE(SOURCE)

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_PeriphCLKInitTypeDef according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)

Detailed Description

Header file of RCC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rcc_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rng.h File Reference

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stm32f7xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00, HAL_RNG_STATE_READY = 0x01, HAL_RNG_STATE_BUSY = 0x02, HAL_RNG_STATE_TIMEOUT = 0x03,
HAL_RNG_STATE_ERROR = 0x04
}

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rng.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc.h File Reference

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stm32f7xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
#define | RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001)
#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)
#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)
#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)
#define | IS_RTC_HOUR_FORMAT(__FORMAT__)
#define | IS_RTC_OUTPUT_POL(__POL__)
#define | IS_RTC_OUTPUT_TYPE(__TYPE__)
#define | IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F)
#define | IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7FFF)
#define | IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))
#define | IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23)
#define | IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59)
#define | IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59)
#define | IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(__SAVE__)
#define | IS_RTC_STORE_OPERATION(__OPERATION__)
#define | IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99)
#define | IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))
#define | IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))
#define | IS_RTC_WEEKDAY(__WEEKDAY__)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__)

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00, HAL_RTC_STATE_READY = 0x01, HAL_RTC_STATE_BUSY = 0x02, HAL_RTC_STATE_TIMEOUT = 0x03,
HAL_RTC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rtc.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)
#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002)
#define | RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004)
#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)
#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)
#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22)
#define | RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define | RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT))
#define | IS_RTC_OUTPUT(__OUTPUT__)
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(__EDGE__)
#define | IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(__PIN__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_WAKEUP_CLOCK(__CLOCK__)
#define | IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFFF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__)
#define | IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__)
#define | IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)
#define | IS_RTC_SHIFT_ADD1S(__SEL__)
#define | IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)
#define | IS_RTC_CALIB_OUTPUT(__OUTPUT__)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Sets Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.
void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Header file of RTC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rtc_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f7xx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_sai_ex.h"

Go to the source code of this file.

Data Structures

struct | SAI_InitTypeDef
SAI Init Structure definition. More...
struct | SAI_FrameInitTypeDef
SAI Block Frame Init structure definition. More...
struct | SAI_SlotInitTypeDef
SAI Block Slot Init Structure definition. More...
struct | __SAI_HandleTypeDef
SAI handle Structure definition. More...

Defines

#define | HAL_SAI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SAI_ERROR_OVR ((uint32_t)0x00000001)
#define | HAL_SAI_ERROR_UDR ((uint32_t)0x00000002)
#define | HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004)
#define | HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008)
#define | HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010)
#define | HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020)
#define | HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040)
#define | SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000)
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000001)
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000002)
#define | SAI_I2S_STANDARD ((uint32_t)0x00000000)
#define | SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001)
#define | SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002)
#define | SAI_PCM_LONG ((uint32_t)0x00000004)
#define | SAI_PCM_SHORT ((uint32_t)0x00000008)
#define | SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000)
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001)
#define | SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002)
#define | SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004)
#define | SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
#define | SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000)
#define | SAI_CLKSOURCE_EXT ((uint32_t)0x00200000)
#define | SAI_CLKSOURCE_NA ((uint32_t)0x00400000)
#define | SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)
#define | SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000)
#define | SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000)
#define | SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100)
#define | SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000)
#define | SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)
#define | SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)
#define | SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)
#define | SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
#define | SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0)
#define | SAI_MODEMASTER_TX ((uint32_t)0x00000000)
#define | SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define | SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define | SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
#define | SAI_FREE_PROTOCOL ((uint32_t)0x00000000)
#define | SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define | SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
#define | SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define | SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define | SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define | SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define | SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
#define | SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)
#define | SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)0x00000001)
#define | SAI_ASYNCHRONOUS ((uint32_t)0x00000000)
#define | SAI_SYNCHRONOUS ((uint32_t)0x00000001)
#define | SAI_SYNCHRONOUS_EXT_SAI1 ((uint32_t)0x00000002)
#define | SAI_SYNCHRONOUS_EXT_SAI2 ((uint32_t)0x00000003)
#define | SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000)
#define | SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
#define | SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000)
#define | SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
#define | SAI_FS_STARTFRAME ((uint32_t)0x00000000)
#define | SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
#define | SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)
#define | SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)
#define | SAI_FS_FIRSTBIT ((uint32_t)0x00000000)
#define | SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
#define | SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000)
#define | SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define | SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
#define | SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
#define | SAI_SLOTACTIVE_0 ((uint32_t)0x00000001)
#define | SAI_SLOTACTIVE_1 ((uint32_t)0x00000002)
#define | SAI_SLOTACTIVE_2 ((uint32_t)0x00000004)
#define | SAI_SLOTACTIVE_3 ((uint32_t)0x00000008)
#define | SAI_SLOTACTIVE_4 ((uint32_t)0x00000010)
#define | SAI_SLOTACTIVE_5 ((uint32_t)0x00000020)
#define | SAI_SLOTACTIVE_6 ((uint32_t)0x00000040)
#define | SAI_SLOTACTIVE_7 ((uint32_t)0x00000080)
#define | SAI_SLOTACTIVE_8 ((uint32_t)0x00000100)
#define | SAI_SLOTACTIVE_9 ((uint32_t)0x00000200)
#define | SAI_SLOTACTIVE_10 ((uint32_t)0x00000400)
#define | SAI_SLOTACTIVE_11 ((uint32_t)0x00000800)
#define | SAI_SLOTACTIVE_12 ((uint32_t)0x00001000)
#define | SAI_SLOTACTIVE_13 ((uint32_t)0x00002000)
#define | SAI_SLOTACTIVE_14 ((uint32_t)0x00004000)
#define | SAI_SLOTACTIVE_15 ((uint32_t)0x00008000)
#define | SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFF)
#define | SAI_STEREOMODE ((uint32_t)0x00000000)
#define | SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
#define | SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)
#define | SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
#define | SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)
#define | SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1)
#define | SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2)
#define | SAI_NOCOMPANDING ((uint32_t)0x00000000)
#define | SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1)
#define | SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define | SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define | SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
#define | SAI_ZERO_VALUE ((uint32_t)0x00000000)
#define | SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
#define | SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define | SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define | SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define | SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define | SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define | SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define | SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
#define | SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define | SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define | SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define | SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define | SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define | SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define | SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
#define | SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000)
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000)
#define | SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000)
#define | SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000)
#define | SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000)
#define | SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000)
#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified SAI interrupt source is enabled or disabled.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clears the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_CLK_SOURCE(SOURCE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_FIFO_STATUS(STATUS)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef
SAI handle Structure definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00, HAL_SAI_STATE_READY = 0x01, HAL_SAI_STATE_BUSY = 0x02, HAL_SAI_STATE_BUSY_TX = 0x12,
HAL_SAI_STATE_BUSY_RX = 0x22, HAL_SAI_STATE_TIMEOUT = 0x03, HAL_SAI_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initializes the SAI according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitializes the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
SAI MSP Init.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
SAI MSP DeInit.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmits an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receives an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmits an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receives an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stops the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disbaled the SAI.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
This function handles SAI interrupt request.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callbacks.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callbacks.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callbacks.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callbacks.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callbacks.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Returns the SAI state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sai.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai_ex.h File Reference

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Functions
stm32f7xx_hal_sai_ex.h File Reference

Header file of SAI Extension HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Functions

void | SAI_BlockSynchroConfig (SAI_HandleTypeDef *hsai)
Configure SAI Block synchronization mode.
uint32_t | SAI_GetInputClock (SAI_HandleTypeDef *hsai)
Get SAI Input Clock based on SAI source clock selection.

Detailed Description

Header file of SAI Extension HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sai_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sd.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_sd.h File Reference

Header file of SD HAL module. More...

#include "stm32f7xx_ll_sdmmc.h"

Go to the source code of this file.

Data Structures

struct | SD_HandleTypeDef
struct | HAL_SD_CSDTypedef
struct | HAL_SD_CIDTypedef
struct | HAL_SD_CardStatusTypedef
struct | HAL_SD_CardInfoTypedef

Defines

#define | SD_InitTypeDef SDMMC_InitTypeDef
#define | SD_TypeDef SDMMC_TypeDef
#define | SD_CMD_GO_IDLE_STATE ((uint8_t)0)
SD Commands Index.
#define | SD_CMD_SEND_OP_COND ((uint8_t)1)
#define | SD_CMD_ALL_SEND_CID ((uint8_t)2)
#define | SD_CMD_SET_REL_ADDR ((uint8_t)3)
#define | SD_CMD_SET_DSR ((uint8_t)4)
#define | SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5)
#define | SD_CMD_HS_SWITCH ((uint8_t)6)
#define | SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
#define | SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)
#define | SD_CMD_SEND_CSD ((uint8_t)9)
#define | SD_CMD_SEND_CID ((uint8_t)10)
#define | SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11)
#define | SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
#define | SD_CMD_SEND_STATUS ((uint8_t)13)
#define | SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
#define | SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)
#define | SD_CMD_SET_BLOCKLEN ((uint8_t)16)
#define | SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
#define | SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
#define | SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)
#define | SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20)
#define | SD_CMD_SET_BLOCK_COUNT ((uint8_t)23)
#define | SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
#define | SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
#define | SD_CMD_PROG_CID ((uint8_t)26)
#define | SD_CMD_PROG_CSD ((uint8_t)27)
#define | SD_CMD_SET_WRITE_PROT ((uint8_t)28)
#define | SD_CMD_CLR_WRITE_PROT ((uint8_t)29)
#define | SD_CMD_SEND_WRITE_PROT ((uint8_t)30)
#define | SD_CMD_SD_ERASE_GRP_START ((uint8_t)32)
#define | SD_CMD_SD_ERASE_GRP_END ((uint8_t)33)
#define | SD_CMD_ERASE_GRP_START ((uint8_t)35)
#define | SD_CMD_ERASE_GRP_END ((uint8_t)36)
#define | SD_CMD_ERASE ((uint8_t)38)
#define | SD_CMD_FAST_IO ((uint8_t)39)
#define | SD_CMD_GO_IRQ_STATE ((uint8_t)40)
#define | SD_CMD_LOCK_UNLOCK ((uint8_t)42)
#define | SD_CMD_APP_CMD ((uint8_t)55)
#define | SD_CMD_GEN_CMD ((uint8_t)56)
#define | SD_CMD_NO_CMD ((uint8_t)64)
#define | SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)
Following commands are SD Card Specific commands.
#define | SD_CMD_SD_APP_STATUS ((uint8_t)13)
#define | SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)
#define | SD_CMD_SD_APP_OP_COND ((uint8_t)41)
#define | SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)
#define | SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)
#define | SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52)
#define | SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53)
#define | SD_CMD_SD_APP_GET_MKB ((uint8_t)43)
Following commands are SD Card Specific security commands.
#define | SD_CMD_SD_APP_GET_MID ((uint8_t)44)
#define | SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
#define | SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
#define | SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
#define | SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
#define | SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
#define | SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
#define | SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
#define | SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
#define | SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
#define | STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
Supported SD Memory Cards.
#define | STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
#define | HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
#define | MULTIMEDIA_CARD ((uint32_t)0x00000003)
#define | SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
#define | HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
#define | SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
#define | HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
#define | __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
Enable the SD device.
#define | __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
Disable the SD device.
#define | __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
Enable the SDMMC DMA transfer.
#define | __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
Disable the SDMMC DMA transfer.
#define | __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Enable the SD device interrupt.
#define | __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Disable the SD device interrupt.
#define | __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
Check whether the specified SD flag is set or not.
#define | __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
Clear the SD's pending flags.
#define | __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Check whether the specified SD interrupt has occurred or not.
#define | __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
Clear the SD's interrupt pending bits.

Enumerations

enum HAL_SD_ErrorTypedef {
SD_CMD_CRC_FAIL = (1), SD_DATA_CRC_FAIL = (2), SD_CMD_RSP_TIMEOUT = (3), SD_DATA_TIMEOUT = (4),
SD_TX_UNDERRUN = (5), SD_RX_OVERRUN = (6), SD_START_BIT_ERR = (7), SD_CMD_OUT_OF_RANGE = (8),
SD_ADDR_MISALIGNED = (9), SD_BLOCK_LEN_ERR = (10), SD_ERASE_SEQ_ERR = (11), SD_BAD_ERASE_PARAM = (12),
SD_WRITE_PROT_VIOLATION = (13), SD_LOCK_UNLOCK_FAILED = (14), SD_COM_CRC_FAILED = (15), SD_ILLEGAL_CMD = (16),
SD_CARD_ECC_FAILED = (17), SD_CC_ERROR = (18), SD_GENERAL_UNKNOWN_ERROR = (19), SD_STREAM_READ_UNDERRUN = (20),
SD_STREAM_WRITE_OVERRUN = (21), SD_CID_CSD_OVERWRITE = (22), SD_WP_ERASE_SKIP = (23), SD_CARD_ECC_DISABLED = (24),
SD_ERASE_RESET = (25), SD_AKE_SEQ_ERROR = (26), SD_INVALID_VOLTRANGE = (27), SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29), SD_SDMMC_DISABLED = (30), SD_SDMMC_FUNCTION_BUSY = (31), SD_SDMMC_FUNCTION_FAILED = (32),
SD_SDMMC_UNKNOWN_FUNCTION = (33), SD_INTERNAL_ERROR = (34), SD_NOT_CONFIGURED = (35), SD_REQUEST_PENDING = (36),
SD_REQUEST_NOT_APPLICABLE = (37), SD_INVALID_PARAMETER = (38), SD_UNSUPPORTED_FEATURE = (39), SD_UNSUPPORTED_HW = (40),
SD_ERROR = (41), SD_OK = (0)
}
enum | HAL_SD_TransferStateTypedef { SD_TRANSFER_OK = 0, SD_TRANSFER_BUSY = 1, SD_TRANSFER_ERROR = 2 }
enum HAL_SD_CardStateTypedef {
SD_CARD_READY = ((uint32_t)0x00000001), SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), SD_CARD_STANDBY = ((uint32_t)0x00000003), SD_CARD_TRANSFER = ((uint32_t)0x00000004),
SD_CARD_SENDING = ((uint32_t)0x00000005), SD_CARD_RECEIVING = ((uint32_t)0x00000006), SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), SD_CARD_DISCONNECTED = ((uint32_t)0x00000008),
SD_CARD_ERROR = ((uint32_t)0x000000FF)
}
enum | HAL_SD_OperationTypedef { SD_READ_SINGLE_BLOCK = 0, SD_READ_MULTIPLE_BLOCK = 1, SD_WRITE_SINGLE_BLOCK = 2, SD_WRITE_MULTIPLE_BLOCK = 3 }

Functions

HAL_SD_ErrorTypedef | HAL_SD_Init (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Allows to write block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_DMA_RxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Rx callback in non blocking mode.
__weak void | HAL_SD_DMA_RxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx error callback.
__weak void | HAL_SD_DMA_TxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Tx callback in non blocking mode.
__weak void | HAL_SD_DMA_TxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete error Tx callback.
__weak void | HAL_SD_XferCpltCallback (SD_HandleTypeDef *hsd)
SD end of transfer callback.
__weak void | HAL_SD_XferErrorCallback (SD_HandleTypeDef *hsd)
SD Transfer Error callback.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_CheckWriteOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data write transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_CheckReadOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data read transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_Get_CardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
Returns information about specific card.
HAL_SD_ErrorTypedef | HAL_SD_WideBusOperation_Config (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_ErrorTypedef | HAL_SD_StopTransfer (SD_HandleTypeDef *hsd)
Aborts an ongoing data transfer.
HAL_SD_ErrorTypedef | HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
HAL_SD_ErrorTypedef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Returns the current SD card's status.
HAL_SD_ErrorTypedef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
Gets the SD card status.
HAL_SD_TransferStateTypedef | HAL_SD_GetStatus (SD_HandleTypeDef *hsd)
Gets the current sd card data status.

Detailed Description

Header file of SD HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sd.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sdram.h File Reference

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stm32f7xx_hal_sdram.h File Reference

Header file of SDRAM HAL module. More...

#include "stm32f7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | SDRAM_HandleTypeDef
SDRAM handle Structure definition. More...

Defines

#define | __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
Reset SDRAM handle state.

Enumerations

enum HAL_SDRAM_StateTypeDef {
HAL_SDRAM_STATE_RESET = 0x00, HAL_SDRAM_STATE_READY = 0x01, HAL_SDRAM_STATE_BUSY = 0x02, HAL_SDRAM_STATE_ERROR = 0x03,
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, HAL_SDRAM_STATE_PRECHARGED = 0x05
}
HAL SDRAM State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.
HAL_SDRAM_StateTypeDef | HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

Header file of SDRAM HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sdram.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard.h File Reference

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stm32f7xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10)
#define | HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20)
#define | SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x0000)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x0000)
#define | SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define | SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
#define | SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
#define | SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
#define | SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
#define | SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
#define | SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
#define | SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
#define | SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
#define | SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
#define | SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
#define | SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
#define | SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
#define | SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
#define | SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
#define | SMARTCARD_IT_PE ((uint16_t)0x0028)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)
#define | SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)
#define | SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)
#define | SMARTCARD_IT_MASK ((uint16_t)0x001F)
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
Reset SMARTCARD handle state.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))
Flush the Smartcard DR register.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Checks whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Checks whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified SmartCard interrupt interrupt source is enabled.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
Macros to enable or disable the SmartCard DMA request.
#define | __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
#define | IS_SMARTCARD_PARITY(__PARITY__)
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
#define | IS_SMARTCARD_NACK(__NACK__)
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
#define | IS_SMARTCARD_ADVFEATURE_INIT(INIT)
#define | IS_SMARTCARD_ADVFEATURE_TXINV(TXINV)
#define | IS_SMARTCARD_ADVFEATURE_RXINV(RXINV)
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV)
#define | IS_SMARTCARD_ADVFEATURE_SWAP(SWAP)
#define | IS_SMARTCARD_OVERRUN(OVERRUN)
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA)
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST)
#define | IS_SMARTCARD_REQUEST_PARAMETER(PARAM)

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00, HAL_SMARTCARD_STATE_READY = 0x01, HAL_SMARTCARD_STATE_BUSY = 0x02, HAL_SMARTCARD_STATE_BUSY_TX = 0x12,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, HAL_SMARTCARD_STATE_TIMEOUT = 0x03, HAL_SMARTCARD_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_HSI = 0x02, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04,
SMARTCARD_CLOCKSOURCE_LSE = 0x08
}
SMARTCARD clock sources definition. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SMARTCARD mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD interrupt requests handling.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_smartcard.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard_ex.h File Reference

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Defines | Functions
stm32f7xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the SMARTCARD clock source.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_smartcard_ex.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spdifrx.h File Reference

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  • STM32F7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_spdifrx.h File Reference

Header file of SPDIFRX HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SPDIFRX_InitTypeDef
SPDIFRX Init structure definition. More...
struct | SPDIFRX_SetDataFormatTypeDef
SPDIFRX SetDataFormat structure definition. More...
struct | SPDIFRX_HandleTypeDef
SPDIFRX handle Structure definition. More...

Defines

#define | HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002)
#define | HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004)
#define | HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008)
#define | HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010)
#define | SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)
#define | SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000)
#define | SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)
#define | SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)
#define | SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)
#define | SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000)
#define | SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)
#define | SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)
#define | SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
#define | SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
#define | SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */
#define | SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
#define | SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
#define | SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)
#define | SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
#define | SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)
#define | SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
#define | SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)
#define | SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)
#define | SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)
#define | SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)
#define | SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
#define | SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)
#define | SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
#define | SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
#define | SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define | SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define | SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define | SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define | SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define | SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define | SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
#define | SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define | SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define | SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define | SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define | SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define | SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define | SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define | SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define | SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
#define | __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
Reset SPDIFRX handle state.
#define | __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
Disable the specified SPDIFRX peripheral (IDLE State).
#define | __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
Enable the specified SPDIFRX peripheral (SYNC State).
#define | __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
Enable the specified SPDIFRX peripheral (RCV State).
#define | __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SPDIFRX interrupts.
#define | __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
#define | __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPDIFRX interrupt source is enabled or disabled.
#define | __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified SPDIFRX flag is set or not.
#define | __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
#define | IS_SPDIFRX_INPUT_SELECT(INPUT)
#define | IS_SPDIFRX_MAX_RETRIES(RET)
#define | IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)
#define | IS_PREAMBLE_TYPE_MASK(VAL)
#define | IS_VALIDITY_MASK(VAL)
#define | IS_PARITY_ERROR_MASK(VAL)
#define | IS_SPDIFRX_CHANNEL(CHANNEL)
#define | IS_SPDIFRX_DATA_FORMAT(FORMAT)
#define | IS_STEREO_MODE(MODE)
#define | IS_CHANNEL_STATUS_MASK(VAL)

Enumerations

enum HAL_SPDIFRX_StateTypeDef {
HAL_SPDIFRX_STATE_RESET = 0x00, HAL_SPDIFRX_STATE_READY = 0x01, HAL_SPDIFRX_STATE_BUSY = 0x02, HAL_SPDIFRX_STATE_BUSY_RX = 0x03,
HAL_SPDIFRX_STATE_BUSY_CX = 0x04, HAL_SPDIFRX_STATE_ERROR = 0x07
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX error code.

Detailed Description

Header file of SPDIFRX HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_spdifrx.h.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spi.h File Reference

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stm32f7xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE (uint32_t)0x00000000
#define | HAL_SPI_ERROR_MODF (uint32_t)0x00000001
#define | HAL_SPI_ERROR_CRC (uint32_t)0x00000002
#define | HAL_SPI_ERROR_OVR (uint32_t)0x00000004
#define | HAL_SPI_ERROR_FRE (uint32_t)0x00000008
#define | HAL_SPI_ERROR_DMA (uint32_t)0x00000010
#define | HAL_SPI_ERROR_FLAG (uint32_t)0x00000020
#define | HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040
#define | SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_4BIT ((uint32_t)0x0300)
#define | SPI_DATASIZE_5BIT ((uint32_t)0x0400)
#define | SPI_DATASIZE_6BIT ((uint32_t)0x0500)
#define | SPI_DATASIZE_7BIT ((uint32_t)0x0600)
#define | SPI_DATASIZE_8BIT ((uint32_t)0x0700)
#define | SPI_DATASIZE_9BIT ((uint32_t)0x0800)
#define | SPI_DATASIZE_10BIT ((uint32_t)0x0900)
#define | SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
#define | SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
#define | SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
#define | SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
#define | SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
#define | SPI_DATASIZE_16BIT ((uint32_t)0x0F00)
#define | SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
#define | SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
#define | SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FTLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
#define | SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
#define | SPI_FTLVL_FULL ((uint32_t)0x1800)
#define | SPI_FRLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
#define | SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
#define | SPI_FRLVL_FULL ((uint32_t)0x0600)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enables or disables the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified SPI interrupt source is enabled or disabled.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clears the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clears the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clears the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clears the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enables the SPI.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disables the SPI.
#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Sets the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Sets the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Resets the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00, HAL_SPI_STATE_READY = 0x01, HAL_SPI_STATE_BUSY = 0x02, HAL_SPI_STATE_BUSY_TX = 0x03,
HAL_SPI_STATE_BUSY_RX = 0x04, HAL_SPI_STATE_BUSY_TX_RX = 0x05, HAL_SPI_STATE_ERROR = 0x06
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initializes the SPI according to the specified parameters in the SPI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
DeInitializes the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
SPI MSP Init.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
SPI MSP DeInit.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stops the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
This function handles SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callbacks.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_spi.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sram.h File Reference

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stm32f7xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

#include "stm32f7xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Defines

#define | __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
Reset SRAM handle state.

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00, HAL_SRAM_STATE_READY = 0x01, HAL_SRAM_STATE_BUSY = 0x02, HAL_SRAM_STATE_ERROR = 0x03,
HAL_SRAM_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sram.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim.h File Reference

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stm32f7xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000)
#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
#define | TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
#define | TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
#define | TIM_OCFAST_DISABLE ((uint32_t)0x0000)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
#define | TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
#define | TIM_ICPSC_DIV1 ((uint32_t)0x0000)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)
#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_BREAK2 (TIM_SR_B2IF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)
#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x0000)
#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x0000)
#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x0000)
#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
#define | TIM_TRGO_RESET ((uint32_t)0x0000)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
#define | TIM_TS_ITR0 ((uint32_t)0x0000)
#define | TIM_TS_ITR1 ((uint32_t)0x0010)
#define | TIM_TS_ITR2 ((uint32_t)0x0020)
#define | TIM_TS_ITR3 ((uint32_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint32_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint32_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define | TIM_TS_ETRF ((uint32_t)0x0070)
#define | TIM_TS_NONE ((uint32_t)0xFFFF)
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define | TIM_DMABASE_CR1 (0x00000000)
#define | TIM_DMABASE_CR2 (0x00000001)
#define | TIM_DMABASE_SMCR (0x00000002)
#define | TIM_DMABASE_DIER (0x00000003)
#define | TIM_DMABASE_SR (0x00000004)
#define | TIM_DMABASE_EGR (0x00000005)
#define | TIM_DMABASE_CCMR1 (0x00000006)
#define | TIM_DMABASE_CCMR2 (0x00000007)
#define | TIM_DMABASE_CCER (0x00000008)
#define | TIM_DMABASE_CNT (0x00000009)
#define | TIM_DMABASE_PSC (0x0000000A)
#define | TIM_DMABASE_ARR (0x0000000B)
#define | TIM_DMABASE_RCR (0x0000000C)
#define | TIM_DMABASE_CCR1 (0x0000000D)
#define | TIM_DMABASE_CCR2 (0x0000000E)
#define | TIM_DMABASE_CCR3 (0x0000000F)
#define | TIM_DMABASE_CCR4 (0x00000010)
#define | TIM_DMABASE_BDTR (0x00000011)
#define | TIM_DMABASE_DCR (0x00000012)
#define | TIM_DMABASE_OR (0x00000013)
#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6)
#define | TIM_CCx_ENABLE ((uint32_t)0x0001)
#define | TIM_CCx_DISABLE ((uint32_t)0x0000)
#define | TIM_CCxN_ENABLE ((uint32_t)0x0004)
#define | TIM_CCxN_DISABLE ((uint32_t)0x0000)
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
Enable the TIM update source request.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Disable the TIM update source request.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
#define | __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OUTPUT_STATE(STATE)
#define | IS_TIM_OUTPUTN_STATE(STATE)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))
#define | IS_TIM_GET_IT(__IT__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_FLAG(__FLAG__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00, HAL_TIM_STATE_READY = 0x01, HAL_TIM_STATE_BUSY = 0x02, HAL_TIM_STATE_TIMEOUT = 0x03,
HAL_TIM_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00
}
HAL Active channel structures definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
__weak HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 4 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_tim.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim_ex.h File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...

Defines

#define | TIM_CHANNEL_1 ((uint32_t)0x0000)
#define | TIM_CHANNEL_2 ((uint32_t)0x0004)
#define | TIM_CHANNEL_3 ((uint32_t)0x0008)
#define | TIM_CHANNEL_4 ((uint32_t)0x000C)
#define | TIM_CHANNEL_5 ((uint32_t)0x0010)
#define | TIM_CHANNEL_6 ((uint32_t)0x0014)
#define | TIM_CHANNEL_ALL ((uint32_t)0x003C)
#define | TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | TIM_TIM2_TIM8_TRGO (0x00000000)
#define | TIM_TIM2_ETH_PTP (0x00000400)
#define | TIM_TIM2_USBFS_SOF (0x00000800)
#define | TIM_TIM2_USBHS_SOF (0x00000C00)
#define | TIM_TIM5_GPIO (0x00000000)
#define | TIM_TIM5_LSI (0x00000040)
#define | TIM_TIM5_LSE (0x00000080)
#define | TIM_TIM5_RTC (0x000000C0)
#define | TIM_TIM11_GPIO (0x00000000)
#define | TIM_TIM11_SPDIFRX (0x00000001)
#define | TIM_TIM11_HSE (0x00000002)
#define | TIM_TIM11_MCO1 (0x00000003)
#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define | TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
#define | TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
#define | TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
#define | TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
#define | TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)
#define | TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
#define | TIM_TRGO2_RESET ((uint32_t)0x00000000)
#define | TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define | TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
#define | TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Gets the TIM Capture Compare Register value on runtime.
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_PWMI_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_REMAP(__TIM_REMAP__)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
#define | IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
#define | IS_TIM_CLEARINPUT_SOURCE(MODE)
#define | IS_TIM_BREAK2_STATE(STATE)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
#define | IS_TIM_TRGO2_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t OCRef)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Header file of TIM HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_tim_ex.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_uart.h File Reference

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stm32f7xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010)
#define | UART_STOPBITS_1 ((uint32_t)0x0000)
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | UART_PARITY_NONE ((uint32_t)0x00000000)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | UART_STATE_DISABLE ((uint32_t)0x00000000)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
#define | UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | UART_LIN_DISABLE ((uint32_t)0x00000000)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
#define | UART_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | UART_DMA_RX_DISABLE ((uint32_t)0x0000)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)
#define | UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
#define | UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
#define | UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)
#define | UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
#define | UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)
#define | UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)
#define | UART_IT_MASK ((uint32_t)0x001F)
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFF
#define | UART_FLAG_TEACK ((uint32_t)0x00200000)
#define | UART_FLAG_SBKF ((uint32_t)0x00040000)
#define | UART_FLAG_CMF ((uint32_t)0x00020000)
#define | UART_FLAG_BUSY ((uint32_t)0x00010000)
#define | UART_FLAG_ABRF ((uint32_t)0x00008000)
#define | UART_FLAG_ABRE ((uint32_t)0x00004000)
#define | UART_FLAG_EOBF ((uint32_t)0x00001000)
#define | UART_FLAG_RTOF ((uint32_t)0x00000800)
#define | UART_FLAG_CTS ((uint32_t)0x00000400)
#define | UART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | UART_FLAG_LBDF ((uint32_t)0x00000100)
#define | UART_FLAG_TXE ((uint32_t)0x00000080)
#define | UART_FLAG_TC ((uint32_t)0x00000040)
#define | UART_FLAG_RXNE ((uint32_t)0x00000020)
#define | UART_FLAG_IDLE ((uint32_t)0x00000010)
#define | UART_FLAG_ORE ((uint32_t)0x00000008)
#define | UART_FLAG_NE ((uint32_t)0x00000004)
#define | UART_FLAG_FE ((uint32_t)0x00000002)
#define | UART_FLAG_PE ((uint32_t)0x00000001)
#define | UART_IT_PE ((uint32_t)0x0028)
#define | UART_IT_TXE ((uint32_t)0x0727)
#define | UART_IT_TC ((uint32_t)0x0626)
#define | UART_IT_RXNE ((uint32_t)0x0525)
#define | UART_IT_IDLE ((uint32_t)0x0424)
#define | UART_IT_LBD ((uint32_t)0x0846)
#define | UART_IT_CTS ((uint32_t)0x096A)
#define | UART_IT_CM ((uint32_t)0x112E)
#define | UART_IT_ERR ((uint32_t)0x0060)
Elements values convention: 000000000XXYYYYYb.
#define | UART_IT_ORE ((uint32_t)0x0300)
Elements values convention: 0000ZZZZ00000000b.
#define | UART_IT_NE ((uint32_t)0x0200)
#define | UART_IT_FE ((uint32_t)0x0100)
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_EOBF USART_ICR_EOBCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
Reset UART handle state.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
Clears the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Checks whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Checks whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified UART interrupt source is enabled.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enables the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disables the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | UART_DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_)))
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_)))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_)))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
Check UART deassertion time.
#define | IS_UART_STOPBITS(STOPBITS)
#define | IS_UART_PARITY(PARITY)
#define | IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
#define | IS_UART_STATE(STATE)
#define | IS_UART_OVERSAMPLING(SAMPLING)
#define | IS_UART_ONE_BIT_SAMPLE(ONEBIT)
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE)
#define | IS_UART_RECEIVER_TIMEOUT(TIMEOUT)
#define | IS_UART_LIN(LIN)
#define | IS_UART_WAKEUPMETHOD(WAKEUP)
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_UART_DMA_TX(DMATX)
#define | IS_UART_DMA_RX(DMARX)
#define | IS_UART_HALF_DUPLEX(HDSEL)
#define | IS_UART_REQUEST_PARAMETER(PARAM)
#define | IS_UART_ADVFEATURE_INIT(INIT)
#define | IS_UART_ADVFEATURE_TXINV(TXINV)
#define | IS_UART_ADVFEATURE_RXINV(RXINV)
#define | IS_UART_ADVFEATURE_DATAINV(DATAINV)
#define | IS_UART_ADVFEATURE_SWAP(SWAP)
#define | IS_UART_OVERRUN(OVERRUN)
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE)
#define | IS_UART_ADVFEATURE_DMAONRXERROR(DMA)
#define | IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST)
#define | IS_UART_MUTE_MODE(MUTE)
#define | IS_UART_DE_POLARITY(POLARITY)

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00, HAL_UART_STATE_READY = 0x01, HAL_UART_STATE_BUSY = 0x02, HAL_UART_STATE_BUSY_TX = 0x12,
HAL_UART_STATE_BUSY_RX = 0x22, HAL_UART_STATE_BUSY_TX_RX = 0x32, HAL_UART_STATE_TIMEOUT = 0x03, HAL_UART_STATE_ERROR = 0x04
}
HAL UART State structures definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00, UART_CLOCKSOURCE_PCLK2 = 0x01, UART_CLOCKSOURCE_HSI = 0x02, UART_CLOCKSOURCE_SYSCLK = 0x04,
UART_CLOCKSOURCE_LSE = 0x08, UART_CLOCKSOURCE_UNDEFINED = 0x10
}
UART clock sources definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (doesn't mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (doesn't mean it actually wakes up the software, as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
return the UART state
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_uart.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_uart_ex.h File Reference

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Defines
stm32f7xx_hal_uart_ex.h File Reference

Header file of UART HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define | UART_WORDLENGTH_8B ((uint32_t)0x0000)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
#define | IS_UART_WORD_LENGTH(__LENGTH__)
#define | IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define | UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Reports the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Detailed Description

Header file of UART HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_uart_ex.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_usart.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010)
#define | USART_STOPBITS_1 ((uint32_t)0x0000)
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_PARITY_NONE ((uint32_t)0x0000)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | USART_OVERSAMPLING_16 ((uint32_t)0x0000)
#define | USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | USART_CLOCK_DISABLE ((uint32_t)0x0000)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
#define | USART_POLARITY_LOW ((uint32_t)0x0000)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | USART_PHASE_1EDGE ((uint32_t)0x0000)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | USART_LASTBIT_DISABLE ((uint32_t)0x0000)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | USART_FLAG_REACK ((uint32_t)0x00400000)
#define | USART_FLAG_TEACK ((uint32_t)0x00200000)
#define | USART_FLAG_BUSY ((uint32_t)0x00010000)
#define | USART_FLAG_CTS ((uint32_t)0x00000400)
#define | USART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | USART_FLAG_LBDF ((uint32_t)0x00000100)
#define | USART_FLAG_TXE ((uint32_t)0x00000080)
#define | USART_FLAG_TC ((uint32_t)0x00000040)
#define | USART_FLAG_RXNE ((uint32_t)0x00000020)
#define | USART_FLAG_IDLE ((uint32_t)0x00000010)
#define | USART_FLAG_ORE ((uint32_t)0x00000008)
#define | USART_FLAG_NE ((uint32_t)0x00000004)
#define | USART_FLAG_FE ((uint32_t)0x00000002)
#define | USART_FLAG_PE ((uint32_t)0x00000001)
#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_TXE ((uint16_t)0x0727)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_ORE ((uint16_t)0x0300)
#define | USART_IT_NE ((uint16_t)0x0200)
#define | USART_IT_FE ((uint16_t)0x0100)
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_CTSF USART_ICR_CTSCF
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Checks whether the specified USART flag is set or not.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Checks whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified USART interrupt source is enabled.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clears the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_IT_MASK ((uint16_t)0x001F)
USART interruptions flag mask.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Reports the USART clock source.
#define | IS_USART_STOPBITS(__STOPBITS__)
#define | IS_USART_PARITY(__PARITY__)
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
#define | IS_USART_CLOCK(__CLOCK__)
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
#define | IS_USART_LASTBIT(__LASTBIT__)
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00, HAL_USART_STATE_READY = 0x01, HAL_USART_STATE_BUSY = 0x02, HAL_USART_STATE_BUSY_TX = 0x12,
HAL_USART_STATE_BUSY_RX = 0x22, HAL_USART_STATE_BUSY_TX_RX = 0x32, HAL_USART_STATE_TIMEOUT = 0x03, HAL_USART_STATE_ERROR = 0x04
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00, USART_CLOCKSOURCE_PCLK2 = 0x01, USART_CLOCKSOURCE_HSI = 0x02, USART_CLOCKSOURCE_SYSCLK = 0x04,
USART_CLOCKSOURCE_LSE = 0x08, USART_CLOCKSOURCE_UNDEFINED = 0x10
}
USART clock sources definitions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_CheckIdleState (USART_HandleTypeDef *husart)
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in blocking mode To receive synchronous data, dummy data are simultaneously transmitted.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
return the USART state
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_usart.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_usart_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
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Defines
stm32f7xx_hal_usart_ex.h File Reference

Header file of USART HAL Extension module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
#define | __HAL_USART_MASK_COMPUTATION(__HANDLE__)
Computes the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)

Detailed Description

Header file of USART HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_usart_ex.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_wwdg.h File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f7xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 ((uint32_t)0x00000000)
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB
#define | __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
Reset WWDG handle state.
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enables the WWDG peripheral.
#define | __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
Disables the WWDG peripheral.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Gets the selected WWDG's it status.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
Disables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected WWDG's flag status.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clears the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified WWDG interrupt source is enabled or disabled.
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))

Enumerations

enum HAL_WWDG_StateTypeDef {
HAL_WWDG_STATE_RESET = 0x00, HAL_WWDG_STATE_READY = 0x01, HAL_WWDG_STATE_BUSY = 0x02, HAL_WWDG_STATE_TIMEOUT = 0x03,
HAL_WWDG_STATE_ERROR = 0x04
}
WWDG HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_WWDG_DeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG peripheral.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG MSP.
__weak void | HAL_WWDG_MspDeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG MSP.
void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.
HAL_StatusTypeDef | HAL_WWDG_Start (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG.
HAL_StatusTypeDef | HAL_WWDG_Start_IT (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG with interrupt enabled.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
Refreshes the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handles WWDG interrupt request.
HAL_WWDG_StateTypeDef | HAL_WWDG_GetState (WWDG_HandleTypeDef *hwwdg)
Returns the WWDG state.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_wwdg.h.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Defines | Functions | Variables
stm32f7xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32F7xx_HAL_VERSION_MAIN (0x01)
STM32F7xx HAL Driver version number V1.0.3.
#define | __STM32F7xx_HAL_VERSION_SUB1 (0x00)
#define | __STM32F7xx_HAL_VERSION_SUB2 (0x03)
#define | __STM32F7xx_HAL_VERSION_RC (0x00)
#define | __STM32F7xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, and instruction cache through ART accelerator.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.
void | HAL_EnableFMCMemorySwapping (void)
Enables the FMC Memory Mapping Swapping.
void | HAL_DisableFMCMemorySwapping (void)
Disables the FMC Memory Mapping Swapping.

Variables

static __IO uint32_t | uwTick

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Functions
stm32f7xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct without initializing the ADC MSP.
static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitializes the ADCx peripheral registers to their default reset values.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for regular conversion complete.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Disables the interrupt and stop ADC conversion of regular channels.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Gets the converted value from data register of regular channel.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion half DMA transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
Error ADC callback.
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                    ##### ADC Peripheral features #####
  ==============================================================================
  [..]
  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
  (#) Interrupt generation at the end of conversion, end of injected conversion,
      and in case of analog watchdog or overrun events
  (#) Single and continuous conversion modes.
  (#) Scan mode for automatic conversion of channel 0 to channel x.
  (#) Data alignment with in-built data coherency.
  (#) Channel-wise programmable sampling time.
  (#) External trigger option with configurable polarity for both regular and
      injected conversion.
  (#) Dual/Triple mode (on devices with 2 ADCs or more).
  (#) Configurable DMA data storage in Dual/Triple ADC mode.
  (#) Configurable delay between conversions in Dual/Triple interleaved mode.
  (#) ADC conversion type (refer to the datasheets).
  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
      slower speed.
  (#) ADC input range: VREF(minus) = VIN = VREF(plus).
  (#) DMA request generation during regular channel conversion.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
       (##) ADC pins configuration
             (+++) Enable the clock for the ADC GPIOs using the following function:
                   __HAL_RCC_GPIOx_CLK_ENABLE()
             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream.

    *** Configuration of ADC, groups regular/injected, channels parameters ***
  ==============================================================================
  [..]
  (#) Configure the ADC parameters (resolution, data alignment, ...)
      and regular group parameters (conversion trigger, sequencer, ...)
      using function HAL_ADC_Init().

  (#) Configure the channels for regular group parameters (channel number,
      channel rank into sequencer, ..., into regular group)
      using function HAL_ADC_ConfigChannel().

  (#) Optionally, configure the injected group parameters (conversion trigger,
      sequencer, ..., of injected group)
      and the channels for injected group parameters (channel number,
      channel rank into sequencer, ..., into injected group)
      using function HAL_ADCEx_InjectedConfigChannel().

  (#) Optionally, configure the analog watchdog parameters (channels
      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().

  (#) Optionally, for devices with several ADC instances: configure the
      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().

                       *** Execution of ADC conversions ***
  ==============================================================================
  [..]
  (#) ADC driver can be used among three modes: polling, interruption,
      transfer by DMA.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the ADC peripheral using HAL_ADC_Start()
       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
           user can specify the value of timeout according to his end application
       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
       (+) Stop the ADC peripheral using HAL_ADC_Stop()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the ADC peripheral using HAL_ADC_Start_IT()
       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ErrorCallback
       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ErrorCallback
       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()

     *** ADC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in ADC HAL driver.

      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register

     [..]
       (@) You can refer to the ADC HAL driver header file for more useful macros

                      *** Deinitialization of ADC ***
  ==============================================================================
  [..]
  (#) Disable the ADC interface
     (++) ADC clock can be hard reset and disabled at RCC top level.
     (++) Hard reset of ADC peripherals
          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
     (++) ADC clock disable using the equivalent macro/functions as configuration step.
               (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);

  (#) ADC pins configuration
     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()

  (#) Optionally, in case of usage of ADC with interruptions:
     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)

  (#) Optionally, in case of usage of DMA:
        (++) Deinitialize the DMA using function HAL_DMA_DeInit().
        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_adc.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
  • Src
Functions
stm32f7xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | ADC_MultiModeDMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_MultiModeDMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | ADC_MultiModeDMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables the selected ADC software start conversion of the injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for injected conversion complete.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Gets the converted value from data register of injected channel.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Configures the ADC multi-mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
       (##) ADC pins configuration
             (+++) Enable the clock for the ADC GPIOs using the following function:
                   __HAL_RCC_GPIOx_CLK_ENABLE()
             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the ADC DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream.
     (#) Configure the ADC Prescaler, conversion resolution and data alignment
         using the HAL_ADC_Init() function.

     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
         and HAL_ADC_ConfigChannel() functions.

     (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
           user can specify the value of timeout according to his end application
       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()

     *** Multi mode ADCs Regular channels configuration ***
     ======================================================
     [..]
       (+) Select the Multi mode ADC regular channels features (dual or triple mode)
          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_adc_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_can.c File Reference

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Defines | Functions
stm32f7xx_hal_can.c File Reference

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | CAN_TIMEOUT_VALUE 10

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Enable the CAN controller interface clock using
          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.

      (#) CAN pins configuration
        (++) Enable the clock for the CAN GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE()
        (++) Connect and configure the involved CAN pins to AF9 using the
              following function HAL_GPIO_Init()

      (#) Initialize and configure the CAN using HAL_CAN_Init() function.

      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.

      (#) Receive a CAN frame using HAL_CAN_Receive() function.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the CAN peripheral transmission and wait the end of this operation
           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
           according to his end application
       (+) Start the CAN peripheral reception and wait the end of this operation
           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
           according to his end application

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_TxCpltCallback
       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_ErrorCallback

     *** CAN HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in CAN HAL driver.

      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status

     [..]
      (@) You can refer to the CAN HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_can.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cec.c File Reference

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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | CEC_CFGR_FIELDS

Functions

static HAL_StatusTypeDef | CEC_Transmit_IT (CEC_HandleTypeDef *hcec)
Send data in interrupt mode.
static HAL_StatusTypeDef | CEC_Receive_IT (CEC_HandleTypeDef *hcec)
Receive data in interrupt mode.
HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_Transmit (CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
Send data in blocking mode.
HAL_StatusTypeDef | HAL_CEC_Receive (CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
Receive data in blocking mode.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
HAL_StatusTypeDef | HAL_CEC_Receive_IT (CEC_HandleTypeDef *hcec, uint8_t *pData)
Receive data in interrupt mode.
uint32_t | HAL_CEC_GetReceivedFrameSize (CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+++) Enable the clock for the CEC GPIOs.
            (+++) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+++) Configure the CEC interrupt priority.
            (+++) Enable the NVIC CEC IRQ handle.
            (+++) The specific CEC interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                  and receive process.

    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
        in case of Bit Rising Error, Error-Bit generation conditions, device logical
        address and Listen mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

  [..]
    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cec.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cortex.c File Reference

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stm32f7xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M4 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
        function according to the following table.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
    (#) please refer to programming manual for details in how to configure priority.

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest preemption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32f7xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_cortex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc.c File Reference

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Functions
stm32f7xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initialize the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
 ===============================================================================
                     ##### CRC How to use this driver #####
 ===============================================================================
    [..]

    (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();

    (#) Initialize CRC calculator
         (++) specify generating polynomial (IP default or non-default one)
         (++) specify initialization value (IP default or non-default one)
         (++) specify input data format
         (++) specify input or output data inversion mode if any

    (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
        input data buffer starting with the previously computed CRC as
        initialization value

    (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
        input data buffer starting with the defined initialization value
        (default or non-default) to initiate CRC calculation
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_crc.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc_ex.c File Reference

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Functions
stm32f7xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initializes the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015 This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization/de-initialization functions
  ==============================================================================
                    ##### CRC specific features #####
  ==============================================================================
  [..]
  (#) Polynomial configuration.
  (#) Input data reverse mode.
  (#) Output data reverse mode.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_crc_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac.c File Reference

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Functions
stm32f7xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitializes the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initializes the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitializes the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    The device integrates two 12-bit Digital Analog Converters that can
    be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output
      (#) DAC channel2 with DAC_OUT2 (PA5) as output

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_Pin9) must be configured in input mode.

      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
         (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       DAC_OUTx = VREF+ * DOR / 4095
       with  DOR is the Data Output Register
          VEF+ is the input voltage reference (refer to the device datasheet)
        e.g. To set DAC_OUT1 to 0.7V, use
          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests  ***
       =====================
       [..]
       A DMA1 request can be generated when an external trigger (but not
       a software trigger) occurs if DMA1 requests are enabled using
       HAL_DAC_Start_DMA()
       [..]
       DMA1 requests are mapped as following:
         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
             already configured
         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
             already configured

    -@- For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extension Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dac.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac_ex.c File Reference

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Functions
stm32f7xx_hal_dac_ex.c File Reference

Extended DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dac_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi.c File Reference

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Defines | Functions
stm32f7xx_hal_dcmi.c File Reference

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */

Functions

static void | DCMI_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DCMI_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
__weak HAL_StatusTypeDef | HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DCMI_DeInit (DCMI_HandleTypeDef *hdcmi)
Deinitializes the DCMI peripheral registers to their default reset values.
__weak void | HAL_DCMI_MspInit (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI MSP.
__weak void | HAL_DCMI_MspDeInit (DCMI_HandleTypeDef *hdcmi)
DeInitializes the DCMI MSP.
HAL_StatusTypeDef | HAL_DCMI_Start_DMA (DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
Enables DCMI DMA request and enables DCMI capture.
HAL_StatusTypeDef | HAL_DCMI_Stop (DCMI_HandleTypeDef *hdcmi)
Disable DCMI DMA request and Disable DCMI capture.
void | HAL_DCMI_IRQHandler (DCMI_HandleTypeDef *hdcmi)
Handles DCMI interrupt request.
__weak void | HAL_DCMI_ErrorCallback (DCMI_HandleTypeDef *hdcmi)
Error DCMI callback.
__weak void | HAL_DCMI_LineEventCallback (DCMI_HandleTypeDef *hdcmi)
Line Event callback.
__weak void | HAL_DCMI_VsyncEventCallback (DCMI_HandleTypeDef *hdcmi)
VSYNC Event callback.
__weak void | HAL_DCMI_FrameEventCallback (DCMI_HandleTypeDef *hdcmi)
Frame Event callback.
HAL_StatusTypeDef | HAL_DCMI_ConfigCROP (DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
Configure the DCMI CROP coordinate.
HAL_StatusTypeDef | HAL_DCMI_DisableCROP (DCMI_HandleTypeDef *hdcmi)
Disable the Crop feature.
HAL_StatusTypeDef | HAL_DCMI_EnableCROP (DCMI_HandleTypeDef *hdcmi)
Enable the Crop feature.
HAL_DCMI_StateTypeDef | HAL_DCMI_GetState (DCMI_HandleTypeDef *hdcmi)
Return the DCMI state.
uint32_t | HAL_DCMI_GetError (DCMI_HandleTypeDef *hdcmi)
Return the DCMI error code.

Detailed Description

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
      The sequence below describes how to use this driver to capture image
      from a camera module connected to the DCMI Interface.
      This sequence does not take into account the configuration of the
      camera module, which should be made before to configure and enable
      the DCMI to capture images.

    (#) Program the required configuration through following parameters:
        horizontal and vertical polarity, pixel clock polarity, Capture Rate,
        Synchronization Mode, code of the frame delimiter and data width
        using HAL_DCMI_Init() function.

    (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
        register to the destination memory buffer.

    (#) Program the required configuration through following parameters:
        DCMI mode, destination memory Buffer address and the data length
        and enable capture using HAL_DCMI_Start_DMA() function.

    (#) Optionally, configure and Enable the CROP feature to select a rectangular
        window from the received image using HAL_DCMI_ConfigCrop()
        and HAL_DCMI_EnableCROP() functions

    (#) The capture can be stopped using HAL_DCMI_Stop() function.

    (#) To control DCMI state you can use the function HAL_DCMI_GetState().

     *** DCMI HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DCMI HAL driver.

      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.

     [..]
       (@) You can refer to the DCMI HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dcmi.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi_ex.c File Reference

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Functions
stm32f7xx_hal_dcmi_ex.c File Reference

DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_DCMI_Init (DCMI_HandleTypeDef *hdcmi)
Initializes the DCMI according to the specified parameters in the DCMI_InitTypeDef and create the associated handle.

Detailed Description

DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
               ##### DCMI peripheral extension features  #####
  ==============================================================================

  [..]  Support of Black and White cameras

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to manage the Black and White feature
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dcmi_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma.c File Reference

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Data Structures | Defines | Functions
stm32f7xx_hal_dma.c File Reference

DMA HAL module driver. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Data Structures

struct | DMA_Base_Registers

Defines

#define | HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015 This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Stream
       (except for internal SRAM/FLASH memories: no initialization is
       necessary) please refer to Reference manual for connection between peripherals
       and DMA requests .

   (#) For a given Stream, program the required configuration through the following parameters:
       Transfer Direction, Source and Destination data formats,
       Circular, Normal or peripheral flow control mode, Stream Priority level,
       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred. In this
              case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e a member of DMA handle structure).
    [..]
     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
         detection.

     (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
           Half-Word data size for the peripheral to access its data register and set Word data size
           for the Memory to gain in access time. Each two half words will be packed and written in
           a single access to a Word in the Memory).

     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
           and Destination. In this case the Peripheral Data Size will be applied to both Source
           and Destination.

     *** DMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA HAL driver.

      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dma.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma2d.c File Reference

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Defines | Functions
stm32f7xx_hal_dma2d.c File Reference

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */
#define | HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */

Functions

static void | DMA2D_SetConfig (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D Transfer parameter.
HAL_StatusTypeDef | HAL_DMA2D_Init (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
__weak void | HAL_DMA2D_MspInit (DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
__weak void | HAL_DMA2D_MspDeInit (DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
HAL_StatusTypeDef | HAL_DMA2D_Start (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Start_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_BlendingStart_IT (DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA2D_Abort (DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Suspend (DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_Resume (DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
HAL_StatusTypeDef | HAL_DMA2D_PollForTransfer (DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
void | HAL_DMA2D_IRQHandler (DMA2D_HandleTypeDef *hdma2d)
Handles DMA2D interrupt request.
HAL_StatusTypeDef | HAL_DMA2D_ConfigLayer (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA2D_ConfigCLUT (DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_EnableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_DisableCLUT (DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Disable the DMA2D CLUT Transfer.
HAL_StatusTypeDef | HAL_DMA2D_ProgramLineEvent (DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Define the configuration of the line watermark .
HAL_DMA2D_StateTypeDef | HAL_DMA2D_GetState (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
uint32_t | HAL_DMA2D_GetError (DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.

Detailed Description

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Program the required configuration through following parameters:
          the Transfer Mode, the output color mode and the output offset using
          HAL_DMA2D_Init() function.

      (#) Program the required configuration through following parameters:
          the input color mode, the input color, input alpha value, alpha mode
          and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
          or/and background layer.

     *** Polling mode IO operation ***
     =================================
    [..]
       (+) Configure the pdata, Destination and data length and Enable
           the transfer using HAL_DMA2D_Start()
       (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
           user can specify the value of timeout according to his end application.

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (#) Configure the pdata, Destination and data length and Enable
           the transfer using HAL_DMA2D_Start_IT()
       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
           add his own function by customization of function pointer XferCpltCallback and
           XferErrorCallback (i.e a member of DMA2D handle structure).

         -@-   In Register-to-Memory transfer mode, the pdata parameter is the register
               color, in Memory-to-memory or memory-to-memory with pixel format
               conversion the pdata is the source address.

         -@-   Configure the foreground source address, the background source address,
               the Destination and data length and Enable the transfer using
               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
               in interrupt mode.

         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
               are used if the memory to memory with blending transfer mode is selected.

      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
          HAL_DMA2D_EnableCLUT() functions.

      (#) Optionally, configure and enable LineInterrupt using the following function:
          HAL_DMA2D_ProgramLineEvent().

      (#) The transfer can be suspended, continued and aborted using the following
          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().

      (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()

     *** DMA2D HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA2D HAL driver :

      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
      (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA2D HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dma2d.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma_ex.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Functions
stm32f7xx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:
   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.

     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_dma_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_eth.c File Reference

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Defines | Functions
stm32f7xx_hal_eth.c File Reference

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
#define | AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */

Functions

static void | ETH_MACDMAConfig (ETH_HandleTypeDef *heth, uint32_t err)
Configures Ethernet MAC and DMA with default parameters.
static void | ETH_MACAddressConfig (ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
Configures the selected MAC address.
static void | ETH_MACReceptionEnable (ETH_HandleTypeDef *heth)
Enables the MAC reception.
static void | ETH_MACReceptionDisable (ETH_HandleTypeDef *heth)
Disables the MAC reception.
static void | ETH_MACTransmissionEnable (ETH_HandleTypeDef *heth)
Enables the MAC transmission.
static void | ETH_MACTransmissionDisable (ETH_HandleTypeDef *heth)
Disables the MAC transmission.
static void | ETH_DMATransmissionEnable (ETH_HandleTypeDef *heth)
Enables the DMA transmission.
static void | ETH_DMATransmissionDisable (ETH_HandleTypeDef *heth)
Disables the DMA transmission.
static void | ETH_DMAReceptionEnable (ETH_HandleTypeDef *heth)
Enables the DMA reception.
static void | ETH_DMAReceptionDisable (ETH_HandleTypeDef *heth)
Disables the DMA reception.
static void | ETH_FlushTransmitFIFO (ETH_HandleTypeDef *heth)
Clears the ETHERNET transmit FIFO.
HAL_StatusTypeDef | HAL_ETH_Init (ETH_HandleTypeDef *heth)
Initializes the Ethernet MAC and DMA according to default parameters.
HAL_StatusTypeDef | HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
De-Initializes the ETH peripheral.
HAL_StatusTypeDef | HAL_ETH_DMATxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
Initializes the DMA Tx descriptors in chain mode.
HAL_StatusTypeDef | HAL_ETH_DMARxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
Initializes the DMA Rx descriptors in chain mode.
__weak void | HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
__weak void | HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
HAL_StatusTypeDef | HAL_ETH_TransmitFrame (ETH_HandleTypeDef *heth, uint32_t FrameLength)
Sends an Ethernet frame.
HAL_StatusTypeDef | HAL_ETH_GetReceivedFrame (ETH_HandleTypeDef *heth)
Checks for received frames.
HAL_StatusTypeDef | HAL_ETH_GetReceivedFrame_IT (ETH_HandleTypeDef *heth)
Gets the Received frame in interrupt mode.
void | HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
__weak void | HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
__weak void | HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
__weak void | HAL_ETH_ErrorCallback (ETH_HandleTypeDef *heth)
Ethernet transfer error callbacks.
HAL_StatusTypeDef | HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
Reads a PHY register.
HAL_StatusTypeDef | HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
Writes to a PHY register.
HAL_StatusTypeDef | HAL_ETH_Start (ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_Stop (ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
HAL_StatusTypeDef | HAL_ETH_ConfigMAC (ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
Set ETH MAC Configuration.
HAL_StatusTypeDef | HAL_ETH_ConfigDMA (ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
Sets ETH DMA Configuration.
HAL_ETH_StateTypeDef | HAL_ETH_GetState (ETH_HandleTypeDef *heth)
Return the ETH HAL state.

Detailed Description

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      (#)Declare a ETH_HandleTypeDef handle structure, for example:
         ETH_HandleTypeDef  heth;

      (#)Fill parameters of Init structure in heth handle

      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)

      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
          (##) Enable the Ethernet interface clock using
               (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
               (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
               (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();

          (##) Initialize the related GPIO clocks
          (##) Configure Ethernet pin-out
          (##) Configure Ethernet NVIC interrupt (IT mode)

      (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
          (##) HAL_ETH_DMATxDescListInit(); for Transmission process
          (##) HAL_ETH_DMARxDescListInit(); for Reception process

      (#)Enable MAC and DMA transmission and reception:
          (##) HAL_ETH_Start();

      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
         the frame to MAC TX FIFO:
         (##) HAL_ETH_TransmitFrame();

      (#)Poll for a received frame in ETH RX DMA Descriptors and get received
         frame parameters
         (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)

      (#) Get a received frame when an ETH RX interrupt occurs:
         (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)

      (#) Communicate with external PHY device:
         (##) Read a specific register from the PHY
              HAL_ETH_ReadPHYRegister();
         (##) Write data to a specific RHY register:
              HAL_ETH_WritePHYRegister();

      (#) Configure the Ethernet MAC after ETH peripheral initialization
          HAL_ETH_ConfigMAC(); all MAC parameters should be filled.

      (#) Configure the Ethernet DMA after ETH peripheral initialization
          HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_eth.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash.c File Reference

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Defines | Functions | Variables
stm32f7xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program a double word (64-bit) at a specified address.
static void | FLASH_Program_Word (uint32_t Address, uint32_t Data)
Program word (32-bit) at a specified address.
static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_Program_Byte (uint32_t Address, uint8_t Data)
Program byte (8-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
       prefetch and cache lines.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Prefetch on I-Code
      (+) 64 cache lines of 128 bits on I-Code
      (+) 8 cache lines of 128 bits on D-Code

                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32F7xx devices.

      (#) FLASH Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: byte, half word, word and double word
           (++) There Two modes of programming :
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions :
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Wait for last FLASH operation according to its status
           (++) Get error flag status by calling HAL_SetErrorCode()
    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the Instruction cache and the Data cache
       (+) Reset the Instruction cache and the Data cache
       (+) Enable/Disable the FLASH interrupts
       (+) Monitor the FLASH flags status
    [..]
    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
        (HCLK) must be at least 1MHz.
    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
        a Flash memory operation.
    (@) Any attempt to read the Flash memory while it is being written or erased, causes the
        bus to stall. Read operations are processed correctly once the program operation has
        completed. This means that code or data fetches cannot be performed while a write/erase
        operation is ongoing.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_flash.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash_ex.c File Reference

  • File List
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Defines | Functions | Variables
stm32f7xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */

Functions

static void | FLASH_MassErase (uint8_t VoltageRange)
Full erase of FLASH memory sectors.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WRPSector)
Enable the write protection of the desired bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WRPSector)
Disable the write protection of the desired bank1 or bank 2 sectors.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t Level)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
static HAL_StatusTypeDef | FLASH_OB_BOR_LevelConfig (uint8_t Level)
Set the BOR Level.
static HAL_StatusTypeDef | FLASH_OB_BootAddressConfig (uint32_t BootOption, uint32_t Address)
Configure Boot base address.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static uint32_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint8_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
static uint32_t | FLASH_OB_GetBootAddress (uint32_t BootOption)
Configure Boot base address.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                   ##### Flash Extension features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and
       devices contains the following additional features

       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
           capability (RWW)
       (+) Dual bank memory organization
       (+) PCROP protection for all banks

                      ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32F7xx devices. It includes
      (#) FLASH Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase sector, erase all sectors
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
           (++) Set/Reset the write protection
           (++) Set the Read protection Level
           (++) Set the BOR level
           (++) Program the user Option Bytes
      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
       (++) Extended space (bank 2) erase function
       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
       (++) Dual Boot activation
       (++) Write protection configuration for bank 2
       (++) PCROP protection configuration and control for both banks
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_flash_ex.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_gpio.c File Reference

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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE ((uint32_t)0x00000003)
#define | EXTI_MODE ((uint32_t)0x10000000)
#define | GPIO_MODE_IT ((uint32_t)0x00010000)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000)
#define | RISING_EDGE ((uint32_t)0x00100000)
#define | FALLING_EDGE ((uint32_t)0x00200000)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define | GPIO_NUMBER ((uint32_t)16)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
  in several modes:
  (+) Input mode
  (+) Analog mode
  (+) Output mode
  (+) Alternate function mode
  (+) External interrupt/event lines

  [..]
  During and just after reset, the alternate functions and external interrupt
  lines are not active and the I/O ports are configured in input floating mode.

  [..]
  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
  activated or not.

  [..]
  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
  type and the IO speed can be selected depending on the VDD value.

  [..]
  All ports have external interrupt/event capability. To use external interrupt
  lines, the port must be configured in input mode. All available GPIO pins are
  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

  [..]
  The external interrupt/event controller consists of up to 23 edge detectors
  (16 lines are connected to GPIO) for generating event/interrupt requests (each
  input line can be independently configured to select the type (interrupt or event)
  and the corresponding trigger event (rising or falling or both). Each line can
  also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_gpio.c.

Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hcd.c File Reference

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Functions
stm32f7xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.
HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macros
             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)

        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_hcd.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c.c File Reference

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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
#define | I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define | I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define | I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAMemTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Write process complete callback.
static void | I2C_DMAMemReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Read process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_MasterTransmit_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Master Transmit Mode.
static HAL_StatusTypeDef | I2C_MasterReceive_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Master Receive Mode.
static HAL_StatusTypeDef | I2C_SlaveTransmit_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Slave Transmit Mode.
static HAL_StatusTypeDef | I2C_SlaveReceive_ISR (I2C_HandleTypeDef *hi2c)
Handle Interrupt Flags Slave Receive Mode.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callbacks.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callbacks.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callbacks.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callbacks.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callbacks.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Returns the I2C state.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx Stream
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_i2c.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
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Functions
stm32f7xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configures I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configures I2C Digital noise filter.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32L4XX
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to:
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_i2c_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2s.c File Reference

  • File List
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  • Drivers
  • STM32F7xx_HAL_Driver
  • Src
Functions
stm32f7xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static uint32_t | I2S_GetClockFreq (I2S_HandleTypeDef *hi2s)
Get I2S Input Clock based on I2S source clock selection.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio stream playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follows:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Channel.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
   -@- Make sure that either:
       (+@) I2S clock is configured based on SYSCLK or
       (+@) External clock source is configured after setting correctly
            the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.

   (#) Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()

   *** I2S HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_i2s.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_irda.c File Reference

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Defines | Functions
stm32f7xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | TEACK_REACK_TIMEOUT 1000
#define | HAL_IRDA_TXDMA_TIMEOUTVALUE 22000
#define | IRDA_CR1_FIELDS

Functions

static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA Tx transfer completed callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA Rx Transfer completed callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles IRDA Communication Timeout.
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure.
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) IRDA pins configuration:
            (+++) Enable the clock for the IRDA GPIOs.
            (+++) Configure these IRDA pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
        and Mode(Receiver/Transmitter) in the hirda Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
            by calling the customized HAL_IRDA_MspInit() API.
    -@@- The specific IRDA interrupts (Transmission complete interrupt,
        RXNE interrupt and Error Interrupts) will be managed using the macros
        __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_IRDA_ErrorCallback

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_IRDA_ErrorCallback

    *** IRDA HAL driver macros list ***
    ===================================
    [..]
      Below the list of most used macros in IRDA HAL driver.

     (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
     (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
     (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
     (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
     (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
     (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt

     (@) You can refer to the IRDA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_irda.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_iwdg.c File Reference

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Defines | Functions
stm32f7xx_hal_iwdg.c File Reference

IWDG HAL module driver. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.
__weak void | HAL_IWDG_MspInit (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG MSP.
HAL_StatusTypeDef | HAL_IWDG_Start (IWDG_HandleTypeDef *hiwdg)
Starts the IWDG.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refreshes the IWDG.
HAL_IWDG_StateTypeDef | HAL_IWDG_GetState (IWDG_HandleTypeDef *hiwdg)
Returns the IWDG state.

Detailed Description

IWDG HAL module driver.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015 This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
    [..]
    (+) The IWDG can be started by either software or hardware (configurable
         through option byte).

    (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
         thus stays active even if the main clock fails.
         Once the IWDG is started, the LSI is forced ON and cannot be disabled
         (LSI cannot be disabled too), and the counter starts counting down from
         the reset value of 0xFFF. When it reaches the end of count value (0x000)
         a system reset is generated.

    (+) The IWDG counter should be refreshed at regular intervals, otherwise the
         watchdog generates an MCU reset when the counter reaches 0.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
         reset occurs.

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM16 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
    [..]
    If Window option is disabled

      (+) Use IWDG using HAL_IWDG_Init() function to :
         (++) Enable write access to IWDG_PR, IWDG_RLR.
         (++) Configure the IWDG prescaler, counter reload value.
              This reload value will be loaded in the IWDG counter each time the counter
              is reloaded, then the IWDG will start counting down from this value.
      (+) Use IWDG using HAL_IWDG_Start() function to :
         (++) Reload IWDG counter with value defined in the IWDG_RLR register.
         (++) Start the IWDG, when the IWDG is used in software mode (no need
              to enable the LSI, it will be enabled by hardware).
      (+) Then the application program must refresh the IWDG counter at regular
          intervals during normal operation to prevent an MCU reset, using
          HAL_IWDG_Refresh() function.
    [..]
    if Window option is enabled:

      (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
      (+) Use IWDG using HAL_IWDG_Init() function to :
         (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
         (++) Configure the IWDG prescaler, reload value and window value.
      (+) Then the application program must refresh the IWDG counter at regular
          intervals during normal operation to prevent an MCU reset, using
          HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver.

      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
      (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
      (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
      (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_iwdg.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_lptim.c File Reference

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Functions
stm32f7xx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
         (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (##) The instance: LPTIM1.
         (##) Clock: the counter clock.
                 - Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
                 - Prescaler: select the clock divider.
         (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
                 - Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
                 - SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (##) Trigger: How the counter start.
                 - Source: trigger can be software or one of the hardware triggers.
                 - ActiveEdge : only for hardware trigger.
                 - SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (##) OutputPolarity : 2 opposite polarities are possibles.
         (##) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.

      (#)Six modes are available:

         (##) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (##) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (##) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (##) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode.

         (##) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (##) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

       (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_lptim.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nand.c File Reference

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Functions
stm32f7xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
NAND MSP Init.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
NAND MSP DeInit.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Write_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory.
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory.
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enables dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disables dynamically FMC_NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disables dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
return the NAND state

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC/FSMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_nand.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nor.c File Reference

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Defines | Functions
stm32f7xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
NOR MSP Init.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
NOR MSP DeInit.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Returns the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Reads a half-word buffer from the NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Writes a half-word buffer to the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enables dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disables dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
return the NOR controller state
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Returns the NOR operation status.

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_nor.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd.c File Reference

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Defines | Functions
stm32f7xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
Check FIFO for the next packet to be loaded.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handle PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pcd.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd_ex.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Functions
stm32f7xx_hal_pcd_ex.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM Feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
DeActivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pcd_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr.c File Reference

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Defines | Functions
stm32f7xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000)
#define | PVD_MODE_EVT ((uint32_t)0x00020000)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002)
#define | PWR_EWUP_MASK ((uint32_t)0x00003F00)

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pwr.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr_ex.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | PWR_OVERDRIVE_TIMEOUT_VALUE 1000
#define | PWR_UDERDRIVE_TIMEOUT_VALUE 1000
#define | PWR_BKPREG_TIMEOUT_VALUE 1000
#define | PWR_VOSRDY_TIMEOUT_VALUE 1000

Functions

HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enables the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disables the Backup Regulator.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enables the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disables the Flash Power Down in Stop mode.
void | HAL_PWREx_EnableMainRegulatorLowVoltage (void)
Enables Main Regulator low voltage mode.
void | HAL_PWREx_DisableMainRegulatorLowVoltage (void)
Disables Main Regulator low voltage mode.
void | HAL_PWREx_EnableLowRegulatorLowVoltage (void)
Enables Low Power Regulator low voltage mode.
void | HAL_PWREx_DisableLowRegulatorLowVoltage (void)
Disables Low Power Regulator low voltage mode.
HAL_StatusTypeDef | HAL_PWREx_EnableOverDrive (void)
Activates the Over-Drive mode.
HAL_StatusTypeDef | HAL_PWREx_DisableOverDrive (void)
Deactivates the Over-Drive mode.
HAL_StatusTypeDef | HAL_PWREx_EnterUnderDriveSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters in Under-Drive STOP mode.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Returns Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configures the main internal regulator output voltage.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_pwr_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_qspi.c File Reference

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Defines | Functions
stm32f7xx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)
#define | IS_QSPI_FUNCTIONAL_MODE(MODE)

Functions

static void | QSPI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process half complete callback.
static void | QSPI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process half complete callback.
static void | QSPI_DMAError (DMA_HandleTypeDef *hdma)
DMA QSPI communication error callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function wait a flag state until time out.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
This function configures the communication registers.
HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initializes the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
DeInitializes the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
QSPI MSP Init.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
QSPI MSP DeInit.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
This function handles QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Sets the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Sets the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Sends an amount of data in non blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receives an amount of data in non blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callbacks.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callbacks.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callbacks.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callbacks.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callbacks.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callbacks.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callbacks.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callbacks.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callbacks.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and the size.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    ==================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_qspi.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Defines | Functions | Variables
stm32f7xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Variables

const uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
      and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
          all peripherals mapped on these busses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB busses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
          after the clock enable bit is set on the hardware register
      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
          after the clock enable bit is set on the hardware register

    [..]
      Implemented Workaround:
      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rcc.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc_ex.c File Reference

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Defines | Functions
stm32f7xx_hal_rcc_ex.c File Reference

Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
#define | PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_PeriphCLKInitTypeDef according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for a given peripheral(SAI..)

Detailed Description

Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rcc_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rng.c File Reference

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Defines | Functions
stm32f7xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rng.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc.c File Reference

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Functions
stm32f7xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
              ##### Backup Domain Operating Condition #####
  ==============================================================================
  [..] The real-time clock (RTC), the RTC backup registers, and the backup
       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
       VDD supply is powered off.
       To retain the content of the RTC backup registers, backup SRAM, and supply
       the RTC when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
       off, the VBAT pin powers the following blocks:
    (#) The RTC
    (#) The LSE oscillator
    (#) The backup SRAM when the low power backup regulator is enabled
    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)

  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
       the following pins are available:
    (#) PC14 and PC15 can be used as either GPIO or LSE pins
    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin

  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
       because VDD is not present), the following pins are available:
    (#) PC14 and PC15 can be used as LSE pins only
    (#) PC13 can be used as the RTC_AF1 pin
    (#) PI8 can be used as the RTC_AF2 pin
    (#) PC1 can be used as the RTC_AF3 pin

                   ##### Backup Domain Reset #####
  ==================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values. The BKPSRAM is not affected by this reset. The only
       way to reset the BKPSRAM is through the Flash interface by requesting
       a protection level change from 1 to 0.
  [..] A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.

                   ##### Backup Domain Access #####
  ==================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.
  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Enable the Power Controller (PWR) APB1 interface clock using the
        __HAL_RCC_PWR_CLK_ENABLE() function.
    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.

                  ##### How to use this driver #####
  ==================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
  ==================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
       is LSE or LSI.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rtc.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc_ex.c File Reference

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Functions
stm32f7xx_hal_rtc_ex.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Sets Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer in interrupt mode
        using the HAL_RTC_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTC_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
        function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
        Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper
        with interrupt mode using HAL_RTC_SetTamper_IT() function.
    (+) The default configuration of the Tamper erases the backup registers. To avoid
        erase, enable the NoErase field on the RTC_TAMPCR register.

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
        function.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_rtc_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai.c File Reference

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Defines | Enumerations | Functions
stm32f7xx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_FIFO_SIZE 8
#define | SAI_DEFAULT_TIMEOUT 4
#define | SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
#define | CR1_CLEAR_MASK ((uint32_t)0xFF04C010)
#define | FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)
#define | SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)
#define | SAI_TIMEOUT_VALUE 10

Enumerations

enum | SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (SAI_HandleTypeDef *hsai, uint32_t mode)
return the interrupt flag to set according the SAI setup
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
disable the SAI and wait the disabling
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initializes the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initializes the SAI according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitializes the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
SAI MSP Init.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
SAI MSP DeInit.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmits an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receives an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pauses the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resumes the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stops the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disbaled the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmits an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receives an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
This function handles SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callbacks.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callbacks.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callbacks.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callbacks.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callbacks.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Returns the SAI state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
 ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure.
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

   (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_SAI_Init() function.

   -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
       will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
       inside the transmit and receive process.

  [..]
   (@) SAI Clock Source, the configuration is managed through RCCEx_PeriphCLKConfig()
            function in the HAL RCC drivers
  [..]
   (@) Make sure that either:
       (+@) I2S PLL is configured or
       (+@) SAI PLL is configured or
       (+@) External clock source is configured after setting correctly
            the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@)  First bit Offset <= (SLOT size - Data size)
        (+@)  Data size <= SLOT size
        (+@)  Number of SLOT x SLOT size = Frame length
        (+@)  The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
     Three operation modes are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT()
     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT()
     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_RxCpltCallback
     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SAI_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA()
     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA()
     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_RxCpltCallback
     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SAI_ErrorCallback
     (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
     (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
     (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

   *** SAI HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in USART HAL driver :

      (+) __HAL_SAI_ENABLE: Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE: Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sai.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
  • Src
Functions
stm32f7xx_hal_sai_ex.c File Reference

SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

void | SAI_BlockSynchroConfig (SAI_HandleTypeDef *hsai)
Configure SAI Block synchronization mode.
uint32_t | SAI_GetInputClock (SAI_HandleTypeDef *hsai)
Get SAI Input Clock based on SAI source clock selection.

Detailed Description

SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
               ##### SAI peripheral extension features  #####
  ==============================================================================

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to manage several sources to clock SAI
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sai_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sd.c File Reference

  • File List
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  • Drivers
  • STM32F7xx_HAL_Driver
  • Src
Defines | Functions
stm32f7xx_hal_sd.c File Reference

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
SDMMC Data block size.
#define | SDMMC_STATIC_FLAGS
SDMMC Static flags, Timeout, FIFO Address.
#define | SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)
#define | SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
Mask for errors Card Status R1 (OCR Register)
#define | SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define | SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define | SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define | SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define | SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define | SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define | SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define | SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define | SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define | SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define | SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define | SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define | SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define | SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define | SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define | SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define | SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define | SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define | SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define | SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
Masks for R6 Response.
#define | SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define | SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define | SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define | SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define | SD_STD_CAPACITY ((uint32_t)0x00000000)
#define | SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define | SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define | SD_ALLZERO ((uint32_t)0x00000000)
#define | SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define | SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define | SD_CARD_LOCKED ((uint32_t)0x02000000)
#define | SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define | SD_0TO7BITS ((uint32_t)0x000000FF)
#define | SD_8TO15BITS ((uint32_t)0x0000FF00)
#define | SD_16TO23BITS ((uint32_t)0x00FF0000)
#define | SD_24TO31BITS ((uint32_t)0xFF000000)
#define | SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define | SD_HALFFIFO ((uint32_t)0x00000008)
#define | SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define | SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
Command Class Supported.
#define | SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define | SD_CCCC_ERASE ((uint32_t)0x00000020)
#define | SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
Following commands are SD Card Specific commands.

Functions

static HAL_SD_ErrorTypedef | SD_Initialize_Cards (SD_HandleTypeDef *hsd)
Initializes all cards or single card as the case may be Card(s) come into standby state.
static HAL_SD_ErrorTypedef | SD_Select_Deselect (SD_HandleTypeDef *hsd, uint64_t addr)
Selects od Deselects the corresponding card.
static HAL_SD_ErrorTypedef | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static HAL_SD_ErrorTypedef | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static HAL_SD_ErrorTypedef | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static HAL_SD_CardStateTypedef | SD_GetState (SD_HandleTypeDef *hsd)
Returns the SD current state.
static HAL_SD_ErrorTypedef | SD_IsCardProgramming (SD_HandleTypeDef *hsd, uint8_t *pStatus)
Checks if the SD card is in programming state.
static HAL_SD_ErrorTypedef | SD_CmdError (SD_HandleTypeDef *hsd)
Checks for error conditions for CMD0.
static HAL_SD_ErrorTypedef | SD_CmdResp1Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD)
Checks for error conditions for R1 response.
static HAL_SD_ErrorTypedef | SD_CmdResp7Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R7 response.
static HAL_SD_ErrorTypedef | SD_CmdResp3Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R3 (OCR) response.
static HAL_SD_ErrorTypedef | SD_CmdResp2Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R2 (CID or CSD) response.
static HAL_SD_ErrorTypedef | SD_CmdResp6Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
Checks for error conditions for R6 (RCA) response.
static HAL_SD_ErrorTypedef | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static void | SD_DMA_RxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx callback.
static void | SD_DMA_RxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Rx callback.
static void | SD_DMA_TxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Tx callback.
static void | SD_DMA_TxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Tx callback.
HAL_SD_ErrorTypedef | HAL_SD_Init (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Allows to write block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_CheckReadOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data read transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_CheckWriteOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data write transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_XferCpltCallback (SD_HandleTypeDef *hsd)
SD end of transfer callback.
__weak void | HAL_SD_XferErrorCallback (SD_HandleTypeDef *hsd)
SD Transfer Error callback.
__weak void | HAL_SD_DMA_RxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Rx callback in non blocking mode.
__weak void | HAL_SD_DMA_RxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx error callback.
__weak void | HAL_SD_DMA_TxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Tx callback in non blocking mode.
__weak void | HAL_SD_DMA_TxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete error Tx callback.
HAL_SD_ErrorTypedef | HAL_SD_Get_CardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
Returns information about specific card.
HAL_SD_ErrorTypedef | HAL_SD_WideBusOperation_Config (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_ErrorTypedef | HAL_SD_StopTransfer (SD_HandleTypeDef *hsd)
Aborts an ongoing data transfer.
HAL_SD_ErrorTypedef | HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
HAL_SD_ErrorTypedef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Returns the current SD card's status.
HAL_SD_TransferStateTypedef | HAL_SD_GetStatus (SD_HandleTypeDef *hsd)
Gets the current sd card data status.
HAL_SD_ErrorTypedef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
Gets the SD card status.

Detailed Description

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
    the user in HAL_SD_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDMMC memories which uses the HAL
    SDMMC driver functions to interface with SD and uSD cards devices.
    It is used as follows:

    (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
        (##) SDMMC pins configuration for SD card
            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
             and HAL_SD_WriteBlocks_DMA() APIs).
            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
            (+++) Configure the SDMMC and DMA interrupt priorities using functions
                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT()
                  and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.
            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()
                  and __HAL_SD_SDMMC_CLEAR_IT()
    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization

  *** SD Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
    the SD Card and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
        type (Standard Capacity or High Capacity). You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        The SD Card frequency (SDMMC_CK) is computed as follows:

           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)

        In initialization mode and according to the SD Card standard,
        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.

    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
        structure. This structure provide also ready computed SD Card capacity
        and Block size.

        -@- These information are stored in SD handle structure in case of future use.

    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
        frequency is set to 24MHz. You can change or adapt this frequency by adjusting
        the "ClockDiv" field.
        In transfer mode and according to the SD Card standard, make sure that the
        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
        To be able to use a frequency higher than 24MHz, you should use the SDMMC
        peripheral in bypass mode. Refer to the corresponding reference manual
        for more details.

    (#) Select the corresponding SD Card according to the address read with the step 2.

    (#) Configure the SD Card in wide bus mode: 4-bits data.

  *** SD Card Read operation ***
  ==============================
  [..]
    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
        that the read transfer is done correctly in both DMA and SD sides.

  *** SD Card Write operation ***
  ===============================
  [..]
    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 byte).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
        that the write transfer is done correctly in both DMA and SD sides.

  *** SD card status ***
  ======================
  [..]
    (+) At any time, you can check the SD Card status and get the SD card state
        by using the HAL_SD_GetStatus() function. This function checks first if the
        SD card is still connected and then get the internal SD Card transfer state.
    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
        function.

  *** SD HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in SD HAL driver.

    (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device
    (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device
    (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer
    (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer
    (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt
    (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt
    (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not
    (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags

    (@) You can refer to the SD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sd.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sdram.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Functions
stm32f7xx_hal_sdram.c File Reference

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SDRAM_Init (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
Performs the SDRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SDRAM_DeInit (SDRAM_HandleTypeDef *hsdram)
Perform the SDRAM device initialization sequence.
__weak void | HAL_SDRAM_MspInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP Init.
__weak void | HAL_SDRAM_MspDeInit (SDRAM_HandleTypeDef *hsdram)
SDRAM MSP DeInit.
void | HAL_SDRAM_IRQHandler (SDRAM_HandleTypeDef *hsdram)
This function handles SDRAM refresh error interrupt request.
__weak void | HAL_SDRAM_RefreshErrorCallback (SDRAM_HandleTypeDef *hsdram)
SDRAM Refresh error callback.
__weak void | HAL_SDRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SDRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SDRAM_Read_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_8b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_16b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit data buffer from the SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Write_32b (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit data buffer to SDRAM memory.
HAL_StatusTypeDef | HAL_SDRAM_Read_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_Write_DMA (SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SDRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Enable (SDRAM_HandleTypeDef *hsdram)
Enables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_WriteProtection_Disable (SDRAM_HandleTypeDef *hsdram)
Disables dynamically SDRAM write protection.
HAL_StatusTypeDef | HAL_SDRAM_SendCommand (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Sends Command to the SDRAM bank.
HAL_StatusTypeDef | HAL_SDRAM_ProgramRefreshRate (SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
Programs the SDRAM Memory Refresh rate.
HAL_StatusTypeDef | HAL_SDRAM_SetAutoRefreshNumber (SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
Sets the Number of consecutive SDRAM Memory auto Refresh commands.
uint32_t | HAL_SDRAM_GetModeStatus (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM memory current mode.
HAL_SDRAM_StateTypeDef | HAL_SDRAM_GetState (SDRAM_HandleTypeDef *hsdram)
Returns the SDRAM state.

Detailed Description

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                       ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SDRAM memories. It uses the FMC layer functions to interface
    with SDRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SDRAM memories:

   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
          SDRAM_HandleTypeDef  hdsram

       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SDRAM device

   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
          FMC_SDRAM_TimingTypeDef  Timing;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
       (##) Control register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Init()
       (##) Timing register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Timing_Init()
       (##) Program the SDRAM external device by applying its initialization sequence
            according to the device plugged in your hardware. This step is mandatory
            for accessing the SDRAM device.

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the SDRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
       structure.

   (#) You can continuously monitor the SDRAM device HAL state by calling the function
       HAL_SDRAM_GetState()
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sdram.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | TEACK_REACK_TIMEOUT 1000
#define | HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

Functions

static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD associated USART peripheral.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles SMARTCARD Communication Timeout.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsc)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc)
Receive an amount of data in non blocking mode.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD associated USART peripheral advanced features.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SMARTCARD mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD interrupt requests handling.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follow:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure.
    (#) Associate a USART to the SMARTCARD handle hsc.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) SMARTCARD pins configuration:
            (+++) Enable the clock for the SMARTCARD GPIOs.
            (+++) Configure these SMARTCARD pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (+++) The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsc Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsc AdvancedInit structure.

    (#) Initialize the SMARTCARD associated USART registers by calling
        the HAL_SMARTCARD_Init() API.

  [..]
    (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_SMARTCARD_MspInit() API.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_smartcard.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard_ex.c File Reference

  • File List
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Functions
stm32f7xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsc)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

SMARTCARD HAL module driver.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015 This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The Extended SMARTCARD HAL driver can be used as follow:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsc AdvancedInit structure.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_smartcard_ex.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spdifrx.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_spdifrx.c File Reference

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | SPDIFRX_TIMEOUT_VALUE 0xFFFF

Functions

static void | SPDIFRX_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) complete callback.
static void | SPDIFRX_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Data flow) half complete callback.
static void | SPDIFRX_DMACxCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) complete callback.
static void | SPDIFRX_DMACxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SPDIFRX receive process (Control flow) half complete callback.
static void | SPDIFRX_DMAError (DMA_HandleTypeDef *hdma)
DMA SPDIFRX communication error callback.
static void | SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Control Flow) with Interrupt.
static void | SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif)
Receive an amount of data (Data Flow) with Interrupt.
static HAL_StatusTypeDef | SPDIFRX_WaitOnFlagUntilTimeout (SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles SPDIFRX Communication Timeout.
HAL_StatusTypeDef | HAL_SPDIFRX_Init (SPDIFRX_HandleTypeDef *hspdif)
Initializes the SPDIFRX according to the specified parameters in the SPDIFRX_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif)
DeInitializes the SPDIFRX peripheral.
__weak void | HAL_SPDIFRX_MspInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP Init.
__weak void | HAL_SPDIFRX_MspDeInit (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX MSP DeInit.
HAL_StatusTypeDef | HAL_SPDIFRX_SetDataFormat (SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
Sets the SPDIFRX dtat format according to the specified parameters in the SPDIFRX_InitTypeDef.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Data Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data (Control Flow) in blocking mode.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_IT (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with Interrupt.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveDataFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Data Flow) mode with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_ReceiveControlFlow_DMA (SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
Receive an amount of data (Control Flow) with DMA.
HAL_StatusTypeDef | HAL_SPDIFRX_DMAStop (SPDIFRX_HandleTypeDef *hspdif)
stop the audio stream receive from the Media.
void | HAL_SPDIFRX_IRQHandler (SPDIFRX_HandleTypeDef *hspdif)
This function handles SPDIFRX interrupt request.
__weak void | HAL_SPDIFRX_RxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) half completed callbacks.
__weak void | HAL_SPDIFRX_RxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Data flow) completed callbacks.
__weak void | HAL_SPDIFRX_CxHalfCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx (Control flow) Transfer half completed callbacks.
__weak void | HAL_SPDIFRX_CxCpltCallback (SPDIFRX_HandleTypeDef *hspdif)
Rx Transfer (Control flow) completed callbacks.
__weak void | HAL_SPDIFRX_ErrorCallback (SPDIFRX_HandleTypeDef *hspdif)
SPDIFRX error callbacks.
HAL_SPDIFRX_StateTypeDef | HAL_SPDIFRX_GetState (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX state.
uint32_t | HAL_SPDIFRX_GetError (SPDIFRX_HandleTypeDef *hspdif)
Return the SPDIFRX error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The SPDIFRX HAL driver can be used as follow:

    (#) Declare SPDIFRX_HandleTypeDef handle structure.
    (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
        (##) Enable the SPDIFRX interface clock.
        (##) SPDIFRX pins configuration:
            (+++) Enable the clock for the SPDIFRX GPIOs.
            (+++) Configure these SPDIFRX pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
            (+++) Configure the SPDIFRX interrupt priority.
            (+++) Enable the NVIC SPDIFRX IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
            (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
            (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
            (+++) Configure the DMA Channel.
            (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA CtrlRx/DataRx channel.

   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
       using HAL_SPDIFRX_Init() function.

   -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
       __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
   -@- Make sure that ck_spdif clock is configured.

   (#) Three operation modes are available within this driver :

   *** Polling mode for reception operation (for debug purpose) ***
   ================================================================
   [..]
     (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
         (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()

   *** Interrupt mode for reception operation ***
   =========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
         (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback

   *** DMA mode for reception operation ***
   ========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
         (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
     (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()

   *** SPDIFRX HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in USART HAL driver.
      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
      (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
      (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.

    [..]
      (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_spdifrx.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spi.c File Reference

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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 50

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI Half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
This function handles SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
This function handles SPI Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8Bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16Bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive in Interrupt context.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC receive in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16Bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16Bit Handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
This function handles the close of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
This function handles the close of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
This function handles the close of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
This function handles the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
This function handles the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initializes the SPI according to the specified parameters in the SPI_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
DeInitializes the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
SPI MSP Init.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
SPI MSP DeInit.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stops the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
This function handles SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callbacks.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx channel
              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customised HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_spi.c.

Generated on Fri Nov 13 2015 11:37:28 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sram.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Functions
stm32f7xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Performs the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Performs the SRAM device De-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
SRAM MSP Init.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
SRAM MSP DeInit.
__weak void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Reads 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Writes 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Reads 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Writes 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Reads a Words data from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Writes a Words data buffer to SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enables dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disables dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Returns the SRAM controller state.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_sram.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim.c File Reference

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stm32f7xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Time Output Compare 4 configuration.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
__weak HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
__weak HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
__weak HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | HAL_TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | HAL_TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | HAL_TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 1 configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 3 configuration.
void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 4 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output

                        ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
                 __GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
              Output Compare signal.
         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
              PWM signal.
         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
              external signal.
         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
              in One Pulse Mode.
         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_tim.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim_ex.c File Reference

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Defines | Functions
stm32f7xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | BDTR_BKF_SHIFT (16)
#define | BDTR_BK2F_SHIFT (20)

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t OCRef)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | HAL_TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extension features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Input Capture
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

                        ##### How to use this driver #####
  ==============================================================================
  [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
                 __GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

    (#) Configure the TIM in the desired functioning mode using one of the
        initialization function of this driver:
        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
             Timer Hall Sensor Interface and the commutation event with the corresponding
             Interrupt and DMA request if needed (Note that One Timer is used to interface
             with the Hall sensor Interface and another Timer should be used to use
             the commutation event).

    (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_tim_ex.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_uart.c File Reference

  • File List
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Defines | Functions
stm32f7xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_UART_TXDMA_TIMEOUTVALUE 22000
#define | UART_CR1_FIELDS

Functions

static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode Function called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT()
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode Function called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles UART Communication Timeout.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (doesn't mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (doesn't mean it actually wakes up the software, as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
return the UART state
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required
                  Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the Init structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.

    (#) For the Multi-Processor mode, initialize the UART registers by calling
        the HAL_MultiProcessor_Init() API.

     [..]
       (@) The specific UART interrupts (Transmission complete interrupt,
            RXNE interrupt and Error Interrupts) will be managed using the macros
            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
            and receive process.

     [..]
       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
            HAL_UART_MspInit() API.

     [..]
        Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
       (+) Stop the DMA Transfer using HAL_UART_DMAStop()

     *** UART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in UART HAL driver.

      (+) __HAL_UART_ENABLE: Enable the UART peripheral
      (+) __HAL_UART_DISABLE: Disable the UART peripheral
      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
      (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag
      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not

     [..]
       (@) You can refer to the UART HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_uart.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_usart.c File Reference

  • File List
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  • STM32F7xx_HAL_Driver
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Defines | Functions
stm32f7xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Defines

#define | DUMMY_DATA ((uint16_t) 0xFFFF)
#define | TEACK_REACK_TIMEOUT ((uint32_t) 1000)
#define | USART_TXDMA_TIMEOUTVALUE 22000
#define | USART_TIMEOUT_VALUE 22000
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS

Functions

static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in blocking mode To receive synchronous data, dummy data are simultaneously transmitted.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
return the USART state
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure.
      (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:
          (##) Enable the USARTx interface clock.
          (##) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (+++) The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
          flow control and Mode(Receiver/Transmitter) in the husart Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
               by calling the customed HAL_USART_MspInit(&husart) API.
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_usart.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F7xx_HAL_Driver
  • Src
Functions
stm32f7xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions. More...

#include "stm32f7xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_WWDG_DeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG peripheral.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG MSP.
__weak void | HAL_WWDG_MspDeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Start (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG.
HAL_StatusTypeDef | HAL_WWDG_Start_IT (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG with interrupt enabled.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
Refreshes the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handles WWDG interrupt request.
__weak void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.
HAL_WWDG_StateTypeDef | HAL_WWDG_GetState (WWDG_HandleTypeDef *hwwdg)
Returns the WWDG state.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.3
Date:
13-November-2015
  ==============================================================================
                      ##### WWDG specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (down-counter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls over from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock

    (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
    (+) Set the WWDG prescaler, refresh window and counter value
        using HAL_WWDG_Init() function.
    (+) Start the WWDG using HAL_WWDG_Start() function.
        When the WWDG is enabled the counter value should be configured to
        a value greater than 0x40 to prevent generating an immediate reset.
    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
        generated when the counter reaches 0x40, and then start the WWDG using
        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
        add his own code by customization of function pointer HAL_WWDG_WakeupCallback
        Once enabled, EWI interrupt cannot be disabled except by a system reset.
    (+) Then the application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the refresh window value already programmed.

     *** WWDG HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in WWDG HAL driver.

      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
      (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wake-up interrupt
Attention:

© COPYRIGHT(c) 2015 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_wwdg.c.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__DMA2D_HandleTypeDef | DMA2D handle Structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__SAI_HandleTypeDef | SAI handle Structure definition
__SPI_HandleTypeDef | SPI handle Structure definition
ADC_AnalogWDGConfTypeDef | ADC Configuration multi-mode structure definition
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_HandleTypeDef | ADC handle Structure definition
ADC_InitTypeDef | Structure definition of ADC and regular group initialization
ADC_InjectionConfTypeDef | ADC Configuration injected Channel structure definition
ADC_MultiModeTypeDef | ADC Configuration multi-mode structure definition
CAN_FilterConfTypeDef | CAN filter configuration structure definition
CAN_HandleTypeDef | CAN handle Structure definition
CAN_InitTypeDef | CAN init structure definition
CanRxMsgTypeDef | CAN Rx message structure definition
CanTxMsgTypeDef | CAN Tx message structure definition
CEC_HandleTypeDef | CEC handle Structure definition
CEC_InitTypeDef | CEC Init Structure definition
CRC_HandleTypeDef |
CRC_InitTypeDef |
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_HandleTypeDef | DAC handle Structure definition
DCMI_CodesInitTypeDef | DCMIEx Embedded Synchronisation CODE Init structure definition
DCMI_HandleTypeDef | DCMI handle Structure definition
DCMI_InitTypeDef | DCMI Init structure definition
DMA2D_CLUTCfgTypeDef | DMA2D CLUT Structure definition
DMA2D_ColorTypeDef | DMA2D color Structure definition
DMA2D_InitTypeDef | DMA2D Init structure definition
DMA2D_LayerCfgTypeDef | DMA2D Layer structure definition
DMA_Base_Registers |
DMA_InitTypeDef | DMA Configuration Structure definition
ETH_DMADescTypeDef | ETH DMA Descriptors data structure definition
ETH_DMAInitTypeDef | ETH DMA Configuration Structure definition
ETH_DMARxFrameInfos | Received Frame Informations structure definition
ETH_HandleTypeDef | ETH Handle Structure definition
ETH_InitTypeDef | ETH Init Structure definition
ETH_MACInitTypeDef | ETH MAC Configuration Structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HAL_SD_CardInfoTypedef |
HAL_SD_CardStatusTypedef |
HAL_SD_CIDTypedef |
HAL_SD_CSDTypedef |
HCD_HandleTypeDef |
I2C_HandleTypeDef |
I2C_InitTypeDef |
I2S_HandleTypeDef | I2S handle Structure definition
I2S_InitTypeDef | I2S Init structure definition
IRDA_HandleTypeDef | IRDA handle Structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_HandleTypeDef | LPTIM handle Structure definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
MPU_Region_InitTypeDef |
NAND_AddressTypeDef | NAND Memory address Structure definition
NAND_HandleTypeDef | NAND handle Structure definition
NAND_IDTypeDef | NAND Memory electronic signature Structure definition
NAND_InfoTypeDef | NAND Memory info Structure definition
NOR_CFITypeDef | FMC NOR CFI typedef
NOR_HandleTypeDef | NOR handle Structure definition
NOR_IDTypeDef | FMC NOR ID typedef
PCD_HandleTypeDef | PCD Handle Structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
QSPI_AutoPollingTypeDef | QSPI Auto Polling mode configuration structure definition
QSPI_CommandTypeDef | QSPI Command structure definition
QSPI_HandleTypeDef | QSPI Handle Structure definition
QSPI_InitTypeDef | QSPI Init structure definition
QSPI_MemoryMappedTypeDef | QSPI Memory Mapped mode configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLI2SInitTypeDef | PLLI2S Clock structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RCC_PLLSAIInitTypeDef | PLLSAI Clock structure definition
RNG_HandleTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_HandleTypeDef | RTC Handle Structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SAI_FrameInitTypeDef | SAI Block Frame Init structure definition
SAI_InitTypeDef | SAI Init Structure definition
SAI_SlotInitTypeDef | SAI Block Slot Init Structure definition
SD_HandleTypeDef |
SDRAM_HandleTypeDef | SDRAM handle Structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initalization structure definition
SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SPDIFRX_HandleTypeDef | SPDIFRX handle Structure definition
SPDIFRX_InitTypeDef | SPDIFRX Init structure definition
SPDIFRX_SetDataFormatTypeDef | SPDIFRX SetDataFormat structure definition
SPI_InitTypeDef | SPI Configuration Structure definition
SRAM_HandleTypeDef | SRAM handle Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef | TIM Time Base Handle Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
UART_AdvFeatureInitTypeDef | UART Advanced Features initialization structure definition
UART_HandleTypeDef | UART handle Structure definition
UART_InitTypeDef | UART Init Structure definition
USART_HandleTypeDef | USART handle Structure definition
USART_InitTypeDef | USART Init Structure definition
WWDG_HandleTypeDef | WWDG handle Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | E | F | G | H | I | L | M | N | P | Q | R | S | T | U | W | _
A
E
IWDG_InitTypeDef RCC_OscInitTypeDef TIM_ClockConfigTypeDef
L
RCC_PeriphCLKInitTypeDef TIM_Encoder_InitTypeDef
ADC_AnalogWDGConfTypeDef ETH_DMADescTypeDef RCC_PLLI2SInitTypeDef TIM_HallSensor_InitTypeDef
ADC_ChannelConfTypeDef ETH_DMAInitTypeDef LPTIM_ClockConfigTypeDef RCC_PLLInitTypeDef TIM_HandleTypeDef
ADC_HandleTypeDef ETH_DMARxFrameInfos LPTIM_HandleTypeDef RCC_PLLSAIInitTypeDef TIM_IC_InitTypeDef
ADC_InitTypeDef ETH_HandleTypeDef LPTIM_InitTypeDef RNG_HandleTypeDef TIM_MasterConfigTypeDef
ADC_InjectionConfTypeDef ETH_InitTypeDef LPTIM_TriggerConfigTypeDef RTC_AlarmTypeDef TIM_OC_InitTypeDef
ADC_MultiModeTypeDef ETH_MACInitTypeDef LPTIM_ULPClockConfigTypeDef RTC_DateTypeDef TIM_OnePulse_InitTypeDef
C
F
M
RTC_HandleTypeDef TIM_SlaveConfigTypeDef
RTC_InitTypeDef
U
CAN_FilterConfTypeDef FLASH_EraseInitTypeDef MPU_Region_InitTypeDef RTC_TamperTypeDef
CAN_HandleTypeDef FLASH_OBProgramInitTypeDef
N
RTC_TimeTypeDef UART_AdvFeatureInitTypeDef
CAN_InitTypeDef FLASH_ProcessTypeDef
S
UART_HandleTypeDef
CanRxMsgTypeDef
G
NAND_AddressTypeDef UART_InitTypeDef
CanTxMsgTypeDef NAND_HandleTypeDef SAI_FrameInitTypeDef USART_HandleTypeDef
CEC_HandleTypeDef GPIO_InitTypeDef NAND_IDTypeDef SAI_InitTypeDef USART_InitTypeDef
CEC_InitTypeDef
H
NAND_InfoTypeDef SAI_SlotInitTypeDef
W
CRC_HandleTypeDef NOR_CFITypeDef SD_HandleTypeDef
CRC_InitTypeDef HAL_SD_CardInfoTypedef NOR_HandleTypeDef SDRAM_HandleTypeDef WWDG_HandleTypeDef
D
HAL_SD_CardStatusTypedef NOR_IDTypeDef SMARTCARD_AdvFeatureInitTypeDef WWDG_InitTypeDef
HAL_SD_CIDTypedef
P
SMARTCARD_HandleTypeDef
_
DAC_ChannelConfTypeDef HAL_SD_CSDTypedef SMARTCARD_InitTypeDef
DAC_HandleTypeDef HCD_HandleTypeDef PCD_HandleTypeDef SPDIFRX_HandleTypeDef __DMA2D_HandleTypeDef
DCMI_CodesInitTypeDef
I
PWR_PVDTypeDef SPDIFRX_InitTypeDef __DMA_HandleTypeDef
DCMI_HandleTypeDef
Q
SPDIFRX_SetDataFormatTypeDef __SAI_HandleTypeDef
DCMI_InitTypeDef I2C_HandleTypeDef SPI_InitTypeDef __SPI_HandleTypeDef
DMA2D_CLUTCfgTypeDef I2C_InitTypeDef QSPI_AutoPollingTypeDef SRAM_HandleTypeDef
DMA2D_ColorTypeDef I2S_HandleTypeDef QSPI_CommandTypeDef
T
DMA2D_InitTypeDef I2S_InitTypeDef QSPI_HandleTypeDef
DMA2D_LayerCfgTypeDef IRDA_HandleTypeDef QSPI_InitTypeDef TIM_Base_InitTypeDef
DMA_Base_Registers IRDA_InitTypeDef QSPI_MemoryMappedTypeDef TIM_BreakDeadTimeConfigTypeDef
DMA_InitTypeDef IWDG_HandleTypeDef
R
TIM_ClearInputConfigTypeDef
RCC_ClkInitTypeDef
A | C | D | E | F | G | H | I | L | M | N | P | Q | R | S | T | U | W | _
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: C:/SVN/STM32F7xx_HAL_Driver/Trunk/Drivers/STM32F7xx_HAL_Driver/Inc/ Directory Reference

  • Drivers
  • STM32F7xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32f7xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32f7xx_hal_adc.h [code]

Header file of ADC HAL extension module.

file | stm32f7xx_hal_adc_ex.h [code]
file | stm32f7xx_hal_can.h [code]

Header file of CAN HAL module.

file | stm32f7xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32f7xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32f7xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32f7xx_hal_crc_ex.h [code]

Header file of CRC HAL extension module.

file | stm32f7xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32f7xx_hal_cryp_ex.h [code]

Header file of CRYP HAL Extension module.

file | stm32f7xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32f7xx_hal_dac_ex.h [code]
file | stm32f7xx_hal_dcmi.h [code]

Header file of DCMI HAL module.

file | stm32f7xx_hal_dcmi_ex.h [code]

Header file of DCMI Extension HAL module.

file | stm32f7xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32f7xx_hal_dma2d.h [code]

Header file of DMA2D HAL module.

file | stm32f7xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32f7xx_hal_eth.h [code]

Header file of ETH HAL module.

file | stm32f7xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32f7xx_hal_flash_ex.h [code]

Header file of FLASH HAL Extension module.

file | stm32f7xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32f7xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extension module.

file | stm32f7xx_hal_hash.h [code]

Header file of HASH HAL module.

file | stm32f7xx_hal_hash_ex.h [code]

Header file of HASH HAL Extension module.

file | stm32f7xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32f7xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32f7xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extension module.

file | stm32f7xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32f7xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32f7xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extension module.

file | stm32f7xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32f7xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32f7xx_hal_ltdc.h [code]

Header file of LTDC HAL module.

file | stm32f7xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32f7xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32f7xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32f7xx_hal_pcd_ex.h [code]

Header file of PCD HAL module.

file | stm32f7xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32f7xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extension module.

file | stm32f7xx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32f7xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32f7xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extension module.

file | stm32f7xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32f7xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32f7xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extension module.

file | stm32f7xx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32f7xx_hal_sai_ex.h [code]

Header file of SAI Extension HAL module.

file | stm32f7xx_hal_sd.h [code]

Header file of SD HAL module.

file | stm32f7xx_hal_sdram.h [code]

Header file of SDRAM HAL module.

file | stm32f7xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32f7xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL module.

file | stm32f7xx_hal_spdifrx.h [code]

Header file of SPDIFRX HAL module.

file | stm32f7xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32f7xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32f7xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32f7xx_hal_tim_ex.h [code]

Header file of TIM HAL Extension module.

file | stm32f7xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32f7xx_hal_uart_ex.h [code]

Header file of UART HAL Extension module.

file | stm32f7xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32f7xx_hal_usart_ex.h [code]

Header file of USART HAL Extension module.

file | stm32f7xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: C:/SVN/STM32F7xx_HAL_Driver/Trunk/Drivers/ Directory Reference

  • Drivers
Drivers Directory Reference

Directories

directory STM32F7xx_HAL_Driver
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: C:/SVN/STM32F7xx_HAL_Driver/Trunk/Drivers/STM32F7xx_HAL_Driver/ Directory Reference

  • Drivers
  • STM32F7xx_HAL_Driver
STM32F7xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: C:/SVN/STM32F7xx_HAL_Driver/Trunk/Drivers/STM32F7xx_HAL_Driver/Src/ Directory Reference

  • Drivers
  • STM32F7xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32f7xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32f7xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions.

file | stm32f7xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions.

file | stm32f7xx_hal_can.c [code]

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f7xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

file | stm32f7xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f7xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_crc_ex.c [code]

Extended CRC HAL module driver.

file | stm32f7xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32f7xx_hal_cryp_ex.c [code]

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

file | stm32f7xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_dac_ex.c [code]

Extended DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions.

file | stm32f7xx_hal_dcmi.c [code]

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f7xx_hal_dcmi_ex.c [code]

DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions.

file | stm32f7xx_hal_dma.c [code]

DMA HAL module driver.

file | stm32f7xx_hal_dma2d.c [code]

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32f7xx_hal_eth.c [code]

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32f7xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

file | stm32f7xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32f7xx_hal_hash.c [code]

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions.

file | stm32f7xx_hal_hash_ex.c [code]

HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm.

file | stm32f7xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

file | stm32f7xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods.

file | stm32f7xx_hal_iwdg.c [code]

IWDG HAL module driver.

file | stm32f7xx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32f7xx_hal_ltdc.c [code]

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32f7xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32f7xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_pcd_ex.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32f7xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f7xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

file | stm32f7xx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32f7xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f7xx_hal_rcc_ex.c [code]

Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

file | stm32f7xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_rtc_ex.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions.

file | stm32f7xx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_sai_ex.c [code]

SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions.

file | stm32f7xx_hal_sd.c [code]

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_sdram.c [code]

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

file | stm32f7xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver.

file | stm32f7xx_hal_spdifrx.c [code]

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32f7xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f7xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32f7xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

file | stm32f7xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

file | stm32f7xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f7xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32f7xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Drivers
    • STM32F7xx_HAL_Driver
      • Inc
      • Src
Generated on Fri Nov 13 2015 11:37:39 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32f7xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32f7xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32f7xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions
stm32f7xx_hal_adc.h [code] | Header file of ADC HAL extension module
stm32f7xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions
stm32f7xx_hal_adc_ex.h [code] |
stm32f7xx_hal_can.c [code] | CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f7xx_hal_can.h [code] | Header file of CAN HAL module
stm32f7xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function
stm32f7xx_hal_cec.h [code] | Header file of CEC HAL module
stm32f7xx_hal_conf.h [code] |
stm32f7xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions
stm32f7xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32f7xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_crc.h [code] | Header file of CRC HAL module
stm32f7xx_hal_crc_ex.c [code] | Extended CRC HAL module driver
stm32f7xx_hal_crc_ex.h [code] | Header file of CRC HAL extension module
stm32f7xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32f7xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32f7xx_hal_cryp_ex.c [code] | Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions
stm32f7xx_hal_cryp_ex.h [code] | Header file of CRYP HAL Extension module
stm32f7xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f7xx_hal_dac.h [code] | Header file of DAC HAL module
stm32f7xx_hal_dac_ex.c [code] | Extended DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions
stm32f7xx_hal_dac_ex.h [code] |
stm32f7xx_hal_dcmi.c [code] | DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f7xx_hal_dcmi.h [code] | Header file of DCMI HAL module
stm32f7xx_hal_dcmi_ex.c [code] | DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions
stm32f7xx_hal_dcmi_ex.h [code] | Header file of DCMI Extension HAL module
stm32f7xx_hal_dma.c [code] | DMA HAL module driver
stm32f7xx_hal_dma.h [code] | Header file of DMA HAL module
stm32f7xx_hal_dma2d.c [code] | DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f7xx_hal_dma2d.h [code] | Header file of DMA2D HAL module
stm32f7xx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32f7xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32f7xx_hal_eth.c [code] | ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f7xx_hal_eth.h [code] | Header file of ETH HAL module
stm32f7xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32f7xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32f7xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions
stm32f7xx_hal_flash_ex.h [code] | Header file of FLASH HAL Extension module
stm32f7xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32f7xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32f7xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extension module
stm32f7xx_hal_hash.c [code] | HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions
stm32f7xx_hal_hash.h [code] | Header file of HASH HAL module
stm32f7xx_hal_hash_ex.c [code] | HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm
stm32f7xx_hal_hash_ex.h [code] | Header file of HASH HAL Extension module
stm32f7xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32f7xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f7xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32f7xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions
stm32f7xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extension module
stm32f7xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f7xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32f7xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods
stm32f7xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32f7xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extension module
stm32f7xx_hal_iwdg.c [code] | IWDG HAL module driver
stm32f7xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32f7xx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32f7xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32f7xx_hal_ltdc.c [code] | LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f7xx_hal_ltdc.h [code] | Header file of LTDC HAL module
stm32f7xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32f7xx_hal_nand.h [code] | Header file of NAND HAL module
stm32f7xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32f7xx_hal_nor.h [code] | Header file of NOR HAL module
stm32f7xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32f7xx_hal_pcd_ex.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32f7xx_hal_pcd_ex.h [code] | Header file of PCD HAL module
stm32f7xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32f7xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32f7xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions
stm32f7xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extension module
stm32f7xx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32f7xx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32f7xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32f7xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32f7xx_hal_rcc_ex.c [code] | Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions
stm32f7xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extension module
stm32f7xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_rng.h [code] | Header file of RNG HAL module
stm32f7xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32f7xx_hal_rtc_ex.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions
stm32f7xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extension module
stm32f7xx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_sai.h [code] | Header file of SAI HAL module
stm32f7xx_hal_sai_ex.c [code] | SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions
stm32f7xx_hal_sai_ex.h [code] | Header file of SAI Extension HAL module
stm32f7xx_hal_sd.c [code] | SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_sd.h [code] | Header file of SD HAL module
stm32f7xx_hal_sdram.c [code] | SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device
stm32f7xx_hal_sdram.h [code] | Header file of SDRAM HAL module
stm32f7xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f7xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32f7xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver
stm32f7xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL module
stm32f7xx_hal_spdifrx.c [code] | This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32f7xx_hal_spdifrx.h [code] | Header file of SPDIFRX HAL module
stm32f7xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f7xx_hal_spi.h [code] | Header file of SPI HAL module
stm32f7xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32f7xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32f7xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration
stm32f7xx_hal_tim.h [code] | Header file of TIM HAL module
stm32f7xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration
stm32f7xx_hal_tim_ex.h [code] | Header file of TIM HAL Extension module
stm32f7xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f7xx_hal_uart.h [code] | Header file of UART HAL module
stm32f7xx_hal_uart_ex.h [code] | Header file of UART HAL Extension module
stm32f7xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32f7xx_hal_usart.h [code] | Header file of USART HAL module
stm32f7xx_hal_usart_ex.h [code] | Header file of USART HAL Extension module
stm32f7xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions
stm32f7xx_hal_wwdg.h [code] | Header file of WWDG HAL module
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STM32F745xx HAL User Manual: ADC

Modules
ADC
STM32F7xx_HAL_Driver

ADC driver modules. More...

Modules

ADC Exported Functions
ADC Private Functions
ADC Exported Types
ADC Exported Constants
ADC Exported Macros
ADC Private Constants
ADC Private Macros

Detailed Description

ADC driver modules.

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STM32F745xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC Clock Prescaler
ADC Delay Between 2 Sampling Phases
ADC Resolution
ADC External Trigger Edge Regular
ADC External Trigger Source Regular
ADC Data Align
ADC Common Channels
ADC Sampling Times
ADC EOC Selection
ADC Event Type
ADC Analog Watchdog Selection
ADC Interrupts Definition
ADC Flags Definition
ADC Channels Type
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STM32F745xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

ADC Peripheral State functions

ADC Peripheral State functions.

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STM32F745xx HAL User Manual: ADCEx

Data Structures | Modules
ADCEx
STM32F7xx_HAL_Driver

ADC Extended driver modules. More...

Data Structures

struct ADC_MultiModeTypeDef
ADC Configuration multi-mode structure definition. More...

Modules

ADC Exported Functions
ADC Exported Types
ADC Private Functions

Detailed Description

ADC Extended driver modules.

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STM32F745xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
STM32F7xx_HAL_Driver

Modules

ADC Common Mode
ADC Direct Memory Access Mode For Multi Mode
ADC External Trigger Edge Injected
ADC External Trigger Source Injected
ADC Injected Channel Selection
ADC Specific Channels
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STM32F745xx HAL User Manual: ADC Exported Types

Data Structures
ADC Exported Types
ADCEx

Data Structures

struct ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
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STM32F745xx HAL User Manual: CAN

Modules
CAN
STM32F7xx_HAL_Driver

CAN driver modules. More...

Modules

CAN Exported Functions
CAN Exported Types
CAN Exported Constants
CAN Exported Macros
CAN Private Types
CAN Private Variables
CAN Private Constants
CAN Private Macros
CAN Private Functions

Detailed Description

CAN driver modules.

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STM32F745xx HAL User Manual: CAN Exported Constants

Modules
CAN Exported Constants
CAN

Modules

HAL CAN Error Code
CAN InitStatus
CAN Operating Mode
CAN Synchronisation Jump Width
CAN Time Quantum in bit segment 1
CAN Time Quantum in bit segment 2
CAN Filter Mode
CAN Filter Scale
CAN Filter FIFO
CAN Identifier Type
CAN Remote Transmission Request
CAN Receive FIFO Number Constants
CAN Flags
CAN Interrupts
CAN Mailboxes Definition
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STM32F745xx HAL User Manual: CEC

Modules
CEC
STM32F7xx_HAL_Driver

HAL CEC module driver. More...

Modules

CEC Private Constants
CEC Private Functions
CEC Exported Functions
CEC Exported Types
CEC Exported Constants
CEC Exported Macros
CEC Private Types
CEC Private Variables
CEC Private Macros

Detailed Description

HAL CEC module driver.

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STM32F745xx HAL User Manual: CEC Exported Constants

Modules
CEC Exported Constants
CEC

Modules

CEC Error Code
CEC Signal Free Time setting parameter
CEC Receiver Tolerance
CEC Reception Stop on Error
CEC Error Bit Generation if Bit Rise Error reported
CEC Error Bit Generation if Long Bit Period Error reported
CEC Error Bit Generation on Broadcast message
CEC Signal Free Time start option
CEC Listening mode option
CEC Device Own Address position in CEC CFGR register
CEC Initiator logical address position in message header
CEC Interrupts definition
CEC Flags definition
CEC all RX or TX errors flags
CEC all RX errors interrupts enabling flag
CEC all TX errors interrupts enabling flag
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STM32F745xx HAL User Manual: CORTEX

Modules
CORTEX
STM32F7xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Functions
Cortex Exported Types
CORTEX Exported Constants
CORTEX Private Macros
CORTEX Private Functions

CORTEX private functions.

Detailed Description

CORTEX HAL module driver.

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STM32F745xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX _SysTick clock source
MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
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STM32F745xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

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STM32F745xx HAL User Manual: Cortex Exported Types

Modules
Cortex Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

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STM32F745xx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
Cortex Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

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STM32F745xx HAL User Manual: CRC

Modules
CRC
STM32F7xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Exported Functions
CRC Exported Types
CRC exported constants
CRC exported macros
CRC Private Types
CRC Private Defines
CRC Private Variables
CRC Private Constants
CRC Private Macros
CRC Private Functions Prototypes
CRC Private Functions

Detailed Description

CRC HAL module driver.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: CRC exported constants

Modules
CRC exported constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the IP
CRC polynomial possible sizes actual definitions
CRC input buffer format
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STM32F745xx HAL User Manual: CRC Exported Types

Modules
CRC Exported Types
CRC

Modules

CRC State Structure definition
CRC Init Structure definition
CRC Handle Structure definition
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STM32F745xx HAL User Manual: CRC Init Structure definition

Data Structures
CRC Init Structure definition
CRC Exported Types

Data Structures

struct CRC_InitTypeDef
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STM32F745xx HAL User Manual: CRC Handle Structure definition

Data Structures
CRC Handle Structure definition
CRC Exported Types

Data Structures

struct CRC_HandleTypeDef
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STM32F745xx HAL User Manual: CRCEx

Modules
CRCEx
STM32F7xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended exported constants
CRC Extended exported macros
CRC Extended Exported Functions

Detailed Description

CRC Extended HAL module driver.

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STM32F745xx HAL User Manual: CRC Extended exported constants

Modules
CRC Extended exported constants
CRCEx

Modules

CRC Extended input data inversion modes
CRC Extended output data inversion modes
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STM32F745xx HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended CRC features functions

Extended CRC features functions.

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STM32F745xx HAL User Manual: DAC

Modules
DAC
STM32F7xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Constants
DAC Private Macros
DAC Private Functions

Detailed Description

DAC driver modules.

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STM32F745xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC Trigger Selection
DAC Output Buffer
DAC Channel Selection
DAC Data Alignment
DAC Flags Definition
DAC IT Definition
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STM32F745xx HAL User Manual: DACEx

Modules
DACEx
STM32F7xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Constants
DAC Private Constants
DAC Private Macros
DAC Private Functions

Detailed Description

DAC driver modules.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DACEx

Modules

DAC LFS Run Mask Triangle Amplitude
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STM32F745xx HAL User Manual: DCMI Exported Constants

Modules
DCMI Exported Constants
DCMI

Modules

DCMI Error Code
DCMI Capture Mode
DCMI Synchronization Mode
DCMI PIXCK Polarity
DCMI VSYNC Polarity
DCMI HSYNC Polarity
DCMI MODE JPEG
DCMI Capture Rate
DCMI Extended Data Mode
DCMI Window Coordinate
DCMI Window Height
DCMI interrupt sources
DCMI Flags
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STM32F745xx HAL User Manual: DCMI Exported Functions

Modules
DCMI Exported Functions
DCMI

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

DCMI Private Functions
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STM32F745xx HAL User Manual: DCMIEx

Modules
DCMIEx
STM32F7xx_HAL_Driver

DCMI Extended HAL module driver. More...

Modules

DCMIEx Exported Functions
DCMIEx Exported Types
DCMIEx Exported Constants
DCMIEx Private Macros

Detailed Description

DCMI Extended HAL module driver.

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STM32F745xx HAL User Manual: DCMIEx Exported Constants

Modules
DCMIEx Exported Constants
DCMIEx

Modules

DCMIEx Byte Select Mode
DCMIEx Byte Select Start
DCMIEx Line Select Mode
DCMIEx Line Select Start
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STM32F745xx HAL User Manual: DCMIEx Exported Functions

Modules
DCMIEx Exported Functions
DCMIEx

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

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STM32F745xx HAL User Manual: DCMIEx Exported Types

Data Structures
DCMIEx Exported Types
DCMIEx

Data Structures

struct | DCMI_CodesInitTypeDef
DCMIEx Embedded Synchronisation CODE Init structure definition. More...
struct | DCMI_InitTypeDef
DCMI Init structure definition. More...
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STM32F745xx HAL User Manual: DMA2D

Modules
DMA2D
STM32F7xx_HAL_Driver

DMA2D HAL module driver. More...

Modules

DMA2D Exported Types
DMA2D Exported Constants
DMA2D Exported Macros
DMA2D Exported Functions
DMA2D Private Types
DMA2D Private Defines
DMA2D Private Variables
DMA2D Private Constants
DMA2D Private Macros
DMA2D Private Functions Prototypes
DMA2D Private Functions

Detailed Description

DMA2D HAL module driver.

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STM32F745xx HAL User Manual: DMA2D Exported Constants

Modules
DMA2D Exported Constants
DMA2D

Modules

DMA2D Error Code
DMA2D Mode
DMA2D Color Mode
DMA2D COLOR VALUE
DMA2D SIZE
DMA2D Offset
DMA2D Input Color Mode
DMA2D ALPHA MODE
DMA2D CLUT CM
DMA2D Size Clut
DMA2D DeadTime
DMA2D Interrupts
DMA2D Flag
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STM32F745xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

DMA Exported constants. More...

Modules

DMA Error Code

DMA Error Code.

DMA Channel selection

DMA channel selection.

DMA Data transfer direction

DMA data transfer direction.

DMA Peripheral incremented mode

DMA peripheral incremented mode.

DMA Memory incremented mode

DMA memory incremented mode.

DMA Peripheral data size

DMA peripheral data size.

DMA Memory data size

DMA memory data size.

DMA mode

DMA mode.

DMA Priority level

DMA priority levels.

DMA FIFO direct mode

DMA FIFO direct mode.

DMA FIFO threshold level

DMA FIFO level.

DMA Memory burst

DMA memory burst.

DMA Peripheral burst

DMA peripheral burst.

DMA interrupt enable definitions

DMA interrupts definition.

DMA flag definitions

DMA flag definitions.

Detailed Description

DMA Exported constants.

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STM32F745xx HAL User Manual: DMAEx

Modules
DMAEx
STM32F7xx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Types

DMAEx Exported types.

DMAEx Exported Functions

DMAEx Exported functions.

DMAEx Private Functions

DMAEx Private functions.

Detailed Description

DMA Extended HAL module driver.

Generated on Fri Nov 13 2015 11:37:30 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

DMAEx Exported functions. More...

Modules

Extended features functions

Extended features functions.

Detailed Description

DMAEx Exported functions.

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STM32F745xx HAL User Manual: ETH

Modules
ETH
STM32F7xx_HAL_Driver

ETH HAL module driver. More...

Modules

ETH Private Constants
ETH Private Functions
ETH Exported Functions
ETH Exported Types
ETH Exported Constants
ETH Exported Macros

macros to handle interrupts and specific clock configurations

ETH_Private_Macros
ETH_Private_Defines

Detailed Description

ETH HAL module driver.

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STM32F745xx HAL User Manual: ETH Exported Constants

Modules
ETH Exported Constants
ETH

Modules

ETH Buffers setting
ETH DMA TX Descriptor
ETH DMA RX Descriptor
ETH AutoNegotiation
ETH Speed
ETH Duplex Mode
ETH Rx Mode
ETH Checksum Mode
ETH Media Interface
ETH Watchdog
ETH Jabber
ETH Inter Frame Gap
ETH Carrier Sense
ETH Receive Own
ETH Loop Back Mode
ETH Checksum Offload
ETH Retry Transmission
ETH Automatic Pad CRC Strip
ETH Back Off Limit
ETH Deferral Check
ETH Receive All
ETH Source Addr Filter
ETH Pass Control Frames
ETH Broadcast Frames Reception
ETH Destination Addr Filter
ETH Promiscuous Mode
ETH Multicast Frames Filter
ETH Unicast Frames Filter
ETH Zero Quanta Pause
ETH Pause Low Threshold
ETH Unicast Pause Frame Detect
ETH Receive Flow Control
ETH Transmit Flow Control
ETH VLAN Tag Comparison
ETH MAC addresses
ETH MAC addresses filter SA DA
ETH MAC addresses filter Mask bytes
ETH MAC Debug flags
ETH Drop TCP IP Checksum Error Frame
ETH Receive Store Forward
ETH Flush Received Frame
ETH Transmit Store Forward
ETH Transmit Threshold Control
ETH Forward Error Frames
ETH Forward Undersized Good Frames
ETH Receive Threshold Control
ETH Second Frame Operate
ETH Address Aligned Beats
ETH Fixed Burst
ETH Rx DMA Burst Length
ETH Tx DMA Burst Length
ETH DMA Enhanced descriptor format
ETH DMA Arbitration
ETH DMA Tx descriptor segment
ETH DMA Tx descriptor Checksum Insertion Control
ETH DMA Rx descriptor buffers
ETH PMT Flags
ETH MMC Tx Interrupts
ETH MMC Rx Interrupts
ETH MAC Flags
ETH DMA Flags
ETH MAC Interrupts
ETH DMA Interrupts
ETH DMA transmit process state
ETH DMA receive process state
ETH DMA overflow
ETH EXTI LINE WAKEUP
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STM32F745xx HAL User Manual: ETH Exported Functions

Modules
ETH Exported Functions
ETH

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

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STM32F745xx HAL User Manual: FLASH

Modules
FLASH
STM32F7xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros
FLASH Private Variables
FLASH Private Constants
FLASH Private Macros
FLASH Private Functions

Detailed Description

FLASH HAL module driver.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error Code

FLASH Error Code.

FLASH Type Program
FLASH Flag definition

Flag definition.

FLASH Interrupt definition

FLASH Interrupt definition.

FLASH Program Parallelism
FLASH Keys
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STM32F745xx HAL User Manual: FLASH Private Macros

Modules
FLASH Private Macros
FLASH

Modules

FLASH Private macros to check input parameters
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STM32F745xx HAL User Manual: FLASHEx

Modules
FLASHEx
STM32F7xx_HAL_Driver

FLASH HAL Extension module driver. More...

Modules

FLASHEx Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Private Constants
FLASH Private Macros
FLASH Private Functions
FLASHEx_Private_Variables

Detailed Description

FLASH HAL Extension module driver.

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STM32F745xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASHEx

Modules

FLASH Type Erase
FLASH Voltage Range
FLASH WRP State
FLASH Option Type
FLASH Option Bytes Read Protection
FLASH Option Bytes WWatchdog
FLASH Option Bytes IWatchdog
FLASH Option Bytes nRST_STOP
FLASH Option Bytes nRST_STDBY
FLASH IWDG Counter Freeze in STOP
FLASH IWDG Counter Freeze in STANDBY
FLASH BOR Reset Level
FLASH Boot Address
FLASH Latency
FLASH Mass Erase bit
FLASH Sectors
FLASH Option Bytes Write Protection
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STM32F745xx HAL User Manual: FLASH Exported Types

Data Structures
FLASH Exported Types
FLASHEx

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
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STM32F745xx HAL User Manual: FLASH Private Macros

Modules
FLASH Private Macros
FLASHEx

Modules

FLASH Private macros to check input parameters
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STM32F745xx HAL User Manual: GPIO

Modules
GPIO
STM32F7xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions

Detailed Description

GPIO HAL module driver.

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STM32F745xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins define
GPIO mode define

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed define

GPIO Output Maximum frequency.

GPIO pull define

GPIO Pull-Up or Pull-Down Activation.

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STM32F745xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read and Write.

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STM32F745xx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32F7xx_HAL_Driver

Modules

GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions
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STM32F745xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIOEx

Modules

GPIO Alternate Function Selection
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STM32F745xx HAL User Manual: HAL

Modules
HAL
STM32F7xx_HAL_Driver

HAL module driver. More...

Modules

HAL Exported Functions
HAL Exported Macros
HAL Private Variables
HAL Private Constants

Detailed Description

HAL module driver.

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STM32F745xx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

Generated on Fri Nov 13 2015 11:37:29 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HCD

Modules
HCD
STM32F7xx_HAL_Driver

HCD HAL module driver. More...

Modules

HCD Private Functions
HCD Exported Functions
HCD Exported Types
HCD Exported Constants
HCD Exported Macros

macros to handle interrupts and specific clock configurations

HCD Private Macros
HCD Private Functions Prototypes

Detailed Description

HCD HAL module driver.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: HCD Exported Constants

Modules
HCD Exported Constants
HCD

Modules

HCD Speed
HCD PHY Module
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STM32F745xx HAL User Manual: HCD Exported Functions

Modules
HCD Exported Functions
HCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

HCD IO operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

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STM32F745xx HAL User Manual: HCD Exported Types

Modules
HCD Exported Types
HCD

Modules

HCD State Structure definition
HCD Handle Structure definition
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STM32F745xx HAL User Manual: HCD Handle Structure definition

Data Structures
HCD Handle Structure definition
HCD Exported Types

Data Structures

struct HCD_HandleTypeDef
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STM32F745xx HAL User Manual: HCD Private Macros

Modules
HCD Private Macros
HCD

Modules

HCD Instance definition
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STM32F745xx HAL User Manual: I2C HAL module driver

Modules
I2C HAL module driver
STM32F7xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros
I2C Private Functions

Detailed Description

I2C HAL module driver.

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STM32F745xx HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

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STM32F745xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C HAL module driver

Modules

I2C addressing mode
I2C dual addressing mode
I2C own address2 masks
I2C general call addressing mode
I2C nostretch mode
I2C Memory Address Size
I2C ReloadEndMode definition
I2C StartStopMode definition
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32F745xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C HAL module driver

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C HAL module driver

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

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STM32F745xx HAL User Manual: I2C handle Structure definition

Data Structures
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct I2C_HandleTypeDef

Detailed Description

I2C handle Structure definition.

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STM32F745xx HAL User Manual: I2CEx Exported Constants

Modules
I2CEx Exported Constants
I2C Extended HAL module driver

Modules

I2CEx Analog Filter
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STM32F745xx HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2C Extended HAL module driver

Modules

Extended features functions

Extended features functions.

Generated on Fri Nov 13 2015 11:37:31 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S_Error_Defintion

I2S Error Code.

I2S Clock Source
I2S Mode
I2S Standard
I2S Data Format
I2S Mclk Output
I2S Audio Frequency
I2S Clock Polarity
I2S Interrupts Definition
I2S Flags Definition
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STM32F745xx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

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STM32F745xx HAL User Manual: IRDA

Modules
IRDA
STM32F7xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IrDA Exported Functions
IRDA Exported Types
IRDA Exported constants

IRDA Configuration enumeration values definition.

IRDA Exported Macros
IRDA Private Constants
IRDA Private Macros
IRDA Private Functions

Detailed Description

HAL IRDA module driver.

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STM32F745xx HAL User Manual: IRDA Exported constants

Modules
IRDA Exported constants
IRDA

IRDA Configuration enumeration values definition. More...

Modules

IRDA Error Code

IRDA Error Code.

IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA State
IRDA Mode
IRDA One Bit
IRDA DMA Tx
IRDA DMA Rx
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupt definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA IT CLEAR Flags
IRDA Request Parameters

Detailed Description

IRDA Configuration enumeration values definition.

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STM32F745xx HAL User Manual: IRDAEx

Modules
IRDAEx
STM32F7xx_HAL_Driver

Modules

IRDAEx Extended Exported Constants
IRDAEx Private Macros
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IRDAEx Extended Exported Constants

Modules
IRDAEx Extended Exported Constants
IRDAEx

Modules

IRDAEx Word Length
Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG HAL module driver

Modules
IWDG HAL module driver
STM32F7xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Functions
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG HAL module driver

Modules

IWDG Prescaler
IWDG Window
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STM32F745xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG HAL module driver

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral State functions

Peripheral State functions.

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STM32F745xx HAL User Manual: LPTIM

Modules
LPTIM
STM32F7xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Private Types
LPTIM Private Defines
LPTIM Exported Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros
LPTIM Private Functions
LPTIM Private Functions Prototypes

Detailed Description

LPTIM HAL module driver.

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STM32F745xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Flag Definition
LPTIM Interrupts Definition
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STM32F745xx HAL User Manual: NAND

Modules
NAND
STM32F7xx_HAL_Driver

NAND HAL module driver. More...

Modules

NAND Exported Functions
NAND Exported Types
NAND Exported Macros
NAND Private Constants
NAND Private Macros

Detailed Description

NAND HAL module driver.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NAND Exported Functions

Modules
NAND Exported Functions
NAND

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR

Modules
NOR
STM32F7xx_HAL_Driver

NOR driver modules. More...

Modules

NOR Private Defines
NOR Exported Functions
NOR Exported Types
NOR Exported Macros
NOR Private Constants
NOR Private Macros

Detailed Description

NOR driver modules.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: NOR Exported Functions

Modules
NOR Exported Functions
NOR

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

NOR Control functions

management functions

NOR State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD

Modules
PCD
STM32F7xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

Detailed Description

PCD HAL module driver.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
Turnaround Timeout Value
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STM32F745xx HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PCD Extended Exported Functions

Modules
PCD Extended Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

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STM32F745xx HAL User Manual: PWR

Modules
PWR
STM32F7xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macro
PWR Private Constants
PWR Private Macros

Detailed Description

PWR HAL module driver.

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STM32F745xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR PVD detection level
PWR PVD Mode
PWR Regulator state in SLEEP/STOP mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Regulator Voltage Scale
PWR Flag
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STM32F745xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

Generated on Fri Nov 13 2015 11:37:32 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32F745xx HAL User Manual: PWR Private Constants

Modules
PWR Private Constants
PWR

Modules

PWR PVD Mode Mask
PWR Enable WUP Mask
PWR PVD EXTI Line
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STM32F745xx HAL User Manual: PWR Private Macros

Modules
PWR Private Macros
PWR

Modules

PWR Private macros to check input parameters
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STM32F745xx HAL User Manual: PWREx

Modules
PWREx
STM32F7xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWREx Exported Functions
PWREx Exported Constants
PWREx Exported Macro
PWREx Private Macros
PWREx_Private_Constants

Detailed Description

PWR HAL module driver.

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STM32F745xx HAL User Manual: PWREx Exported Constants

Modules
PWREx Exported Constants
PWREx

Modules

PWREx Wake Up Pins
PWREx Regulator state in UnderDrive mode
PWREx Over Under Drive Flag
PWREx Wake Up Pin Flags
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STM32F745xx HAL User Manual: PWREx Exported Functions

Modules
PWREx Exported Functions
PWREx

Modules

Peripheral Extended features functions

Peripheral Extended features functions.

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STM32F745xx HAL User Manual: PWREx Private Macros

Modules
PWREx Private Macros
PWREx

Modules

PWREx Private macros to check input parameters
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STM32F745xx HAL User Manual: QSPI

Modules
QSPI
STM32F7xx_HAL_Driver

HAL QSPI module driver. More...

Modules

QSPI Exported Functions
QSPI Exported Types
QSPI Exported Constants
QSPI Exported Macros
QSPI Private Constants
QSPI Private Macros
QSPI Private Functions

Detailed Description

HAL QSPI module driver.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: QSPI Exported Constants

Modules
QSPI Exported Constants
QSPI

Modules

QSPI Error Code
QSPI Sample Shifting
QSPI Chip Select High Time
QSPI Clock Mode
QSPI Flash Select
QSPI Dual Flash Mode
QSPI Address Size
QSPI Alternate Bytes Size
QSPI Instruction Mode
QSPI Address Mode
QSPI Alternate Bytes Mode
QSPI Data Mode
QSPI Ddr Mode
QSPI Ddr HoldHalfCycle
QSPI SIOO Mode
QSPI Match Mode
QSPI Automatic Stop
QSPI TimeOut Activation
QSPI Flags
QSPI Interrupts
QSPI Timeout definition
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STM32F745xx HAL User Manual: RCC

Modules
RCC
STM32F7xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Macros
RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Private Constants

Detailed Description

RCC HAL module driver.

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STM32F745xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Type
RCC HSE Config
RCC LSE Config
RCC HSI Config
RCC LSI Config
RCC PLL Config
PLLP Clock Divider
PLL Clock Source
RCC System Clock Type
RCC System Clock Source
System Clock Source Status
RCC AHB Clock Source
RCC APB1/APB2 Clock Source
RCC RTC Clock Source
RCC MCO Index
RCC MCO1 Clock Source
RCC MCO2 Clock Source
RCC MCO1 Clock Prescaler
RCC Interrupt
RCC Flags

Elements values convention: 0XXYYYYYb.

RCC LSE Drive configurations
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STM32F745xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

AHB1 Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

AHB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB1 peripheral clock.

APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable Status

EGet the enable or disable status of the APB2 peripheral clock.

RCC Peripheral Clock Force Release

Force or release AHB peripheral reset.

APB1 Force Release Reset

Force or release APB1 peripheral reset.

APB2 Force Release Reset

Force or release APB2 peripheral reset.

RCC Peripheral Clock Sleep Enable Disable
AHB1 Peripheral Clock Sleep Enable Disable Status

Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.

APB1 Peripheral Clock Sleep Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Clock Sleep Enable Disable Status

Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.

HSI Configuration
LSI Configuration
HSE Configuration
LSE Configuration
RTC Clock Configuration
PLL Configuration
PLL I2S Configuration
Get Clock source
RCC Extended MCOx Clock Config
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

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STM32F745xx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
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STM32F745xx HAL User Manual: RCCEx

Modules
RCCEx
STM32F7xx_HAL_Driver

RCCEx HAL module driver. More...

Modules

RCCEx Private Defines
RCCEx Private Macros
RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
Extended Peripheral Control functions

Extended Peripheral Control functions.

Detailed Description

RCCEx HAL module driver.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

RCC Periph Clock Selection
RCCEx PLLI2SP Clock Divider
RCCEx PLLSAIP Clock Divider
RCCEx PLLSAI DIVR
RCCEx I2S Clock Source
RCCEx SAI1 Clock Source
RCCEx SAI2 Clock Source
RCCEx CEC Clock Source
RCCEx USART1 Clock Source
RCCEx USART2 Clock Source
RCCEx USART3 Clock Source
RCCEx UART4 Clock Source
RCCEx UART5 Clock Source
RCCEx USART6 Clock Source
RCCEx UART7 Clock Source
RCCEx UART8 Clock Source
RCCEx I2C1 Clock Source
RCCEx I2C2 Clock Source
RCCEx I2C3 Clock Source
RCCEx I2C4 Clock Source
RCCEx LPTIM1 Clock Source
RCCEx CLK48 Clock Source
RCCEx TIM Prescaler Selection
RCCEx SDMMC1 Clock Source
Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition. More...
struct | RCC_PLLSAIInitTypeDef
PLLSAI Clock structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RCCEx Private Macros

Modules
RCCEx Private Macros
RCCEx

Modules

RCC Private macros to check input parameters
Generated on Fri Nov 13 2015 11:37:33 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG

Modules
RNG
STM32F7xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Types
RNG Private Defines
RNG Private Variables
RNG Private Constants
RNG Private Macros
RNG Private Functions Prototypes
RNG Private Functions

Detailed Description

RNG HAL module driver.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupt definition
RNG Flag definition
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG State Structure definition
RNG Handle Structure definition
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RNG Handle Structure definition

Data Structures
RNG Handle Structure definition
RNG Exported Types

Data Structures

struct RNG_HandleTypeDef
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC

Modules
RTC
STM32F7xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Functions
RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Private Constants
RTC Private Macros
RTC Private Functions

Detailed Description

RTC HAL module driver.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC AM PM Definitions
RTC DayLight Saving Definitions
RTC Store Operation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC Alarm Date WeekDay Definitions
RTC Alarm Mask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx

Modules
RTCEx
STM32F7xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Exported Functions
RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Private Constants
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTCEx Output selection Definitions
RTC Backup Registers Definitions
RTCEx Time Stamp Edges definitions
RTCEx Tamper Pins Definitions
RTCEx Tamper Interrupt Definitions
RTCEx TimeStamp Pin Selection
RTCEx Tamper Trigger Definitions
RTCEx Tamper EraseBackUp Definitions
RTCEx Tamper MaskFlag Definitions
RTCEx Tamper Filter Definitions
RTCEx Tamper Sampling Frequencies Definitions
RTCEx Tamper Pin Precharge Duration Definitions
RTCEx Tamper TimeStampOnTamperDetection Definitions
RTCEx Tamper Pull UP Definitions
RTCEx Wakeup Timer Definitions
RTCEx Smooth calib period Definitions
RTCEx Smooth calib Plus pulses Definitions
RTCEx Add 1 Second Parameter Definitions
RTCEx Calib Output selection Definitions
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

RTC TimeStamp and Tamper functions

RTC TimeStamp and Tamper functions.

RTC Wake-up functions

RTC Wake-up functions.

Extension Peripheral Control functions

Extension Peripheral Control functions.

Extended features functions

Extended features functions.

RTCEx_Exported_Functions_Group1
RTCEx_Exported_Functions_Group2
RTCEx_Exported_Functions_Group3
RTCEx_Exported_Functions_Group4
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: RTCEx Exported Types

Data Structures
RTCEx Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
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STM32F745xx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
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STM32F745xx HAL User Manual: SAI Exported Constants

Modules
SAI Exported Constants
SAI

Modules

SAI Error Code
SAI External synchronisation
SAI Supported protocol
SAI protocol data size
SAI Clock Source
SAI Audio Frequency
SAI Block Mode
SAI Block Protocol
SAI Block Data Size
SAI Block MSB LSB transmission
SAI Block Clock Strobing
SAI Block Synchronization
SAI Block Output Drive
SAI Block NoDivider
SAI Block FS Definition
SAI Block FS Polarity
SAI Block FS Offset
SAI Block Slot Size
SAI Block Slot Active
SAI Mono Stereo Mode
SAI TRIState Management
SAI Block Fifo Threshold
SAI Block Companding Mode
SAI Block Mute Value
SAI Block Interrupts Definition
SAI Block Flags Definition
SAI Block Fifo Status Level
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STM32F745xx HAL User Manual: SAIEx

Modules
SAIEx
STM32F7xx_HAL_Driver

SAI Extension HAL module driver. More...

Modules

SAI Private Functions
SAI Extended Exported Functions

Detailed Description

SAI Extension HAL module driver.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SAI Extended Exported Functions

Modules
SAI Extended Exported Functions
SAIEx

Modules

Extension features functions

Extension features functions.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD

Modules
SD
STM32F7xx_HAL_Driver

SD HAL module driver. More...

Modules

SD Private Functions
SD Exported Types
SD Exported Constants
SD Exported Macros

macros to handle interrupts and specific clock configurations

SD Exported Functions
SD Private Types
SD Private Defines
SD Private Variables
SD Private Constants
SD Private Macros
SD Private Functions Prototypes

Detailed Description

SD HAL module driver.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Exported Functions

Modules
SD Exported Functions
SD

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Data transfer functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SD Exported Types

Modules
SD Exported Types
SD

Modules

SD Handle Structure definition
Card Specific Data: CSD Register
Card Identification Data: CID Register
SD Card Status returned by ACMD13
SD Card information structure
SD Error status enumeration Structure definition
SD Transfer state enumeration structure
SD Card State enumeration structure
SD Operation enumeration structure
Generated on Fri Nov 13 2015 11:37:34 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Card Specific Data: CSD Register

Data Structures
Card Specific Data: CSD Register
SD Exported Types

Data Structures

struct HAL_SD_CSDTypedef
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STM32F745xx HAL User Manual: Card Identification Data: CID Register

Data Structures
Card Identification Data: CID Register
SD Exported Types

Data Structures

struct HAL_SD_CIDTypedef
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STM32F745xx HAL User Manual: SD Card Status returned by ACMD13

Data Structures
SD Card Status returned by ACMD13
SD Exported Types

Data Structures

struct HAL_SD_CardStatusTypedef
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STM32F745xx HAL User Manual: SD Card information structure

Data Structures
SD Card information structure
SD Exported Types

Data Structures

struct HAL_SD_CardInfoTypedef
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STM32F745xx HAL User Manual: SDRAM

Modules
SDRAM
STM32F7xx_HAL_Driver

SDRAM driver modules. More...

Modules

SDRAM Exported Functions
SDRAM Exported Types
SDRAM Exported Macros

Detailed Description

SDRAM driver modules.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SDRAM Exported Functions

Modules
SDRAM Exported Functions
SDRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Control functions

management functions

State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32F7xx_HAL_Driver

HAL USART SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Exported Types
SMARTCARD Exported constants
SMARTCARD Exported Macros
SMARTCARD Private Functions

Detailed Description

HAL USART SMARTCARD module driver.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SMARTCARD Exported constants

Modules
SMARTCARD Exported constants
SMARTCARD

Modules

SMARTCARD Error Code

SMARTCARD Error Code.

SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD OneBit Sampling
SMARTCARD NACK State
SMARTCARD Timeout Enable
SMARTCARD DMA requests
SMARTCARD Advanced Features Initialization Type
SMARTCARD Tx Inv
SMARTCARD Rx Inv
SMARTCARD Data Inv
SMARTCARD Rx Tx Swap
SMARTCARD Overrun Disable
SMARTCARD DMA Disable on Rx Error
SMARTCARD MSB First
SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupt definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

SMARTCARD IT CLEAR Flags
SMARTCARD Request Parameters
SMARTCARD CR3 SCAR CNT LSB POS
SMARTCARD GTPR GT LSBPOS
SMARTCARD RTOR BLEN LSBPOS
SMARTCARD Interruption Mask
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STM32F745xx HAL User Manual: SMARTCARDEx Exported Functions

Modules
SMARTCARDEx Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPDIFRX Exported Constants

Modules
SPDIFRX Exported Constants
SPDIFRX

Modules

SPDIFRX Error Code
SPDIFRX Input Selection
SPDIFRX Maximum Retries
SPDIFRX Wait For Activity
SPDIFRX Preamble Type Mask
SPDIFRX Channel Status Mask
SPDIFRX Validity Mask
SPDIFRX Parity Error Mask
SPDIFRX Channel Selection
SPDIFRX Data Format
SPDIFRX Stereo Mode
SPDIFRX State
SPDIFRX Interrupts Definition
SPDIFRX Flags Definition
Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI

Modules
SPI
STM32F7xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Exported Functions
Peripheral State and Errors functions

SPI control functions.

SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros
SPI Private Functions

Detailed Description

SPI HAL module driver.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB transmission
SPI TI mode
SPI CRC Calculation
SPI CRC Length

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

SPI FIFO Reception Threshold

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits).

SPI Interrupt configuration definition

SPI Interrupt definition Elements values convention: 0xXXXXXXXX.

SPI Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

SPI Transmission FIFO Status Level
SPI Reception FIFO Status Level
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STM32F745xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: SRAM

Modules
SRAM
STM32F7xx_HAL_Driver

SRAM driver modules. More...

Modules

SRAM Exported Functions
SRAM Exported Types
SRAM Exported Macros

Detailed Description

SRAM driver modules.

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STM32F745xx HAL User Manual: SRAM Exported Functions

Modules
SRAM Exported Functions
SRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input Output and memory control functions

Input Output and memory control functions.

Control functions

Control functions.

Peripheral State functions

Peripheral State functions.

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STM32F745xx HAL User Manual: STM32F7xx_HAL_Driver

Modules
STM32F7xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC driver modules.

ADCEx

ADC Extended driver modules.

ADC Exported Constants
ADC Exported Macros
ADC Private Constants
ADC Private Macros
ADC Private Functions
CAN

CAN driver modules.

CEC

HAL CEC module driver.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

DAC

DAC driver modules.

DACEx

DAC driver modules.

DCMI

DCMI HAL module driver.

DCMIEx

DCMI Extended HAL module driver.

DMA

DMA HAL module driver.

DMA2D

DMA2D HAL module driver.

DMAEx

DMA Extended HAL module driver.

ETH

ETH HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH HAL Extension module driver.

GPIO

GPIO HAL module driver.

GPIOEx
HCD

HCD HAL module driver.

I2C HAL module driver

I2C HAL module driver.

I2C Extended HAL module driver

I2C Extended HAL module driver.

I2S

I2S HAL module driver.

IRDA

HAL IRDA module driver.

IWDG HAL module driver

IWDG HAL module driver.

LPTIM

LPTIM HAL module driver.

NAND

NAND HAL module driver.

NOR

NOR driver modules.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR HAL module driver.

QSPI

HAL QSPI module driver.

RCC

RCC HAL module driver.

RCCEx

RCCEx HAL module driver.

RNG

RNG HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SAI

SAI HAL module driver.

SAIEx

SAI Extension HAL module driver.

SD

SD HAL module driver.

SDRAM

SDRAM driver modules.

SMARTCARD

HAL USART SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SPDIFRX

SPDIFRX HAL module driver.

SPI

SPI HAL module driver.

SPI Private Functions
SRAM

SRAM driver modules.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

UART

HAL UART module driver.

USART

HAL USART Synchronous module driver.

WWDG

WWDG HAL module driver.

ADC Exported Functions
IRDAEx
UARTEx
USARTEx
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM

Modules
TIM
STM32F7xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Macros
TIM Private Functions

Detailed Description

TIM HAL module driver.

Generated on Fri Nov 13 2015 11:37:35 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Input Channel Polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Output Compare State
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Output Compare N Idle State
TIM Input Capture Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM Interrupt definition
TIM Commutation Source
TIM DMA sources
TIM Event Source
TIM Flag definition
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input State
TIM Break Polarity
TIM AOE Bit State
TIM Master Mode Selection
TIM Master Slave Mode
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Selection
TIM DMA Base address
TIM DMA Burst Length
DMA Handle index
Channel CC State
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STM32F745xx HAL User Manual: TIM Private Macros

Modules
TIM Private Macros
TIM

Modules

TIM Private macros to check input parameters
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STM32F745xx HAL User Manual: TIMEx Exported Constants

Modules
TIMEx Exported Constants
TIMEx

Modules

TIMEx Channel
TIMEx Output Compare and PWM Modes
TIMEx Remap
TIMEx Clear Input Source
TIMEx Break input 2 Enable
TIMEx Break2 Polarity
TIMEx Group Channel 5 and Channel 1, 2 or 3
TIMEx Master Mode Selection 2 (TRGO2)
TIMEx Slave mode
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STM32F745xx HAL User Manual: TIM Exported Types

Data Structures
TIM Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
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STM32F745xx HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART Error Definition
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Advanced Feature AutoBaud Rate Mode
UART Receiver TimeOut
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

UART Interruption Clear Flags
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STM32F745xx HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions
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STM32F745xx HAL User Manual: UARTEx

Modules
UARTEx
STM32F7xx_HAL_Driver

Modules

UARTEx Exported Constants
UARTEx Exported Macros
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UARTEx Word Length
UARTEx WakeUp Address Length
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STM32F745xx HAL User Manual: USART

Modules
USART
STM32F7xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Exported Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Constants
USART Private Macros
USART Private Functions

Detailed Description

HAL USART Synchronous module driver.

Generated on Fri Nov 13 2015 11:37:36 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Code

USART Error Code.

USART Number of Stop Bits
USART Parity
USART Mode
USART Over Sampling
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
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STM32F745xx HAL User Manual: USARTEx

Modules
USARTEx
STM32F7xx_HAL_Driver

Modules

USARTEx Exported Constants
USARTEx Private Macros
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
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STM32F745xx HAL User Manual: WWDG

Modules
WWDG
STM32F7xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Exported Macros
WWDG Private Constants
WWDG Private Macros
WWDG Private Functions

Detailed Description

WWDG HAL module driver.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Nov 13 2015 11:37:37 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • Initialization/de-initialization functions
  • Peripheral Control functions
  • Peripheral State functions
  • STM32F7xx_HAL_Driver
    • HAL
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
      • HAL Exported Macros
      • HAL Private Variables
      • HAL Private Constants
    • ADC
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • ADC Peripheral State functions
      • ADC Private Functions
      • ADC Exported Types
      • ADC Exported Constants
        • ADC Error Code
        • ADC Clock Prescaler
        • ADC Delay Between 2 Sampling Phases
        • ADC Resolution
        • ADC External Trigger Edge Regular
        • ADC External Trigger Source Regular
        • ADC Data Align
        • ADC Common Channels
        • ADC Sampling Times
        • ADC EOC Selection
        • ADC Event Type
        • ADC Analog Watchdog Selection
        • ADC Interrupts Definition
        • ADC Flags Definition
        • ADC Channels Type
      • ADC Exported Macros
      • ADC Private Constants
      • ADC Private Macros
    • ADCEx
      • ADC Exported Functions
        • Extended features functions
      • ADC Exported Types
      • ADC Private Functions
    • ADC Exported Constants
      • ADC Common Mode
      • ADC Direct Memory Access Mode For Multi Mode
      • ADC External Trigger Edge Injected
      • ADC External Trigger Source Injected
      • ADC Injected Channel Selection
      • ADC Specific Channels
    • ADC Exported Macros
    • ADC Private Constants
    • ADC Private Macros
    • ADC Private Functions
    • CAN
      • CAN Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • CAN Exported Types
      • CAN Exported Constants
        • HAL CAN Error Code
        • CAN InitStatus
        • CAN Operating Mode
        • CAN Synchronisation Jump Width
        • CAN Time Quantum in bit segment 1
        • CAN Time Quantum in bit segment 2
        • CAN Filter Mode
        • CAN Filter Scale
        • CAN Filter FIFO
        • CAN Identifier Type
        • CAN Remote Transmission Request
        • CAN Receive FIFO Number Constants
        • CAN Flags
        • CAN Interrupts
        • CAN Mailboxes Definition
      • CAN Exported Macros
      • CAN Private Types
      • CAN Private Variables
      • CAN Private Constants
      • CAN Private Macros
      • CAN Private Functions
    • CEC
      • CEC Private Constants
      • CEC Private Functions
      • CEC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control function
      • CEC Exported Types
      • CEC Exported Constants
        • CEC Error Code
        • CEC Signal Free Time setting parameter
        • CEC Receiver Tolerance
        • CEC Reception Stop on Error
        • CEC Error Bit Generation if Bit Rise Error reported
        • CEC Error Bit Generation if Long Bit Period Error reported
        • CEC Error Bit Generation on Broadcast message
        • CEC Signal Free Time start option
        • CEC Listening mode option
        • CEC Device Own Address position in CEC CFGR register
        • CEC Initiator logical address position in message header
        • CEC Interrupts definition
        • CEC Flags definition
        • CEC all RX or TX errors flags
        • CEC all RX errors interrupts enabling flag
        • CEC all TX errors interrupts enabling flag
      • CEC Exported Macros
      • CEC Private Types
      • CEC Private Variables
      • CEC Private Macros
    • CORTEX
      • CORTEX Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • Cortex Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX _SysTick clock source
        • MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Private Macros
      • CORTEX Private Functions
    • CRC
      • CRC Exported Functions
        • Initialization/de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
        • CRC State Structure definition
        • CRC Init Structure definition
        • CRC Handle Structure definition
      • CRC exported constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the IP
        • CRC polynomial possible sizes actual definitions
        • CRC input buffer format
      • CRC exported macros
      • CRC Private Types
      • CRC Private Defines
      • CRC Private Variables
      • CRC Private Constants
      • CRC Private Macros
      • CRC Private Functions Prototypes
      • CRC Private Functions
    • CRCEx
      • CRC Extended exported constants
        • CRC Extended input data inversion modes
        • CRC Extended output data inversion modes
      • CRC Extended exported macros
      • CRC Extended Exported Functions
        • Extended CRC features functions
    • DAC
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC Trigger Selection
        • DAC Output Buffer
        • DAC Channel Selection
        • DAC Data Alignment
        • DAC Flags Definition
        • DAC IT Definition
      • DAC Exported Macros
      • DAC Private Constants
      • DAC Private Macros
      • DAC Private Functions
    • DACEx
      • DAC Exported Functions
        • Extended features functions
      • DAC Exported Constants
        • DAC LFS Run Mask Triangle Amplitude
      • DAC Private Constants
      • DAC Private Macros
      • DAC Private Functions
    • DCMI
      • DCMI Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
        • DCMI Private Functions
      • DCMI Exported Types
      • DCMI Exported Constants
        • DCMI Error Code
        • DCMI Capture Mode
        • DCMI Synchronization Mode
        • DCMI PIXCK Polarity
        • DCMI VSYNC Polarity
        • DCMI HSYNC Polarity
        • DCMI MODE JPEG
        • DCMI Capture Rate
        • DCMI Extended Data Mode
        • DCMI Window Coordinate
        • DCMI Window Height
        • DCMI interrupt sources
        • DCMI Flags
      • DCMI Exported Macros
      • DCMI Private Macros
      • DCMI Private Functions
    • DCMIEx
      • DCMIEx Exported Functions
        • Initialization and Configuration functions
      • DCMIEx Exported Types
      • DCMIEx Exported Constants
        • DCMIEx Byte Select Mode
        • DCMIEx Byte Select Start
        • DCMIEx Line Select Mode
        • DCMIEx Line Select Start
      • DCMIEx Private Macros
    • DMA
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA Channel selection
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA FIFO direct mode
        • DMA FIFO threshold level
        • DMA Memory burst
        • DMA Peripheral burst
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • I/O operation functions
        • Peripheral State functions
      • DMA Private Constants
      • DMA Private Macros
      • DMA Private Functions
    • DMA2D
      • DMA2D Exported Types
      • DMA2D Exported Constants
        • DMA2D Error Code
        • DMA2D Mode
        • DMA2D Color Mode
        • DMA2D COLOR VALUE
        • DMA2D SIZE
        • DMA2D Offset
        • DMA2D Input Color Mode
        • DMA2D ALPHA MODE
        • DMA2D CLUT CM
        • DMA2D Size Clut
        • DMA2D DeadTime
        • DMA2D Interrupts
        • DMA2D Flag
      • DMA2D Exported Macros
      • DMA2D Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • DMA2D Private Types
      • DMA2D Private Defines
      • DMA2D Private Variables
      • DMA2D Private Constants
      • DMA2D Private Macros
      • DMA2D Private Functions Prototypes
      • DMA2D Private Functions
    • DMAEx
      • DMAEx Exported Types
      • DMAEx Exported Functions
        • Extended features functions
      • DMAEx Private Functions
    • ETH
      • ETH Private Constants
      • ETH Private Functions
      • ETH Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ETH Exported Types
      • ETH Exported Constants
        • ETH Buffers setting
        • ETH DMA TX Descriptor
        • ETH DMA RX Descriptor
        • ETH AutoNegotiation
        • ETH Speed
        • ETH Duplex Mode
        • ETH Rx Mode
        • ETH Checksum Mode
        • ETH Media Interface
        • ETH Watchdog
        • ETH Jabber
        • ETH Inter Frame Gap
        • ETH Carrier Sense
        • ETH Receive Own
        • ETH Loop Back Mode
        • ETH Checksum Offload
        • ETH Retry Transmission
        • ETH Automatic Pad CRC Strip
        • ETH Back Off Limit
        • ETH Deferral Check
        • ETH Receive All
        • ETH Source Addr Filter
        • ETH Pass Control Frames
        • ETH Broadcast Frames Reception
        • ETH Destination Addr Filter
        • ETH Promiscuous Mode
        • ETH Multicast Frames Filter
        • ETH Unicast Frames Filter
        • ETH Zero Quanta Pause
        • ETH Pause Low Threshold
        • ETH Unicast Pause Frame Detect
        • ETH Receive Flow Control
        • ETH Transmit Flow Control
        • ETH VLAN Tag Comparison
        • ETH MAC addresses
        • ETH MAC addresses filter SA DA
        • ETH MAC addresses filter Mask bytes
        • ETH MAC Debug flags
        • ETH Drop TCP IP Checksum Error Frame
        • ETH Receive Store Forward
        • ETH Flush Received Frame
        • ETH Transmit Store Forward
        • ETH Transmit Threshold Control
        • ETH Forward Error Frames
        • ETH Forward Undersized Good Frames
        • ETH Receive Threshold Control
        • ETH Second Frame Operate
        • ETH Address Aligned Beats
        • ETH Fixed Burst
        • ETH Rx DMA Burst Length
        • ETH Tx DMA Burst Length
        • ETH DMA Enhanced descriptor format
        • ETH DMA Arbitration
        • ETH DMA Tx descriptor segment
        • ETH DMA Tx descriptor Checksum Insertion Control
        • ETH DMA Rx descriptor buffers
        • ETH PMT Flags
        • ETH MMC Tx Interrupts
        • ETH MMC Rx Interrupts
        • ETH MAC Flags
        • ETH DMA Flags
        • ETH MAC Interrupts
        • ETH DMA Interrupts
        • ETH DMA transmit process state
        • ETH DMA receive process state
        • ETH DMA overflow
        • ETH EXTI LINE WAKEUP
      • ETH Exported Macros
      • ETH_Private_Macros
      • ETH_Private_Defines
    • FLASH
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error Code
        • FLASH Type Program
        • FLASH Flag definition
        • FLASH Interrupt definition
        • FLASH Program Parallelism
        • FLASH Keys
      • FLASH Exported Macros
      • FLASH Private Variables
      • FLASH Private Constants
      • FLASH Private Macros
        • FLASH Private macros to check input parameters
      • FLASH Private Functions
    • FLASHEx
      • FLASHEx Exported Functions
        • Extended IO operation functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Type Erase
        • FLASH Voltage Range
        • FLASH WRP State
        • FLASH Option Type
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes WWatchdog
        • FLASH Option Bytes IWatchdog
        • FLASH Option Bytes nRST_STOP
        • FLASH Option Bytes nRST_STDBY
        • FLASH IWDG Counter Freeze in STOP
        • FLASH IWDG Counter Freeze in STANDBY
        • FLASH BOR Reset Level
        • FLASH Boot Address
        • FLASH Latency
        • FLASH Mass Erase bit
        • FLASH Sectors
        • FLASH Option Bytes Write Protection
      • FLASH Private Constants
      • FLASH Private Macros
        • FLASH Private macros to check input parameters
      • FLASH Private Functions
      • FLASHEx_Private_Variables
    • GPIO
      • GPIO Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins define
        • GPIO mode define
        • GPIO speed define
        • GPIO pull define
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Private Functions
    • GPIOEx
      • GPIO Exported Constants
        • GPIO Alternate Function Selection
      • GPIO Exported Macros
      • GPIO Exported Functions
      • GPIO Private Constants
      • GPIO Private Macros
        • GPIO Get Port Index
        • GPIO Check Alternate Function
      • GPIO Private Functions
    • HCD
      • HCD Private Functions
      • HCD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • HCD Exported Types
        • HCD State Structure definition
        • HCD Handle Structure definition
      • HCD Exported Constants
        • HCD Speed
        • HCD PHY Module
      • HCD Exported Macros
      • HCD Private Macros
        • HCD Instance definition
      • HCD Private Functions Prototypes
    • I2C HAL module driver
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C addressing mode
        • I2C dual addressing mode
        • I2C own address2 masks
        • I2C general call addressing mode
        • I2C nostretch mode
        • I2C Memory Address Size
        • I2C ReloadEndMode definition
        • I2C StartStopMode definition
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
      • I2C Private Functions
    • I2C Extended HAL module driver
      • I2C Extended Exported Functions
        • Extended features functions
      • I2CEx Exported Constants
        • I2CEx Analog Filter
      • I2C Private Constants
      • I2C Private Macros
      • I2C Private Functions
    • I2S
      • I2S Private Functions
      • I2S Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Errors functions
      • I2S Exported Types
      • I2S Exported Constants
        • I2S_Error_Defintion
        • I2S Clock Source
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S Mclk Output
        • I2S Audio Frequency
        • I2S Clock Polarity
        • I2S Interrupts Definition
        • I2S Flags Definition
      • I2S Exported Macros
      • I2S Private Constants
      • I2S Private Macros
    • IRDA
      • IrDA Exported Functions
        • IrDA Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
      • IRDA Exported Types
      • IRDA Exported constants
        • IRDA Error Code
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA State
        • IRDA Mode
        • IRDA One Bit
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Flags
        • IRDA Interrupt definition
        • IRDA IT CLEAR Flags
        • IRDA Request Parameters
      • IRDA Exported Macros
      • IRDA Private Constants
        • IRDA Interruption Mask
      • IRDA Private Macros
      • IRDA Private Functions
    • IWDG HAL module driver
      • IWDG Private Defines
      • IWDG Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window
      • IWDG Exported Macros
      • IWDG Private Macros
    • LPTIM
      • LPTIM Private Types
      • LPTIM Private Defines
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler
        • Peripheral State functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Flag Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
      • LPTIM Private Functions
      • LPTIM Private Functions Prototypes
    • NAND
      • NAND Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Peripheral Control functions
        • Peripheral State functions
      • NAND Exported Types
      • NAND Exported Macros
      • NAND Private Constants
      • NAND Private Macros
    • NOR
      • NOR Private Defines
      • NOR Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • NOR Control functions
        • NOR State functions
      • NOR Exported Types
      • NOR Exported Macros
      • NOR Private Constants
      • NOR Private Macros
    • PCD
      • PCD Private Macros
        • PCD Instance definition
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • Turnaround Timeout Value
      • PCD Exported Macros
    • PCDEx
      • PCD Extended Exported Functions
        • Peripheral Control functions
    • PWR
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • PWR Exported Types
      • PWR Exported Constants
        • PWR PVD detection level
        • PWR PVD Mode
        • PWR Regulator state in SLEEP/STOP mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Regulator Voltage Scale
        • PWR Flag
      • PWR Exported Macro
      • PWR Private Constants
        • PWR PVD Mode Mask
        • PWR Enable WUP Mask
        • PWR PVD EXTI Line
      • PWR Private Macros
        • PWR Private macros to check input parameters
    • PWREx
      • PWREx Exported Functions
        • Peripheral Extended features functions
      • PWREx Exported Constants
        • PWREx Wake Up Pins
        • PWREx Regulator state in UnderDrive mode
        • PWREx Over Under Drive Flag
        • PWREx Wake Up Pin Flags
      • PWREx Exported Macro
      • PWREx Private Macros
        • PWREx Private macros to check input parameters
      • PWREx_Private_Constants
    • QSPI
      • QSPI Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
        • Peripheral Control and State functions
        • QSPI_Exported_Functions_Group4
      • QSPI Exported Types
      • QSPI Exported Constants
        • QSPI Error Code
        • QSPI Sample Shifting
        • QSPI Chip Select High Time
        • QSPI Clock Mode
        • QSPI Flash Select
        • QSPI Dual Flash Mode
        • QSPI Address Size
        • QSPI Alternate Bytes Size
        • QSPI Instruction Mode
        • QSPI Address Mode
        • QSPI Alternate Bytes Mode
        • QSPI Data Mode
        • QSPI Ddr Mode
        • QSPI Ddr HoldHalfCycle
        • QSPI SIOO Mode
        • QSPI Match Mode
        • QSPI Automatic Stop
        • QSPI TimeOut Activation
        • QSPI Flags
        • QSPI Interrupts
        • QSPI Timeout definition
      • QSPI Exported Macros
      • QSPI Private Constants
      • QSPI Private Macros
        • QSPI Clock Prescaler
        • QSPI Fifo Threshold
        • QSPI Flash Size
        • QSPI Instruction
        • QSPI Dummy Cycles
        • QSPI Interval
        • QSPI Status Bytes Size
        • QSPI TimeOut Period
      • QSPI Private Functions
    • RCC
      • RCC Private Macros
        • RCC Private macros to check input parameters
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • Oscillator Type
        • RCC HSE Config
        • RCC LSE Config
        • RCC HSI Config
        • RCC LSI Config
        • RCC PLL Config
        • PLLP Clock Divider
        • PLL Clock Source
        • RCC System Clock Type
        • RCC System Clock Source
        • System Clock Source Status
        • RCC AHB Clock Source
        • RCC APB1/APB2 Clock Source
        • RCC RTC Clock Source
        • RCC MCO Index
        • RCC MCO1 Clock Source
        • RCC MCO2 Clock Source
        • RCC MCO1 Clock Prescaler
        • RCC Interrupt
        • RCC Flags
        • RCC LSE Drive configurations
      • RCC Exported Macros
        • AHB1 Peripheral Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enable Disable Status
        • APB1 Peripheral Clock Enable Disable Status
        • APB2 Peripheral Clock Enable Disable Status
        • RCC Peripheral Clock Force Release
        • APB1 Force Release Reset
        • APB2 Force Release Reset
        • RCC Peripheral Clock Sleep Enable Disable
        • AHB1 Peripheral Clock Sleep Enable Disable Status
        • APB1 Peripheral Clock Sleep Enable Disable Status
        • APB2 Peripheral Clock Sleep Enable Disable Status
        • HSI Configuration
        • LSI Configuration
        • HSE Configuration
        • LSE Configuration
        • RTC Clock Configuration
        • PLL Configuration
        • PLL I2S Configuration
        • Get Clock source
        • RCC Extended MCOx Clock Config
        • Flags Interrupts Management
      • RCC Private Constants
        • RCC BitAddress Alias
    • RCCEx
      • RCCEx Private Defines
      • RCCEx Private Macros
        • RCC Private macros to check input parameters
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • RCC Periph Clock Selection
        • RCCEx PLLI2SP Clock Divider
        • RCCEx PLLSAIP Clock Divider
        • RCCEx PLLSAI DIVR
        • RCCEx I2S Clock Source
        • RCCEx SAI1 Clock Source
        • RCCEx SAI2 Clock Source
        • RCCEx CEC Clock Source
        • RCCEx USART1 Clock Source
        • RCCEx USART2 Clock Source
        • RCCEx USART3 Clock Source
        • RCCEx UART4 Clock Source
        • RCCEx UART5 Clock Source
        • RCCEx USART6 Clock Source
        • RCCEx UART7 Clock Source
        • RCCEx UART8 Clock Source
        • RCCEx I2C1 Clock Source
        • RCCEx I2C2 Clock Source
        • RCCEx I2C3 Clock Source
        • RCCEx I2C4 Clock Source
        • RCCEx LPTIM1 Clock Source
        • RCCEx CLK48 Clock Source
        • RCCEx TIM Prescaler Selection
        • RCCEx SDMMC1 Clock Source
      • RCCEx Exported Macros
        • RCCEx_Peripheral_Clock_Enable_Disable
        • Peripheral Clock Enable Disable Status
        • RCCEx Force Release Peripheral Reset
        • RCCEx Peripheral Clock Sleep Enable Disable
        • AHB/APB Peripheral Clock Sleep Enable Disable Status
      • Extended Peripheral Control functions
    • RNG
      • RNG Exported Types
        • RNG State Structure definition
        • RNG Handle Structure definition
      • RNG Exported Constants
        • RNG Interrupt definition
        • RNG Flag definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • RNG Private Types
      • RNG Private Defines
      • RNG Private Variables
      • RNG Private Constants
      • RNG Private Macros
      • RNG Private Functions Prototypes
      • RNG Private Functions
    • RTC
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
        • RTC_Exported_Functions_Group1
        • RTC_Exported_Functions_Group2
        • RTC_Exported_Functions_Group3
        • RTC_Exported_Functions_Group4
        • RTC_Exported_Functions_Group5
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC AM PM Definitions
        • RTC DayLight Saving Definitions
        • RTC Store Operation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC Alarm Date WeekDay Definitions
        • RTC Alarm Mask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
      • RTC Exported Macros
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTCEx Exported Functions
        • RTC TimeStamp and Tamper functions
        • RTC Wake-up functions
        • Extension Peripheral Control functions
        • Extended features functions
        • RTCEx_Exported_Functions_Group1
        • RTCEx_Exported_Functions_Group2
        • RTCEx_Exported_Functions_Group3
        • RTCEx_Exported_Functions_Group4
      • RTCEx Exported Types
      • RTCEx Exported Constants
        • RTCEx Output selection Definitions
        • RTC Backup Registers Definitions
        • RTCEx Time Stamp Edges definitions
        • RTCEx Tamper Pins Definitions
        • RTCEx Tamper Interrupt Definitions
        • RTCEx TimeStamp Pin Selection
        • RTCEx Tamper Trigger Definitions
        • RTCEx Tamper EraseBackUp Definitions
        • RTCEx Tamper MaskFlag Definitions
        • RTCEx Tamper Filter Definitions
        • RTCEx Tamper Sampling Frequencies Definitions
        • RTCEx Tamper Pin Precharge Duration Definitions
        • RTCEx Tamper TimeStampOnTamperDetection Definitions
        • RTCEx Tamper Pull UP Definitions
        • RTCEx Wakeup Timer Definitions
        • RTCEx Smooth calib period Definitions
        • RTCEx Smooth calib Plus pulses Definitions
        • RTCEx Add 1 Second Parameter Definitions
        • RTCEx Calib Output selection Definitions
      • RTCEx Exported Macros
      • RTCEx Private Constants
      • RTCEx Private Macros
        • Private macros to check input parameters
    • SAI
      • SAI Private Typedefs
      • SAI Private Constants
      • SAI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SAI Exported Types
      • SAI Exported Constants
        • SAI Error Code
        • SAI External synchronisation
        • SAI Supported protocol
        • SAI protocol data size
        • SAI Clock Source
        • SAI Audio Frequency
        • SAI Block Mode
        • SAI Block Protocol
        • SAI Block Data Size
        • SAI Block MSB LSB transmission
        • SAI Block Clock Strobing
        • SAI Block Synchronization
        • SAI Block Output Drive
        • SAI Block NoDivider
        • SAI Block FS Definition
        • SAI Block FS Polarity
        • SAI Block FS Offset
        • SAI Block Slot Size
        • SAI Block Slot Active
        • SAI Mono Stereo Mode
        • SAI TRIState Management
        • SAI Block Fifo Threshold
        • SAI Block Companding Mode
        • SAI Block Mute Value
        • SAI Block Interrupts Definition
        • SAI Block Flags Definition
        • SAI Block Fifo Status Level
      • SAI Exported Macros
      • SAI Private Types
      • SAI Private Variables
      • SAI Private Functions
      • SAI_Private_Macros
    • SAIEx
      • SAI Private Functions
      • SAI Extended Exported Functions
        • Extension features functions
    • SD
      • SD Private Functions
      • SD Exported Types
        • SD Handle Structure definition
        • Card Specific Data: CSD Register
        • Card Identification Data: CID Register
        • SD Card Status returned by ACMD13
        • SD Card information structure
        • SD Error status enumeration Structure definition
        • SD Transfer state enumeration structure
        • SD Card State enumeration structure
        • SD Operation enumeration structure
      • SD Exported Constants
      • SD Exported Macros
      • SD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • SD Private Types
      • SD Private Defines
      • SD Private Variables
      • SD Private Constants
      • SD Private Macros
      • SD Private Functions Prototypes
    • SDRAM
      • SDRAM Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Control functions
        • State functions
      • SDRAM Exported Types
      • SDRAM Exported Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • SmartCard Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported constants
        • SMARTCARD Error Code
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD OneBit Sampling
        • SMARTCARD NACK State
        • SMARTCARD Timeout Enable
        • SMARTCARD DMA requests
        • SMARTCARD Advanced Features Initialization Type
        • SMARTCARD Tx Inv
        • SMARTCARD Rx Inv
        • SMARTCARD Data Inv
        • SMARTCARD Rx Tx Swap
        • SMARTCARD Overrun Disable
        • SMARTCARD DMA Disable on Rx Error
        • SMARTCARD MSB First
        • SMARTCARD Flags
        • SMARTCARD Interrupt definition
        • SMARTCARD IT CLEAR Flags
        • SMARTCARD Request Parameters
        • SMARTCARD CR3 SCAR CNT LSB POS
        • SMARTCARD GTPR GT LSBPOS
        • SMARTCARD RTOR BLEN LSBPOS
        • SMARTCARD Interruption Mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Functions
    • SMARTCARDEx
      • SMARTCARDEx Exported Functions
        • Extended Peripheral Control functions
    • SPDIFRX
      • SPDIFRX Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPDIFRX Exported Types
      • SPDIFRX Exported Constants
        • SPDIFRX Error Code
        • SPDIFRX Input Selection
        • SPDIFRX Maximum Retries
        • SPDIFRX Wait For Activity
        • SPDIFRX Preamble Type Mask
        • SPDIFRX Channel Status Mask
        • SPDIFRX Validity Mask
        • SPDIFRX Parity Error Mask
        • SPDIFRX Channel Selection
        • SPDIFRX Data Format
        • SPDIFRX Stereo Mode
        • SPDIFRX State
        • SPDIFRX Interrupts Definition
        • SPDIFRX Flags Definition
      • SPDIFRX Exported Macros
      • SPDIFRX Private Macros
      • SPDIFRX Private Functions
    • SPI
      • SPI Private Constants
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB transmission
        • SPI TI mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI FIFO Reception Threshold
        • SPI Interrupt configuration definition
        • SPI Flag definition
        • SPI Transmission FIFO Status Level
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
      • SPI Private Functions
    • SPI Private Functions
    • SRAM
      • SRAM Exported Functions
        • Initialization and de-initialization functions
        • Input Output and memory control functions
        • Control functions
        • Peripheral State functions
      • SRAM Exported Types
      • SRAM Exported Macros
    • TIM
      • TIM Exported Functions
        • Time Base functions
        • Time Output Compare functions
        • Time PWM functions
        • Time Input Capture functions
        • Time One Pulse functions
        • Time Encoder functions
        • TIM IRQ handler management
        • Peripheral Control functions
        • TIM Callbacks functions
        • Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Input Channel Polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Output Compare N Idle State
        • TIM Input Capture Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM Interrupt definition
        • TIM Commutation Source
        • TIM DMA sources
        • TIM Event Source
        • TIM Flag definition
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input State
        • TIM Break Polarity
        • TIM AOE Bit State
        • TIM Master Mode Selection
        • TIM Master Slave Mode
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Selection
        • TIM DMA Base address
        • TIM DMA Burst Length
        • DMA Handle index
        • Channel CC State
      • TIM Exported Macros
      • TIM Private Macros
        • TIM Private macros to check input parameters
      • TIM Private Functions
    • TIMEx
      • TIMEx Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIM Exported Types
      • TIMEx Exported Constants
        • TIMEx Channel
        • TIMEx Output Compare and PWM Modes
        • TIMEx Remap
        • TIMEx Clear Input Source
        • TIMEx Break input 2 Enable
        • TIMEx Break2 Polarity
        • TIMEx Group Channel 5 and Channel 1, 2 or 3
        • TIMEx Master Mode Selection 2 (TRGO2)
        • TIMEx Slave mode
      • TIMEx Exported Macros
      • TIMEx Private Macros
      • TIMEx Private Functions
    • UART
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Exported Types
      • UART Exported Constants
        • UART Error Definition
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver TimeOut
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
      • UART Exported Macros
      • UART Private Macros
      • UART Private Functions
    • USART
      • USART Exported Functions
        • USART Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Code
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Over Sampling
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
      • USART Exported Macros
      • USART Private Constants
      • USART Private Macros
      • USART Private Functions
    • WWDG
      • WWDG Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
      • WWDG Exported Macros
      • WWDG Private Constants
      • WWDG Private Macros
      • WWDG Private Functions
    • ADC Exported Functions
      • Extended features functions
    • IRDAEx
      • IRDAEx Extended Exported Constants
        • IRDAEx Word Length
      • IRDAEx Private Macros
    • UARTEx
      • UARTEx Exported Constants
        • UARTEx Word Length
        • UARTEx WakeUp Address Length
      • UARTEx Exported Macros
    • USARTEx
      • USARTEx Exported Constants
        • USARTEx Word Length
      • USARTEx Private Macros
Generated on Fri Nov 13 2015 11:37:38 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal.c Source File

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stm32f7xx_hal.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   HAL module driver.
00008   *          This is the common part of the HAL initialization
00009   *
00010   @verbatim
00011   ==============================================================================
00012                      ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015     The common HAL driver contains a set of generic and common APIs that can be
00016     used by the PPP peripheral drivers and the user to start using the HAL.
00017     [..]
00018     The HAL contains two APIs' categories:
00019          (+) Common HAL APIs
00020          (+) Services HAL APIs
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32f7xx_hal.h"
00055
00056 /** @addtogroup STM32F7xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup HAL HAL
00061   * @brief HAL module driver.
00062   * @{
00063   */
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 /** @addtogroup HAL_Private_Constants
00068   * @{
00069   */
00070 /**
00071  * @brief STM32F7xx HAL Driver version number V1.0.3
00072    */
00073 #define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
00074 #define __STM32F7xx_HAL_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
00075 #define __STM32F7xx_HAL_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
00076 #define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
00077 #define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
00078                                         |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
00079                                         |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
00080                                         |(__STM32F7xx_HAL_VERSION_RC))
00081
00082 #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
00083 /**
00084   * @}
00085   */
00086
00087 /* Private macro -------------------------------------------------------------*/
00088 /* Private variables ---------------------------------------------------------*/
00089 /** @addtogroup HAL_Private_Variables
00090   * @{
00091   */
00092 static __IO uint32_t uwTick;
00093 /**
00094   * @}
00095   */
00096
00097 /* Private function prototypes -----------------------------------------------*/
00098 /* Private functions ---------------------------------------------------------*/
00099
00100 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00101   * @{
00102   */
00103
00104 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00105  *  @brief    Initialization and de-initialization functions
00106  *
00107 @verbatim
00108  ===============================================================================
00109               ##### Initialization and de-initialization functions #####
00110  ===============================================================================
00111     [..]  This section provides functions allowing to:
00112       (+) Initializes the Flash interface the NVIC allocation and initial clock
00113           configuration. It initializes the systick also when timeout is needed
00114           and the backup domain when enabled.
00115       (+) de-Initializes common part of the HAL
00116       (+) Configure The time base source to have 1ms time base with a dedicated
00117           Tick interrupt priority.
00118         (++) Systick timer is used by default as source of time base, but user
00119              can eventually implement his proper time base source (a general purpose
00120              timer for example or other time source), keeping in mind that Time base
00121              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00122              handled in milliseconds basis.
00123         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00124              at the beginning of the program after reset by HAL_Init() or at any time
00125              when clock is configured, by HAL_RCC_ClockConfig().
00126         (++) Source of time base is configured  to generate interrupts at regular
00127              time intervals. Care must be taken if HAL_Delay() is called from a
00128              peripheral ISR process, the Tick interrupt line must have higher priority
00129             (numerically lower) than the peripheral interrupt. Otherwise the caller
00130             ISR process will be blocked.
00131        (++) functions affecting time base configurations are declared as __weak
00132              to make  override possible  in case of other  implementations in user file.
00133 @endverbatim
00134   * @{
00135   */
00136
00137 /**
00138   * @brief  This function is used to initialize the HAL Library; it must be the first
00139   *         instruction to be executed in the main program (before to call any other
00140   *         HAL function), it performs the following:
00141   *           Configure the Flash prefetch, and instruction cache through ART accelerator.
00142   *           Configures the SysTick to generate an interrupt each 1 millisecond,
00143   *           which is clocked by the HSI (at this stage, the clock is not yet
00144   *           configured and thus the system is running from the internal HSI at 16 MHz).
00145   *           Set NVIC Group Priority to 4.
00146   *           Calls the HAL_MspInit() callback function defined in user file
00147   *           "stm32f7xx_hal_msp.c" to do the global low level hardware initialization
00148   *
00149   * @note   SysTick is used as time base for the HAL_Delay() function, the application
00150   *         need to ensure that the SysTick time base is always set to 1 millisecond
00151   *         to have correct HAL operation.
00152   * @retval HAL status
00153   */
00154 HAL_StatusTypeDef HAL_Init(void)
00155 {
00156   /* Configure Flash prefetch and Instruction cache through ART accelerator */
00157 #if (ART_ACCLERATOR_ENABLE != 0)
00158    __HAL_FLASH_ART_ENABLE();
00159 #endif /* ART_ACCLERATOR_ENABLE */
00160
00161   /* Set Interrupt Group Priority */
00162   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00163
00164   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
00165   HAL_InitTick(TICK_INT_PRIORITY);
00166
00167   /* Init the low level hardware */
00168   HAL_MspInit();
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  This function de-Initializes common part of the HAL and stops the systick.
00176   *         This function is optional.
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_DeInit(void)
00180 {
00181   /* Reset of all peripherals */
00182   __HAL_RCC_APB1_FORCE_RESET();
00183   __HAL_RCC_APB1_RELEASE_RESET();
00184
00185   __HAL_RCC_APB2_FORCE_RESET();
00186   __HAL_RCC_APB2_RELEASE_RESET();
00187
00188   __HAL_RCC_AHB1_FORCE_RESET();
00189   __HAL_RCC_AHB1_RELEASE_RESET();
00190
00191   __HAL_RCC_AHB2_FORCE_RESET();
00192   __HAL_RCC_AHB2_RELEASE_RESET();
00193
00194   __HAL_RCC_AHB3_FORCE_RESET();
00195   __HAL_RCC_AHB3_RELEASE_RESET();
00196
00197   /* De-Init the low level hardware */
00198   HAL_MspDeInit();
00199
00200   /* Return function status */
00201   return HAL_OK;
00202 }
00203
00204 /**
00205   * @brief  Initializes the MSP.
00206   * @retval None
00207   */
00208 __weak void HAL_MspInit(void)
00209 {
00210   /* Prevent unused argument(s) compilation warning */
00211 __IO uint32_t tmpreg = 0x00;
00212   UNUSED(tmpreg);
00213   /* NOTE : This function Should not be modified, when the callback is needed,
00214             the HAL_MspInit could be implemented in the user file
00215    */
00216 }
00217
00218 /**
00219   * @brief  DeInitializes the MSP.
00220   * @retval None
00221   */
00222 __weak void HAL_MspDeInit(void)
00223 {
00224   /* Prevent unused argument(s) compilation warning */
00225 __IO uint32_t tmpreg = 0x00;
00226   UNUSED(tmpreg);
00227   /* NOTE : This function Should not be modified, when the callback is needed,
00228             the HAL_MspDeInit could be implemented in the user file
00229    */
00230 }
00231
00232 /**
00233   * @brief This function configures the source of the time base.
00234   *        The time source is configured  to have 1ms time base with a dedicated
00235   *        Tick interrupt priority.
00236   * @note This function is called  automatically at the beginning of program after
00237   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00238   * @note In the default implementation, SysTick timer is the source of time base.
00239   *       It is used to generate interrupts at regular time intervals.
00240   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00241   *       The the SysTick interrupt must have higher priority (numerically lower)
00242   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00243   *       The function is declared as __weak  to be overwritten  in case of other
00244   *       implementation  in user file.
00245   * @param TickPriority: Tick interrupt priority.
00246   * @retval HAL status
00247   */
00248 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00249 {
00250   /*Configure the SysTick to have interrupt in 1ms time basis*/
00251   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
00252
00253   /*Configure the SysTick IRQ priority */
00254   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
00255
00256   /* Return function status */
00257   return HAL_OK;
00258 }
00259
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00265  *  @brief    HAL Control functions
00266  *
00267 @verbatim
00268  ===============================================================================
00269                       ##### HAL Control functions #####
00270  ===============================================================================
00271     [..]  This section provides functions allowing to:
00272       (+) Provide a tick value in millisecond
00273       (+) Provide a blocking delay in millisecond
00274       (+) Suspend the time base source interrupt
00275       (+) Resume the time base source interrupt
00276       (+) Get the HAL API driver version
00277       (+) Get the device identifier
00278       (+) Get the device revision identifier
00279       (+) Enable/Disable Debug module during SLEEP mode
00280       (+) Enable/Disable Debug module during STOP mode
00281       (+) Enable/Disable Debug module during STANDBY mode
00282
00283 @endverbatim
00284   * @{
00285   */
00286
00287 /**
00288   * @brief This function is called to increment  a global variable "uwTick"
00289   *        used as application time base.
00290   * @note In the default implementation, this variable is incremented each 1ms
00291   *       in Systick ISR.
00292  * @note This function is declared as __weak to be overwritten in case of other
00293   *      implementations in user file.
00294   * @retval None
00295   */
00296 __weak void HAL_IncTick(void)
00297 {
00298   uwTick++;
00299 }
00300
00301 /**
00302   * @brief Provides a tick value in millisecond.
00303   * @note This function is declared as __weak to be overwritten in case of other
00304   *       implementations in user file.
00305   * @retval tick value
00306   */
00307 __weak uint32_t HAL_GetTick(void)
00308 {
00309   return uwTick;
00310 }
00311
00312 /**
00313   * @brief This function provides accurate delay (in milliseconds) based
00314   *        on variable incremented.
00315   * @note In the default implementation , SysTick timer is the source of time base.
00316   *       It is used to generate interrupts at regular time intervals where uwTick
00317   *       is incremented.
00318   * @note This function is declared as __weak to be overwritten in case of other
00319   *       implementations in user file.
00320   * @param Delay: specifies the delay time length, in milliseconds.
00321   * @retval None
00322   */
00323 __weak void HAL_Delay(__IO uint32_t Delay)
00324 {
00325   uint32_t tickstart = 0;
00326   tickstart = HAL_GetTick();
00327   while((HAL_GetTick() - tickstart) < Delay)
00328   {
00329   }
00330 }
00331
00332 /**
00333   * @brief Suspend Tick increment.
00334   * @note In the default implementation , SysTick timer is the source of time base. It is
00335   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00336   *       is called, the SysTick interrupt will be disabled and so Tick increment
00337   *       is suspended.
00338   * @note This function is declared as __weak to be overwritten in case of other
00339   *       implementations in user file.
00340   * @retval None
00341   */
00342 __weak void HAL_SuspendTick(void)
00343 {
00344   /* Disable SysTick Interrupt */
00345   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00346 }
00347
00348 /**
00349   * @brief Resume Tick increment.
00350   * @note In the default implementation , SysTick timer is the source of time base. It is
00351   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00352   *       is called, the SysTick interrupt will be enabled and so Tick increment
00353   *       is resumed.
00354   * @note This function is declared as __weak to be overwritten in case of other
00355   *       implementations in user file.
00356   * @retval None
00357   */
00358 __weak void HAL_ResumeTick(void)
00359 {
00360   /* Enable SysTick Interrupt */
00361   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
00362 }
00363
00364 /**
00365   * @brief  Returns the HAL revision
00366   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00367   */
00368 uint32_t HAL_GetHalVersion(void)
00369 {
00370  return __STM32F7xx_HAL_VERSION;
00371 }
00372
00373 /**
00374   * @brief  Returns the device revision identifier.
00375   * @retval Device revision identifier
00376   */
00377 uint32_t HAL_GetREVID(void)
00378 {
00379    return((DBGMCU->IDCODE) >> 16);
00380 }
00381
00382 /**
00383   * @brief  Returns the device identifier.
00384   * @retval Device identifier
00385   */
00386 uint32_t HAL_GetDEVID(void)
00387 {
00388    return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
00389 }
00390
00391 /**
00392   * @brief  Enable the Debug Module during SLEEP mode
00393   * @retval None
00394   */
00395 void HAL_DBGMCU_EnableDBGSleepMode(void)
00396 {
00397   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00398 }
00399
00400 /**
00401   * @brief  Disable the Debug Module during SLEEP mode
00402   * @retval None
00403   */
00404 void HAL_DBGMCU_DisableDBGSleepMode(void)
00405 {
00406   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00407 }
00408
00409 /**
00410   * @brief  Enable the Debug Module during STOP mode
00411   * @retval None
00412   */
00413 void HAL_DBGMCU_EnableDBGStopMode(void)
00414 {
00415   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00416 }
00417
00418 /**
00419   * @brief  Disable the Debug Module during STOP mode
00420   * @retval None
00421   */
00422 void HAL_DBGMCU_DisableDBGStopMode(void)
00423 {
00424   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00425 }
00426
00427 /**
00428   * @brief  Enable the Debug Module during STANDBY mode
00429   * @retval None
00430   */
00431 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00432 {
00433   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00434 }
00435
00436 /**
00437   * @brief  Disable the Debug Module during STANDBY mode
00438   * @retval None
00439   */
00440 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00441 {
00442   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00443 }
00444
00445 /**
00446   * @brief  Enables the I/O Compensation Cell.
00447   * @note   The I/O compensation cell can be used only when the device supply
00448   *         voltage ranges from 2.4 to 3.6 V.
00449   * @retval None
00450   */
00451 void HAL_EnableCompensationCell(void)
00452 {
00453   SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
00454 }
00455
00456 /**
00457   * @brief  Power-down the I/O Compensation Cell.
00458   * @note   The I/O compensation cell can be used only when the device supply
00459   *         voltage ranges from 2.4 to 3.6 V.
00460   * @retval None
00461   */
00462 void HAL_DisableCompensationCell(void)
00463 {
00464   SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
00465 }
00466
00467 /**
00468   * @brief  Enables the FMC Memory Mapping Swapping.
00469   *
00470   * @note   SDRAM is accessible at 0x60000000
00471   *         and NOR/RAM is accessible at 0xC0000000
00472   *
00473   * @retval None
00474   */
00475 void HAL_EnableFMCMemorySwapping(void)
00476 {
00477   SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
00478 }
00479
00480 /**
00481   * @brief  Disables the FMC Memory Mapping Swapping
00482   *
00483   * @note   SDRAM is accessible at 0xC0000000 (default mapping)
00484   *         and NOR/RAM is accessible at 0x60000000 (default mapping)
00485   *
00486   * @retval None
00487   */
00488 void HAL_DisableFMCMemorySwapping(void)
00489 {
00490
00491   SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
00492 }
00493
00494 /**
00495   * @}
00496   */
00497
00498 /**
00499   * @}
00500   */
00501
00502 /**
00503   * @}
00504   */
00505
00506 /**
00507   * @}
00508   */
00509
00510 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal.h Source File

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  • Inc
stm32f7xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   This file contains all the functions prototypes for the HAL
00008   *          module driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32F7xx_HAL_H
00041 #define __STM32F7xx_HAL_H
00042
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_conf.h"
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HAL
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /* Exported macro ------------------------------------------------------------*/
00061 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00062   * @{
00063   */
00064
00065 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00066   */
00067 #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
00068 #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
00069 #define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
00070 #define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
00071 #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
00072 #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
00073 #define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
00074 #define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
00075 #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
00076 #define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
00077 #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
00078 #define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
00079 #define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
00080 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
00081 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
00082 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
00083 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
00084 #define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
00085 #define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
00086 #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
00087 #define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
00088 #define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
00089 #define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
00090 #define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
00091
00092 #define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
00093 #define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
00094 #define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
00095 #define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
00096 #define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
00097 #define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
00098 #define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
00099 #define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
00100 #define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
00101 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
00102 #define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
00103 #define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
00104 #define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
00105 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
00106 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
00107 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
00108 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
00109 #define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
00110 #define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
00111 #define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
00112 #define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
00113 #define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
00114 #define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
00115 #define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
00116
00117
00118 /** @brief  FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000
00119   */
00120 #define __HAL_SYSCFG_REMAPMEMORY_FMC()          (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
00121
00122
00123 /** @brief  FMC/SDRAM  mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000
00124   */
00125 #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
00126                                           SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
00127                                          }while(0);
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions --------------------------------------------------------*/
00133 /** @addtogroup HAL_Exported_Functions
00134   * @{
00135   */
00136 /** @addtogroup HAL_Exported_Functions_Group1
00137   * @{
00138   */
00139 /* Initialization and de-initialization functions  ******************************/
00140 HAL_StatusTypeDef HAL_Init(void);
00141 HAL_StatusTypeDef HAL_DeInit(void);
00142 void HAL_MspInit(void);
00143 void HAL_MspDeInit(void);
00144 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00145 /**
00146   * @}
00147   */
00148
00149 /** @addtogroup HAL_Exported_Functions_Group2
00150   * @{
00151   */
00152 /* Peripheral Control functions  ************************************************/
00153 void HAL_IncTick(void);
00154 void HAL_Delay(__IO uint32_t Delay);
00155 uint32_t HAL_GetTick(void);
00156 void HAL_SuspendTick(void);
00157 void HAL_ResumeTick(void);
00158 uint32_t HAL_GetHalVersion(void);
00159 uint32_t HAL_GetREVID(void);
00160 uint32_t HAL_GetDEVID(void);
00161 void HAL_DBGMCU_EnableDBGSleepMode(void);
00162 void HAL_DBGMCU_DisableDBGSleepMode(void);
00163 void HAL_DBGMCU_EnableDBGStopMode(void);
00164 void HAL_DBGMCU_DisableDBGStopMode(void);
00165 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00166 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00167 void HAL_EnableCompensationCell(void);
00168 void HAL_DisableCompensationCell(void);
00169 void HAL_EnableFMCMemorySwapping(void);
00170 void HAL_DisableFMCMemorySwapping(void);
00171 /**
00172   * @}
00173   */
00174
00175 /**
00176   * @}
00177   */
00178 /* Private types -------------------------------------------------------------*/
00179 /* Private variables ---------------------------------------------------------*/
00180 /** @defgroup HAL_Private_Variables HAL Private Variables
00181   * @{
00182   */
00183 /**
00184   * @}
00185   */
00186 /* Private constants ---------------------------------------------------------*/
00187 /** @defgroup HAL_Private_Constants HAL Private Constants
00188   * @{
00189   */
00190 /**
00191   * @}
00192   */
00193 /* Private macros ------------------------------------------------------------*/
00194 /* Private functions ---------------------------------------------------------*/
00195 /**
00196   * @}
00197   */
00198
00199 /**
00200   * @}
00201   */
00202
00203 #ifdef __cplusplus
00204 }
00205 #endif
00206
00207 #endif /* __STM32F7xx_HAL_H */
00208
00209 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc.c Source File

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stm32f7xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + State and errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### ADC Peripheral features #####
00016   ==============================================================================
00017   [..]
00018   (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00019   (#) Interrupt generation at the end of conversion, end of injected conversion,
00020       and in case of analog watchdog or overrun events
00021   (#) Single and continuous conversion modes.
00022   (#) Scan mode for automatic conversion of channel 0 to channel x.
00023   (#) Data alignment with in-built data coherency.
00024   (#) Channel-wise programmable sampling time.
00025   (#) External trigger option with configurable polarity for both regular and
00026       injected conversion.
00027   (#) Dual/Triple mode (on devices with 2 ADCs or more).
00028   (#) Configurable DMA data storage in Dual/Triple ADC mode.
00029   (#) Configurable delay between conversions in Dual/Triple interleaved mode.
00030   (#) ADC conversion type (refer to the datasheets).
00031   (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
00032       slower speed.
00033   (#) ADC input range: VREF(minus) = VIN = VREF(plus).
00034   (#) DMA request generation during regular channel conversion.
00035
00036
00037                      ##### How to use this driver #####
00038   ==============================================================================
00039   [..]
00040   (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
00041        (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
00042        (##) ADC pins configuration
00043              (+++) Enable the clock for the ADC GPIOs using the following function:
00044                    __HAL_RCC_GPIOx_CLK_ENABLE()
00045              (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
00046        (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
00047              (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
00048              (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
00049              (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
00050        (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
00051              (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
00052              (+++) Configure and enable two DMA streams stream for managing data
00053                  transfer from peripheral to memory (output stream)
00054              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00055                  using  __HAL_LINKDMA()
00056              (+++) Configure the priority and enable the NVIC for the transfer complete
00057                  interrupt on the two DMA Streams. The output stream should have higher
00058                  priority than the input stream.
00059
00060     *** Configuration of ADC, groups regular/injected, channels parameters ***
00061   ==============================================================================
00062   [..]
00063   (#) Configure the ADC parameters (resolution, data alignment, ...)
00064       and regular group parameters (conversion trigger, sequencer, ...)
00065       using function HAL_ADC_Init().
00066
00067   (#) Configure the channels for regular group parameters (channel number,
00068       channel rank into sequencer, ..., into regular group)
00069       using function HAL_ADC_ConfigChannel().
00070
00071   (#) Optionally, configure the injected group parameters (conversion trigger,
00072       sequencer, ..., of injected group)
00073       and the channels for injected group parameters (channel number,
00074       channel rank into sequencer, ..., into injected group)
00075       using function HAL_ADCEx_InjectedConfigChannel().
00076
00077   (#) Optionally, configure the analog watchdog parameters (channels
00078       monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
00079
00080   (#) Optionally, for devices with several ADC instances: configure the
00081       multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
00082
00083                        *** Execution of ADC conversions ***
00084   ==============================================================================
00085   [..]
00086   (#) ADC driver can be used among three modes: polling, interruption,
00087       transfer by DMA.
00088
00089      *** Polling mode IO operation ***
00090      =================================
00091      [..]
00092        (+) Start the ADC peripheral using HAL_ADC_Start()
00093        (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
00094            user can specify the value of timeout according to his end application
00095        (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
00096        (+) Stop the ADC peripheral using HAL_ADC_Stop()
00097
00098      *** Interrupt mode IO operation ***
00099      ===================================
00100      [..]
00101        (+) Start the ADC peripheral using HAL_ADC_Start_IT()
00102        (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
00103        (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
00104            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
00105        (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
00106            add his own code by customization of function pointer HAL_ADC_ErrorCallback
00107        (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
00108
00109      *** DMA mode IO operation ***
00110      ==============================
00111      [..]
00112        (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
00113            of data to be transferred at each end of conversion
00114        (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
00115            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
00116        (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
00117            add his own code by customization of function pointer HAL_ADC_ErrorCallback
00118        (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
00119
00120      *** ADC HAL driver macros list ***
00121      =============================================
00122      [..]
00123        Below the list of most used macros in ADC HAL driver.
00124
00125       (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
00126       (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
00127       (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
00128       (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
00129       (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
00130       (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
00131       (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
00132       (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
00133
00134      [..]
00135        (@) You can refer to the ADC HAL driver header file for more useful macros
00136
00137                       *** Deinitialization of ADC ***
00138   ==============================================================================
00139   [..]
00140   (#) Disable the ADC interface
00141      (++) ADC clock can be hard reset and disabled at RCC top level.
00142      (++) Hard reset of ADC peripherals
00143           using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
00144      (++) ADC clock disable using the equivalent macro/functions as configuration step.
00145                (+++) Example:
00146                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00147                    other device clock parameters configuration:
00148                (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
00149                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
00150                (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
00151                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
00152
00153   (#) ADC pins configuration
00154      (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00155
00156   (#) Optionally, in case of usage of ADC with interruptions:
00157      (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
00158
00159   (#) Optionally, in case of usage of DMA:
00160         (++) Deinitialize the DMA using function HAL_DMA_DeInit().
00161         (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
00162
00163     @endverbatim
00164   ******************************************************************************
00165   * @attention
00166   *
00167   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00168   *
00169   * Redistribution and use in source and binary forms, with or without modification,
00170   * are permitted provided that the following conditions are met:
00171   *   1. Redistributions of source code must retain the above copyright notice,
00172   *      this list of conditions and the following disclaimer.
00173   *   2. Redistributions in binary form must reproduce the above copyright notice,
00174   *      this list of conditions and the following disclaimer in the documentation
00175   *      and/or other materials provided with the distribution.
00176   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00177   *      may be used to endorse or promote products derived from this software
00178   *      without specific prior written permission.
00179   *
00180   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00181   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00182   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00183   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00184   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00185   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00186   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00187   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00188   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00189   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00190   *
00191   ******************************************************************************
00192   */
00193
00194 /* Includes ------------------------------------------------------------------*/
00195 #include "stm32f7xx_hal.h"
00196
00197 /** @addtogroup STM32F7xx_HAL_Driver
00198   * @{
00199   */
00200
00201 /** @defgroup ADC ADC
00202   * @brief ADC driver modules
00203   * @{
00204   */
00205
00206 #ifdef HAL_ADC_MODULE_ENABLED
00207
00208 /* Private typedef -----------------------------------------------------------*/
00209 /* Private define ------------------------------------------------------------*/
00210 /* Private macro -------------------------------------------------------------*/
00211 /* Private variables ---------------------------------------------------------*/
00212 /** @addtogroup ADC_Private_Functions
00213   * @{
00214   */
00215 /* Private function prototypes -----------------------------------------------*/
00216 static void ADC_Init(ADC_HandleTypeDef* hadc);
00217 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00218 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
00219 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00220 /**
00221   * @}
00222   */
00223
00224 /* Exported functions --------------------------------------------------------*/
00225 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00226   * @{
00227   */
00228
00229 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00230  *  @brief    Initialization and Configuration functions
00231  *
00232 @verbatim
00233  ===============================================================================
00234               ##### Initialization and de-initialization functions #####
00235  ===============================================================================
00236     [..]  This section provides functions allowing to:
00237       (+) Initialize and configure the ADC.
00238       (+) De-initialize the ADC.
00239
00240 @endverbatim
00241   * @{
00242   */
00243
00244 /**
00245   * @brief  Initializes the ADCx peripheral according to the specified parameters
00246   *         in the ADC_InitStruct and initializes the ADC MSP.
00247   *
00248   * @note   This function is used to configure the global features of the ADC (
00249   *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
00250   *         the rest of the configuration parameters are specific to the regular
00251   *         channels group (scan mode activation, continuous mode activation,
00252   *         External trigger source and edge, DMA continuous request after the
00253   *         last transfer and End of conversion selection).
00254   *
00255   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00256   *         the configuration information for the specified ADC.
00257   * @retval HAL status
00258   */
00259 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00260 {
00261   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00262
00263   /* Check ADC handle */
00264   if(hadc == NULL)
00265   {
00266     return HAL_ERROR;
00267   }
00268
00269   /* Check the parameters */
00270   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00271   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00272   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00273   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
00274   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00275   assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
00276   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00277   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
00278   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00279   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
00280   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00281
00282   if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00283   {
00284     assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00285   }
00286
00287   if(hadc->State == HAL_ADC_STATE_RESET)
00288   {
00289     /* Initialize ADC error code */
00290     ADC_CLEAR_ERRORCODE(hadc);
00291
00292     /* Allocate lock resource and initialize it */
00293     hadc->Lock = HAL_UNLOCKED;
00294     /* Init the low level hardware */
00295     HAL_ADC_MspInit(hadc);
00296   }
00297
00298   /* Configuration of ADC parameters if previous preliminary actions are      */
00299   /* correctly completed.                                                     */
00300   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00301   {
00302     /* Set ADC state */
00303     ADC_STATE_CLR_SET(hadc->State,
00304                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00305                       HAL_ADC_STATE_BUSY_INTERNAL);
00306
00307     /* Set ADC parameters */
00308     ADC_Init(hadc);
00309
00310     /* Set ADC error code to none */
00311     ADC_CLEAR_ERRORCODE(hadc);
00312
00313     /* Set the ADC state */
00314     ADC_STATE_CLR_SET(hadc->State,
00315                       HAL_ADC_STATE_BUSY_INTERNAL,
00316                       HAL_ADC_STATE_READY);
00317   }
00318   else
00319   {
00320     tmp_hal_status = HAL_ERROR;
00321   }
00322
00323   /* Release Lock */
00324   __HAL_UNLOCK(hadc);
00325
00326   /* Return function status */
00327   return tmp_hal_status;
00328 }
00329
00330 /**
00331   * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
00332   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00333   *         the configuration information for the specified ADC.
00334   * @retval HAL status
00335   */
00336 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00337 {
00338   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00339
00340   /* Check ADC handle */
00341   if(hadc == NULL)
00342   {
00343     return HAL_ERROR;
00344   }
00345
00346   /* Check the parameters */
00347   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00348
00349   /* Set ADC state */
00350   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00351
00352   /* Stop potential conversion on going, on regular and injected groups */
00353   /* Disable ADC peripheral */
00354   __HAL_ADC_DISABLE(hadc);
00355
00356   /* Configuration of ADC parameters if previous preliminary actions are      */
00357   /* correctly completed.                                                     */
00358   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00359   {
00360     /* DeInit the low level hardware */
00361     HAL_ADC_MspDeInit(hadc);
00362
00363     /* Set ADC error code to none */
00364     ADC_CLEAR_ERRORCODE(hadc);
00365
00366     /* Set ADC state */
00367     hadc->State = HAL_ADC_STATE_RESET;
00368   }
00369
00370   /* Process unlocked */
00371   __HAL_UNLOCK(hadc);
00372
00373   /* Return function status */
00374   return tmp_hal_status;
00375 }
00376
00377 /**
00378   * @brief  Initializes the ADC MSP.
00379   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00380   *         the configuration information for the specified ADC.
00381   * @retval None
00382   */
00383 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00384 {
00385   /* Prevent unused argument(s) compilation warning */
00386   UNUSED(hadc);
00387   /* NOTE : This function Should not be modified, when the callback is needed,
00388             the HAL_ADC_MspInit could be implemented in the user file
00389    */
00390 }
00391
00392 /**
00393   * @brief  DeInitializes the ADC MSP.
00394   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00395   *         the configuration information for the specified ADC.
00396   * @retval None
00397   */
00398 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00399 {
00400   /* Prevent unused argument(s) compilation warning */
00401   UNUSED(hadc);
00402   /* NOTE : This function Should not be modified, when the callback is needed,
00403             the HAL_ADC_MspDeInit could be implemented in the user file
00404    */
00405 }
00406
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
00412  *  @brief    IO operation functions
00413  *
00414 @verbatim
00415  ===============================================================================
00416              ##### IO operation functions #####
00417  ===============================================================================
00418     [..]  This section provides functions allowing to:
00419       (+) Start conversion of regular channel.
00420       (+) Stop conversion of regular channel.
00421       (+) Start conversion of regular channel and enable interrupt.
00422       (+) Stop conversion of regular channel and disable interrupt.
00423       (+) Start conversion of regular channel and enable DMA transfer.
00424       (+) Stop conversion of regular channel and disable DMA transfer.
00425       (+) Handle ADC interrupt request.
00426
00427 @endverbatim
00428   * @{
00429   */
00430
00431 /**
00432   * @brief  Enables ADC and starts conversion of the regular channels.
00433   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00434   *         the configuration information for the specified ADC.
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00438 {
00439   __IO uint32_t counter = 0;
00440
00441   /* Check the parameters */
00442   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00443   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00444
00445   /* Process locked */
00446   __HAL_LOCK(hadc);
00447
00448   /* Enable the ADC peripheral */
00449   /* Check if ADC peripheral is disabled in order to enable it and wait during
00450   Tstab time the ADC's stabilization */
00451   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00452   {
00453     /* Enable the Peripheral */
00454     __HAL_ADC_ENABLE(hadc);
00455
00456     /* Delay for ADC stabilization time */
00457     /* Compute number of CPU cycles to wait for */
00458     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
00459     while(counter != 0)
00460     {
00461       counter--;
00462     }
00463   }
00464
00465   /* Start conversion if ADC is effectively enabled */
00466   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00467   {
00468     /* Set ADC state                                                          */
00469     /* - Clear state bitfield related to regular group conversion results     */
00470     /* - Set state bitfield related to regular group operation                */
00471     ADC_STATE_CLR_SET(hadc->State,
00472                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
00473                       HAL_ADC_STATE_REG_BUSY);
00474
00475     /* If conversions on group regular are also triggering group injected,    */
00476     /* update ADC state.                                                      */
00477     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00478     {
00479       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00480     }
00481
00482     /* State machine update: Check if an injected conversion is ongoing */
00483     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00484     {
00485       /* Reset ADC error code fields related to conversions on group regular */
00486       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00487     }
00488     else
00489     {
00490       /* Reset ADC all error code fields */
00491       ADC_CLEAR_ERRORCODE(hadc);
00492     }
00493
00494     /* Process unlocked */
00495     /* Unlock before starting ADC conversions: in case of potential           */
00496     /* interruption, to let the process to ADC IRQ Handler.                   */
00497     __HAL_UNLOCK(hadc);
00498
00499     /* Clear regular group conversion flag and overrun flag */
00500     /* (To ensure of no unknown state from potential previous ADC operations) */
00501     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00502
00503     /* Check if Multimode enabled */
00504     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00505     {
00506       /* if no external trigger present enable software conversion of regular channels */
00507       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00508       {
00509         /* Enable the selected ADC software conversion for regular group */
00510         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00511       }
00512     }
00513     else
00514     {
00515       /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
00516       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
00517       {
00518         /* Enable the selected ADC software conversion for regular group */
00519           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00520       }
00521     }
00522   }
00523
00524   /* Return function status */
00525   return HAL_OK;
00526 }
00527
00528 /**
00529   * @brief  Disables ADC and stop conversion of regular channels.
00530   *
00531   * @note   Caution: This function will stop also injected channels.
00532   *
00533   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00534   *         the configuration information for the specified ADC.
00535   *
00536   * @retval HAL status.
00537   */
00538 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
00539 {
00540   /* Check the parameters */
00541   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00542
00543   /* Process locked */
00544   __HAL_LOCK(hadc);
00545
00546   /* Stop potential conversion on going, on regular and injected groups */
00547   /* Disable ADC peripheral */
00548   __HAL_ADC_DISABLE(hadc);
00549
00550   /* Check if ADC is effectively disabled */
00551   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00552   {
00553     /* Set ADC state */
00554     ADC_STATE_CLR_SET(hadc->State,
00555                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00556                       HAL_ADC_STATE_READY);
00557   }
00558
00559   /* Process unlocked */
00560   __HAL_UNLOCK(hadc);
00561
00562   /* Return function status */
00563   return HAL_OK;
00564 }
00565
00566 /**
00567   * @brief  Poll for regular conversion complete
00568   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
00569   *         conversion) are cleared by this function.
00570   * @note   This function cannot be used in a particular setup: ADC configured
00571   *         in DMA mode and polling for end of each conversion (ADC init
00572   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
00573   *         In this case, DMA resets the flag EOC and polling cannot be
00574   *         performed on each conversion. Nevertheless, polling can still
00575   *         be performed on the complete sequence.
00576   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00577   *         the configuration information for the specified ADC.
00578   * @param  Timeout: Timeout value in millisecond.
00579   * @retval HAL status
00580   */
00581 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00582 {
00583   uint32_t tickstart = 0;
00584
00585   /* Verification that ADC configuration is compliant with polling for      */
00586   /* each conversion:                                                       */
00587   /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
00588   /* several ranks and polling for end of each conversion.                  */
00589   /* For code simplicity sake, this particular case is generalized to       */
00590   /* ADC configured in DMA mode and polling for end of each conversion.     */
00591   if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
00592       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
00593   {
00594     /* Update ADC state machine to error */
00595     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00596
00597     /* Process unlocked */
00598     __HAL_UNLOCK(hadc);
00599
00600     return HAL_ERROR;
00601   }
00602
00603   /* Get tick */
00604   tickstart = HAL_GetTick();
00605
00606   /* Check End of conversion flag */
00607   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
00608   {
00609     /* Check if timeout is disabled (set to infinite wait) */
00610     if(Timeout != HAL_MAX_DELAY)
00611     {
00612       if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
00613       {
00614         /* Update ADC state machine to timeout */
00615         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00616
00617         /* Process unlocked */
00618         __HAL_UNLOCK(hadc);
00619
00620         return HAL_TIMEOUT;
00621       }
00622     }
00623   }
00624
00625   /* Clear regular group conversion flag */
00626   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
00627
00628   /* Update ADC state machine */
00629   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
00630
00631   /* Determine whether any further conversion upcoming on group regular       */
00632   /* by external trigger, continuous mode or scan sequence on going.          */
00633   /* Note: On STM32F7, there is no independent flag of end of sequence.       */
00634   /*       The test of scan sequence on going is done either with scan        */
00635   /*       sequence disabled or with end of conversion flag set to            */
00636   /*       of end of sequence.                                                */
00637   if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
00638      (hadc->Init.ContinuousConvMode == DISABLE)            &&
00639      (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
00640       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
00641   {
00642     /* Set ADC state */
00643     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00644
00645     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00646     {
00647       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00648     }
00649   }
00650
00651   /* Return ADC state */
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @brief  Poll for conversion event
00657   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00658   *         the configuration information for the specified ADC.
00659   * @param  EventType: the ADC event type.
00660   *          This parameter can be one of the following values:
00661   *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
00662   *            @arg ADC_OVR_EVENT: ADC Overrun event.
00663   * @param  Timeout: Timeout value in millisecond.
00664   * @retval HAL status
00665   */
00666 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
00667 {
00668   uint32_t tickstart = 0;
00669
00670   /* Check the parameters */
00671   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00672   assert_param(IS_ADC_EVENT_TYPE(EventType));
00673
00674   /* Get tick */
00675   tickstart = HAL_GetTick();
00676
00677   /* Check selected event flag */
00678   while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
00679   {
00680     /* Check for the Timeout */
00681     if(Timeout != HAL_MAX_DELAY)
00682     {
00683       if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
00684       {
00685         /* Update ADC state machine to timeout */
00686         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00687
00688         /* Process unlocked */
00689         __HAL_UNLOCK(hadc);
00690
00691         return HAL_TIMEOUT;
00692       }
00693     }
00694   }
00695
00696   /* Analog watchdog (level out of window) event */
00697   if(EventType == ADC_AWD_EVENT)
00698   {
00699     /* Set ADC state */
00700     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
00701
00702     /* Clear ADC analog watchdog flag */
00703     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
00704   }
00705   /* Overrun event */
00706   else
00707   {
00708     /* Set ADC state */
00709     SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
00710     /* Set ADC error code to overrun */
00711     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
00712
00713     /* Clear ADC overrun flag */
00714     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
00715   }
00716
00717   /* Return ADC state */
00718   return HAL_OK;
00719 }
00720
00721
00722 /**
00723   * @brief  Enables the interrupt and starts ADC conversion of regular channels.
00724   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00725   *         the configuration information for the specified ADC.
00726   * @retval HAL status.
00727   */
00728 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
00729 {
00730   __IO uint32_t counter = 0;
00731
00732   /* Check the parameters */
00733   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00734   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00735
00736   /* Process locked */
00737   __HAL_LOCK(hadc);
00738
00739   /* Enable the ADC peripheral */
00740   /* Check if ADC peripheral is disabled in order to enable it and wait during
00741      Tstab time the ADC's stabilization */
00742   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00743   {
00744     /* Enable the Peripheral */
00745     __HAL_ADC_ENABLE(hadc);
00746
00747     /* Delay for ADC stabilization time */
00748     /* Compute number of CPU cycles to wait for */
00749     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
00750     while(counter != 0)
00751     {
00752       counter--;
00753     }
00754   }
00755
00756   /* Start conversion if ADC is effectively enabled */
00757   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00758   {
00759     /* Set ADC state                                                          */
00760     /* - Clear state bitfield related to regular group conversion results     */
00761     /* - Set state bitfield related to regular group operation                */
00762     ADC_STATE_CLR_SET(hadc->State,
00763                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
00764                       HAL_ADC_STATE_REG_BUSY);
00765
00766     /* If conversions on group regular are also triggering group injected,    */
00767     /* update ADC state.                                                      */
00768     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00769     {
00770       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00771     }
00772
00773     /* State machine update: Check if an injected conversion is ongoing */
00774     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00775     {
00776       /* Reset ADC error code fields related to conversions on group regular */
00777       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00778     }
00779     else
00780     {
00781       /* Reset ADC all error code fields */
00782       ADC_CLEAR_ERRORCODE(hadc);
00783     }
00784
00785     /* Process unlocked */
00786     /* Unlock before starting ADC conversions: in case of potential           */
00787     /* interruption, to let the process to ADC IRQ Handler.                   */
00788     __HAL_UNLOCK(hadc);
00789
00790     /* Clear regular group conversion flag and overrun flag */
00791     /* (To ensure of no unknown state from potential previous ADC operations) */
00792     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00793
00794     /* Enable end of conversion interrupt for regular group */
00795     __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
00796
00797     /* Check if Multimode enabled */
00798     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00799     {
00800       /* if no external trigger present enable software conversion of regular channels */
00801       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00802       {
00803         /* Enable the selected ADC software conversion for regular group */
00804         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00805       }
00806     }
00807     else
00808     {
00809       /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
00810       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
00811       {
00812         /* Enable the selected ADC software conversion for regular group */
00813           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00814       }
00815     }
00816   }
00817
00818   /* Return function status */
00819   return HAL_OK;
00820 }
00821
00822 /**
00823   * @brief  Disables the interrupt and stop ADC conversion of regular channels.
00824   *
00825   * @note   Caution: This function will stop also injected channels.
00826   *
00827   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00828   *         the configuration information for the specified ADC.
00829   * @retval HAL status.
00830   */
00831 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
00832 {
00833   /* Check the parameters */
00834   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00835
00836   /* Process locked */
00837   __HAL_LOCK(hadc);
00838
00839   /* Stop potential conversion on going, on regular and injected groups */
00840   /* Disable ADC peripheral */
00841   __HAL_ADC_DISABLE(hadc);
00842
00843   /* Check if ADC is effectively disabled */
00844   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00845   {
00846     /* Set ADC state */
00847     ADC_STATE_CLR_SET(hadc->State,
00848                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00849                       HAL_ADC_STATE_READY);
00850   }
00851
00852   /* Process unlocked */
00853   __HAL_UNLOCK(hadc);
00854
00855   /* Return function status */
00856   return HAL_OK;
00857 }
00858
00859 /**
00860   * @brief  Handles ADC interrupt request
00861   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00862   *         the configuration information for the specified ADC.
00863   * @retval None
00864   */
00865 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
00866 {
00867   uint32_t tmp1 = 0, tmp2 = 0;
00868
00869   /* Check the parameters */
00870   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00871   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
00872   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
00873
00874   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
00875   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
00876   /* Check End of conversion flag for regular channels */
00877   if(tmp1 && tmp2)
00878   {
00879     /* Update state machine on conversion status if not in error state */
00880     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00881     {
00882       /* Set ADC state */
00883       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
00884     }
00885
00886     /* Determine whether any further conversion upcoming on group regular   */
00887     /* by external trigger, continuous mode or scan sequence on going.      */
00888     /* Note: On STM32F7, there is no independent flag of end of sequence.   */
00889     /*       The test of scan sequence on going is done either with scan    */
00890     /*       sequence disabled or with end of conversion flag set to        */
00891     /*       of end of sequence.                                            */
00892     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
00893        (hadc->Init.ContinuousConvMode == DISABLE)            &&
00894        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
00895         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
00896     {
00897       /* Disable ADC end of single conversion interrupt on group regular */
00898       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
00899       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
00900       /* by overrun IRQ process below.                                      */
00901       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
00902
00903       /* Set ADC state */
00904       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00905
00906       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00907       {
00908         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00909       }
00910     }
00911
00912     /* Conversion complete callback */
00913     HAL_ADC_ConvCpltCallback(hadc);
00914
00915     /* Clear regular group conversion flag */
00916     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
00917   }
00918
00919   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
00920   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
00921   /* Check End of conversion flag for injected channels */
00922   if(tmp1 && tmp2)
00923   {
00924     /* Update state machine on conversion status if not in error state */
00925     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00926     {
00927       /* Set ADC state */
00928       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00929     }
00930
00931     /* Determine whether any further conversion upcoming on group injected  */
00932     /* by external trigger, scan sequence on going or by automatic injected */
00933     /* conversion from group regular (same conditions as group regular      */
00934     /* interruption disabling above).                                       */
00935     if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
00936        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
00937         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
00938        (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
00939        (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
00940        (hadc->Init.ContinuousConvMode == DISABLE))))
00941     {
00942       /* Disable ADC end of single conversion interrupt on group injected */
00943       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00944
00945       /* Set ADC state */
00946       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00947
00948       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00949       {
00950         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00951       }
00952     }
00953
00954     /* Conversion complete callback */
00955     HAL_ADCEx_InjectedConvCpltCallback(hadc);
00956
00957     /* Clear injected group conversion flag */
00958     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
00959   }
00960
00961   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
00962   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
00963   /* Check Analog watchdog flag */
00964   if(tmp1 && tmp2)
00965   {
00966     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
00967     {
00968       /* Set ADC state */
00969       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
00970
00971       /* Level out of window callback */
00972       HAL_ADC_LevelOutOfWindowCallback(hadc);
00973
00974       /* Clear the ADC analog watchdog flag */
00975       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
00976     }
00977   }
00978
00979   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
00980   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
00981   /* Check Overrun flag */
00982   if(tmp1 && tmp2)
00983   {
00984     /* Note: On STM32F7, ADC overrun can be set through other parameters    */
00985     /*       refer to description of parameter "EOCSelection" for more      */
00986     /*       details.                                                       */
00987
00988     /* Set ADC error code to overrun */
00989     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
00990
00991     /* Clear ADC overrun flag */
00992     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
00993
00994     /* Error callback */
00995     HAL_ADC_ErrorCallback(hadc);
00996
00997     /* Clear the Overrun flag */
00998     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
00999   }
01000 }
01001
01002 /**
01003   * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
01004   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01005   *         the configuration information for the specified ADC.
01006   * @param  pData: The destination Buffer address.
01007   * @param  Length: The length of data to be transferred from ADC peripheral to memory.
01008   * @retval HAL status
01009   */
01010 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
01011 {
01012   __IO uint32_t counter = 0;
01013
01014   /* Check the parameters */
01015   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
01016   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
01017
01018   /* Process locked */
01019   __HAL_LOCK(hadc);
01020
01021   /* Enable the ADC peripheral */
01022   /* Check if ADC peripheral is disabled in order to enable it and wait during
01023      Tstab time the ADC's stabilization */
01024   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
01025   {
01026     /* Enable the Peripheral */
01027     __HAL_ADC_ENABLE(hadc);
01028
01029     /* Delay for ADC stabilization time */
01030     /* Compute number of CPU cycles to wait for */
01031     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
01032     while(counter != 0)
01033     {
01034       counter--;
01035     }
01036   }
01037
01038   /* Start conversion if ADC is effectively enabled */
01039   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
01040   {
01041     /* Set ADC state                                                          */
01042     /* - Clear state bitfield related to regular group conversion results     */
01043     /* - Set state bitfield related to regular group operation                */
01044     ADC_STATE_CLR_SET(hadc->State,
01045                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
01046                       HAL_ADC_STATE_REG_BUSY);
01047
01048     /* If conversions on group regular are also triggering group injected,    */
01049     /* update ADC state.                                                      */
01050     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
01051     {
01052       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01053     }
01054
01055     /* State machine update: Check if an injected conversion is ongoing */
01056     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01057     {
01058       /* Reset ADC error code fields related to conversions on group regular */
01059       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01060     }
01061     else
01062     {
01063       /* Reset ADC all error code fields */
01064       ADC_CLEAR_ERRORCODE(hadc);
01065     }
01066
01067     /* Process unlocked */
01068     /* Unlock before starting ADC conversions: in case of potential           */
01069     /* interruption, to let the process to ADC IRQ Handler.                   */
01070     __HAL_UNLOCK(hadc);
01071
01072     /* Set the DMA transfer complete callback */
01073     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01074
01075     /* Set the DMA half transfer complete callback */
01076     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01077
01078     /* Set the DMA error callback */
01079     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01080
01081
01082     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
01083     /* start (in case of SW start):                                           */
01084
01085     /* Clear regular group conversion flag and overrun flag */
01086     /* (To ensure of no unknown state from potential previous ADC operations) */
01087     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01088
01089     /* Enable ADC overrun interrupt */
01090     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01091
01092     /* Enable ADC DMA mode */
01093     hadc->Instance->CR2 |= ADC_CR2_DMA;
01094
01095     /* Start the DMA channel */
01096     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01097
01098     /* Check if Multimode enabled */
01099     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
01100     {
01101       /* if no external trigger present enable software conversion of regular channels */
01102       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
01103       {
01104         /* Enable the selected ADC software conversion for regular group */
01105         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
01106       }
01107     }
01108     else
01109     {
01110       /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
01111       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
01112       {
01113         /* Enable the selected ADC software conversion for regular group */
01114           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
01115       }
01116     }
01117   }
01118
01119   /* Return function status */
01120   return HAL_OK;
01121 }
01122
01123 /**
01124   * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
01125   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01126   *         the configuration information for the specified ADC.
01127   * @retval HAL status
01128   */
01129 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
01130 {
01131   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01132
01133   /* Check the parameters */
01134   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01135
01136   /* Process locked */
01137   __HAL_LOCK(hadc);
01138
01139   /* Stop potential conversion on going, on regular and injected groups */
01140   /* Disable ADC peripheral */
01141   __HAL_ADC_DISABLE(hadc);
01142
01143   /* Check if ADC is effectively disabled */
01144   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
01145   {
01146     /* Disable the selected ADC DMA mode */
01147     hadc->Instance->CR2 &= ~ADC_CR2_DMA;
01148
01149     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01150     /* DMA transfer is on going)                                              */
01151     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01152
01153     /* Disable ADC overrun interrupt */
01154     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01155
01156     /* Set ADC state */
01157     ADC_STATE_CLR_SET(hadc->State,
01158                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01159                       HAL_ADC_STATE_READY);
01160   }
01161
01162   /* Process unlocked */
01163   __HAL_UNLOCK(hadc);
01164
01165   /* Return function status */
01166   return tmp_hal_status;
01167 }
01168
01169 /**
01170   * @brief  Gets the converted value from data register of regular channel.
01171   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01172   *         the configuration information for the specified ADC.
01173   * @retval Converted value
01174   */
01175 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
01176 {
01177   /* Return the selected ADC converted value */
01178   return hadc->Instance->DR;
01179 }
01180
01181 /**
01182   * @brief  Regular conversion complete callback in non blocking mode
01183   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01184   *         the configuration information for the specified ADC.
01185   * @retval None
01186   */
01187 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
01188 {
01189   /* Prevent unused argument(s) compilation warning */
01190   UNUSED(hadc);
01191   /* NOTE : This function Should not be modified, when the callback is needed,
01192             the HAL_ADC_ConvCpltCallback could be implemented in the user file
01193    */
01194 }
01195
01196 /**
01197   * @brief  Regular conversion half DMA transfer callback in non blocking mode
01198   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01199   *         the configuration information for the specified ADC.
01200   * @retval None
01201   */
01202 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
01203 {
01204   /* Prevent unused argument(s) compilation warning */
01205   UNUSED(hadc);
01206   /* NOTE : This function Should not be modified, when the callback is needed,
01207             the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
01208    */
01209 }
01210
01211 /**
01212   * @brief  Analog watchdog callback in non blocking mode
01213   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01214   *         the configuration information for the specified ADC.
01215   * @retval None
01216   */
01217 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
01218 {
01219   /* Prevent unused argument(s) compilation warning */
01220   UNUSED(hadc);
01221   /* NOTE : This function Should not be modified, when the callback is needed,
01222             the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
01223    */
01224 }
01225
01226 /**
01227   * @brief  Error ADC callback.
01228   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01229   *         the configuration information for the specified ADC.
01230   * @retval None
01231   */
01232 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
01233 {
01234   /* Prevent unused argument(s) compilation warning */
01235   UNUSED(hadc);
01236   /* NOTE : This function Should not be modified, when the callback is needed,
01237             the HAL_ADC_ErrorCallback could be implemented in the user file
01238    */
01239 }
01240
01241 /**
01242   * @}
01243   */
01244
01245 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
01246  *  @brief      Peripheral Control functions
01247  *
01248 @verbatim
01249  ===============================================================================
01250              ##### Peripheral Control functions #####
01251  ===============================================================================
01252     [..]  This section provides functions allowing to:
01253       (+) Configure regular channels.
01254       (+) Configure injected channels.
01255       (+) Configure multimode.
01256       (+) Configure the analog watch dog.
01257
01258 @endverbatim
01259   * @{
01260   */
01261
01262   /**
01263   * @brief  Configures for the selected ADC regular channel its corresponding
01264   *         rank in the sequencer and its sample time.
01265   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01266   *         the configuration information for the specified ADC.
01267   * @param  sConfig: ADC configuration structure.
01268   * @retval HAL status
01269   */
01270 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
01271 {
01272   __IO uint32_t counter = 0;
01273
01274   /* Check the parameters */
01275   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
01276   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
01277   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
01278
01279   /* Process locked */
01280   __HAL_LOCK(hadc);
01281
01282         /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
01283         if (sConfig->Channel > ADC_CHANNEL_9)
01284         {
01285                 /* Clear the old sample time */
01286                 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
01287
01288                 if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
01289                 {
01290                         /* Set the new sample time */
01291                         hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
01292                 }
01293           else
01294           {
01295                   /* Set the new sample time */
01296                   hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
01297           }
01298   }
01299   else /* ADC_Channel include in ADC_Channel_[0..9] */
01300   {
01301     /* Clear the old sample time */
01302     hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
01303
01304     /* Set the new sample time */
01305     hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
01306   }
01307
01308   /* For Rank 1 to 6 */
01309   if (sConfig->Rank < 7)
01310   {
01311     /* Clear the old SQx bits for the selected rank */
01312     hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
01313
01314     /* Set the SQx bits for the selected rank */
01315     hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
01316   }
01317   /* For Rank 7 to 12 */
01318   else if (sConfig->Rank < 13)
01319   {
01320     /* Clear the old SQx bits for the selected rank */
01321     hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
01322
01323     /* Set the SQx bits for the selected rank */
01324     hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
01325   }
01326   /* For Rank 13 to 16 */
01327   else
01328   {
01329     /* Clear the old SQx bits for the selected rank */
01330     hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
01331
01332     /* Set the SQx bits for the selected rank */
01333     hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
01334   }
01335
01336   /* if ADC1 Channel_18 is selected enable VBAT Channel */
01337   if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
01338   {
01339     /* Enable the VBAT channel*/
01340     ADC->CCR |= ADC_CCR_VBATE;
01341   }
01342
01343   /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
01344   if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
01345   {
01346     /* Enable the TSVREFE channel*/
01347     ADC->CCR |= ADC_CCR_TSVREFE;
01348
01349     if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
01350     {
01351       /* Delay for temperature sensor stabilization time */
01352       /* Compute number of CPU cycles to wait for */
01353       counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
01354       while(counter != 0)
01355       {
01356         counter--;
01357       }
01358     }
01359   }
01360
01361   /* Process unlocked */
01362   __HAL_UNLOCK(hadc);
01363
01364   /* Return function status */
01365   return HAL_OK;
01366 }
01367
01368 /**
01369   * @brief  Configures the analog watchdog.
01370   * @note   Analog watchdog thresholds can be modified while ADC conversion
01371   *         is on going.
01372   *         In this case, some constraints must be taken into account:
01373   *         the programmed threshold values are effective from the next
01374   *         ADC EOC (end of unitary conversion).
01375   *         Considering that registers write delay may happen due to
01376   *         bus activity, this might cause an uncertainty on the
01377   *         effective timing of the new programmed threshold values.
01378   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01379   *         the configuration information for the specified ADC.
01380   * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
01381   *         that contains the configuration information of ADC analog watchdog.
01382   * @retval HAL status
01383   */
01384 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
01385 {
01386 #ifdef USE_FULL_ASSERT
01387   uint32_t tmp = 0;
01388 #endif /* USE_FULL_ASSERT  */
01389
01390   /* Check the parameters */
01391   assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
01392   assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
01393   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
01394
01395 #ifdef USE_FULL_ASSERT
01396   tmp = ADC_GET_RESOLUTION(hadc);
01397   assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
01398   assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
01399 #endif /* USE_FULL_ASSERT  */
01400
01401   /* Process locked */
01402   __HAL_LOCK(hadc);
01403
01404   if(AnalogWDGConfig->ITMode == ENABLE)
01405   {
01406     /* Enable the ADC Analog watchdog interrupt */
01407     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
01408   }
01409   else
01410   {
01411     /* Disable the ADC Analog watchdog interrupt */
01412     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
01413   }
01414
01415   /* Clear AWDEN, JAWDEN and AWDSGL bits */
01416   hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
01417
01418   /* Set the analog watchdog enable mode */
01419   hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
01420
01421   /* Set the high threshold */
01422   hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
01423
01424   /* Set the low threshold */
01425   hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
01426
01427   /* Clear the Analog watchdog channel select bits */
01428   hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
01429
01430   /* Set the Analog watchdog channel */
01431   hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
01432
01433   /* Process unlocked */
01434   __HAL_UNLOCK(hadc);
01435
01436   /* Return function status */
01437   return HAL_OK;
01438 }
01439
01440 /**
01441   * @}
01442   */
01443
01444 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
01445  *  @brief   ADC Peripheral State functions
01446  *
01447 @verbatim
01448  ===============================================================================
01449             ##### Peripheral State and errors functions #####
01450  ===============================================================================
01451     [..]
01452     This subsection provides functions allowing to
01453       (+) Check the ADC state
01454       (+) Check the ADC Error
01455
01456 @endverbatim
01457   * @{
01458   */
01459
01460 /**
01461   * @brief  return the ADC state
01462   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01463   *         the configuration information for the specified ADC.
01464   * @retval HAL state
01465   */
01466 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
01467 {
01468   /* Return ADC state */
01469   return hadc->State;
01470 }
01471
01472 /**
01473   * @brief  Return the ADC error code
01474   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01475   *         the configuration information for the specified ADC.
01476   * @retval ADC Error Code
01477   */
01478 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
01479 {
01480   return hadc->ErrorCode;
01481 }
01482
01483 /**
01484   * @}
01485   */
01486
01487 /**
01488   * @}
01489   */
01490
01491 /* Private functions ---------------------------------------------------------*/
01492
01493 /** @defgroup ADC_Private_Functions ADC Private Functions
01494   * @{
01495   */
01496
01497 /**
01498   * @brief  Initializes the ADCx peripheral according to the specified parameters
01499   *         in the ADC_InitStruct without initializing the ADC MSP.
01500   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01501   *         the configuration information for the specified ADC.
01502   * @retval None
01503   */
01504 static void ADC_Init(ADC_HandleTypeDef* hadc)
01505 {
01506   /* Set ADC parameters */
01507   /* Set the ADC clock prescaler */
01508   ADC->CCR &= ~(ADC_CCR_ADCPRE);
01509   ADC->CCR |=  hadc->Init.ClockPrescaler;
01510
01511   /* Set ADC scan mode */
01512   hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
01513   hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
01514
01515   /* Set ADC resolution */
01516   hadc->Instance->CR1 &= ~(ADC_CR1_RES);
01517   hadc->Instance->CR1 |=  hadc->Init.Resolution;
01518
01519   /* Set ADC data alignment */
01520   hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
01521   hadc->Instance->CR2 |= hadc->Init.DataAlign;
01522
01523   /* Enable external trigger if trigger selection is different of software  */
01524   /* start.                                                                 */
01525   /* Note: This configuration keeps the hardware feature of parameter       */
01526   /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
01527   /*       software start.                                                  */
01528   if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
01529   {
01530     /* Select external trigger to start conversion */
01531     hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
01532     hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
01533
01534     /* Select external trigger polarity */
01535     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
01536     hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
01537   }
01538   else
01539   {
01540     /* Reset the external trigger */
01541     hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
01542     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
01543   }
01544
01545   /* Enable or disable ADC continuous conversion mode */
01546   hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
01547   hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
01548
01549   if(hadc->Init.DiscontinuousConvMode != DISABLE)
01550   {
01551     assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
01552
01553     /* Enable the selected ADC regular discontinuous mode */
01554     hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
01555
01556     /* Set the number of channels to be converted in discontinuous mode */
01557     hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
01558     hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
01559   }
01560   else
01561   {
01562     /* Disable the selected ADC regular discontinuous mode */
01563     hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
01564   }
01565
01566   /* Set ADC number of conversion */
01567   hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
01568   hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
01569
01570   /* Enable or disable ADC DMA continuous request */
01571   hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
01572   hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
01573
01574   /* Enable or disable ADC end of conversion selection */
01575   hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
01576   hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
01577 }
01578
01579 /**
01580   * @brief  DMA transfer complete callback.
01581   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01582   *                the configuration information for the specified DMA module.
01583   * @retval None
01584   */
01585 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
01586 {
01587   /* Retrieve ADC handle corresponding to current DMA handle */
01588   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01589
01590   /* Update state machine on conversion status if not in error state */
01591   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
01592   {
01593     /* Update ADC state machine */
01594     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01595
01596     /* Determine whether any further conversion upcoming on group regular   */
01597     /* by external trigger, continuous mode or scan sequence on going.      */
01598     /* Note: On STM32F7, there is no independent flag of end of sequence.   */
01599     /*       The test of scan sequence on going is done either with scan    */
01600     /*       sequence disabled or with end of conversion flag set to        */
01601     /*       of end of sequence.                                            */
01602     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
01603        (hadc->Init.ContinuousConvMode == DISABLE)            &&
01604        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
01605         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
01606     {
01607       /* Disable ADC end of single conversion interrupt on group regular */
01608       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
01609       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
01610       /* by overrun IRQ process below.                                      */
01611       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
01612
01613       /* Set ADC state */
01614       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01615
01616       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01617       {
01618         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01619       }
01620     }
01621
01622     /* Conversion complete callback */
01623     HAL_ADC_ConvCpltCallback(hadc);
01624   }
01625   else
01626   {
01627     /* Call DMA error callback */
01628     hadc->DMA_Handle->XferErrorCallback(hdma);
01629   }
01630 }
01631
01632 /**
01633   * @brief  DMA half transfer complete callback.
01634   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01635   *                the configuration information for the specified DMA module.
01636   * @retval None
01637   */
01638 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
01639 {
01640   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01641   /* Conversion complete callback */
01642   HAL_ADC_ConvHalfCpltCallback(hadc);
01643 }
01644
01645 /**
01646   * @brief  DMA error callback
01647   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01648   *                the configuration information for the specified DMA module.
01649   * @retval None
01650   */
01651 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
01652 {
01653   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01654   hadc->State= HAL_ADC_STATE_ERROR_DMA;
01655   /* Set ADC error code to DMA error */
01656   hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
01657   HAL_ADC_ErrorCallback(hadc);
01658 }
01659
01660 /**
01661   * @}
01662   */
01663
01664 /**
01665   * @}
01666   */
01667
01668 #endif /* HAL_ADC_MODULE_ENABLED */
01669 /**
01670   * @}
01671   */
01672
01673 /**
01674   * @}
01675   */
01676
01677 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc.h Source File

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stm32f7xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of ADC HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_ADC_H
00040 #define __STM32F7xx_ADC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADC_Exported_Types ADC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  Structure definition of ADC and regular group initialization
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
00066   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
00067   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
00068   *         ADC state can be either:
00069   *          - For all parameters: ADC disabled
00070   *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
00071   *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
00072   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00073   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
00074   */
00075 typedef struct
00076 {
00077   uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for
00078                                        all the ADCs.
00079                                        This parameter can be a value of @ref ADC_ClockPrescaler */
00080   uint32_t Resolution;            /*!< Configures the ADC resolution.
00081                                        This parameter can be a value of @ref ADC_Resolution */
00082   uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
00083                                        or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
00084                                        This parameter can be a value of @ref ADC_data_align */
00085   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
00086                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00087                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
00088                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00089                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
00090                                                     Scan direction is upward: from rank1 to rank 'n'. */
00091   uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
00092                                        This parameter can be a value of @ref ADC_EOCSelection.
00093                                        Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
00094                                              Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
00095                                              or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
00096                                        Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
00097                                              If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
00098   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
00099                                        after the selected trigger occurred (software start or external trigger).
00100                                        This parameter can be set to ENABLE or DISABLE. */
00101   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
00102                                        To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00103                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
00104   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00105                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00106                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00107                                        This parameter can be set to ENABLE or DISABLE. */
00108   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
00109                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00110                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00111   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
00112                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
00113                                        If set to external trigger source, triggering is on event rising edge by default.
00114                                        This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
00115   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
00116                                        If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
00117                                        This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
00118   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
00119                                        or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
00120                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
00121                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
00122                                        This parameter can be set to ENABLE or DISABLE. */
00123 }ADC_InitTypeDef;
00124
00125
00126
00127 /**
00128   * @brief  Structure definition of ADC channel for regular group
00129   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00130   *         ADC can be either disabled or enabled without conversion on going on regular group.
00131   */
00132 typedef struct
00133 {
00134   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
00135                                         This parameter can be a value of @ref ADC_channels */
00136   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
00137                                         This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00138   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00139                                         Unit: ADC clock cycles
00140                                         Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
00141                                         This parameter can be a value of @ref ADC_sampling_times
00142                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00143                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00144                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00145                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00146                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
00147   uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
00148 }ADC_ChannelConfTypeDef;
00149
00150 /**
00151   * @brief ADC Configuration multi-mode structure definition
00152   */
00153 typedef struct
00154 {
00155   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
00156                                    This parameter can be a value of @ref ADC_analog_watchdog_selection */
00157   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
00158                                    This parameter must be a 12-bit value. */
00159   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
00160                                    This parameter must be a 12-bit value. */
00161   uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog.
00162                                    This parameter has an effect only if watchdog mode is configured on single channel
00163                                    This parameter can be a value of @ref ADC_channels */
00164   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
00165                                    is interrupt mode or in polling mode.
00166                                    This parameter can be set to ENABLE or DISABLE */
00167   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
00168 }ADC_AnalogWDGConfTypeDef;
00169
00170 /**
00171   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00172   */
00173 /* States of ADC global scope */
00174 #define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
00175 #define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
00176 #define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy to internal process (initialization, calibration) */
00177 #define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
00178
00179 /* States of ADC errors */
00180 #define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
00181 #define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
00182 #define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
00183
00184 /* States of ADC group regular */
00185 #define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
00186                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00187 #define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
00188 #define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
00189
00190 /* States of ADC group injected */
00191 #define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
00192                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00193 #define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
00194
00195 /* States of ADC analog watchdogs */
00196 #define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of analog watchdog 1 */
00197 #define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
00198 #define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
00199
00200 /* States of ADC multi-mode */
00201 #define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
00202
00203
00204 /**
00205   * @brief  ADC handle Structure definition
00206   */
00207 typedef struct
00208 {
00209   ADC_TypeDef                   *Instance;                   /*!< Register base address */
00210
00211   ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
00212
00213   __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
00214
00215   DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
00216
00217   HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
00218
00219   __IO uint32_t                 State;                       /*!< ADC communication state */
00220
00221   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
00222 }ADC_HandleTypeDef;
00223 /**
00224   * @}
00225   */
00226
00227 /* Exported constants --------------------------------------------------------*/
00228 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00229   * @{
00230   */
00231
00232 /** @defgroup ADC_Error_Code ADC Error Code
00233   * @{
00234   */
00235 #define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
00236 #define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking,
00237                                                           enable/disable, erroneous state                       */
00238 #define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
00239 #define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
00240 /**
00241   * @}
00242   */
00243
00244
00245 /** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
00246   * @{
00247   */
00248 #define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000)
00249 #define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
00250 #define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
00251 #define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
00257   * @{
00258   */
00259 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000)
00260 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
00261 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
00262 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
00263 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
00264 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
00265 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
00266 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
00267 #define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
00268 #define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
00269 #define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
00270 #define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
00271 #define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
00272 #define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
00273 #define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
00274 #define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup ADC_Resolution ADC Resolution
00280   * @{
00281   */
00282 #define ADC_RESOLUTION_12B  ((uint32_t)0x00000000)
00283 #define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
00284 #define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
00285 #define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
00291   * @{
00292   */
00293 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
00294 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
00295 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
00296 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
00302   * @{
00303   */
00304 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
00305 /*       compatibility with other STM32 devices.                              */
00306
00307
00308 #define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000)
00309 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
00310 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
00311 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00312 #define ADC_EXTERNALTRIGCONV_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)
00313 #define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
00314 #define ADC_EXTERNALTRIGCONV_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
00315 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00316 #define ADC_EXTERNALTRIGCONV_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)
00317 #define ADC_EXTERNALTRIGCONV_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
00318 #define ADC_EXTERNALTRIGCONV_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
00319 #define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00320 #define ADC_EXTERNALTRIGCONV_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
00321 #define ADC_EXTERNALTRIGCONV_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
00322
00323 #define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)
00324 #define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
00325
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup ADC_data_align ADC Data Align
00331   * @{
00332   */
00333 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
00334 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup ADC_channels ADC Common Channels
00340   * @{
00341   */
00342 #define ADC_CHANNEL_0           ((uint32_t)0x00000000)
00343 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
00344 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
00345 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00346 #define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
00347 #define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
00348 #define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
00349 #define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00350 #define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
00351 #define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
00352 #define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
00353 #define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00354 #define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
00355 #define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
00356 #define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
00357 #define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00358 #define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
00359 #define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
00360 #define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
00361
00362 #define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
00363 #define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup ADC_sampling_times ADC Sampling Times
00369   * @{
00370   */
00371 #define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000)
00372 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
00373 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
00374 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
00375 #define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
00376 #define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
00377 #define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
00378 #define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
00379 /**
00380   * @}
00381   */
00382
00383   /** @defgroup ADC_EOCSelection ADC EOC Selection
00384   * @{
00385   */
00386 #define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000)
00387 #define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001)
00388 #define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002)  /*!< reserved for future use */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup ADC_Event_type ADC Event Type
00394   * @{
00395   */
00396 #define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
00397 #define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
00403   * @{
00404   */
00405 #define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
00406 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
00407 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
00408 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
00409 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
00410 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
00411 #define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000)
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
00417   * @{
00418   */
00419 #define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
00420 #define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
00421 #define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
00422 #define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup ADC_flags_definition ADC Flags Definition
00428   * @{
00429   */
00430 #define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
00431 #define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
00432 #define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
00433 #define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
00434 #define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
00435 #define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
00436 /**
00437   * @}
00438   */
00439
00440 /** @defgroup ADC_channels_type ADC Channels Type
00441   * @{
00442   */
00443 #define ADC_ALL_CHANNELS      ((uint32_t)0x00000001)
00444 #define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002) /*!< reserved for future use */
00445 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
00446 /**
00447   * @}
00448   */
00449
00450 /**
00451   * @}
00452   */
00453
00454 /* Exported macro ------------------------------------------------------------*/
00455 /** @defgroup ADC_Exported_Macros ADC Exported Macros
00456   * @{
00457   */
00458
00459 /** @brief Reset ADC handle state
00460   * @param  __HANDLE__: ADC handle
00461   * @retval None
00462   */
00463 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00464
00465 /**
00466   * @brief  Enable the ADC peripheral.
00467   * @param  __HANDLE__: ADC handle
00468   * @retval None
00469   */
00470 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
00471
00472 /**
00473   * @brief  Disable the ADC peripheral.
00474   * @param  __HANDLE__: ADC handle
00475   * @retval None
00476   */
00477 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
00478
00479 /**
00480   * @brief  Enable the ADC end of conversion interrupt.
00481   * @param  __HANDLE__: specifies the ADC Handle.
00482   * @param  __INTERRUPT__: ADC Interrupt.
00483   * @retval None
00484   */
00485 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
00486
00487 /**
00488   * @brief  Disable the ADC end of conversion interrupt.
00489   * @param  __HANDLE__: specifies the ADC Handle.
00490   * @param  __INTERRUPT__: ADC interrupt.
00491   * @retval None
00492   */
00493 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
00494
00495 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
00496   * @param  __HANDLE__: specifies the ADC Handle.
00497   * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
00498   * @retval The new state of __IT__ (TRUE or FALSE).
00499   */
00500 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
00501
00502 /**
00503   * @brief  Clear the ADC's pending flags.
00504   * @param  __HANDLE__: specifies the ADC Handle.
00505   * @param  __FLAG__: ADC flag.
00506   * @retval None
00507   */
00508 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
00509
00510 /**
00511   * @brief  Get the selected ADC's flag status.
00512   * @param  __HANDLE__: specifies the ADC Handle.
00513   * @param  __FLAG__: ADC flag.
00514   * @retval None
00515   */
00516 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00517
00518 /**
00519   * @}
00520   */
00521
00522 /* Include ADC HAL Extension module */
00523 #include "stm32f7xx_hal_adc_ex.h"
00524
00525 /* Exported functions --------------------------------------------------------*/
00526 /** @addtogroup ADC_Exported_Functions
00527   * @{
00528   */
00529
00530 /** @addtogroup ADC_Exported_Functions_Group1
00531   * @{
00532   */
00533 /* Initialization/de-initialization functions ***********************************/
00534 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
00535 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
00536 void       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
00537 void       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
00538 /**
00539   * @}
00540   */
00541
00542 /** @addtogroup ADC_Exported_Functions_Group2
00543   * @{
00544   */
00545 /* I/O operation functions ******************************************************/
00546 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
00547 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
00548 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00549
00550 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
00551
00552 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
00553 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
00554
00555 void              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
00556
00557 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00558 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
00559
00560 uint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
00561
00562 void       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
00563 void       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
00564 void       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
00565 void       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
00566 /**
00567   * @}
00568   */
00569
00570 /** @addtogroup ADC_Exported_Functions_Group3
00571   * @{
00572   */
00573 /* Peripheral Control functions *************************************************/
00574 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
00575 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
00576 /**
00577   * @}
00578   */
00579
00580 /** @addtogroup ADC_Exported_Functions_Group4
00581   * @{
00582   */
00583 /* Peripheral State functions ***************************************************/
00584 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
00585 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
00586 /**
00587   * @}
00588   */
00589
00590 /**
00591   * @}
00592   */
00593
00594 /* Private types -------------------------------------------------------------*/
00595 /* Private variables ---------------------------------------------------------*/
00596 /* Private constants ---------------------------------------------------------*/
00597 /** @defgroup ADC_Private_Constants ADC Private Constants
00598   * @{
00599   */
00600 /* Delay for ADC stabilization time.                                        */
00601 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
00602 /* Unit: us                                                                 */
00603 #define ADC_STAB_DELAY_US               ((uint32_t) 3)
00604 /* Delay for temperature sensor stabilization time.                         */
00605 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
00606 /* Unit: us                                                                 */
00607 #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10)
00608 /**
00609   * @}
00610   */
00611
00612 /* Private macros ------------------------------------------------------------*/
00613 /** @defgroup ADC_Private_Macros ADC Private Macros
00614   * @{
00615   */
00616 /* Macro reserved for internal HAL driver usage, not intended to be used in
00617    code of final user */
00618
00619 /**
00620   * @brief Verification of ADC state: enabled or disabled
00621   * @param __HANDLE__: ADC handle
00622   * @retval SET (ADC enabled) or RESET (ADC disabled)
00623   */
00624 #define ADC_IS_ENABLE(__HANDLE__)                                              \
00625   ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
00626   ) ? SET : RESET)
00627
00628 /**
00629   * @brief Test if conversion trigger of regular group is software start
00630   *        or external trigger.
00631   * @param __HANDLE__: ADC handle
00632   * @retval SET (software start) or RESET (external trigger)
00633   */
00634 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
00635   (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00636
00637 /**
00638   * @brief Test if conversion trigger of injected group is software start
00639   *        or external trigger.
00640   * @param __HANDLE__: ADC handle
00641   * @retval SET (software start) or RESET (external trigger)
00642   */
00643 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
00644   (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
00645
00646 /**
00647   * @brief Simultaneously clears and sets specific bits of the handle State
00648   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00649   *        the first parameter is the ADC handle State, the second parameter is the
00650   *        bit field to clear, the third and last parameter is the bit field to set.
00651   * @retval None
00652   */
00653 #define ADC_STATE_CLR_SET MODIFY_REG
00654
00655 /**
00656   * @brief Clear ADC error code (set it to error code: "no error")
00657   * @param __HANDLE__: ADC handle
00658   * @retval None
00659   */
00660 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
00661   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00662 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00663                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
00664                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
00665                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
00666 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
00667                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
00668                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
00669                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
00670                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
00671                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
00672                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
00673                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
00674                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
00675                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
00676                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
00677                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
00678                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
00679                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
00680                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
00681                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
00682 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
00683                                            ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
00684                                            ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
00685                                            ((__RESOLUTION__) == ADC_RESOLUTION_6B))
00686 #define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
00687                                         ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
00688                                         ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
00689                                         ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
00690 #define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
00691                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
00692                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
00693                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
00694                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \
00695                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
00696                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
00697                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
00698                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
00699                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
00700                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
00701                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
00702                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
00703                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
00704                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
00705                                                                                                                                                         ((__REGTRIG__) == ADC_SOFTWARE_START))
00706 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
00707                                       ((__ALIGN__) == ADC_DATAALIGN_LEFT))
00708
00709 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \
00710                                       ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \
00711                                       ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \
00712                                       ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \
00713                                       ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \
00714                                       ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
00715                                       ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
00716                                       ((__TIME__) == ADC_SAMPLETIME_480CYCLES))
00717 #define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \
00718                                                ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \
00719                                                ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
00720 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
00721                                       ((__EVENT__) == ADC_OVR_EVENT))
00722 #define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
00723                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
00724                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
00725                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
00726                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
00727                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
00728                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
00729 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
00730                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
00731                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
00732 #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
00733 #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
00734 #define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
00735 #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
00736 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \
00737    ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
00738     (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
00739     (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
00740     (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
00741
00742 /**
00743   * @brief  Set ADC Regular channel sequence length.
00744   * @param  _NbrOfConversion_: Regular channel sequence length.
00745   * @retval None
00746   */
00747 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
00748
00749 /**
00750   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
00751   * @param  _SAMPLETIME_: Sample time parameter.
00752   * @param  _CHANNELNB_: Channel number.
00753   * @retval None
00754   */
00755 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
00756
00757 /**
00758   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
00759   * @param  _SAMPLETIME_: Sample time parameter.
00760   * @param  _CHANNELNB_: Channel number.
00761   * @retval None
00762   */
00763 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
00764
00765 /**
00766   * @brief  Set the selected regular channel rank for rank between 1 and 6.
00767   * @param  _CHANNELNB_: Channel number.
00768   * @param  _RANKNB_: Rank number.
00769   * @retval None
00770   */
00771 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
00772
00773 /**
00774   * @brief  Set the selected regular channel rank for rank between 7 and 12.
00775   * @param  _CHANNELNB_: Channel number.
00776   * @param  _RANKNB_: Rank number.
00777   * @retval None
00778   */
00779 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
00780
00781 /**
00782   * @brief  Set the selected regular channel rank for rank between 13 and 16.
00783   * @param  _CHANNELNB_: Channel number.
00784   * @param  _RANKNB_: Rank number.
00785   * @retval None
00786   */
00787 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
00788
00789 /**
00790   * @brief  Enable ADC continuous conversion mode.
00791   * @param  _CONTINUOUS_MODE_: Continuous mode.
00792   * @retval None
00793   */
00794 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
00795
00796 /**
00797   * @brief  Configures the number of discontinuous conversions for the regular group channels.
00798   * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
00799   * @retval None
00800   */
00801 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
00802
00803 /**
00804   * @brief  Enable ADC scan mode.
00805   * @param  _SCANCONV_MODE_: Scan conversion mode.
00806   * @retval None
00807   */
00808 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
00809
00810 /**
00811   * @brief  Enable the ADC end of conversion selection.
00812   * @param  _EOCSelection_MODE_: End of conversion selection mode.
00813   * @retval None
00814   */
00815 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
00816
00817 /**
00818   * @brief  Enable the ADC DMA continuous request.
00819   * @param  _DMAContReq_MODE_: DMA continuous request mode.
00820   * @retval None
00821   */
00822 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
00823
00824 /**
00825   * @brief Return resolution bits in CR1 register.
00826   * @param __HANDLE__: ADC handle
00827   * @retval None
00828   */
00829 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
00830
00831 /**
00832   * @}
00833   */
00834
00835 /* Private functions ---------------------------------------------------------*/
00836 /** @defgroup ADC_Private_Functions ADC Private Functions
00837   * @{
00838   */
00839
00840 /**
00841   * @}
00842   */
00843
00844 /**
00845   * @}
00846   */
00847
00848 /**
00849   * @}
00850   */
00851
00852 #ifdef __cplusplus
00853 }
00854 #endif
00855
00856 #endif /*__STM32F7xx_ADC_H */
00857
00858
00859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc_ex.c Source File

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stm32f7xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the ADC extension peripheral:
00009   *           + Extended features functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016     (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
00017        (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
00018        (##) ADC pins configuration
00019              (+++) Enable the clock for the ADC GPIOs using the following function:
00020                    __HAL_RCC_GPIOx_CLK_ENABLE()
00021              (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
00022        (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
00023              (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
00024              (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
00025              (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
00026       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
00027              (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
00028              (+++) Configure and enable two DMA streams stream for managing data
00029                  transfer from peripheral to memory (output stream)
00030              (+++) Associate the initialized DMA handle to the ADC DMA handle
00031                  using  __HAL_LINKDMA()
00032              (+++) Configure the priority and enable the NVIC for the transfer complete
00033                  interrupt on the two DMA Streams. The output stream should have higher
00034                  priority than the input stream.
00035      (#) Configure the ADC Prescaler, conversion resolution and data alignment
00036          using the HAL_ADC_Init() function.
00037
00038      (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
00039          and HAL_ADC_ConfigChannel() functions.
00040
00041      (#) Three operation modes are available within this driver :
00042
00043      *** Polling mode IO operation ***
00044      =================================
00045      [..]
00046        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
00047        (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
00048            user can specify the value of timeout according to his end application
00049        (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
00050        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
00051
00052      *** Interrupt mode IO operation ***
00053      ===================================
00054      [..]
00055        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
00056        (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
00057        (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
00058             add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
00059        (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
00060             add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
00061        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
00062
00063
00064      *** DMA mode IO operation ***
00065      ==============================
00066      [..]
00067        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
00068            of data to be transferred at each end of conversion
00069        (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
00070             add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
00071        (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
00072             add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
00073         (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
00074
00075      *** Multi mode ADCs Regular channels configuration ***
00076      ======================================================
00077      [..]
00078        (+) Select the Multi mode ADC regular channels features (dual or triple mode)
00079           and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
00080        (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
00081            of data to be transferred at each end of conversion
00082        (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
00083
00084
00085     @endverbatim
00086   ******************************************************************************
00087   * @attention
00088   *
00089   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00090   *
00091   * Redistribution and use in source and binary forms, with or without modification,
00092   * are permitted provided that the following conditions are met:
00093   *   1. Redistributions of source code must retain the above copyright notice,
00094   *      this list of conditions and the following disclaimer.
00095   *   2. Redistributions in binary form must reproduce the above copyright notice,
00096   *      this list of conditions and the following disclaimer in the documentation
00097   *      and/or other materials provided with the distribution.
00098   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00099   *      may be used to endorse or promote products derived from this software
00100   *      without specific prior written permission.
00101   *
00102   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00103   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00104   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00105   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00106   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00107   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00108   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00109   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00110   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00111   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00112   *
00113   ******************************************************************************
00114   */
00115
00116 /* Includes ------------------------------------------------------------------*/
00117 #include "stm32f7xx_hal.h"
00118
00119 /** @addtogroup STM32F7xx_HAL_Driver
00120   * @{
00121   */
00122
00123 /** @defgroup ADCEx ADCEx
00124   * @brief ADC Extended driver modules
00125   * @{
00126   */
00127
00128 #ifdef HAL_ADC_MODULE_ENABLED
00129
00130 /* Private typedef -----------------------------------------------------------*/
00131 /* Private define ------------------------------------------------------------*/
00132 /* Private macro -------------------------------------------------------------*/
00133 /* Private variables ---------------------------------------------------------*/
00134 /** @addtogroup ADCEx_Private_Functions
00135   * @{
00136   */
00137 /* Private function prototypes -----------------------------------------------*/
00138 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
00139 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
00140 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions --------------------------------------------------------*/
00146 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions
00151   *  @brief    Extended features functions
00152   *
00153 @verbatim
00154  ===============================================================================
00155                  ##### Extended features functions #####
00156  ===============================================================================
00157     [..]  This section provides functions allowing to:
00158       (+) Start conversion of injected channel.
00159       (+) Stop conversion of injected channel.
00160       (+) Start multimode and enable DMA transfer.
00161       (+) Stop multimode and disable DMA transfer.
00162       (+) Get result of injected channel conversion.
00163       (+) Get result of multimode conversion.
00164       (+) Configure injected channels.
00165       (+) Configure multimode.
00166
00167 @endverbatim
00168   * @{
00169   */
00170
00171 /**
00172   * @brief  Enables the selected ADC software start conversion of the injected channels.
00173   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00174   *         the configuration information for the specified ADC.
00175   * @retval HAL status
00176   */
00177 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
00178 {
00179   __IO uint32_t counter = 0;
00180   uint32_t tmp1 = 0, tmp2 = 0;
00181
00182   /* Process locked */
00183   __HAL_LOCK(hadc);
00184
00185   /* Enable the ADC peripheral */
00186
00187   /* Check if ADC peripheral is disabled in order to enable it and wait during
00188      Tstab time the ADC's stabilization */
00189   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00190   {
00191     /* Enable the Peripheral */
00192     __HAL_ADC_ENABLE(hadc);
00193
00194     /* Delay for ADC stabilization time */
00195     /* Compute number of CPU cycles to wait for */
00196     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
00197     while(counter != 0)
00198     {
00199       counter--;
00200     }
00201   }
00202
00203   /* Start conversion if ADC is effectively enabled */
00204   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00205   {
00206     /* Set ADC state                                                          */
00207     /* - Clear state bitfield related to injected group conversion results    */
00208     /* - Set state bitfield related to injected operation                     */
00209     ADC_STATE_CLR_SET(hadc->State,
00210                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00211                       HAL_ADC_STATE_INJ_BUSY);
00212
00213     /* Check if a regular conversion is ongoing */
00214     /* Note: On this device, there is no ADC error code fields related to     */
00215     /*       conversions on group injected only. In case of conversion on     */
00216     /*       going on group regular, no error code is reset.                  */
00217     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00218     {
00219       /* Reset ADC all error code fields */
00220       ADC_CLEAR_ERRORCODE(hadc);
00221     }
00222
00223     /* Process unlocked */
00224     /* Unlock before starting ADC conversions: in case of potential           */
00225     /* interruption, to let the process to ADC IRQ Handler.                   */
00226     __HAL_UNLOCK(hadc);
00227
00228     /* Clear injected group conversion flag */
00229     /* (To ensure of no unknown state from potential previous ADC operations) */
00230     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00231
00232     /* Check if Multimode enabled */
00233     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00234     {
00235       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00236       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00237       if(tmp1 && tmp2)
00238       {
00239         /* Enable the selected ADC software conversion for injected group */
00240         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00241       }
00242     }
00243     else
00244     {
00245       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00246       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00247       if((hadc->Instance == ADC1) && tmp1 && tmp2)
00248       {
00249         /* Enable the selected ADC software conversion for injected group */
00250         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00251       }
00252     }
00253   }
00254
00255   /* Return function status */
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Enables the interrupt and starts ADC conversion of injected channels.
00261   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00262   *         the configuration information for the specified ADC.
00263   *
00264   * @retval HAL status.
00265   */
00266 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
00267 {
00268   __IO uint32_t counter = 0;
00269   uint32_t tmp1 = 0, tmp2 = 0;
00270
00271   /* Process locked */
00272   __HAL_LOCK(hadc);
00273
00274   /* Enable the ADC peripheral */
00275
00276   /* Check if ADC peripheral is disabled in order to enable it and wait during
00277      Tstab time the ADC's stabilization */
00278   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00279   {
00280     /* Enable the Peripheral */
00281     __HAL_ADC_ENABLE(hadc);
00282
00283     /* Delay for ADC stabilization time */
00284     /* Compute number of CPU cycles to wait for */
00285     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
00286     while(counter != 0)
00287     {
00288       counter--;
00289     }
00290   }
00291
00292   /* Start conversion if ADC is effectively enabled */
00293   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00294   {
00295     /* Set ADC state                                                          */
00296     /* - Clear state bitfield related to injected group conversion results    */
00297     /* - Set state bitfield related to injected operation                     */
00298     ADC_STATE_CLR_SET(hadc->State,
00299                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00300                       HAL_ADC_STATE_INJ_BUSY);
00301
00302     /* Check if a regular conversion is ongoing */
00303     /* Note: On this device, there is no ADC error code fields related to     */
00304     /*       conversions on group injected only. In case of conversion on     */
00305     /*       going on group regular, no error code is reset.                  */
00306     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00307     {
00308       /* Reset ADC all error code fields */
00309       ADC_CLEAR_ERRORCODE(hadc);
00310     }
00311
00312     /* Process unlocked */
00313     /* Unlock before starting ADC conversions: in case of potential           */
00314     /* interruption, to let the process to ADC IRQ Handler.                   */
00315     __HAL_UNLOCK(hadc);
00316
00317     /* Clear injected group conversion flag */
00318     /* (To ensure of no unknown state from potential previous ADC operations) */
00319     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00320
00321     /* Enable end of conversion interrupt for injected channels */
00322     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00323
00324     /* Check if Multimode enabled */
00325     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00326     {
00327       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00328       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00329       if(tmp1 && tmp2)
00330       {
00331         /* Enable the selected ADC software conversion for injected group */
00332         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00333       }
00334     }
00335     else
00336     {
00337       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00338       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00339       if((hadc->Instance == ADC1) && tmp1 && tmp2)
00340       {
00341         /* Enable the selected ADC software conversion for injected group */
00342         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00343       }
00344     }
00345   }
00346
00347   /* Return function status */
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
00353   *         no regular conversion is on going.
00354   * @note   If ADC must be disabled and if conversion is on going on
00355   *         regular group, function HAL_ADC_Stop must be used to stop both
00356   *         injected and regular groups, and disable the ADC.
00357   * @note   If injected group mode auto-injection is enabled,
00358   *         function HAL_ADC_Stop must be used.
00359   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
00360   * @param  hadc: ADC handle
00361   * @retval None
00362   */
00363 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
00364 {
00365   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00366
00367   /* Check the parameters */
00368   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00369
00370   /* Process locked */
00371   __HAL_LOCK(hadc);
00372
00373   /* Stop potential conversion and disable ADC peripheral                     */
00374   /* Conditioned to:                                                          */
00375   /* - No conversion on the other group (regular group) is intended to        */
00376   /*   continue (injected and regular groups stop conversion and ADC disable  */
00377   /*   are common)                                                            */
00378   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
00379   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
00380      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
00381   {
00382     /* Stop potential conversion on going, on regular and injected groups */
00383     /* Disable ADC peripheral */
00384     __HAL_ADC_DISABLE(hadc);
00385
00386     /* Check if ADC is effectively disabled */
00387     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00388     {
00389       /* Set ADC state */
00390       ADC_STATE_CLR_SET(hadc->State,
00391                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00392                         HAL_ADC_STATE_READY);
00393     }
00394   }
00395   else
00396   {
00397     /* Update ADC state machine to error */
00398     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00399
00400     tmp_hal_status = HAL_ERROR;
00401   }
00402
00403   /* Process unlocked */
00404   __HAL_UNLOCK(hadc);
00405
00406   /* Return function status */
00407   return tmp_hal_status;
00408 }
00409
00410 /**
00411   * @brief  Poll for injected conversion complete
00412   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00413   *         the configuration information for the specified ADC.
00414   * @param  Timeout: Timeout value in millisecond.
00415   * @retval HAL status
00416   */
00417 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00418 {
00419   uint32_t tickstart = 0;
00420
00421   /* Get tick */
00422   tickstart = HAL_GetTick();
00423
00424   /* Check End of conversion flag */
00425   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
00426   {
00427     /* Check for the Timeout */
00428     if(Timeout != HAL_MAX_DELAY)
00429     {
00430       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00431       {
00432         hadc->State= HAL_ADC_STATE_TIMEOUT;
00433         /* Process unlocked */
00434         __HAL_UNLOCK(hadc);
00435         return HAL_TIMEOUT;
00436       }
00437     }
00438   }
00439
00440   /* Clear injected group conversion flag */
00441   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
00442
00443   /* Update ADC state machine */
00444   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00445
00446   /* Determine whether any further conversion upcoming on group injected      */
00447   /* by external trigger, continuous mode or scan sequence on going.          */
00448   /* Note: On STM32F7, there is no independent flag of end of sequence.       */
00449   /*       The test of scan sequence on going is done either with scan        */
00450   /*       sequence disabled or with end of conversion flag set to            */
00451   /*       of end of sequence.                                                */
00452   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
00453      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
00454       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
00455      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
00456       (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
00457       (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
00458   {
00459     /* Set ADC state */
00460     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00461
00462     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00463     {
00464       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00465     }
00466   }
00467
00468   /* Return ADC state */
00469   return HAL_OK;
00470 }
00471
00472 /**
00473   * @brief  Stop conversion of injected channels, disable interruption of
00474   *         end-of-conversion. Disable ADC peripheral if no regular conversion
00475   *         is on going.
00476   * @note   If ADC must be disabled and if conversion is on going on
00477   *         regular group, function HAL_ADC_Stop must be used to stop both
00478   *         injected and regular groups, and disable the ADC.
00479   * @note   If injected group mode auto-injection is enabled,
00480   *         function HAL_ADC_Stop must be used.
00481   * @param  hadc: ADC handle
00482   * @retval None
00483   */
00484 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
00485 {
00486   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00487
00488   /* Check the parameters */
00489   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00490
00491   /* Process locked */
00492   __HAL_LOCK(hadc);
00493
00494   /* Stop potential conversion and disable ADC peripheral                     */
00495   /* Conditioned to:                                                          */
00496   /* - No conversion on the other group (regular group) is intended to        */
00497   /*   continue (injected and regular groups stop conversion and ADC disable  */
00498   /*   are common)                                                            */
00499   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
00500   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
00501      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
00502   {
00503     /* Stop potential conversion on going, on regular and injected groups */
00504     /* Disable ADC peripheral */
00505     __HAL_ADC_DISABLE(hadc);
00506
00507     /* Check if ADC is effectively disabled */
00508     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00509     {
00510       /* Disable ADC end of conversion interrupt for injected channels */
00511       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00512
00513       /* Set ADC state */
00514       ADC_STATE_CLR_SET(hadc->State,
00515                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00516                         HAL_ADC_STATE_READY);
00517     }
00518   }
00519   else
00520   {
00521     /* Update ADC state machine to error */
00522     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00523
00524     tmp_hal_status = HAL_ERROR;
00525   }
00526
00527   /* Process unlocked */
00528   __HAL_UNLOCK(hadc);
00529
00530   /* Return function status */
00531   return tmp_hal_status;
00532 }
00533
00534 /**
00535   * @brief  Gets the converted value from data register of injected channel.
00536   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00537   *         the configuration information for the specified ADC.
00538   * @param  InjectedRank: the ADC injected rank.
00539   *          This parameter can be one of the following values:
00540   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
00541   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
00542   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
00543   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
00544   * @retval None
00545   */
00546 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
00547 {
00548   __IO uint32_t tmp = 0;
00549
00550   /* Check the parameters */
00551   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
00552
00553   /* Clear injected group conversion flag to have similar behaviour as        */
00554   /* regular group: reading data register also clears end of conversion flag. */
00555   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00556
00557   /* Return the selected ADC converted value */
00558   switch(InjectedRank)
00559   {
00560     case ADC_INJECTED_RANK_4:
00561     {
00562       tmp =  hadc->Instance->JDR4;
00563     }
00564     break;
00565     case ADC_INJECTED_RANK_3:
00566     {
00567       tmp =  hadc->Instance->JDR3;
00568     }
00569     break;
00570     case ADC_INJECTED_RANK_2:
00571     {
00572       tmp =  hadc->Instance->JDR2;
00573     }
00574     break;
00575     case ADC_INJECTED_RANK_1:
00576     {
00577       tmp =  hadc->Instance->JDR1;
00578     }
00579     break;
00580     default:
00581     break;
00582   }
00583   return tmp;
00584 }
00585
00586 /**
00587   * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
00588   *
00589   * @note   Caution: This function must be used only with the ADC master.
00590   *
00591   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00592   *         the configuration information for the specified ADC.
00593   * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
00594   * @param  Length:  The length of data to be transferred from ADC peripheral to memory.
00595   * @retval HAL status
00596   */
00597 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00598 {
00599   __IO uint32_t counter = 0;
00600
00601   /* Check the parameters */
00602   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00603   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00604   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00605
00606   /* Process locked */
00607   __HAL_LOCK(hadc);
00608
00609   /* Check if ADC peripheral is disabled in order to enable it and wait during
00610      Tstab time the ADC's stabilization */
00611   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00612   {
00613     /* Enable the Peripheral */
00614     __HAL_ADC_ENABLE(hadc);
00615
00616     /* Delay for temperature sensor stabilization time */
00617     /* Compute number of CPU cycles to wait for */
00618     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
00619     while(counter != 0)
00620     {
00621       counter--;
00622     }
00623   }
00624
00625   /* Start conversion if ADC is effectively enabled */
00626   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00627   {
00628     /* Set ADC state                                                          */
00629     /* - Clear state bitfield related to regular group conversion results     */
00630     /* - Set state bitfield related to regular group operation                */
00631     ADC_STATE_CLR_SET(hadc->State,
00632                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
00633                       HAL_ADC_STATE_REG_BUSY);
00634
00635     /* If conversions on group regular are also triggering group injected,    */
00636     /* update ADC state.                                                      */
00637     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00638     {
00639       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00640     }
00641
00642     /* State machine update: Check if an injected conversion is ongoing */
00643     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00644     {
00645       /* Reset ADC error code fields related to conversions on group regular */
00646       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00647     }
00648     else
00649     {
00650       /* Reset ADC all error code fields */
00651       ADC_CLEAR_ERRORCODE(hadc);
00652     }
00653
00654     /* Process unlocked */
00655     /* Unlock before starting ADC conversions: in case of potential           */
00656     /* interruption, to let the process to ADC IRQ Handler.                   */
00657     __HAL_UNLOCK(hadc);
00658
00659     /* Set the DMA transfer complete callback */
00660     hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
00661
00662     /* Set the DMA half transfer complete callback */
00663     hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
00664
00665     /* Set the DMA error callback */
00666     hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
00667
00668     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
00669     /* start (in case of SW start):                                           */
00670
00671     /* Clear regular group conversion flag and overrun flag */
00672     /* (To ensure of no unknown state from potential previous ADC operations) */
00673     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00674
00675     /* Enable ADC overrun interrupt */
00676     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
00677
00678     if (hadc->Init.DMAContinuousRequests != DISABLE)
00679     {
00680       /* Enable the selected ADC DMA request after last transfer */
00681       ADC->CCR |= ADC_CCR_DDS;
00682     }
00683     else
00684     {
00685       /* Disable the selected ADC EOC rising on each regular channel conversion */
00686       ADC->CCR &= ~ADC_CCR_DDS;
00687     }
00688
00689     /* Enable the DMA Stream */
00690     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
00691
00692     /* if no external trigger present enable software conversion of regular channels */
00693     if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00694     {
00695       /* Enable the selected ADC software conversion for regular group */
00696       hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00697     }
00698   }
00699
00700   /* Return function status */
00701   return HAL_OK;
00702 }
00703
00704 /**
00705   * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
00706   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00707   *         the configuration information for the specified ADC.
00708   * @retval HAL status
00709   */
00710 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
00711 {
00712   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00713
00714   /* Check the parameters */
00715   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00716
00717   /* Process locked */
00718   __HAL_LOCK(hadc);
00719
00720   /* Stop potential conversion on going, on regular and injected groups */
00721   /* Disable ADC peripheral */
00722   __HAL_ADC_DISABLE(hadc);
00723
00724   /* Check if ADC is effectively disabled */
00725   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00726   {
00727     /* Disable the selected ADC DMA mode for multimode */
00728     ADC->CCR &= ~ADC_CCR_DDS;
00729
00730     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
00731     /* DMA transfer is on going)                                              */
00732     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
00733
00734     /* Disable ADC overrun interrupt */
00735     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
00736
00737     /* Set ADC state */
00738     ADC_STATE_CLR_SET(hadc->State,
00739                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00740                       HAL_ADC_STATE_READY);
00741   }
00742
00743   /* Process unlocked */
00744   __HAL_UNLOCK(hadc);
00745
00746   /* Return function status */
00747   return tmp_hal_status;
00748 }
00749
00750 /**
00751   * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results
00752   *         data in the selected multi mode.
00753   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00754   *         the configuration information for the specified ADC.
00755   * @retval The converted data value.
00756   */
00757 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
00758 {
00759   /* Return the multi mode conversion value */
00760   return ADC->CDR;
00761 }
00762
00763 /**
00764   * @brief  Injected conversion complete callback in non blocking mode
00765   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00766   *         the configuration information for the specified ADC.
00767   * @retval None
00768   */
00769 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
00770 {
00771   /* Prevent unused argument(s) compilation warning */
00772   UNUSED(hadc);
00773   /* NOTE : This function Should not be modified, when the callback is needed,
00774             the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
00775    */
00776 }
00777
00778 /**
00779   * @brief  Configures for the selected ADC injected channel its corresponding
00780   *         rank in the sequencer and its sample time.
00781   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00782   *         the configuration information for the specified ADC.
00783   * @param  sConfigInjected: ADC configuration structure for injected channel.
00784   * @retval None
00785   */
00786 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
00787 {
00788
00789 #ifdef USE_FULL_ASSERT
00790   uint32_t tmp = 0;
00791 #endif /* USE_FULL_ASSERT  */
00792
00793   /* Check the parameters */
00794   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
00795   assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
00796   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
00797   assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
00798   assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
00799   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
00800   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
00801
00802 #ifdef USE_FULL_ASSERT
00803   tmp = ADC_GET_RESOLUTION(hadc);
00804   assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
00805 #endif /* USE_FULL_ASSERT  */
00806
00807   if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
00808   {
00809     assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
00810   }
00811
00812   /* Process locked */
00813   __HAL_LOCK(hadc);
00814
00815   /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
00816   if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
00817   {
00818     /* Clear the old sample time */
00819     hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
00820
00821     /* Set the new sample time */
00822     hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
00823   }
00824   else /* ADC_Channel include in ADC_Channel_[0..9] */
00825   {
00826     /* Clear the old sample time */
00827     hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
00828
00829     /* Set the new sample time */
00830     hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
00831   }
00832
00833   /*---------------------------- ADCx JSQR Configuration -----------------*/
00834   hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
00835   hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
00836
00837   /* Rank configuration */
00838
00839   /* Clear the old SQx bits for the selected rank */
00840   hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
00841
00842   /* Set the SQx bits for the selected rank */
00843   hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
00844
00845   /* Enable external trigger if trigger selection is different of software  */
00846   /* start.                                                                 */
00847   /* Note: This configuration keeps the hardware feature of parameter       */
00848   /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00849   /*       software start.                                                  */
00850   if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
00851   {
00852     /* Select external trigger to start conversion */
00853     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
00854     hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
00855
00856     /* Select external trigger polarity */
00857     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
00858     hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
00859   }
00860   else
00861   {
00862     /* Reset the external trigger */
00863     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
00864     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
00865   }
00866
00867   if (sConfigInjected->AutoInjectedConv != DISABLE)
00868   {
00869     /* Enable the selected ADC automatic injected group conversion */
00870     hadc->Instance->CR1 |= ADC_CR1_JAUTO;
00871   }
00872   else
00873   {
00874     /* Disable the selected ADC automatic injected group conversion */
00875     hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
00876   }
00877
00878   if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
00879   {
00880     /* Enable the selected ADC injected discontinuous mode */
00881     hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
00882   }
00883   else
00884   {
00885     /* Disable the selected ADC injected discontinuous mode */
00886     hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
00887   }
00888
00889   switch(sConfigInjected->InjectedRank)
00890   {
00891     case 1:
00892       /* Set injected channel 1 offset */
00893       hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
00894       hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
00895       break;
00896     case 2:
00897       /* Set injected channel 2 offset */
00898       hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
00899       hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
00900       break;
00901     case 3:
00902       /* Set injected channel 3 offset */
00903       hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
00904       hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
00905       break;
00906     default:
00907       /* Set injected channel 4 offset */
00908       hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
00909       hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
00910       break;
00911   }
00912
00913   /* if ADC1 Channel_18 is selected enable VBAT Channel */
00914   if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
00915   {
00916     /* Enable the VBAT channel*/
00917     ADC->CCR |= ADC_CCR_VBATE;
00918   }
00919
00920   /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
00921   if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
00922   {
00923     /* Enable the TSVREFE channel*/
00924     ADC->CCR |= ADC_CCR_TSVREFE;
00925   }
00926
00927   /* Process unlocked */
00928   __HAL_UNLOCK(hadc);
00929
00930   /* Return function status */
00931   return HAL_OK;
00932 }
00933
00934 /**
00935   * @brief  Configures the ADC multi-mode
00936   * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
00937   *                     the configuration information for the specified ADC.
00938   * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains
00939   *                     the configuration information for  multimode.
00940   * @retval HAL status
00941   */
00942 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
00943 {
00944   /* Check the parameters */
00945   assert_param(IS_ADC_MODE(multimode->Mode));
00946   assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
00947   assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
00948
00949   /* Process locked */
00950   __HAL_LOCK(hadc);
00951
00952   /* Set ADC mode */
00953   ADC->CCR &= ~(ADC_CCR_MULTI);
00954   ADC->CCR |= multimode->Mode;
00955
00956   /* Set the ADC DMA access mode */
00957   ADC->CCR &= ~(ADC_CCR_DMA);
00958   ADC->CCR |= multimode->DMAAccessMode;
00959
00960   /* Set delay between two sampling phases */
00961   ADC->CCR &= ~(ADC_CCR_DELAY);
00962   ADC->CCR |= multimode->TwoSamplingDelay;
00963
00964   /* Process unlocked */
00965   __HAL_UNLOCK(hadc);
00966
00967   /* Return function status */
00968   return HAL_OK;
00969 }
00970
00971 /**
00972   * @}
00973   */
00974
00975   /**
00976   * @brief  DMA transfer complete callback.
00977   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00978   *                the configuration information for the specified DMA module.
00979   * @retval None
00980   */
00981 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
00982 {
00983   /* Retrieve ADC handle corresponding to current DMA handle */
00984   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00985
00986   /* Update state machine on conversion status if not in error state */
00987   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
00988   {
00989     /* Update ADC state machine */
00990     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
00991
00992     /* Determine whether any further conversion upcoming on group regular   */
00993     /* by external trigger, continuous mode or scan sequence on going.      */
00994     /* Note: On STM32F7, there is no independent flag of end of sequence.   */
00995     /*       The test of scan sequence on going is done either with scan    */
00996     /*       sequence disabled or with end of conversion flag set to        */
00997     /*       of end of sequence.                                            */
00998     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
00999        (hadc->Init.ContinuousConvMode == DISABLE)            &&
01000        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
01001         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
01002     {
01003       /* Disable ADC end of single conversion interrupt on group regular */
01004       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
01005       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
01006       /* by overrun IRQ process below.                                      */
01007       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
01008
01009       /* Set ADC state */
01010       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01011
01012       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01013       {
01014         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01015       }
01016     }
01017
01018     /* Conversion complete callback */
01019     HAL_ADC_ConvCpltCallback(hadc);
01020   }
01021   else
01022   {
01023     /* Call DMA error callback */
01024     hadc->DMA_Handle->XferErrorCallback(hdma);
01025   }
01026 }
01027
01028 /**
01029   * @brief  DMA half transfer complete callback.
01030   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01031   *                the configuration information for the specified DMA module.
01032   * @retval None
01033   */
01034 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
01035 {
01036     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01037     /* Conversion complete callback */
01038     HAL_ADC_ConvHalfCpltCallback(hadc);
01039 }
01040
01041 /**
01042   * @brief  DMA error callback
01043   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01044   *                the configuration information for the specified DMA module.
01045   * @retval None
01046   */
01047 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
01048 {
01049     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01050     hadc->State= HAL_ADC_STATE_ERROR_DMA;
01051     /* Set ADC error code to DMA error */
01052     hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
01053     HAL_ADC_ErrorCallback(hadc);
01054 }
01055
01056 /**
01057   * @}
01058   */
01059
01060 #endif /* HAL_ADC_MODULE_ENABLED */
01061 /**
01062   * @}
01063   */
01064
01065 /**
01066   * @}
01067   */
01068
01069 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_adc_ex.h Source File

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stm32f7xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of ADC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_ADC_EX_H
00040 #define __STM32F7xx_ADC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADCEx_Exported_Types ADC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  ADC Configuration injected Channel structure definition
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
00066   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00067   *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
00068   * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00069   *         ADC state can be either:
00070   *          - For all parameters: ADC disabled
00071   *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
00072   *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
00073   */
00074 typedef struct
00075 {
00076   uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
00077                                                This parameter can be a value of @ref ADC_channels
00078                                                Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
00079   uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
00080                                                This parameter must be a value of @ref ADCEx_injected_channel_selection
00081                                                Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00082   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00083                                                Unit: ADC clock cycles
00084                                                Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
00085                                                This parameter can be a value of @ref ADC_sampling_times
00086                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00087                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00088                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00089                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00090                                                      Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
00091   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
00092                                                Offset value must be a positive number.
00093                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits),
00094                                                this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
00095   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
00096                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00097                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00098                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00099                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00100   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00101                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00102                                                Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00103                                                This parameter can be set to ENABLE or DISABLE.
00104                                                Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
00105                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00106                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00107   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
00108                                                This parameter can be set to ENABLE or DISABLE.
00109                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00110                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
00111                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00112                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00113                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00114                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00115   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00116                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
00117                                                If set to external trigger source, triggering is on event rising edge.
00118                                                This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
00119                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00120                                                      If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
00121                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00122                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00123   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00124                                                This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
00125                                                If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
00126                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00127                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00128 }ADC_InjectionConfTypeDef;
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @brief ADC Configuration multi-mode structure definition
00135   */
00136 typedef struct
00137 {
00138   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode.
00139                                    This parameter can be a value of @ref ADCEx_Common_mode */
00140   uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.
00141                                    This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
00142   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00143                                    This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
00144 }ADC_MultiModeTypeDef;
00145
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /** @defgroup ADCEx_Exported_Constants ADC Exported Constants
00152   * @{
00153   */
00154
00155 /** @defgroup ADCEx_Common_mode ADC Common Mode
00156   * @{
00157   */
00158 #define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000)
00159 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
00160 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
00161 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
00162 #define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
00163 #define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
00164 #define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
00165 #define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
00166 #define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
00167 #define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
00168 #define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
00169 #define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
00170 #define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
00176   * @{
00177   */
00178 #define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000)     /*!< DMA mode disabled */
00179 #define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
00180 #define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
00181 #define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
00187   * @{
00188   */
00189 #define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000)
00190 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
00191 #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
00192 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
00198   * @{
00199   */
00200 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO         ((uint32_t)0x00000000)
00201 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4          ((uint32_t)ADC_CR2_JEXTSEL_0)
00202 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO         ((uint32_t)ADC_CR2_JEXTSEL_1)
00203 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00204 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4          ((uint32_t)ADC_CR2_JEXTSEL_2)
00205 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
00206
00207 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4          ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00208 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2        ((uint32_t)ADC_CR2_JEXTSEL_3)
00209 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
00210 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2        ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
00211 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00212 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
00213 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
00214 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
00215 #define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection
00221   * @{
00222   */
00223 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
00224 #define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
00225 #define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
00226 #define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup ADCEx_channels  ADC Specific Channels
00232   * @{
00233   */
00234 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | 0x10000000)
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 /* Exported macro ------------------------------------------------------------*/
00244 /** @defgroup ADC_Exported_Macros ADC Exported Macros
00245   * @{
00246   */
00247 /**
00248   * @}
00249   */
00250
00251 /* Exported functions --------------------------------------------------------*/
00252 /** @addtogroup ADCEx_Exported_Functions
00253   * @{
00254   */
00255
00256 /** @addtogroup ADCEx_Exported_Functions_Group1
00257   * @{
00258   */
00259
00260 /* I/O operation functions ******************************************************/
00261 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
00262 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
00263 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00264 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
00265 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
00266 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
00267 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00268 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
00269 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
00270 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
00271
00272 /* Peripheral Control functions *************************************************/
00273 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
00274 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283 /* Private types -------------------------------------------------------------*/
00284 /* Private variables ---------------------------------------------------------*/
00285 /* Private constants ---------------------------------------------------------*/
00286 /** @defgroup ADCEx_Private_Constants ADC Private Constants
00287   * @{
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /* Private macros ------------------------------------------------------------*/
00295 /** @defgroup ADCEx_Private_Macros ADC Private Macros
00296   * @{
00297   */
00298 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \
00299                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
00300
00301 #define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)                 || \
00302                                ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
00303                                ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
00304                                ((__MODE__) == ADC_DUALMODE_INJECSIMULT)             || \
00305                                ((__MODE__) == ADC_DUALMODE_REGSIMULT)               || \
00306                                ((__MODE__) == ADC_DUALMODE_INTERL)                  || \
00307                                ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               || \
00308                                ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
00309                                ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
00310                                ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT)           || \
00311                                ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT)             || \
00312                                ((__MODE__) == ADC_TRIPLEMODE_INTERL)                || \
00313                                ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))
00314 #define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
00315                                           ((__MODE__) == ADC_DMAACCESSMODE_1)        || \
00316                                           ((__MODE__) == ADC_DMAACCESSMODE_2)        || \
00317                                           ((__MODE__) == ADC_DMAACCESSMODE_3))
00318 #define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
00319                                               ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
00320                                               ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
00321                                               ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
00322 #define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
00323                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
00324                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
00325                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
00326                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
00327                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
00328                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
00329                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
00330                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
00331                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
00332                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
00333                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
00334                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
00335                                             ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
00336                                                                                         ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
00337 #define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
00338 #define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
00339
00340 /**
00341   * @brief  Set the selected injected Channel rank.
00342   * @param  _CHANNELNB_: Channel number.
00343   * @param  _RANKNB_: Rank number.
00344   * @param  _JSQR_JL_: Sequence length.
00345   * @retval None
00346   */
00347 #define   ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
00348 /**
00349   * @}
00350   */
00351
00352 /* Private functions ---------------------------------------------------------*/
00353 /** @defgroup ADCEx_Private_Functions ADC Private Functions
00354   * @{
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 #ifdef __cplusplus
00370 }
00371 #endif
00372
00373 #endif /*__STM32F7xx_ADC_EX_H */
00374
00375
00376 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_can.c Source File

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stm32f7xx_hal_can.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_can.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   CAN HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Controller Area Network (CAN) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#) Enable the CAN controller interface clock using
00021           __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
00022       -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
00023
00024       (#) CAN pins configuration
00025         (++) Enable the clock for the CAN GPIOs using the following function:
00026              __HAL_RCC_GPIOx_CLK_ENABLE()
00027         (++) Connect and configure the involved CAN pins to AF9 using the
00028               following function HAL_GPIO_Init()
00029
00030       (#) Initialize and configure the CAN using HAL_CAN_Init() function.
00031
00032       (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
00033
00034       (#) Receive a CAN frame using HAL_CAN_Receive() function.
00035
00036      *** Polling mode IO operation ***
00037      =================================
00038      [..]
00039        (+) Start the CAN peripheral transmission and wait the end of this operation
00040            using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
00041            according to his end application
00042        (+) Start the CAN peripheral reception and wait the end of this operation
00043            using HAL_CAN_Receive(), at this stage user can specify the value of timeout
00044            according to his end application
00045
00046      *** Interrupt mode IO operation ***
00047      ===================================
00048      [..]
00049        (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
00050        (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
00051        (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
00052        (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
00053             add his own code by customization of function pointer HAL_CAN_TxCpltCallback
00054        (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
00055             add his own code by customization of function pointer HAL_CAN_ErrorCallback
00056
00057      *** CAN HAL driver macros list ***
00058      =============================================
00059      [..]
00060        Below the list of most used macros in CAN HAL driver.
00061
00062       (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
00063       (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
00064       (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
00065       (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
00066       (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
00067
00068      [..]
00069       (@) You can refer to the CAN HAL driver header file for more useful macros
00070
00071   @endverbatim
00072
00073   ******************************************************************************
00074   * @attention
00075   *
00076   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00077   *
00078   * Redistribution and use in source and binary forms, with or without modification,
00079   * are permitted provided that the following conditions are met:
00080   *   1. Redistributions of source code must retain the above copyright notice,
00081   *      this list of conditions and the following disclaimer.
00082   *   2. Redistributions in binary form must reproduce the above copyright notice,
00083   *      this list of conditions and the following disclaimer in the documentation
00084   *      and/or other materials provided with the distribution.
00085   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00086   *      may be used to endorse or promote products derived from this software
00087   *      without specific prior written permission.
00088   *
00089   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00090   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00091   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00092   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00093   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00094   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00095   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00096   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00097   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00098   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00099   *
00100   ******************************************************************************
00101   */
00102
00103 /* Includes ------------------------------------------------------------------*/
00104 #include "stm32f7xx_hal.h"
00105
00106 /** @addtogroup STM32F7xx_HAL_Driver
00107   * @{
00108   */
00109
00110 /** @defgroup CAN CAN
00111   * @brief CAN driver modules
00112   * @{
00113   */
00114
00115 #ifdef HAL_CAN_MODULE_ENABLED
00116
00117
00118 /* Private typedef -----------------------------------------------------------*/
00119 /* Private define ------------------------------------------------------------*/
00120 /** @addtogroup CAN_Private_Constants
00121   * @{
00122   */
00123 #define CAN_TIMEOUT_VALUE  10
00124 /**
00125   * @}
00126   */
00127 /* Private macro -------------------------------------------------------------*/
00128 /* Private variables ---------------------------------------------------------*/
00129 /* Private function prototypes -----------------------------------------------*/
00130 /** @addtogroup CAN_Private_Functions
00131   * @{
00132   */
00133 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
00134 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
00135 /**
00136   * @}
00137   */
00138
00139 /* Exported functions --------------------------------------------------------*/
00140 /** @defgroup CAN_Exported_Functions CAN Exported Functions
00141   * @{
00142   */
00143
00144 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00145  *  @brief    Initialization and Configuration functions
00146  *
00147 @verbatim
00148   ==============================================================================
00149               ##### Initialization and de-initialization functions #####
00150   ==============================================================================
00151     [..]  This section provides functions allowing to:
00152       (+) Initialize and configure the CAN.
00153       (+) De-initialize the CAN.
00154
00155 @endverbatim
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Initializes the CAN peripheral according to the specified
00161   *         parameters in the CAN_InitStruct.
00162   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00163   *         the configuration information for the specified CAN.
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
00167 {
00168   uint32_t InitStatus = 3;
00169   uint32_t tickstart = 0;
00170
00171   /* Check CAN handle */
00172   if(hcan == NULL)
00173   {
00174      return HAL_ERROR;
00175   }
00176
00177   /* Check the parameters */
00178   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00179   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
00180   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
00181   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
00182   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
00183   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
00184   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
00185   assert_param(IS_CAN_MODE(hcan->Init.Mode));
00186   assert_param(IS_CAN_SJW(hcan->Init.SJW));
00187   assert_param(IS_CAN_BS1(hcan->Init.BS1));
00188   assert_param(IS_CAN_BS2(hcan->Init.BS2));
00189   assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
00190
00191
00192   if(hcan->State == HAL_CAN_STATE_RESET)
00193   {
00194     /* Allocate lock resource and initialize it */
00195     hcan->Lock = HAL_UNLOCKED;
00196     /* Init the low level hardware */
00197     HAL_CAN_MspInit(hcan);
00198   }
00199
00200   /* Initialize the CAN state*/
00201   hcan->State = HAL_CAN_STATE_BUSY;
00202
00203   /* Exit from sleep mode */
00204   hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
00205
00206   /* Request initialisation */
00207   hcan->Instance->MCR |= CAN_MCR_INRQ ;
00208
00209   /* Get tick */
00210   tickstart = HAL_GetTick();
00211
00212   /* Wait the acknowledge */
00213   while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00214   {
00215     if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
00216     {
00217       hcan->State= HAL_CAN_STATE_TIMEOUT;
00218       /* Process unlocked */
00219       __HAL_UNLOCK(hcan);
00220       return HAL_TIMEOUT;
00221     }
00222   }
00223
00224   /* Check acknowledge */
00225   if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00226   {
00227     InitStatus = CAN_INITSTATUS_FAILED;
00228   }
00229   else
00230   {
00231     /* Set the time triggered communication mode */
00232     if (hcan->Init.TTCM == ENABLE)
00233     {
00234       hcan->Instance->MCR |= CAN_MCR_TTCM;
00235     }
00236     else
00237     {
00238       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
00239     }
00240
00241     /* Set the automatic bus-off management */
00242     if (hcan->Init.ABOM == ENABLE)
00243     {
00244       hcan->Instance->MCR |= CAN_MCR_ABOM;
00245     }
00246     else
00247     {
00248       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
00249     }
00250
00251     /* Set the automatic wake-up mode */
00252     if (hcan->Init.AWUM == ENABLE)
00253     {
00254       hcan->Instance->MCR |= CAN_MCR_AWUM;
00255     }
00256     else
00257     {
00258       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
00259     }
00260
00261     /* Set the no automatic retransmission */
00262     if (hcan->Init.NART == ENABLE)
00263     {
00264       hcan->Instance->MCR |= CAN_MCR_NART;
00265     }
00266     else
00267     {
00268       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
00269     }
00270
00271     /* Set the receive FIFO locked mode */
00272     if (hcan->Init.RFLM == ENABLE)
00273     {
00274       hcan->Instance->MCR |= CAN_MCR_RFLM;
00275     }
00276     else
00277     {
00278       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
00279     }
00280
00281     /* Set the transmit FIFO priority */
00282     if (hcan->Init.TXFP == ENABLE)
00283     {
00284       hcan->Instance->MCR |= CAN_MCR_TXFP;
00285     }
00286     else
00287     {
00288       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
00289     }
00290
00291     /* Set the bit timing register */
00292     hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
00293                 ((uint32_t)hcan->Init.SJW) | \
00294                 ((uint32_t)hcan->Init.BS1) | \
00295                 ((uint32_t)hcan->Init.BS2) | \
00296                ((uint32_t)hcan->Init.Prescaler - 1);
00297
00298     /* Request leave initialisation */
00299     hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
00300
00301   /* Get tick */
00302   tickstart = HAL_GetTick();
00303
00304    /* Wait the acknowledge */
00305    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00306    {
00307     if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
00308      {
00309        hcan->State= HAL_CAN_STATE_TIMEOUT;
00310        /* Process unlocked */
00311        __HAL_UNLOCK(hcan);
00312        return HAL_TIMEOUT;
00313      }
00314    }
00315
00316     /* Check acknowledged */
00317     if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00318     {
00319       InitStatus = CAN_INITSTATUS_FAILED;
00320     }
00321     else
00322     {
00323       InitStatus = CAN_INITSTATUS_SUCCESS;
00324     }
00325   }
00326
00327   if(InitStatus == CAN_INITSTATUS_SUCCESS)
00328   {
00329     /* Set CAN error code to none */
00330     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00331
00332     /* Initialize the CAN state */
00333     hcan->State = HAL_CAN_STATE_READY;
00334
00335     /* Return function status */
00336     return HAL_OK;
00337   }
00338   else
00339   {
00340     /* Initialize the CAN state */
00341     hcan->State = HAL_CAN_STATE_ERROR;
00342
00343     /* Return function status */
00344     return HAL_ERROR;
00345   }
00346 }
00347
00348 /**
00349   * @brief  Configures the CAN reception filter according to the specified
00350   *         parameters in the CAN_FilterInitStruct.
00351   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00352   *         the configuration information for the specified CAN.
00353   * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
00354   *         contains the filter configuration information.
00355   * @retval None
00356   */
00357 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
00358 {
00359   uint32_t filternbrbitpos = 0;
00360
00361   /* Check the parameters */
00362   assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
00363   assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
00364   assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
00365   assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
00366   assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
00367   assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
00368
00369   filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
00370
00371   /* Initialisation mode for the filter */
00372   CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
00373
00374   /* Select the start slave bank */
00375   CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
00376   CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
00377
00378   /* Filter Deactivation */
00379   CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
00380
00381   /* Filter Scale */
00382   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
00383   {
00384     /* 16-bit scale for the filter */
00385     CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
00386
00387     /* First 16-bit identifier and First 16-bit mask */
00388     /* Or First 16-bit identifier and Second 16-bit identifier */
00389     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00390        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
00391         (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
00392
00393     /* Second 16-bit identifier and Second 16-bit mask */
00394     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00395     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00396        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
00397         (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
00398   }
00399
00400   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
00401   {
00402     /* 32-bit scale for the filter */
00403     CAN1->FS1R |= filternbrbitpos;
00404     /* 32-bit identifier or First 32-bit identifier */
00405     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00406        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
00407         (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
00408     /* 32-bit mask or Second 32-bit identifier */
00409     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00410        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
00411         (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
00412   }
00413
00414   /* Filter Mode */
00415   if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
00416   {
00417     /*Id/Mask mode for the filter*/
00418     CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
00419   }
00420   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00421   {
00422     /*Identifier list mode for the filter*/
00423     CAN1->FM1R |= (uint32_t)filternbrbitpos;
00424   }
00425
00426   /* Filter FIFO assignment */
00427   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
00428   {
00429     /* FIFO 0 assignation for the filter */
00430     CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
00431   }
00432
00433   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
00434   {
00435     /* FIFO 1 assignation for the filter */
00436     CAN1->FFA1R |= (uint32_t)filternbrbitpos;
00437   }
00438
00439   /* Filter activation */
00440   if (sFilterConfig->FilterActivation == ENABLE)
00441   {
00442     CAN1->FA1R |= filternbrbitpos;
00443   }
00444
00445   /* Leave the initialisation mode for the filter */
00446   CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
00447
00448   /* Return function status */
00449   return HAL_OK;
00450 }
00451
00452 /**
00453   * @brief  Deinitializes the CANx peripheral registers to their default reset values.
00454   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00455   *         the configuration information for the specified CAN.
00456   * @retval HAL status
00457   */
00458 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
00459 {
00460   /* Check CAN handle */
00461   if(hcan == NULL)
00462   {
00463      return HAL_ERROR;
00464   }
00465
00466   /* Check the parameters */
00467   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00468
00469   /* Change CAN state */
00470   hcan->State = HAL_CAN_STATE_BUSY;
00471
00472   /* DeInit the low level hardware */
00473   HAL_CAN_MspDeInit(hcan);
00474
00475   /* Change CAN state */
00476   hcan->State = HAL_CAN_STATE_RESET;
00477
00478   /* Release Lock */
00479   __HAL_UNLOCK(hcan);
00480
00481   /* Return function status */
00482   return HAL_OK;
00483 }
00484
00485 /**
00486   * @brief  Initializes the CAN MSP.
00487   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00488   *         the configuration information for the specified CAN.
00489   * @retval None
00490   */
00491 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
00492 {
00493   /* Prevent unused argument(s) compilation warning */
00494   UNUSED(hcan);
00495   /* NOTE : This function Should not be modified, when the callback is needed,
00496             the HAL_CAN_MspInit could be implemented in the user file
00497    */
00498 }
00499
00500 /**
00501   * @brief  DeInitializes the CAN MSP.
00502   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00503   *         the configuration information for the specified CAN.
00504   * @retval None
00505   */
00506 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
00507 {
00508   /* Prevent unused argument(s) compilation warning */
00509   UNUSED(hcan);
00510   /* NOTE : This function Should not be modified, when the callback is needed,
00511             the HAL_CAN_MspDeInit could be implemented in the user file
00512    */
00513 }
00514
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup CAN_Exported_Functions_Group2 IO operation functions
00520  *  @brief    IO operation functions
00521  *
00522 @verbatim
00523   ==============================================================================
00524                       ##### IO operation functions #####
00525   ==============================================================================
00526     [..]  This section provides functions allowing to:
00527       (+) Transmit a CAN frame message.
00528       (+) Receive a CAN frame message.
00529       (+) Enter CAN peripheral in sleep mode.
00530       (+) Wake up the CAN peripheral from sleep mode.
00531
00532 @endverbatim
00533   * @{
00534   */
00535
00536 /**
00537   * @brief  Initiates and transmits a CAN frame message.
00538   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00539   *         the configuration information for the specified CAN.
00540   * @param  Timeout: Specify Timeout value
00541   * @retval HAL status
00542   */
00543 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
00544 {
00545   uint32_t  transmitmailbox = 5;
00546   uint32_t tickstart = 0;
00547
00548   /* Check the parameters */
00549   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00550   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00551   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00552
00553   /* Process locked */
00554   __HAL_LOCK(hcan);
00555
00556   if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00557   {
00558     /* Change CAN state */
00559     hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00560   }
00561   else
00562   {
00563     /* Change CAN state */
00564     hcan->State = HAL_CAN_STATE_BUSY_TX;
00565   }
00566
00567   /* Select one empty transmit mailbox */
00568   if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00569   {
00570     transmitmailbox = 0;
00571   }
00572   else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00573   {
00574     transmitmailbox = 1;
00575   }
00576   else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
00577   {
00578     transmitmailbox = 2;
00579   }
00580   else
00581   {
00582     transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00583   }
00584
00585   if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
00586   {
00587     /* Set up the Id */
00588     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00589     if (hcan->pTxMsg->IDE == CAN_ID_STD)
00590     {
00591       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00592       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
00593                                                   hcan->pTxMsg->RTR);
00594     }
00595     else
00596     {
00597       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00598       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
00599                                                   hcan->pTxMsg->IDE | \
00600                                                   hcan->pTxMsg->RTR);
00601     }
00602
00603     /* Set up the DLC */
00604     hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
00605     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
00606     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00607
00608     /* Set up the data field */
00609     hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
00610                                              ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
00611                                              ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
00612                                              ((uint32_t)hcan->pTxMsg->Data[0]));
00613     hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
00614                                              ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
00615                                              ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
00616                                              ((uint32_t)hcan->pTxMsg->Data[4]));
00617     /* Request transmission */
00618     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00619
00620   /* Get tick */
00621   tickstart = HAL_GetTick();
00622
00623     /* Check End of transmission flag */
00624     while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
00625     {
00626       /* Check for the Timeout */
00627       if(Timeout != HAL_MAX_DELAY)
00628       {
00629        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00630        {
00631          hcan->State = HAL_CAN_STATE_TIMEOUT;
00632          /* Process unlocked */
00633          __HAL_UNLOCK(hcan);
00634          return HAL_TIMEOUT;
00635         }
00636       }
00637     }
00638     if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00639     {
00640       /* Change CAN state */
00641       hcan->State = HAL_CAN_STATE_BUSY_RX;
00642
00643       /* Process unlocked */
00644       __HAL_UNLOCK(hcan);
00645     }
00646     else
00647     {
00648       /* Change CAN state */
00649       hcan->State = HAL_CAN_STATE_READY;
00650
00651       /* Process unlocked */
00652       __HAL_UNLOCK(hcan);
00653     }
00654
00655     /* Return function status */
00656     return HAL_OK;
00657   }
00658   else
00659   {
00660     /* Change CAN state */
00661     hcan->State = HAL_CAN_STATE_ERROR;
00662
00663     /* Process unlocked */
00664     __HAL_UNLOCK(hcan);
00665
00666     /* Return function status */
00667     return HAL_ERROR;
00668   }
00669 }
00670
00671 /**
00672   * @brief  Initiates and transmits a CAN frame message.
00673   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00674   *         the configuration information for the specified CAN.
00675   * @retval HAL status
00676   */
00677 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
00678 {
00679   uint32_t  transmitmailbox = 5;
00680   uint32_t tmp = 0;
00681
00682   /* Check the parameters */
00683   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00684   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00685   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00686
00687   tmp = hcan->State;
00688   if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))
00689   {
00690     /* Process Locked */
00691     __HAL_LOCK(hcan);
00692
00693     /* Select one empty transmit mailbox */
00694     if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00695     {
00696       transmitmailbox = 0;
00697     }
00698     else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00699     {
00700       transmitmailbox = 1;
00701     }
00702     else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
00703     {
00704       transmitmailbox = 2;
00705     }
00706     else
00707     {
00708       transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00709     }
00710
00711     if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
00712     {
00713       /* Set up the Id */
00714       hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00715       if(hcan->pTxMsg->IDE == CAN_ID_STD)
00716       {
00717         assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00718         hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
00719                                                   hcan->pTxMsg->RTR);
00720       }
00721       else
00722       {
00723         assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00724         hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
00725                                                   hcan->pTxMsg->IDE | \
00726                                                   hcan->pTxMsg->RTR);
00727       }
00728
00729       /* Set up the DLC */
00730       hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
00731       hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
00732       hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00733
00734       /* Set up the data field */
00735       hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
00736                                              ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
00737                                              ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
00738                                              ((uint32_t)hcan->pTxMsg->Data[0]));
00739       hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
00740                                              ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
00741                                              ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
00742                                              ((uint32_t)hcan->pTxMsg->Data[4]));
00743
00744       if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00745       {
00746         /* Change CAN state */
00747         hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00748       }
00749       else
00750       {
00751         /* Change CAN state */
00752         hcan->State = HAL_CAN_STATE_BUSY_TX;
00753       }
00754
00755       /* Set CAN error code to none */
00756       hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00757
00758       /* Process Unlocked */
00759       __HAL_UNLOCK(hcan);
00760
00761       /* Enable Error warning Interrupt */
00762       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
00763
00764       /* Enable Error passive Interrupt */
00765       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
00766
00767       /* Enable Bus-off Interrupt */
00768       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
00769
00770       /* Enable Last error code Interrupt */
00771       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
00772
00773       /* Enable Error Interrupt */
00774       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
00775
00776       /* Enable Transmit mailbox empty Interrupt */
00777       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
00778
00779       /* Request transmission */
00780       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00781     }
00782   }
00783   else
00784   {
00785     return HAL_BUSY;
00786   }
00787
00788   return HAL_OK;
00789 }
00790
00791 /**
00792   * @brief  Receives a correct CAN frame.
00793   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00794   *         the configuration information for the specified CAN.
00795   * @param  FIFONumber: FIFO Number value
00796   * @param  Timeout: Specify Timeout value
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
00800 {
00801   uint32_t tickstart = 0;
00802
00803   /* Check the parameters */
00804   assert_param(IS_CAN_FIFO(FIFONumber));
00805
00806   /* Process locked */
00807   __HAL_LOCK(hcan);
00808
00809   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00810   {
00811     /* Change CAN state */
00812     hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00813   }
00814   else
00815   {
00816     /* Change CAN state */
00817     hcan->State = HAL_CAN_STATE_BUSY_RX;
00818   }
00819
00820   /* Get tick */
00821   tickstart = HAL_GetTick();
00822
00823   /* Check pending message */
00824   while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
00825   {
00826     /* Check for the Timeout */
00827     if(Timeout != HAL_MAX_DELAY)
00828     {
00829       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00830       {
00831         hcan->State = HAL_CAN_STATE_TIMEOUT;
00832         /* Process unlocked */
00833         __HAL_UNLOCK(hcan);
00834         return HAL_TIMEOUT;
00835       }
00836     }
00837   }
00838
00839   /* Get the Id */
00840   hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00841   if (hcan->pRxMsg->IDE == CAN_ID_STD)
00842   {
00843     hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
00844   }
00845   else
00846   {
00847     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
00848   }
00849
00850   hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00851   /* Get the DLC */
00852   hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
00853   /* Get the FMI */
00854   hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
00855   /* Get the data field */
00856   hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
00857   hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
00858   hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
00859   hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
00860   hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
00861   hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
00862   hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
00863   hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
00864
00865   /* Release the FIFO */
00866   if(FIFONumber == CAN_FIFO0)
00867   {
00868     /* Release FIFO0 */
00869     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
00870   }
00871   else /* FIFONumber == CAN_FIFO1 */
00872   {
00873     /* Release FIFO1 */
00874     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
00875   }
00876
00877   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00878   {
00879     /* Change CAN state */
00880     hcan->State = HAL_CAN_STATE_BUSY_TX;
00881
00882     /* Process unlocked */
00883     __HAL_UNLOCK(hcan);
00884   }
00885   else
00886   {
00887     /* Change CAN state */
00888     hcan->State = HAL_CAN_STATE_READY;
00889
00890     /* Process unlocked */
00891     __HAL_UNLOCK(hcan);
00892   }
00893
00894   /* Return function status */
00895   return HAL_OK;
00896 }
00897
00898 /**
00899   * @brief  Receives a correct CAN frame.
00900   * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
00901   *         the configuration information for the specified CAN.
00902   * @param  FIFONumber: Specify the FIFO number
00903   * @retval HAL status
00904   */
00905 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
00906 {
00907   uint32_t tmp = 0;
00908
00909   /* Check the parameters */
00910   assert_param(IS_CAN_FIFO(FIFONumber));
00911
00912   tmp = hcan->State;
00913   if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
00914   {
00915     /* Process locked */
00916     __HAL_LOCK(hcan);
00917
00918     if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00919     {
00920       /* Change CAN state */
00921       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00922     }
00923     else
00924     {
00925       /* Change CAN state */
00926       hcan->State = HAL_CAN_STATE_BUSY_RX;
00927     }
00928
00929     /* Set CAN error code to none */
00930     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00931
00932     /* Enable Error warning Interrupt */
00933     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
00934
00935     /* Enable Error passive Interrupt */
00936     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
00937
00938     /* Enable Bus-off Interrupt */
00939     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
00940
00941     /* Enable Last error code Interrupt */
00942     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
00943
00944     /* Enable Error Interrupt */
00945     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
00946
00947     /* Process unlocked */
00948     __HAL_UNLOCK(hcan);
00949
00950     if(FIFONumber == CAN_FIFO0)
00951     {
00952       /* Enable FIFO 0 message pending Interrupt */
00953       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
00954     }
00955     else
00956     {
00957       /* Enable FIFO 1 message pending Interrupt */
00958       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
00959     }
00960
00961   }
00962   else
00963   {
00964     return HAL_BUSY;
00965   }
00966
00967   /* Return function status */
00968   return HAL_OK;
00969 }
00970
00971 /**
00972   * @brief  Enters the Sleep (low power) mode.
00973   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00974   *         the configuration information for the specified CAN.
00975   * @retval HAL status.
00976   */
00977 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
00978 {
00979   uint32_t tickstart = 0;
00980
00981   /* Process locked */
00982   __HAL_LOCK(hcan);
00983
00984   /* Change CAN state */
00985   hcan->State = HAL_CAN_STATE_BUSY;
00986
00987   /* Request Sleep mode */
00988    hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00989
00990   /* Sleep mode status */
00991   if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
00992   {
00993     /* Process unlocked */
00994     __HAL_UNLOCK(hcan);
00995
00996     /* Return function status */
00997     return HAL_ERROR;
00998   }
00999
01000   /* Get tick */
01001   tickstart = HAL_GetTick();
01002
01003   /* Wait the acknowledge */
01004   while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
01005   {
01006     if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
01007     {
01008       hcan->State = HAL_CAN_STATE_TIMEOUT;
01009       /* Process unlocked */
01010       __HAL_UNLOCK(hcan);
01011       return HAL_TIMEOUT;
01012     }
01013   }
01014
01015   /* Change CAN state */
01016   hcan->State = HAL_CAN_STATE_READY;
01017
01018   /* Process unlocked */
01019   __HAL_UNLOCK(hcan);
01020
01021   /* Return function status */
01022   return HAL_OK;
01023 }
01024
01025 /**
01026   * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
01027   *         is in the normal mode.
01028   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01029   *         the configuration information for the specified CAN.
01030   * @retval HAL status.
01031   */
01032 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
01033 {
01034   uint32_t tickstart = 0;
01035
01036   /* Process locked */
01037   __HAL_LOCK(hcan);
01038
01039   /* Change CAN state */
01040   hcan->State = HAL_CAN_STATE_BUSY;
01041
01042   /* Wake up request */
01043   hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
01044
01045   /* Get tick */
01046   tickstart = HAL_GetTick();
01047
01048   /* Sleep mode status */
01049   while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01050   {
01051     if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
01052     {
01053       hcan->State= HAL_CAN_STATE_TIMEOUT;
01054       /* Process unlocked */
01055       __HAL_UNLOCK(hcan);
01056       return HAL_TIMEOUT;
01057     }
01058   }
01059   if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01060   {
01061     /* Process unlocked */
01062     __HAL_UNLOCK(hcan);
01063
01064     /* Return function status */
01065     return HAL_ERROR;
01066   }
01067
01068   /* Change CAN state */
01069   hcan->State = HAL_CAN_STATE_READY;
01070
01071   /* Process unlocked */
01072   __HAL_UNLOCK(hcan);
01073
01074   /* Return function status */
01075   return HAL_OK;
01076 }
01077
01078 /**
01079   * @brief  Handles CAN interrupt request
01080   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01081   *         the configuration information for the specified CAN.
01082   * @retval None
01083   */
01084 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
01085 {
01086   uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
01087
01088   /* Check End of transmission flag */
01089   if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
01090   {
01091     tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
01092     tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
01093     tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
01094     if(tmp1 || tmp2 || tmp3)
01095     {
01096       /* Call transmit function */
01097       CAN_Transmit_IT(hcan);
01098     }
01099   }
01100
01101   tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
01102   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
01103   /* Check End of reception flag for FIFO0 */
01104   if((tmp1 != 0) && tmp2)
01105   {
01106     /* Call receive function */
01107     CAN_Receive_IT(hcan, CAN_FIFO0);
01108   }
01109
01110   tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
01111   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
01112   /* Check End of reception flag for FIFO1 */
01113   if((tmp1 != 0) && tmp2)
01114   {
01115     /* Call receive function */
01116     CAN_Receive_IT(hcan, CAN_FIFO1);
01117   }
01118
01119   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
01120   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
01121   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01122   /* Check Error Warning Flag */
01123   if(tmp1 && tmp2 && tmp3)
01124   {
01125     /* Set CAN error code to EWG error */
01126     hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
01127     /* Clear Error Warning Flag */
01128     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);
01129   }
01130
01131   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
01132   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
01133   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01134   /* Check Error Passive Flag */
01135   if(tmp1 && tmp2 && tmp3)
01136   {
01137     /* Set CAN error code to EPV error */
01138     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
01139     /* Clear Error Passive Flag */
01140     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);
01141   }
01142
01143   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
01144   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
01145   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01146   /* Check Bus-Off Flag */
01147   if(tmp1 && tmp2 && tmp3)
01148   {
01149     /* Set CAN error code to BOF error */
01150     hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
01151     /* Clear Bus-Off Flag */
01152     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);
01153   }
01154
01155   tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
01156   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
01157   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01158   /* Check Last error code Flag */
01159   if((!tmp1) && tmp2 && tmp3)
01160   {
01161     tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
01162     switch(tmp1)
01163     {
01164       case(CAN_ESR_LEC_0):
01165           /* Set CAN error code to STF error */
01166           hcan->ErrorCode |= HAL_CAN_ERROR_STF;
01167           break;
01168       case(CAN_ESR_LEC_1):
01169           /* Set CAN error code to FOR error */
01170           hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
01171           break;
01172       case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
01173           /* Set CAN error code to ACK error */
01174           hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
01175           break;
01176       case(CAN_ESR_LEC_2):
01177           /* Set CAN error code to BR error */
01178           hcan->ErrorCode |= HAL_CAN_ERROR_BR;
01179           break;
01180       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
01181           /* Set CAN error code to BD error */
01182           hcan->ErrorCode |= HAL_CAN_ERROR_BD;
01183           break;
01184       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
01185           /* Set CAN error code to CRC error */
01186           hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
01187           break;
01188       default:
01189           break;
01190     }
01191
01192     /* Clear Last error code Flag */
01193     hcan->Instance->ESR &= ~(CAN_ESR_LEC);
01194   }
01195
01196   /* Call the Error call Back in case of Errors */
01197   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
01198   {
01199     /* Clear ERRI Flag */
01200     hcan->Instance->MSR |= CAN_MSR_ERRI;
01201     /* Set the CAN state ready to be able to start again the process */
01202     hcan->State = HAL_CAN_STATE_READY;
01203     /* Call Error callback function */
01204     HAL_CAN_ErrorCallback(hcan);
01205   }
01206 }
01207
01208 /**
01209   * @brief  Transmission  complete callback in non blocking mode
01210   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01211   *         the configuration information for the specified CAN.
01212   * @retval None
01213   */
01214 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
01215 {
01216   /* Prevent unused argument(s) compilation warning */
01217   UNUSED(hcan);
01218   /* NOTE : This function Should not be modified, when the callback is needed,
01219             the HAL_CAN_TxCpltCallback could be implemented in the user file
01220    */
01221 }
01222
01223 /**
01224   * @brief  Transmission  complete callback in non blocking mode
01225   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01226   *         the configuration information for the specified CAN.
01227   * @retval None
01228   */
01229 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
01230 {
01231   /* Prevent unused argument(s) compilation warning */
01232   UNUSED(hcan);
01233   /* NOTE : This function Should not be modified, when the callback is needed,
01234             the HAL_CAN_RxCpltCallback could be implemented in the user file
01235    */
01236 }
01237
01238 /**
01239   * @brief  Error CAN callback.
01240   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01241   *         the configuration information for the specified CAN.
01242   * @retval None
01243   */
01244 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
01245 {
01246   /* Prevent unused argument(s) compilation warning */
01247   UNUSED(hcan);
01248   /* NOTE : This function Should not be modified, when the callback is needed,
01249             the HAL_CAN_ErrorCallback could be implemented in the user file
01250    */
01251 }
01252
01253 /**
01254   * @}
01255   */
01256
01257 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
01258  *  @brief   CAN Peripheral State functions
01259  *
01260 @verbatim
01261   ==============================================================================
01262             ##### Peripheral State and Error functions #####
01263   ==============================================================================
01264     [..]
01265     This subsection provides functions allowing to :
01266       (+) Check the CAN state.
01267       (+) Check CAN Errors detected during interrupt process
01268
01269 @endverbatim
01270   * @{
01271   */
01272
01273 /**
01274   * @brief  return the CAN state
01275   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01276   *         the configuration information for the specified CAN.
01277   * @retval HAL state
01278   */
01279 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
01280 {
01281   /* Return CAN state */
01282   return hcan->State;
01283 }
01284
01285 /**
01286   * @brief  Return the CAN error code
01287   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01288   *         the configuration information for the specified CAN.
01289   * @retval CAN Error Code
01290   */
01291 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
01292 {
01293   return hcan->ErrorCode;
01294 }
01295
01296 /**
01297   * @}
01298   */
01299 /**
01300   * @brief  Initiates and transmits a CAN frame message.
01301   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01302   *         the configuration information for the specified CAN.
01303   * @retval HAL status
01304   */
01305 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
01306 {
01307   /* Disable Transmit mailbox empty Interrupt */
01308   __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
01309
01310   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
01311   {
01312     /* Disable Error warning Interrupt */
01313     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
01314
01315     /* Disable Error passive Interrupt */
01316     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
01317
01318     /* Disable Bus-off Interrupt */
01319     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
01320
01321     /* Disable Last error code Interrupt */
01322     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
01323
01324     /* Disable Error Interrupt */
01325     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
01326   }
01327
01328   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01329   {
01330     /* Change CAN state */
01331     hcan->State = HAL_CAN_STATE_BUSY_RX;
01332   }
01333   else
01334   {
01335     /* Change CAN state */
01336     hcan->State = HAL_CAN_STATE_READY;
01337   }
01338
01339   /* Transmission complete callback */
01340   HAL_CAN_TxCpltCallback(hcan);
01341
01342   return HAL_OK;
01343 }
01344
01345 /**
01346   * @brief  Receives a correct CAN frame.
01347   * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
01348   *         the configuration information for the specified CAN.
01349   * @param  FIFONumber: Specify the FIFO number
01350   * @retval HAL status
01351   * @retval None
01352   */
01353 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
01354 {
01355   /* Get the Id */
01356   hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01357   if (hcan->pRxMsg->IDE == CAN_ID_STD)
01358   {
01359     hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
01360   }
01361   else
01362   {
01363     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
01364   }
01365
01366   hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01367   /* Get the DLC */
01368   hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
01369   /* Get the FMI */
01370   hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
01371   /* Get the data field */
01372   hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
01373   hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
01374   hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
01375   hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
01376   hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
01377   hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
01378   hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
01379   hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
01380   /* Release the FIFO */
01381   /* Release FIFO0 */
01382   if (FIFONumber == CAN_FIFO0)
01383   {
01384     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
01385
01386     /* Disable FIFO 0 message pending Interrupt */
01387     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
01388   }
01389   /* Release FIFO1 */
01390   else /* FIFONumber == CAN_FIFO1 */
01391   {
01392     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
01393
01394     /* Disable FIFO 1 message pending Interrupt */
01395     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
01396   }
01397
01398   if(hcan->State == HAL_CAN_STATE_BUSY_RX)
01399   {
01400     /* Disable Error warning Interrupt */
01401     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
01402
01403     /* Disable Error passive Interrupt */
01404     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
01405
01406     /* Disable Bus-off Interrupt */
01407     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
01408
01409     /* Disable Last error code Interrupt */
01410     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
01411
01412     /* Disable Error Interrupt */
01413     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
01414   }
01415
01416   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01417   {
01418     /* Disable CAN state */
01419     hcan->State = HAL_CAN_STATE_BUSY_TX;
01420   }
01421   else
01422   {
01423     /* Change CAN state */
01424     hcan->State = HAL_CAN_STATE_READY;
01425   }
01426
01427   /* Receive complete callback */
01428   HAL_CAN_RxCpltCallback(hcan);
01429
01430   /* Return function status */
01431   return HAL_OK;
01432 }
01433
01434 /**
01435  * @}
01436  */
01437
01438 #endif /* HAL_CAN_MODULE_ENABLED */
01439 /**
01440   * @}
01441   */
01442
01443 /**
01444   * @}
01445   */
01446
01447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_can.h Source File

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stm32f7xx_hal_can.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_can.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CAN HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CAN_H
00040 #define __STM32F7xx_HAL_CAN_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CAN
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup CAN_Exported_Types CAN Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
00068   HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
00069   HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
00070   HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
00071   HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
00072   HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
00073   HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
00074   HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
00075
00076 }HAL_CAN_StateTypeDef;
00077
00078 /**
00079   * @brief  CAN init structure definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
00084                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00085
00086   uint32_t Mode;       /*!< Specifies the CAN operating mode.
00087                             This parameter can be a value of @ref CAN_operating_mode */
00088
00089   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
00090                             the CAN hardware is allowed to lengthen or
00091                             shorten a bit to perform resynchronization.
00092                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
00093
00094   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
00095                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
00096
00097   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
00098                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
00099
00100   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
00101                             This parameter can be set to ENABLE or DISABLE. */
00102
00103   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
00104                             This parameter can be set to ENABLE or DISABLE */
00105
00106   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
00107                             This parameter can be set to ENABLE or DISABLE */
00108
00109   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
00110                             This parameter can be set to ENABLE or DISABLE */
00111
00112   uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
00113                             This parameter can be set to ENABLE or DISABLE */
00114
00115   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
00116                             This parameter can be set to ENABLE or DISABLE */
00117 }CAN_InitTypeDef;
00118
00119 /**
00120   * @brief  CAN filter configuration structure definition
00121   */
00122 typedef struct
00123 {
00124   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
00125                                        configuration, first one for a 16-bit configuration).
00126                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00127
00128   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
00129                                        configuration, second one for a 16-bit configuration).
00130                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00131
00132   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
00133                                        according to the mode (MSBs for a 32-bit configuration,
00134                                        first one for a 16-bit configuration).
00135                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00136
00137   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
00138                                        according to the mode (LSBs for a 32-bit configuration,
00139                                        second one for a 16-bit configuration).
00140                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00141
00142   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
00143                                        This parameter can be a value of @ref CAN_filter_FIFO */
00144
00145   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
00146                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
00147
00148   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
00149                                        This parameter can be a value of @ref CAN_filter_mode */
00150
00151   uint32_t FilterScale;           /*!< Specifies the filter scale.
00152                                        This parameter can be a value of @ref CAN_filter_scale */
00153
00154   uint32_t FilterActivation;      /*!< Enable or disable the filter.
00155                                        This parameter can be set to ENABLE or DISABLE. */
00156
00157   uint32_t BankNumber;            /*!< Select the start slave bank filter.
00158                                        This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
00159
00160 }CAN_FilterConfTypeDef;
00161
00162 /**
00163   * @brief  CAN Tx message structure definition
00164   */
00165 typedef struct
00166 {
00167   uint32_t StdId;    /*!< Specifies the standard identifier.
00168                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00169
00170   uint32_t ExtId;    /*!< Specifies the extended identifier.
00171                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
00172
00173   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
00174                           This parameter can be a value of @ref CAN_Identifier_Type */
00175
00176   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
00177                           This parameter can be a value of @ref CAN_remote_transmission_request */
00178
00179   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
00180                           This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00181
00182   uint8_t Data[8];  /*!< Contains the data to be transmitted.
00183                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00184
00185 }CanTxMsgTypeDef;
00186
00187 /**
00188   * @brief  CAN Rx message structure definition
00189   */
00190 typedef struct
00191 {
00192   uint32_t StdId;       /*!< Specifies the standard identifier.
00193                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00194
00195   uint32_t ExtId;       /*!< Specifies the extended identifier.
00196                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
00197
00198   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
00199                              This parameter can be a value of @ref CAN_Identifier_Type */
00200
00201   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
00202                              This parameter can be a value of @ref CAN_remote_transmission_request */
00203
00204   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
00205                              This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00206
00207   uint8_t Data[8];      /*!< Contains the data to be received.
00208                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00209
00210   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
00211                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00212
00213   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
00214                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
00215
00216 }CanRxMsgTypeDef;
00217
00218 /**
00219   * @brief  CAN handle Structure definition
00220   */
00221 typedef struct
00222 {
00223   CAN_TypeDef                 *Instance;  /*!< Register base address          */
00224
00225   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
00226
00227   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
00228
00229   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
00230
00231   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
00232
00233   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
00234
00235   __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
00236
00237 }CAN_HandleTypeDef;
00238
00239 /**
00240   * @}
00241   */
00242
00243 /* Exported constants --------------------------------------------------------*/
00244 /** @defgroup CAN_Exported_Constants CAN Exported Constants
00245   * @{
00246   */
00247
00248 /** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
00249   * @{
00250   */
00251 #define   HAL_CAN_ERROR_NONE      0x00    /*!< No error             */
00252 #define   HAL_CAN_ERROR_EWG       0x01    /*!< EWG error            */
00253 #define   HAL_CAN_ERROR_EPV       0x02    /*!< EPV error            */
00254 #define   HAL_CAN_ERROR_BOF       0x04    /*!< BOF error            */
00255 #define   HAL_CAN_ERROR_STF       0x08    /*!< Stuff error          */
00256 #define   HAL_CAN_ERROR_FOR       0x10    /*!< Form error           */
00257 #define   HAL_CAN_ERROR_ACK       0x20    /*!< Acknowledgment error */
00258 #define   HAL_CAN_ERROR_BR        0x40    /*!< Bit recessive        */
00259 #define   HAL_CAN_ERROR_BD        0x80    /*!< LEC dominant         */
00260 #define   HAL_CAN_ERROR_CRC       0x100   /*!< LEC transfer error   */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup CAN_InitStatus CAN InitStatus
00266   * @{
00267   */
00268 #define CAN_INITSTATUS_FAILED       ((uint8_t)0x00)  /*!< CAN initialization failed */
00269 #define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01)  /*!< CAN initialization OK */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup CAN_operating_mode CAN Operating Mode
00275   * @{
00276   */
00277 #define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
00278 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
00279 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
00280 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
00286   * @{
00287   */
00288 #define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
00289 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
00290 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
00291 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
00297   * @{
00298   */
00299 #define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
00300 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
00301 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
00302 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
00303 #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
00304 #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
00305 #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
00306 #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
00307 #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
00308 #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
00309 #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
00310 #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
00311 #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
00312 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
00313 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
00314 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
00320   * @{
00321   */
00322 #define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
00323 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
00324 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
00325 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
00326 #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
00327 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
00328 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
00329 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup CAN_filter_mode  CAN Filter Mode
00335   * @{
00336   */
00337 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
00338 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup CAN_filter_scale CAN Filter Scale
00344   * @{
00345   */
00346 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
00347 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
00353   * @{
00354   */
00355 #define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
00356 #define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup CAN_Identifier_Type CAN Identifier Type
00362   * @{
00363   */
00364 #define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
00365 #define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
00371   * @{
00372   */
00373 #define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
00374 #define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
00380   * @{
00381   */
00382 #define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
00383 #define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup CAN_flags CAN Flags
00389   * @{
00390   */
00391 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
00392    and CAN_ClearFlag() functions. */
00393 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
00394    CAN_GetFlagStatus() function.  */
00395
00396 /* Transmit Flags */
00397 #define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
00398 #define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
00399 #define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
00400 #define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
00401 #define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
00402 #define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
00403 #define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
00404 #define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
00405 #define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
00406
00407 /* Receive Flags */
00408 #define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
00409 #define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
00410
00411 #define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
00412 #define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
00413
00414 /* Operating Mode Flags */
00415 #define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
00416 #define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
00417 #define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
00418 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
00419          In this case the SLAK bit can be polled.*/
00420
00421 /* Error Flags */
00422 #define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
00423 #define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
00424 #define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup CAN_Interrupts CAN Interrupts
00430   * @{
00431   */
00432 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
00433
00434 /* Receive Interrupts */
00435 #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
00436 #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
00437 #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
00438 #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
00439 #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
00440 #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
00441
00442 /* Operating Mode Interrupts */
00443 #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
00444 #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
00445
00446 /* Error Interrupts */
00447 #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
00448 #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
00449 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
00450 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
00451 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
00457   * @{
00458   */
00459 #define CAN_TXMAILBOX_0   ((uint8_t)0x00)
00460 #define CAN_TXMAILBOX_1   ((uint8_t)0x01)
00461 #define CAN_TXMAILBOX_2   ((uint8_t)0x02)
00462 /**
00463   * @}
00464   */
00465
00466 /**
00467   * @}
00468   */
00469
00470 /* Exported macro ------------------------------------------------------------*/
00471 /** @defgroup CAN_Exported_Macros CAN Exported Macros
00472   * @{
00473   */
00474
00475 /** @brief Reset CAN handle state
00476   * @param  __HANDLE__: specifies the CAN Handle.
00477   * @retval None
00478   */
00479 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
00480
00481 /**
00482   * @brief  Enable the specified CAN interrupts.
00483   * @param  __HANDLE__: CAN handle
00484   * @param  __INTERRUPT__: CAN Interrupt
00485   * @retval None
00486   */
00487 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00488
00489 /**
00490   * @brief  Disable the specified CAN interrupts.
00491   * @param  __HANDLE__: CAN handle
00492   * @param  __INTERRUPT__: CAN Interrupt
00493   * @retval None
00494   */
00495 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00496
00497 /**
00498   * @brief  Return the number of pending received messages.
00499   * @param  __HANDLE__: CAN handle
00500   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00501   * @retval The number of pending message.
00502   */
00503 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00504 ((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
00505
00506 /** @brief  Check whether the specified CAN flag is set or not.
00507   * @param  __HANDLE__: CAN Handle
00508   * @param  __FLAG__: specifies the flag to check.
00509   *         This parameter can be one of the following values:
00510   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00511   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00512   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00513   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00514   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00515   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00516   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00517   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00518   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00519   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00520   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00521   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00522   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00523   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00524   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00525   *            @arg CAN_FLAG_WKU: Wake up Flag
00526   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00527   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00528   *            @arg CAN_FLAG_EWG: Error Warning Flag
00529   *            @arg CAN_FLAG_EPV: Error Passive Flag
00530   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00531   * @retval The new state of __FLAG__ (TRUE or FALSE).
00532   */
00533 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
00534 ((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00535  (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00536  (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00537  (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00538  ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
00539
00540 /** @brief  Clear the specified CAN pending flag.
00541   * @param  __HANDLE__: CAN Handle.
00542   * @param  __FLAG__: specifies the flag to check.
00543   *         This parameter can be one of the following values:
00544   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00545   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00546   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00547   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00548   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00549   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00550   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00551   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00552   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00553   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00554   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00555   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00556   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00557   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00558   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00559   *            @arg CAN_FLAG_WKU: Wake up Flag
00560   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00561   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00562   *            @arg CAN_FLAG_EWG: Error Warning Flag
00563   *            @arg CAN_FLAG_EPV: Error Passive Flag
00564   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00565   * @retval The new state of __FLAG__ (TRUE or FALSE).
00566   */
00567 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00568 ((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00569  (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00570  (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00571  (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
00572  (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
00573
00574 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
00575   * @param  __HANDLE__: CAN Handle
00576   * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
00577   *          This parameter can be one of the following values:
00578   *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00579   *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
00580   *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
00581   * @retval The new state of __IT__ (TRUE or FALSE).
00582   */
00583 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00584
00585 /**
00586   * @brief  Check the transmission status of a CAN Frame.
00587   * @param  __HANDLE__: CAN Handle
00588   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00589   * @retval The new status of transmission  (TRUE or FALSE).
00590   */
00591 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
00592 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
00593  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
00594  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
00595
00596 /**
00597   * @brief  Release the specified receive FIFO.
00598   * @param  __HANDLE__: CAN handle
00599   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00600   * @retval None
00601   */
00602 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00603 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
00604
00605 /**
00606   * @brief  Cancel a transmit request.
00607   * @param  __HANDLE__: CAN Handle
00608   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00609   * @retval None
00610   */
00611 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
00612 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
00613  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
00614  ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
00615
00616 /**
00617   * @brief  Enable or disable the DBG Freeze for CAN.
00618   * @param  __HANDLE__: CAN Handle
00619   * @param  __NEWSTATE__: new state of the CAN peripheral.
00620   *          This parameter can be: ENABLE (CAN reception/transmission is frozen
00621   *          during debug. Reception FIFOs can still be accessed/controlled normally)
00622   *          or DISABLE (CAN is working during debug).
00623   * @retval None
00624   */
00625 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
00626 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
00627
00628 /**
00629   * @}
00630   */
00631
00632 /* Exported functions --------------------------------------------------------*/
00633 /** @addtogroup CAN_Exported_Functions
00634   * @{
00635   */
00636
00637 /** @addtogroup CAN_Exported_Functions_Group1
00638   * @{
00639   */
00640 /* Initialization/de-initialization functions ***********************************/
00641 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
00642 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
00643 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
00644 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
00645 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
00646 /**
00647   * @}
00648   */
00649
00650 /** @addtogroup CAN_Exported_Functions_Group2
00651   * @{
00652   */
00653 /* I/O operation functions ******************************************************/
00654 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
00655 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
00656 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
00657 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
00658 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
00659 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
00660 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
00661 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
00662 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
00663 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
00664 /**
00665   * @}
00666   */
00667
00668 /** @addtogroup CAN_Exported_Functions_Group3
00669   * @{
00670   */
00671 /* Peripheral State functions ***************************************************/
00672 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
00673 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /* Private types -------------------------------------------------------------*/
00683 /** @defgroup CAN_Private_Types CAN Private Types
00684   * @{
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /* Private variables ---------------------------------------------------------*/
00692 /** @defgroup CAN_Private_Variables CAN Private Variables
00693   * @{
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /* Private constants ---------------------------------------------------------*/
00701 /** @defgroup CAN_Private_Constants CAN Private Constants
00702   * @{
00703   */
00704 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
00705 #define CAN_FLAG_MASK  ((uint32_t)0x000000FF)
00706 /**
00707   * @}
00708   */
00709
00710 /* Private macros ------------------------------------------------------------*/
00711 /** @defgroup CAN_Private_Macros CAN Private Macros
00712   * @{
00713   */
00714 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
00715                            ((MODE) == CAN_MODE_LOOPBACK)|| \
00716                            ((MODE) == CAN_MODE_SILENT) || \
00717                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
00718 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
00719                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
00720 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
00721 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
00722 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
00723 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
00724 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
00725                                   ((MODE) == CAN_FILTERMODE_IDLIST))
00726 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
00727                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
00728 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
00729                                   ((FIFO) == CAN_FILTER_FIFO1))
00730 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
00731
00732 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
00733 #define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
00734 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
00735 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
00736
00737 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
00738                                 ((IDTYPE) == CAN_ID_EXT))
00739 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
00740 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
00741
00742 /**
00743   * @}
00744   */
00745
00746 /* Private functions ---------------------------------------------------------*/
00747 /** @defgroup CAN_Private_Functions CAN Private Functions
00748   * @{
00749   */
00750
00751 /**
00752   * @}
00753   */
00754 /**
00755   * @}
00756   */
00757
00758 /**
00759   * @}
00760   */
00761
00762 #ifdef __cplusplus
00763 }
00764 #endif
00765
00766 #endif /* __STM32F7xx_CAN_H */
00767
00768
00769 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cec.c Source File

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stm32f7xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   CEC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the High Definition Multimedia Interface
00010   *          Consumer Electronics Control Peripheral (CEC).
00011   *           + Initialization and de-initialization function
00012   *           + IO operation function
00013   *           + Peripheral Control function
00014   *
00015   *
00016   @verbatim
00017  ===============================================================================
00018                         ##### How to use this driver #####
00019  ===============================================================================
00020     [..]
00021     The CEC HAL driver can be used as follow:
00022
00023     (#) Declare a CEC_HandleTypeDef handle structure.
00024     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00025         (##) Enable the CEC interface clock.
00026         (##) CEC pins configuration:
00027             (+++) Enable the clock for the CEC GPIOs.
00028             (+++) Configure these CEC pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00030              and HAL_CEC_Receive_IT() APIs):
00031             (+++) Configure the CEC interrupt priority.
00032             (+++) Enable the NVIC CEC IRQ handle.
00033             (+++) The specific CEC interrupts (Transmission complete interrupt,
00034                   RXNE interrupt and Error Interrupts) will be managed using the macros
00035                   __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00036                   and receive process.
00037
00038     (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
00039         in case of Bit Rising Error, Error-Bit generation conditions, device logical
00040         address and Listen mode in the hcec Init structure.
00041
00042     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00043
00044   [..]
00045     (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00046         by calling the customed HAL_CEC_MspInit() API.
00047
00048   @endverbatim
00049   ******************************************************************************
00050   * @attention
00051   *
00052   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00053   *
00054   * Redistribution and use in source and binary forms, with or without modification,
00055   * are permitted provided that the following conditions are met:
00056   *   1. Redistributions of source code must retain the above copyright notice,
00057   *      this list of conditions and the following disclaimer.
00058   *   2. Redistributions in binary form must reproduce the above copyright notice,
00059   *      this list of conditions and the following disclaimer in the documentation
00060   *      and/or other materials provided with the distribution.
00061   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00062   *      may be used to endorse or promote products derived from this software
00063   *      without specific prior written permission.
00064   *
00065   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00066   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00067   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00068   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00069   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00070   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00071   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00072   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00073   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00074   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32f7xx_hal.h"
00081
00082 /** @addtogroup STM32F7xx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup CEC CEC
00087   * @brief HAL CEC module driver
00088   * @{
00089   */
00090 #ifdef HAL_CEC_MODULE_ENABLED
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /** @defgroup CEC_Private_Constants CEC Private Constants
00095   * @{
00096   */
00097 #define CEC_CFGR_FIELDS     (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
00098                            | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
00099                            | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
00100 /**
00101   * @}
00102   */
00103
00104 /* Private macro -------------------------------------------------------------*/
00105 /* Private variables ---------------------------------------------------------*/
00106 /* Private function prototypes -----------------------------------------------*/
00107 /** @defgroup CEC_Private_Functions CEC Private Functions
00108   * @{
00109   */
00110 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
00111 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
00112 /**
00113   * @}
00114   */
00115
00116 /* Exported functions ---------------------------------------------------------*/
00117
00118 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00119   * @{
00120   */
00121
00122 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00123   *  @brief    Initialization and Configuration functions
00124   *
00125 @verbatim
00126 ===============================================================================
00127             ##### Initialization and Configuration functions #####
00128  ===============================================================================
00129     [..]
00130     This subsection provides a set of functions allowing to initialize the CEC
00131       (+) The following parameters need to be configured:
00132         (++) SignalFreeTime
00133         (++) Tolerance
00134         (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
00135         (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
00136         (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
00137         (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
00138         (++) SignalFreeTimeOption      (SFT Timer start definition)
00139         (++) OwnAddress                (CEC device address)
00140         (++) ListenMode
00141
00142 @endverbatim
00143   * @{
00144   */
00145
00146 /**
00147   * @brief Initializes the CEC mode according to the specified
00148   *         parameters in the CEC_InitTypeDef and creates the associated handle .
00149   * @param hcec: CEC handle
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00153 {
00154   uint32_t tmpreg = 0x0;
00155
00156   /* Check the CEC handle allocation */
00157   if(hcec == NULL)
00158   {
00159     return HAL_ERROR;
00160   }
00161
00162   /* Check the parameters */
00163   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00164   assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
00165   assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
00166   assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
00167   assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
00168   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
00169   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
00170   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
00171   assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
00172   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
00173   assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
00174
00175
00176   if(hcec->State == HAL_CEC_STATE_RESET)
00177   {
00178     /* Allocate lock resource and initialize it */
00179     hcec->Lock = HAL_UNLOCKED;
00180     /* Init the low level hardware : GPIO, CLOCK */
00181     HAL_CEC_MspInit(hcec);
00182   }
00183
00184   hcec->State = HAL_CEC_STATE_BUSY;
00185
00186   /* Disable the Peripheral */
00187   __HAL_CEC_DISABLE(hcec);
00188
00189   tmpreg = hcec->Init.SignalFreeTime;
00190   tmpreg |= hcec->Init.Tolerance;
00191   tmpreg |= hcec->Init.BRERxStop;
00192   tmpreg |= hcec->Init.BREErrorBitGen;
00193   tmpreg |= hcec->Init.LBPEErrorBitGen;
00194   tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
00195   tmpreg |= hcec->Init.SignalFreeTimeOption;
00196   tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
00197   tmpreg |= hcec->Init.ListenMode;
00198
00199   /* Write to CEC Control Register */
00200   MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
00201
00202   /* Enable the Peripheral */
00203   __HAL_CEC_ENABLE(hcec);
00204
00205   hcec->State = HAL_CEC_STATE_READY;
00206
00207   return HAL_OK;
00208 }
00209
00210 /**
00211   * @brief DeInitializes the CEC peripheral
00212   * @param hcec: CEC handle
00213   * @retval HAL status
00214   */
00215 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00216 {
00217   /* Check the CEC handle allocation */
00218   if(hcec == NULL)
00219   {
00220     return HAL_ERROR;
00221   }
00222
00223   /* Check the parameters */
00224   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00225
00226   hcec->State = HAL_CEC_STATE_BUSY;
00227
00228   /* DeInit the low level hardware */
00229   HAL_CEC_MspDeInit(hcec);
00230   /* Disable the Peripheral */
00231   __HAL_CEC_DISABLE(hcec);
00232
00233   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00234   hcec->State = HAL_CEC_STATE_RESET;
00235
00236   /* Process Unlock */
00237   __HAL_UNLOCK(hcec);
00238
00239   return HAL_OK;
00240 }
00241
00242 /**
00243   * @brief CEC MSP Init
00244   * @param hcec: CEC handle
00245   * @retval None
00246   */
00247  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00248 {
00249   /* Prevent unused argument(s) compilation warning */
00250   UNUSED(hcec);
00251   /* NOTE : This function should not be modified, when the callback is needed,
00252             the HAL_CEC_MspInit can be implemented in the user file
00253    */
00254 }
00255
00256 /**
00257   * @brief CEC MSP DeInit
00258   * @param hcec: CEC handle
00259   * @retval None
00260   */
00261  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00262 {
00263   /* Prevent unused argument(s) compilation warning */
00264   UNUSED(hcec);
00265   /* NOTE : This function should not be modified, when the callback is needed,
00266             the HAL_CEC_MspDeInit can be implemented in the user file
00267    */
00268 }
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00275   *  @brief CEC Transmit/Receive functions
00276   *
00277 @verbatim
00278  ===============================================================================
00279                       ##### IO operation functions #####
00280  ===============================================================================
00281     This subsection provides a set of functions allowing to manage the CEC data transfers.
00282
00283     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00284         logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
00285
00286     (#) There are two mode of transfer:
00287        (+) Blocking mode: The communication is performed in polling mode.
00288             The HAL status of all data processing is returned by the same function
00289             after finishing transfer.
00290        (+) No-Blocking mode: The communication is performed using Interrupts.
00291            These API's return the HAL status.
00292            The end of the data processing will be indicated through the
00293            dedicated CEC IRQ when using Interrupt mode.
00294            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00295            will be executed respectively at the end of the transmit or Receive process
00296            The HAL_CEC_ErrorCallback()user callback will be executed when a communication
00297            error is detected
00298
00299     (#) Blocking mode API's are :
00300         (+) HAL_CEC_Transmit()
00301         (+) HAL_CEC_Receive()
00302
00303     (#) Non-Blocking mode API's with Interrupt are :
00304         (+) HAL_CEC_Transmit_IT()
00305         (+) HAL_CEC_Receive_IT()
00306         (+) HAL_CEC_IRQHandler()
00307
00308     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00309         (+) HAL_CEC_TxCpltCallback()
00310         (+) HAL_CEC_RxCpltCallback()
00311         (+) HAL_CEC_ErrorCallback()
00312
00313 @endverbatim
00314   * @{
00315   */
00316
00317 /**
00318   * @brief Send data in blocking mode
00319   * @param hcec: CEC handle
00320   * @param DestinationAddress: destination logical address
00321   * @param pData: pointer to input byte data buffer
00322   * @param Size: amount of data to be sent in bytes (without counting the header).
00323   *              0 means only the header is sent (ping operation).
00324   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00325   * @param  Timeout: Timeout duration.
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
00329 {
00330   uint8_t  temp = 0;
00331   uint32_t tempisr = 0;
00332   uint32_t tickstart = 0;
00333
00334   if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
00335   {
00336     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00337     if((pData == NULL ) && (Size > 0))
00338     {
00339       hcec->State = HAL_CEC_STATE_ERROR;
00340       return  HAL_ERROR;
00341     }
00342
00343     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00344     assert_param(IS_CEC_MSGSIZE(Size));
00345
00346     /* Process Locked */
00347     __HAL_LOCK(hcec);
00348
00349     hcec->State = HAL_CEC_STATE_BUSY_TX;
00350
00351     hcec->TxXferCount = Size;
00352
00353     /* case no data to be sent, sender is only pinging the system */
00354     if (Size == 0)
00355     {
00356       /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00357       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00358     }
00359
00360     /* send header block */
00361     temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
00362     hcec->Instance->TXDR = temp;
00363     /* Set TX Start of Message  (TXSOM) bit */
00364     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00365
00366     while (hcec->TxXferCount > 0)
00367     {
00368       hcec->TxXferCount--;
00369
00370       tickstart = HAL_GetTick();
00371       while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
00372       {
00373         if(Timeout != HAL_MAX_DELAY)
00374         {
00375           if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00376           {
00377             hcec->State = HAL_CEC_STATE_TIMEOUT;
00378             /* Process Unlocked */
00379             __HAL_UNLOCK(hcec);
00380             return HAL_TIMEOUT;
00381           }
00382         }
00383
00384         /* check whether error occurred while waiting for TXBR to be set:
00385          * has Tx underrun occurred ?
00386          * has Tx error occurred ?
00387          * has Tx Missing Acknowledge error occurred ?
00388          * has Arbitration Loss error occurred ? */
00389         tempisr = hcec->Instance->ISR;
00390         if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
00391         {
00392           /* copy ISR for error handling purposes */
00393           hcec->ErrorCode = tempisr;
00394          /* clear all error flags by default */
00395          __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
00396          hcec->State = HAL_CEC_STATE_ERROR;
00397          __HAL_UNLOCK(hcec);
00398          return  HAL_ERROR;
00399         }
00400       }
00401       /* TXBR to clear BEFORE writing TXDR register */
00402       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
00403       if (hcec->TxXferCount == 0)
00404       {
00405         /* if last byte transmission, set TX End of Message (TXEOM) bit */
00406         __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00407       }
00408       hcec->Instance->TXDR = *pData++;
00409
00410       /* error check after TX byte write up */
00411       tempisr = hcec->Instance->ISR;
00412       if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
00413       {
00414         /* copy ISR for error handling purposes */
00415         hcec->ErrorCode = tempisr;
00416         /* clear all error flags by default */
00417         __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
00418         hcec->State = HAL_CEC_STATE_ERROR;
00419         __HAL_UNLOCK(hcec);
00420         return  HAL_ERROR;
00421       }
00422     } /* end while (while (hcec->TxXferCount > 0)) */
00423
00424
00425     /* if no error up to this point, check that transmission is
00426      * complete, that is wait until TXEOM is reset */
00427     tickstart = HAL_GetTick();
00428
00429     while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
00430     {
00431         if(Timeout != HAL_MAX_DELAY)
00432       {
00433         if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00434         {
00435           hcec->State = HAL_CEC_STATE_ERROR;
00436           __HAL_UNLOCK(hcec);
00437           return HAL_TIMEOUT;
00438         }
00439       }
00440     }
00441
00442     /* Final error check once all bytes have been transmitted */
00443     tempisr = hcec->Instance->ISR;
00444     if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
00445     {
00446       /* copy ISR for error handling purposes */
00447       hcec->ErrorCode = tempisr;
00448       /* clear all error flags by default */
00449       __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
00450       hcec->State = HAL_CEC_STATE_ERROR;
00451       __HAL_UNLOCK(hcec);
00452       return  HAL_ERROR;
00453     }
00454
00455     hcec->State = HAL_CEC_STATE_READY;
00456     __HAL_UNLOCK(hcec);
00457
00458     return HAL_OK;
00459   }
00460   else
00461   {
00462     return HAL_BUSY;
00463   }
00464 }
00465
00466 /**
00467   * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
00468   * @param hcec: CEC handle
00469   * @param pData: pointer to received data buffer.
00470   * @param Timeout: Timeout duration.
00471   *       Note that the received data size is not known beforehand, the latter is known
00472   *       when the reception is complete and is stored in hcec->RxXferSize.
00473   *       hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
00474   *       If only a header is received, hcec->RxXferSize = 0
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
00478 {
00479   uint32_t temp;
00480   uint32_t tickstart = 0;
00481
00482   if (hcec->State == HAL_CEC_STATE_READY)
00483   {
00484     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00485     if (pData == NULL )
00486     {
00487       hcec->State = HAL_CEC_STATE_ERROR;
00488       return  HAL_ERROR;
00489     }
00490
00491     hcec->RxXferSize = 0;
00492     /* Process Locked */
00493     __HAL_LOCK(hcec);
00494
00495
00496     /* Rx loop until CEC_ISR_RXEND  is set */
00497     while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
00498     {
00499       tickstart = HAL_GetTick();
00500       /* Wait for next byte to be received */
00501       while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
00502       {
00503           if(Timeout != HAL_MAX_DELAY)
00504         {
00505           if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00506           {
00507             hcec->State = HAL_CEC_STATE_TIMEOUT;
00508             __HAL_UNLOCK(hcec);
00509             return HAL_TIMEOUT;
00510           }
00511         }
00512         /* any error so far ?
00513          * has Rx Missing Acknowledge occurred ?
00514          * has Rx Long Bit Period error occurred ?
00515          * has Rx Short Bit Period error occurred ?
00516          * has Rx Bit Rising error occurred ?
00517          * has Rx Overrun error occurred ? */
00518         temp = (uint32_t) (hcec->Instance->ISR);
00519         if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
00520         {
00521           /* copy ISR for error handling purposes */
00522           hcec->ErrorCode = temp;
00523           /* clear all error flags by default */
00524           __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
00525           hcec->State = HAL_CEC_STATE_ERROR;
00526           __HAL_UNLOCK(hcec);
00527           return  HAL_ERROR;
00528         }
00529       } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
00530
00531
00532       /* read received data */
00533       *pData++ = hcec->Instance->RXDR;
00534       temp = (uint32_t) (hcec->Instance->ISR);
00535       /* end of message ? */
00536       if ((temp &  CEC_ISR_RXEND) != 0)
00537       {
00538          assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
00539          __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
00540           hcec->State = HAL_CEC_STATE_READY;
00541          __HAL_UNLOCK(hcec);
00542          return HAL_OK;
00543       }
00544
00545       /* clear Rx-Byte Received flag */
00546       __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
00547       /* increment payload byte counter */
00548        hcec->RxXferSize++;
00549     } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
00550
00551     /* if the instructions below are executed, it means RXEND was set when RXBR was
00552      * set for the first time:
00553      * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
00554      * loop has not been executed and this means a single byte has been sent */
00555     *pData++ = hcec->Instance->RXDR;
00556      /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
00557      hcec->RxXferSize = 0;
00558      __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
00559
00560     hcec->State = HAL_CEC_STATE_READY;
00561     __HAL_UNLOCK(hcec);
00562     return HAL_OK;
00563   }
00564   else
00565   {
00566     return HAL_BUSY;
00567   }
00568 }
00569
00570 /**
00571   * @brief Send data in interrupt mode
00572   * @param hcec: CEC handle
00573   * @param DestinationAddress: destination logical address
00574   * @param pData: pointer to input byte data buffer
00575   * @param Size: amount of data to be sent in bytes (without counting the header).
00576   *              0 means only the header is sent (ping operation).
00577   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00578   * @retval HAL status
00579   */
00580 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
00581 {
00582   uint8_t  temp = 0;
00583   /* if the IP isn't already busy and if there is no previous transmission
00584      already pending due to arbitration lost */
00585   if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
00586   &&   (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
00587   {
00588     if((pData == NULL ) && (Size > 0))
00589     {
00590       hcec->State = HAL_CEC_STATE_ERROR;
00591       return  HAL_ERROR;
00592     }
00593
00594     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00595     assert_param(IS_CEC_MSGSIZE(Size));
00596
00597     /* Process Locked */
00598     __HAL_LOCK(hcec);
00599     hcec->pTxBuffPtr = pData;
00600     hcec->State = HAL_CEC_STATE_BUSY_TX;
00601     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00602
00603     /* Disable Peripheral to write CEC_IER register */
00604     __HAL_CEC_DISABLE(hcec);
00605
00606     /* Enable the following two CEC Transmission interrupts as
00607      * well as the following CEC Transmission Errors interrupts:
00608      * Tx Byte Request IT
00609      * End of Transmission IT
00610      * Tx Missing Acknowledge IT
00611      * Tx-Error IT
00612      * Tx-Buffer Underrun IT
00613      * Tx arbitration lost     */
00614     __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
00615
00616     /* Enable the Peripheral */
00617     __HAL_CEC_ENABLE(hcec);
00618
00619     /* initialize the number of bytes to send,
00620      * 0 means only one header is sent (ping operation) */
00621     hcec->TxXferCount = Size;
00622
00623     /* Process Unlocked */
00624     __HAL_UNLOCK(hcec);
00625
00626     /* in case of no payload (Size = 0), sender is only pinging the system;
00627      * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00628     if (Size == 0)
00629     {
00630       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00631     }
00632
00633     /* send header block */
00634     temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
00635     hcec->Instance->TXDR = temp;
00636     /* Set TX Start of Message  (TXSOM) bit */
00637     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00638
00639     return HAL_OK;
00640   }
00641     /* if the IP is already busy or if there is a previous transmission
00642      already pending due to arbitration loss */
00643   else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
00644         || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
00645   {
00646     __HAL_LOCK(hcec);
00647     /* set state to BUSY TX, in case it wasn't set already (case
00648      * of transmission new attempt after arbitration loss) */
00649     if (hcec->State != HAL_CEC_STATE_BUSY_TX)
00650     {
00651       hcec->State = HAL_CEC_STATE_BUSY_TX;
00652     }
00653
00654     /* if all data have been sent */
00655     if(hcec->TxXferCount == 0)
00656     {
00657       /* Disable Peripheral to write CEC_IER register */
00658       __HAL_CEC_DISABLE(hcec);
00659
00660       /* Disable the CEC Transmission Interrupts */
00661       __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
00662       /* Disable the CEC Transmission Error Interrupts */
00663       __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
00664
00665       /* Enable the Peripheral */
00666       __HAL_CEC_ENABLE(hcec);
00667
00668       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
00669
00670       hcec->State = HAL_CEC_STATE_READY;
00671       /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
00672       start again the Transmission under the Tx call back API */
00673       __HAL_UNLOCK(hcec);
00674
00675       HAL_CEC_TxCpltCallback(hcec);
00676
00677       return HAL_OK;
00678     }
00679     else
00680     {
00681       if (hcec->TxXferCount == 1)
00682       {
00683         /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
00684         __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00685       }
00686       /* clear Tx-Byte request flag */
00687        __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
00688        hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
00689       hcec->TxXferCount--;
00690
00691       /* Process Unlocked */
00692       __HAL_UNLOCK(hcec);
00693
00694       return HAL_OK;
00695     }
00696   }
00697   else
00698   {
00699     return HAL_BUSY;
00700   }
00701 }
00702
00703 /**
00704   * @brief Receive data in interrupt mode.
00705   * @param hcec: CEC handle
00706   * @param pData: pointer to received data buffer.
00707   * Note that the received data size is not known beforehand, the latter is known
00708   * when the reception is complete and is stored in hcec->RxXferSize.
00709   * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
00710   * If only a header is received, hcec->RxXferSize = 0
00711   * @retval HAL status
00712   */
00713 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
00714 {
00715   if(hcec->State == HAL_CEC_STATE_READY)
00716   {
00717     if(pData == NULL )
00718     {
00719       hcec->State = HAL_CEC_STATE_ERROR;
00720       return HAL_ERROR;
00721     }
00722
00723     /* Process Locked */
00724     __HAL_LOCK(hcec);
00725     hcec->RxXferSize = 0;
00726     hcec->pRxBuffPtr = pData;
00727     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00728     /* the IP is moving to a ready to receive state */
00729     hcec->State = HAL_CEC_STATE_STANDBY_RX;
00730
00731     /* Disable Peripheral to write CEC_IER register */
00732     __HAL_CEC_DISABLE(hcec);
00733
00734     /* Enable the following CEC Reception Error Interrupts:
00735      * Rx overrun
00736      * Rx bit rising error
00737      * Rx short bit period error
00738      * Rx long bit period error
00739      * Rx missing acknowledge  */
00740     __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
00741
00742     /* Process Unlocked */
00743     __HAL_UNLOCK(hcec);
00744
00745     /* Enable the following two CEC Reception interrupts:
00746      * Rx Byte Received IT
00747      * End of Reception IT */
00748     __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
00749
00750     __HAL_CEC_ENABLE(hcec);
00751
00752     return HAL_OK;
00753   }
00754   else
00755   {
00756     return HAL_BUSY;
00757   }
00758 }
00759
00760 /**
00761   * @brief Get size of the received frame.
00762   * @param hcec: CEC handle
00763   * @retval Frame size
00764   */
00765 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
00766 {
00767   return hcec->RxXferSize;
00768 }
00769
00770 /**
00771   * @brief This function handles CEC interrupt requests.
00772   * @param hcec: CEC handle
00773   * @retval None
00774   */
00775 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00776 {
00777   /* save interrupts register for further error or interrupts handling purposes */
00778   hcec->ErrorCode = hcec->Instance->ISR;
00779   /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
00780   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
00781   {
00782     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
00783     hcec->State = HAL_CEC_STATE_ERROR;
00784   }
00785
00786   /* CEC transmit error interrupt occurred --------------------------------------*/
00787   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
00788   {
00789     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
00790     hcec->State = HAL_CEC_STATE_ERROR;
00791   }
00792
00793   /* CEC TX underrun error interrupt occurred --------------------------------------*/
00794   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
00795   {
00796     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
00797     hcec->State = HAL_CEC_STATE_ERROR;
00798   }
00799
00800   /* CEC TX arbitration error interrupt occurred --------------------------------------*/
00801   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
00802   {
00803     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
00804     hcec->State = HAL_CEC_STATE_ERROR;
00805   }
00806
00807   /* CEC RX overrun error interrupt occurred --------------------------------------*/
00808   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
00809   {
00810     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
00811     hcec->State = HAL_CEC_STATE_ERROR;
00812   }
00813
00814   /* CEC RX bit rising error interrupt occurred --------------------------------------*/
00815   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
00816   {
00817     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
00818     hcec->State = HAL_CEC_STATE_ERROR;
00819   }
00820
00821   /* CEC RX short bit period error interrupt occurred --------------------------------------*/
00822   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
00823   {
00824     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
00825     hcec->State = HAL_CEC_STATE_ERROR;
00826   }
00827
00828   /* CEC RX long bit period error interrupt occurred --------------------------------------*/
00829   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
00830   {
00831     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
00832     hcec->State = HAL_CEC_STATE_ERROR;
00833   }
00834
00835   /* CEC RX missing acknowledge error interrupt occurred --------------------------------------*/
00836   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
00837   {
00838     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
00839     hcec->State = HAL_CEC_STATE_ERROR;
00840   }
00841
00842   if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
00843   {
00844     HAL_CEC_ErrorCallback(hcec);
00845   }
00846
00847   /* CEC RX byte received interrupt  ---------------------------------------------------*/
00848   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
00849   {
00850     /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
00851     CEC_Receive_IT(hcec);
00852   }
00853
00854   /* CEC RX end received interrupt  ---------------------------------------------------*/
00855   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
00856   {
00857     /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
00858     CEC_Receive_IT(hcec);
00859   }
00860
00861
00862   /* CEC TX byte request interrupt ------------------------------------------------*/
00863   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
00864   {
00865     /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
00866     CEC_Transmit_IT(hcec);
00867   }
00868
00869   /* CEC TX end interrupt ------------------------------------------------*/
00870   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
00871   {
00872    /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
00873     CEC_Transmit_IT(hcec);
00874   }
00875 }
00876
00877 /**
00878   * @brief Tx Transfer completed callback
00879   * @param hcec: CEC handle
00880   * @retval None
00881   */
00882  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00883 {
00884   /* Prevent unused argument(s) compilation warning */
00885   UNUSED(hcec);
00886   /* NOTE : This function should not be modified, when the callback is needed,
00887             the HAL_CEC_TxCpltCallback can be implemented in the user file
00888    */
00889 }
00890
00891 /**
00892   * @brief Rx Transfer completed callback
00893   * @param hcec: CEC handle
00894   * @retval None
00895   */
00896 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
00897 {
00898   /* Prevent unused argument(s) compilation warning */
00899   UNUSED(hcec);
00900   /* NOTE : This function should not be modified, when the callback is needed,
00901             the HAL_CEC_TxCpltCallback can be implemented in the user file
00902    */
00903 }
00904
00905 /**
00906   * @brief CEC error callbacks
00907   * @param hcec: CEC handle
00908   * @retval None
00909   */
00910  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00911 {
00912   /* Prevent unused argument(s) compilation warning */
00913   UNUSED(hcec);
00914   /* NOTE : This function should not be modified, when the callback is needed,
00915             the HAL_CEC_ErrorCallback can be implemented in the user file
00916    */
00917 }
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
00923   *  @brief   CEC control functions
00924   *
00925 @verbatim
00926  ===============================================================================
00927                       ##### Peripheral Control function #####
00928  ===============================================================================
00929     [..]
00930     This subsection provides a set of functions allowing to control the CEC.
00931      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00932 @endverbatim
00933   * @{
00934   */
00935 /**
00936   * @brief return the CEC state
00937   * @param hcec: CEC handle
00938   * @retval HAL state
00939   */
00940 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
00941 {
00942   return hcec->State;
00943 }
00944
00945 /**
00946 * @brief  Return the CEC error code
00947 * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
00948   *              the configuration information for the specified CEC.
00949 * @retval CEC Error Code
00950 */
00951 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
00952 {
00953   return hcec->ErrorCode;
00954 }
00955
00956 /**
00957   * @}
00958   */
00959
00960 /**
00961   * @brief Send data in interrupt mode
00962   * @param hcec: CEC handle.
00963   *         Function called under interruption only, once
00964   *         interruptions have been enabled by HAL_CEC_Transmit_IT()
00965   * @retval HAL status
00966   */
00967 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
00968 {
00969   /* if the IP is already busy or if there is a previous transmission
00970      already pending due to arbitration loss */
00971   if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
00972         || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
00973   {
00974     __HAL_LOCK(hcec);
00975     /* set state to BUSY TX, in case it wasn't set already (case
00976      * of transmission new attempt after arbitration loss) */
00977     if (hcec->State != HAL_CEC_STATE_BUSY_TX)
00978     {
00979       hcec->State = HAL_CEC_STATE_BUSY_TX;
00980     }
00981
00982     /* if all data have been sent */
00983     if(hcec->TxXferCount == 0)
00984     {
00985       /* Disable Peripheral to write CEC_IER register */
00986       __HAL_CEC_DISABLE(hcec);
00987
00988       /* Disable the CEC Transmission Interrupts */
00989       __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
00990       /* Disable the CEC Transmission Error Interrupts */
00991       __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
00992
00993       /* Enable the Peripheral */
00994       __HAL_CEC_ENABLE(hcec);
00995
00996       __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
00997
00998       hcec->State = HAL_CEC_STATE_READY;
00999       /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
01000       start again the Transmission under the Tx call back API */
01001       __HAL_UNLOCK(hcec);
01002
01003       HAL_CEC_TxCpltCallback(hcec);
01004
01005       return HAL_OK;
01006     }
01007     else
01008     {
01009       if (hcec->TxXferCount == 1)
01010       {
01011         /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
01012         __HAL_CEC_LAST_BYTE_TX_SET(hcec);
01013       }
01014       /* clear Tx-Byte request flag */
01015        __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
01016        hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
01017       hcec->TxXferCount--;
01018
01019       /* Process Unlocked */
01020       __HAL_UNLOCK(hcec);
01021
01022       return HAL_OK;
01023     }
01024   }
01025   else
01026   {
01027     return HAL_BUSY;
01028   }
01029 }
01030
01031
01032 /**
01033   * @brief Receive data in interrupt mode.
01034   * @param hcec: CEC handle.
01035   *         Function called under interruption only, once
01036   *         interruptions have been enabled by HAL_CEC_Receive_IT()
01037   * @retval HAL status
01038   */
01039 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
01040 {
01041   uint32_t tempisr;
01042
01043   /* Three different conditions are tested to carry out the RX IT processing:
01044    * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
01045    *   the reception of the first byte is starting
01046    * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
01047    *   and a new byte is being received
01048    * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
01049    *   but has been interrupted by a new message reception or discarded due to
01050    *   arbitration loss: the reception of the first or higher priority message
01051    *   (the arbitration winner) is starting */
01052   if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
01053   ||  (hcec->State == HAL_CEC_STATE_BUSY_RX)
01054   ||  (hcec->State == HAL_CEC_STATE_BUSY_TX))
01055   {
01056     /* reception is starting */
01057     hcec->State = HAL_CEC_STATE_BUSY_RX;
01058     tempisr =  (uint32_t) (hcec->Instance->ISR);
01059     if ((tempisr & CEC_FLAG_RXBR) != 0)
01060     {
01061       /* Process Locked */
01062       __HAL_LOCK(hcec);
01063       /* read received byte */
01064       *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
01065       /* if last byte has been received */
01066       if ((tempisr & CEC_FLAG_RXEND) != 0)
01067       {
01068         /* clear IT */
01069         __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR|CEC_FLAG_RXEND);
01070         /* RX interrupts are not disabled at this point.
01071          * Indeed, to disable the IT, the IP must be disabled first
01072          * which resets the TXSOM flag. In case of arbitration loss,
01073          * this leads to a transmission abort.
01074          * Therefore, RX interruptions disabling if so required,
01075          * is done in HAL_CEC_RxCpltCallback */
01076
01077         /* IP state is moved to READY.
01078          * If the IP must remain in standby mode to listen
01079          * any new message, it is up to HAL_CEC_RxCpltCallback
01080          * to move it again to HAL_CEC_STATE_STANDBY_RX */
01081         hcec->State = HAL_CEC_STATE_READY;
01082
01083         /* Call the Process Unlocked before calling the Rx call back API */
01084         __HAL_UNLOCK(hcec);
01085         HAL_CEC_RxCpltCallback(hcec);
01086
01087         return HAL_OK;
01088       }
01089       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
01090
01091       hcec->RxXferSize++;
01092       /* Process Unlocked */
01093       __HAL_UNLOCK(hcec);
01094
01095       return HAL_OK;
01096     }
01097     else
01098     {
01099       return HAL_BUSY;
01100     }
01101   }
01102   else
01103   {
01104     return HAL_BUSY;
01105   }
01106 }
01107 /**
01108   * @}
01109   */
01110 #endif /* HAL_CEC_MODULE_ENABLED */
01111 /**
01112   * @}
01113   */
01114
01115 /**
01116   * @}
01117   */
01118
01119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cec.h Source File

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stm32f7xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CEC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CEC_H
00040 #define __STM32F7xx_HAL_CEC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CEC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup CEC_Exported_Types CEC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief CEC Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
00068                                               It can be one of @ref CEC_Signal_Free_Time
00069                                               and belongs to the set {0,...,7} where
00070                                               0x0 is the default configuration
00071                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
00072
00073   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
00074                                               it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
00075                                               or CEC_EXTENDED_TOLERANCE */
00076
00077   uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
00078                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
00079                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
00080
00081   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
00082                                               CEC line upon Bit Rising Error detection.
00083                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
00084                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
00085
00086   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
00087                                               CEC line upon Long Bit Period Error detection.
00088                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
00089                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
00090
00091   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
00092                                               upon an error detected on a broadcast message.
00093
00094                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
00095
00096                                               1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
00097                                                  a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
00098                                                     and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
00099                                                  b) LBPE detection: error-bit generation on the CEC line
00100                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
00101
00102                                               2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
00103                                                  no error-bit generation in case neither a) nor b) are satisfied. Additionally,
00104                                                  there is no error-bit generation in case of Short Bit Period Error detection in
00105                                                  a broadcast message while LSTN bit is set. */
00106
00107   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
00108                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
00109                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
00110
00111   uint32_t OwnAddress;                   /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
00112
00113   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
00114
00115                                               CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
00116                                                 own address (OAR). Messages addressed to different destination are ignored.
00117                                                 Broadcast messages are always received.
00118
00119                                               CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
00120                                                 address (OAR) with positive acknowledge. Messages addressed to different destination
00121                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
00122
00123   uint8_t  InitiatorAddress;             /* Initiator address (source logical address, sent in each header) */
00124
00125 }CEC_InitTypeDef;
00126
00127 /**
00128   * @brief HAL CEC State structures definition
00129   */
00130 typedef enum
00131 {
00132   HAL_CEC_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                              */
00133   HAL_CEC_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use            */
00134   HAL_CEC_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                      */
00135   HAL_CEC_STATE_BUSY_TX           = 0x03,    /*!< Data Transmission process is ongoing                */
00136   HAL_CEC_STATE_BUSY_RX           = 0x04,    /*!< Data Reception process is ongoing                   */
00137   HAL_CEC_STATE_STANDBY_RX        = 0x05,    /*!< IP ready to receive, doesn't prevent IP to transmit */
00138   HAL_CEC_STATE_TIMEOUT           = 0x06,    /*!< Timeout state                                       */
00139   HAL_CEC_STATE_ERROR             = 0x07     /*!< State Error                                         */
00140 }HAL_CEC_StateTypeDef;
00141
00142 /**
00143   * @brief  CEC handle Structure definition
00144   */
00145 typedef struct
00146 {
00147   CEC_TypeDef             *Instance;      /* CEC registers base address */
00148
00149   CEC_InitTypeDef         Init;           /* CEC communication parameters */
00150
00151   uint8_t                 *pTxBuffPtr;    /* Pointer to CEC Tx transfer Buffer */
00152
00153   uint16_t                TxXferCount;    /* CEC Tx Transfer Counter */
00154
00155   uint8_t                 *pRxBuffPtr;    /* Pointer to CEC Rx transfer Buffer */
00156
00157   uint16_t                RxXferSize;     /* CEC Rx Transfer size, 0: header received only */
00158
00159   uint32_t                ErrorCode;      /* For errors handling purposes, copy of ISR register
00160                                             in case error is reported */
00161
00162   HAL_LockTypeDef         Lock;           /* Locking object */
00163
00164   HAL_CEC_StateTypeDef    State;          /* CEC communication state */
00165
00166 }CEC_HandleTypeDef;
00167 /**
00168   * @}
00169   */
00170
00171 /* Exported constants --------------------------------------------------------*/
00172 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00173   * @{
00174   */
00175
00176 /** @defgroup CEC_Error_Code CEC Error Code
00177   * @{
00178   */
00179 #define HAL_CEC_ERROR_NONE    (uint32_t) 0x0         /*!< no error                      */
00180 #define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */
00181 #define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */
00182 #define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */
00183 #define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */
00184 #define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */
00185 #define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */
00186 #define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */
00187 #define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */
00188 #define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter
00194   * @{
00195   */
00196 #define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000)
00197 #define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001)
00198 #define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002)
00199 #define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003)
00200 #define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004)
00201 #define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005)
00202 #define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006)
00203 #define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007)
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
00209   * @{
00210   */
00211 #define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000)
00212 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
00218   * @{
00219   */
00220 #define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000)
00221 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported
00227   * @{
00228   */
00229 #define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000)
00230 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported
00236   * @{
00237   */
00238 #define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000)
00239 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message
00245   * @{
00246   */
00247 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000)
00248 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup CEC_SFT_Option     CEC Signal Free Time start option
00254   * @{
00255   */
00256 #define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000)
00257 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup CEC_Listening_Mode    CEC Listening mode option
00263   * @{
00264   */
00265 #define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000)
00266 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register
00272   * @{
00273   */
00274 #define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16)
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00280   * @{
00281   */
00282 #define CEC_INITIATOR_LSB_POS           ((uint32_t) 4)
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
00288   * @{
00289   */
00290 #define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
00291 #define CEC_IT_TXERR                    CEC_IER_TXERRIE
00292 #define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
00293 #define CEC_IT_TXEND                    CEC_IER_TXENDIE
00294 #define CEC_IT_TXBR                     CEC_IER_TXBRIE
00295 #define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
00296 #define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
00297 #define CEC_IT_LBPE                     CEC_IER_LBPEIE
00298 #define CEC_IT_SBPE                     CEC_IER_SBPEIE
00299 #define CEC_IT_BRE                      CEC_IER_BREIE
00300 #define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
00301 #define CEC_IT_RXEND                    CEC_IER_RXENDIE
00302 #define CEC_IT_RXBR                     CEC_IER_RXBRIE
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup CEC_Flags_Definitions  CEC Flags definition
00308   * @{
00309   */
00310 #define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
00311 #define CEC_FLAG_TXERR                  CEC_ISR_TXERR
00312 #define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
00313 #define CEC_FLAG_TXEND                  CEC_ISR_TXEND
00314 #define CEC_FLAG_TXBR                   CEC_ISR_TXBR
00315 #define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
00316 #define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
00317 #define CEC_FLAG_LBPE                   CEC_ISR_LBPE
00318 #define CEC_FLAG_SBPE                   CEC_ISR_SBPE
00319 #define CEC_FLAG_BRE                    CEC_ISR_BRE
00320 #define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
00321 #define CEC_FLAG_RXEND                  CEC_ISR_RXEND
00322 #define CEC_FLAG_RXBR                   CEC_ISR_RXBR
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
00328   * @{
00329   */
00330 #define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
00331                                                   CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
00337   * @{
00338   */
00339 #define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
00345   * @{
00346   */
00347 #define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Exported macros -----------------------------------------------------------*/
00357 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00358   * @{
00359   */
00360
00361 /** @brief  Reset CEC handle state
00362   * @param  __HANDLE__: CEC handle.
00363   * @retval None
00364   */
00365 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
00366
00367 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00368   * @param  __HANDLE__: specifies the CEC Handle.
00369   * @param  __FLAG__: specifies the flag to check.
00370   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00371   *            @arg CEC_FLAG_TXERR: Tx Error.
00372   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00373   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00374   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00375   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00376   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00377   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00378   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00379   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00380   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00381   *            @arg CEC_FLAG_RXEND: End Of Reception.
00382   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00383   * @retval ITStatus
00384   */
00385 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))
00386
00387 /** @brief  Clears the interrupt or status flag when raised (write at 1)
00388   * @param  __HANDLE__: specifies the CEC Handle.
00389   * @param  __FLAG__: specifies the interrupt/status flag to clear.
00390   *        This parameter can be one of the following values:
00391   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00392   *            @arg CEC_FLAG_TXERR: Tx Error.
00393   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00394   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00395   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00396   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00397   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00398   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00399   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00400   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00401   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00402   *            @arg CEC_FLAG_RXEND: End Of Reception.
00403   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00404   * @retval none
00405   */
00406 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))
00407
00408 /** @brief  Enables the specified CEC interrupt.
00409   * @param  __HANDLE__: specifies the CEC Handle.
00410   * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
00411   *          This parameter can be one of the following values:
00412   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00413   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00414   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00415   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00416   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00417   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00418   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00419   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00420   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00421   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00422   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00423   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00424   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00425   * @retval none
00426   */
00427 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00428
00429 /** @brief  Disables the specified CEC interrupt.
00430   * @param  __HANDLE__: specifies the CEC Handle.
00431   * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
00432   *          This parameter can be one of the following values:
00433   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00434   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00435   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00436   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00437   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00438   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00439   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00440   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00441   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00442   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00443   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00444   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00445   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00446   * @retval none
00447   */
00448 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00449
00450 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00451   * @param  __HANDLE__: specifies the CEC Handle.
00452   * @param  __INTERRUPT__: specifies the CEC interrupt to check.
00453   *          This parameter can be one of the following values:
00454   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00455   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00456   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00457   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00458   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00459   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00460   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00461   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00462   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00463   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00464   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00465   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00466   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00467   * @retval FlagStatus
00468   */
00469 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00470
00471 /** @brief  Enables the CEC device
00472   * @param  __HANDLE__: specifies the CEC Handle.
00473   * @retval none
00474   */
00475 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
00476
00477 /** @brief  Disables the CEC device
00478   * @param  __HANDLE__: specifies the CEC Handle.
00479   * @retval none
00480   */
00481 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
00482
00483 /** @brief  Set Transmission Start flag
00484   * @param  __HANDLE__: specifies the CEC Handle.
00485   * @retval none
00486   */
00487 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
00488
00489 /** @brief  Set Transmission End flag
00490   * @param  __HANDLE__: specifies the CEC Handle.
00491   * @retval none
00492   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
00493   */
00494 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
00495
00496 /** @brief  Get Transmission Start flag
00497   * @param  __HANDLE__: specifies the CEC Handle.
00498   * @retval FlagStatus
00499   */
00500 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
00501
00502 /** @brief  Get Transmission End flag
00503   * @param  __HANDLE__: specifies the CEC Handle.
00504   * @retval FlagStatus
00505   */
00506 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
00507
00508 /** @brief  Clear OAR register
00509   * @param  __HANDLE__: specifies the CEC Handle.
00510   * @retval none
00511   */
00512 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
00513
00514 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
00515   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
00516   * @param  __HANDLE__: specifies the CEC Handle.
00517   * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
00518   * @retval none
00519   */
00520 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
00521
00522 /**
00523   * @}
00524   */
00525
00526 /* Exported functions --------------------------------------------------------*/
00527 /** @addtogroup CEC_Exported_Functions
00528   * @{
00529   */
00530
00531 /** @addtogroup CEC_Exported_Functions_Group1
00532   * @{
00533   */
00534 /* Initialization and de-initialization functions  ****************************/
00535 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00536 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00537 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00538 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00539 /**
00540   * @}
00541   */
00542
00543 /** @addtogroup CEC_Exported_Functions_Group2
00544   * @{
00545   */
00546 /* I/O operation functions  ***************************************************/
00547 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
00548 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
00549 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
00550 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
00551 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
00552 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00553 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00554 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
00555 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00556 /**
00557   * @}
00558   */
00559
00560 /** @addtogroup CEC_Exported_Functions_Group3
00561   * @{
00562   */
00563 /* Peripheral State functions  ************************************************/
00564 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
00565 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
00566 /**
00567   * @}
00568   */
00569
00570 /**
00571   * @}
00572   */
00573
00574 /* Private types -------------------------------------------------------------*/
00575 /** @defgroup CEC_Private_Types CEC Private Types
00576   * @{
00577   */
00578
00579 /**
00580   * @}
00581   */
00582
00583 /* Private variables ---------------------------------------------------------*/
00584 /** @defgroup CEC_Private_Variables CEC Private Variables
00585   * @{
00586   */
00587
00588 /**
00589   * @}
00590   */
00591
00592 /* Private constants ---------------------------------------------------------*/
00593 /** @defgroup CEC_Private_Constants CEC Private Constants
00594   * @{
00595   */
00596
00597 /**
00598   * @}
00599   */
00600
00601 /* Private macros ------------------------------------------------------------*/
00602 /** @defgroup CEC_Private_Macros CEC Private Macros
00603   * @{
00604   */
00605
00606 #define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)
00607
00608 #define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
00609                                             ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
00610
00611 #define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
00612                                            ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
00613
00614 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
00615                                                 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
00616
00617 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
00618                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
00619
00620 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
00621                                                                        ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
00622
00623 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
00624                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
00625
00626 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
00627                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
00628
00629 /** @brief Check CEC device Own Address Register (OAR) setting.
00630   *        OAR address is written in a 15-bit field within CEC_CFGR register.
00631   * @param  __ADDRESS__: CEC own address.
00632   * @retval Test result (TRUE or FALSE).
00633   */
00634 #define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
00635
00636 /** @brief Check CEC initiator or destination logical address setting.
00637   *        Initiator and destination addresses are coded over 4 bits.
00638   * @param  __ADDRESS__: CEC initiator or logical address.
00639   * @retval Test result (TRUE or FALSE).
00640   */
00641 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
00642
00643 /** @brief Check CEC message size.
00644   *       The message size is the payload size: without counting the header,
00645   *       it varies from 0 byte (ping operation, one header only, no payload) to
00646   *       15 bytes (1 opcode and up to 14 operands following the header).
00647   * @param  __SIZE__: CEC message size.
00648   * @retval Test result (TRUE or FALSE).
00649   */
00650 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
00651
00652 /**
00653   * @}
00654   */
00655
00656 /* Private functions ---------------------------------------------------------*/
00657 /** @defgroup CEC_Private_Functions CEC Private Functions
00658   * @{
00659   */
00660
00661 /**
00662   * @}
00663   */
00664
00665 /**
00666   * @}
00667   */
00668
00669 /**
00670   * @}
00671   */
00672
00673 #ifdef __cplusplus
00674 }
00675 #endif
00676
00677 #endif /* __STM32F7xx_HAL_CEC_H */
00678
00679 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_conf.h Source File

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stm32f7xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_conf_template.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   HAL configuration template file.
00008   *          This file should be copied to the application folder and renamed
00009   *          to stm32f7xx_hal_conf.h.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __STM32F7xx_HAL_CONF_H
00042 #define __STM32F7xx_HAL_CONF_H
00043
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047
00048 /* Exported types ------------------------------------------------------------*/
00049 /* Exported constants --------------------------------------------------------*/
00050
00051 /* ########################## Module Selection ############################## */
00052 /**
00053   * @brief This is the list of modules to be used in the HAL driver
00054   */
00055 #define HAL_MODULE_ENABLED
00056 #define HAL_ADC_MODULE_ENABLED
00057 #define HAL_CAN_MODULE_ENABLED
00058 #define HAL_CEC_MODULE_ENABLED
00059 #define HAL_CRC_MODULE_ENABLED
00060 #define HAL_CRYP_MODULE_ENABLED
00061 #define HAL_DAC_MODULE_ENABLED
00062 #define HAL_DCMI_MODULE_ENABLED
00063 #define HAL_DMA_MODULE_ENABLED
00064 #define HAL_DMA2D_MODULE_ENABLED
00065 #define HAL_ETH_MODULE_ENABLED
00066 #define HAL_FLASH_MODULE_ENABLED
00067 #define HAL_NAND_MODULE_ENABLED
00068 #define HAL_NOR_MODULE_ENABLED
00069 #define HAL_SRAM_MODULE_ENABLED
00070 #define HAL_SDRAM_MODULE_ENABLED
00071 #define HAL_HASH_MODULE_ENABLED
00072 #define HAL_GPIO_MODULE_ENABLED
00073 #define HAL_I2C_MODULE_ENABLED
00074 #define HAL_I2S_MODULE_ENABLED
00075 #define HAL_IWDG_MODULE_ENABLED
00076 #define HAL_LPTIM_MODULE_ENABLED
00077 #define HAL_LTDC_MODULE_ENABLED
00078 #define HAL_PWR_MODULE_ENABLED
00079 #define HAL_QSPI_MODULE_ENABLED
00080 #define HAL_RCC_MODULE_ENABLED
00081 #define HAL_RNG_MODULE_ENABLED
00082 #define HAL_RTC_MODULE_ENABLED
00083 #define HAL_SAI_MODULE_ENABLED
00084 #define HAL_SD_MODULE_ENABLED
00085 #define HAL_SPDIFRX_MODULE_ENABLED
00086 #define HAL_SPI_MODULE_ENABLED
00087 #define HAL_TIM_MODULE_ENABLED
00088 #define HAL_UART_MODULE_ENABLED
00089 #define HAL_USART_MODULE_ENABLED
00090 #define HAL_IRDA_MODULE_ENABLED
00091 #define HAL_SMARTCARD_MODULE_ENABLED
00092 #define HAL_WWDG_MODULE_ENABLED
00093 #define HAL_CORTEX_MODULE_ENABLED
00094 #define HAL_PCD_MODULE_ENABLED
00095 #define HAL_HCD_MODULE_ENABLED
00096
00097
00098 /* ########################## HSE/HSI Values adaptation ##################### */
00099 /**
00100   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00101   *        This value is used by the RCC HAL module to compute the system frequency
00102   *        (when HSE is used as system clock source, directly or through the PLL).
00103   */
00104 #if !defined  (HSE_VALUE)
00105   #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
00106 #endif /* HSE_VALUE */
00107
00108 #if !defined  (HSE_STARTUP_TIMEOUT)
00109   #define HSE_STARTUP_TIMEOUT    ((uint32_t)500)   /*!< Time out for HSE start up, in ms */
00110 #endif /* HSE_STARTUP_TIMEOUT */
00111
00112 /**
00113   * @brief Internal High Speed oscillator (HSI) value.
00114   *        This value is used by the RCC HAL module to compute the system frequency
00115   *        (when HSI is used as system clock source, directly or through the PLL).
00116   */
00117 #if !defined  (HSI_VALUE)
00118   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
00119 #endif /* HSI_VALUE */
00120
00121 /**
00122   * @brief Internal Low Speed oscillator (LSI) value.
00123   */
00124 #if !defined  (LSI_VALUE)
00125  #define LSI_VALUE  ((uint32_t)32000)       /*!< LSI Typical Value in Hz*/
00126 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00127                                              The real value may vary depending on the variations
00128                                              in voltage and temperature.  */
00129 /**
00130   * @brief External Low Speed oscillator (LSE) value.
00131   */
00132 #if !defined  (LSE_VALUE)
00133  #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
00134 #endif /* LSE_VALUE */
00135
00136 /**
00137   * @brief External clock source for I2S peripheral
00138   *        This value is used by the I2S HAL module to compute the I2S clock source
00139   *        frequency, this source is inserted directly through I2S_CKIN pad.
00140   */
00141 #if !defined  (EXTERNAL_CLOCK_VALUE)
00142   #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
00143 #endif /* EXTERNAL_CLOCK_VALUE */
00144
00145 /* Tip: To avoid modifying this file each time you need to use different HSE,
00146    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00147
00148 /* ########################### System Configuration ######################### */
00149 /**
00150   * @brief This is the HAL system configuration section
00151   */
00152 #define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
00153 #define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
00154 #define  USE_RTOS                     0
00155 #define  PREFETCH_ENABLE              1
00156 #define  ART_ACCLERATOR_ENABLE        1 /* To enable instruction cache and prefetch */
00157
00158 /* ########################## Assert Selection ############################## */
00159 /**
00160   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00161   *        HAL drivers code
00162   */
00163 /* #define USE_FULL_ASSERT    1 */
00164
00165 /* ################## Ethernet peripheral configuration ##################### */
00166
00167 /* Section 1 : Ethernet peripheral configuration */
00168
00169 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
00170 #define MAC_ADDR0   2
00171 #define MAC_ADDR1   0
00172 #define MAC_ADDR2   0
00173 #define MAC_ADDR3   0
00174 #define MAC_ADDR4   0
00175 #define MAC_ADDR5   0
00176
00177 /* Definition of the Ethernet driver buffers size and count */
00178 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
00179 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
00180 #define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
00181 #define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
00182
00183 /* Section 2: PHY configuration section */
00184
00185 /* DP83848 PHY Address*/
00186 #define DP83848_PHY_ADDRESS             0x01
00187 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
00188 #define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
00189 /* PHY Configuration delay */
00190 #define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
00191
00192 #define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
00193 #define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
00194
00195 /* Section 3: Common PHY Registers */
00196
00197 #define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
00198 #define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
00199
00200 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
00201 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
00202 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
00203 #define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
00204 #define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
00205 #define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
00206 #define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
00207 #define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
00208 #define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
00209 #define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
00210
00211 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
00212 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
00213 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
00214
00215 /* Section 4: Extended PHY Registers */
00216
00217 #define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
00218 #define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
00219 #define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
00220
00221 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
00222 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
00223 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
00224
00225 #define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
00226 #define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
00227
00228 #define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
00229 #define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
00230
00231 /* Includes ------------------------------------------------------------------*/
00232 /**
00233   * @brief Include module's header file
00234   */
00235
00236 #ifdef HAL_RCC_MODULE_ENABLED
00237   #include "stm32f7xx_hal_rcc.h"
00238 #endif /* HAL_RCC_MODULE_ENABLED */
00239
00240 #ifdef HAL_GPIO_MODULE_ENABLED
00241   #include "stm32f7xx_hal_gpio.h"
00242 #endif /* HAL_GPIO_MODULE_ENABLED */
00243
00244 #ifdef HAL_DMA_MODULE_ENABLED
00245   #include "stm32f7xx_hal_dma.h"
00246 #endif /* HAL_DMA_MODULE_ENABLED */
00247
00248 #ifdef HAL_CORTEX_MODULE_ENABLED
00249   #include "stm32f7xx_hal_cortex.h"
00250 #endif /* HAL_CORTEX_MODULE_ENABLED */
00251
00252 #ifdef HAL_ADC_MODULE_ENABLED
00253   #include "stm32f7xx_hal_adc.h"
00254 #endif /* HAL_ADC_MODULE_ENABLED */
00255
00256 #ifdef HAL_CAN_MODULE_ENABLED
00257   #include "stm32f7xx_hal_can.h"
00258 #endif /* HAL_CAN_MODULE_ENABLED */
00259
00260 #ifdef HAL_CEC_MODULE_ENABLED
00261   #include "stm32f7xx_hal_cec.h"
00262 #endif /* HAL_CEC_MODULE_ENABLED */
00263
00264 #ifdef HAL_CRC_MODULE_ENABLED
00265   #include "stm32f7xx_hal_crc.h"
00266 #endif /* HAL_CRC_MODULE_ENABLED */
00267
00268 #ifdef HAL_CRYP_MODULE_ENABLED
00269   #include "stm32f7xx_hal_cryp.h"
00270 #endif /* HAL_CRYP_MODULE_ENABLED */
00271
00272 #ifdef HAL_DMA2D_MODULE_ENABLED
00273   #include "stm32f7xx_hal_dma2d.h"
00274 #endif /* HAL_DMA2D_MODULE_ENABLED */
00275
00276 #ifdef HAL_DAC_MODULE_ENABLED
00277   #include "stm32f7xx_hal_dac.h"
00278 #endif /* HAL_DAC_MODULE_ENABLED */
00279
00280 #ifdef HAL_DCMI_MODULE_ENABLED
00281   #include "stm32f7xx_hal_dcmi.h"
00282 #endif /* HAL_DCMI_MODULE_ENABLED */
00283
00284 #ifdef HAL_ETH_MODULE_ENABLED
00285   #include "stm32f7xx_hal_eth.h"
00286 #endif /* HAL_ETH_MODULE_ENABLED */
00287
00288 #ifdef HAL_FLASH_MODULE_ENABLED
00289   #include "stm32f7xx_hal_flash.h"
00290 #endif /* HAL_FLASH_MODULE_ENABLED */
00291
00292 #ifdef HAL_SRAM_MODULE_ENABLED
00293   #include "stm32f7xx_hal_sram.h"
00294 #endif /* HAL_SRAM_MODULE_ENABLED */
00295
00296 #ifdef HAL_NOR_MODULE_ENABLED
00297   #include "stm32f7xx_hal_nor.h"
00298 #endif /* HAL_NOR_MODULE_ENABLED */
00299
00300 #ifdef HAL_NAND_MODULE_ENABLED
00301   #include "stm32f7xx_hal_nand.h"
00302 #endif /* HAL_NAND_MODULE_ENABLED */
00303
00304 #ifdef HAL_SDRAM_MODULE_ENABLED
00305   #include "stm32f7xx_hal_sdram.h"
00306 #endif /* HAL_SDRAM_MODULE_ENABLED */
00307
00308 #ifdef HAL_HASH_MODULE_ENABLED
00309  #include "stm32f7xx_hal_hash.h"
00310 #endif /* HAL_HASH_MODULE_ENABLED */
00311
00312 #ifdef HAL_I2C_MODULE_ENABLED
00313  #include "stm32f7xx_hal_i2c.h"
00314 #endif /* HAL_I2C_MODULE_ENABLED */
00315
00316 #ifdef HAL_I2S_MODULE_ENABLED
00317  #include "stm32f7xx_hal_i2s.h"
00318 #endif /* HAL_I2S_MODULE_ENABLED */
00319
00320 #ifdef HAL_IWDG_MODULE_ENABLED
00321  #include "stm32f7xx_hal_iwdg.h"
00322 #endif /* HAL_IWDG_MODULE_ENABLED */
00323
00324 #ifdef HAL_LPTIM_MODULE_ENABLED
00325  #include "stm32f7xx_hal_lptim.h"
00326 #endif /* HAL_LPTIM_MODULE_ENABLED */
00327
00328 #ifdef HAL_LTDC_MODULE_ENABLED
00329  #include "stm32f7xx_hal_ltdc.h"
00330 #endif /* HAL_LTDC_MODULE_ENABLED */
00331
00332 #ifdef HAL_PWR_MODULE_ENABLED
00333  #include "stm32f7xx_hal_pwr.h"
00334 #endif /* HAL_PWR_MODULE_ENABLED */
00335
00336 #ifdef HAL_QSPI_MODULE_ENABLED
00337  #include "stm32f7xx_hal_qspi.h"
00338 #endif /* HAL_QSPI_MODULE_ENABLED */
00339
00340 #ifdef HAL_RNG_MODULE_ENABLED
00341  #include "stm32f7xx_hal_rng.h"
00342 #endif /* HAL_RNG_MODULE_ENABLED */
00343
00344 #ifdef HAL_RTC_MODULE_ENABLED
00345  #include "stm32f7xx_hal_rtc.h"
00346 #endif /* HAL_RTC_MODULE_ENABLED */
00347
00348 #ifdef HAL_SAI_MODULE_ENABLED
00349  #include "stm32f7xx_hal_sai.h"
00350 #endif /* HAL_SAI_MODULE_ENABLED */
00351
00352 #ifdef HAL_SD_MODULE_ENABLED
00353  #include "stm32f7xx_hal_sd.h"
00354 #endif /* HAL_SD_MODULE_ENABLED */
00355
00356 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00357  #include "stm32f7xx_hal_spdifrx.h"
00358 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
00359
00360 #ifdef HAL_SPI_MODULE_ENABLED
00361  #include "stm32f7xx_hal_spi.h"
00362 #endif /* HAL_SPI_MODULE_ENABLED */
00363
00364 #ifdef HAL_TIM_MODULE_ENABLED
00365  #include "stm32f7xx_hal_tim.h"
00366 #endif /* HAL_TIM_MODULE_ENABLED */
00367
00368 #ifdef HAL_UART_MODULE_ENABLED
00369  #include "stm32f7xx_hal_uart.h"
00370 #endif /* HAL_UART_MODULE_ENABLED */
00371
00372 #ifdef HAL_USART_MODULE_ENABLED
00373  #include "stm32f7xx_hal_usart.h"
00374 #endif /* HAL_USART_MODULE_ENABLED */
00375
00376 #ifdef HAL_IRDA_MODULE_ENABLED
00377  #include "stm32f7xx_hal_irda.h"
00378 #endif /* HAL_IRDA_MODULE_ENABLED */
00379
00380 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00381  #include "stm32f7xx_hal_smartcard.h"
00382 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00383
00384 #ifdef HAL_WWDG_MODULE_ENABLED
00385  #include "stm32f7xx_hal_wwdg.h"
00386 #endif /* HAL_WWDG_MODULE_ENABLED */
00387
00388 #ifdef HAL_PCD_MODULE_ENABLED
00389  #include "stm32f7xx_hal_pcd.h"
00390 #endif /* HAL_PCD_MODULE_ENABLED */
00391
00392 #ifdef HAL_HCD_MODULE_ENABLED
00393  #include "stm32f7xx_hal_hcd.h"
00394 #endif /* HAL_HCD_MODULE_ENABLED */
00395
00396 /* Exported macro ------------------------------------------------------------*/
00397 #ifdef  USE_FULL_ASSERT
00398 /**
00399   * @brief  The assert_param macro is used for function's parameters check.
00400   * @param  expr: If expr is false, it calls assert_failed function
00401   *         which reports the name of the source file and the source
00402   *         line number of the call that failed.
00403   *         If expr is true, it returns no value.
00404   * @retval None
00405   */
00406   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00407 /* Exported functions ------------------------------------------------------- */
00408   void assert_failed(uint8_t* file, uint32_t line);
00409 #else
00410   #define assert_param(expr) ((void)0)
00411 #endif /* USE_FULL_ASSERT */
00412
00413
00414 #ifdef __cplusplus
00415 }
00416 #endif
00417
00418 #endif /* __STM32F7xx_HAL_CONF_H */
00419
00420
00421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cortex.c Source File

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stm32f7xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   CORTEX HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CORTEX:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017
00018     [..]
00019     *** How to configure Interrupts using CORTEX HAL driver ***
00020     ===========================================================
00021     [..]
00022     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00023     The Cortex-M4 exceptions are managed by CMSIS functions.
00024
00025     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
00026         function according to the following table.
00027     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00028     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00029     (#) please refer to programming manual for details in how to configure priority.
00030
00031      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
00032          The pending IRQ priority will be managed only by the sub priority.
00033
00034      -@- IRQ priority order (sorted by highest to lowest priority):
00035         (+@) Lowest preemption priority
00036         (+@) Lowest sub priority
00037         (+@) Lowest hardware priority (IRQ number)
00038
00039     [..]
00040     *** How to configure Systick using CORTEX HAL driver ***
00041     ========================================================
00042     [..]
00043     Setup SysTick Timer for time base.
00044
00045    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
00046        is a CMSIS function that:
00047         (++) Configures the SysTick Reload register with value passed as function parameter.
00048         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
00049         (++) Resets the SysTick Counter register.
00050         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00051         (++) Enables the SysTick Interrupt.
00052         (++) Starts the SysTick Counter.
00053
00054    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00055        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00056        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00057        inside the stm32f7xx_hal_cortex.h file.
00058
00059    (+) You can change the SysTick IRQ priority by calling the
00060        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00061        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00062
00063    (+) To adjust the SysTick time base, use the following formula:
00064
00065        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00066        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00067        (++) Reload Value should not exceed 0xFFFFFF
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f7xx_hal.h"
00102
00103 /** @addtogroup STM32F7xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup CORTEX CORTEX
00108   * @brief CORTEX HAL module driver
00109   * @{
00110   */
00111
00112 #ifdef HAL_CORTEX_MODULE_ENABLED
00113
00114 /* Private types -------------------------------------------------------------*/
00115 /* Private variables ---------------------------------------------------------*/
00116 /* Private constants ---------------------------------------------------------*/
00117 /* Private macros ------------------------------------------------------------*/
00118 /* Private functions ---------------------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120
00121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00122   * @{
00123   */
00124
00125
00126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
00127  *  @brief    Initialization and Configuration functions
00128  *
00129 @verbatim
00130   ==============================================================================
00131               ##### Initialization and de-initialization functions #####
00132   ==============================================================================
00133     [..]
00134       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00135       Systick functionalities
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141
00142 /**
00143   * @brief  Sets the priority grouping field (preemption priority and subpriority)
00144   *         using the required unlock sequence.
00145   * @param  PriorityGroup: The priority grouping bits length.
00146   *         This parameter can be one of the following values:
00147   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00148   *                                    4 bits for subpriority
00149   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00150   *                                    3 bits for subpriority
00151   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00152   *                                    2 bits for subpriority
00153   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00154   *                                    1 bits for subpriority
00155   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00156   *                                    0 bits for subpriority
00157   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
00158   *         The pending IRQ priority will be managed only by the subpriority.
00159   * @retval None
00160   */
00161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00162 {
00163   /* Check the parameters */
00164   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00165
00166   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00167   NVIC_SetPriorityGrouping(PriorityGroup);
00168 }
00169
00170 /**
00171   * @brief  Sets the priority of an interrupt.
00172   * @param  IRQn: External interrupt number.
00173   *         This parameter can be an enumerator of IRQn_Type enumeration
00174   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00175   * @param  PreemptPriority: The preemption priority for the IRQn channel.
00176   *         This parameter can be a value between 0 and 15
00177   *         A lower priority value indicates a higher priority
00178   * @param  SubPriority: the subpriority level for the IRQ channel.
00179   *         This parameter can be a value between 0 and 15
00180   *         A lower priority value indicates a higher priority.
00181   * @retval None
00182   */
00183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00184 {
00185   uint32_t prioritygroup = 0x00;
00186
00187   /* Check the parameters */
00188   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00189   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00190
00191   prioritygroup = NVIC_GetPriorityGrouping();
00192
00193   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00194 }
00195
00196 /**
00197   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
00198   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00199   *         function should be called before.
00200   * @param  IRQn External interrupt number.
00201   *         This parameter can be an enumerator of IRQn_Type enumeration
00202   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00203   * @retval None
00204   */
00205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00206 {
00207   /* Check the parameters */
00208   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00209
00210   /* Enable interrupt */
00211   NVIC_EnableIRQ(IRQn);
00212 }
00213
00214 /**
00215   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
00216   * @param  IRQn External interrupt number.
00217   *         This parameter can be an enumerator of IRQn_Type enumeration
00218   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00219   * @retval None
00220   */
00221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00222 {
00223   /* Check the parameters */
00224   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00225
00226   /* Disable interrupt */
00227   NVIC_DisableIRQ(IRQn);
00228 }
00229
00230 /**
00231   * @brief  Initiates a system reset request to reset the MCU.
00232   * @retval None
00233   */
00234 void HAL_NVIC_SystemReset(void)
00235 {
00236   /* System Reset */
00237   NVIC_SystemReset();
00238 }
00239
00240 /**
00241   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00242   *         Counter is in free running mode to generate periodic interrupts.
00243   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
00244   * @retval status:  - 0  Function succeeded.
00245   *                  - 1  Function failed.
00246   */
00247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00248 {
00249    return SysTick_Config(TicksNumb);
00250 }
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00256  *  @brief   Cortex control functions
00257  *
00258 @verbatim
00259   ==============================================================================
00260                       ##### Peripheral Control functions #####
00261   ==============================================================================
00262     [..]
00263       This subsection provides a set of functions allowing to control the CORTEX
00264       (NVIC, SYSTICK, MPU) functionalities.
00265
00266
00267 @endverbatim
00268   * @{
00269   */
00270
00271 #if (__MPU_PRESENT == 1)
00272 /**
00273   * @brief  Initializes and configures the Region and the memory to be protected.
00274   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
00275   *                the initialization and configuration information.
00276   * @retval None
00277   */
00278 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00279 {
00280   /* Check the parameters */
00281   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00282   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00283
00284   /* Set the Region number */
00285   MPU->RNR = MPU_Init->Number;
00286
00287   if ((MPU_Init->Enable) != RESET)
00288   {
00289     /* Check the parameters */
00290     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00291     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00292     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00293     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00294     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00295     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00296     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00297     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00298
00299     MPU->RBAR = MPU_Init->BaseAddress;
00300     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00301                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00302                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00303                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00304                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00305                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00306                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00307                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00308                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00309   }
00310   else
00311   {
00312     MPU->RBAR = 0x00;
00313     MPU->RASR = 0x00;
00314   }
00315 }
00316 #endif /* __MPU_PRESENT */
00317
00318 /**
00319   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
00320   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00321   */
00322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00323 {
00324   /* Get the PRIGROUP[10:8] field value */
00325   return NVIC_GetPriorityGrouping();
00326 }
00327
00328 /**
00329   * @brief  Gets the priority of an interrupt.
00330   * @param  IRQn: External interrupt number.
00331   *         This parameter can be an enumerator of IRQn_Type enumeration
00332   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00333   * @param   PriorityGroup: the priority grouping bits length.
00334   *         This parameter can be one of the following values:
00335   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00336   *                                      4 bits for subpriority
00337   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00338   *                                      3 bits for subpriority
00339   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00340   *                                      2 bits for subpriority
00341   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00342   *                                      1 bits for subpriority
00343   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00344   *                                      0 bits for subpriority
00345   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
00346   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
00347   * @retval None
00348   */
00349 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00350 {
00351   /* Check the parameters */
00352   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00353  /* Get priority for Cortex-M system or device specific interrupts */
00354   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00355 }
00356
00357 /**
00358   * @brief  Sets Pending bit of an external interrupt.
00359   * @param  IRQn External interrupt number
00360   *         This parameter can be an enumerator of IRQn_Type enumeration
00361   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00362   * @retval None
00363   */
00364 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00365 {
00366   /* Check the parameters */
00367   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00368
00369   /* Set interrupt pending */
00370   NVIC_SetPendingIRQ(IRQn);
00371 }
00372
00373 /**
00374   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
00375   *         and returns the pending bit for the specified interrupt).
00376   * @param  IRQn External interrupt number.
00377   *          This parameter can be an enumerator of IRQn_Type enumeration
00378   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00379   * @retval status: - 0  Interrupt status is not pending.
00380   *                 - 1  Interrupt status is pending.
00381   */
00382 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00383 {
00384   /* Check the parameters */
00385   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00386
00387   /* Return 1 if pending else 0 */
00388   return NVIC_GetPendingIRQ(IRQn);
00389 }
00390
00391 /**
00392   * @brief  Clears the pending bit of an external interrupt.
00393   * @param  IRQn External interrupt number.
00394   *         This parameter can be an enumerator of IRQn_Type enumeration
00395   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00396   * @retval None
00397   */
00398 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00399 {
00400   /* Check the parameters */
00401   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00402
00403   /* Clear pending interrupt */
00404   NVIC_ClearPendingIRQ(IRQn);
00405 }
00406
00407 /**
00408   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
00409   * @param IRQn External interrupt number
00410   *         This parameter can be an enumerator of IRQn_Type enumeration
00411   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
00412   * @retval status: - 0  Interrupt status is not pending.
00413   *                 - 1  Interrupt status is pending.
00414   */
00415 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00416 {
00417   /* Check the parameters */
00418   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00419
00420   /* Return 1 if active else 0 */
00421   return NVIC_GetActive(IRQn);
00422 }
00423
00424 /**
00425   * @brief  Configures the SysTick clock source.
00426   * @param  CLKSource: specifies the SysTick clock source.
00427   *          This parameter can be one of the following values:
00428   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00429   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00430   * @retval None
00431   */
00432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00433 {
00434   /* Check the parameters */
00435   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00436   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00437   {
00438     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00439   }
00440   else
00441   {
00442     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00443   }
00444 }
00445
00446 /**
00447   * @brief  This function handles SYSTICK interrupt request.
00448   * @retval None
00449   */
00450 void HAL_SYSTICK_IRQHandler(void)
00451 {
00452   HAL_SYSTICK_Callback();
00453 }
00454
00455 /**
00456   * @brief  SYSTICK callback.
00457   * @retval None
00458   */
00459 __weak void HAL_SYSTICK_Callback(void)
00460 {
00461 __IO uint32_t tmpreg = 0x00;
00462   UNUSED(tmpreg);
00463   /* NOTE : This function Should not be modified, when the callback is needed,
00464             the HAL_SYSTICK_Callback could be implemented in the user file
00465    */
00466 }
00467
00468 /**
00469   * @}
00470   */
00471
00472 /**
00473   * @}
00474   */
00475
00476 #endif /* HAL_CORTEX_MODULE_ENABLED */
00477 /**
00478   * @}
00479   */
00480
00481 /**
00482   * @}
00483   */
00484
00485 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cortex.h Source File

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stm32f7xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CORTEX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CORTEX_H
00040 #define __STM32F7xx_HAL_CORTEX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CORTEX
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
00058   * @{
00059   */
00060
00061 #if (__MPU_PRESENT == 1)
00062 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00063   * @brief  MPU Region initialization structure
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint8_t                Enable;                /*!< Specifies the status of the region.
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00070   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00071                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00072   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00073   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00074                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00075   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00076                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00077   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00079   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00081   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00083   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00085   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00087   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00088                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00089 }MPU_Region_InitTypeDef;
00090 /**
00091   * @}
00092   */
00093 #endif /* __MPU_PRESENT */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100
00101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00106   * @{
00107   */
00108 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
00109                                                                  4 bits for subpriority */
00110 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
00111                                                                  3 bits for subpriority */
00112 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
00113                                                                  2 bits for subpriority */
00114 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
00115                                                                  1 bits for subpriority */
00116 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
00117                                                                  0 bits for subpriority */
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
00123   * @{
00124   */
00125 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
00126 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
00127
00128 /**
00129   * @}
00130   */
00131
00132 #if (__MPU_PRESENT == 1)
00133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00134   * @{
00135   */
00136 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
00137 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
00138 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
00139 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00145   * @{
00146   */
00147 #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
00148 #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00154   * @{
00155   */
00156 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00157 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00163   * @{
00164   */
00165 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00166 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00172   * @{
00173   */
00174 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
00175 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00181   * @{
00182   */
00183 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
00184 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00190   * @{
00191   */
00192 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
00193 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
00194 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00200   * @{
00201   */
00202 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
00203 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
00204 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
00205 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
00206 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
00207 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
00208 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
00209 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
00210 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
00211 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
00212 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
00213 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
00214 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
00215 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
00216 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
00217 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
00218 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
00219 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
00220 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
00221 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
00222 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
00223 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
00224 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
00225 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
00226 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
00227 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
00228 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
00229 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00235   * @{
00236   */
00237 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
00238 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
00239 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
00240 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
00241 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
00242 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00248   * @{
00249   */
00250 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
00251 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
00252 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
00253 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
00254 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
00255 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
00256 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
00257 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
00258 /**
00259   * @}
00260   */
00261 #endif /* __MPU_PRESENT */
00262
00263 /**
00264   * @}
00265   */
00266
00267
00268 /* Exported Macros -----------------------------------------------------------*/
00269
00270 /* Exported functions --------------------------------------------------------*/
00271 /** @addtogroup CORTEX_Exported_Functions
00272   * @{
00273   */
00274
00275 /** @addtogroup CORTEX_Exported_Functions_Group1
00276  * @{
00277  */
00278 /* Initialization and de-initialization functions *****************************/
00279 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00283 void HAL_NVIC_SystemReset(void);
00284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00285 /**
00286   * @}
00287   */
00288
00289 /** @addtogroup CORTEX_Exported_Functions_Group2
00290  * @{
00291  */
00292 /* Peripheral Control functions ***********************************************/
00293 #if (__MPU_PRESENT == 1)
00294 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00295 #endif /* __MPU_PRESENT */
00296 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00298 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00299 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00300 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00301 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00302 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00303 void HAL_SYSTICK_IRQHandler(void);
00304 void HAL_SYSTICK_Callback(void);
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Private types -------------------------------------------------------------*/
00314 /* Private variables ---------------------------------------------------------*/
00315 /* Private constants ---------------------------------------------------------*/
00316 /* Private macros ------------------------------------------------------------*/
00317 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00318   * @{
00319   */
00320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00321                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00322                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00323                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00324                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00325
00326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00327
00328 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
00329
00330 #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
00331
00332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00333                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00334
00335 #if (__MPU_PRESENT == 1)
00336 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00337                                      ((STATE) == MPU_REGION_DISABLE))
00338
00339 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00340                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00341
00342 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00343                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00344
00345 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00346                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00347
00348 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00349                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00350
00351 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00352                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00353                                 ((TYPE) == MPU_TEX_LEVEL2))
00354
00355 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00356                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00357                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00358                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00359                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00360                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00361
00362 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00363                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00364                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00365                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00366                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00367                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00368                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00369                                          ((NUMBER) == MPU_REGION_NUMBER7))
00370
00371 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00372                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00373                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00374                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00375                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00376                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00377                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00378                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00379                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00380                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00381                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00382                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00383                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00384                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00385                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00386                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00387                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00388                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00389                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00390                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00391                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00392                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00393                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00394                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00395                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00396                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00397                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00398                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00399
00400 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00401 #endif /* __MPU_PRESENT */
00402
00403 /**
00404   * @}
00405   */
00406
00407 /* Private functions ---------------------------------------------------------*/
00408 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
00409   * @brief    CORTEX private  functions
00410   * @{
00411   */
00412
00413 #if (__MPU_PRESENT == 1)
00414 /**
00415   * @brief  Disables the MPU
00416   * @retval None
00417   */
00418 __STATIC_INLINE void HAL_MPU_Disable(void)
00419 {
00420   /* Disable fault exceptions */
00421   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00422
00423   /* Disable the MPU */
00424   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00425 }
00426
00427 /**
00428   * @brief  Enables the MPU
00429   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00430   *          NMI, FAULTMASK and privileged access to the default memory
00431   *          This parameter can be one of the following values:
00432   *            @arg MPU_HFNMI_PRIVDEF_NONE
00433   *            @arg MPU_HARDFAULT_NMI
00434   *            @arg MPU_PRIVILEGED_DEFAULT
00435   *            @arg MPU_HFNMI_PRIVDEF
00436   * @retval None
00437   */
00438 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
00439 {
00440   /* Enable the MPU */
00441   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
00442
00443   /* Enable fault exceptions */
00444   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00445 }
00446 #endif /* __MPU_PRESENT */
00447
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /**
00457   * @}
00458   */
00459
00460 #ifdef __cplusplus
00461 }
00462 #endif
00463
00464 #endif /* __STM32F7xx_HAL_CORTEX_H */
00465
00466
00467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc.c Source File

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stm32f7xx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   CRC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015  ===============================================================================
00016                      ##### CRC How to use this driver #####
00017  ===============================================================================
00018     [..]
00019
00020     (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00021
00022     (#) Initialize CRC calculator
00023          (++) specify generating polynomial (IP default or non-default one)
00024          (++) specify initialization value (IP default or non-default one)
00025          (++) specify input data format
00026          (++) specify input or output data inversion mode if any
00027
00028     (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00029         input data buffer starting with the previously computed CRC as
00030         initialization value
00031
00032     (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
00033         input data buffer starting with the defined initialization value
00034         (default or non-default) to initiate CRC calculation
00035
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00041   *
00042   * Redistribution and use in source and binary forms, with or without modification,
00043   * are permitted provided that the following conditions are met:
00044   *   1. Redistributions of source code must retain the above copyright notice,
00045   *      this list of conditions and the following disclaimer.
00046   *   2. Redistributions in binary form must reproduce the above copyright notice,
00047   *      this list of conditions and the following disclaimer in the documentation
00048   *      and/or other materials provided with the distribution.
00049   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00050   *      may be used to endorse or promote products derived from this software
00051   *      without specific prior written permission.
00052   *
00053   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00054   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00055   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00056   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00057   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00058   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00059   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00060   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00061   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00062   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00063   *
00064   ******************************************************************************
00065   */
00066
00067 /* Includes ------------------------------------------------------------------*/
00068 #include "stm32f7xx_hal.h"
00069
00070 /** @addtogroup STM32F7xx_HAL_Driver
00071   * @{
00072   */
00073
00074 /** @defgroup CRC CRC
00075   * @brief CRC HAL module driver.
00076   * @{
00077   */
00078
00079 #ifdef HAL_CRC_MODULE_ENABLED
00080
00081 /* Private typedef -----------------------------------------------------------*/
00082 /* Private define ------------------------------------------------------------*/
00083 /* Private macro -------------------------------------------------------------*/
00084 /* Private variables ---------------------------------------------------------*/
00085 /* Private function prototypes -----------------------------------------------*/
00086 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00087 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00088 /* Exported functions --------------------------------------------------------*/
00089
00090 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00091   * @{
00092   */
00093
00094 /** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
00095   *  @brief    Initialization and Configuration functions.
00096   *
00097 @verbatim
00098  ===============================================================================
00099             ##### Initialization and de-initialization functions #####
00100  ===============================================================================
00101     [..]  This section provides functions allowing to:
00102       (+) Initialize the CRC according to the specified parameters
00103           in the CRC_InitTypeDef and create the associated handle
00104       (+) DeInitialize the CRC peripheral
00105       (+) Initialize the CRC MSP
00106       (+) DeInitialize CRC MSP
00107
00108 @endverbatim
00109   * @{
00110   */
00111
00112 /**
00113   * @brief  Initialize the CRC according to the specified
00114   *         parameters in the CRC_InitTypeDef and create the associated handle.
00115   * @param  hcrc: CRC handle
00116   * @retval HAL status
00117   */
00118 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00119 {
00120   /* Check the CRC handle allocation */
00121   if(hcrc == NULL)
00122   {
00123     return HAL_ERROR;
00124   }
00125
00126   /* Check the parameters */
00127   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00128
00129   if(hcrc->State == HAL_CRC_STATE_RESET)
00130   {
00131     /* Allocate lock resource and initialize it */
00132     hcrc->Lock = HAL_UNLOCKED;
00133     /* Init the low level hardware */
00134     HAL_CRC_MspInit(hcrc);
00135   }
00136
00137   /* Change CRC peripheral state */
00138   hcrc->State = HAL_CRC_STATE_BUSY;
00139
00140   /* check whether or not non-default generating polynomial has been
00141    * picked up by user */
00142   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00143   if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00144   {
00145     /* initialize IP with default generating polynomial */
00146     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00147     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00148   }
00149   else
00150   {
00151     /* initialize CRC IP with generating polynomial defined by user */
00152     if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00153     {
00154       return HAL_ERROR;
00155     }
00156   }
00157
00158   /* check whether or not non-default CRC initial value has been
00159    * picked up by user */
00160   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00161   if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00162   {
00163     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00164   }
00165   else
00166   {
00167     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00168   }
00169
00170
00171   /* set input data inversion mode */
00172   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00173   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00174
00175   /* set output data inversion mode */
00176   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00177   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00178
00179   /* makes sure the input data format (bytes, halfwords or words stream)
00180    * is properly specified by user */
00181   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00182
00183   /* Change CRC peripheral state */
00184   hcrc->State = HAL_CRC_STATE_READY;
00185
00186   /* Return function status */
00187   return HAL_OK;
00188 }
00189
00190 /**
00191   * @brief  DeInitialize the CRC peripheral.
00192   * @param  hcrc: CRC handle
00193   * @retval HAL status
00194   */
00195 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00196 {
00197   /* Check the CRC handle allocation */
00198   if(hcrc == NULL)
00199   {
00200     return HAL_ERROR;
00201   }
00202
00203   /* Check the parameters */
00204   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00205
00206   /* Check the CRC peripheral state */
00207   if(hcrc->State == HAL_CRC_STATE_BUSY)
00208   {
00209     return HAL_BUSY;
00210   }
00211
00212   /* Change CRC peripheral state */
00213   hcrc->State = HAL_CRC_STATE_BUSY;
00214
00215   /* Reset CRC calculation unit */
00216   __HAL_CRC_DR_RESET(hcrc);
00217
00218   /* DeInit the low level hardware */
00219   HAL_CRC_MspDeInit(hcrc);
00220
00221   /* Change CRC peripheral state */
00222   hcrc->State = HAL_CRC_STATE_RESET;
00223
00224   /* Process unlocked */
00225   __HAL_UNLOCK(hcrc);
00226
00227   /* Return function status */
00228   return HAL_OK;
00229 }
00230
00231 /**
00232   * @brief  Initialize the CRC MSP.
00233   * @param  hcrc: CRC handle
00234   * @retval None
00235   */
00236 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00237 {
00238   /* Prevent unused argument(s) compilation warning */
00239   UNUSED(hcrc);
00240
00241   /* NOTE : This function should not be modified, when the callback is needed,
00242             the HAL_CRC_MspInit can be implemented in the user file
00243    */
00244 }
00245
00246 /**
00247   * @brief  DeInitialize the CRC MSP.
00248   * @param  hcrc: CRC handle
00249   * @retval None
00250   */
00251 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00252 {
00253   /* Prevent unused argument(s) compilation warning */
00254   UNUSED(hcrc);
00255
00256   /* NOTE : This function should not be modified, when the callback is needed,
00257             the HAL_CRC_MspDeInit can be implemented in the user file
00258    */
00259 }
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup HAL_CRC_Group2 Peripheral Control functions
00266   *  @brief   Peripheral Control functions
00267   *
00268 @verbatim
00269  ==============================================================================
00270                       ##### Peripheral Control functions #####
00271  ==============================================================================
00272     [..]  This section provides functions allowing to:
00273       (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00274           using combination of the previous CRC value and the new one.
00275
00276           or
00277
00278       (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00279           independently of the previous CRC value.
00280
00281 @endverbatim
00282   * @{
00283   */
00284
00285 /**
00286   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00287   *         starting with the previously computed CRC as initialization value.
00288   * @param  hcrc: CRC handle
00289   * @param  pBuffer: pointer to the input data buffer, exact input data format is
00290   *         provided by hcrc->InputDataFormat.
00291   * @param  BufferLength: input data buffer length (number of bytes if pBuffer
00292   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00293   *         number of words if pBuffer type is * uint32_t).
00294   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00295   *        Input buffer pointers with other types simply need to be cast in uint32_t
00296   *        and the API will internally adjust its input data processing based on the
00297   *        handle field hcrc->InputDataFormat.
00298   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00299   */
00300 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00301 {
00302   uint32_t index = 0; /* CRC input data buffer index */
00303   uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
00304
00305   /* Process locked */
00306   __HAL_LOCK(hcrc);
00307
00308   /* Change CRC peripheral state */
00309   hcrc->State = HAL_CRC_STATE_BUSY;
00310
00311   switch (hcrc->InputDataFormat)
00312   {
00313     case CRC_INPUTDATA_FORMAT_WORDS:
00314       /* Enter Data to the CRC calculator */
00315       for(index = 0; index < BufferLength; index++)
00316       {
00317         hcrc->Instance->DR = pBuffer[index];
00318       }
00319       temp = hcrc->Instance->DR;
00320       break;
00321
00322     case CRC_INPUTDATA_FORMAT_BYTES:
00323       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00324       break;
00325
00326     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00327       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00328       break;
00329     default:
00330       break;
00331   }
00332
00333   /* Change CRC peripheral state */
00334   hcrc->State = HAL_CRC_STATE_READY;
00335
00336   /* Process unlocked */
00337   __HAL_UNLOCK(hcrc);
00338
00339   /* Return the CRC computed value */
00340   return temp;
00341 }
00342
00343 /**
00344   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00345   *         starting with hcrc->Instance->INIT as initialization value.
00346   * @param  hcrc: CRC handle
00347   * @param  pBuffer: pointer to the input data buffer, exact input data format is
00348   *         provided by hcrc->InputDataFormat.
00349   * @param  BufferLength: input data buffer length (number of bytes if pBuffer
00350   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00351   *         number of words if pBuffer type is * uint32_t).
00352   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00353   *        Input buffer pointers with other types simply need to be cast in uint32_t
00354   *        and the API will internally adjust its input data processing based on the
00355   *        handle field hcrc->InputDataFormat.
00356   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00357   */
00358 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00359 {
00360   uint32_t index = 0; /* CRC input data buffer index */
00361   uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
00362
00363   /* Process locked */
00364   __HAL_LOCK(hcrc);
00365
00366   /* Change CRC peripheral state */
00367   hcrc->State = HAL_CRC_STATE_BUSY;
00368
00369   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00370   *  written in hcrc->Instance->DR) */
00371   __HAL_CRC_DR_RESET(hcrc);
00372
00373   switch (hcrc->InputDataFormat)
00374   {
00375     case CRC_INPUTDATA_FORMAT_WORDS:
00376       /* Enter 32-bit input data to the CRC calculator */
00377       for(index = 0; index < BufferLength; index++)
00378       {
00379         hcrc->Instance->DR = pBuffer[index];
00380       }
00381       temp = hcrc->Instance->DR;
00382       break;
00383
00384     case CRC_INPUTDATA_FORMAT_BYTES:
00385       /* Specific 8-bit input data handling  */
00386       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00387       break;
00388
00389     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00390       /* Specific 16-bit input data handling  */
00391       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00392       break;
00393     default:
00394       break;
00395   }
00396
00397   /* Change CRC peripheral state */
00398   hcrc->State = HAL_CRC_STATE_READY;
00399
00400   /* Process unlocked */
00401   __HAL_UNLOCK(hcrc);
00402
00403   /* Return the CRC computed value */
00404   return temp;
00405 }
00406
00407 /**
00408   * @brief  Enter 8-bit input data to the CRC calculator.
00409   *         Specific data handling to optimize processing time.
00410   * @param  hcrc: CRC handle
00411   * @param  pBuffer: pointer to the input data buffer
00412   * @param  BufferLength: input data buffer length
00413   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00414   */
00415 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00416 {
00417   uint32_t i = 0; /* input data buffer index */
00418
00419    /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00420     * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00421     * handling by the IP */
00422    for(i = 0; i < (BufferLength/4); i++)
00423    {
00424      hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
00425    }
00426    /* last bytes specific handling */
00427    if((BufferLength%4) != 0)
00428    {
00429      if(BufferLength%4 == 1)
00430      {
00431        *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
00432      }
00433      if(BufferLength%4 == 2)
00434      {
00435        *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
00436      }
00437      if(BufferLength%4 == 3)
00438      {
00439        *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
00440        *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
00441      }
00442    }
00443
00444   /* Return the CRC computed value */
00445   return hcrc->Instance->DR;
00446 }
00447
00448 /**
00449   * @brief  Enter 16-bit input data to the CRC calculator.
00450   *         Specific data handling to optimize processing time.
00451   * @param  hcrc: CRC handle
00452   * @param  pBuffer: pointer to the input data buffer
00453   * @param  BufferLength: input data buffer length
00454   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00455   */
00456 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00457 {
00458   uint32_t i = 0;  /* input data buffer index */
00459
00460   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00461    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00462    * a correct type handling by the IP */
00463   for(i = 0; i < (BufferLength/2); i++)
00464   {
00465     hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
00466   }
00467   if((BufferLength%2) != 0)
00468   {
00469      *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
00470   }
00471
00472   /* Return the CRC computed value */
00473   return hcrc->Instance->DR;
00474 }
00475
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup HAL_CRC_Group3 Peripheral State functions
00481   *  @brief    Peripheral State functions.
00482   *
00483 @verbatim
00484  ==============================================================================
00485                       ##### Peripheral State functions #####
00486  ==============================================================================
00487     [..]
00488     This subsection permits to get in run-time the status of the peripheral
00489     and the data flow.
00490
00491 @endverbatim
00492   * @{
00493   */
00494
00495 /**
00496   * @brief  Return the CRC state.
00497   * @param  hcrc: CRC handle
00498   * @retval HAL state
00499   */
00500 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00501 {
00502   return hcrc->State;
00503 }
00504
00505 /**
00506   * @}
00507   */
00508
00509 /**
00510   * @}
00511   */
00512
00513 #endif /* HAL_CRC_MODULE_ENABLED */
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:24 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc.h Source File

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stm32f7xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CRC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CRC_H
00040 #define __STM32F7xx_HAL_CRC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup CRC CRC
00054   * @brief CRC HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup CRC_Exported_Types CRC Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
00069   HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
00070   HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
00071   HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
00072   HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
00073 }HAL_CRC_StateTypeDef;
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition
00079   * @{
00080   */
00081 typedef struct
00082 {
00083   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00084                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00085                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
00086                                             In that case, there is no need to set GeneratingPolynomial field.
00087                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
00088
00089   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00090                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00091                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field.
00092                                            If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set */
00093
00094   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
00095                                            respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
00096                                            e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
00097                                            No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE   */
00098
00099   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00100                                            Value can be either one of
00101                                            CRC_POLYLENGTH_32B                  (32-bit CRC)
00102                                            CRC_POLYLENGTH_16B                  (16-bit CRC)
00103                                            CRC_POLYLENGTH_8B                   (8-bit CRC)
00104                                            CRC_POLYLENGTH_7B                   (7-bit CRC) */
00105
00106   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00107                                            is set to DEFAULT_INIT_VALUE_ENABLE   */
00108
00109   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00110                                            Can be either one of the following values
00111                                            CRC_INPUTDATA_INVERSION_NONE      no input data inversion
00112                                            CRC_INPUTDATA_INVERSION_BYTE      byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
00113                                            CRC_INPUTDATA_INVERSION_HALFWORD  halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
00114                                            CRC_INPUTDATA_INVERSION_WORD      word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
00115
00116   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00117                                             Can be either
00118                                             CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion, or
00119                                             CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
00120 }CRC_InitTypeDef;
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition
00126   * @{
00127   */
00128 typedef struct
00129 {
00130   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00131
00132   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00133
00134   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00135
00136   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00137
00138   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00139                                             Can be either
00140                                             CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
00141                                             CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
00142                                             CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bits data)
00143                                            Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
00144                                            must occur if InputBufferFormat is not one of the three values listed above  */
00145 }CRC_HandleTypeDef;
00146 /**
00147   * @}
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Exported constants --------------------------------------------------------*/
00155 /** @defgroup CRC_Exported_Constants   CRC exported constants
00156   * @{
00157   */
00158
00159 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00160   * @{
00161   */
00162 #define DEFAULT_CRC32_POLY      0x04C11DB7
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00169   * @{
00170   */
00171 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFF
00172
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00178   * @{
00179   */
00180 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00)
00181 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01)
00182
00183
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00189   * @{
00190   */
00191 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00)
00192 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01)
00193
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
00199   * @{
00200   */
00201 #define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000)
00202 #define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0)
00203 #define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1)
00204 #define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00210   * @{
00211   */
00212 #define HAL_CRC_LENGTH_32B     32
00213 #define HAL_CRC_LENGTH_16B     16
00214 #define HAL_CRC_LENGTH_8B       8
00215 #define HAL_CRC_LENGTH_7B       7
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup CRC_Input_Buffer_Format CRC input buffer format
00222   * @{
00223   */
00224 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00225  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00226  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00227  * the CRC APIs to provide a correct result */
00228 #define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000)
00229 #define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001)
00230 #define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002)
00231 #define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003)
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239 /* Exported macros -----------------------------------------------------------*/
00240
00241 /** @defgroup CRC_Exported_Macros CRC exported macros
00242   * @{
00243   */
00244
00245 /** @brief Reset CRC handle state
00246   * @param  __HANDLE__: CRC handle.
00247   * @retval None
00248   */
00249 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00250
00251 /**
00252   * @brief  Reset CRC Data Register.
00253   * @param  __HANDLE__: CRC handle
00254   * @retval None.
00255   */
00256 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00257
00258 /**
00259   * @brief  Set CRC INIT non-default value
00260   * @param  __HANDLE__    : CRC handle
00261   * @param  __INIT__      : 32-bit initial value
00262   * @retval None.
00263   */
00264 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00265
00266 /**
00267   * @brief Stores a 8-bit data in the Independent Data(ID) register.
00268   * @param __HANDLE__: CRC handle
00269   * @param __VALUE__: 8-bit value to be stored in the ID register
00270   * @retval None
00271   */
00272 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
00273
00274 /**
00275   * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
00276   * @param __HANDLE__: CRC handle
00277   * @retval 8-bit value of the ID register
00278   */
00279 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00280 /**
00281   * @}
00282   */
00283
00284
00285 /* Include CRC HAL Extension module */
00286 #include "stm32f7xx_hal_crc_ex.h"
00287
00288 /* Exported functions --------------------------------------------------------*/
00289 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00290   * @{
00291   */
00292
00293 /** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
00294   * @{
00295   */
00296 /* Initialization and de-initialization functions  ****************************/
00297 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00298 HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
00299 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00300 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00301 /**
00302   * @}
00303   */
00304
00305 /* Aliases for inter STM32 series compatibility */
00306 #define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse
00307 #define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse
00308
00309 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00310   * @{
00311   */
00312 /* Peripheral Control functions ***********************************************/
00313 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00314 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00320   * @{
00321   */
00322 /* Peripheral State and Error functions ***************************************/
00323 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332
00333 /* Private types -------------------------------------------------------------*/
00334 /** @defgroup CRC_Private_Types CRC Private Types
00335   * @{
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /* Private defines -----------------------------------------------------------*/
00343 /** @defgroup CRC_Private_Defines CRC Private Defines
00344   * @{
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /* Private variables ---------------------------------------------------------*/
00352 /** @defgroup CRC_Private_Variables CRC Private Variables
00353   * @{
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /* Private constants ---------------------------------------------------------*/
00361 /** @defgroup CRC_Private_Constants CRC Private Constants
00362   * @{
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /* Private macros ------------------------------------------------------------*/
00370 /** @defgroup CRC_Private_Macros CRC Private Macros
00371   * @{
00372   */
00373 #define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
00374                                             ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
00375 #define IS_DEFAULT_INIT_VALUE(__VALUE__)  (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
00376                                            ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
00377 #define IS_CRC_POL_LENGTH(__LENGTH__)     (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
00378                                            ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
00379                                            ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \
00380                                            ((__LENGTH__) == CRC_POLYLENGTH_7B))
00381 #define IS_CRC_INPUTDATA_FORMAT(__FORMAT__)       (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
00382                                                    ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00383                                                    ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
00384
00385
00386 /**
00387   * @}
00388   */
00389
00390 /* Private functions prototypes ----------------------------------------------*/
00391 /** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
00392   * @{
00393   */
00394
00395 /**
00396   * @}
00397   */
00398
00399 /* Private functions ---------------------------------------------------------*/
00400 /** @defgroup CRC_Private_Functions CRC Private Functions
00401   * @{
00402   */
00403
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 /**
00413   * @}
00414   */
00415
00416 #ifdef __cplusplus
00417 }
00418 #endif
00419
00420 #endif /* __STM32F7xx_HAL_CRC_H */
00421
00422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00423
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc_ex.c Source File

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stm32f7xx_hal_crc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Extended CRC HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the CRC peripheral:
00011   *           + Initialization/de-initialization functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### CRC specific features #####
00016   ==============================================================================
00017   [..]
00018   (#) Polynomial configuration.
00019   (#) Input data reverse mode.
00020   (#) Output data reverse mode.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32f7xx_hal.h"
00055
00056 /** @addtogroup STM32F7xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @addtogroup CRCEx
00061   * @brief CRC Extended HAL module driver
00062   * @{
00063   */
00064
00065 #ifdef HAL_CRC_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 /* Private macro -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073
00074 /** @addtogroup CRCEx_Exported_Functions
00075   * @{
00076   */
00077
00078 /** @addtogroup CRCEx_Exported_Functions_Group1
00079  *  @brief    Extended CRC features functions
00080  *
00081 @verbatim
00082  ===============================================================================
00083             ##### CRC Extended features functions #####
00084  ===============================================================================
00085     [..]
00086 This subsection provides function allowing to:
00087       (+) Set CRC polynomial if different from default one.
00088
00089 @endverbatim
00090   * @{
00091   */
00092
00093
00094 /**
00095   * @brief  Initializes the CRC polynomial if different from default one.
00096   * @param  hcrc: CRC handle
00097   * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
00098   *         This parameter is written in normal representation, e.g.
00099   *         for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00100   *         for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00101   * @param  PolyLength: CRC polynomial length
00102   *         This parameter can be one of the following values:
00103   *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
00104   *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
00105   *          @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
00106   *          @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
00107   * @retval HAL status
00108   */
00109 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00110 {
00111   uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
00112
00113   /* Check the parameters */
00114   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00115
00116   /* check polynomial definition vs polynomial size:
00117    * polynomial length must be aligned with polynomial
00118    * definition. HAL_ERROR is reported if Pol degree is
00119    * larger than that indicated by PolyLength.
00120    * Look for MSB position: msb will contain the degree of
00121    *  the second to the largest polynomial member. E.g., for
00122    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00123   while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))
00124   {
00125   }
00126
00127   switch (PolyLength)
00128   {
00129     case CRC_POLYLENGTH_7B:
00130       if (msb >= HAL_CRC_LENGTH_7B)
00131       {
00132         return  HAL_ERROR;
00133       }
00134       break;
00135     case CRC_POLYLENGTH_8B:
00136       if (msb >= HAL_CRC_LENGTH_8B)
00137       {
00138         return  HAL_ERROR;
00139       }
00140       break;
00141     case CRC_POLYLENGTH_16B:
00142       if (msb >= HAL_CRC_LENGTH_16B)
00143       {
00144         return  HAL_ERROR;
00145       }
00146       break;
00147     case CRC_POLYLENGTH_32B:
00148       /* no polynomial definition vs. polynomial length issue possible */
00149       break;
00150   default:
00151       break;
00152   }
00153
00154   /* set generating polynomial */
00155   WRITE_REG(hcrc->Instance->POL, Pol);
00156
00157   /* set generating polynomial size */
00158   MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00159
00160   /* Return function status */
00161   return HAL_OK;
00162 }
00163
00164 /**
00165   * @brief  Set the Reverse Input data mode.
00166   * @param  hcrc: CRC handle
00167   * @param  InputReverseMode: Input Data inversion mode
00168   *         This parameter can be one of the following values:
00169   *          @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
00170   *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
00171   *          @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
00172   *          @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
00173   * @retval HAL status
00174   */
00175 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00176 {
00177   /* Check the parameters */
00178   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00179
00180   /* Change CRC peripheral state */
00181   hcrc->State = HAL_CRC_STATE_BUSY;
00182
00183   /* set input data inversion mode */
00184   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00185   /* Change CRC peripheral state */
00186   hcrc->State = HAL_CRC_STATE_READY;
00187
00188   /* Return function status */
00189   return HAL_OK;
00190 }
00191
00192 /**
00193   * @brief  Set the Reverse Output data mode.
00194   * @param  hcrc: CRC handle
00195   * @param  OutputReverseMode: Output Data inversion mode
00196   *         This parameter can be one of the following values:
00197   *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
00198   *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00202 {
00203   /* Check the parameters */
00204   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00205
00206   /* Change CRC peripheral state */
00207   hcrc->State = HAL_CRC_STATE_BUSY;
00208
00209   /* set output data inversion mode */
00210   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00211
00212   /* Change CRC peripheral state */
00213   hcrc->State = HAL_CRC_STATE_READY;
00214
00215   /* Return function status */
00216   return HAL_OK;
00217 }
00218
00219
00220
00221
00222 /**
00223   * @}
00224   */
00225
00226
00227 /**
00228   * @}
00229   */
00230
00231
00232 #endif /* HAL_CRC_MODULE_ENABLED */
00233 /**
00234   * @}
00235   */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00242
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_crc_ex.h Source File

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stm32f7xx_hal_crc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CRC HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CRC_EX_H
00040 #define __STM32F7xx_HAL_CRC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup CRCEx CRCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
00061  * @{
00062  */
00063
00064 /** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
00065   * @{
00066   */
00067 #define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000)
00068 #define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0)
00069 #define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1)
00070 #define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)
00071
00072 #define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)     (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
00073                                                        ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
00074                                                        ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00075                                                        ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
00081   * @{
00082   */
00083 #define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000)
00084 #define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT)
00085
00086 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)    (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00087                                                        ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00088 /**
00089   * @}
00090   */
00091
00092
00093 /**
00094  * @}
00095  */
00096 /* Exported macro ------------------------------------------------------------*/
00097
00098 /** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  Set CRC output reversal
00104   * @param  __HANDLE__    : CRC handle
00105   * @retval None.
00106   */
00107 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00108
00109 /**
00110   * @brief  Unset CRC output reversal
00111   * @param  __HANDLE__    : CRC handle
00112   * @retval None.
00113   */
00114 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00115
00116 /**
00117   * @brief  Set CRC non-default polynomial
00118   * @param  __HANDLE__    : CRC handle
00119   * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
00120   * @retval None.
00121   */
00122 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00123
00124 /**
00125   * @}
00126   */
00127
00128
00129 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00130   * @{
00131   */
00132
00133 /** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
00134   * @{
00135   */
00136 /* Exported functions --------------------------------------------------------*/
00137 /* Initialization and de-initialization functions  ****************************/
00138 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00139 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00140 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00141
00142 /* Peripheral Control functions ***********************************************/
00143 /* Peripheral State and Error functions ***************************************/
00144
00145 /**
00146   * @}
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153
00154 /**
00155   * @}
00156   */
00157
00158 /**
00159   * @}
00160   */
00161
00162 #ifdef __cplusplus
00163 }
00164 #endif
00165
00166 #endif /* __STM32F7xx_HAL_CRC_EX_H */
00167
00168 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp.c Source File

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stm32f7xx_hal_cryp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   CRYP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cryptography (CRYP) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + AES processing functions
00012   *           + DES processing functions
00013   *           + TDES processing functions
00014   *           + DMA callback functions
00015   *           + CRYP IRQ handler management
00016   *           + Peripheral State functions
00017   *
00018   @verbatim
00019   ==============================================================================
00020                      ##### How to use this driver #####
00021   ==============================================================================
00022     [..]
00023       The CRYP HAL driver can be used as follows:
00024
00025       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00026          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00027          (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
00028              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00029              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00030              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00031          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
00032              (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00033              (+++) Configure and enable two DMA streams one for managing data transfer from
00034                  memory to peripheral (input stream) and another stream for managing data
00035                  transfer from peripheral to memory (output stream)
00036              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00037                  using  __HAL_LINKDMA()
00038              (+++) Configure the priority and enable the NVIC for the transfer complete
00039                  interrupt on the two DMA Streams. The output stream should have higher
00040                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00041
00042       (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
00043          (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
00044          (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
00045          (##) The encryption/decryption key. It's size depends on the algorithm
00046               used for encryption/decryption
00047          (##) The initialization vector (counter). It is not used ECB mode.
00048
00049       (#)Three processing (encryption/decryption) functions are available:
00050          (##) Polling mode: encryption and decryption APIs are blocking functions
00051               i.e. they process the data and wait till the processing is finished,
00052               e.g. HAL_CRYP_AESCBC_Encrypt()
00053          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00054               i.e. they process the data under interrupt,
00055               e.g. HAL_CRYP_AESCBC_Encrypt_IT()
00056          (##) DMA mode: encryption and decryption APIs are not blocking functions
00057               i.e. the data transfer is ensured by DMA,
00058               e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
00059
00060       (#)When the processing function is called at first time after HAL_CRYP_Init()
00061          the CRYP peripheral is initialized and processes the buffer in input.
00062          At second call, the processing function performs an append of the already
00063          processed buffer.
00064          When a new data block is to be processed, call HAL_CRYP_Init() then the
00065          processing function.
00066
00067        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f7xx_hal.h"
00102
00103 /** @addtogroup STM32F7xx_HAL_Driver
00104   * @{
00105   */
00106 #if defined (STM32F756xx)
00107 /** @defgroup CRYP CRYP
00108   * @brief CRYP HAL module driver.
00109   * @{
00110   */
00111
00112
00113 #ifdef HAL_CRYP_MODULE_ENABLED
00114
00115 /* Private typedef -----------------------------------------------------------*/
00116 /* Private define ------------------------------------------------------------*/
00117 /** @addtogroup CRYP_Private_define
00118   * @{
00119   */
00120 #define CRYP_TIMEOUT_VALUE  1
00121 /**
00122   * @}
00123   */
00124
00125 /* Private macro -------------------------------------------------------------*/
00126 /* Private variables ---------------------------------------------------------*/
00127 /* Private function prototypes -----------------------------------------------*/
00128 /** @addtogroup CRYP_Private_Functions_prototypes
00129   * @{
00130   */
00131 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
00132 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
00133 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
00134 static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
00135 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00136 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00137 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00138 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00139 static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00140 static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00141 static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00142 static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00143 /**
00144   * @}
00145   */
00146 /* Private functions ---------------------------------------------------------*/
00147
00148 /** @addtogroup CRYP_Private_Functions
00149   * @{
00150   */
00151
00152 /**
00153   * @brief  DMA CRYP Input Data process complete callback.
00154   * @param  hdma: DMA handle
00155   * @retval None
00156   */
00157 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
00158 {
00159   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00160
00161   /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
00162      in the DMACR register */
00163   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
00164
00165   /* Call input data transfer complete callback */
00166   HAL_CRYP_InCpltCallback(hcryp);
00167 }
00168
00169 /**
00170   * @brief  DMA CRYP Output Data process complete callback.
00171   * @param  hdma: DMA handle
00172   * @retval None
00173   */
00174 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
00175 {
00176   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00177
00178   /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
00179      in the DMACR register */
00180   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
00181
00182   /* Disable CRYP */
00183   __HAL_CRYP_DISABLE(hcryp);
00184
00185   /* Change the CRYP state to ready */
00186   hcryp->State = HAL_CRYP_STATE_READY;
00187
00188   /* Call output data transfer complete callback */
00189   HAL_CRYP_OutCpltCallback(hcryp);
00190 }
00191
00192 /**
00193   * @brief  DMA CRYP communication error callback.
00194   * @param  hdma: DMA handle
00195   * @retval None
00196   */
00197 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
00198 {
00199   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00200   hcryp->State= HAL_CRYP_STATE_READY;
00201   HAL_CRYP_ErrorCallback(hcryp);
00202 }
00203
00204 /**
00205   * @brief  Writes the Key in Key registers.
00206   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00207   *         the configuration information for CRYP module
00208   * @param  Key: Pointer to Key buffer
00209   * @param  KeySize: Size of Key
00210   * @retval None
00211   */
00212 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
00213 {
00214   uint32_t keyaddr = (uint32_t)Key;
00215
00216   switch(KeySize)
00217   {
00218   case CRYP_KEYSIZE_256B:
00219     /* Key Initialisation */
00220     hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
00221     keyaddr+=4;
00222     hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
00223     keyaddr+=4;
00224     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00225     keyaddr+=4;
00226     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00227     keyaddr+=4;
00228     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00229     keyaddr+=4;
00230     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00231     keyaddr+=4;
00232     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00233     keyaddr+=4;
00234     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00235     break;
00236   case CRYP_KEYSIZE_192B:
00237     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00238     keyaddr+=4;
00239     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00240     keyaddr+=4;
00241     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00242     keyaddr+=4;
00243     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00244     keyaddr+=4;
00245     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00246     keyaddr+=4;
00247     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00248     break;
00249   case CRYP_KEYSIZE_128B:
00250     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00251     keyaddr+=4;
00252     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00253     keyaddr+=4;
00254     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00255     keyaddr+=4;
00256     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00257     break;
00258   default:
00259     break;
00260   }
00261 }
00262
00263 /**
00264   * @brief  Writes the InitVector/InitCounter in IV registers.
00265   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00266   *         the configuration information for CRYP module
00267   * @param  InitVector: Pointer to InitVector/InitCounter buffer
00268   * @param  IVSize: Size of the InitVector/InitCounter
00269   * @retval None
00270   */
00271 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
00272 {
00273   uint32_t ivaddr = (uint32_t)InitVector;
00274
00275   switch(IVSize)
00276   {
00277   case CRYP_KEYSIZE_128B:
00278     hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00279     ivaddr+=4;
00280     hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00281     ivaddr+=4;
00282     hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
00283     ivaddr+=4;
00284     hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
00285     break;
00286     /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
00287   case CRYP_KEYSIZE_192B:
00288     hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00289     ivaddr+=4;
00290     hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00291     break;
00292   case CRYP_KEYSIZE_256B:
00293     hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00294     ivaddr+=4;
00295     hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00296     break;
00297   default:
00298     break;
00299   }
00300 }
00301
00302 /**
00303   * @brief  Process Data: Writes Input data in polling mode and read the output data
00304   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00305   *         the configuration information for CRYP module
00306   * @param  Input: Pointer to the Input buffer
00307   * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
00308   * @param  Output: Pointer to the returned buffer
00309   * @param  Timeout: Timeout value
00310   * @retval None
00311   */
00312 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
00313 {
00314   uint32_t tickstart = 0;
00315
00316   uint32_t i = 0;
00317   uint32_t inputaddr  = (uint32_t)Input;
00318   uint32_t outputaddr = (uint32_t)Output;
00319
00320   for(i=0; (i < Ilength); i+=16)
00321   {
00322     /* Write the Input block in the IN FIFO */
00323     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00324     inputaddr+=4;
00325     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00326     inputaddr+=4;
00327     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
00328     inputaddr+=4;
00329     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00330     inputaddr+=4;
00331
00332     /* Get tick */
00333     tickstart = HAL_GetTick();
00334
00335     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00336     {
00337       /* Check for the Timeout */
00338       if(Timeout != HAL_MAX_DELAY)
00339       {
00340         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00341         {
00342           /* Change state */
00343           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00344
00345           /* Process Unlocked */
00346           __HAL_UNLOCK(hcryp);
00347
00348           return HAL_TIMEOUT;
00349         }
00350       }
00351     }
00352     /* Read the Output block from the Output FIFO */
00353     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00354     outputaddr+=4;
00355     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00356     outputaddr+=4;
00357     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00358     outputaddr+=4;
00359     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00360     outputaddr+=4;
00361   }
00362   /* Return function status */
00363   return HAL_OK;
00364 }
00365
00366 /**
00367   * @brief  Process Data: Write Input data in polling mode.
00368   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00369   *         the configuration information for CRYP module
00370   * @param  Input: Pointer to the Input buffer
00371   * @param  Ilength: Length of the Input buffer, must be a multiple of 8
00372   * @param  Output: Pointer to the returned buffer
00373   * @param  Timeout: Specify Timeout value
00374   * @retval None
00375   */
00376 static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
00377 {
00378   uint32_t tickstart = 0;
00379
00380   uint32_t i = 0;
00381   uint32_t inputaddr  = (uint32_t)Input;
00382   uint32_t outputaddr = (uint32_t)Output;
00383
00384   for(i=0; (i < Ilength); i+=8)
00385   {
00386     /* Write the Input block in the IN FIFO */
00387     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
00388     inputaddr+=4;
00389     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00390     inputaddr+=4;
00391
00392     /* Get tick */
00393     tickstart = HAL_GetTick();
00394
00395     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00396     {
00397       /* Check for the Timeout */
00398       if(Timeout != HAL_MAX_DELAY)
00399       {
00400         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00401         {
00402           /* Change state */
00403           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00404
00405           /* Process Unlocked */
00406           __HAL_UNLOCK(hcryp);
00407
00408           return HAL_TIMEOUT;
00409         }
00410       }
00411     }
00412     /* Read the Output block from the Output FIFO */
00413     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00414     outputaddr+=4;
00415     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00416     outputaddr+=4;
00417   }
00418   /* Return function status */
00419   return HAL_OK;
00420 }
00421
00422 /**
00423   * @brief  Set the DMA configuration and start the DMA transfer
00424   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00425   *         the configuration information for CRYP module
00426   * @param  inputaddr: address of the Input buffer
00427   * @param  Size: Size of the Input buffer, must be a multiple of 16.
00428   * @param  outputaddr: address of the Output buffer
00429   * @retval None
00430   */
00431 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
00432 {
00433   /* Set the CRYP DMA transfer complete callback */
00434   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
00435   /* Set the DMA error callback */
00436   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
00437
00438   /* Set the CRYP DMA transfer complete callback */
00439   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
00440   /* Set the DMA error callback */
00441   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
00442
00443   /* Enable CRYP */
00444   __HAL_CRYP_ENABLE(hcryp);
00445
00446   /* Enable the DMA In DMA Stream */
00447   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
00448
00449   /* Enable In DMA request */
00450   hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
00451
00452   /* Enable the DMA Out DMA Stream */
00453   HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
00454
00455   /* Enable Out DMA request */
00456   hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
00457
00458 }
00459
00460 /**
00461   * @brief  Sets the CRYP peripheral in DES ECB mode.
00462   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00463   *         the configuration information for CRYP module
00464   * @param  Direction: Encryption or decryption
00465   * @retval None
00466   */
00467 static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00468 {
00469   /* Check if initialization phase has already been performed */
00470   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00471   {
00472     /* Set the CRYP peripheral in AES ECB mode */
00473     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
00474
00475     /* Set the key */
00476     hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
00477     hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
00478
00479     /* Flush FIFO */
00480     __HAL_CRYP_FIFO_FLUSH(hcryp);
00481
00482     /* Set the phase */
00483     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00484   }
00485 }
00486
00487 /**
00488   * @brief  Sets the CRYP peripheral in DES CBC mode.
00489   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00490   *         the configuration information for CRYP module
00491   * @param  Direction: Encryption or decryption
00492   * @retval None
00493   */
00494 static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00495 {
00496   /* Check if initialization phase has already been performed */
00497   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00498   {
00499     /* Set the CRYP peripheral in AES ECB mode */
00500     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
00501
00502     /* Set the key */
00503     hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
00504     hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
00505
00506     /* Set the Initialization Vector */
00507     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
00508
00509     /* Flush FIFO */
00510     __HAL_CRYP_FIFO_FLUSH(hcryp);
00511
00512     /* Set the phase */
00513     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00514   }
00515 }
00516
00517 /**
00518   * @brief  Sets the CRYP peripheral in TDES ECB mode.
00519   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00520   *         the configuration information for CRYP module
00521   * @param  Direction: Encryption or decryption
00522   * @retval None
00523   */
00524 static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00525 {
00526   /* Check if initialization phase has already been performed */
00527   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00528   {
00529     /* Set the CRYP peripheral in AES ECB mode */
00530     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
00531
00532     /* Set the key */
00533     CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
00534
00535     /* Flush FIFO */
00536     __HAL_CRYP_FIFO_FLUSH(hcryp);
00537
00538     /* Set the phase */
00539     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00540   }
00541 }
00542
00543 /**
00544   * @brief  Sets the CRYP peripheral in TDES CBC mode
00545   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00546   *         the configuration information for CRYP module
00547   * @param  Direction: Encryption or decryption
00548   * @retval None
00549   */
00550 static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00551 {
00552   /* Check if initialization phase has already been performed */
00553   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00554   {
00555     /* Set the CRYP peripheral in AES CBC mode */
00556     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
00557
00558     /* Set the key */
00559     CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
00560
00561     /* Set the Initialization Vector */
00562     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
00563
00564     /* Flush FIFO */
00565     __HAL_CRYP_FIFO_FLUSH(hcryp);
00566
00567     /* Set the phase */
00568     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00569   }
00570 }
00571
00572 /**
00573   * @}
00574   */
00575
00576  /* Exported functions --------------------------------------------------------*/
00577 /** @addtogroup CRYP_Exported_Functions
00578   * @{
00579   */
00580
00581 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00582  *  @brief    Initialization and Configuration functions.
00583  *
00584 @verbatim
00585   ==============================================================================
00586               ##### Initialization and de-initialization functions #####
00587   ==============================================================================
00588     [..]  This section provides functions allowing to:
00589       (+) Initialize the CRYP according to the specified parameters
00590           in the CRYP_InitTypeDef and creates the associated handle
00591       (+) DeInitialize the CRYP peripheral
00592       (+) Initialize the CRYP MSP
00593       (+) DeInitialize CRYP MSP
00594
00595 @endverbatim
00596   * @{
00597   */
00598
00599 /**
00600   * @brief  Initializes the CRYP according to the specified
00601   *         parameters in the CRYP_InitTypeDef and creates the associated handle.
00602   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00603   *         the configuration information for CRYP module
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00607 {
00608   /* Check the CRYP handle allocation */
00609   if(hcryp == NULL)
00610   {
00611     return HAL_ERROR;
00612   }
00613
00614   /* Check the parameters */
00615   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00616   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00617
00618   if(hcryp->State == HAL_CRYP_STATE_RESET)
00619   {
00620     /* Allocate lock resource and initialize it */
00621     hcryp->Lock = HAL_UNLOCKED;
00622     /* Init the low level hardware */
00623     HAL_CRYP_MspInit(hcryp);
00624   }
00625
00626   /* Change the CRYP state */
00627   hcryp->State = HAL_CRYP_STATE_BUSY;
00628
00629   /* Set the key size and data type*/
00630   CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
00631
00632   /* Reset CrypInCount and CrypOutCount */
00633   hcryp->CrypInCount = 0;
00634   hcryp->CrypOutCount = 0;
00635
00636   /* Change the CRYP state */
00637   hcryp->State = HAL_CRYP_STATE_READY;
00638
00639   /* Set the default CRYP phase */
00640   hcryp->Phase = HAL_CRYP_PHASE_READY;
00641
00642   /* Return function status */
00643   return HAL_OK;
00644 }
00645
00646 /**
00647   * @brief  DeInitializes the CRYP peripheral.
00648   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00649   *         the configuration information for CRYP module
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00653 {
00654   /* Check the CRYP handle allocation */
00655   if(hcryp == NULL)
00656   {
00657     return HAL_ERROR;
00658   }
00659
00660   /* Change the CRYP state */
00661   hcryp->State = HAL_CRYP_STATE_BUSY;
00662
00663   /* Set the default CRYP phase */
00664   hcryp->Phase = HAL_CRYP_PHASE_READY;
00665
00666   /* Reset CrypInCount and CrypOutCount */
00667   hcryp->CrypInCount = 0;
00668   hcryp->CrypOutCount = 0;
00669
00670   /* Disable the CRYP Peripheral Clock */
00671   __HAL_CRYP_DISABLE(hcryp);
00672
00673   /* DeInit the low level hardware: CLOCK, NVIC.*/
00674   HAL_CRYP_MspDeInit(hcryp);
00675
00676   /* Change the CRYP state */
00677   hcryp->State = HAL_CRYP_STATE_RESET;
00678
00679   /* Release Lock */
00680   __HAL_UNLOCK(hcryp);
00681
00682   /* Return function status */
00683   return HAL_OK;
00684 }
00685
00686 /**
00687   * @brief  Initializes the CRYP MSP.
00688   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00689   *         the configuration information for CRYP module
00690   * @retval None
00691   */
00692 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00693 {
00694   /* Prevent unused argument(s) compilation warning */
00695   UNUSED(hcryp);
00696
00697   /* NOTE : This function Should not be modified, when the callback is needed,
00698             the HAL_CRYP_MspInit could be implemented in the user file
00699    */
00700 }
00701
00702 /**
00703   * @brief  DeInitializes CRYP MSP.
00704   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00705   *         the configuration information for CRYP module
00706   * @retval None
00707   */
00708 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00709 {
00710   /* Prevent unused argument(s) compilation warning */
00711   UNUSED(hcryp);
00712
00713   /* NOTE : This function Should not be modified, when the callback is needed,
00714             the HAL_CRYP_MspDeInit could be implemented in the user file
00715    */
00716 }
00717
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
00723  *  @brief   processing functions.
00724  *
00725 @verbatim
00726   ==============================================================================
00727                       ##### AES processing functions #####
00728   ==============================================================================
00729     [..]  This section provides functions allowing to:
00730       (+) Encrypt plaintext using AES-128/192/256 using chaining modes
00731       (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
00732     [..]  Three processing functions are available:
00733       (+) Polling mode
00734       (+) Interrupt mode
00735       (+) DMA mode
00736
00737 @endverbatim
00738   * @{
00739   */
00740
00741 /**
00742   * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
00743   *         then encrypt pPlainData. The cypher data are available in pCypherData
00744   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00745   *         the configuration information for CRYP module
00746   * @param  pPlainData: Pointer to the plaintext buffer
00747   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00748   * @param  pCypherData: Pointer to the cyphertext buffer
00749   * @param  Timeout: Specify Timeout value
00750   * @retval HAL status
00751   */
00752 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00753 {
00754   /* Process Locked */
00755   __HAL_LOCK(hcryp);
00756
00757   /* Change the CRYP state */
00758   hcryp->State = HAL_CRYP_STATE_BUSY;
00759
00760   /* Check if initialization phase has already been performed */
00761   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00762   {
00763     /* Set the key */
00764     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00765
00766     /* Set the CRYP peripheral in AES ECB mode */
00767     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
00768
00769     /* Flush FIFO */
00770     __HAL_CRYP_FIFO_FLUSH(hcryp);
00771
00772     /* Enable CRYP */
00773     __HAL_CRYP_ENABLE(hcryp);
00774
00775     /* Set the phase */
00776     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00777   }
00778
00779     /* Write Plain Data and Get Cypher Data */
00780     if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00781     {
00782       return HAL_TIMEOUT;
00783     }
00784
00785   /* Change the CRYP state */
00786   hcryp->State = HAL_CRYP_STATE_READY;
00787
00788   /* Process Unlocked */
00789   __HAL_UNLOCK(hcryp);
00790
00791   /* Return function status */
00792   return HAL_OK;
00793 }
00794
00795 /**
00796   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
00797   *         then encrypt pPlainData. The cypher data are available in pCypherData
00798   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00799   *         the configuration information for CRYP module
00800   * @param  pPlainData: Pointer to the plaintext buffer
00801   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00802   * @param  pCypherData: Pointer to the cyphertext buffer
00803   * @param  Timeout: Specify Timeout value
00804   * @retval HAL status
00805   */
00806 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00807 {
00808   /* Process Locked */
00809   __HAL_LOCK(hcryp);
00810
00811   /* Change the CRYP state */
00812   hcryp->State = HAL_CRYP_STATE_BUSY;
00813
00814   /* Check if initialization phase has already been performed */
00815   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00816   {
00817     /* Set the key */
00818     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00819
00820     /* Set the CRYP peripheral in AES ECB mode */
00821     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
00822
00823     /* Set the Initialization Vector */
00824     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
00825
00826     /* Flush FIFO */
00827     __HAL_CRYP_FIFO_FLUSH(hcryp);
00828
00829     /* Enable CRYP */
00830     __HAL_CRYP_ENABLE(hcryp);
00831
00832     /* Set the phase */
00833     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00834   }
00835
00836     /* Write Plain Data and Get Cypher Data */
00837     if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00838     {
00839       return HAL_TIMEOUT;
00840     }
00841
00842   /* Change the CRYP state */
00843   hcryp->State = HAL_CRYP_STATE_READY;
00844
00845   /* Process Unlocked */
00846   __HAL_UNLOCK(hcryp);
00847
00848   /* Return function status */
00849   return HAL_OK;
00850 }
00851
00852 /**
00853   * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
00854   *         then encrypt pPlainData. The cypher data are available in pCypherData
00855   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00856   *         the configuration information for CRYP module
00857   * @param  pPlainData: Pointer to the plaintext buffer
00858   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00859   * @param  pCypherData: Pointer to the cyphertext buffer
00860   * @param  Timeout: Specify Timeout value
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00864 {
00865   /* Process Locked */
00866   __HAL_LOCK(hcryp);
00867
00868   /* Change the CRYP state */
00869   hcryp->State = HAL_CRYP_STATE_BUSY;
00870
00871   /* Check if initialization phase has already been performed */
00872   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00873   {
00874     /* Set the key */
00875     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00876
00877     /* Set the CRYP peripheral in AES ECB mode */
00878     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
00879
00880     /* Set the Initialization Vector */
00881     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
00882
00883     /* Flush FIFO */
00884     __HAL_CRYP_FIFO_FLUSH(hcryp);
00885
00886     /* Enable CRYP */
00887     __HAL_CRYP_ENABLE(hcryp);
00888
00889     /* Set the phase */
00890     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00891   }
00892
00893     /* Write Plain Data and Get Cypher Data */
00894     if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00895     {
00896       return HAL_TIMEOUT;
00897     }
00898
00899   /* Change the CRYP state */
00900   hcryp->State = HAL_CRYP_STATE_READY;
00901
00902   /* Process Unlocked */
00903   __HAL_UNLOCK(hcryp);
00904
00905   /* Return function status */
00906   return HAL_OK;
00907 }
00908
00909
00910
00911 /**
00912   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
00913   *         then decrypted pCypherData. The cypher data are available in pPlainData
00914   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00915   *         the configuration information for CRYP module
00916   * @param  pCypherData: Pointer to the cyphertext buffer
00917   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00918   * @param  pPlainData: Pointer to the plaintext buffer
00919   * @param  Timeout: Specify Timeout value
00920   * @retval HAL status
00921   */
00922 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00923 {
00924    uint32_t tickstart = 0;
00925
00926   /* Process Locked */
00927   __HAL_LOCK(hcryp);
00928
00929   /* Change the CRYP state */
00930   hcryp->State = HAL_CRYP_STATE_BUSY;
00931
00932   /* Check if initialization phase has already been performed */
00933   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00934   {
00935     /* Set the key */
00936     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00937
00938     /* Set the CRYP peripheral in AES Key mode */
00939     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
00940
00941     /* Enable CRYP */
00942     __HAL_CRYP_ENABLE(hcryp);
00943
00944     /* Get tick */
00945     tickstart = HAL_GetTick();
00946
00947     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
00948     {
00949       /* Check for the Timeout */
00950       if(Timeout != HAL_MAX_DELAY)
00951       {
00952         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00953         {
00954           /* Change state */
00955           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00956
00957           /* Process Unlocked */
00958           __HAL_UNLOCK(hcryp);
00959
00960           return HAL_TIMEOUT;
00961         }
00962       }
00963     }
00964
00965     /* Disable CRYP */
00966     __HAL_CRYP_DISABLE(hcryp);
00967
00968     /* Reset the ALGOMODE bits*/
00969     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
00970
00971     /* Set the CRYP peripheral in AES ECB decryption mode */
00972     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
00973     /* Flush FIFO */
00974     __HAL_CRYP_FIFO_FLUSH(hcryp);
00975
00976     /* Enable CRYP */
00977     __HAL_CRYP_ENABLE(hcryp);
00978
00979     /* Set the phase */
00980     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00981   }
00982
00983     /* Write Plain Data and Get Cypher Data */
00984     if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
00985     {
00986       return HAL_TIMEOUT;
00987     }
00988
00989   /* Change the CRYP state */
00990   hcryp->State = HAL_CRYP_STATE_READY;
00991
00992   /* Process Unlocked */
00993   __HAL_UNLOCK(hcryp);
00994
00995   /* Return function status */
00996   return HAL_OK;
00997 }
00998
00999 /**
01000   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
01001   *         then decrypted pCypherData. The cypher data are available in pPlainData
01002   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01003   *         the configuration information for CRYP module
01004   * @param  pCypherData: Pointer to the cyphertext buffer
01005   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01006   * @param  pPlainData: Pointer to the plaintext buffer
01007   * @param  Timeout: Specify Timeout value
01008   * @retval HAL status
01009   */
01010 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
01011 {
01012   uint32_t tickstart = 0;
01013
01014   /* Process Locked */
01015   __HAL_LOCK(hcryp);
01016
01017   /* Change the CRYP state */
01018   hcryp->State = HAL_CRYP_STATE_BUSY;
01019
01020   /* Check if initialization phase has already been performed */
01021   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01022   {
01023     /* Set the key */
01024     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01025
01026     /* Set the CRYP peripheral in AES Key mode */
01027     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
01028
01029     /* Enable CRYP */
01030     __HAL_CRYP_ENABLE(hcryp);
01031
01032     /* Get tick */
01033     tickstart = HAL_GetTick();
01034
01035     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
01036     {
01037       /* Check for the Timeout */
01038       if(Timeout != HAL_MAX_DELAY)
01039       {
01040         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01041         {
01042           /* Change state */
01043           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01044
01045           /* Process Unlocked */
01046           __HAL_UNLOCK(hcryp);
01047
01048           return HAL_TIMEOUT;
01049         }
01050       }
01051     }
01052
01053     /* Reset the ALGOMODE bits*/
01054     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
01055
01056     /* Set the CRYP peripheral in AES CBC decryption mode */
01057     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
01058
01059     /* Set the Initialization Vector */
01060     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01061
01062     /* Flush FIFO */
01063     __HAL_CRYP_FIFO_FLUSH(hcryp);
01064
01065     /* Enable CRYP */
01066     __HAL_CRYP_ENABLE(hcryp);
01067
01068     /* Set the phase */
01069     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01070   }
01071
01072     /* Write Plain Data and Get Cypher Data */
01073     if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
01074     {
01075       return HAL_TIMEOUT;
01076     }
01077
01078   /* Change the CRYP state */
01079   hcryp->State = HAL_CRYP_STATE_READY;
01080
01081   /* Process Unlocked */
01082   __HAL_UNLOCK(hcryp);
01083
01084   /* Return function status */
01085   return HAL_OK;
01086 }
01087
01088 /**
01089   * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
01090   *         then decrypted pCypherData. The cypher data are available in pPlainData
01091   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01092   *         the configuration information for CRYP module
01093   * @param  pCypherData: Pointer to the cyphertext buffer
01094   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01095   * @param  pPlainData: Pointer to the plaintext buffer
01096   * @param  Timeout: Specify Timeout value
01097   * @retval HAL status
01098   */
01099 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
01100 {
01101   /* Process Locked */
01102   __HAL_LOCK(hcryp);
01103
01104   /* Check if initialization phase has already been performed */
01105   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01106   {
01107     /* Change the CRYP state */
01108     hcryp->State = HAL_CRYP_STATE_BUSY;
01109
01110     /* Set the key */
01111     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01112
01113     /* Set the CRYP peripheral in AES CTR mode */
01114     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
01115
01116     /* Set the Initialization Vector */
01117     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01118
01119     /* Flush FIFO */
01120     __HAL_CRYP_FIFO_FLUSH(hcryp);
01121
01122     /* Enable CRYP */
01123     __HAL_CRYP_ENABLE(hcryp);
01124
01125     /* Set the phase */
01126     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01127   }
01128
01129     /* Write Plain Data and Get Cypher Data */
01130     if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
01131     {
01132       return HAL_TIMEOUT;
01133     }
01134
01135   /* Change the CRYP state */
01136   hcryp->State = HAL_CRYP_STATE_READY;
01137
01138   /* Process Unlocked */
01139   __HAL_UNLOCK(hcryp);
01140
01141   /* Return function status */
01142   return HAL_OK;
01143 }
01144
01145 /**
01146   * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
01147   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01148   *         the configuration information for CRYP module
01149   * @param  pPlainData: Pointer to the plaintext buffer
01150   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01151   * @param  pCypherData: Pointer to the cyphertext buffer
01152   * @retval HAL status
01153   */
01154 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01155 {
01156   uint32_t inputaddr;
01157   uint32_t outputaddr;
01158
01159   if(hcryp->State == HAL_CRYP_STATE_READY)
01160   {
01161     /* Process Locked */
01162     __HAL_LOCK(hcryp);
01163
01164     hcryp->CrypInCount = Size;
01165     hcryp->pCrypInBuffPtr = pPlainData;
01166     hcryp->pCrypOutBuffPtr = pCypherData;
01167     hcryp->CrypOutCount = Size;
01168
01169     /* Change the CRYP state */
01170     hcryp->State = HAL_CRYP_STATE_BUSY;
01171
01172     /* Check if initialization phase has already been performed */
01173     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01174     {
01175       /* Set the key */
01176       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01177
01178       /* Set the CRYP peripheral in AES ECB mode */
01179       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
01180
01181       /* Flush FIFO */
01182       __HAL_CRYP_FIFO_FLUSH(hcryp);
01183
01184      /* Set the phase */
01185      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01186     }
01187
01188     /* Enable Interrupts */
01189     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01190
01191     /* Enable CRYP */
01192     __HAL_CRYP_ENABLE(hcryp);
01193
01194     /* Return function status */
01195     return HAL_OK;
01196   }
01197   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01198   {
01199     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01200     /* Write the Input block in the IN FIFO */
01201     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01202     inputaddr+=4;
01203     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01204     inputaddr+=4;
01205     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01206     inputaddr+=4;
01207     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01208     hcryp->pCrypInBuffPtr += 16;
01209     hcryp->CrypInCount -= 16;
01210     if(hcryp->CrypInCount == 0)
01211     {
01212       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01213       /* Call the Input data transfer complete callback */
01214       HAL_CRYP_InCpltCallback(hcryp);
01215     }
01216   }
01217   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01218   {
01219     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01220     /* Read the Output block from the Output FIFO */
01221     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01222     outputaddr+=4;
01223     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01224     outputaddr+=4;
01225     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01226     outputaddr+=4;
01227     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01228     hcryp->pCrypOutBuffPtr += 16;
01229     hcryp->CrypOutCount -= 16;
01230     if(hcryp->CrypOutCount == 0)
01231     {
01232       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01233       /* Process Locked */
01234       __HAL_UNLOCK(hcryp);
01235       /* Change the CRYP state */
01236       hcryp->State = HAL_CRYP_STATE_READY;
01237       /* Call Input transfer complete callback */
01238       HAL_CRYP_OutCpltCallback(hcryp);
01239     }
01240   }
01241
01242   /* Return function status */
01243   return HAL_OK;
01244 }
01245
01246 /**
01247   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
01248   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01249   *         the configuration information for CRYP module
01250   * @param  pPlainData: Pointer to the plaintext buffer
01251   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01252   * @param  pCypherData: Pointer to the cyphertext buffer
01253   * @retval HAL status
01254   */
01255 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01256 {
01257   uint32_t inputaddr;
01258   uint32_t outputaddr;
01259
01260   if(hcryp->State == HAL_CRYP_STATE_READY)
01261   {
01262     /* Process Locked */
01263     __HAL_LOCK(hcryp);
01264
01265     hcryp->CrypInCount = Size;
01266     hcryp->pCrypInBuffPtr = pPlainData;
01267     hcryp->pCrypOutBuffPtr = pCypherData;
01268     hcryp->CrypOutCount = Size;
01269
01270     /* Change the CRYP state */
01271     hcryp->State = HAL_CRYP_STATE_BUSY;
01272
01273     /* Check if initialization phase has already been performed */
01274     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01275     {
01276       /* Set the key */
01277       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01278
01279       /* Set the CRYP peripheral in AES CBC mode */
01280       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
01281
01282       /* Set the Initialization Vector */
01283       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01284
01285       /* Flush FIFO */
01286       __HAL_CRYP_FIFO_FLUSH(hcryp);
01287
01288      /* Set the phase */
01289      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01290     }
01291     /* Enable Interrupts */
01292     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01293
01294     /* Enable CRYP */
01295     __HAL_CRYP_ENABLE(hcryp);
01296
01297     /* Return function status */
01298     return HAL_OK;
01299   }
01300   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01301   {
01302     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01303     /* Write the Input block in the IN FIFO */
01304     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01305     inputaddr+=4;
01306     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01307     inputaddr+=4;
01308     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01309     inputaddr+=4;
01310     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01311     hcryp->pCrypInBuffPtr += 16;
01312     hcryp->CrypInCount -= 16;
01313     if(hcryp->CrypInCount == 0)
01314     {
01315       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01316       /* Call the Input data transfer complete callback */
01317       HAL_CRYP_InCpltCallback(hcryp);
01318     }
01319   }
01320   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01321   {
01322     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01323     /* Read the Output block from the Output FIFO */
01324     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01325     outputaddr+=4;
01326     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01327     outputaddr+=4;
01328     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01329     outputaddr+=4;
01330     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01331     hcryp->pCrypOutBuffPtr += 16;
01332     hcryp->CrypOutCount -= 16;
01333     if(hcryp->CrypOutCount == 0)
01334     {
01335       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01336       /* Process Locked */
01337       __HAL_UNLOCK(hcryp);
01338       /* Change the CRYP state */
01339       hcryp->State = HAL_CRYP_STATE_READY;
01340       /* Call Input transfer complete callback */
01341       HAL_CRYP_OutCpltCallback(hcryp);
01342     }
01343   }
01344
01345   /* Return function status */
01346   return HAL_OK;
01347 }
01348
01349 /**
01350   * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
01351   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01352   *         the configuration information for CRYP module
01353   * @param  pPlainData: Pointer to the plaintext buffer
01354   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01355   * @param  pCypherData: Pointer to the cyphertext buffer
01356   * @retval HAL status
01357   */
01358 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01359 {
01360   uint32_t inputaddr;
01361   uint32_t outputaddr;
01362
01363   if(hcryp->State == HAL_CRYP_STATE_READY)
01364   {
01365     /* Process Locked */
01366     __HAL_LOCK(hcryp);
01367
01368     hcryp->CrypInCount = Size;
01369     hcryp->pCrypInBuffPtr = pPlainData;
01370     hcryp->pCrypOutBuffPtr = pCypherData;
01371     hcryp->CrypOutCount = Size;
01372
01373     /* Change the CRYP state */
01374     hcryp->State = HAL_CRYP_STATE_BUSY;
01375
01376     /* Check if initialization phase has already been performed */
01377     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01378     {
01379       /* Set the key */
01380       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01381
01382       /* Set the CRYP peripheral in AES CTR mode */
01383       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
01384
01385       /* Set the Initialization Vector */
01386       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01387
01388       /* Flush FIFO */
01389       __HAL_CRYP_FIFO_FLUSH(hcryp);
01390
01391      /* Set the phase */
01392      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01393     }
01394     /* Enable Interrupts */
01395     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01396
01397     /* Enable CRYP */
01398     __HAL_CRYP_ENABLE(hcryp);
01399
01400     /* Return function status */
01401     return HAL_OK;
01402   }
01403   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01404   {
01405     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01406     /* Write the Input block in the IN FIFO */
01407     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01408     inputaddr+=4;
01409     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01410     inputaddr+=4;
01411     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01412     inputaddr+=4;
01413     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01414     hcryp->pCrypInBuffPtr += 16;
01415     hcryp->CrypInCount -= 16;
01416     if(hcryp->CrypInCount == 0)
01417     {
01418       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01419       /* Call the Input data transfer complete callback */
01420       HAL_CRYP_InCpltCallback(hcryp);
01421     }
01422   }
01423   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01424   {
01425     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01426     /* Read the Output block from the Output FIFO */
01427     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01428     outputaddr+=4;
01429     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01430     outputaddr+=4;
01431     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01432     outputaddr+=4;
01433     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01434     hcryp->pCrypOutBuffPtr += 16;
01435     hcryp->CrypOutCount -= 16;
01436     if(hcryp->CrypOutCount == 0)
01437     {
01438       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01439       /* Process Unlocked */
01440       __HAL_UNLOCK(hcryp);
01441       /* Change the CRYP state */
01442       hcryp->State = HAL_CRYP_STATE_READY;
01443       /* Call Input transfer complete callback */
01444       HAL_CRYP_OutCpltCallback(hcryp);
01445     }
01446   }
01447
01448   /* Return function status */
01449   return HAL_OK;
01450 }
01451
01452
01453 /**
01454   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
01455   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01456   *         the configuration information for CRYP module
01457   * @param  pCypherData: Pointer to the cyphertext buffer
01458   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01459   * @param  pPlainData: Pointer to the plaintext buffer
01460   * @retval HAL status
01461   */
01462 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01463 {
01464   uint32_t tickstart = 0;
01465
01466   uint32_t inputaddr;
01467   uint32_t outputaddr;
01468
01469   if(hcryp->State == HAL_CRYP_STATE_READY)
01470   {
01471     /* Process Locked */
01472     __HAL_LOCK(hcryp);
01473
01474     hcryp->CrypInCount = Size;
01475     hcryp->pCrypInBuffPtr = pCypherData;
01476     hcryp->pCrypOutBuffPtr = pPlainData;
01477     hcryp->CrypOutCount = Size;
01478
01479     /* Change the CRYP state */
01480     hcryp->State = HAL_CRYP_STATE_BUSY;
01481
01482   /* Check if initialization phase has already been performed */
01483   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01484   {
01485     /* Set the key */
01486     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01487
01488     /* Set the CRYP peripheral in AES Key mode */
01489     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
01490     /* Enable CRYP */
01491     __HAL_CRYP_ENABLE(hcryp);
01492
01493     /* Get tick */
01494     tickstart = HAL_GetTick();
01495
01496     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
01497     {
01498       /* Check for the Timeout */
01499       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
01500       {
01501         /* Change state */
01502         hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01503
01504         /* Process Unlocked */
01505         __HAL_UNLOCK(hcryp);
01506
01507         return HAL_TIMEOUT;
01508       }
01509     }
01510
01511     /* Reset the ALGOMODE bits*/
01512     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
01513
01514     /* Set the CRYP peripheral in AES ECB decryption mode */
01515     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
01516
01517     /* Flush FIFO */
01518     __HAL_CRYP_FIFO_FLUSH(hcryp);
01519
01520      /* Set the phase */
01521      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01522   }
01523
01524     /* Enable Interrupts */
01525     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01526
01527     /* Enable CRYP */
01528     __HAL_CRYP_ENABLE(hcryp);
01529
01530     /* Return function status */
01531     return HAL_OK;
01532   }
01533   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01534   {
01535     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01536     /* Write the Input block in the IN FIFO */
01537     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01538     inputaddr+=4;
01539     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01540     inputaddr+=4;
01541     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01542     inputaddr+=4;
01543     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01544     hcryp->pCrypInBuffPtr += 16;
01545     hcryp->CrypInCount -= 16;
01546     if(hcryp->CrypInCount == 0)
01547     {
01548       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01549       /* Call the Input data transfer complete callback */
01550       HAL_CRYP_InCpltCallback(hcryp);
01551     }
01552   }
01553   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01554   {
01555     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01556     /* Read the Output block from the Output FIFO */
01557     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01558     outputaddr+=4;
01559     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01560     outputaddr+=4;
01561     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01562     outputaddr+=4;
01563     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01564     hcryp->pCrypOutBuffPtr += 16;
01565     hcryp->CrypOutCount -= 16;
01566     if(hcryp->CrypOutCount == 0)
01567     {
01568       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01569       /* Process Unlocked */
01570       __HAL_UNLOCK(hcryp);
01571       /* Change the CRYP state */
01572       hcryp->State = HAL_CRYP_STATE_READY;
01573       /* Call Input transfer complete callback */
01574       HAL_CRYP_OutCpltCallback(hcryp);
01575     }
01576   }
01577
01578   /* Return function status */
01579   return HAL_OK;
01580 }
01581
01582 /**
01583   * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
01584   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01585   *         the configuration information for CRYP module
01586   * @param  pCypherData: Pointer to the cyphertext buffer
01587   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01588   * @param  pPlainData: Pointer to the plaintext buffer
01589   * @retval HAL status
01590   */
01591 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01592 {
01593
01594   uint32_t tickstart = 0;
01595   uint32_t inputaddr;
01596   uint32_t outputaddr;
01597
01598   if(hcryp->State == HAL_CRYP_STATE_READY)
01599   {
01600     /* Process Locked */
01601     __HAL_LOCK(hcryp);
01602
01603     /* Get the buffer addresses and sizes */
01604     hcryp->CrypInCount = Size;
01605     hcryp->pCrypInBuffPtr = pCypherData;
01606     hcryp->pCrypOutBuffPtr = pPlainData;
01607     hcryp->CrypOutCount = Size;
01608
01609     /* Change the CRYP state */
01610     hcryp->State = HAL_CRYP_STATE_BUSY;
01611
01612     /* Check if initialization phase has already been performed */
01613     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01614     {
01615       /* Set the key */
01616       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01617
01618       /* Set the CRYP peripheral in AES Key mode */
01619       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
01620
01621       /* Enable CRYP */
01622       __HAL_CRYP_ENABLE(hcryp);
01623
01624     /* Get tick */
01625     tickstart = HAL_GetTick();
01626
01627     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
01628     {
01629       /* Check for the Timeout */
01630       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
01631       {
01632         /* Change state */
01633         hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01634
01635         /* Process Unlocked */
01636         __HAL_UNLOCK(hcryp);
01637
01638         return HAL_TIMEOUT;
01639       }
01640     }
01641
01642       /* Reset the ALGOMODE bits*/
01643       CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
01644
01645       /* Set the CRYP peripheral in AES CBC decryption mode */
01646       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
01647
01648       /* Set the Initialization Vector */
01649       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01650
01651       /* Flush FIFO */
01652       __HAL_CRYP_FIFO_FLUSH(hcryp);
01653
01654       /* Enable CRYP */
01655       __HAL_CRYP_ENABLE(hcryp);
01656
01657       /* Set the phase */
01658       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01659     }
01660
01661     /* Enable Interrupts */
01662     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01663
01664     /* Enable CRYP */
01665     __HAL_CRYP_ENABLE(hcryp);
01666
01667     /* Return function status */
01668     return HAL_OK;
01669   }
01670   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01671   {
01672     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01673     /* Write the Input block in the IN FIFO */
01674     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01675     inputaddr+=4;
01676     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01677     inputaddr+=4;
01678     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01679     inputaddr+=4;
01680     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01681     hcryp->pCrypInBuffPtr += 16;
01682     hcryp->CrypInCount -= 16;
01683     if(hcryp->CrypInCount == 0)
01684     {
01685       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01686       /* Call the Input data transfer complete callback */
01687       HAL_CRYP_InCpltCallback(hcryp);
01688     }
01689   }
01690   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01691   {
01692     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01693     /* Read the Output block from the Output FIFO */
01694     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01695     outputaddr+=4;
01696     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01697     outputaddr+=4;
01698     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01699     outputaddr+=4;
01700     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01701     hcryp->pCrypOutBuffPtr += 16;
01702     hcryp->CrypOutCount -= 16;
01703     if(hcryp->CrypOutCount == 0)
01704     {
01705       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01706       /* Process Unlocked */
01707       __HAL_UNLOCK(hcryp);
01708       /* Change the CRYP state */
01709       hcryp->State = HAL_CRYP_STATE_READY;
01710       /* Call Input transfer complete callback */
01711       HAL_CRYP_OutCpltCallback(hcryp);
01712     }
01713   }
01714
01715   /* Return function status */
01716   return HAL_OK;
01717 }
01718
01719 /**
01720   * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
01721   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01722   *         the configuration information for CRYP module
01723   * @param  pCypherData: Pointer to the cyphertext buffer
01724   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01725   * @param  pPlainData: Pointer to the plaintext buffer
01726   * @retval HAL status
01727   */
01728 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01729 {
01730   uint32_t inputaddr;
01731   uint32_t outputaddr;
01732
01733   if(hcryp->State == HAL_CRYP_STATE_READY)
01734   {
01735     /* Process Locked */
01736     __HAL_LOCK(hcryp);
01737
01738     /* Get the buffer addresses and sizes */
01739     hcryp->CrypInCount = Size;
01740     hcryp->pCrypInBuffPtr = pCypherData;
01741     hcryp->pCrypOutBuffPtr = pPlainData;
01742     hcryp->CrypOutCount = Size;
01743
01744     /* Change the CRYP state */
01745     hcryp->State = HAL_CRYP_STATE_BUSY;
01746
01747     /* Check if initialization phase has already been performed */
01748     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01749     {
01750       /* Set the key */
01751       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01752
01753       /* Set the CRYP peripheral in AES CTR mode */
01754       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
01755
01756       /* Set the Initialization Vector */
01757       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01758
01759       /* Flush FIFO */
01760       __HAL_CRYP_FIFO_FLUSH(hcryp);
01761
01762       /* Set the phase */
01763       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01764     }
01765
01766     /* Enable Interrupts */
01767     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01768
01769     /* Enable CRYP */
01770     __HAL_CRYP_ENABLE(hcryp);
01771
01772     /* Return function status */
01773     return HAL_OK;
01774   }
01775   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01776   {
01777     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01778     /* Write the Input block in the IN FIFO */
01779     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01780     inputaddr+=4;
01781     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01782     inputaddr+=4;
01783     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01784     inputaddr+=4;
01785     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01786     hcryp->pCrypInBuffPtr += 16;
01787     hcryp->CrypInCount -= 16;
01788     if(hcryp->CrypInCount == 0)
01789     {
01790       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01791       /* Call the Input data transfer complete callback */
01792       HAL_CRYP_InCpltCallback(hcryp);
01793     }
01794   }
01795   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01796   {
01797     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01798     /* Read the Output block from the Output FIFO */
01799     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01800     outputaddr+=4;
01801     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01802     outputaddr+=4;
01803     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01804     outputaddr+=4;
01805     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01806     hcryp->pCrypOutBuffPtr += 16;
01807     hcryp->CrypOutCount -= 16;
01808     if(hcryp->CrypOutCount == 0)
01809     {
01810       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01811       /* Process Unlocked */
01812       __HAL_UNLOCK(hcryp);
01813       /* Change the CRYP state */
01814       hcryp->State = HAL_CRYP_STATE_READY;
01815       /* Call Input transfer complete callback */
01816       HAL_CRYP_OutCpltCallback(hcryp);
01817     }
01818   }
01819
01820   /* Return function status */
01821   return HAL_OK;
01822 }
01823
01824 /**
01825   * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
01826   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01827   *         the configuration information for CRYP module
01828   * @param  pPlainData: Pointer to the plaintext buffer
01829   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01830   * @param  pCypherData: Pointer to the cyphertext buffer
01831   * @retval HAL status
01832   */
01833 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01834 {
01835   uint32_t inputaddr;
01836   uint32_t outputaddr;
01837
01838   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
01839   {
01840     /* Process Locked */
01841     __HAL_LOCK(hcryp);
01842
01843     inputaddr  = (uint32_t)pPlainData;
01844     outputaddr = (uint32_t)pCypherData;
01845
01846     /* Change the CRYP state */
01847     hcryp->State = HAL_CRYP_STATE_BUSY;
01848
01849     /* Check if initialization phase has already been performed */
01850     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01851     {
01852       /* Set the key */
01853       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01854
01855       /* Set the CRYP peripheral in AES ECB mode */
01856       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
01857
01858       /* Flush FIFO */
01859       __HAL_CRYP_FIFO_FLUSH(hcryp);
01860
01861      /* Set the phase */
01862      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01863     }
01864     /* Set the input and output addresses and start DMA transfer */
01865     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01866
01867     /* Process Unlocked */
01868     __HAL_UNLOCK(hcryp);
01869
01870     /* Return function status */
01871     return HAL_OK;
01872   }
01873   else
01874   {
01875     return HAL_ERROR;
01876   }
01877 }
01878
01879 /**
01880   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
01881   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01882   *         the configuration information for CRYP module
01883   * @param  pPlainData: Pointer to the plaintext buffer
01884   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01885   * @param  pCypherData: Pointer to the cyphertext buffer
01886   * @retval HAL status
01887   */
01888 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01889 {
01890   uint32_t inputaddr;
01891   uint32_t outputaddr;
01892
01893   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
01894   {
01895     /* Process Locked */
01896     __HAL_LOCK(hcryp);
01897
01898     inputaddr  = (uint32_t)pPlainData;
01899     outputaddr = (uint32_t)pCypherData;
01900
01901     /* Change the CRYP state */
01902     hcryp->State = HAL_CRYP_STATE_BUSY;
01903
01904     /* Check if initialization phase has already been performed */
01905     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01906     {
01907       /* Set the key */
01908       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01909
01910       /* Set the CRYP peripheral in AES ECB mode */
01911       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
01912
01913       /* Set the Initialization Vector */
01914       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01915
01916       /* Flush FIFO */
01917       __HAL_CRYP_FIFO_FLUSH(hcryp);
01918
01919        /* Set the phase */
01920        hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01921      }
01922      /* Set the input and output addresses and start DMA transfer */
01923      CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01924
01925      /* Process Unlocked */
01926      __HAL_UNLOCK(hcryp);
01927
01928      /* Return function status */
01929      return HAL_OK;
01930   }
01931   else
01932   {
01933     return HAL_ERROR;
01934   }
01935 }
01936
01937 /**
01938   * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
01939   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01940   *         the configuration information for CRYP module
01941   * @param  pPlainData: Pointer to the plaintext buffer
01942   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01943   * @param  pCypherData: Pointer to the cyphertext buffer
01944   * @retval HAL status
01945   */
01946 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01947 {
01948   uint32_t inputaddr;
01949   uint32_t outputaddr;
01950
01951   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
01952   {
01953     /* Process Locked */
01954     __HAL_LOCK(hcryp);
01955
01956     inputaddr  = (uint32_t)pPlainData;
01957     outputaddr = (uint32_t)pCypherData;
01958
01959   /* Change the CRYP state */
01960   hcryp->State = HAL_CRYP_STATE_BUSY;
01961
01962     /* Check if initialization phase has already been performed */
01963     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01964     {
01965       /* Set the key */
01966       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01967
01968       /* Set the CRYP peripheral in AES ECB mode */
01969       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
01970
01971       /* Set the Initialization Vector */
01972       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01973
01974       /* Flush FIFO */
01975       __HAL_CRYP_FIFO_FLUSH(hcryp);
01976
01977        /* Set the phase */
01978        hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01979     }
01980
01981     /* Set the input and output addresses and start DMA transfer */
01982     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01983
01984     /* Process Unlocked */
01985     __HAL_UNLOCK(hcryp);
01986
01987     /* Return function status */
01988     return HAL_OK;
01989   }
01990   else
01991   {
01992     return HAL_ERROR;
01993   }
01994 }
01995
01996 /**
01997   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
01998   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01999   *         the configuration information for CRYP module
02000   * @param  pCypherData: Pointer to the cyphertext buffer
02001   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
02002   * @param  pPlainData: Pointer to the plaintext buffer
02003   * @retval HAL status
02004   */
02005 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02006 {
02007   uint32_t tickstart = 0;
02008   uint32_t inputaddr;
02009   uint32_t outputaddr;
02010
02011   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02012   {
02013     /* Process Locked */
02014     __HAL_LOCK(hcryp);
02015
02016     inputaddr  = (uint32_t)pCypherData;
02017     outputaddr = (uint32_t)pPlainData;
02018
02019     /* Change the CRYP state */
02020     hcryp->State = HAL_CRYP_STATE_BUSY;
02021
02022     /* Check if initialization phase has already been performed */
02023     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02024     {
02025     /* Set the key */
02026     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02027
02028     /* Set the CRYP peripheral in AES Key mode */
02029     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
02030
02031     /* Enable CRYP */
02032     __HAL_CRYP_ENABLE(hcryp);
02033
02034     /* Get tick */
02035     tickstart = HAL_GetTick();
02036
02037     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
02038     {
02039       /* Check for the Timeout */
02040       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
02041       {
02042         /* Change state */
02043         hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02044
02045         /* Process Unlocked */
02046         __HAL_UNLOCK(hcryp);
02047
02048         return HAL_TIMEOUT;
02049       }
02050     }
02051
02052     /* Reset the ALGOMODE bits*/
02053     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
02054
02055     /* Set the CRYP peripheral in AES ECB decryption mode */
02056     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
02057
02058     /* Flush FIFO */
02059     __HAL_CRYP_FIFO_FLUSH(hcryp);
02060
02061      /* Set the phase */
02062      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02063     }
02064
02065     /* Set the input and output addresses and start DMA transfer */
02066     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02067
02068      /* Process Unlocked */
02069      __HAL_UNLOCK(hcryp);
02070
02071     /* Return function status */
02072     return HAL_OK;
02073   }
02074   else
02075   {
02076     return HAL_ERROR;
02077   }
02078 }
02079
02080 /**
02081   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
02082   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02083   *         the configuration information for CRYP module
02084   * @param  pCypherData: Pointer to the cyphertext buffer
02085   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
02086   * @param  pPlainData: Pointer to the plaintext buffer
02087   * @retval HAL status
02088   */
02089 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02090 {
02091   uint32_t tickstart = 0;
02092   uint32_t inputaddr;
02093   uint32_t outputaddr;
02094
02095   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02096   {
02097     /* Process Locked */
02098     __HAL_LOCK(hcryp);
02099
02100     inputaddr  = (uint32_t)pCypherData;
02101     outputaddr = (uint32_t)pPlainData;
02102
02103     /* Change the CRYP state */
02104     hcryp->State = HAL_CRYP_STATE_BUSY;
02105
02106     /* Check if initialization phase has already been performed */
02107     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02108     {
02109       /* Set the key */
02110       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02111
02112       /* Set the CRYP peripheral in AES Key mode */
02113       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
02114
02115       /* Enable CRYP */
02116       __HAL_CRYP_ENABLE(hcryp);
02117
02118       /* Get tick */
02119       tickstart = HAL_GetTick();
02120
02121       while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
02122       {
02123         /* Check for the Timeout */
02124         if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
02125         {
02126           /* Change state */
02127           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02128
02129           /* Process Unlocked */
02130           __HAL_UNLOCK(hcryp);
02131
02132           return HAL_TIMEOUT;
02133         }
02134       }
02135
02136       /* Reset the ALGOMODE bits*/
02137       CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
02138
02139       /* Set the CRYP peripheral in AES CBC decryption mode */
02140       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
02141
02142       /* Set the Initialization Vector */
02143       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
02144
02145       /* Flush FIFO */
02146       __HAL_CRYP_FIFO_FLUSH(hcryp);
02147
02148       /* Set the phase */
02149       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02150     }
02151
02152     /* Set the input and output addresses and start DMA transfer */
02153     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02154
02155     /* Process Unlocked */
02156     __HAL_UNLOCK(hcryp);
02157
02158     /* Return function status */
02159     return HAL_OK;
02160   }
02161   else
02162   {
02163     return HAL_ERROR;
02164   }
02165 }
02166
02167 /**
02168   * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
02169   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02170   *         the configuration information for CRYP module
02171   * @param  pCypherData: Pointer to the cyphertext buffer
02172   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02173   * @param  pPlainData: Pointer to the plaintext buffer
02174   * @retval HAL status
02175   */
02176 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02177 {
02178   uint32_t inputaddr;
02179   uint32_t outputaddr;
02180
02181   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02182   {
02183     /* Process Locked */
02184     __HAL_LOCK(hcryp);
02185
02186     inputaddr  = (uint32_t)pCypherData;
02187     outputaddr = (uint32_t)pPlainData;
02188
02189     /* Change the CRYP state */
02190     hcryp->State = HAL_CRYP_STATE_BUSY;
02191
02192     /* Check if initialization phase has already been performed */
02193     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02194     {
02195       /* Set the key */
02196       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02197
02198       /* Set the CRYP peripheral in AES CTR mode */
02199       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
02200
02201       /* Set the Initialization Vector */
02202       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
02203
02204       /* Flush FIFO */
02205       __HAL_CRYP_FIFO_FLUSH(hcryp);
02206
02207       /* Set the phase */
02208       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02209     }
02210
02211     /* Set the input and output addresses and start DMA transfer */
02212     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02213
02214     /* Process Unlocked */
02215     __HAL_UNLOCK(hcryp);
02216
02217     /* Return function status */
02218     return HAL_OK;
02219   }
02220   else
02221   {
02222     return HAL_ERROR;
02223   }
02224 }
02225
02226
02227 /**
02228   * @}
02229   */
02230
02231 /** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
02232  *  @brief   processing functions.
02233  *
02234 @verbatim
02235   ==============================================================================
02236                       ##### DES processing functions #####
02237   ==============================================================================
02238     [..]  This section provides functions allowing to:
02239       (+) Encrypt plaintext using DES using ECB or CBC chaining modes
02240       (+) Decrypt cyphertext using ECB or CBC chaining modes
02241     [..]  Three processing functions are available:
02242       (+) Polling mode
02243       (+) Interrupt mode
02244       (+) DMA mode
02245
02246 @endverbatim
02247   * @{
02248   */
02249
02250 /**
02251   * @brief  Initializes the CRYP peripheral in DES ECB encryption mode.
02252   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02253   *         the configuration information for CRYP module
02254   * @param  pPlainData: Pointer to the plaintext buffer
02255   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02256   * @param  pCypherData: Pointer to the cyphertext buffer
02257   * @param  Timeout: Specify Timeout value
02258   * @retval HAL status
02259   */
02260 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
02261 {
02262   /* Process Locked */
02263   __HAL_LOCK(hcryp);
02264
02265   /* Change the CRYP state */
02266   hcryp->State = HAL_CRYP_STATE_BUSY;
02267
02268   /* Set CRYP peripheral in DES ECB encryption mode */
02269   CRYP_SetDESECBMode(hcryp, 0);
02270
02271   /* Enable CRYP */
02272   __HAL_CRYP_ENABLE(hcryp);
02273
02274   /* Write Plain Data and Get Cypher Data */
02275   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
02276   {
02277     return HAL_TIMEOUT;
02278   }
02279
02280   /* Change the CRYP state */
02281   hcryp->State = HAL_CRYP_STATE_READY;
02282
02283   /* Process Unlocked */
02284   __HAL_UNLOCK(hcryp);
02285
02286   /* Return function status */
02287   return HAL_OK;
02288 }
02289
02290 /**
02291   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
02292   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02293   *         the configuration information for CRYP module
02294   * @param  pCypherData: Pointer to the cyphertext buffer
02295   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02296   * @param  pPlainData: Pointer to the plaintext buffer
02297   * @param  Timeout: Specify Timeout value
02298   * @retval HAL status
02299   */
02300 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
02301 {
02302   /* Process Locked */
02303   __HAL_LOCK(hcryp);
02304
02305   /* Change the CRYP state */
02306   hcryp->State = HAL_CRYP_STATE_BUSY;
02307
02308   /* Set CRYP peripheral in DES ECB decryption mode */
02309   CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
02310
02311   /* Enable CRYP */
02312   __HAL_CRYP_ENABLE(hcryp);
02313
02314   /* Write Plain Data and Get Cypher Data */
02315   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
02316   {
02317     return HAL_TIMEOUT;
02318   }
02319
02320   /* Change the CRYP state */
02321   hcryp->State = HAL_CRYP_STATE_READY;
02322
02323   /* Process Unlocked */
02324   __HAL_UNLOCK(hcryp);
02325
02326   /* Return function status */
02327   return HAL_OK;
02328 }
02329
02330 /**
02331   * @brief  Initializes the CRYP peripheral in DES CBC encryption mode.
02332   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02333   *         the configuration information for CRYP module
02334   * @param  pPlainData: Pointer to the plaintext buffer
02335   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02336   * @param  pCypherData: Pointer to the cyphertext buffer
02337   * @param  Timeout: Specify Timeout value
02338   * @retval HAL status
02339   */
02340 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
02341 {
02342   /* Process Locked */
02343   __HAL_LOCK(hcryp);
02344
02345   /* Change the CRYP state */
02346   hcryp->State = HAL_CRYP_STATE_BUSY;
02347
02348   /* Set CRYP peripheral in DES CBC encryption mode */
02349   CRYP_SetDESCBCMode(hcryp, 0);
02350
02351   /* Enable CRYP */
02352   __HAL_CRYP_ENABLE(hcryp);
02353
02354   /* Write Plain Data and Get Cypher Data */
02355   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
02356   {
02357     return HAL_TIMEOUT;
02358   }
02359
02360   /* Change the CRYP state */
02361   hcryp->State = HAL_CRYP_STATE_READY;
02362
02363   /* Process Unlocked */
02364   __HAL_UNLOCK(hcryp);
02365
02366   /* Return function status */
02367   return HAL_OK;
02368 }
02369
02370 /**
02371   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
02372   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02373   *         the configuration information for CRYP module
02374   * @param  pCypherData: Pointer to the cyphertext buffer
02375   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02376   * @param  pPlainData: Pointer to the plaintext buffer
02377   * @param  Timeout: Specify Timeout value
02378   * @retval HAL status
02379   */
02380 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
02381 {
02382   /* Process Locked */
02383   __HAL_LOCK(hcryp);
02384
02385   /* Change the CRYP state */
02386   hcryp->State = HAL_CRYP_STATE_BUSY;
02387
02388   /* Set CRYP peripheral in DES CBC decryption mode */
02389   CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
02390
02391   /* Enable CRYP */
02392   __HAL_CRYP_ENABLE(hcryp);
02393
02394   /* Write Plain Data and Get Cypher Data */
02395   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
02396   {
02397     return HAL_TIMEOUT;
02398   }
02399
02400   /* Change the CRYP state */
02401   hcryp->State = HAL_CRYP_STATE_READY;
02402
02403   /* Process Unlocked */
02404   __HAL_UNLOCK(hcryp);
02405
02406   /* Return function status */
02407   return HAL_OK;
02408 }
02409
02410 /**
02411   * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using IT.
02412   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02413   *         the configuration information for CRYP module
02414   * @param  pPlainData: Pointer to the plaintext buffer
02415   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02416   * @param  pCypherData: Pointer to the cyphertext buffer
02417   * @retval HAL status
02418   */
02419 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02420 {
02421   uint32_t inputaddr;
02422   uint32_t outputaddr;
02423
02424   if(hcryp->State == HAL_CRYP_STATE_READY)
02425   {
02426     /* Process Locked */
02427     __HAL_LOCK(hcryp);
02428
02429     hcryp->CrypInCount = Size;
02430     hcryp->pCrypInBuffPtr = pPlainData;
02431     hcryp->pCrypOutBuffPtr = pCypherData;
02432     hcryp->CrypOutCount = Size;
02433
02434     /* Change the CRYP state */
02435     hcryp->State = HAL_CRYP_STATE_BUSY;
02436
02437     /* Set CRYP peripheral in DES ECB encryption mode */
02438     CRYP_SetDESECBMode(hcryp, 0);
02439
02440     /* Enable Interrupts */
02441     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02442
02443     /* Enable CRYP */
02444     __HAL_CRYP_ENABLE(hcryp);
02445
02446     /* Return function status */
02447     return HAL_OK;
02448   }
02449   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02450   {
02451     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02452     /* Write the Input block in the IN FIFO */
02453     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02454     inputaddr+=4;
02455     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02456
02457     hcryp->pCrypInBuffPtr += 8;
02458     hcryp->CrypInCount -= 8;
02459     if(hcryp->CrypInCount == 0)
02460     {
02461       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02462       /* Call the Input data transfer complete callback */
02463       HAL_CRYP_InCpltCallback(hcryp);
02464     }
02465   }
02466   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02467   {
02468     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02469     /* Read the Output block from the Output FIFO */
02470     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02471     outputaddr+=4;
02472     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02473
02474     hcryp->pCrypOutBuffPtr += 8;
02475     hcryp->CrypOutCount -= 8;
02476     if(hcryp->CrypOutCount == 0)
02477     {
02478       /* Disable IT */
02479       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02480       /* Disable CRYP */
02481       __HAL_CRYP_DISABLE(hcryp);
02482       /* Process Unlocked */
02483       __HAL_UNLOCK(hcryp);
02484       /* Change the CRYP state */
02485       hcryp->State = HAL_CRYP_STATE_READY;
02486       /* Call Input transfer complete callback */
02487       HAL_CRYP_OutCpltCallback(hcryp);
02488     }
02489   }
02490
02491   /* Return function status */
02492   return HAL_OK;
02493 }
02494
02495 /**
02496   * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
02497   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02498   *         the configuration information for CRYP module
02499   * @param  pPlainData: Pointer to the plaintext buffer
02500   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02501   * @param  pCypherData: Pointer to the cyphertext buffer
02502   * @retval HAL status
02503   */
02504 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02505 {
02506   uint32_t inputaddr;
02507   uint32_t outputaddr;
02508
02509   if(hcryp->State == HAL_CRYP_STATE_READY)
02510   {
02511     /* Process Locked */
02512     __HAL_LOCK(hcryp);
02513
02514     hcryp->CrypInCount = Size;
02515     hcryp->pCrypInBuffPtr = pPlainData;
02516     hcryp->pCrypOutBuffPtr = pCypherData;
02517     hcryp->CrypOutCount = Size;
02518
02519     /* Change the CRYP state */
02520     hcryp->State = HAL_CRYP_STATE_BUSY;
02521
02522     /* Set CRYP peripheral in DES CBC encryption mode */
02523     CRYP_SetDESCBCMode(hcryp, 0);
02524
02525     /* Enable Interrupts */
02526     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02527
02528     /* Enable CRYP */
02529     __HAL_CRYP_ENABLE(hcryp);
02530
02531     /* Return function status */
02532     return HAL_OK;
02533   }
02534
02535   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02536   {
02537     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02538     /* Write the Input block in the IN FIFO */
02539     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02540     inputaddr+=4;
02541     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02542
02543     hcryp->pCrypInBuffPtr += 8;
02544     hcryp->CrypInCount -= 8;
02545     if(hcryp->CrypInCount == 0)
02546     {
02547       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02548       /* Call the Input data transfer complete callback */
02549       HAL_CRYP_InCpltCallback(hcryp);
02550     }
02551   }
02552   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02553   {
02554     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02555     /* Read the Output block from the Output FIFO */
02556     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02557     outputaddr+=4;
02558     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02559
02560     hcryp->pCrypOutBuffPtr += 8;
02561     hcryp->CrypOutCount -= 8;
02562     if(hcryp->CrypOutCount == 0)
02563     {
02564       /* Disable IT */
02565       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02566       /* Disable CRYP */
02567       __HAL_CRYP_DISABLE(hcryp);
02568       /* Process Unlocked */
02569       __HAL_UNLOCK(hcryp);
02570       /* Change the CRYP state */
02571       hcryp->State = HAL_CRYP_STATE_READY;
02572       /* Call Input transfer complete callback */
02573       HAL_CRYP_OutCpltCallback(hcryp);
02574     }
02575   }
02576
02577   /* Return function status */
02578   return HAL_OK;
02579 }
02580
02581 /**
02582   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using IT.
02583   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02584   *         the configuration information for CRYP module
02585   * @param  pPlainData: Pointer to the plaintext buffer
02586   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02587   * @param  pCypherData: Pointer to the cyphertext buffer
02588   * @retval HAL status
02589   */
02590 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02591 {
02592   uint32_t inputaddr;
02593   uint32_t outputaddr;
02594
02595   if(hcryp->State == HAL_CRYP_STATE_READY)
02596   {
02597     /* Process Locked */
02598     __HAL_LOCK(hcryp);
02599
02600     hcryp->CrypInCount = Size;
02601     hcryp->pCrypInBuffPtr = pCypherData;
02602     hcryp->pCrypOutBuffPtr = pPlainData;
02603     hcryp->CrypOutCount = Size;
02604
02605     /* Change the CRYP state */
02606     hcryp->State = HAL_CRYP_STATE_BUSY;
02607
02608     /* Set CRYP peripheral in DES ECB decryption mode */
02609     CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
02610
02611     /* Enable Interrupts */
02612     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02613
02614     /* Enable CRYP */
02615     __HAL_CRYP_ENABLE(hcryp);
02616
02617     /* Return function status */
02618     return HAL_OK;
02619   }
02620   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02621   {
02622     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02623     /* Write the Input block in the IN FIFO */
02624     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02625     inputaddr+=4;
02626     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02627
02628     hcryp->pCrypInBuffPtr += 8;
02629     hcryp->CrypInCount -= 8;
02630     if(hcryp->CrypInCount == 0)
02631     {
02632       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02633       /* Call the Input data transfer complete callback */
02634       HAL_CRYP_InCpltCallback(hcryp);
02635     }
02636   }
02637   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02638   {
02639     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02640     /* Read the Output block from the Output FIFO */
02641     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02642     outputaddr+=4;
02643     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02644
02645     hcryp->pCrypOutBuffPtr += 8;
02646     hcryp->CrypOutCount -= 8;
02647     if(hcryp->CrypOutCount == 0)
02648     {
02649       /* Disable IT */
02650       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02651       /* Disable CRYP */
02652       __HAL_CRYP_DISABLE(hcryp);
02653       /* Process Unlocked */
02654       __HAL_UNLOCK(hcryp);
02655       /* Change the CRYP state */
02656       hcryp->State = HAL_CRYP_STATE_READY;
02657       /* Call Input transfer complete callback */
02658       HAL_CRYP_OutCpltCallback(hcryp);
02659     }
02660   }
02661
02662   /* Return function status */
02663   return HAL_OK;
02664 }
02665
02666 /**
02667   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
02668   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02669   *         the configuration information for CRYP module
02670   * @param  pPlainData: Pointer to the plaintext buffer
02671   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02672   * @param  pCypherData: Pointer to the cyphertext buffer
02673   * @retval HAL status
02674   */
02675 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02676 {
02677   uint32_t inputaddr;
02678   uint32_t outputaddr;
02679
02680   if(hcryp->State == HAL_CRYP_STATE_READY)
02681   {
02682     /* Process Locked */
02683     __HAL_LOCK(hcryp);
02684
02685     hcryp->CrypInCount = Size;
02686     hcryp->pCrypInBuffPtr = pCypherData;
02687     hcryp->pCrypOutBuffPtr = pPlainData;
02688     hcryp->CrypOutCount = Size;
02689
02690     /* Change the CRYP state */
02691     hcryp->State = HAL_CRYP_STATE_BUSY;
02692
02693     /* Set CRYP peripheral in DES CBC decryption mode */
02694     CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
02695
02696     /* Enable Interrupts */
02697     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02698
02699     /* Enable CRYP */
02700     __HAL_CRYP_ENABLE(hcryp);
02701
02702     /* Return function status */
02703     return HAL_OK;
02704   }
02705   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02706   {
02707     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02708     /* Write the Input block in the IN FIFO */
02709     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02710     inputaddr+=4;
02711     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02712
02713     hcryp->pCrypInBuffPtr += 8;
02714     hcryp->CrypInCount -= 8;
02715     if(hcryp->CrypInCount == 0)
02716     {
02717       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02718       /* Call the Input data transfer complete callback */
02719       HAL_CRYP_InCpltCallback(hcryp);
02720     }
02721   }
02722   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02723   {
02724     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02725     /* Read the Output block from the Output FIFO */
02726     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02727     outputaddr+=4;
02728     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02729
02730     hcryp->pCrypOutBuffPtr += 8;
02731     hcryp->CrypOutCount -= 8;
02732     if(hcryp->CrypOutCount == 0)
02733     {
02734       /* Disable IT */
02735       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02736       /* Disable CRYP */
02737       __HAL_CRYP_DISABLE(hcryp);
02738       /* Process Unlocked */
02739       __HAL_UNLOCK(hcryp);
02740       /* Change the CRYP state */
02741       hcryp->State = HAL_CRYP_STATE_READY;
02742       /* Call Input transfer complete callback */
02743       HAL_CRYP_OutCpltCallback(hcryp);
02744     }
02745   }
02746
02747   /* Return function status */
02748   return HAL_OK;
02749 }
02750
02751 /**
02752   * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
02753   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02754   *         the configuration information for CRYP module
02755   * @param  pPlainData: Pointer to the plaintext buffer
02756   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02757   * @param  pCypherData: Pointer to the cyphertext buffer
02758   * @retval HAL status
02759   */
02760 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02761 {
02762   uint32_t inputaddr;
02763   uint32_t outputaddr;
02764
02765   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02766   {
02767     /* Process Locked */
02768     __HAL_LOCK(hcryp);
02769
02770     inputaddr  = (uint32_t)pPlainData;
02771     outputaddr = (uint32_t)pCypherData;
02772
02773     /* Change the CRYP state */
02774     hcryp->State = HAL_CRYP_STATE_BUSY;
02775
02776     /* Set CRYP peripheral in DES ECB encryption mode */
02777     CRYP_SetDESECBMode(hcryp, 0);
02778
02779     /* Set the input and output addresses and start DMA transfer */
02780     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02781
02782     /* Process Unlocked */
02783     __HAL_UNLOCK(hcryp);
02784
02785     /* Return function status */
02786     return HAL_OK;
02787   }
02788   else
02789   {
02790     return HAL_ERROR;
02791   }
02792 }
02793
02794 /**
02795   * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
02796   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02797   *         the configuration information for CRYP module
02798   * @param  pPlainData: Pointer to the plaintext buffer
02799   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02800   * @param  pCypherData: Pointer to the cyphertext buffer
02801   * @retval HAL status
02802   */
02803 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02804 {
02805   uint32_t inputaddr;
02806   uint32_t outputaddr;
02807
02808   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02809   {
02810     /* Process Locked */
02811     __HAL_LOCK(hcryp);
02812
02813     inputaddr  = (uint32_t)pPlainData;
02814     outputaddr = (uint32_t)pCypherData;
02815
02816     /* Change the CRYP state */
02817     hcryp->State = HAL_CRYP_STATE_BUSY;
02818
02819     /* Set CRYP peripheral in DES CBC encryption mode */
02820     CRYP_SetDESCBCMode(hcryp, 0);
02821
02822     /* Set the input and output addresses and start DMA transfer */
02823     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02824
02825     /* Process Unlocked */
02826     __HAL_UNLOCK(hcryp);
02827
02828     /* Return function status */
02829     return HAL_OK;
02830   }
02831   else
02832   {
02833     return HAL_ERROR;
02834   }
02835 }
02836
02837 /**
02838   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
02839   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02840   *         the configuration information for CRYP module
02841   * @param  pPlainData: Pointer to the plaintext buffer
02842   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02843   * @param  pCypherData: Pointer to the cyphertext buffer
02844   * @retval HAL status
02845   */
02846 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02847 {
02848   uint32_t inputaddr;
02849   uint32_t outputaddr;
02850
02851   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02852   {
02853     /* Process Locked */
02854     __HAL_LOCK(hcryp);
02855
02856     inputaddr  = (uint32_t)pCypherData;
02857     outputaddr = (uint32_t)pPlainData;
02858
02859     /* Change the CRYP state */
02860     hcryp->State = HAL_CRYP_STATE_BUSY;
02861
02862     /* Set CRYP peripheral in DES ECB decryption mode */
02863     CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
02864
02865     /* Set the input and output addresses and start DMA transfer */
02866     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02867
02868     /* Process Unlocked */
02869     __HAL_UNLOCK(hcryp);
02870
02871     /* Return function status */
02872     return HAL_OK;
02873   }
02874   else
02875   {
02876     return HAL_ERROR;
02877   }
02878 }
02879
02880 /**
02881   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
02882   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02883   *         the configuration information for CRYP module
02884   * @param  pPlainData: Pointer to the plaintext buffer
02885   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02886   * @param  pCypherData: Pointer to the cyphertext buffer
02887   * @retval HAL status
02888   */
02889 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02890 {
02891   uint32_t inputaddr;
02892   uint32_t outputaddr;
02893
02894   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02895   {
02896     /* Process Locked */
02897     __HAL_LOCK(hcryp);
02898
02899     inputaddr  = (uint32_t)pCypherData;
02900     outputaddr = (uint32_t)pPlainData;
02901
02902     /* Change the CRYP state */
02903     hcryp->State = HAL_CRYP_STATE_BUSY;
02904
02905     /* Set CRYP peripheral in DES CBC decryption mode */
02906     CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
02907
02908     /* Set the input and output addresses and start DMA transfer */
02909     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02910
02911     /* Process Unlocked */
02912     __HAL_UNLOCK(hcryp);
02913
02914     /* Return function status */
02915     return HAL_OK;
02916   }
02917   else
02918   {
02919     return HAL_ERROR;
02920   }
02921 }
02922
02923 /**
02924   * @}
02925   */
02926
02927 /** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
02928  *  @brief   processing functions.
02929  *
02930 @verbatim
02931   ==============================================================================
02932                       ##### TDES processing functions #####
02933   ==============================================================================
02934     [..]  This section provides functions allowing to:
02935       (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
02936       (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
02937     [..]  Three processing functions are available:
02938       (+) Polling mode
02939       (+) Interrupt mode
02940       (+) DMA mode
02941
02942 @endverbatim
02943   * @{
02944   */
02945
02946 /**
02947   * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode
02948   *         then encrypt pPlainData. The cypher data are available in pCypherData
02949   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02950   *         the configuration information for CRYP module
02951   * @param  pPlainData: Pointer to the plaintext buffer
02952   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02953   * @param  pCypherData: Pointer to the cyphertext buffer
02954   * @param  Timeout: Specify Timeout value
02955   * @retval HAL status
02956   */
02957 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
02958 {
02959   /* Process Locked */
02960   __HAL_LOCK(hcryp);
02961
02962   /* Change the CRYP state */
02963   hcryp->State = HAL_CRYP_STATE_BUSY;
02964
02965   /* Set CRYP peripheral in TDES ECB encryption mode */
02966   CRYP_SetTDESECBMode(hcryp, 0);
02967
02968   /* Enable CRYP */
02969   __HAL_CRYP_ENABLE(hcryp);
02970
02971   /* Write Plain Data and Get Cypher Data */
02972   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
02973   {
02974     return HAL_TIMEOUT;
02975   }
02976
02977   /* Change the CRYP state */
02978   hcryp->State = HAL_CRYP_STATE_READY;
02979
02980   /* Process Unlocked */
02981   __HAL_UNLOCK(hcryp);
02982
02983   /* Return function status */
02984   return HAL_OK;
02985 }
02986
02987 /**
02988   * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode
02989   *         then decrypted pCypherData. The cypher data are available in pPlainData
02990   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02991   *         the configuration information for CRYP module
02992   * @param  pPlainData: Pointer to the plaintext buffer
02993   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02994   * @param  pCypherData: Pointer to the cyphertext buffer
02995   * @param  Timeout: Specify Timeout value
02996   * @retval HAL status
02997   */
02998 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
02999 {
03000   /* Process Locked */
03001   __HAL_LOCK(hcryp);
03002
03003   /* Change the CRYP state */
03004   hcryp->State = HAL_CRYP_STATE_BUSY;
03005
03006   /* Set CRYP peripheral in TDES ECB decryption mode */
03007   CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
03008
03009   /* Enable CRYP */
03010   __HAL_CRYP_ENABLE(hcryp);
03011
03012   /* Write Cypher Data and Get Plain Data */
03013   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
03014   {
03015     return HAL_TIMEOUT;
03016   }
03017
03018   /* Change the CRYP state */
03019   hcryp->State = HAL_CRYP_STATE_READY;
03020
03021   /* Process Unlocked */
03022   __HAL_UNLOCK(hcryp);
03023
03024   /* Return function status */
03025   return HAL_OK;
03026 }
03027
03028 /**
03029   * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode
03030   *         then encrypt pPlainData. The cypher data are available in pCypherData
03031   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03032   *         the configuration information for CRYP module
03033   * @param  pPlainData: Pointer to the plaintext buffer
03034   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03035   * @param  pCypherData: Pointer to the cyphertext buffer
03036   * @param  Timeout: Specify Timeout value
03037   * @retval HAL status
03038   */
03039 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
03040 {
03041   /* Process Locked */
03042   __HAL_LOCK(hcryp);
03043
03044   /* Change the CRYP state */
03045   hcryp->State = HAL_CRYP_STATE_BUSY;
03046
03047   /* Set CRYP peripheral in TDES CBC encryption mode */
03048   CRYP_SetTDESCBCMode(hcryp, 0);
03049
03050   /* Enable CRYP */
03051   __HAL_CRYP_ENABLE(hcryp);
03052
03053   /* Write Plain Data and Get Cypher Data */
03054   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
03055   {
03056     return HAL_TIMEOUT;
03057   }
03058
03059   /* Change the CRYP state */
03060   hcryp->State = HAL_CRYP_STATE_READY;
03061
03062   /* Process Unlocked */
03063   __HAL_UNLOCK(hcryp);
03064
03065   /* Return function status */
03066   return HAL_OK;
03067 }
03068
03069 /**
03070   * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode
03071   *         then decrypted pCypherData. The cypher data are available in pPlainData
03072   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03073   *         the configuration information for CRYP module
03074   * @param  pCypherData: Pointer to the cyphertext buffer
03075   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03076   * @param  pPlainData: Pointer to the plaintext buffer
03077   * @param  Timeout: Specify Timeout value
03078   * @retval HAL status
03079   */
03080 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
03081 {
03082   /* Process Locked */
03083   __HAL_LOCK(hcryp);
03084
03085   /* Change the CRYP state */
03086   hcryp->State = HAL_CRYP_STATE_BUSY;
03087
03088   /* Set CRYP peripheral in TDES CBC decryption mode */
03089   CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
03090
03091   /* Enable CRYP */
03092   __HAL_CRYP_ENABLE(hcryp);
03093
03094   /* Write Cypher Data and Get Plain Data */
03095   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
03096   {
03097     return HAL_TIMEOUT;
03098   }
03099
03100   /* Change the CRYP state */
03101   hcryp->State = HAL_CRYP_STATE_READY;
03102
03103   /* Process Unlocked */
03104   __HAL_UNLOCK(hcryp);
03105
03106   /* Return function status */
03107   return HAL_OK;
03108 }
03109
03110 /**
03111   * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
03112   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03113   *         the configuration information for CRYP module
03114   * @param  pPlainData: Pointer to the plaintext buffer
03115   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03116   * @param  pCypherData: Pointer to the cyphertext buffer
03117   * @retval HAL status
03118   */
03119 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03120 {
03121   uint32_t inputaddr;
03122   uint32_t outputaddr;
03123
03124   if(hcryp->State == HAL_CRYP_STATE_READY)
03125   {
03126     /* Process Locked */
03127     __HAL_LOCK(hcryp);
03128
03129     hcryp->CrypInCount = Size;
03130     hcryp->pCrypInBuffPtr = pPlainData;
03131     hcryp->pCrypOutBuffPtr = pCypherData;
03132     hcryp->CrypOutCount = Size;
03133
03134     /* Change the CRYP state */
03135     hcryp->State = HAL_CRYP_STATE_BUSY;
03136
03137     /* Set CRYP peripheral in TDES ECB encryption mode */
03138     CRYP_SetTDESECBMode(hcryp, 0);
03139
03140     /* Enable Interrupts */
03141     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03142
03143     /* Enable CRYP */
03144     __HAL_CRYP_ENABLE(hcryp);
03145
03146     /* Return function status */
03147     return HAL_OK;
03148   }
03149   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03150   {
03151     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03152     /* Write the Input block in the IN FIFO */
03153     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03154     inputaddr+=4;
03155     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03156
03157     hcryp->pCrypInBuffPtr += 8;
03158     hcryp->CrypInCount -= 8;
03159     if(hcryp->CrypInCount == 0)
03160     {
03161       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03162       /* Call the Input data transfer complete callback */
03163       HAL_CRYP_InCpltCallback(hcryp);
03164     }
03165   }
03166   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03167   {
03168     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03169     /* Read the Output block from the Output FIFO */
03170     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03171     outputaddr+=4;
03172     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03173
03174     hcryp->pCrypOutBuffPtr += 8;
03175     hcryp->CrypOutCount -= 8;
03176     if(hcryp->CrypOutCount == 0)
03177     {
03178       /* Disable IT */
03179       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03180       /* Disable CRYP */
03181       __HAL_CRYP_DISABLE(hcryp);
03182       /* Process Unlocked */
03183       __HAL_UNLOCK(hcryp);
03184       /* Change the CRYP state */
03185       hcryp->State = HAL_CRYP_STATE_READY;
03186       /* Call the Output data transfer complete callback */
03187       HAL_CRYP_OutCpltCallback(hcryp);
03188     }
03189   }
03190
03191   /* Return function status */
03192   return HAL_OK;
03193 }
03194
03195 /**
03196   * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode.
03197   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03198   *         the configuration information for CRYP module
03199   * @param  pPlainData: Pointer to the plaintext buffer
03200   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03201   * @param  pCypherData: Pointer to the cyphertext buffer
03202   * @retval HAL status
03203   */
03204 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03205 {
03206   uint32_t inputaddr;
03207   uint32_t outputaddr;
03208
03209   if(hcryp->State == HAL_CRYP_STATE_READY)
03210   {
03211     /* Process Locked */
03212     __HAL_LOCK(hcryp);
03213
03214     hcryp->CrypInCount = Size;
03215     hcryp->pCrypInBuffPtr = pPlainData;
03216     hcryp->pCrypOutBuffPtr = pCypherData;
03217     hcryp->CrypOutCount = Size;
03218
03219     /* Change the CRYP state */
03220     hcryp->State = HAL_CRYP_STATE_BUSY;
03221
03222     /* Set CRYP peripheral in TDES CBC encryption mode */
03223     CRYP_SetTDESCBCMode(hcryp, 0);
03224
03225     /* Enable Interrupts */
03226     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03227
03228     /* Enable CRYP */
03229     __HAL_CRYP_ENABLE(hcryp);
03230
03231     /* Return function status */
03232     return HAL_OK;
03233   }
03234   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03235   {
03236     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03237     /* Write the Input block in the IN FIFO */
03238     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03239     inputaddr+=4;
03240     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03241
03242     hcryp->pCrypInBuffPtr += 8;
03243     hcryp->CrypInCount -= 8;
03244     if(hcryp->CrypInCount == 0)
03245     {
03246       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03247       /* Call the Input data transfer complete callback */
03248       HAL_CRYP_InCpltCallback(hcryp);
03249     }
03250   }
03251   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03252   {
03253     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03254     /* Read the Output block from the Output FIFO */
03255     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03256     outputaddr+=4;
03257     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03258
03259     hcryp->pCrypOutBuffPtr += 8;
03260     hcryp->CrypOutCount -= 8;
03261     if(hcryp->CrypOutCount == 0)
03262     {
03263       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03264       /* Disable CRYP */
03265       __HAL_CRYP_DISABLE(hcryp);
03266       /* Process Unlocked */
03267       __HAL_UNLOCK(hcryp);
03268       /* Change the CRYP state */
03269       hcryp->State = HAL_CRYP_STATE_READY;
03270       /* Call Input transfer complete callback */
03271       HAL_CRYP_OutCpltCallback(hcryp);
03272     }
03273   }
03274
03275   /* Return function status */
03276   return HAL_OK;
03277 }
03278
03279 /**
03280   * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode.
03281   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03282   *         the configuration information for CRYP module
03283   * @param  pPlainData: Pointer to the plaintext buffer
03284   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03285   * @param  pCypherData: Pointer to the cyphertext buffer
03286   * @retval HAL status
03287   */
03288 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03289 {
03290   uint32_t inputaddr;
03291   uint32_t outputaddr;
03292
03293   if(hcryp->State == HAL_CRYP_STATE_READY)
03294   {
03295     /* Process Locked */
03296     __HAL_LOCK(hcryp);
03297
03298     hcryp->CrypInCount = Size;
03299     hcryp->pCrypInBuffPtr = pCypherData;
03300     hcryp->pCrypOutBuffPtr = pPlainData;
03301     hcryp->CrypOutCount = Size;
03302
03303     /* Change the CRYP state */
03304     hcryp->State = HAL_CRYP_STATE_BUSY;
03305
03306     /* Set CRYP peripheral in TDES ECB decryption mode */
03307     CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
03308
03309     /* Enable Interrupts */
03310     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03311
03312     /* Enable CRYP */
03313     __HAL_CRYP_ENABLE(hcryp);
03314
03315     /* Return function status */
03316     return HAL_OK;
03317   }
03318   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03319   {
03320     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03321     /* Write the Input block in the IN FIFO */
03322     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03323     inputaddr+=4;
03324     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03325
03326     hcryp->pCrypInBuffPtr += 8;
03327     hcryp->CrypInCount -= 8;
03328     if(hcryp->CrypInCount == 0)
03329     {
03330       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03331       /* Call the Input data transfer complete callback */
03332       HAL_CRYP_InCpltCallback(hcryp);
03333     }
03334   }
03335   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03336   {
03337     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03338     /* Read the Output block from the Output FIFO */
03339     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03340     outputaddr+=4;
03341     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03342
03343     hcryp->pCrypOutBuffPtr += 8;
03344     hcryp->CrypOutCount -= 8;
03345     if(hcryp->CrypOutCount == 0)
03346     {
03347       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03348       /* Disable CRYP */
03349       __HAL_CRYP_DISABLE(hcryp);
03350       /* Process Unlocked */
03351       __HAL_UNLOCK(hcryp);
03352       /* Change the CRYP state */
03353       hcryp->State = HAL_CRYP_STATE_READY;
03354       /* Call Input transfer complete callback */
03355       HAL_CRYP_OutCpltCallback(hcryp);
03356     }
03357   }
03358
03359   /* Return function status */
03360   return HAL_OK;
03361 }
03362
03363 /**
03364   * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode.
03365   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03366   *         the configuration information for CRYP module
03367   * @param  pCypherData: Pointer to the cyphertext buffer
03368   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03369   * @param  pPlainData: Pointer to the plaintext buffer
03370   * @retval HAL status
03371   */
03372 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03373 {
03374   uint32_t inputaddr;
03375   uint32_t outputaddr;
03376
03377   if(hcryp->State == HAL_CRYP_STATE_READY)
03378   {
03379     /* Process Locked */
03380     __HAL_LOCK(hcryp);
03381
03382     hcryp->CrypInCount = Size;
03383     hcryp->pCrypInBuffPtr = pCypherData;
03384     hcryp->pCrypOutBuffPtr = pPlainData;
03385     hcryp->CrypOutCount = Size;
03386
03387     /* Change the CRYP state */
03388     hcryp->State = HAL_CRYP_STATE_BUSY;
03389
03390     /* Set CRYP peripheral in TDES CBC decryption mode */
03391     CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
03392
03393     /* Enable Interrupts */
03394     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03395
03396     /* Enable CRYP */
03397     __HAL_CRYP_ENABLE(hcryp);
03398
03399     /* Return function status */
03400     return HAL_OK;
03401   }
03402   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03403   {
03404     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03405     /* Write the Input block in the IN FIFO */
03406     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03407     inputaddr+=4;
03408     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03409
03410     hcryp->pCrypInBuffPtr += 8;
03411     hcryp->CrypInCount -= 8;
03412     if(hcryp->CrypInCount == 0)
03413     {
03414       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03415       /* Call the Input data transfer complete callback */
03416       HAL_CRYP_InCpltCallback(hcryp);
03417     }
03418   }
03419   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03420   {
03421     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03422     /* Read the Output block from the Output FIFO */
03423     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03424     outputaddr+=4;
03425     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03426
03427     hcryp->pCrypOutBuffPtr += 8;
03428     hcryp->CrypOutCount -= 8;
03429     if(hcryp->CrypOutCount == 0)
03430     {
03431       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03432       /* Disable CRYP */
03433       __HAL_CRYP_DISABLE(hcryp);
03434       /* Process Unlocked */
03435       __HAL_UNLOCK(hcryp);
03436       /* Change the CRYP state */
03437       hcryp->State = HAL_CRYP_STATE_READY;
03438       /* Call Input transfer complete callback */
03439       HAL_CRYP_OutCpltCallback(hcryp);
03440     }
03441   }
03442
03443   /* Return function status */
03444   return HAL_OK;
03445 }
03446
03447 /**
03448   * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
03449   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03450   *         the configuration information for CRYP module
03451   * @param  pPlainData: Pointer to the plaintext buffer
03452   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03453   * @param  pCypherData: Pointer to the cyphertext buffer
03454   * @retval HAL status
03455   */
03456 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03457 {
03458   uint32_t inputaddr;
03459   uint32_t outputaddr;
03460
03461   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03462   {
03463     /* Process Locked */
03464     __HAL_LOCK(hcryp);
03465
03466     inputaddr  = (uint32_t)pPlainData;
03467     outputaddr = (uint32_t)pCypherData;
03468
03469     /* Change the CRYP state */
03470     hcryp->State = HAL_CRYP_STATE_BUSY;
03471
03472     /* Set CRYP peripheral in TDES ECB encryption mode */
03473     CRYP_SetTDESECBMode(hcryp, 0);
03474
03475     /* Set the input and output addresses and start DMA transfer */
03476     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03477
03478     /* Process Unlocked */
03479     __HAL_UNLOCK(hcryp);
03480
03481     /* Return function status */
03482     return HAL_OK;
03483   }
03484   else
03485   {
03486     return HAL_ERROR;
03487   }
03488 }
03489
03490 /**
03491   * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
03492   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03493   *         the configuration information for CRYP module
03494   * @param  pPlainData: Pointer to the plaintext buffer
03495   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03496   * @param  pCypherData: Pointer to the cyphertext buffer
03497   * @retval HAL status
03498   */
03499 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03500 {
03501   uint32_t inputaddr;
03502   uint32_t outputaddr;
03503
03504   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03505   {
03506     /* Process Locked */
03507     __HAL_LOCK(hcryp);
03508
03509     inputaddr  = (uint32_t)pPlainData;
03510     outputaddr = (uint32_t)pCypherData;
03511
03512     /* Change the CRYP state */
03513     hcryp->State = HAL_CRYP_STATE_BUSY;
03514
03515     /* Set CRYP peripheral in TDES CBC encryption mode */
03516     CRYP_SetTDESCBCMode(hcryp, 0);
03517
03518     /* Set the input and output addresses and start DMA transfer */
03519     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03520
03521     /* Process Unlocked */
03522     __HAL_UNLOCK(hcryp);
03523
03524     /* Return function status */
03525     return HAL_OK;
03526   }
03527   else
03528   {
03529     return HAL_ERROR;
03530   }
03531 }
03532
03533 /**
03534   * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
03535   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03536   *         the configuration information for CRYP module
03537   * @param  pPlainData: Pointer to the plaintext buffer
03538   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03539   * @param  pCypherData: Pointer to the cyphertext buffer
03540   * @retval HAL status
03541   */
03542 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03543 {
03544   uint32_t inputaddr;
03545   uint32_t outputaddr;
03546
03547   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03548   {
03549     /* Process Locked */
03550     __HAL_LOCK(hcryp);
03551
03552     inputaddr  = (uint32_t)pCypherData;
03553     outputaddr = (uint32_t)pPlainData;
03554
03555     /* Change the CRYP state */
03556     hcryp->State = HAL_CRYP_STATE_BUSY;
03557
03558     /* Set CRYP peripheral in TDES ECB decryption mode */
03559     CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
03560
03561     /* Set the input and output addresses and start DMA transfer */
03562     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03563
03564     /* Process Unlocked */
03565     __HAL_UNLOCK(hcryp);
03566
03567     /* Return function status */
03568     return HAL_OK;
03569   }
03570   else
03571   {
03572     return HAL_ERROR;
03573   }
03574 }
03575
03576 /**
03577   * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
03578   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03579   *         the configuration information for CRYP module
03580   * @param  pCypherData: Pointer to the cyphertext buffer
03581   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03582   * @param  pPlainData: Pointer to the plaintext buffer
03583   * @retval HAL status
03584   */
03585 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03586 {
03587   uint32_t inputaddr;
03588   uint32_t outputaddr;
03589
03590   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03591   {
03592     /* Process Locked */
03593     __HAL_LOCK(hcryp);
03594
03595     inputaddr  = (uint32_t)pCypherData;
03596     outputaddr = (uint32_t)pPlainData;
03597
03598     /* Change the CRYP state */
03599     hcryp->State = HAL_CRYP_STATE_BUSY;
03600
03601     /* Set CRYP peripheral in TDES CBC decryption mode */
03602     CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
03603
03604     /* Set the input and output addresses and start DMA transfer */
03605     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03606
03607     /* Process Unlocked */
03608     __HAL_UNLOCK(hcryp);
03609
03610     /* Return function status */
03611     return HAL_OK;
03612   }
03613   else
03614   {
03615     return HAL_ERROR;
03616   }
03617 }
03618
03619 /**
03620   * @}
03621   */
03622
03623 /** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
03624  *  @brief   DMA callback functions.
03625  *
03626 @verbatim
03627   ==============================================================================
03628                       ##### DMA callback functions  #####
03629   ==============================================================================
03630     [..]  This section provides DMA callback functions:
03631       (+) DMA Input data transfer complete
03632       (+) DMA Output data transfer complete
03633       (+) DMA error
03634
03635 @endverbatim
03636   * @{
03637   */
03638
03639 /**
03640   * @brief  Input FIFO transfer completed callbacks.
03641   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03642   *         the configuration information for CRYP module
03643   * @retval None
03644   */
03645 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
03646 {
03647   /* Prevent unused argument(s) compilation warning */
03648   UNUSED(hcryp);
03649
03650   /* NOTE : This function Should not be modified, when the callback is needed,
03651             the HAL_CRYP_InCpltCallback could be implemented in the user file
03652    */
03653 }
03654
03655 /**
03656   * @brief  Output FIFO transfer completed callbacks.
03657   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03658   *         the configuration information for CRYP module
03659   * @retval None
03660   */
03661 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
03662 {
03663   /* Prevent unused argument(s) compilation warning */
03664   UNUSED(hcryp);
03665
03666   /* NOTE : This function Should not be modified, when the callback is needed,
03667             the HAL_CRYP_OutCpltCallback could be implemented in the user file
03668    */
03669 }
03670
03671 /**
03672   * @brief  CRYP error callbacks.
03673   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03674   *         the configuration information for CRYP module
03675   * @retval None
03676   */
03677  __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
03678 {
03679   /* Prevent unused argument(s) compilation warning */
03680   UNUSED(hcryp);
03681
03682   /* NOTE : This function Should not be modified, when the callback is needed,
03683             the HAL_CRYP_ErrorCallback could be implemented in the user file
03684    */
03685 }
03686
03687 /**
03688   * @}
03689   */
03690
03691 /** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
03692  *  @brief   CRYP IRQ handler.
03693  *
03694 @verbatim
03695   ==============================================================================
03696                 ##### CRYP IRQ handler management #####
03697   ==============================================================================
03698 [..]  This section provides CRYP IRQ handler function.
03699
03700 @endverbatim
03701   * @{
03702   */
03703
03704 /**
03705   * @brief  This function handles CRYP interrupt request.
03706   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03707   *         the configuration information for CRYP module
03708   * @retval None
03709   */
03710 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
03711 {
03712   switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
03713   {
03714   case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
03715     HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
03716     break;
03717
03718   case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
03719     HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
03720     break;
03721
03722   case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
03723     HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
03724     break;
03725
03726   case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
03727     HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
03728     break;
03729
03730   case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
03731     HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
03732     break;
03733
03734   case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
03735     HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
03736     break;
03737
03738   case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
03739     HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
03740     break;
03741
03742   case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
03743     HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
03744     break;
03745
03746   case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
03747     HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
03748     break;
03749
03750   case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
03751     HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
03752     break;
03753
03754   case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
03755     HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
03756     break;
03757
03758   case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
03759     HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
03760     break;
03761
03762   case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
03763     HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);
03764     break;
03765
03766   case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
03767     HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);
03768     break;
03769
03770   default:
03771     break;
03772   }
03773 }
03774
03775 /**
03776   * @}
03777   */
03778
03779 /** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
03780  *  @brief   Peripheral State functions.
03781  *
03782 @verbatim
03783   ==============================================================================
03784                       ##### Peripheral State functions #####
03785   ==============================================================================
03786     [..]
03787     This subsection permits to get in run-time the status of the peripheral.
03788
03789 @endverbatim
03790   * @{
03791   */
03792
03793 /**
03794   * @brief  Returns the CRYP state.
03795   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03796   *         the configuration information for CRYP module
03797   * @retval HAL state
03798   */
03799 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
03800 {
03801   return hcryp->State;
03802 }
03803
03804 /**
03805   * @}
03806   */
03807
03808 /**
03809   * @}
03810   */
03811
03812 #endif /* HAL_CRYP_MODULE_ENABLED */
03813
03814
03815 /**
03816   * @}
03817   */
03818 #endif /* STM32F756xx */
03819 /**
03820   * @}
03821   */
03822
03823 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp.h Source File

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stm32f7xx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CRYP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CRYP_H
00040 #define __STM32F7xx_HAL_CRYP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined (STM32F756xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup CRYP
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
00065   * @{
00066   */
00067
00068 typedef struct
00069 {
00070   uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00071                              This parameter can be a value of @ref CRYP_Data_Type */
00072
00073   uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
00074                              This parameter can be a value of @ref CRYP_Key_Size */
00075
00076   uint8_t* pKey;        /*!< The key used for encryption/decryption */
00077
00078   uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
00079                              counter in CTR mode */
00080
00081   uint8_t IVSize;       /*!< The size of initialization vector.
00082                              This parameter (called nonce size in CCM) is used only
00083                              in AES-128/192/256 encryption/decryption CCM mode */
00084
00085   uint8_t TagSize;      /*!< The size of returned authentication TAG.
00086                              This parameter is used only in AES-128/192/256
00087                              encryption/decryption CCM mode */
00088
00089   uint8_t* Header;      /*!< The header used in GCM and CCM modes */
00090
00091   uint32_t HeaderSize;  /*!< The size of header buffer in bytes */
00092
00093   uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
00094                              This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
00095 }CRYP_InitTypeDef;
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
00102   * @{
00103   */
00104
00105
00106 typedef enum
00107 {
00108   HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
00109   HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
00110   HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
00111   HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
00112   HAL_CRYP_STATE_ERROR             = 0x04   /*!< CRYP error state                      */
00113 }HAL_CRYP_STATETypeDef;
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
00120   * @{
00121   */
00122
00123
00124 typedef enum
00125 {
00126   HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization. */
00127   HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase */
00128   HAL_CRYP_PHASE_FINAL             = 0x03     /*!< CRYP peripheral is in final phase
00129                                                    This is relevant only with CCM and GCM modes */
00130 }HAL_PhaseTypeDef;
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
00137   * @{
00138   */
00139
00140 typedef struct
00141 {
00142       CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */
00143
00144       CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */
00145
00146       uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00147
00148       uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00149
00150       __IO uint16_t            CrypInCount;      /*!< Counter of inputed data */
00151
00152       __IO uint16_t            CrypOutCount;     /*!< Counter of output data */
00153
00154       HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */
00155
00156       HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */
00157
00158       DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */
00159
00160       DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */
00161
00162       HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
00163
00164    __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
00165 }CRYP_HandleTypeDef;
00166
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported constants --------------------------------------------------------*/
00176 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00177   * @{
00178   */
00179
00180 /** @defgroup CRYP_Key_Size CRYP Key Size
00181   * @{
00182   */
00183 #define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)
00184 #define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
00185 #define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CRYP_Data_Type CRYP Data Type
00191   * @{
00192   */
00193 #define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)
00194 #define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
00195 #define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
00196 #define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
00202   * @{
00203   */
00204 #define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003C)
00205 #define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000)
00206 #define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004)
00207 #define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008)
00208 #define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000C)
00209 #define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010)
00210 #define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014)
00211 #define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018)
00212 #define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001C)
00213 #define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020)
00214 #define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024)
00215 #define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028)
00216 #define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002C)
00217 #define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030)
00218 #define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034)
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
00224   * @{
00225   */
00226 #define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */
00227 #define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
00233   * @{
00234   */
00235 #define CRYP_FLAG_BUSY   ((uint32_t)0x00000010)  /*!< The CRYP core is currently
00236                                                      processing a block of data
00237                                                      or a key preparation (for
00238                                                      AES decryption). */
00239 #define CRYP_FLAG_IFEM   ((uint32_t)0x00000001)  /*!< Input FIFO is empty */
00240 #define CRYP_FLAG_IFNF   ((uint32_t)0x00000002)  /*!< Input FIFO is not Full */
00241 #define CRYP_FLAG_OFNE   ((uint32_t)0x00000004)  /*!< Output FIFO is not empty */
00242 #define CRYP_FLAG_OFFU   ((uint32_t)0x00000008)  /*!< Output FIFO is Full */
00243 #define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002)  /*!< Output FIFO service raw
00244                                                       interrupt status */
00245 #define CRYP_FLAG_INRIS  ((uint32_t)0x01000001)  /*!< Input FIFO service raw
00246                                                       interrupt status */
00247 /**
00248   * @}
00249   */
00250
00251 /**
00252   * @}
00253   */
00254
00255 /* Exported macro ------------------------------------------------------------*/
00256 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00257   * @{
00258   */
00259
00260 /** @brief Reset CRYP handle state
00261   * @param  __HANDLE__: specifies the CRYP handle.
00262   * @retval None
00263   */
00264 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00265
00266 /**
00267   * @brief  Enable/Disable the CRYP peripheral.
00268   * @param  __HANDLE__: specifies the CRYP handle.
00269   * @retval None
00270   */
00271 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
00272 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
00273
00274 /**
00275   * @brief  Flush the data FIFO.
00276   * @param  __HANDLE__: specifies the CRYP handle.
00277   * @retval None
00278   */
00279 #define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
00280
00281 /**
00282   * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
00283   * @param  __HANDLE__: specifies the CRYP handle.
00284   * @param  MODE: The algorithm mode.
00285   * @retval None
00286   */
00287 #define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
00288
00289 /** @brief  Check whether the specified CRYP flag is set or not.
00290   * @param  __HANDLE__: specifies the CRYP handle.
00291   * @param  __FLAG__: specifies the flag to check.
00292   *         This parameter can be one of the following values:
00293   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00294   *                                 or a key preparation (for AES decryption).
00295   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00296   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00297   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00298   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00299   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00300   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00301   * @retval The new state of __FLAG__ (TRUE or FALSE).
00302   */
00303
00304 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
00305                                                  ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
00306
00307 /** @brief  Check whether the specified CRYP interrupt is set or not.
00308   * @param  __HANDLE__: specifies the CRYP handle.
00309   * @param  __INTERRUPT__: specifies the interrupt to check.
00310   *         This parameter can be one of the following values:
00311   *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
00312   *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
00313   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00314   */
00315 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
00316
00317 /**
00318   * @brief  Enable the CRYP interrupt.
00319   * @param  __HANDLE__: specifies the CRYP handle.
00320   * @param  __INTERRUPT__: CRYP Interrupt.
00321   * @retval None
00322   */
00323 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
00324
00325 /**
00326   * @brief  Disable the CRYP interrupt.
00327   * @param  __HANDLE__: specifies the CRYP handle.
00328   * @param  __INTERRUPT__: CRYP interrupt.
00329   * @retval None
00330   */
00331 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
00332
00333 /**
00334   * @}
00335   */
00336
00337 /* Include CRYP HAL Extension module */
00338 #include "stm32f7xx_hal_cryp_ex.h"
00339
00340 /* Exported functions --------------------------------------------------------*/
00341 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00342   * @{
00343   */
00344
00345 /** @addtogroup CRYP_Exported_Functions_Group1
00346   * @{
00347   */
00348 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00349 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00350 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00351 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00352 /**
00353   * @}
00354   */
00355
00356 /** @addtogroup CRYP_Exported_Functions_Group2
00357   * @{
00358   */
00359 /* AES encryption/decryption using polling  ***********************************/
00360 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00361 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00362 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00363 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00364 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00365 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00366
00367 /* AES encryption/decryption using interrupt  *********************************/
00368 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00369 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00370 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00371 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00372 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00373 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00374
00375 /* AES encryption/decryption using DMA  ***************************************/
00376 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00377 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00378 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00379 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00380 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00381 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00382 /**
00383   * @}
00384   */
00385
00386 /** @addtogroup CRYP_Exported_Functions_Group3
00387   * @{
00388   */
00389 /* DES encryption/decryption using polling  ***********************************/
00390 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00391 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00392 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00393 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00394
00395 /* DES encryption/decryption using interrupt  *********************************/
00396 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00397 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00398 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00399 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00400
00401 /* DES encryption/decryption using DMA  ***************************************/
00402 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00403 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00404 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00405 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00406 /**
00407   * @}
00408   */
00409
00410 /** @addtogroup CRYP_Exported_Functions_Group4
00411   * @{
00412   */
00413 /* TDES encryption/decryption using polling  **********************************/
00414 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00415 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00416 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00417 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00418
00419 /* TDES encryption/decryption using interrupt  ********************************/
00420 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00421 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00422 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00423 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00424
00425 /* TDES encryption/decryption using DMA  **************************************/
00426 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00427 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00428 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00429 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00430 /**
00431   * @}
00432   */
00433
00434 /** @addtogroup CRYP_Exported_Functions_Group5
00435   * @{
00436   */
00437 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00438 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00439 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00440 /**
00441   * @}
00442   */
00443
00444 /** @addtogroup CRYP_Exported_Functions_Group6
00445   * @{
00446   */
00447 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00448 /**
00449   * @}
00450   */
00451
00452 /** @addtogroup CRYP_Exported_Functions_Group7
00453   * @{
00454   */
00455 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00456 /**
00457   * @}
00458   */
00459
00460 /**
00461   * @}
00462   */
00463
00464 /* Private types -------------------------------------------------------------*/
00465 /** @defgroup CRYP_Private_Types CRYP Private Types
00466   * @{
00467   */
00468
00469 /**
00470   * @}
00471   */
00472
00473 /* Private variables ---------------------------------------------------------*/
00474 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00475   * @{
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Private constants ---------------------------------------------------------*/
00483 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00484   * @{
00485   */
00486 #define CRYP_FLAG_MASK  ((uint32_t)0x0000001F)
00487 /**
00488   * @}
00489   */
00490
00491 /* Private macros ------------------------------------------------------------*/
00492 /** @defgroup CRYP_Private_Macros CRYP Private Macros
00493   * @{
00494   */
00495
00496 #define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
00497                                        ((__KEYSIZE__) == CRYP_KEYSIZE_192B)  || \
00498                                        ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
00499
00500
00501 #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
00502                                         ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
00503                                         ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
00504                                         ((__DATATYPE__) == CRYP_DATATYPE_1B))
00505
00506
00507  /**
00508   * @}
00509   */
00510
00511 /* Private functions ---------------------------------------------------------*/
00512 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00513   * @{
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 /**
00521   * @}
00522   */
00523
00524 #endif /* STM32F756xx */
00525
00526 /**
00527   * @}
00528   */
00529
00530 #ifdef __cplusplus
00531 }
00532 #endif
00533
00534 #endif /* __STM32F7xx_HAL_CRYP_H */
00535
00536 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp_ex.c Source File

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stm32f7xx_hal_cryp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Extended CRYP HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of CRYP extension peripheral:
00010   *           + Extended AES processing functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                      ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The CRYP Extension HAL driver can be used as follows:
00018     (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00019         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00020         (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
00021             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00022             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00023             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00024         (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
00025             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00026             (+++) Configure and enable two DMA streams one for managing data transfer from
00027                 memory to peripheral (input stream) and another stream for managing data
00028                 transfer from peripheral to memory (output stream)
00029             (+++) Associate the initialized DMA handle to the CRYP DMA handle
00030                 using  __HAL_LINKDMA()
00031             (+++) Configure the priority and enable the NVIC for the transfer complete
00032                 interrupt on the two DMA Streams. The output stream should have higher
00033                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00034     (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
00035         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
00036         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
00037         (##) The encryption/decryption key. Its size depends on the algorithm
00038                 used for encryption/decryption
00039         (##) The initialization vector (counter). It is not used ECB mode.
00040     (#)Three processing (encryption/decryption) functions are available:
00041         (##) Polling mode: encryption and decryption APIs are blocking functions
00042              i.e. they process the data and wait till the processing is finished
00043              e.g. HAL_CRYPEx_AESGCM_Encrypt()
00044         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00045                 i.e. they process the data under interrupt
00046                 e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
00047         (##) DMA mode: encryption and decryption APIs are not blocking functions
00048                 i.e. the data transfer is ensured by DMA
00049                 e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
00050     (#)When the processing function is called at first time after HAL_CRYP_Init()
00051        the CRYP peripheral is initialized and processes the buffer in input.
00052        At second call, the processing function performs an append of the already
00053        processed buffer.
00054        When a new data block is to be processed, call HAL_CRYP_Init() then the
00055        processing function.
00056     (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
00057        which provide authentication messages.
00058        HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
00059        authentication messages.
00060        Call those functions after the processing ones (polling, interrupt or DMA).
00061        e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
00062             then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
00063     -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
00064     -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
00065         (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
00066     (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f7xx_hal.h"
00101
00102 /** @addtogroup STM32F7xx_HAL_Driver
00103   * @{
00104   */
00105 #if defined (STM32F756xx)
00106 /** @defgroup CRYPEx CRYPEx
00107   * @brief CRYP Extension HAL module driver.
00108   * @{
00109   */
00110
00111
00112 #ifdef HAL_CRYP_MODULE_ENABLED
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /** @addtogroup CRYPEx_Private_define
00117   * @{
00118   */
00119 #define CRYPEx_TIMEOUT_VALUE  1
00120 /**
00121   * @}
00122   */
00123
00124 /* Private macro -------------------------------------------------------------*/
00125 /* Private variables ---------------------------------------------------------*/
00126 /* Private function prototypes -----------------------------------------------*/
00127 /** @defgroup CRYPEx_Private_Functions_prototypes  CRYP Private Functions Prototypes
00128   * @{
00129   */
00130 static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
00131 static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
00132 static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
00133 static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
00134 static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
00135 static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
00136 static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
00137 static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00138 /**
00139   * @}
00140   */
00141
00142 /* Private functions ---------------------------------------------------------*/
00143 /** @addtogroup CRYPEx_Private_Functions
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  DMA CRYP Input Data process complete callback.
00149   * @param  hdma: DMA handle
00150   * @retval None
00151   */
00152 static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
00153 {
00154   CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00155
00156   /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
00157      in the DMACR register */
00158   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
00159
00160   /* Call input data transfer complete callback */
00161   HAL_CRYP_InCpltCallback(hcryp);
00162 }
00163
00164 /**
00165   * @brief  DMA CRYP Output Data process complete callback.
00166   * @param  hdma: DMA handle
00167   * @retval None
00168   */
00169 static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
00170 {
00171   CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00172
00173   /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
00174      in the DMACR register */
00175   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
00176
00177   /* Enable the CRYP peripheral */
00178   __HAL_CRYP_DISABLE(hcryp);
00179
00180   /* Change the CRYP peripheral state */
00181   hcryp->State = HAL_CRYP_STATE_READY;
00182
00183   /* Call output data transfer complete callback */
00184   HAL_CRYP_OutCpltCallback(hcryp);
00185 }
00186
00187 /**
00188   * @brief  DMA CRYP communication error callback.
00189   * @param  hdma: DMA handle
00190   * @retval None
00191   */
00192 static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
00193 {
00194   CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00195   hcryp->State= HAL_CRYP_STATE_READY;
00196   HAL_CRYP_ErrorCallback(hcryp);
00197 }
00198
00199 /**
00200   * @brief  Writes the Key in Key registers.
00201   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00202   *         the configuration information for CRYP module
00203   * @param  Key: Pointer to Key buffer
00204   * @param  KeySize: Size of Key
00205   * @retval None
00206   */
00207 static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
00208 {
00209   uint32_t keyaddr = (uint32_t)Key;
00210
00211   switch(KeySize)
00212   {
00213   case CRYP_KEYSIZE_256B:
00214     /* Key Initialisation */
00215     hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
00216     keyaddr+=4;
00217     hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
00218     keyaddr+=4;
00219     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00220     keyaddr+=4;
00221     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00222     keyaddr+=4;
00223     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00224     keyaddr+=4;
00225     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00226     keyaddr+=4;
00227     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00228     keyaddr+=4;
00229     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00230     break;
00231   case CRYP_KEYSIZE_192B:
00232     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00233     keyaddr+=4;
00234     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00235     keyaddr+=4;
00236     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00237     keyaddr+=4;
00238     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00239     keyaddr+=4;
00240     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00241     keyaddr+=4;
00242     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00243     break;
00244   case CRYP_KEYSIZE_128B:
00245     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00246     keyaddr+=4;
00247     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00248     keyaddr+=4;
00249     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00250     keyaddr+=4;
00251     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00252     break;
00253   default:
00254     break;
00255   }
00256 }
00257
00258 /**
00259   * @brief  Writes the InitVector/InitCounter in IV registers.
00260   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00261   *         the configuration information for CRYP module
00262   * @param  InitVector: Pointer to InitVector/InitCounter buffer
00263   * @retval None
00264   */
00265 static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
00266 {
00267   uint32_t ivaddr = (uint32_t)InitVector;
00268
00269   hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00270   ivaddr+=4;
00271   hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00272   ivaddr+=4;
00273   hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
00274   ivaddr+=4;
00275   hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
00276 }
00277
00278 /**
00279   * @brief  Process Data: Writes Input data in polling mode and read the Output data.
00280   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00281   *         the configuration information for CRYP module
00282   * @param  Input: Pointer to the Input buffer.
00283   * @param  Ilength: Length of the Input buffer, must be a multiple of 16
00284   * @param  Output: Pointer to the returned buffer
00285   * @param  Timeout: Timeout value
00286   * @retval None
00287   */
00288 static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
00289 {
00290   uint32_t tickstart = 0;
00291   uint32_t i = 0;
00292   uint32_t inputaddr  = (uint32_t)Input;
00293   uint32_t outputaddr = (uint32_t)Output;
00294
00295   for(i=0; (i < Ilength); i+=16)
00296   {
00297     /* Write the Input block in the IN FIFO */
00298     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00299     inputaddr+=4;
00300     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00301     inputaddr+=4;
00302     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
00303     inputaddr+=4;
00304     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00305     inputaddr+=4;
00306
00307     /* Get tick */
00308     tickstart = HAL_GetTick();
00309
00310     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00311     {
00312       /* Check for the Timeout */
00313       if(Timeout != HAL_MAX_DELAY)
00314       {
00315         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
00316         {
00317           /* Change state */
00318           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00319
00320           /* Process Unlocked */
00321           __HAL_UNLOCK(hcryp);
00322
00323           return HAL_TIMEOUT;
00324         }
00325       }
00326     }
00327     /* Read the Output block from the OUT FIFO */
00328     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00329     outputaddr+=4;
00330     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00331     outputaddr+=4;
00332     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00333     outputaddr+=4;
00334     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00335     outputaddr+=4;
00336   }
00337   /* Return function status */
00338   return HAL_OK;
00339 }
00340
00341 /**
00342   * @brief  Sets the header phase
00343   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00344   *         the configuration information for CRYP module
00345   * @param  Input: Pointer to the Input buffer.
00346   * @param  Ilength: Length of the Input buffer, must be a multiple of 16
00347   * @param  Timeout: Timeout value
00348   * @retval None
00349   */
00350 static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
00351 {
00352   uint32_t tickstart = 0;
00353   uint32_t loopcounter = 0;
00354   uint32_t headeraddr = (uint32_t)Input;
00355
00356   /***************************** Header phase *********************************/
00357   if(hcryp->Init.HeaderSize != 0)
00358   {
00359     /* Select header phase */
00360     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
00361     /* Enable the CRYP peripheral */
00362     __HAL_CRYP_ENABLE(hcryp);
00363
00364     for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
00365     {
00366       /* Get tick */
00367       tickstart = HAL_GetTick();
00368
00369       while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
00370       {
00371         /* Check for the Timeout */
00372         if(Timeout != HAL_MAX_DELAY)
00373         {
00374           if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00375           {
00376             /* Change state */
00377             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00378
00379             /* Process Unlocked */
00380             __HAL_UNLOCK(hcryp);
00381
00382             return HAL_TIMEOUT;
00383           }
00384         }
00385       }
00386       /* Write the Input block in the IN FIFO */
00387       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00388       headeraddr+=4;
00389       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00390       headeraddr+=4;
00391       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00392       headeraddr+=4;
00393       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00394       headeraddr+=4;
00395     }
00396
00397     /* Wait until the complete message has been processed */
00398
00399     /* Get tick */
00400     tickstart = HAL_GetTick();
00401
00402     while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
00403     {
00404       /* Check for the Timeout */
00405       if(Timeout != HAL_MAX_DELAY)
00406       {
00407         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00408         {
00409           /* Change state */
00410           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00411
00412           /* Process Unlocked */
00413           __HAL_UNLOCK(hcryp);
00414
00415           return HAL_TIMEOUT;
00416         }
00417       }
00418     }
00419   }
00420   /* Return function status */
00421   return HAL_OK;
00422 }
00423
00424 /**
00425   * @brief  Sets the DMA configuration and start the DMA transfer.
00426   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00427   *         the configuration information for CRYP module
00428   * @param  inputaddr: Address of the Input buffer
00429   * @param  Size: Size of the Input buffer, must be a multiple of 16
00430   * @param  outputaddr: Address of the Output buffer
00431   * @retval None
00432   */
00433 static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
00434 {
00435   /* Set the CRYP DMA transfer complete callback */
00436   hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
00437   /* Set the DMA error callback */
00438   hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
00439
00440   /* Set the CRYP DMA transfer complete callback */
00441   hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
00442   /* Set the DMA error callback */
00443   hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
00444
00445   /* Enable the CRYP peripheral */
00446   __HAL_CRYP_ENABLE(hcryp);
00447
00448   /* Enable the DMA In DMA Stream */
00449   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
00450
00451   /* Enable In DMA request */
00452   hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
00453
00454   /* Enable the DMA Out DMA Stream */
00455   HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
00456
00457   /* Enable Out DMA request */
00458   hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
00459 }
00460
00461 /**
00462   * @}
00463   */
00464
00465 /* Exported functions---------------------------------------------------------*/
00466 /** @addtogroup CRYPEx_Exported_Functions
00467   * @{
00468   */
00469
00470 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00471  *  @brief   Extended processing functions.
00472  *
00473 @verbatim
00474   ==============================================================================
00475               ##### Extended AES processing functions #####
00476   ==============================================================================
00477     [..]  This section provides functions allowing to:
00478       (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
00479       (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
00480       (+) Finish the processing. This function is available only for GCM and CCM
00481     [..]  Three processing methods are available:
00482       (+) Polling mode
00483       (+) Interrupt mode
00484       (+) DMA mode
00485
00486 @endverbatim
00487   * @{
00488   */
00489
00490
00491 /**
00492   * @brief  Initializes the CRYP peripheral in AES CCM encryption mode then
00493   *         encrypt pPlainData. The cypher data are available in pCypherData.
00494   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00495   *         the configuration information for CRYP module
00496   * @param  pPlainData: Pointer to the plaintext buffer
00497   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
00498   * @param  pCypherData: Pointer to the cyphertext buffer
00499   * @param  Timeout: Timeout duration
00500   * @retval HAL status
00501   */
00502 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00503 {
00504   uint32_t tickstart = 0;
00505   uint32_t headersize = hcryp->Init.HeaderSize;
00506   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
00507   uint32_t loopcounter = 0;
00508   uint32_t bufferidx = 0;
00509   uint8_t blockb0[16] = {0};/* Block B0 */
00510   uint8_t ctr[16] = {0}; /* Counter */
00511   uint32_t b0addr = (uint32_t)blockb0;
00512
00513   /* Process Locked */
00514   __HAL_LOCK(hcryp);
00515
00516   /* Change the CRYP peripheral state */
00517   hcryp->State = HAL_CRYP_STATE_BUSY;
00518
00519   /* Check if initialization phase has already been performed */
00520   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00521   {
00522     /************************ Formatting the header block *********************/
00523     if(headersize != 0)
00524     {
00525       /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
00526       if(headersize < 65280)
00527       {
00528         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
00529         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
00530         headersize += 2;
00531       }
00532       else
00533       {
00534         /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
00535         hcryp->Init.pScratch[bufferidx++] = 0xFF;
00536         hcryp->Init.pScratch[bufferidx++] = 0xFE;
00537         hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
00538         hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
00539         hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
00540         hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
00541         headersize += 6;
00542       }
00543       /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
00544       for(loopcounter = 0; loopcounter < headersize; loopcounter++)
00545       {
00546         hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
00547       }
00548       /* Check if the header size is modulo 16 */
00549       if ((headersize % 16) != 0)
00550       {
00551         /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
00552         for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
00553         {
00554           hcryp->Init.pScratch[loopcounter] = 0;
00555         }
00556         /* Set the header size to modulo 16 */
00557         headersize = ((headersize/16) + 1) * 16;
00558       }
00559       /* Set the pointer headeraddr to hcryp->Init.pScratch */
00560       headeraddr = (uint32_t)hcryp->Init.pScratch;
00561     }
00562     /*********************** Formatting the block B0 **************************/
00563     if(headersize != 0)
00564     {
00565       blockb0[0] = 0x40;
00566     }
00567     /* Flags byte */
00568     /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
00569     blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
00570     blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
00571
00572     for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
00573     {
00574       blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
00575     }
00576     for ( ; loopcounter < 13; loopcounter++)
00577     {
00578       blockb0[loopcounter+1] = 0;
00579     }
00580
00581     blockb0[14] = (Size >> 8);
00582     blockb0[15] = (Size & 0xFF);
00583
00584     /************************* Formatting the initial counter *****************/
00585     /* Byte 0:
00586        Bits 7 and 6 are reserved and shall be set to 0
00587        Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
00588        are distinct from B0
00589        Bits 0, 1, and 2 contain the same encoding of q as in B0
00590     */
00591     ctr[0] = blockb0[0] & 0x07;
00592     /* byte 1 to NonceSize is the IV (Nonce) */
00593     for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
00594     {
00595       ctr[loopcounter] = blockb0[loopcounter];
00596     }
00597     /* Set the LSB to 1 */
00598     ctr[15] |= 0x01;
00599
00600     /* Set the key */
00601     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00602
00603     /* Set the CRYP peripheral in AES CCM mode */
00604     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
00605
00606     /* Set the Initialization Vector */
00607     CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
00608
00609     /* Select init phase */
00610     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
00611
00612     b0addr = (uint32_t)blockb0;
00613     /* Write the blockb0 block in the IN FIFO */
00614     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00615     b0addr+=4;
00616     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00617     b0addr+=4;
00618     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00619     b0addr+=4;
00620     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00621
00622     /* Enable the CRYP peripheral */
00623     __HAL_CRYP_ENABLE(hcryp);
00624
00625     /* Get tick */
00626     tickstart = HAL_GetTick();
00627
00628     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
00629     {
00630       /* Check for the Timeout */
00631       if(Timeout != HAL_MAX_DELAY)
00632       {
00633         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00634         {
00635           /* Change state */
00636           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00637
00638           /* Process Unlocked */
00639           __HAL_UNLOCK(hcryp);
00640
00641           return HAL_TIMEOUT;
00642         }
00643       }
00644     }
00645     /***************************** Header phase *******************************/
00646     if(headersize != 0)
00647     {
00648       /* Select header phase */
00649       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
00650
00651       /* Enable the CRYP peripheral */
00652       __HAL_CRYP_ENABLE(hcryp);
00653
00654       for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
00655       {
00656         /* Get tick */
00657         tickstart = HAL_GetTick();
00658
00659         while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
00660         {
00661           {
00662             /* Check for the Timeout */
00663             if(Timeout != HAL_MAX_DELAY)
00664             {
00665               if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00666               {
00667                 /* Change state */
00668                 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00669
00670                 /* Process Unlocked */
00671                 __HAL_UNLOCK(hcryp);
00672
00673                 return HAL_TIMEOUT;
00674               }
00675             }
00676           }
00677         }
00678         /* Write the header block in the IN FIFO */
00679         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00680         headeraddr+=4;
00681         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00682         headeraddr+=4;
00683         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00684         headeraddr+=4;
00685         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00686         headeraddr+=4;
00687       }
00688
00689       /* Get tick */
00690       tickstart = HAL_GetTick();
00691
00692       while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
00693       {
00694         /* Check for the Timeout */
00695         if(Timeout != HAL_MAX_DELAY)
00696         {
00697           if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00698           {
00699             /* Change state */
00700             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00701
00702             /* Process Unlocked */
00703             __HAL_UNLOCK(hcryp);
00704
00705             return HAL_TIMEOUT;
00706           }
00707         }
00708       }
00709     }
00710     /* Save formatted counter into the scratch buffer pScratch */
00711     for(loopcounter = 0; (loopcounter < 16); loopcounter++)
00712     {
00713       hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
00714     }
00715     /* Reset bit 0 */
00716     hcryp->Init.pScratch[15] &= 0xfe;
00717
00718     /* Select payload phase once the header phase is performed */
00719     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
00720
00721     /* Flush FIFO */
00722     __HAL_CRYP_FIFO_FLUSH(hcryp);
00723
00724     /* Enable the CRYP peripheral */
00725     __HAL_CRYP_ENABLE(hcryp);
00726
00727     /* Set the phase */
00728     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00729   }
00730
00731   /* Write Plain Data and Get Cypher Data */
00732   if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00733   {
00734     return HAL_TIMEOUT;
00735   }
00736
00737   /* Change the CRYP peripheral state */
00738   hcryp->State = HAL_CRYP_STATE_READY;
00739
00740   /* Process Unlocked */
00741   __HAL_UNLOCK(hcryp);
00742
00743   /* Return function status */
00744   return HAL_OK;
00745 }
00746
00747 /**
00748   * @brief  Initializes the CRYP peripheral in AES GCM encryption mode then
00749   *         encrypt pPlainData. The cypher data are available in pCypherData.
00750   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00751   *         the configuration information for CRYP module
00752   * @param  pPlainData: Pointer to the plaintext buffer
00753   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
00754   * @param  pCypherData: Pointer to the cyphertext buffer
00755   * @param  Timeout: Timeout duration
00756   * @retval HAL status
00757   */
00758 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00759 {
00760   uint32_t tickstart = 0;
00761
00762   /* Process Locked */
00763   __HAL_LOCK(hcryp);
00764
00765   /* Change the CRYP peripheral state */
00766   hcryp->State = HAL_CRYP_STATE_BUSY;
00767
00768   /* Check if initialization phase has already been performed */
00769   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00770   {
00771     /* Set the key */
00772     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00773
00774     /* Set the CRYP peripheral in AES GCM mode */
00775     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
00776
00777     /* Set the Initialization Vector */
00778     CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
00779
00780     /* Flush FIFO */
00781     __HAL_CRYP_FIFO_FLUSH(hcryp);
00782
00783     /* Enable the CRYP peripheral */
00784     __HAL_CRYP_ENABLE(hcryp);
00785
00786     /* Get tick */
00787     tickstart = HAL_GetTick();
00788
00789     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
00790     {
00791       /* Check for the Timeout */
00792       if(Timeout != HAL_MAX_DELAY)
00793       {
00794         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00795         {
00796           /* Change state */
00797           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00798
00799           /* Process Unlocked */
00800           __HAL_UNLOCK(hcryp);
00801
00802           return HAL_TIMEOUT;
00803         }
00804       }
00805     }
00806
00807     /* Set the header phase */
00808     if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
00809     {
00810       return HAL_TIMEOUT;
00811     }
00812
00813     /* Disable the CRYP peripheral */
00814     __HAL_CRYP_DISABLE(hcryp);
00815
00816     /* Select payload phase once the header phase is performed */
00817     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
00818
00819     /* Flush FIFO */
00820     __HAL_CRYP_FIFO_FLUSH(hcryp);
00821
00822     /* Enable the CRYP peripheral */
00823     __HAL_CRYP_ENABLE(hcryp);
00824
00825     /* Set the phase */
00826     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00827   }
00828
00829   /* Write Plain Data and Get Cypher Data */
00830   if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00831   {
00832     return HAL_TIMEOUT;
00833   }
00834
00835   /* Change the CRYP peripheral state */
00836   hcryp->State = HAL_CRYP_STATE_READY;
00837
00838   /* Process Unlocked */
00839   __HAL_UNLOCK(hcryp);
00840
00841   /* Return function status */
00842   return HAL_OK;
00843 }
00844
00845 /**
00846   * @brief  Initializes the CRYP peripheral in AES GCM decryption mode then
00847   *         decrypted pCypherData. The cypher data are available in pPlainData.
00848   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00849   *         the configuration information for CRYP module
00850   * @param  pCypherData: Pointer to the cyphertext buffer
00851   * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
00852   * @param  pPlainData: Pointer to the plaintext buffer
00853   * @param  Timeout: Timeout duration
00854   * @retval HAL status
00855   */
00856 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00857 {
00858   uint32_t tickstart = 0;
00859
00860   /* Process Locked */
00861   __HAL_LOCK(hcryp);
00862
00863   /* Change the CRYP peripheral state */
00864   hcryp->State = HAL_CRYP_STATE_BUSY;
00865
00866   /* Check if initialization phase has already been performed */
00867   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00868   {
00869     /* Set the key */
00870     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00871
00872     /* Set the CRYP peripheral in AES GCM decryption mode */
00873     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
00874
00875     /* Set the Initialization Vector */
00876     CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
00877
00878     /* Flush FIFO */
00879     __HAL_CRYP_FIFO_FLUSH(hcryp);
00880
00881     /* Enable the CRYP peripheral */
00882     __HAL_CRYP_ENABLE(hcryp);
00883
00884     /* Get tick */
00885     tickstart = HAL_GetTick();
00886
00887     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
00888     {
00889       /* Check for the Timeout */
00890       if(Timeout != HAL_MAX_DELAY)
00891       {
00892         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00893         {
00894           /* Change state */
00895           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00896
00897           /* Process Unlocked */
00898           __HAL_UNLOCK(hcryp);
00899
00900           return HAL_TIMEOUT;
00901         }
00902       }
00903     }
00904
00905     /* Set the header phase */
00906     if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
00907     {
00908       return HAL_TIMEOUT;
00909     }
00910     /* Disable the CRYP peripheral */
00911     __HAL_CRYP_DISABLE(hcryp);
00912
00913     /* Select payload phase once the header phase is performed */
00914     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
00915
00916     /* Enable the CRYP peripheral */
00917     __HAL_CRYP_ENABLE(hcryp);
00918
00919     /* Set the phase */
00920     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00921   }
00922
00923   /* Write Plain Data and Get Cypher Data */
00924   if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
00925   {
00926     return HAL_TIMEOUT;
00927   }
00928
00929   /* Change the CRYP peripheral state */
00930   hcryp->State = HAL_CRYP_STATE_READY;
00931
00932   /* Process Unlocked */
00933   __HAL_UNLOCK(hcryp);
00934
00935   /* Return function status */
00936   return HAL_OK;
00937 }
00938
00939 /**
00940   * @brief  Computes the authentication TAG.
00941   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00942   *         the configuration information for CRYP module
00943   * @param  Size: Total length of the plain/cyphertext buffer
00944   * @param  AuthTag: Pointer to the authentication buffer
00945   * @param  Timeout: Timeout duration
00946   * @retval HAL status
00947   */
00948 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)
00949 {
00950   uint32_t tickstart = 0;
00951   uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
00952   uint64_t inputlength = Size * 8; /* input length in bits */
00953   uint32_t tagaddr = (uint32_t)AuthTag;
00954
00955   /* Process Locked */
00956   __HAL_LOCK(hcryp);
00957
00958   /* Change the CRYP peripheral state */
00959   hcryp->State = HAL_CRYP_STATE_BUSY;
00960
00961   /* Check if initialization phase has already been performed */
00962   if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
00963   {
00964     /* Change the CRYP phase */
00965     hcryp->Phase = HAL_CRYP_PHASE_FINAL;
00966
00967     /* Disable CRYP to start the final phase */
00968     __HAL_CRYP_DISABLE(hcryp);
00969
00970     /* Select final phase */
00971     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
00972
00973     /* Enable the CRYP peripheral */
00974     __HAL_CRYP_ENABLE(hcryp);
00975
00976     /* Write the number of bits in header (64 bits) followed by the number of bits
00977        in the payload */
00978     if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
00979     {
00980       hcryp->Instance->DR = __RBIT(headerlength >> 32);
00981       hcryp->Instance->DR = __RBIT(headerlength);
00982       hcryp->Instance->DR = __RBIT(inputlength >> 32);
00983       hcryp->Instance->DR = __RBIT(inputlength);
00984     }
00985     else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
00986     {
00987       hcryp->Instance->DR = __REV(headerlength >> 32);
00988       hcryp->Instance->DR = __REV(headerlength);
00989       hcryp->Instance->DR = __REV(inputlength >> 32);
00990       hcryp->Instance->DR = __REV(inputlength);
00991     }
00992     else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
00993     {
00994       hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);
00995       hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);
00996       hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);
00997       hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);
00998     }
00999     else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
01000     {
01001       hcryp->Instance->DR = (uint32_t)(headerlength >> 32);
01002       hcryp->Instance->DR = (uint32_t)(headerlength);
01003       hcryp->Instance->DR = (uint32_t)(inputlength >> 32);
01004       hcryp->Instance->DR = (uint32_t)(inputlength);
01005     }
01006     /* Get tick */
01007     tickstart = HAL_GetTick();
01008
01009     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
01010     {
01011       /* Check for the Timeout */
01012       if(Timeout != HAL_MAX_DELAY)
01013       {
01014         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01015         {
01016           /* Change state */
01017           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01018
01019           /* Process Unlocked */
01020           __HAL_UNLOCK(hcryp);
01021
01022           return HAL_TIMEOUT;
01023         }
01024       }
01025     }
01026
01027     /* Read the Auth TAG in the IN FIFO */
01028     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01029     tagaddr+=4;
01030     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01031     tagaddr+=4;
01032     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01033     tagaddr+=4;
01034     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01035   }
01036
01037   /* Change the CRYP peripheral state */
01038   hcryp->State = HAL_CRYP_STATE_READY;
01039
01040   /* Process Unlocked */
01041   __HAL_UNLOCK(hcryp);
01042
01043   /* Return function status */
01044   return HAL_OK;
01045 }
01046
01047 /**
01048   * @brief  Computes the authentication TAG for AES CCM mode.
01049   * @note   This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
01050   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01051   *         the configuration information for CRYP module
01052   * @param  AuthTag: Pointer to the authentication buffer
01053   * @param  Timeout: Timeout duration
01054   * @retval HAL status
01055   */
01056 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
01057 {
01058   uint32_t tickstart = 0;
01059   uint32_t tagaddr = (uint32_t)AuthTag;
01060   uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
01061   uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */
01062   uint32_t loopcounter;
01063
01064   /* Process Locked */
01065   __HAL_LOCK(hcryp);
01066
01067   /* Change the CRYP peripheral state */
01068   hcryp->State = HAL_CRYP_STATE_BUSY;
01069
01070   /* Check if initialization phase has already been performed */
01071   if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
01072   {
01073     /* Change the CRYP phase */
01074     hcryp->Phase = HAL_CRYP_PHASE_FINAL;
01075
01076     /* Disable CRYP to start the final phase */
01077     __HAL_CRYP_DISABLE(hcryp);
01078
01079     /* Select final phase */
01080     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
01081
01082     /* Enable the CRYP peripheral */
01083     __HAL_CRYP_ENABLE(hcryp);
01084
01085     /* Write the counter block in the IN FIFO */
01086     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01087     ctraddr+=4;
01088     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01089     ctraddr+=4;
01090     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01091     ctraddr+=4;
01092     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01093
01094     /* Get tick */
01095     tickstart = HAL_GetTick();
01096
01097     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
01098     {
01099       /* Check for the Timeout */
01100       if(Timeout != HAL_MAX_DELAY)
01101       {
01102         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01103         {
01104           /* Change state */
01105           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01106
01107           /* Process Unlocked */
01108           __HAL_UNLOCK(hcryp);
01109
01110           return HAL_TIMEOUT;
01111         }
01112       }
01113     }
01114
01115     /* Read the Auth TAG in the IN FIFO */
01116     temptag[0] = hcryp->Instance->DOUT;
01117     temptag[1] = hcryp->Instance->DOUT;
01118     temptag[2] = hcryp->Instance->DOUT;
01119     temptag[3] = hcryp->Instance->DOUT;
01120   }
01121
01122   /* Copy temporary authentication TAG in user TAG buffer */
01123   for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)
01124   {
01125     /* Set the authentication TAG buffer */
01126     *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
01127   }
01128
01129   /* Change the CRYP peripheral state */
01130   hcryp->State = HAL_CRYP_STATE_READY;
01131
01132   /* Process Unlocked */
01133   __HAL_UNLOCK(hcryp);
01134
01135   /* Return function status */
01136   return HAL_OK;
01137 }
01138
01139 /**
01140   * @brief  Initializes the CRYP peripheral in AES CCM decryption mode then
01141   *         decrypted pCypherData. The cypher data are available in pPlainData.
01142   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01143   *         the configuration information for CRYP module
01144   * @param  pPlainData: Pointer to the plaintext buffer
01145   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01146   * @param  pCypherData: Pointer to the cyphertext buffer
01147   * @param  Timeout: Timeout duration
01148   * @retval HAL status
01149   */
01150 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
01151 {
01152   uint32_t tickstart = 0;
01153   uint32_t headersize = hcryp->Init.HeaderSize;
01154   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
01155   uint32_t loopcounter = 0;
01156   uint32_t bufferidx = 0;
01157   uint8_t blockb0[16] = {0};/* Block B0 */
01158   uint8_t ctr[16] = {0}; /* Counter */
01159   uint32_t b0addr = (uint32_t)blockb0;
01160
01161   /* Process Locked */
01162   __HAL_LOCK(hcryp);
01163
01164   /* Change the CRYP peripheral state */
01165   hcryp->State = HAL_CRYP_STATE_BUSY;
01166
01167   /* Check if initialization phase has already been performed */
01168   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01169   {
01170     /************************ Formatting the header block *********************/
01171     if(headersize != 0)
01172     {
01173       /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
01174       if(headersize < 65280)
01175       {
01176         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
01177         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
01178         headersize += 2;
01179       }
01180       else
01181       {
01182         /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
01183         hcryp->Init.pScratch[bufferidx++] = 0xFF;
01184         hcryp->Init.pScratch[bufferidx++] = 0xFE;
01185         hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
01186         hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
01187         hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
01188         hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
01189         headersize += 6;
01190       }
01191       /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
01192       for(loopcounter = 0; loopcounter < headersize; loopcounter++)
01193       {
01194         hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
01195       }
01196       /* Check if the header size is modulo 16 */
01197       if ((headersize % 16) != 0)
01198       {
01199         /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
01200         for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
01201         {
01202           hcryp->Init.pScratch[loopcounter] = 0;
01203         }
01204         /* Set the header size to modulo 16 */
01205         headersize = ((headersize/16) + 1) * 16;
01206       }
01207       /* Set the pointer headeraddr to hcryp->Init.pScratch */
01208       headeraddr = (uint32_t)hcryp->Init.pScratch;
01209     }
01210     /*********************** Formatting the block B0 **************************/
01211     if(headersize != 0)
01212     {
01213       blockb0[0] = 0x40;
01214     }
01215     /* Flags byte */
01216     /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
01217     blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
01218     blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
01219
01220     for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
01221     {
01222       blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
01223     }
01224     for ( ; loopcounter < 13; loopcounter++)
01225     {
01226       blockb0[loopcounter+1] = 0;
01227     }
01228
01229     blockb0[14] = (Size >> 8);
01230     blockb0[15] = (Size & 0xFF);
01231
01232     /************************* Formatting the initial counter *****************/
01233     /* Byte 0:
01234        Bits 7 and 6 are reserved and shall be set to 0
01235        Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
01236        blocks are distinct from B0
01237        Bits 0, 1, and 2 contain the same encoding of q as in B0
01238     */
01239     ctr[0] = blockb0[0] & 0x07;
01240     /* byte 1 to NonceSize is the IV (Nonce) */
01241     for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
01242     {
01243       ctr[loopcounter] = blockb0[loopcounter];
01244     }
01245     /* Set the LSB to 1 */
01246     ctr[15] |= 0x01;
01247
01248     /* Set the key */
01249     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01250
01251     /* Set the CRYP peripheral in AES CCM mode */
01252     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
01253
01254     /* Set the Initialization Vector */
01255     CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
01256
01257     /* Select init phase */
01258     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
01259
01260     b0addr = (uint32_t)blockb0;
01261     /* Write the blockb0 block in the IN FIFO */
01262     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01263     b0addr+=4;
01264     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01265     b0addr+=4;
01266     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01267     b0addr+=4;
01268     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01269
01270     /* Enable the CRYP peripheral */
01271     __HAL_CRYP_ENABLE(hcryp);
01272
01273     /* Get tick */
01274     tickstart = HAL_GetTick();
01275
01276     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01277     {
01278       /* Check for the Timeout */
01279       if(Timeout != HAL_MAX_DELAY)
01280       {
01281         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01282         {
01283           /* Change state */
01284           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01285
01286           /* Process Unlocked */
01287           __HAL_UNLOCK(hcryp);
01288
01289           return HAL_TIMEOUT;
01290         }
01291       }
01292     }
01293     /***************************** Header phase *******************************/
01294     if(headersize != 0)
01295     {
01296       /* Select header phase */
01297       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
01298
01299       /* Enable Crypto processor */
01300       __HAL_CRYP_ENABLE(hcryp);
01301
01302       for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
01303       {
01304         /* Get tick */
01305         tickstart = HAL_GetTick();
01306
01307         while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
01308         {
01309           /* Check for the Timeout */
01310           if(Timeout != HAL_MAX_DELAY)
01311           {
01312             if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01313             {
01314               /* Change state */
01315               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01316
01317               /* Process Unlocked */
01318               __HAL_UNLOCK(hcryp);
01319
01320               return HAL_TIMEOUT;
01321             }
01322           }
01323         }
01324         /* Write the header block in the IN FIFO */
01325         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01326         headeraddr+=4;
01327         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01328         headeraddr+=4;
01329         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01330         headeraddr+=4;
01331         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01332         headeraddr+=4;
01333       }
01334
01335       /* Get tick */
01336       tickstart = HAL_GetTick();
01337
01338       while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
01339       {
01340       /* Check for the Timeout */
01341         if(Timeout != HAL_MAX_DELAY)
01342         {
01343           if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01344           {
01345             /* Change state */
01346             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01347
01348             /* Process Unlocked */
01349             __HAL_UNLOCK(hcryp);
01350
01351             return HAL_TIMEOUT;
01352           }
01353         }
01354       }
01355     }
01356     /* Save formatted counter into the scratch buffer pScratch */
01357     for(loopcounter = 0; (loopcounter < 16); loopcounter++)
01358     {
01359       hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
01360     }
01361     /* Reset bit 0 */
01362     hcryp->Init.pScratch[15] &= 0xfe;
01363     /* Select payload phase once the header phase is performed */
01364     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01365
01366     /* Flush FIFO */
01367     __HAL_CRYP_FIFO_FLUSH(hcryp);
01368
01369     /* Enable the CRYP peripheral */
01370     __HAL_CRYP_ENABLE(hcryp);
01371
01372     /* Set the phase */
01373     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01374   }
01375
01376   /* Write Plain Data and Get Cypher Data */
01377   if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
01378   {
01379     return HAL_TIMEOUT;
01380   }
01381
01382   /* Change the CRYP peripheral state */
01383   hcryp->State = HAL_CRYP_STATE_READY;
01384
01385   /* Process Unlocked */
01386   __HAL_UNLOCK(hcryp);
01387
01388   /* Return function status */
01389   return HAL_OK;
01390 }
01391
01392 /**
01393   * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using IT.
01394   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01395   *         the configuration information for CRYP module
01396   * @param  pPlainData: Pointer to the plaintext buffer
01397   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01398   * @param  pCypherData: Pointer to the cyphertext buffer
01399   * @retval HAL status
01400   */
01401 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01402 {
01403   uint32_t tickstart = 0;
01404   uint32_t inputaddr;
01405   uint32_t outputaddr;
01406
01407   if(hcryp->State == HAL_CRYP_STATE_READY)
01408   {
01409     /* Process Locked */
01410     __HAL_LOCK(hcryp);
01411
01412     /* Get the buffer addresses and sizes */
01413     hcryp->CrypInCount = Size;
01414     hcryp->pCrypInBuffPtr = pPlainData;
01415     hcryp->pCrypOutBuffPtr = pCypherData;
01416     hcryp->CrypOutCount = Size;
01417
01418     /* Change the CRYP peripheral state */
01419     hcryp->State = HAL_CRYP_STATE_BUSY;
01420
01421     /* Check if initialization phase has already been performed */
01422     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01423     {
01424       /* Set the key */
01425       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01426
01427       /* Set the CRYP peripheral in AES GCM mode */
01428       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
01429
01430       /* Set the Initialization Vector */
01431       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
01432
01433       /* Flush FIFO */
01434       __HAL_CRYP_FIFO_FLUSH(hcryp);
01435
01436       /* Enable CRYP to start the init phase */
01437       __HAL_CRYP_ENABLE(hcryp);
01438
01439      /* Get tick */
01440      tickstart = HAL_GetTick();
01441
01442       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01443       {
01444         /* Check for the Timeout */
01445
01446         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01447         {
01448           /* Change state */
01449           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01450
01451           /* Process Unlocked */
01452           __HAL_UNLOCK(hcryp);
01453
01454           return HAL_TIMEOUT;
01455
01456         }
01457       }
01458
01459       /* Set the header phase */
01460       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
01461       {
01462         return HAL_TIMEOUT;
01463       }
01464       /* Disable the CRYP peripheral */
01465       __HAL_CRYP_DISABLE(hcryp);
01466
01467       /* Select payload phase once the header phase is performed */
01468       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01469
01470       /* Flush FIFO */
01471       __HAL_CRYP_FIFO_FLUSH(hcryp);
01472
01473       /* Set the phase */
01474       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01475     }
01476
01477     if(Size != 0)
01478     {
01479       /* Enable Interrupts */
01480       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01481       /* Enable the CRYP peripheral */
01482       __HAL_CRYP_ENABLE(hcryp);
01483     }
01484     else
01485     {
01486       /* Process Locked */
01487       __HAL_UNLOCK(hcryp);
01488       /* Change the CRYP state and phase */
01489       hcryp->State = HAL_CRYP_STATE_READY;
01490     }
01491     /* Return function status */
01492     return HAL_OK;
01493   }
01494   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01495   {
01496     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01497     /* Write the Input block in the IN FIFO */
01498     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01499     inputaddr+=4;
01500     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01501     inputaddr+=4;
01502     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01503     inputaddr+=4;
01504     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01505     hcryp->pCrypInBuffPtr += 16;
01506     hcryp->CrypInCount -= 16;
01507     if(hcryp->CrypInCount == 0)
01508     {
01509       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01510       /* Call the Input data transfer complete callback */
01511       HAL_CRYP_InCpltCallback(hcryp);
01512     }
01513   }
01514   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01515   {
01516     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01517     /* Read the Output block from the Output FIFO */
01518     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01519     outputaddr+=4;
01520     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01521     outputaddr+=4;
01522     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01523     outputaddr+=4;
01524     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01525     hcryp->pCrypOutBuffPtr += 16;
01526     hcryp->CrypOutCount -= 16;
01527     if(hcryp->CrypOutCount == 0)
01528     {
01529       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01530       /* Process Unlocked */
01531       __HAL_UNLOCK(hcryp);
01532       /* Change the CRYP peripheral state */
01533       hcryp->State = HAL_CRYP_STATE_READY;
01534       /* Call Input transfer complete callback */
01535       HAL_CRYP_OutCpltCallback(hcryp);
01536     }
01537   }
01538
01539   /* Return function status */
01540   return HAL_OK;
01541 }
01542
01543 /**
01544   * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
01545   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01546   *         the configuration information for CRYP module
01547   * @param  pPlainData: Pointer to the plaintext buffer
01548   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01549   * @param  pCypherData: Pointer to the cyphertext buffer
01550   * @retval HAL status
01551   */
01552 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01553 {
01554   uint32_t tickstart = 0;
01555   uint32_t inputaddr;
01556   uint32_t outputaddr;
01557
01558   uint32_t headersize = hcryp->Init.HeaderSize;
01559   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
01560   uint32_t loopcounter = 0;
01561   uint32_t bufferidx = 0;
01562   uint8_t blockb0[16] = {0};/* Block B0 */
01563   uint8_t ctr[16] = {0}; /* Counter */
01564   uint32_t b0addr = (uint32_t)blockb0;
01565
01566   if(hcryp->State == HAL_CRYP_STATE_READY)
01567   {
01568     /* Process Locked */
01569     __HAL_LOCK(hcryp);
01570
01571     hcryp->CrypInCount = Size;
01572     hcryp->pCrypInBuffPtr = pPlainData;
01573     hcryp->pCrypOutBuffPtr = pCypherData;
01574     hcryp->CrypOutCount = Size;
01575
01576     /* Change the CRYP peripheral state */
01577     hcryp->State = HAL_CRYP_STATE_BUSY;
01578
01579     /* Check if initialization phase has already been performed */
01580     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01581     {
01582       /************************ Formatting the header block *******************/
01583       if(headersize != 0)
01584       {
01585         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
01586         if(headersize < 65280)
01587         {
01588           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
01589           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
01590           headersize += 2;
01591         }
01592         else
01593         {
01594           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
01595           hcryp->Init.pScratch[bufferidx++] = 0xFF;
01596           hcryp->Init.pScratch[bufferidx++] = 0xFE;
01597           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
01598           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
01599           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
01600           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
01601           headersize += 6;
01602         }
01603         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
01604         for(loopcounter = 0; loopcounter < headersize; loopcounter++)
01605         {
01606           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
01607         }
01608         /* Check if the header size is modulo 16 */
01609         if ((headersize % 16) != 0)
01610         {
01611           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
01612           for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
01613           {
01614             hcryp->Init.pScratch[loopcounter] = 0;
01615           }
01616           /* Set the header size to modulo 16 */
01617           headersize = ((headersize/16) + 1) * 16;
01618         }
01619         /* Set the pointer headeraddr to hcryp->Init.pScratch */
01620         headeraddr = (uint32_t)hcryp->Init.pScratch;
01621       }
01622       /*********************** Formatting the block B0 ************************/
01623       if(headersize != 0)
01624       {
01625         blockb0[0] = 0x40;
01626       }
01627       /* Flags byte */
01628       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
01629       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
01630       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
01631
01632       for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
01633       {
01634         blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
01635       }
01636       for ( ; loopcounter < 13; loopcounter++)
01637       {
01638         blockb0[loopcounter+1] = 0;
01639       }
01640
01641       blockb0[14] = (Size >> 8);
01642       blockb0[15] = (Size & 0xFF);
01643
01644       /************************* Formatting the initial counter ***************/
01645       /* Byte 0:
01646          Bits 7 and 6 are reserved and shall be set to 0
01647          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
01648          blocks are distinct from B0
01649          Bits 0, 1, and 2 contain the same encoding of q as in B0
01650       */
01651       ctr[0] = blockb0[0] & 0x07;
01652       /* byte 1 to NonceSize is the IV (Nonce) */
01653       for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
01654       {
01655         ctr[loopcounter] = blockb0[loopcounter];
01656       }
01657       /* Set the LSB to 1 */
01658       ctr[15] |= 0x01;
01659
01660       /* Set the key */
01661       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01662
01663       /* Set the CRYP peripheral in AES CCM mode */
01664       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
01665
01666       /* Set the Initialization Vector */
01667       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
01668
01669       /* Select init phase */
01670       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
01671
01672       b0addr = (uint32_t)blockb0;
01673       /* Write the blockb0 block in the IN FIFO */
01674       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01675       b0addr+=4;
01676       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01677       b0addr+=4;
01678       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01679       b0addr+=4;
01680       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01681
01682       /* Enable the CRYP peripheral */
01683       __HAL_CRYP_ENABLE(hcryp);
01684
01685      /* Get tick */
01686      tickstart = HAL_GetTick();
01687
01688       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01689       {
01690         /* Check for the Timeout */
01691         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01692         {
01693           /* Change state */
01694           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01695
01696           /* Process Unlocked */
01697           __HAL_UNLOCK(hcryp);
01698
01699           return HAL_TIMEOUT;
01700         }
01701       }
01702       /***************************** Header phase *****************************/
01703       if(headersize != 0)
01704       {
01705         /* Select header phase */
01706         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
01707
01708         /* Enable Crypto processor */
01709         __HAL_CRYP_ENABLE(hcryp);
01710
01711         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
01712         {
01713          /* Get tick */
01714          tickstart = HAL_GetTick();
01715
01716           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
01717           {
01718             /* Check for the Timeout */
01719             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01720             {
01721               /* Change state */
01722               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01723
01724               /* Process Unlocked */
01725               __HAL_UNLOCK(hcryp);
01726
01727               return HAL_TIMEOUT;
01728             }
01729           }
01730           /* Write the header block in the IN FIFO */
01731           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01732           headeraddr+=4;
01733           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01734           headeraddr+=4;
01735           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01736           headeraddr+=4;
01737           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01738           headeraddr+=4;
01739         }
01740
01741         /* Get tick */
01742         tickstart = HAL_GetTick();
01743
01744         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
01745         {
01746           /* Check for the Timeout */
01747           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01748           {
01749             /* Change state */
01750             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01751
01752             /* Process Unlocked */
01753             __HAL_UNLOCK(hcryp);
01754
01755             return HAL_TIMEOUT;
01756           }
01757         }
01758       }
01759       /* Save formatted counter into the scratch buffer pScratch */
01760       for(loopcounter = 0; (loopcounter < 16); loopcounter++)
01761       {
01762         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
01763       }
01764       /* Reset bit 0 */
01765       hcryp->Init.pScratch[15] &= 0xfe;
01766
01767       /* Select payload phase once the header phase is performed */
01768       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01769
01770       /* Flush FIFO */
01771       __HAL_CRYP_FIFO_FLUSH(hcryp);
01772
01773       /* Set the phase */
01774       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01775     }
01776
01777     if(Size != 0)
01778     {
01779       /* Enable Interrupts */
01780       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01781       /* Enable the CRYP peripheral */
01782       __HAL_CRYP_ENABLE(hcryp);
01783     }
01784     else
01785     {
01786       /* Change the CRYP state and phase */
01787       hcryp->State = HAL_CRYP_STATE_READY;
01788     }
01789
01790     /* Return function status */
01791     return HAL_OK;
01792   }
01793   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01794   {
01795     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01796     /* Write the Input block in the IN FIFO */
01797     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01798     inputaddr+=4;
01799     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01800     inputaddr+=4;
01801     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01802     inputaddr+=4;
01803     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01804     hcryp->pCrypInBuffPtr += 16;
01805     hcryp->CrypInCount -= 16;
01806     if(hcryp->CrypInCount == 0)
01807     {
01808       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01809       /* Call Input transfer complete callback */
01810       HAL_CRYP_InCpltCallback(hcryp);
01811     }
01812   }
01813   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01814   {
01815     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01816     /* Read the Output block from the Output FIFO */
01817     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01818     outputaddr+=4;
01819     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01820     outputaddr+=4;
01821     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01822     outputaddr+=4;
01823     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01824     hcryp->pCrypOutBuffPtr += 16;
01825     hcryp->CrypOutCount -= 16;
01826     if(hcryp->CrypOutCount == 0)
01827     {
01828       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01829       /* Process Unlocked */
01830       __HAL_UNLOCK(hcryp);
01831       /* Change the CRYP peripheral state */
01832       hcryp->State = HAL_CRYP_STATE_READY;
01833       /* Call Input transfer complete callback */
01834       HAL_CRYP_OutCpltCallback(hcryp);
01835     }
01836   }
01837
01838   /* Return function status */
01839   return HAL_OK;
01840 }
01841
01842 /**
01843   * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using IT.
01844   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01845   *         the configuration information for CRYP module
01846   * @param  pCypherData: Pointer to the cyphertext buffer
01847   * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
01848   * @param  pPlainData: Pointer to the plaintext buffer
01849   * @retval HAL status
01850   */
01851 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01852 {
01853   uint32_t tickstart = 0;
01854   uint32_t inputaddr;
01855   uint32_t outputaddr;
01856
01857   if(hcryp->State == HAL_CRYP_STATE_READY)
01858   {
01859     /* Process Locked */
01860     __HAL_LOCK(hcryp);
01861
01862     /* Get the buffer addresses and sizes */
01863     hcryp->CrypInCount = Size;
01864     hcryp->pCrypInBuffPtr = pCypherData;
01865     hcryp->pCrypOutBuffPtr = pPlainData;
01866     hcryp->CrypOutCount = Size;
01867
01868     /* Change the CRYP peripheral state */
01869     hcryp->State = HAL_CRYP_STATE_BUSY;
01870
01871     /* Check if initialization phase has already been performed */
01872     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01873     {
01874       /* Set the key */
01875       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01876
01877       /* Set the CRYP peripheral in AES GCM decryption mode */
01878       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
01879
01880       /* Set the Initialization Vector */
01881       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
01882
01883       /* Flush FIFO */
01884       __HAL_CRYP_FIFO_FLUSH(hcryp);
01885
01886       /* Enable CRYP to start the init phase */
01887       __HAL_CRYP_ENABLE(hcryp);
01888
01889         /* Get tick */
01890         tickstart = HAL_GetTick();
01891
01892       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01893       {
01894         /* Check for the Timeout */
01895         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01896         {
01897           /* Change state */
01898           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01899
01900           /* Process Unlocked */
01901           __HAL_UNLOCK(hcryp);
01902
01903           return HAL_TIMEOUT;
01904         }
01905       }
01906
01907       /* Set the header phase */
01908       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
01909       {
01910         return HAL_TIMEOUT;
01911       }
01912       /* Disable the CRYP peripheral */
01913       __HAL_CRYP_DISABLE(hcryp);
01914
01915       /* Select payload phase once the header phase is performed */
01916       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01917
01918       /* Set the phase */
01919       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01920     }
01921
01922     if(Size != 0)
01923     {
01924       /* Enable Interrupts */
01925       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01926       /* Enable the CRYP peripheral */
01927       __HAL_CRYP_ENABLE(hcryp);
01928     }
01929     else
01930     {
01931       /* Process Locked */
01932       __HAL_UNLOCK(hcryp);
01933       /* Change the CRYP state and phase */
01934       hcryp->State = HAL_CRYP_STATE_READY;
01935     }
01936
01937     /* Return function status */
01938     return HAL_OK;
01939   }
01940   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01941   {
01942     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01943     /* Write the Input block in the IN FIFO */
01944     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01945     inputaddr+=4;
01946     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01947     inputaddr+=4;
01948     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01949     inputaddr+=4;
01950     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01951     hcryp->pCrypInBuffPtr += 16;
01952     hcryp->CrypInCount -= 16;
01953     if(hcryp->CrypInCount == 0)
01954     {
01955       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01956       /* Call the Input data transfer complete callback */
01957       HAL_CRYP_InCpltCallback(hcryp);
01958     }
01959   }
01960   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01961   {
01962     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01963     /* Read the Output block from the Output FIFO */
01964     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01965     outputaddr+=4;
01966     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01967     outputaddr+=4;
01968     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01969     outputaddr+=4;
01970     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01971     hcryp->pCrypOutBuffPtr += 16;
01972     hcryp->CrypOutCount -= 16;
01973     if(hcryp->CrypOutCount == 0)
01974     {
01975       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01976       /* Process Unlocked */
01977       __HAL_UNLOCK(hcryp);
01978       /* Change the CRYP peripheral state */
01979       hcryp->State = HAL_CRYP_STATE_READY;
01980       /* Call Input transfer complete callback */
01981       HAL_CRYP_OutCpltCallback(hcryp);
01982     }
01983   }
01984
01985   /* Return function status */
01986   return HAL_OK;
01987 }
01988
01989 /**
01990   * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
01991   *         then decrypted pCypherData. The cypher data are available in pPlainData.
01992   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01993   *         the configuration information for CRYP module
01994   * @param  pCypherData: Pointer to the cyphertext buffer
01995   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01996   * @param  pPlainData: Pointer to the plaintext buffer
01997   * @retval HAL status
01998   */
01999 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02000 {
02001   uint32_t inputaddr;
02002   uint32_t outputaddr;
02003   uint32_t tickstart = 0;
02004   uint32_t headersize = hcryp->Init.HeaderSize;
02005   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
02006   uint32_t loopcounter = 0;
02007   uint32_t bufferidx = 0;
02008   uint8_t blockb0[16] = {0};/* Block B0 */
02009   uint8_t ctr[16] = {0}; /* Counter */
02010   uint32_t b0addr = (uint32_t)blockb0;
02011
02012   if(hcryp->State == HAL_CRYP_STATE_READY)
02013   {
02014     /* Process Locked */
02015     __HAL_LOCK(hcryp);
02016
02017     hcryp->CrypInCount = Size;
02018     hcryp->pCrypInBuffPtr = pCypherData;
02019     hcryp->pCrypOutBuffPtr = pPlainData;
02020     hcryp->CrypOutCount = Size;
02021
02022     /* Change the CRYP peripheral state */
02023     hcryp->State = HAL_CRYP_STATE_BUSY;
02024
02025     /* Check if initialization phase has already been performed */
02026     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02027     {
02028       /************************ Formatting the header block *******************/
02029       if(headersize != 0)
02030       {
02031         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
02032         if(headersize < 65280)
02033         {
02034           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
02035           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
02036           headersize += 2;
02037         }
02038         else
02039         {
02040           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
02041           hcryp->Init.pScratch[bufferidx++] = 0xFF;
02042           hcryp->Init.pScratch[bufferidx++] = 0xFE;
02043           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
02044           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
02045           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
02046           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
02047           headersize += 6;
02048         }
02049         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
02050         for(loopcounter = 0; loopcounter < headersize; loopcounter++)
02051         {
02052           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
02053         }
02054         /* Check if the header size is modulo 16 */
02055         if ((headersize % 16) != 0)
02056         {
02057           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
02058           for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
02059           {
02060             hcryp->Init.pScratch[loopcounter] = 0;
02061           }
02062           /* Set the header size to modulo 16 */
02063           headersize = ((headersize/16) + 1) * 16;
02064         }
02065         /* Set the pointer headeraddr to hcryp->Init.pScratch */
02066         headeraddr = (uint32_t)hcryp->Init.pScratch;
02067       }
02068       /*********************** Formatting the block B0 ************************/
02069       if(headersize != 0)
02070       {
02071         blockb0[0] = 0x40;
02072       }
02073       /* Flags byte */
02074       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
02075       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
02076       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
02077
02078       for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
02079       {
02080         blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
02081       }
02082       for ( ; loopcounter < 13; loopcounter++)
02083       {
02084         blockb0[loopcounter+1] = 0;
02085       }
02086
02087       blockb0[14] = (Size >> 8);
02088       blockb0[15] = (Size & 0xFF);
02089
02090       /************************* Formatting the initial counter ***************/
02091       /* Byte 0:
02092          Bits 7 and 6 are reserved and shall be set to 0
02093          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
02094          blocks are distinct from B0
02095          Bits 0, 1, and 2 contain the same encoding of q as in B0
02096       */
02097       ctr[0] = blockb0[0] & 0x07;
02098       /* byte 1 to NonceSize is the IV (Nonce) */
02099       for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
02100       {
02101         ctr[loopcounter] = blockb0[loopcounter];
02102       }
02103       /* Set the LSB to 1 */
02104       ctr[15] |= 0x01;
02105
02106       /* Set the key */
02107       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02108
02109       /* Set the CRYP peripheral in AES CCM mode */
02110       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
02111
02112       /* Set the Initialization Vector */
02113       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
02114
02115       /* Select init phase */
02116       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02117
02118       b0addr = (uint32_t)blockb0;
02119       /* Write the blockb0 block in the IN FIFO */
02120       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02121       b0addr+=4;
02122       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02123       b0addr+=4;
02124       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02125       b0addr+=4;
02126       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02127
02128       /* Enable the CRYP peripheral */
02129       __HAL_CRYP_ENABLE(hcryp);
02130
02131       /* Get tick */
02132       tickstart = HAL_GetTick();
02133
02134       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02135       {
02136         /* Check for the Timeout */
02137         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02138         {
02139           /* Change state */
02140           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02141
02142           /* Process Unlocked */
02143           __HAL_UNLOCK(hcryp);
02144
02145           return HAL_TIMEOUT;
02146         }
02147       }
02148       /***************************** Header phase *****************************/
02149       if(headersize != 0)
02150       {
02151         /* Select header phase */
02152         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02153
02154         /* Enable Crypto processor */
02155         __HAL_CRYP_ENABLE(hcryp);
02156
02157         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
02158         {
02159          /* Get tick */
02160          tickstart = HAL_GetTick();
02161
02162           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
02163           {
02164             /* Check for the Timeout */
02165             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02166             {
02167               /* Change state */
02168               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02169
02170               /* Process Unlocked */
02171               __HAL_UNLOCK(hcryp);
02172
02173               return HAL_TIMEOUT;
02174             }
02175           }
02176           /* Write the header block in the IN FIFO */
02177           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02178           headeraddr+=4;
02179           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02180           headeraddr+=4;
02181           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02182           headeraddr+=4;
02183           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02184           headeraddr+=4;
02185         }
02186
02187         /* Get tick */
02188         tickstart = HAL_GetTick();
02189
02190         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
02191         {
02192           /* Check for the Timeout */
02193           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02194           {
02195             /* Change state */
02196             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02197
02198             /* Process Unlocked */
02199             __HAL_UNLOCK(hcryp);
02200
02201             return HAL_TIMEOUT;
02202           }
02203         }
02204       }
02205       /* Save formatted counter into the scratch buffer pScratch */
02206       for(loopcounter = 0; (loopcounter < 16); loopcounter++)
02207       {
02208         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
02209       }
02210       /* Reset bit 0 */
02211       hcryp->Init.pScratch[15] &= 0xfe;
02212       /* Select payload phase once the header phase is performed */
02213       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02214
02215       /* Flush FIFO */
02216       __HAL_CRYP_FIFO_FLUSH(hcryp);
02217
02218       /* Set the phase */
02219       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02220     }
02221
02222     /* Enable Interrupts */
02223     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02224
02225     /* Enable the CRYP peripheral */
02226     __HAL_CRYP_ENABLE(hcryp);
02227
02228     /* Return function status */
02229     return HAL_OK;
02230   }
02231   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02232   {
02233     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02234     /* Write the Input block in the IN FIFO */
02235     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02236     inputaddr+=4;
02237     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02238     inputaddr+=4;
02239     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
02240     inputaddr+=4;
02241     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02242     hcryp->pCrypInBuffPtr += 16;
02243     hcryp->CrypInCount -= 16;
02244     if(hcryp->CrypInCount == 0)
02245     {
02246       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02247       /* Call the Input data transfer complete callback */
02248       HAL_CRYP_InCpltCallback(hcryp);
02249     }
02250   }
02251   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02252   {
02253     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02254     /* Read the Output block from the Output FIFO */
02255     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02256     outputaddr+=4;
02257     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02258     outputaddr+=4;
02259     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02260     outputaddr+=4;
02261     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02262     hcryp->pCrypOutBuffPtr += 16;
02263     hcryp->CrypOutCount -= 16;
02264     if(hcryp->CrypOutCount == 0)
02265     {
02266       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02267       /* Process Unlocked */
02268       __HAL_UNLOCK(hcryp);
02269       /* Change the CRYP peripheral state */
02270       hcryp->State = HAL_CRYP_STATE_READY;
02271       /* Call Input transfer complete callback */
02272       HAL_CRYP_OutCpltCallback(hcryp);
02273     }
02274   }
02275
02276   /* Return function status */
02277   return HAL_OK;
02278 }
02279
02280 /**
02281   * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
02282   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02283   *         the configuration information for CRYP module
02284   * @param  pPlainData: Pointer to the plaintext buffer
02285   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02286   * @param  pCypherData: Pointer to the cyphertext buffer
02287   * @retval HAL status
02288   */
02289 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02290 {
02291   uint32_t tickstart = 0;
02292   uint32_t inputaddr;
02293   uint32_t outputaddr;
02294
02295   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02296   {
02297     /* Process Locked */
02298     __HAL_LOCK(hcryp);
02299
02300     inputaddr  = (uint32_t)pPlainData;
02301     outputaddr = (uint32_t)pCypherData;
02302
02303     /* Change the CRYP peripheral state */
02304     hcryp->State = HAL_CRYP_STATE_BUSY;
02305
02306     /* Check if initialization phase has already been performed */
02307     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02308     {
02309       /* Set the key */
02310       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02311
02312       /* Set the CRYP peripheral in AES GCM mode */
02313       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
02314
02315       /* Set the Initialization Vector */
02316       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
02317
02318       /* Flush FIFO */
02319       __HAL_CRYP_FIFO_FLUSH(hcryp);
02320
02321       /* Enable CRYP to start the init phase */
02322       __HAL_CRYP_ENABLE(hcryp);
02323
02324       /* Get tick */
02325       tickstart = HAL_GetTick();
02326
02327       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02328       {
02329         /* Check for the Timeout */
02330         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02331         {
02332           /* Change state */
02333           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02334
02335           /* Process Unlocked */
02336           __HAL_UNLOCK(hcryp);
02337
02338           return HAL_TIMEOUT;
02339         }
02340       }
02341       /* Flush FIFO */
02342       __HAL_CRYP_FIFO_FLUSH(hcryp);
02343
02344       /* Set the header phase */
02345       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
02346       {
02347         return HAL_TIMEOUT;
02348       }
02349       /* Disable the CRYP peripheral */
02350       __HAL_CRYP_DISABLE(hcryp);
02351
02352       /* Select payload phase once the header phase is performed */
02353       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02354
02355       /* Flush FIFO */
02356       __HAL_CRYP_FIFO_FLUSH(hcryp);
02357
02358       /* Set the phase */
02359       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02360     }
02361
02362     /* Set the input and output addresses and start DMA transfer */
02363     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02364
02365     /* Unlock process */
02366     __HAL_UNLOCK(hcryp);
02367
02368     /* Return function status */
02369     return HAL_OK;
02370   }
02371   else
02372   {
02373     return HAL_ERROR;
02374   }
02375 }
02376
02377 /**
02378   * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
02379   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02380   *         the configuration information for CRYP module
02381   * @param  pPlainData: Pointer to the plaintext buffer
02382   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02383   * @param  pCypherData: Pointer to the cyphertext buffer
02384   * @retval HAL status
02385   */
02386 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02387 {
02388   uint32_t tickstart = 0;
02389   uint32_t inputaddr;
02390   uint32_t outputaddr;
02391   uint32_t headersize;
02392   uint32_t headeraddr;
02393   uint32_t loopcounter = 0;
02394   uint32_t bufferidx = 0;
02395   uint8_t blockb0[16] = {0};/* Block B0 */
02396   uint8_t ctr[16] = {0}; /* Counter */
02397   uint32_t b0addr = (uint32_t)blockb0;
02398
02399   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02400   {
02401     /* Process Locked */
02402     __HAL_LOCK(hcryp);
02403
02404     inputaddr  = (uint32_t)pPlainData;
02405     outputaddr = (uint32_t)pCypherData;
02406
02407     headersize = hcryp->Init.HeaderSize;
02408     headeraddr = (uint32_t)hcryp->Init.Header;
02409
02410     hcryp->CrypInCount = Size;
02411     hcryp->pCrypInBuffPtr = pPlainData;
02412     hcryp->pCrypOutBuffPtr = pCypherData;
02413     hcryp->CrypOutCount = Size;
02414
02415     /* Change the CRYP peripheral state */
02416     hcryp->State = HAL_CRYP_STATE_BUSY;
02417
02418     /* Check if initialization phase has already been performed */
02419     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02420     {
02421       /************************ Formatting the header block *******************/
02422       if(headersize != 0)
02423       {
02424         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
02425         if(headersize < 65280)
02426         {
02427           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
02428           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
02429           headersize += 2;
02430         }
02431         else
02432         {
02433           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
02434           hcryp->Init.pScratch[bufferidx++] = 0xFF;
02435           hcryp->Init.pScratch[bufferidx++] = 0xFE;
02436           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
02437           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
02438           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
02439           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
02440           headersize += 6;
02441         }
02442         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
02443         for(loopcounter = 0; loopcounter < headersize; loopcounter++)
02444         {
02445           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
02446         }
02447         /* Check if the header size is modulo 16 */
02448         if ((headersize % 16) != 0)
02449         {
02450           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
02451           for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
02452           {
02453             hcryp->Init.pScratch[loopcounter] = 0;
02454           }
02455           /* Set the header size to modulo 16 */
02456           headersize = ((headersize/16) + 1) * 16;
02457         }
02458         /* Set the pointer headeraddr to hcryp->Init.pScratch */
02459         headeraddr = (uint32_t)hcryp->Init.pScratch;
02460       }
02461       /*********************** Formatting the block B0 ************************/
02462       if(headersize != 0)
02463       {
02464         blockb0[0] = 0x40;
02465       }
02466       /* Flags byte */
02467       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
02468       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
02469       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
02470
02471       for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
02472       {
02473         blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
02474       }
02475       for ( ; loopcounter < 13; loopcounter++)
02476       {
02477         blockb0[loopcounter+1] = 0;
02478       }
02479
02480       blockb0[14] = (Size >> 8);
02481       blockb0[15] = (Size & 0xFF);
02482
02483       /************************* Formatting the initial counter ***************/
02484       /* Byte 0:
02485          Bits 7 and 6 are reserved and shall be set to 0
02486          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
02487          blocks are distinct from B0
02488          Bits 0, 1, and 2 contain the same encoding of q as in B0
02489       */
02490       ctr[0] = blockb0[0] & 0x07;
02491       /* byte 1 to NonceSize is the IV (Nonce) */
02492       for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
02493       {
02494         ctr[loopcounter] = blockb0[loopcounter];
02495       }
02496       /* Set the LSB to 1 */
02497       ctr[15] |= 0x01;
02498
02499       /* Set the key */
02500       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02501
02502       /* Set the CRYP peripheral in AES CCM mode */
02503       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
02504
02505       /* Set the Initialization Vector */
02506       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
02507
02508       /* Select init phase */
02509       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02510
02511       b0addr = (uint32_t)blockb0;
02512       /* Write the blockb0 block in the IN FIFO */
02513       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02514       b0addr+=4;
02515       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02516       b0addr+=4;
02517       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02518       b0addr+=4;
02519       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02520
02521       /* Enable the CRYP peripheral */
02522       __HAL_CRYP_ENABLE(hcryp);
02523
02524       /* Get tick */
02525       tickstart = HAL_GetTick();
02526
02527       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02528       {
02529         /* Check for the Timeout */
02530         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02531         {
02532           /* Change state */
02533           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02534
02535           /* Process Unlocked */
02536           __HAL_UNLOCK(hcryp);
02537
02538           return HAL_TIMEOUT;
02539         }
02540       }
02541       /***************************** Header phase *****************************/
02542       if(headersize != 0)
02543       {
02544         /* Select header phase */
02545         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02546
02547         /* Enable Crypto processor */
02548         __HAL_CRYP_ENABLE(hcryp);
02549
02550         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
02551         {
02552          /* Get tick */
02553          tickstart = HAL_GetTick();
02554
02555           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
02556           {
02557             /* Check for the Timeout */
02558             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02559             {
02560               /* Change state */
02561               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02562
02563               /* Process Unlocked */
02564               __HAL_UNLOCK(hcryp);
02565
02566               return HAL_TIMEOUT;
02567             }
02568           }
02569           /* Write the header block in the IN FIFO */
02570           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02571           headeraddr+=4;
02572           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02573           headeraddr+=4;
02574           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02575           headeraddr+=4;
02576           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02577           headeraddr+=4;
02578         }
02579
02580         /* Get tick */
02581         tickstart = HAL_GetTick();
02582
02583         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
02584         {
02585           /* Check for the Timeout */
02586           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02587           {
02588             /* Change state */
02589             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02590
02591             /* Process Unlocked */
02592             __HAL_UNLOCK(hcryp);
02593
02594             return HAL_TIMEOUT;
02595           }
02596         }
02597       }
02598       /* Save formatted counter into the scratch buffer pScratch */
02599       for(loopcounter = 0; (loopcounter < 16); loopcounter++)
02600       {
02601         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
02602       }
02603       /* Reset bit 0 */
02604       hcryp->Init.pScratch[15] &= 0xfe;
02605
02606       /* Select payload phase once the header phase is performed */
02607       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02608
02609       /* Flush FIFO */
02610       __HAL_CRYP_FIFO_FLUSH(hcryp);
02611
02612       /* Set the phase */
02613       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02614     }
02615
02616     /* Set the input and output addresses and start DMA transfer */
02617     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02618
02619     /* Unlock process */
02620     __HAL_UNLOCK(hcryp);
02621
02622     /* Return function status */
02623     return HAL_OK;
02624   }
02625   else
02626   {
02627     return HAL_ERROR;
02628   }
02629 }
02630
02631 /**
02632   * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
02633   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02634   *         the configuration information for CRYP module
02635   * @param  pCypherData: Pointer to the cyphertext buffer.
02636   * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
02637   * @param  pPlainData: Pointer to the plaintext buffer
02638   * @retval HAL status
02639   */
02640 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02641 {
02642   uint32_t tickstart = 0;
02643   uint32_t inputaddr;
02644   uint32_t outputaddr;
02645
02646   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02647   {
02648     /* Process Locked */
02649     __HAL_LOCK(hcryp);
02650
02651     inputaddr  = (uint32_t)pCypherData;
02652     outputaddr = (uint32_t)pPlainData;
02653
02654     /* Change the CRYP peripheral state */
02655     hcryp->State = HAL_CRYP_STATE_BUSY;
02656
02657     /* Check if initialization phase has already been performed */
02658     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02659     {
02660       /* Set the key */
02661       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02662
02663       /* Set the CRYP peripheral in AES GCM decryption mode */
02664       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
02665
02666       /* Set the Initialization Vector */
02667       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
02668
02669       /* Enable CRYP to start the init phase */
02670       __HAL_CRYP_ENABLE(hcryp);
02671
02672       /* Get tick */
02673       tickstart = HAL_GetTick();
02674
02675       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02676       {
02677         /* Check for the Timeout */
02678         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02679         {
02680           /* Change state */
02681           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02682
02683           /* Process Unlocked */
02684           __HAL_UNLOCK(hcryp);
02685
02686           return HAL_TIMEOUT;
02687         }
02688       }
02689
02690       /* Set the header phase */
02691       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
02692       {
02693         return HAL_TIMEOUT;
02694       }
02695       /* Disable the CRYP peripheral */
02696       __HAL_CRYP_DISABLE(hcryp);
02697
02698       /* Select payload phase once the header phase is performed */
02699       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02700
02701       /* Set the phase */
02702       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02703     }
02704
02705     /* Set the input and output addresses and start DMA transfer */
02706     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02707
02708     /* Unlock process */
02709     __HAL_UNLOCK(hcryp);
02710
02711     /* Return function status */
02712     return HAL_OK;
02713   }
02714   else
02715   {
02716     return HAL_ERROR;
02717   }
02718 }
02719
02720 /**
02721   * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using DMA
02722   *         then decrypted pCypherData. The cypher data are available in pPlainData.
02723   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02724   *         the configuration information for CRYP module
02725   * @param  pCypherData: Pointer to the cyphertext buffer
02726   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02727   * @param  pPlainData: Pointer to the plaintext buffer
02728   * @retval HAL status
02729   */
02730 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02731 {
02732   uint32_t tickstart = 0;
02733   uint32_t inputaddr;
02734   uint32_t outputaddr;
02735   uint32_t headersize;
02736   uint32_t headeraddr;
02737   uint32_t loopcounter = 0;
02738   uint32_t bufferidx = 0;
02739   uint8_t blockb0[16] = {0};/* Block B0 */
02740   uint8_t ctr[16] = {0}; /* Counter */
02741   uint32_t b0addr = (uint32_t)blockb0;
02742
02743   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02744   {
02745     /* Process Locked */
02746     __HAL_LOCK(hcryp);
02747
02748     inputaddr  = (uint32_t)pCypherData;
02749     outputaddr = (uint32_t)pPlainData;
02750
02751     headersize = hcryp->Init.HeaderSize;
02752     headeraddr = (uint32_t)hcryp->Init.Header;
02753
02754     hcryp->CrypInCount = Size;
02755     hcryp->pCrypInBuffPtr = pCypherData;
02756     hcryp->pCrypOutBuffPtr = pPlainData;
02757     hcryp->CrypOutCount = Size;
02758
02759     /* Change the CRYP peripheral state */
02760     hcryp->State = HAL_CRYP_STATE_BUSY;
02761
02762     /* Check if initialization phase has already been performed */
02763     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02764     {
02765       /************************ Formatting the header block *******************/
02766       if(headersize != 0)
02767       {
02768         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
02769         if(headersize < 65280)
02770         {
02771           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
02772           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
02773           headersize += 2;
02774         }
02775         else
02776         {
02777           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
02778           hcryp->Init.pScratch[bufferidx++] = 0xFF;
02779           hcryp->Init.pScratch[bufferidx++] = 0xFE;
02780           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
02781           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
02782           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
02783           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
02784           headersize += 6;
02785         }
02786         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
02787         for(loopcounter = 0; loopcounter < headersize; loopcounter++)
02788         {
02789           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
02790         }
02791         /* Check if the header size is modulo 16 */
02792         if ((headersize % 16) != 0)
02793         {
02794           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
02795           for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
02796           {
02797             hcryp->Init.pScratch[loopcounter] = 0;
02798           }
02799           /* Set the header size to modulo 16 */
02800           headersize = ((headersize/16) + 1) * 16;
02801         }
02802         /* Set the pointer headeraddr to hcryp->Init.pScratch */
02803         headeraddr = (uint32_t)hcryp->Init.pScratch;
02804       }
02805       /*********************** Formatting the block B0 ************************/
02806       if(headersize != 0)
02807       {
02808         blockb0[0] = 0x40;
02809       }
02810       /* Flags byte */
02811       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
02812       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
02813       blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
02814
02815       for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
02816       {
02817         blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
02818       }
02819       for ( ; loopcounter < 13; loopcounter++)
02820       {
02821         blockb0[loopcounter+1] = 0;
02822       }
02823
02824       blockb0[14] = (Size >> 8);
02825       blockb0[15] = (Size & 0xFF);
02826
02827       /************************* Formatting the initial counter ***************/
02828       /* Byte 0:
02829          Bits 7 and 6 are reserved and shall be set to 0
02830          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
02831          blocks are distinct from B0
02832          Bits 0, 1, and 2 contain the same encoding of q as in B0
02833       */
02834       ctr[0] = blockb0[0] & 0x07;
02835       /* byte 1 to NonceSize is the IV (Nonce) */
02836       for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
02837       {
02838         ctr[loopcounter] = blockb0[loopcounter];
02839       }
02840       /* Set the LSB to 1 */
02841       ctr[15] |= 0x01;
02842
02843       /* Set the key */
02844       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02845
02846       /* Set the CRYP peripheral in AES CCM mode */
02847       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
02848
02849       /* Set the Initialization Vector */
02850       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
02851
02852       /* Select init phase */
02853       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02854
02855       b0addr = (uint32_t)blockb0;
02856       /* Write the blockb0 block in the IN FIFO */
02857       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02858       b0addr+=4;
02859       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02860       b0addr+=4;
02861       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02862       b0addr+=4;
02863       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02864
02865       /* Enable the CRYP peripheral */
02866       __HAL_CRYP_ENABLE(hcryp);
02867
02868       /* Get tick */
02869       tickstart = HAL_GetTick();
02870
02871       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02872       {
02873         /* Check for the Timeout */
02874
02875         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02876         {
02877           /* Change state */
02878           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02879
02880           /* Process Unlocked */
02881           __HAL_UNLOCK(hcryp);
02882
02883           return HAL_TIMEOUT;
02884
02885         }
02886       }
02887       /***************************** Header phase *****************************/
02888       if(headersize != 0)
02889       {
02890         /* Select header phase */
02891         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02892
02893         /* Enable Crypto processor */
02894         __HAL_CRYP_ENABLE(hcryp);
02895
02896         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
02897         {
02898          /* Get tick */
02899          tickstart = HAL_GetTick();
02900
02901           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
02902           {
02903             /* Check for the Timeout */
02904             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02905             {
02906               /* Change state */
02907               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02908
02909               /* Process Unlocked */
02910               __HAL_UNLOCK(hcryp);
02911
02912               return HAL_TIMEOUT;
02913             }
02914           }
02915           /* Write the header block in the IN FIFO */
02916           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02917           headeraddr+=4;
02918           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02919           headeraddr+=4;
02920           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02921           headeraddr+=4;
02922           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02923           headeraddr+=4;
02924         }
02925
02926         /* Get tick */
02927         tickstart = HAL_GetTick();
02928
02929         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
02930         {
02931           /* Check for the Timeout */
02932           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02933           {
02934             /* Change state */
02935             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02936
02937             /* Process Unlocked */
02938             __HAL_UNLOCK(hcryp);
02939
02940             return HAL_TIMEOUT;
02941           }
02942         }
02943       }
02944       /* Save formatted counter into the scratch buffer pScratch */
02945       for(loopcounter = 0; (loopcounter < 16); loopcounter++)
02946       {
02947         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
02948       }
02949       /* Reset bit 0 */
02950       hcryp->Init.pScratch[15] &= 0xfe;
02951       /* Select payload phase once the header phase is performed */
02952       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02953
02954       /* Flush FIFO */
02955       __HAL_CRYP_FIFO_FLUSH(hcryp);
02956
02957       /* Set the phase */
02958       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02959     }
02960     /* Set the input and output addresses and start DMA transfer */
02961     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02962
02963     /* Unlock process */
02964     __HAL_UNLOCK(hcryp);
02965
02966     /* Return function status */
02967     return HAL_OK;
02968   }
02969   else
02970   {
02971     return HAL_ERROR;
02972   }
02973 }
02974
02975 /**
02976   * @}
02977   */
02978
02979 /** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management
02980  *  @brief   CRYPEx IRQ handler.
02981  *
02982 @verbatim
02983   ==============================================================================
02984                 ##### CRYPEx IRQ handler management #####
02985   ==============================================================================
02986 [..]  This section provides CRYPEx IRQ handler function.
02987
02988 @endverbatim
02989   * @{
02990   */
02991
02992 /**
02993   * @brief  This function handles CRYPEx interrupt request.
02994   * @param  hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains
02995   *         the configuration information for CRYP module
02996   * @retval None
02997   */
02998 void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
02999 {
03000   switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
03001   {
03002   case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
03003     HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);
03004     break;
03005
03006   case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
03007     HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);
03008     break;
03009
03010   case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
03011     HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);
03012     break;
03013
03014   case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
03015     HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);
03016     break;
03017
03018   default:
03019     break;
03020   }
03021 }
03022
03023 /**
03024   * @}
03025   */
03026
03027 /**
03028   * @}
03029   */
03030 #endif /* HAL_CRYP_MODULE_ENABLED */
03031
03032 /**
03033   * @}
03034   */
03035 #endif /* STM32F756xx */
03036 /**
03037   * @}
03038   */
03039
03040 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_cryp_ex.h Source File

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stm32f7xx_hal_cryp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of CRYP HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_CRYP_EX_H
00040 #define __STM32F7xx_HAL_CRYP_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined (STM32F756xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup CRYPEx
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060
00061 /** @defgroup CRYPEx_Exported_Constants   CRYPEx Exported Constants
00062   * @{
00063   */
00064
00065 /** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
00066   * @{
00067   */
00068 #define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT   ((uint32_t)0x00080000)
00069 #define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT   ((uint32_t)0x00080004)
00070 #define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT   ((uint32_t)0x00080008)
00071 #define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT   ((uint32_t)0x0008000C)
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
00077   * @brief    The phases are relevant only to AES-GCM and AES-CCM
00078   * @{
00079   */
00080 #define CRYP_PHASE_INIT           ((uint32_t)0x00000000)
00081 #define CRYP_PHASE_HEADER         CRYP_CR_GCM_CCMPH_0
00082 #define CRYP_PHASE_PAYLOAD        CRYP_CR_GCM_CCMPH_1
00083 #define CRYP_PHASE_FINAL          CRYP_CR_GCM_CCMPH
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /* Exported macro ------------------------------------------------------------*/
00093 /** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Set the phase: Init, header, payload, final.
00099   *         This is relevant only for GCM and CCM modes.
00100   * @param  __HANDLE__: specifies the CRYP handle.
00101   * @param  __PHASE__: The phase.
00102   * @retval None
00103   */
00104 #define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
00105                                                         (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
00106                                                        }while(0)
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Exported functions --------------------------------------------------------*/
00113 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00114   * @{
00115   */
00116
00117 /** @addtogroup CRYPEx_Exported_Functions_Group1
00118   * @{
00119   */
00120
00121 /* AES encryption/decryption using polling  ***********************************/
00122 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00123 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00124 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
00125 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00126 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00127 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
00128
00129 /* AES encryption/decryption using interrupt  *********************************/
00130 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00131 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00132 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00133 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00134
00135 /* AES encryption/decryption using DMA  ***************************************/
00136 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00137 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00138 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00139 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00140
00141 /**
00142   * @}
00143   */
00144
00145 /** @addtogroup CRYPEx_Exported_Functions_Group2
00146   * @{
00147   */
00148
00149 void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
00150
00151 /**
00152   * @}
00153   */
00154
00155  /**
00156   * @}
00157   */
00158
00159
00160  /* Private types -------------------------------------------------------------*/
00161 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00162   * @{
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /* Private variables ---------------------------------------------------------*/
00170 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00171   * @{
00172   */
00173
00174 /**
00175   * @}
00176   */
00177
00178 /* Private constants ---------------------------------------------------------*/
00179 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00180   * @{
00181   */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /* Private macros ------------------------------------------------------------*/
00188 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00189   * @{
00190   */
00191
00192  /**
00193   * @}
00194   */
00195
00196 /* Private functions ---------------------------------------------------------*/
00197 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00198   * @{
00199   */
00200
00201 /**
00202   * @}
00203   */
00204
00205 /**
00206   * @}
00207   */
00208
00209 #endif /* STM32F756xx */
00210
00211 /**
00212   * @}
00213   */
00214
00215 #ifdef __cplusplus
00216 }
00217 #endif
00218
00219 #endif /* __STM32F7xx_HAL_CRYP_EX_H */
00220
00221 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac.c Source File

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stm32f7xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   *
00016   @verbatim
00017   ==============================================================================
00018                       ##### DAC Peripheral features #####
00019   ==============================================================================
00020     [..]
00021       *** DAC Channels ***
00022       ====================
00023     [..]
00024     The device integrates two 12-bit Digital Analog Converters that can
00025     be used independently or simultaneously (dual mode):
00026       (#) DAC channel1 with DAC_OUT1 (PA4) as output
00027       (#) DAC channel2 with DAC_OUT2 (PA5) as output
00028
00029       *** DAC Triggers ***
00030       ====================
00031     [..]
00032     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00033     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00034     [..]
00035     Digital to Analog conversion can be triggered by:
00036       (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
00037           The used pin (GPIOx_Pin9) must be configured in input mode.
00038
00039       (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
00040           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
00041
00042       (#) Software using DAC_TRIGGER_SOFTWARE
00043
00044       *** DAC Buffer mode feature ***
00045       ===============================
00046       [..]
00047       Each DAC channel integrates an output buffer that can be used to
00048       reduce the output impedance, and to drive external loads directly
00049       without having to add an external operational amplifier.
00050       To enable, the output buffer use
00051       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00052       [..]
00053       (@) Refer to the device datasheet for more details about output
00054           impedance value with and without output buffer.
00055
00056        *** DAC wave generation feature ***
00057        ===================================
00058        [..]
00059        Both DAC channels can be used to generate
00060          (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
00061          (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
00062
00063        *** DAC data format ***
00064        =======================
00065        [..]
00066        The DAC data format can be:
00067          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00068          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00069          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00070
00071        *** DAC data value to voltage correspondence ***
00072        ================================================
00073        [..]
00074        The analog output voltage on each DAC channel pin is determined
00075        by the following equation:
00076        DAC_OUTx = VREF+ * DOR / 4095
00077        with  DOR is the Data Output Register
00078           VEF+ is the input voltage reference (refer to the device datasheet)
00079         e.g. To set DAC_OUT1 to 0.7V, use
00080           Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00081
00082        *** DMA requests  ***
00083        =====================
00084        [..]
00085        A DMA1 request can be generated when an external trigger (but not
00086        a software trigger) occurs if DMA1 requests are enabled using
00087        HAL_DAC_Start_DMA()
00088        [..]
00089        DMA1 requests are mapped as following:
00090          (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
00091              already configured
00092          (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
00093              already configured
00094
00095     -@- For Dual mode and specific signal (Triangle and noise) generation please
00096         refer to Extension Features Driver description
00097
00098
00099                       ##### How to use this driver #####
00100   ==============================================================================
00101     [..]
00102       (+) DAC APB clock must be enabled to get write access to DAC
00103           registers using HAL_DAC_Init()
00104       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00105       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00106       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
00107
00108      *** Polling mode IO operation ***
00109      =================================
00110      [..]
00111        (+) Start the DAC peripheral using HAL_DAC_Start()
00112        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00113        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00114
00115
00116      *** DMA mode IO operation ***
00117      ==============================
00118      [..]
00119        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00120            of data to be transferred at each end of conversion
00121        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
00122            function is executed and user can add his own code by customization of function pointer
00123            HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
00124        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00125             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00126        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00127
00128
00129      *** DAC HAL driver macros list ***
00130      =============================================
00131      [..]
00132        Below the list of most used macros in DAC HAL driver.
00133
00134       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00135       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00136       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00137       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00138
00139      [..]
00140       (@) You can refer to the DAC HAL driver header file for more useful macros
00141
00142  @endverbatim
00143   ******************************************************************************
00144   * @attention
00145   *
00146   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00147   *
00148   * Redistribution and use in source and binary forms, with or without modification,
00149   * are permitted provided that the following conditions are met:
00150   *   1. Redistributions of source code must retain the above copyright notice,
00151   *      this list of conditions and the following disclaimer.
00152   *   2. Redistributions in binary form must reproduce the above copyright notice,
00153   *      this list of conditions and the following disclaimer in the documentation
00154   *      and/or other materials provided with the distribution.
00155   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00156   *      may be used to endorse or promote products derived from this software
00157   *      without specific prior written permission.
00158   *
00159   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00160   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00161   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00162   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00163   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00164   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00165   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00166   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00167   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00168   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00169   *
00170   ******************************************************************************
00171   */
00172
00173
00174 /* Includes ------------------------------------------------------------------*/
00175 #include "stm32f7xx_hal.h"
00176
00177 /** @addtogroup STM32F7xx_HAL_Driver
00178   * @{
00179   */
00180
00181 /** @defgroup DAC DAC
00182   * @brief DAC driver modules
00183   * @{
00184   */
00185
00186 #ifdef HAL_DAC_MODULE_ENABLED
00187
00188 /* Private typedef -----------------------------------------------------------*/
00189 /* Private define ------------------------------------------------------------*/
00190 /* Private macro -------------------------------------------------------------*/
00191 /* Private variables ---------------------------------------------------------*/
00192 /** @addtogroup DAC_Private_Functions
00193   * @{
00194   */
00195 /* Private function prototypes -----------------------------------------------*/
00196 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00197 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00198 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported functions --------------------------------------------------------*/
00204 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00205   * @{
00206   */
00207
00208 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00209  *  @brief    Initialization and Configuration functions
00210  *
00211 @verbatim
00212   ==============================================================================
00213               ##### Initialization and de-initialization functions #####
00214   ==============================================================================
00215     [..]  This section provides functions allowing to:
00216       (+) Initialize and configure the DAC.
00217       (+) De-initialize the DAC.
00218
00219 @endverbatim
00220   * @{
00221   */
00222
00223 /**
00224   * @brief  Initializes the DAC peripheral according to the specified parameters
00225   *         in the DAC_InitStruct.
00226   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00227   *         the configuration information for the specified DAC.
00228   * @retval HAL status
00229   */
00230 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
00231 {
00232   /* Check DAC handle */
00233   if(hdac == NULL)
00234   {
00235      return HAL_ERROR;
00236   }
00237   /* Check the parameters */
00238   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00239
00240   if(hdac->State == HAL_DAC_STATE_RESET)
00241   {
00242     /* Allocate lock resource and initialize it */
00243     hdac->Lock = HAL_UNLOCKED;
00244     /* Init the low level hardware */
00245     HAL_DAC_MspInit(hdac);
00246   }
00247
00248   /* Initialize the DAC state*/
00249   hdac->State = HAL_DAC_STATE_BUSY;
00250
00251   /* Set DAC error code to none */
00252   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00253
00254   /* Initialize the DAC state*/
00255   hdac->State = HAL_DAC_STATE_READY;
00256
00257   /* Return function status */
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  Deinitializes the DAC peripheral registers to their default reset values.
00263   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00264   *         the configuration information for the specified DAC.
00265   * @retval HAL status
00266   */
00267 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
00268 {
00269   /* Check DAC handle */
00270   if(hdac == NULL)
00271   {
00272      return HAL_ERROR;
00273   }
00274
00275   /* Check the parameters */
00276   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00277
00278   /* Change DAC state */
00279   hdac->State = HAL_DAC_STATE_BUSY;
00280
00281   /* DeInit the low level hardware */
00282   HAL_DAC_MspDeInit(hdac);
00283
00284   /* Set DAC error code to none */
00285   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00286
00287   /* Change DAC state */
00288   hdac->State = HAL_DAC_STATE_RESET;
00289
00290   /* Release Lock */
00291   __HAL_UNLOCK(hdac);
00292
00293   /* Return function status */
00294   return HAL_OK;
00295 }
00296
00297 /**
00298   * @brief  Initializes the DAC MSP.
00299   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00300   *         the configuration information for the specified DAC.
00301   * @retval None
00302   */
00303 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
00304 {
00305   /* Prevent unused argument(s) compilation warning */
00306   UNUSED(hdac);
00307
00308   /* NOTE : This function Should not be modified, when the callback is needed,
00309             the HAL_DAC_MspInit could be implemented in the user file
00310    */
00311 }
00312
00313 /**
00314   * @brief  DeInitializes the DAC MSP.
00315   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00316   *         the configuration information for the specified DAC.
00317   * @retval None
00318   */
00319 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
00320 {
00321   /* Prevent unused argument(s) compilation warning */
00322   UNUSED(hdac);
00323
00324   /* NOTE : This function Should not be modified, when the callback is needed,
00325             the HAL_DAC_MspDeInit could be implemented in the user file
00326    */
00327 }
00328
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00334  *  @brief    IO operation functions
00335  *
00336 @verbatim
00337   ==============================================================================
00338              ##### IO operation functions #####
00339   ==============================================================================
00340     [..]  This section provides functions allowing to:
00341       (+) Start conversion.
00342       (+) Stop conversion.
00343       (+) Start conversion and enable DMA transfer.
00344       (+) Stop conversion and disable DMA transfer.
00345       (+) Get result of conversion.
00346
00347 @endverbatim
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Enables DAC and starts conversion of channel.
00353   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00354   *         the configuration information for the specified DAC.
00355   * @param  Channel: The selected DAC channel.
00356   *          This parameter can be one of the following values:
00357   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00358   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00362 {
00363   uint32_t tmp1 = 0, tmp2 = 0;
00364
00365   /* Check the parameters */
00366   assert_param(IS_DAC_CHANNEL(Channel));
00367
00368   /* Process locked */
00369   __HAL_LOCK(hdac);
00370
00371   /* Change DAC state */
00372   hdac->State = HAL_DAC_STATE_BUSY;
00373
00374   /* Enable the Peripheral */
00375   __HAL_DAC_ENABLE(hdac, Channel);
00376
00377   if(Channel == DAC_CHANNEL_1)
00378   {
00379     tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
00380     tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
00381     /* Check if software trigger enabled */
00382     if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
00383     {
00384       /* Enable the selected DAC software conversion */
00385       hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
00386     }
00387   }
00388   else
00389   {
00390     tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
00391     tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
00392     /* Check if software trigger enabled */
00393     if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
00394     {
00395       /* Enable the selected DAC software conversion*/
00396       hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
00397     }
00398   }
00399
00400   /* Change DAC state */
00401   hdac->State = HAL_DAC_STATE_READY;
00402
00403   /* Process unlocked */
00404   __HAL_UNLOCK(hdac);
00405
00406   /* Return function status */
00407   return HAL_OK;
00408 }
00409
00410 /**
00411   * @brief  Disables DAC and stop conversion of channel.
00412   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00413   *         the configuration information for the specified DAC.
00414   * @param  Channel: The selected DAC channel.
00415   *          This parameter can be one of the following values:
00416   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00417   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00418   * @retval HAL status
00419   */
00420 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
00421 {
00422   /* Check the parameters */
00423   assert_param(IS_DAC_CHANNEL(Channel));
00424
00425   /* Disable the Peripheral */
00426   __HAL_DAC_DISABLE(hdac, Channel);
00427
00428   /* Change DAC state */
00429   hdac->State = HAL_DAC_STATE_READY;
00430
00431   /* Return function status */
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief  Enables DAC and starts conversion of channel.
00437   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00438   *         the configuration information for the specified DAC.
00439   * @param  Channel: The selected DAC channel.
00440   *          This parameter can be one of the following values:
00441   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00442   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00443   * @param  pData: The destination peripheral Buffer address.
00444   * @param  Length: The length of data to be transferred from memory to DAC peripheral
00445   * @param  Alignment: Specifies the data alignment for DAC channel.
00446   *          This parameter can be one of the following values:
00447   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00448   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00449   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00450   * @retval HAL status
00451   */
00452 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00453 {
00454   uint32_t tmpreg = 0;
00455
00456   /* Check the parameters */
00457   assert_param(IS_DAC_CHANNEL(Channel));
00458   assert_param(IS_DAC_ALIGN(Alignment));
00459
00460   /* Process locked */
00461   __HAL_LOCK(hdac);
00462
00463   /* Change DAC state */
00464   hdac->State = HAL_DAC_STATE_BUSY;
00465
00466   if(Channel == DAC_CHANNEL_1)
00467   {
00468     /* Set the DMA transfer complete callback for channel1 */
00469     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00470
00471     /* Set the DMA half transfer complete callback for channel1 */
00472     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00473
00474     /* Set the DMA error callback for channel1 */
00475     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00476
00477     /* Enable the selected DAC channel1 DMA request */
00478     hdac->Instance->CR |= DAC_CR_DMAEN1;
00479
00480     /* Case of use of channel 1 */
00481     switch(Alignment)
00482     {
00483       case DAC_ALIGN_12B_R:
00484         /* Get DHR12R1 address */
00485         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00486         break;
00487       case DAC_ALIGN_12B_L:
00488         /* Get DHR12L1 address */
00489         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00490         break;
00491       case DAC_ALIGN_8B_R:
00492         /* Get DHR8R1 address */
00493         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00494         break;
00495       default:
00496         break;
00497     }
00498   }
00499   else
00500   {
00501     /* Set the DMA transfer complete callback for channel2 */
00502     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00503
00504     /* Set the DMA half transfer complete callback for channel2 */
00505     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00506
00507     /* Set the DMA error callback for channel2 */
00508     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00509
00510     /* Enable the selected DAC channel2 DMA request */
00511     hdac->Instance->CR |= DAC_CR_DMAEN2;
00512
00513     /* Case of use of channel 2 */
00514     switch(Alignment)
00515     {
00516       case DAC_ALIGN_12B_R:
00517         /* Get DHR12R2 address */
00518         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00519         break;
00520       case DAC_ALIGN_12B_L:
00521         /* Get DHR12L2 address */
00522         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00523         break;
00524       case DAC_ALIGN_8B_R:
00525         /* Get DHR8R2 address */
00526         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00527         break;
00528       default:
00529         break;
00530     }
00531   }
00532
00533   /* Enable the DMA Stream */
00534   if(Channel == DAC_CHANNEL_1)
00535   {
00536     /* Enable the DAC DMA underrun interrupt */
00537     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00538
00539     /* Enable the DMA Stream */
00540     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00541   }
00542   else
00543   {
00544     /* Enable the DAC DMA underrun interrupt */
00545     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00546
00547     /* Enable the DMA Stream */
00548     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00549   }
00550
00551   /* Enable the Peripheral */
00552   __HAL_DAC_ENABLE(hdac, Channel);
00553
00554   /* Process Unlocked */
00555   __HAL_UNLOCK(hdac);
00556
00557   /* Return function status */
00558   return HAL_OK;
00559 }
00560
00561 /**
00562   * @brief  Disables DAC and stop conversion of channel.
00563   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00564   *         the configuration information for the specified DAC.
00565   * @param  Channel: The selected DAC channel.
00566   *          This parameter can be one of the following values:
00567   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00568   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00569   * @retval HAL status
00570   */
00571 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00572 {
00573   HAL_StatusTypeDef status = HAL_OK;
00574
00575   /* Check the parameters */
00576   assert_param(IS_DAC_CHANNEL(Channel));
00577
00578   /* Disable the selected DAC channel DMA request */
00579    hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
00580
00581   /* Disable the Peripheral */
00582   __HAL_DAC_DISABLE(hdac, Channel);
00583
00584   /* Disable the DMA Channel */
00585   /* Channel1 is used */
00586   if(Channel == DAC_CHANNEL_1)
00587   {
00588     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00589   }
00590   else /* Channel2 is used for */
00591   {
00592     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00593   }
00594
00595   /* Check if DMA Channel effectively disabled */
00596   if(status != HAL_OK)
00597   {
00598     /* Update DAC state machine to error */
00599     hdac->State = HAL_DAC_STATE_ERROR;
00600   }
00601   else
00602   {
00603     /* Change DAC state */
00604     hdac->State = HAL_DAC_STATE_READY;
00605   }
00606
00607   /* Return function status */
00608   return status;
00609 }
00610
00611 /**
00612   * @brief  Returns the last data output value of the selected DAC channel.
00613   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00614   *         the configuration information for the specified DAC.
00615   * @param  Channel: The selected DAC channel.
00616   *          This parameter can be one of the following values:
00617   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00618   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00619   * @retval The selected DAC channel data output value.
00620   */
00621 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00622 {
00623   /* Check the parameters */
00624   assert_param(IS_DAC_CHANNEL(Channel));
00625
00626   /* Returns the DAC channel data output register value */
00627   if(Channel == DAC_CHANNEL_1)
00628   {
00629     return hdac->Instance->DOR1;
00630   }
00631   else
00632   {
00633     return hdac->Instance->DOR2;
00634   }
00635 }
00636
00637 /**
00638   * @brief  Handles DAC interrupt request
00639   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00640   *         the configuration information for the specified DAC.
00641   * @retval None
00642   */
00643 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
00644 {
00645   /* Check underrun channel 1 flag */
00646   if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00647   {
00648     /* Change DAC state to error state */
00649     hdac->State = HAL_DAC_STATE_ERROR;
00650
00651     /* Set DAC error code to channel1 DMA underrun error */
00652     hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
00653
00654     /* Clear the underrun flag */
00655     __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00656
00657     /* Disable the selected DAC channel1 DMA request */
00658     hdac->Instance->CR &= ~DAC_CR_DMAEN1;
00659
00660     /* Error callback */
00661     HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00662   }
00663   /* Check underrun channel 2 flag */
00664   if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00665   {
00666     /* Change DAC state to error state */
00667     hdac->State = HAL_DAC_STATE_ERROR;
00668
00669     /* Set DAC error code to channel2 DMA underrun error */
00670     hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
00671
00672     /* Clear the underrun flag */
00673     __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
00674
00675     /* Disable the selected DAC channel1 DMA request */
00676     hdac->Instance->CR &= ~DAC_CR_DMAEN2;
00677
00678     /* Error callback */
00679     HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00680   }
00681 }
00682
00683 /**
00684   * @brief  Conversion complete callback in non blocking mode for Channel1
00685   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00686   *         the configuration information for the specified DAC.
00687   * @retval None
00688   */
00689 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00690 {
00691   /* Prevent unused argument(s) compilation warning */
00692   UNUSED(hdac);
00693
00694   /* NOTE : This function Should not be modified, when the callback is needed,
00695             the HAL_DAC_ConvCpltCallback could be implemented in the user file
00696    */
00697 }
00698
00699 /**
00700   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1
00701   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00702   *         the configuration information for the specified DAC.
00703   * @retval None
00704   */
00705 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00706 {
00707   /* Prevent unused argument(s) compilation warning */
00708   UNUSED(hdac);
00709
00710   /* NOTE : This function Should not be modified, when the callback is needed,
00711             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00712    */
00713 }
00714
00715 /**
00716   * @brief  Error DAC callback for Channel1.
00717   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00718   *         the configuration information for the specified DAC.
00719   * @retval None
00720   */
00721 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00722 {
00723   /* Prevent unused argument(s) compilation warning */
00724   UNUSED(hdac);
00725
00726   /* NOTE : This function Should not be modified, when the callback is needed,
00727             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00728    */
00729 }
00730
00731 /**
00732   * @brief  DMA underrun DAC callback for channel1.
00733   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00734   *         the configuration information for the specified DAC.
00735   * @retval None
00736   */
00737 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00738 {
00739   /* Prevent unused argument(s) compilation warning */
00740   UNUSED(hdac);
00741
00742   /* NOTE : This function Should not be modified, when the callback is needed,
00743             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00744    */
00745 }
00746
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00752  *  @brief      Peripheral Control functions
00753  *
00754 @verbatim
00755   ==============================================================================
00756              ##### Peripheral Control functions #####
00757   ==============================================================================
00758     [..]  This section provides functions allowing to:
00759       (+) Configure channels.
00760       (+) Set the specified data holding register value for DAC channel.
00761
00762 @endverbatim
00763   * @{
00764   */
00765
00766 /**
00767   * @brief  Configures the selected DAC channel.
00768   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00769   *         the configuration information for the specified DAC.
00770   * @param  sConfig: DAC configuration structure.
00771   * @param  Channel: The selected DAC channel.
00772   *          This parameter can be one of the following values:
00773   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00774   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00775   * @retval HAL status
00776   */
00777 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00778 {
00779   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00780
00781   /* Check the DAC parameters */
00782   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
00783   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00784   assert_param(IS_DAC_CHANNEL(Channel));
00785
00786   /* Process locked */
00787   __HAL_LOCK(hdac);
00788
00789   /* Change DAC state */
00790   hdac->State = HAL_DAC_STATE_BUSY;
00791
00792   /* Get the DAC CR value */
00793   tmpreg1 = hdac->Instance->CR;
00794   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
00795   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
00796   /* Configure for the selected DAC channel: buffer output, trigger */
00797   /* Set TSELx and TENx bits according to DAC_Trigger value */
00798   /* Set BOFFx bit according to DAC_OutputBuffer value */
00799   tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
00800   /* Calculate CR register value depending on DAC_Channel */
00801   tmpreg1 |= tmpreg2 << Channel;
00802   /* Write to DAC CR */
00803   hdac->Instance->CR = tmpreg1;
00804   /* Disable wave generation */
00805   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
00806
00807   /* Change DAC state */
00808   hdac->State = HAL_DAC_STATE_READY;
00809
00810   /* Process unlocked */
00811   __HAL_UNLOCK(hdac);
00812
00813   /* Return function status */
00814   return HAL_OK;
00815 }
00816
00817 /**
00818   * @brief  Set the specified data holding register value for DAC channel.
00819   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00820   *         the configuration information for the specified DAC.
00821   * @param  Channel: The selected DAC channel.
00822   *          This parameter can be one of the following values:
00823   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00824   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00825   * @param  Alignment: Specifies the data alignment.
00826   *          This parameter can be one of the following values:
00827   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00828   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00829   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00830   * @param  Data: Data to be loaded in the selected data holding register.
00831   * @retval HAL status
00832   */
00833 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00834 {
00835   __IO uint32_t tmp = 0;
00836
00837   /* Check the parameters */
00838   assert_param(IS_DAC_CHANNEL(Channel));
00839   assert_param(IS_DAC_ALIGN(Alignment));
00840   assert_param(IS_DAC_DATA(Data));
00841
00842   tmp = (uint32_t)hdac->Instance;
00843   if(Channel == DAC_CHANNEL_1)
00844   {
00845     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00846   }
00847   else
00848   {
00849     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00850   }
00851
00852   /* Set the DAC channel1 selected data holding register */
00853   *(__IO uint32_t *) tmp = Data;
00854
00855   /* Return function status */
00856   return HAL_OK;
00857 }
00858
00859 /**
00860   * @}
00861   */
00862
00863 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
00864  *  @brief   Peripheral State and Errors functions
00865  *
00866 @verbatim
00867   ==============================================================================
00868             ##### Peripheral State and Errors functions #####
00869   ==============================================================================
00870     [..]
00871     This subsection provides functions allowing to
00872       (+) Check the DAC state.
00873       (+) Check the DAC Errors.
00874
00875 @endverbatim
00876   * @{
00877   */
00878
00879 /**
00880   * @brief  return the DAC state
00881   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00882   *         the configuration information for the specified DAC.
00883   * @retval HAL state
00884   */
00885 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
00886 {
00887   /* Return DAC state */
00888   return hdac->State;
00889 }
00890
00891
00892 /**
00893   * @brief  Return the DAC error code
00894   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00895   *         the configuration information for the specified DAC.
00896   * @retval DAC Error Code
00897   */
00898 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
00899 {
00900   return hdac->ErrorCode;
00901 }
00902
00903 /**
00904   * @}
00905   */
00906
00907 /**
00908   * @brief  DMA conversion complete callback.
00909   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00910   *                the configuration information for the specified DMA module.
00911   * @retval None
00912   */
00913 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
00914 {
00915   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00916
00917   HAL_DAC_ConvCpltCallbackCh1(hdac);
00918
00919   hdac->State= HAL_DAC_STATE_READY;
00920 }
00921
00922 /**
00923   * @brief  DMA half transfer complete callback.
00924   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00925   *                the configuration information for the specified DMA module.
00926   * @retval None
00927   */
00928 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
00929 {
00930     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00931     /* Conversion complete callback */
00932     HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
00933 }
00934
00935 /**
00936   * @brief  DMA error callback
00937   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00938   *                the configuration information for the specified DMA module.
00939   * @retval None
00940   */
00941 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
00942 {
00943   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00944
00945   /* Set DAC error code to DMA error */
00946   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00947
00948   HAL_DAC_ErrorCallbackCh1(hdac);
00949
00950   hdac->State= HAL_DAC_STATE_READY;
00951 }
00952
00953 /**
00954   * @}
00955   */
00956
00957 #endif /* HAL_DAC_MODULE_ENABLED */
00958
00959 /**
00960   * @}
00961   */
00962
00963 /**
00964   * @}
00965   */
00966
00967 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac.h Source File

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stm32f7xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DAC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DAC_H
00040 #define __STM32F7xx_HAL_DAC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DAC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup DAC_Exported_Types DAC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
00068   HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
00069   HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
00070   HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
00071   HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
00072 }HAL_DAC_StateTypeDef;
00073
00074 /**
00075   * @brief DAC handle Structure definition
00076   */
00077 typedef struct
00078 {
00079   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00080
00081   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00082
00083   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00084
00085   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00086
00087   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00088
00089   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00090
00091 }DAC_HandleTypeDef;
00092
00093 /**
00094   * @brief DAC Configuration regular Channel structure definition
00095   */
00096 typedef struct
00097 {
00098   uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
00099                                    This parameter can be a value of @ref DAC_trigger_selection */
00100
00101   uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00102                                    This parameter can be a value of @ref DAC_output_buffer */
00103 }DAC_ChannelConfTypeDef;
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported constants --------------------------------------------------------*/
00109 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00110   * @{
00111   */
00112
00113 /** @defgroup DAC_Error_Code DAC Error Code
00114   * @{
00115   */
00116 #define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
00117 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DAM underrun error   */
00118 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DAM underrun error   */
00119 #define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup DAC_trigger_selection DAC Trigger Selection
00125   * @{
00126   */
00127
00128 #define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00129                                                                        has been loaded, and not by external trigger */
00130 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00131 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00132 #define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00133 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00134 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00135 #define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
00136
00137 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00138 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup DAC_output_buffer  DAC Output Buffer
00144   * @{
00145   */
00146 #define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
00147 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup DAC_Channel_selection DAC Channel Selection
00153   * @{
00154   */
00155 #define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
00156 #define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup DAC_data_alignment DAC Data Alignment
00162   * @{
00163   */
00164 #define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
00165 #define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
00166 #define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup DAC_flags_definition DAC Flags Definition
00172   * @{
00173   */
00174 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00175 #define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup DAC_IT_definition DAC IT Definition
00181   * @{
00182   */
00183 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00184 #define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /* Exported macro ------------------------------------------------------------*/
00194 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00195   * @{
00196   */
00197
00198 /** @brief Reset DAC handle state
00199   * @param  __HANDLE__: specifies the DAC handle.
00200   * @retval None
00201   */
00202 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00203
00204 /** @brief Enable the DAC channel
00205   * @param  __HANDLE__: specifies the DAC handle.
00206   * @param  __DAC_CHANNEL__: specifies the DAC channel
00207   * @retval None
00208   */
00209 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
00210 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_CHANNEL__)))
00211
00212 /** @brief Disable the DAC channel
00213   * @param  __HANDLE__: specifies the DAC handle
00214   * @param  __DAC_CHANNEL__: specifies the DAC channel.
00215   * @retval None
00216   */
00217 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
00218 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))
00219
00220
00221 /** @brief Enable the DAC interrupt
00222   * @param  __HANDLE__: specifies the DAC handle
00223   * @param  __INTERRUPT__: specifies the DAC interrupt.
00224   * @retval None
00225   */
00226 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00227
00228 /** @brief Disable the DAC interrupt
00229   * @param  __HANDLE__: specifies the DAC handle
00230   * @param  __INTERRUPT__: specifies the DAC interrupt.
00231   * @retval None
00232   */
00233 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00234
00235 /** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
00236   * @param __HANDLE__: DAC handle
00237   * @param __INTERRUPT__: DAC interrupt source to check
00238   *          This parameter can be any combination of the following values:
00239   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00240   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00241   * @retval State of interruption (SET or RESET)
00242   */
00243 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00244
00245 /** @brief  Get the selected DAC's flag status.
00246   * @param  __HANDLE__: specifies the DAC handle.
00247   * @param  __FLAG__: specifies the flag to clear.
00248   *         This parameter can be any combination of the following values:
00249   *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
00250   *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
00251   * @retval None
00252   */
00253 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00254
00255 /** @brief  Clear the DAC's flag.
00256   * @param  __HANDLE__: specifies the DAC handle.
00257   * @param  __FLAG__: specifies the flag to clear.
00258   *         This parameter can be any combination of the following values:
00259   *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
00260   *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
00261   * @retval None
00262   */
00263 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00264 /**
00265   * @}
00266   */
00267
00268 /* Include DAC HAL Extension module */
00269 #include "stm32f7xx_hal_dac_ex.h"
00270
00271 /* Exported functions --------------------------------------------------------*/
00272 /** @addtogroup DAC_Exported_Functions
00273   * @{
00274   */
00275
00276 /** @addtogroup DAC_Exported_Functions_Group1
00277   * @{
00278   */
00279 /* Initialization/de-initialization functions *********************************/
00280 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
00281 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
00282 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
00283 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
00284 /**
00285   * @}
00286   */
00287
00288 /** @addtogroup DAC_Exported_Functions_Group2
00289   * @{
00290   */
00291 /* I/O operation functions ****************************************************/
00292 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
00293 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
00294 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
00295 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
00296 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
00297 /**
00298   * @}
00299   */
00300
00301 /** @addtogroup DAC_Exported_Functions_Group3
00302   * @{
00303   */
00304 /* Peripheral Control functions ***********************************************/
00305 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00306 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00307 /**
00308   * @}
00309   */
00310
00311 /** @addtogroup DAC_Exported_Functions_Group4
00312   * @{
00313   */
00314 /* Peripheral State functions *************************************************/
00315 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
00316 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
00317 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00318
00319 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00320 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00321 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00322 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330 /* Private types -------------------------------------------------------------*/
00331 /* Private variables ---------------------------------------------------------*/
00332 /* Private constants ---------------------------------------------------------*/
00333 /** @defgroup DAC_Private_Constants DAC Private Constants
00334   * @{
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Private macros ------------------------------------------------------------*/
00342 /** @defgroup DAC_Private_Macros DAC Private Macros
00343   * @{
00344   */
00345 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
00346 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00347                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00348                              ((ALIGN) == DAC_ALIGN_8B_R))
00349 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00350                                  ((CHANNEL) == DAC_CHANNEL_2))
00351 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00352                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00353
00354 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00355                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00356                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
00357                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00358                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00359                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00360                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00361                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00362                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00363
00364 /** @brief Set DHR12R1 alignment
00365   * @param  __ALIGNMENT__: specifies the DAC alignment
00366   * @retval None
00367   */
00368 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
00369
00370 /** @brief  Set DHR12R2 alignment
00371   * @param  __ALIGNMENT__: specifies the DAC alignment
00372   * @retval None
00373   */
00374 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
00375
00376 /** @brief  Set DHR12RD alignment
00377   * @param  __ALIGNMENT__: specifies the DAC alignment
00378   * @retval None
00379   */
00380 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
00381
00382 /**
00383   * @}
00384   */
00385
00386 /* Private functions ---------------------------------------------------------*/
00387 /** @defgroup DAC_Private_Functions DAC Private Functions
00388   * @{
00389   */
00390 /**
00391   * @}
00392   */
00393
00394 /**
00395   * @}
00396   */
00397
00398 /**
00399   * @}
00400   */
00401
00402 #ifdef __cplusplus
00403 }
00404 #endif
00405
00406 #endif /*__STM32F7xx_HAL_DAC_H */
00407
00408 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac_ex.c Source File

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stm32f7xx_hal_dac_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Extended DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of DAC extension peripheral:
00010   *           + Extended features functions
00011   *
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
00019           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00020           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
00021       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00022       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00023
00024  @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f7xx_hal.h"
00058
00059 /** @addtogroup STM32F7xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup DACEx DACEx
00064   * @brief DAC driver modules
00065   * @{
00066   */
00067
00068 #ifdef HAL_DAC_MODULE_ENABLED
00069
00070 /* Private typedef -----------------------------------------------------------*/
00071 /* Private define ------------------------------------------------------------*/
00072 /* Private macro -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private function prototypes -----------------------------------------------*/
00075 /* Private functions ---------------------------------------------------------*/
00076 /* Exported functions --------------------------------------------------------*/
00077 /** @defgroup DACEx_Exported_Functions DAC Exported Functions
00078   * @{
00079   */
00080
00081 /** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
00082  *  @brief    Extended features functions
00083  *
00084 @verbatim
00085   ==============================================================================
00086                  ##### Extended features functions #####
00087   ==============================================================================
00088     [..]  This section provides functions allowing to:
00089       (+) Start conversion.
00090       (+) Stop conversion.
00091       (+) Start conversion and enable DMA transfer.
00092       (+) Stop conversion and disable DMA transfer.
00093       (+) Get result of conversion.
00094       (+) Get result of dual mode conversion.
00095
00096 @endverbatim
00097   * @{
00098   */
00099
00100 /**
00101   * @brief  Returns the last data output value of the selected DAC channel.
00102   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00103   *         the configuration information for the specified DAC.
00104   * @retval The selected DAC channel data output value.
00105   */
00106 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00107 {
00108   uint32_t tmp = 0;
00109
00110   tmp |= hdac->Instance->DOR1;
00111
00112   tmp |= hdac->Instance->DOR2 << 16;
00113
00114   /* Returns the DAC channel data output register value */
00115   return tmp;
00116 }
00117
00118 /**
00119   * @brief  Enables or disables the selected DAC channel wave generation.
00120   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00121   *         the configuration information for the specified DAC.
00122   * @param  Channel: The selected DAC channel.
00123   *          This parameter can be one of the following values:
00124   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00125   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00126   * @param  Amplitude: Select max triangle amplitude.
00127   *          This parameter can be one of the following values:
00128   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00129   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00130   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00131   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00132   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00133   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00134   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00135   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00136   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00137   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00138   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00139   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00143 {
00144   /* Check the parameters */
00145   assert_param(IS_DAC_CHANNEL(Channel));
00146   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00147
00148   /* Process locked */
00149   __HAL_LOCK(hdac);
00150
00151   /* Change DAC state */
00152   hdac->State = HAL_DAC_STATE_BUSY;
00153
00154   /* Enable the selected wave generation for the selected DAC channel */
00155   MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
00156
00157   /* Change DAC state */
00158   hdac->State = HAL_DAC_STATE_READY;
00159
00160   /* Process unlocked */
00161   __HAL_UNLOCK(hdac);
00162
00163   /* Return function status */
00164   return HAL_OK;
00165 }
00166
00167 /**
00168   * @brief  Enables or disables the selected DAC channel wave generation.
00169   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00170   *         the configuration information for the specified DAC.
00171   * @param  Channel: The selected DAC channel.
00172   *          This parameter can be one of the following values:
00173   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00174   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00175   * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
00176   *          This parameter can be one of the following values:
00177   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00178   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00179   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00180   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00181   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00182   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00183   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00184   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00185   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00186   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00187   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00188   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00189   * @retval HAL status
00190   */
00191 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00192 {
00193   /* Check the parameters */
00194   assert_param(IS_DAC_CHANNEL(Channel));
00195   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00196
00197   /* Process locked */
00198   __HAL_LOCK(hdac);
00199
00200   /* Change DAC state */
00201   hdac->State = HAL_DAC_STATE_BUSY;
00202
00203   /* Enable the selected wave generation for the selected DAC channel */
00204   MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
00205
00206   /* Change DAC state */
00207   hdac->State = HAL_DAC_STATE_READY;
00208
00209   /* Process unlocked */
00210   __HAL_UNLOCK(hdac);
00211
00212   /* Return function status */
00213   return HAL_OK;
00214 }
00215
00216 /**
00217   * @brief  Set the specified data holding register value for dual DAC channel.
00218   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00219   *               the configuration information for the specified DAC.
00220   * @param  Alignment: Specifies the data alignment for dual channel DAC.
00221   *          This parameter can be one of the following values:
00222   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00223   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00224   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00225   * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
00226   * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
00227   * @note   In dual mode, a unique register access is required to write in both
00228   *          DAC channels at the same time.
00229   * @retval HAL status
00230   */
00231 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00232 {
00233   uint32_t data = 0, tmp = 0;
00234
00235   /* Check the parameters */
00236   assert_param(IS_DAC_ALIGN(Alignment));
00237   assert_param(IS_DAC_DATA(Data1));
00238   assert_param(IS_DAC_DATA(Data2));
00239
00240   /* Calculate and set dual DAC data holding register value */
00241   if (Alignment == DAC_ALIGN_8B_R)
00242   {
00243     data = ((uint32_t)Data2 << 8) | Data1;
00244   }
00245   else
00246   {
00247     data = ((uint32_t)Data2 << 16) | Data1;
00248   }
00249
00250   tmp = (uint32_t)hdac->Instance;
00251   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00252
00253   /* Set the dual DAC selected data holding register */
00254   *(__IO uint32_t *)tmp = data;
00255
00256   /* Return function status */
00257   return HAL_OK;
00258 }
00259
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @brief  Conversion complete callback in non blocking mode for Channel2
00266   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00267   *         the configuration information for the specified DAC.
00268   * @retval None
00269   */
00270 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00271 {
00272   /* Prevent unused argument(s) compilation warning */
00273   UNUSED(hdac);
00274
00275   /* NOTE : This function Should not be modified, when the callback is needed,
00276             the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
00277    */
00278 }
00279
00280 /**
00281   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2
00282   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00283   *         the configuration information for the specified DAC.
00284   * @retval None
00285   */
00286 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00287 {
00288   /* Prevent unused argument(s) compilation warning */
00289   UNUSED(hdac);
00290
00291   /* NOTE : This function Should not be modified, when the callback is needed,
00292             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00293    */
00294 }
00295
00296 /**
00297   * @brief  Error DAC callback for Channel2.
00298   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00299   *         the configuration information for the specified DAC.
00300   * @retval None
00301   */
00302 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(hdac);
00306
00307   /* NOTE : This function Should not be modified, when the callback is needed,
00308             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00309    */
00310 }
00311
00312 /**
00313   * @brief  DMA underrun DAC callback for channel2.
00314   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00315   *         the configuration information for the specified DAC.
00316   * @retval None
00317   */
00318 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00319 {
00320   /* Prevent unused argument(s) compilation warning */
00321   UNUSED(hdac);
00322
00323   /* NOTE : This function Should not be modified, when the callback is needed,
00324             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00325    */
00326 }
00327
00328 /**
00329   * @brief  DMA conversion complete callback.
00330   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00331   *                the configuration information for the specified DMA module.
00332   * @retval None
00333   */
00334 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00335 {
00336   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00337
00338   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00339
00340   hdac->State= HAL_DAC_STATE_READY;
00341 }
00342
00343 /**
00344   * @brief  DMA half transfer complete callback.
00345   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00346   *                the configuration information for the specified DMA module.
00347   * @retval None
00348   */
00349 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00350 {
00351     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00352     /* Conversion complete callback */
00353     HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00354 }
00355
00356 /**
00357   * @brief  DMA error callback
00358   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00359   *                the configuration information for the specified DMA module.
00360   * @retval None
00361   */
00362 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00363 {
00364   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00365
00366   /* Set DAC error code to DMA error */
00367   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00368
00369   HAL_DACEx_ErrorCallbackCh2(hdac);
00370
00371   hdac->State= HAL_DAC_STATE_READY;
00372 }
00373
00374 /**
00375   * @}
00376   */
00377
00378 #endif /* HAL_DAC_MODULE_ENABLED */
00379
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dac_ex.h Source File

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stm32f7xx_hal_dac_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DAC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DAC_EX_H
00040 #define __STM32F7xx_HAL_DAC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DACEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup DACEx_Exported_Constants DAC Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
00064   * @{
00065   */
00066 #define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00067 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00068 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00069 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00070 #define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00071 #define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00072 #define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00073 #define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00074 #define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00075 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00076 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00077 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00078 #define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
00079 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00080 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
00081 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00082 #define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
00083 #define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00084 #define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
00085 #define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00086 #define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
00087 #define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00088 #define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
00089 #define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00090 /**
00091   * @}
00092   */
00093
00094 /**
00095   * @}
00096   */
00097 /* Exported macro ------------------------------------------------------------*/
00098 /* Exported functions --------------------------------------------------------*/
00099 /** @addtogroup DACEx_Exported_Functions
00100   * @{
00101   */
00102
00103 /** @addtogroup DACEx_Exported_Functions_Group1
00104   * @{
00105   */
00106 /* Extension features functions ***********************************************/
00107 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
00108 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00109 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00110 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00111
00112 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00113 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00114 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
00115 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123 /* Private types -------------------------------------------------------------*/
00124 /* Private variables ---------------------------------------------------------*/
00125 /* Private constants ---------------------------------------------------------*/
00126 /** @defgroup DACEx_Private_Constants DAC Private Constants
00127   * @{
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /* Private macros ------------------------------------------------------------*/
00135 /** @defgroup DACEx_Private_Macros DAC Private Macros
00136   * @{
00137   */
00138 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00139                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00140                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00141                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00142                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00143                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00144                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00145                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00146                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00147                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00148                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00149                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00150                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00151                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00152                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00153                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00154                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00155                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00156                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00157                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00158                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00159                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00160                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00161                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00162 /**
00163   * @}
00164   */
00165
00166 /* Private functions ---------------------------------------------------------*/
00167 /** @defgroup DACEx_Private_Functions DAC Private Functions
00168   * @{
00169   */
00170 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00171 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00172 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 #ifdef __cplusplus
00186 }
00187 #endif
00188
00189 #endif /*__STM32F7xx_HAL_DAC_EX_H */
00190
00191 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi.c Source File

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stm32f7xx_hal_dcmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dcmi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   DCMI HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020       The sequence below describes how to use this driver to capture image
00021       from a camera module connected to the DCMI Interface.
00022       This sequence does not take into account the configuration of the
00023       camera module, which should be made before to configure and enable
00024       the DCMI to capture images.
00025
00026     (#) Program the required configuration through following parameters:
00027         horizontal and vertical polarity, pixel clock polarity, Capture Rate,
00028         Synchronization Mode, code of the frame delimiter and data width
00029         using HAL_DCMI_Init() function.
00030
00031     (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
00032         register to the destination memory buffer.
00033
00034     (#) Program the required configuration through following parameters:
00035         DCMI mode, destination memory Buffer address and the data length
00036         and enable capture using HAL_DCMI_Start_DMA() function.
00037
00038     (#) Optionally, configure and Enable the CROP feature to select a rectangular
00039         window from the received image using HAL_DCMI_ConfigCrop()
00040         and HAL_DCMI_EnableCROP() functions
00041
00042     (#) The capture can be stopped using HAL_DCMI_Stop() function.
00043
00044     (#) To control DCMI state you can use the function HAL_DCMI_GetState().
00045
00046      *** DCMI HAL driver macros list ***
00047      =============================================
00048      [..]
00049        Below the list of most used macros in DCMI HAL driver.
00050
00051       (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
00052       (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
00053       (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
00054       (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
00055       (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
00056       (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
00057       (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
00058
00059      [..]
00060        (@) You can refer to the DCMI HAL driver header file for more useful macros
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32f7xx_hal.h"
00095
00096 /** @addtogroup STM32F7xx_HAL_Driver
00097   * @{
00098   */
00099 /** @defgroup DCMI DCMI
00100   * @brief DCMI HAL module driver
00101   * @{
00102   */
00103
00104 #ifdef HAL_DCMI_MODULE_ENABLED
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 #define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000)  /* 1s  */
00109 /* Private macro -------------------------------------------------------------*/
00110 /* Private variables ---------------------------------------------------------*/
00111 /* Private function prototypes -----------------------------------------------*/
00112 static void       DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
00113 static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
00114
00115 /* Exported functions --------------------------------------------------------*/
00116
00117 /** @defgroup DCMI_Exported_Functions DCMI Exported Functions
00118   * @{
00119   */
00120
00121 /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00122  *  @brief   Initialization and Configuration functions
00123  *
00124 @verbatim
00125  ===============================================================================
00126                 ##### Initialization and Configuration functions #####
00127  ===============================================================================
00128     [..]  This section provides functions allowing to:
00129       (+) Initialize and configure the DCMI
00130       (+) De-initialize the DCMI
00131
00132 @endverbatim
00133   * @{
00134   */
00135
00136 /**
00137   * @brief  Initializes the DCMI according to the specified
00138   *         parameters in the DCMI_InitTypeDef and create the associated handle.
00139   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00140   *                the configuration information for DCMI.
00141   * @retval HAL status
00142   */
00143 __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
00144 {
00145   /* Check the DCMI peripheral state */
00146   if(hdcmi == NULL)
00147   {
00148      return HAL_ERROR;
00149   }
00150
00151   /* Check function parameters */
00152   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
00153   assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
00154   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
00155   assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
00156   assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
00157   assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
00158   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
00159   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
00160
00161   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00162   {
00163     /* Allocate lock resource and initialize it */
00164     hdcmi->Lock = HAL_UNLOCKED;
00165     /* Init the low level hardware */
00166     HAL_DCMI_MspInit(hdcmi);
00167   }
00168
00169   /* Change the DCMI state */
00170   hdcmi->State = HAL_DCMI_STATE_BUSY;
00171
00172   /* Set DCMI parameters */
00173   /* Configures the HS, VS, DE and PC polarity */
00174   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |
00175                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |
00176                            DCMI_CR_ESS);
00177   hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
00178                                      hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  | \
00179                                      hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
00180                                      hdcmi->Init.JPEGMode);
00181
00182   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
00183   {
00184     DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
00185                   ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
00186                   ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
00187                   ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
00188   }
00189
00190   /* Enable the Line interrupt */
00191   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
00192
00193   /* Enable the VSYNC interrupt */
00194   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
00195
00196   /* Enable the Frame capture complete interrupt */
00197   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
00198
00199   /* Enable the Synchronization error interrupt */
00200   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
00201
00202   /* Enable the Overflow interrupt */
00203   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
00204
00205   /* Enable DCMI by setting DCMIEN bit */
00206   __HAL_DCMI_ENABLE(hdcmi);
00207
00208   /* Update error code */
00209   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00210
00211   /* Initialize the DCMI state*/
00212   hdcmi->State  = HAL_DCMI_STATE_READY;
00213
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Deinitializes the DCMI peripheral registers to their default reset
00219   *         values.
00220   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00221   *                the configuration information for DCMI.
00222   * @retval HAL status
00223   */
00224
00225 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
00226 {
00227   /* DeInit the low level hardware */
00228   HAL_DCMI_MspDeInit(hdcmi);
00229
00230   /* Update error code */
00231   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00232
00233   /* Initialize the DCMI state*/
00234   hdcmi->State = HAL_DCMI_STATE_RESET;
00235
00236   /* Release Lock */
00237   __HAL_UNLOCK(hdcmi);
00238
00239   return HAL_OK;
00240 }
00241
00242 /**
00243   * @brief  Initializes the DCMI MSP.
00244   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00245   *                the configuration information for DCMI.
00246   * @retval None
00247   */
00248 __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
00249 {
00250   /* Prevent unused argument(s) compilation warning */
00251   UNUSED(hdcmi);
00252
00253   /* NOTE : This function Should not be modified, when the callback is needed,
00254             the HAL_DCMI_MspInit could be implemented in the user file
00255    */
00256 }
00257
00258 /**
00259   * @brief  DeInitializes the DCMI MSP.
00260   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00261   *                the configuration information for DCMI.
00262   * @retval None
00263   */
00264 __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hdcmi);
00268
00269   /* NOTE : This function Should not be modified, when the callback is needed,
00270             the HAL_DCMI_MspDeInit could be implemented in the user file
00271    */
00272 }
00273
00274 /**
00275   * @}
00276   */
00277 /** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
00278  *  @brief   IO operation functions
00279  *
00280 @verbatim
00281  ===============================================================================
00282                       #####  IO operation functions  #####
00283  ===============================================================================
00284     [..]  This section provides functions allowing to:
00285       (+) Configure destination address and data length and
00286           Enables DCMI DMA request and enables DCMI capture
00287       (+) Stop the DCMI capture.
00288       (+) Handles DCMI interrupt request.
00289
00290 @endverbatim
00291   * @{
00292   */
00293
00294 /**
00295   * @brief  Enables DCMI DMA request and enables DCMI capture
00296   * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains
00297   *                    the configuration information for DCMI.
00298   * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
00299   * @param  pData:     The destination memory Buffer address (LCD Frame buffer).
00300   * @param  Length:    The length of capture to be transferred.
00301   * @retval HAL status
00302   */
00303 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
00304 {
00305   /* Initialize the second memory address */
00306   uint32_t SecondMemAddress = 0;
00307
00308   /* Check function parameters */
00309   assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
00310
00311   /* Process Locked */
00312   __HAL_LOCK(hdcmi);
00313
00314   /* Lock the DCMI peripheral state */
00315   hdcmi->State = HAL_DCMI_STATE_BUSY;
00316
00317   /* Check the parameters */
00318   assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
00319
00320   /* Configure the DCMI Mode */
00321   hdcmi->Instance->CR &= ~(DCMI_CR_CM);
00322   hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);
00323
00324   /* Set the DMA memory0 conversion complete callback */
00325   hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;
00326
00327   /* Set the DMA error callback */
00328   hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
00329
00330   if(Length <= 0xFFFF)
00331   {
00332     /* Enable the DMA Stream */
00333     HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
00334   }
00335   else /* DCMI_DOUBLE_BUFFER Mode */
00336   {
00337     /* Set the DMA memory1 conversion complete callback */
00338     hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;
00339
00340     /* Initialize transfer parameters */
00341     hdcmi->XferCount = 1;
00342     hdcmi->XferSize = Length;
00343     hdcmi->pBuffPtr = pData;
00344
00345     /* Get the number of buffer */
00346     while(hdcmi->XferSize > 0xFFFF)
00347     {
00348       hdcmi->XferSize = (hdcmi->XferSize/2);
00349       hdcmi->XferCount = hdcmi->XferCount*2;
00350     }
00351
00352     /* Update DCMI counter  and transfer number*/
00353     hdcmi->XferCount = (hdcmi->XferCount - 2);
00354     hdcmi->XferTransferNumber = hdcmi->XferCount;
00355
00356     /* Update second memory address */
00357     SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
00358
00359     /* Start DMA multi buffer transfer */
00360     HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
00361   }
00362
00363   /* Enable Capture */
00364   DCMI->CR |= DCMI_CR_CAPTURE;
00365
00366   /* Return function status */
00367   return HAL_OK;
00368 }
00369
00370 /**
00371   * @brief  Disable DCMI DMA request and Disable DCMI capture
00372   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00373   *                the configuration information for DCMI.
00374   * @retval HAL status
00375   */
00376 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
00377 {
00378   uint32_t tickstart = 0;
00379
00380   /* Lock the DCMI peripheral state */
00381   hdcmi->State = HAL_DCMI_STATE_BUSY;
00382
00383   __HAL_DCMI_DISABLE(hdcmi);
00384
00385   /* Disable Capture */
00386   DCMI->CR &= ~(DCMI_CR_CAPTURE);
00387
00388   /* Get tick */
00389   tickstart = HAL_GetTick();
00390
00391   /* Check if the DCMI capture effectively disabled */
00392   while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
00393   {
00394     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
00395     {
00396       /* Process Unlocked */
00397       __HAL_UNLOCK(hdcmi);
00398
00399       /* Update error code */
00400       hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
00401
00402       /* Change DCMI state */
00403       hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
00404
00405       return HAL_TIMEOUT;
00406     }
00407   }
00408
00409   /* Disable the DMA */
00410   HAL_DMA_Abort(hdcmi->DMA_Handle);
00411
00412   /* Update error code */
00413   hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
00414
00415   /* Change DCMI state */
00416   hdcmi->State = HAL_DCMI_STATE_READY;
00417
00418   /* Process Unlocked */
00419   __HAL_UNLOCK(hdcmi);
00420
00421   /* Return function status */
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @brief  Handles DCMI interrupt request.
00427   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00428   *                the configuration information for the DCMI.
00429   * @retval None
00430   */
00431 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
00432 {
00433   /* Synchronization error interrupt management *******************************/
00434   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
00435   {
00436     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
00437     {
00438       /* Disable the Synchronization error interrupt */
00439       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR);
00440
00441       /* Clear the Synchronization error flag */
00442       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
00443
00444       /* Update error code */
00445       hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
00446
00447       /* Change DCMI state */
00448       hdcmi->State = HAL_DCMI_STATE_ERROR;
00449
00450       /* Process Unlocked */
00451       __HAL_UNLOCK(hdcmi);
00452
00453       /* Abort the DMA Transfer */
00454       HAL_DMA_Abort(hdcmi->DMA_Handle);
00455
00456       /* Synchronization error Callback */
00457       HAL_DCMI_ErrorCallback(hdcmi);
00458     }
00459   }
00460   /* Overflow interrupt management ********************************************/
00461   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET)
00462   {
00463     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
00464     {
00465       /* Disable the Overflow interrupt */
00466       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF);
00467
00468       /* Clear the Overflow flag */
00469       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
00470
00471       /* Update error code */
00472       hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
00473
00474       /* Change DCMI state */
00475       hdcmi->State = HAL_DCMI_STATE_ERROR;
00476
00477       /* Process Unlocked */
00478       __HAL_UNLOCK(hdcmi);
00479
00480       /* Abort the DMA Transfer */
00481       HAL_DMA_Abort(hdcmi->DMA_Handle);
00482
00483       /* Overflow Callback */
00484       HAL_DCMI_ErrorCallback(hdcmi);
00485     }
00486   }
00487   /* Line Interrupt management ************************************************/
00488   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
00489   {
00490     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
00491     {
00492       /* Clear the Line interrupt flag */
00493       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
00494
00495       /* Process Unlocked */
00496       __HAL_UNLOCK(hdcmi);
00497
00498       /* Line interrupt Callback */
00499       HAL_DCMI_LineEventCallback(hdcmi);
00500     }
00501   }
00502   /* VSYNC interrupt management ***********************************************/
00503   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
00504   {
00505     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
00506     {
00507       /* Disable the VSYNC interrupt */
00508       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC);
00509
00510       /* Clear the VSYNC flag */
00511       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
00512
00513       /* Process Unlocked */
00514       __HAL_UNLOCK(hdcmi);
00515
00516       /* VSYNC Callback */
00517       HAL_DCMI_VsyncEventCallback(hdcmi);
00518     }
00519   }
00520   /* End of Frame interrupt management ****************************************/
00521   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
00522   {
00523     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
00524     {
00525       /* Disable the End of Frame interrupt */
00526       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
00527
00528       /* Clear the End of Frame flag */
00529       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
00530
00531       /* Process Unlocked */
00532       __HAL_UNLOCK(hdcmi);
00533
00534       /* End of Frame Callback */
00535       HAL_DCMI_FrameEventCallback(hdcmi);
00536     }
00537   }
00538 }
00539
00540 /**
00541   * @brief  Error DCMI callback.
00542   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00543   *                the configuration information for DCMI.
00544   * @retval None
00545   */
00546 __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
00547 {
00548   /* Prevent unused argument(s) compilation warning */
00549   UNUSED(hdcmi);
00550
00551   /* NOTE : This function Should not be modified, when the callback is needed,
00552             the HAL_DCMI_ErrorCallback could be implemented in the user file
00553    */
00554 }
00555
00556 /**
00557   * @brief  Line Event callback.
00558   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00559   *                the configuration information for DCMI.
00560   * @retval None
00561   */
00562 __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
00563 {
00564   /* NOTE : This function Should not be modified, when the callback is needed,
00565             the HAL_DCMI_LineEventCallback could be implemented in the user file
00566    */
00567 }
00568
00569 /**
00570   * @brief  VSYNC Event callback.
00571   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00572   *                the configuration information for DCMI.
00573   * @retval None
00574   */
00575 __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
00576 {
00577   /* Prevent unused argument(s) compilation warning */
00578   UNUSED(hdcmi);
00579
00580   /* NOTE : This function Should not be modified, when the callback is needed,
00581             the HAL_DCMI_VsyncEventCallback could be implemented in the user file
00582    */
00583 }
00584
00585 /**
00586   * @brief  Frame Event callback.
00587   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00588   *                the configuration information for DCMI.
00589   * @retval None
00590   */
00591 __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
00592 {
00593   /* Prevent unused argument(s) compilation warning */
00594   UNUSED(hdcmi);
00595
00596   /* NOTE : This function Should not be modified, when the callback is needed,
00597             the HAL_DCMI_FrameEventCallback could be implemented in the user file
00598    */
00599 }
00600
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00606  *  @brief    Peripheral Control functions
00607  *
00608 @verbatim
00609  ===============================================================================
00610                     ##### Peripheral Control functions #####
00611  ===============================================================================
00612 [..]  This section provides functions allowing to:
00613       (+) Configure the CROP feature.
00614       (+) Enable/Disable the CROP feature.
00615                         (+) Enable/Disable the JPEG feature.
00616
00617 @endverbatim
00618   * @{
00619   */
00620
00621 /**
00622   * @brief  Configure the DCMI CROP coordinate.
00623   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00624   *                the configuration information for DCMI.
00625   * @param  YSize: DCMI Line number
00626   * @param  XSize: DCMI Pixel per line
00627   * @param  X0:    DCMI window X offset
00628   * @param  Y0:    DCMI window Y offset
00629   * @retval HAL status
00630   */
00631 HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
00632 {
00633   /* Process Locked */
00634   __HAL_LOCK(hdcmi);
00635
00636   /* Lock the DCMI peripheral state */
00637   hdcmi->State = HAL_DCMI_STATE_BUSY;
00638
00639   /* Check the parameters */
00640   assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
00641   assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
00642   assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
00643   assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
00644
00645   /* Configure CROP */
00646   DCMI->CWSIZER = (XSize | (YSize << 16));
00647   DCMI->CWSTRTR = (X0 | (Y0 << 16));
00648
00649   /* Initialize the DCMI state*/
00650   hdcmi->State  = HAL_DCMI_STATE_READY;
00651
00652   /* Process Unlocked */
00653   __HAL_UNLOCK(hdcmi);
00654
00655   return HAL_OK;
00656 }
00657
00658 /**
00659   * @brief  Disable the Crop feature.
00660   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00661   *                the configuration information for DCMI.
00662   * @retval HAL status
00663   */
00664 HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
00665 {
00666   /* Process Locked */
00667   __HAL_LOCK(hdcmi);
00668
00669   /* Lock the DCMI peripheral state */
00670   hdcmi->State = HAL_DCMI_STATE_BUSY;
00671
00672   /* Disable DCMI Crop feature */
00673   DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
00674
00675   /* Change the DCMI state*/
00676   hdcmi->State = HAL_DCMI_STATE_READY;
00677
00678   /* Process Unlocked */
00679   __HAL_UNLOCK(hdcmi);
00680
00681   return HAL_OK;
00682 }
00683
00684 /**
00685   * @brief  Enable the Crop feature.
00686   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00687   *                the configuration information for DCMI.
00688   * @retval HAL status
00689   */
00690 HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
00691 {
00692   /* Process Locked */
00693   __HAL_LOCK(hdcmi);
00694
00695   /* Lock the DCMI peripheral state */
00696   hdcmi->State = HAL_DCMI_STATE_BUSY;
00697
00698   /* Enable DCMI Crop feature */
00699   DCMI->CR |= (uint32_t)DCMI_CR_CROP;
00700
00701   /* Change the DCMI state*/
00702   hdcmi->State = HAL_DCMI_STATE_READY;
00703
00704   /* Process Unlocked */
00705   __HAL_UNLOCK(hdcmi);
00706
00707   return HAL_OK;
00708 }
00709
00710 /**
00711   * @}
00712   */
00713
00714 /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
00715  *  @brief    Peripheral State functions
00716  *
00717 @verbatim
00718  ===============================================================================
00719                ##### Peripheral State and Errors functions #####
00720  ===============================================================================
00721     [..]
00722     This subsection provides functions allowing to
00723       (+) Check the DCMI state.
00724       (+) Get the specific DCMI error flag.
00725
00726 @endverbatim
00727   * @{
00728   */
00729
00730 /**
00731   * @brief  Return the DCMI state
00732   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00733   *                the configuration information for DCMI.
00734   * @retval HAL state
00735   */
00736 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
00737 {
00738   return hdcmi->State;
00739 }
00740
00741 /**
00742 * @brief  Return the DCMI error code
00743 * @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
00744   *               the configuration information for DCMI.
00745 * @retval DCMI Error Code
00746 */
00747 uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
00748 {
00749   return hdcmi->ErrorCode;
00750 }
00751
00752 /**
00753   * @}
00754   */
00755 /* Private functions ---------------------------------------------------------*/
00756 /** @defgroup DCMI_Private_Functions DCMI Private Functions
00757   * @{
00758   */
00759   /**
00760   * @brief  DMA conversion complete callback.
00761   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00762   *                the configuration information for the specified DMA module.
00763   * @retval None
00764   */
00765 static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
00766 {
00767   uint32_t tmp = 0;
00768
00769   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00770   hdcmi->State= HAL_DCMI_STATE_READY;
00771
00772   if(hdcmi->XferCount != 0)
00773   {
00774     /* Update memory 0 address location */
00775     tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
00776     if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
00777     {
00778       tmp = hdcmi->DMA_Handle->Instance->M0AR;
00779       HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
00780       hdcmi->XferCount--;
00781     }
00782     /* Update memory 1 address location */
00783     else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
00784     {
00785       tmp = hdcmi->DMA_Handle->Instance->M1AR;
00786       HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
00787       hdcmi->XferCount--;
00788     }
00789   }
00790   /* Update memory 0 address location */
00791   else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
00792   {
00793     hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
00794   }
00795   /* Update memory 1 address location */
00796   else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
00797   {
00798     tmp = hdcmi->pBuffPtr;
00799     hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
00800     hdcmi->XferCount = hdcmi->XferTransferNumber;
00801   }
00802
00803   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
00804   {
00805     /* Process Unlocked */
00806     __HAL_UNLOCK(hdcmi);
00807
00808     /* FRAME Callback */
00809     HAL_DCMI_FrameEventCallback(hdcmi);
00810   }
00811 }
00812
00813 /**
00814   * @brief  DMA error callback
00815   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00816   *                the configuration information for the specified DMA module.
00817   * @retval None
00818   */
00819 static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
00820 {
00821     DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00822     hdcmi->State= HAL_DCMI_STATE_READY;
00823     HAL_DCMI_ErrorCallback(hdcmi);
00824 }
00825
00826 /**
00827   * @}
00828   */
00829
00830 /**
00831   * @}
00832   */
00833 #endif /* HAL_DCMI_MODULE_ENABLED */
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi.h Source File

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stm32f7xx_hal_dcmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dcmi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DCMI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DCMI_H
00040 #define __STM32F7xx_HAL_DCMI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /* Include DCMI HAL Extended module */
00050 /* (include on top of file since DCMI structures are defined in extended file) */
00051 #include "stm32f7xx_hal_dcmi_ex.h"
00052
00053 /** @addtogroup STM32F7xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @addtogroup DCMI DCMI
00058   * @brief DCMI HAL module driver
00059   * @{
00060   */
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /** @defgroup DCMI_Exported_Types DCMI Exported Types
00064   * @{
00065   */
00066 /**
00067   * @brief  HAL DCMI State structures definition
00068   */
00069 typedef enum
00070 {
00071   HAL_DCMI_STATE_RESET             = 0x00,  /*!< DCMI not yet initialized or disabled  */
00072   HAL_DCMI_STATE_READY             = 0x01,  /*!< DCMI initialized and ready for use    */
00073   HAL_DCMI_STATE_BUSY              = 0x02,  /*!< DCMI internal processing is ongoing   */
00074   HAL_DCMI_STATE_TIMEOUT           = 0x03,  /*!< DCMI timeout state                    */
00075   HAL_DCMI_STATE_ERROR             = 0x04   /*!< DCMI error state                      */
00076 }HAL_DCMI_StateTypeDef;
00077
00078 /**
00079   * @brief  DCMI handle Structure definition
00080   */
00081 typedef struct
00082 {
00083   DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
00084
00085   DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */
00086
00087   HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
00088
00089   __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
00090
00091   __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */
00092
00093   __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
00094
00095   uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */
00096
00097   uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
00098
00099   DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
00100
00101   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
00102
00103 }DCMI_HandleTypeDef;
00104 /**
00105   * @}
00106   */
00107 /* Exported constants --------------------------------------------------------*/
00108
00109 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
00110   * @{
00111   */
00112
00113 /** @defgroup DCMI_Error_Code DCMI Error Code
00114   * @{
00115   */
00116 #define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
00117 #define HAL_DCMI_ERROR_OVF       ((uint32_t)0x00000001)    /*!< Overflow error        */
00118 #define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002)    /*!< Synchronization error */
00119 #define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
00125   * @{
00126   */
00127 #define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000)  /*!< The received data are transferred continuously
00128                                                                     into the destination memory through the DMA             */
00129 #define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of
00130                                                                     frame and then transfers a single frame through the DMA */
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
00136   * @{
00137   */
00138 #define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000)   /*!< Hardware synchronization data capture (frame/line start/stop)
00139                                                                    is synchronized with the HSYNC/VSYNC signals                  */
00140 #define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with
00141                                                                    synchronization codes embedded in the data flow               */
00142
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
00148   * @{
00149   */
00150 #define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000)      /*!< Pixel clock active on Falling edge */
00151 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
00158   * @{
00159   */
00160 #define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Vertical synchronization active Low  */
00161 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
00168   * @{
00169   */
00170 #define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Horizontal synchronization active Low  */
00171 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
00178   * @{
00179   */
00180 #define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000)    /*!< Mode JPEG Disabled  */
00181 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
00188   * @{
00189   */
00190 #define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000)      /*!< All frames are captured        */
00191 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
00192 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
00193
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
00199   * @{
00200   */
00201 #define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000)                       /*!< Interface captures 8-bit data on every pixel clock  */
00202 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
00203 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
00204 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
00211   * @{
00212   */
00213 #define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFF)  /*!< Window coordinate */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup DCMI_Window_Height DCMI Window Height
00220   * @{
00221   */
00222 #define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFF)  /*!< Window Height */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
00229   * @{
00230   */
00231 #define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)
00232 #define DCMI_IT_OVF      ((uint32_t)DCMI_IER_OVF_IE)
00233 #define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)
00234 #define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)
00235 #define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup DCMI_Flags DCMI Flags
00241   * @{
00242   */
00243
00244 /**
00245   * @brief   DCMI SR register
00246   */
00247 #define DCMI_FLAG_HSYNC     ((uint32_t)0x2001)
00248 #define DCMI_FLAG_VSYNC     ((uint32_t)0x2002)
00249 #define DCMI_FLAG_FNE       ((uint32_t)0x2004)
00250 /**
00251   * @brief   DCMI RISR register
00252   */
00253 #define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)
00254 #define DCMI_FLAG_OVFRI      ((uint32_t)DCMI_RISR_OVF_RIS)
00255 #define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)
00256 #define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)
00257 #define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)
00258 /**
00259   * @brief   DCMI MISR register
00260   */
00261 #define DCMI_FLAG_FRAMEMI    ((uint32_t)0x1001)
00262 #define DCMI_FLAG_OVFMI      ((uint32_t)0x1002)
00263 #define DCMI_FLAG_ERRMI      ((uint32_t)0x1004)
00264 #define DCMI_FLAG_VSYNCMI    ((uint32_t)0x1008)
00265 #define DCMI_FLAG_LINEMI     ((uint32_t)0x1010)
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /* Exported macro ------------------------------------------------------------*/
00275 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
00276   * @{
00277   */
00278
00279 /** @brief Reset DCMI handle state
00280   * @param  __HANDLE__: specifies the DCMI handle.
00281   * @retval None
00282   */
00283 #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
00284
00285 /**
00286   * @brief  Enable the DCMI.
00287   * @param  __HANDLE__: DCMI handle
00288   * @retval None
00289   */
00290 #define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
00291
00292 /**
00293   * @brief  Disable the DCMI.
00294   * @param  __HANDLE__: DCMI handle
00295   * @retval None
00296   */
00297 #define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
00298
00299 /* Interrupt & Flag management */
00300 /**
00301   * @brief  Get the DCMI pending flags.
00302   * @param  __HANDLE__: DCMI handle
00303   * @param  __FLAG__: Get the specified flag.
00304   *         This parameter can be any combination of the following values:
00305   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00306   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
00307   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00308   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00309   *            @arg DCMI_FLAG_LINERI: Line flag mask
00310   * @retval The state of FLAG.
00311   */
00312 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
00313 ((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
00314  (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
00315
00316 /**
00317   * @brief  Clear the DCMI pending flags.
00318   * @param  __HANDLE__: DCMI handle
00319   * @param  __FLAG__: specifies the flag to clear.
00320   *         This parameter can be any combination of the following values:
00321   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00322   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
00323   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00324   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00325   *            @arg DCMI_FLAG_LINERI: Line flag mask
00326   * @retval None
00327   */
00328 #define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00329
00330 /**
00331   * @brief  Enable the specified DCMI interrupts.
00332   * @param  __HANDLE__:    DCMI handle
00333   * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
00334   *         This parameter can be any combination of the following values:
00335   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00336   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00337   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00338   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00339   *            @arg DCMI_IT_LINE: Line interrupt mask
00340   * @retval None
00341   */
00342 #define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00343
00344 /**
00345   * @brief  Disable the specified DCMI interrupts.
00346   * @param  __HANDLE__: DCMI handle
00347   * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
00348   *         This parameter can be any combination of the following values:
00349   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00350   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00351   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00352   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00353   *            @arg DCMI_IT_LINE: Line interrupt mask
00354   * @retval None
00355   */
00356 #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00357
00358 /**
00359   * @brief  Check whether the specified DCMI interrupt has occurred or not.
00360   * @param  __HANDLE__: DCMI handle
00361   * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
00362   *         This parameter can be one of the following values:
00363   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00364   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00365   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00366   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00367   *            @arg DCMI_IT_LINE: Line interrupt mask
00368   * @retval The state of INTERRUPT.
00369   */
00370 #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
00371
00372 /**
00373   * @}
00374   */
00375
00376 /* Exported functions --------------------------------------------------------*/
00377 /** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
00378   * @{
00379   */
00380
00381 /** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00382  * @{
00383  */
00384 /* Initialization and de-initialization functions *****************************/
00385 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
00386 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
00387 void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
00388 void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
00389 /**
00390   * @}
00391   */
00392
00393 /** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
00394  * @{
00395  */
00396 /* IO operation functions *****************************************************/
00397 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
00398 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
00399 void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
00400 void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
00401 void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
00402 void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
00403 void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
00404 /**
00405   * @}
00406   */
00407
00408 /** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00409  * @{
00410  */
00411 /* Peripheral Control functions ***********************************************/
00412 HAL_StatusTypeDef     HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
00413 HAL_StatusTypeDef     HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
00414 HAL_StatusTypeDef     HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
00415 /**
00416   * @}
00417   */
00418
00419 /** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
00420  * @{
00421  */
00422 /* Peripheral State functions *************************************************/
00423 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
00424 uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
00425 /**
00426   * @}
00427   */
00428
00429 /**
00430   * @}
00431   */
00432
00433 /* Private types -------------------------------------------------------------*/
00434 /* Private variables ---------------------------------------------------------*/
00435 /* Private constants ---------------------------------------------------------*/
00436 /* Private macro -------------------------------------------------------------*/
00437 /** @defgroup DCMI_Private_Macros DCMI Private Macros
00438   * @{
00439   */
00440 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
00441                                    ((MODE) == DCMI_MODE_SNAPSHOT))
00442
00443 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
00444                               ((MODE) == DCMI_SYNCHRO_EMBEDDED))
00445
00446 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
00447                                       ((POLARITY) == DCMI_PCKPOLARITY_RISING))
00448
00449 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
00450                                      ((POLARITY) == DCMI_VSPOLARITY_HIGH))
00451
00452 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
00453                                      ((POLARITY) == DCMI_HSPOLARITY_HIGH))
00454
00455 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
00456                                      ((JPEG_MODE) == DCMI_JPEG_ENABLE))
00457
00458 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
00459                                     ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
00460                                     ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
00461
00462 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
00463                                     ((DATA) == DCMI_EXTEND_DATA_10B) || \
00464                                     ((DATA) == DCMI_EXTEND_DATA_12B) || \
00465                                     ((DATA) == DCMI_EXTEND_DATA_14B))
00466
00467 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
00468
00469 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
00470
00471 /**
00472   * @}
00473   */
00474
00475 /* Private functions ---------------------------------------------------------*/
00476 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
00477   * @{
00478   */
00479
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487 /**
00488   * @}
00489   */
00490
00491 #ifdef __cplusplus
00492 }
00493 #endif
00494
00495 #endif /* __STM32F7xx_HAL_DCMI_H */
00496
00497 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi_ex.c Source File

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stm32f7xx_hal_dcmi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dcmi_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   DCMI Extension HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of DCMI extension peripheral:
00010   *           + Extension features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### DCMI peripheral extension features  #####
00015   ==============================================================================
00016
00017   [..]  Support of Black and White cameras
00018
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021   [..] This driver provides functions to manage the Black and White feature
00022
00023   @endverbatim
00024   ******************************************************************************
00025   * @attention
00026   *
00027   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00028   *
00029   * Redistribution and use in source and binary forms, with or without modification,
00030   * are permitted provided that the following conditions are met:
00031   *   1. Redistributions of source code must retain the above copyright notice,
00032   *      this list of conditions and the following disclaimer.
00033   *   2. Redistributions in binary form must reproduce the above copyright notice,
00034   *      this list of conditions and the following disclaimer in the documentation
00035   *      and/or other materials provided with the distribution.
00036   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00037   *      may be used to endorse or promote products derived from this software
00038   *      without specific prior written permission.
00039   *
00040   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00041   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00042   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00043   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00044   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00045   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00046   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00047   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00048   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00049   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00050   *
00051   ******************************************************************************
00052   */
00053
00054 /* Includes ------------------------------------------------------------------*/
00055 #include "stm32f7xx_hal.h"
00056
00057 /** @addtogroup STM32F7xx_HAL_Driver
00058   * @{
00059   */
00060 /** @defgroup DCMIEx DCMIEx
00061   * @brief DCMI Extended HAL module driver
00062   * @{
00063   */
00064
00065 #ifdef HAL_DCMI_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 /* Private macro -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Exported functions --------------------------------------------------------*/
00073
00074 /** @defgroup DCMIEx_Exported_Functions DCMIEx Exported Functions
00075   * @{
00076   */
00077
00078 /** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions
00079  *  @brief   Initialization and Configuration functions
00080  *
00081 @verbatim
00082  ===============================================================================
00083                 ##### Initialization and Configuration functions #####
00084  ===============================================================================
00085     [..]  This section provides functions allowing to:
00086       (+) Initialize and configure the DCMI
00087       (+) De-initialize the DCMI
00088
00089 @endverbatim
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  Initializes the DCMI according to the specified
00095   *         parameters in the DCMI_InitTypeDef and create the associated handle.
00096   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00097   *                the configuration information for DCMI.
00098   * @retval HAL status
00099   */
00100 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
00101 {
00102   /* Check the DCMI peripheral state */
00103   if(hdcmi == NULL)
00104   {
00105      return HAL_ERROR;
00106   }
00107
00108   /* Check function parameters */
00109   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
00110   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
00111   assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
00112   assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
00113   assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
00114   assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
00115   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
00116   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
00117
00118   assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
00119   assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
00120   assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
00121   assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
00122
00123   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00124   {
00125     /* Init the low level hardware */
00126     HAL_DCMI_MspInit(hdcmi);
00127   }
00128
00129   /* Change the DCMI state */
00130   hdcmi->State = HAL_DCMI_STATE_BUSY;
00131                           /* Configures the HS, VS, DE and PC polarity */
00132   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\
00133                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\
00134                            DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
00135                            DCMI_CR_LSM | DCMI_CR_OELS);
00136
00137   hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
00138                                      hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  |\
00139                                      hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
00140                                      hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
00141                                      hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
00142                                      hdcmi->Init.LineSelectStart);
00143
00144   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
00145   {
00146     DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
00147                   ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
00148                   ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
00149                   ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
00150
00151   }
00152
00153   /* Enable the Line interrupt */
00154   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
00155
00156   /* Enable the VSYNC interrupt */
00157   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
00158
00159   /* Enable the Frame capture complete interrupt */
00160   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
00161
00162   /* Enable the Synchronization error interrupt */
00163   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
00164
00165   /* Enable the Overflow interrupt */
00166   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
00167
00168   /* Enable DCMI by setting DCMIEN bit */
00169   __HAL_DCMI_ENABLE(hdcmi);
00170
00171   /* Update error code */
00172   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00173
00174   /* Initialize the DCMI state*/
00175   hdcmi->State  = HAL_DCMI_STATE_READY;
00176
00177   return HAL_OK;
00178 }
00179
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192 #endif /* HAL_DCMI_MODULE_ENABLED */
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dcmi_ex.h Source File

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stm32f7xx_hal_dcmi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dcmi_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DCMI Extension HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DCMI_EX_H
00040 #define __STM32F7xx_HAL_DCMI_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050
00051 /** @addtogroup STM32F7xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup DCMIEx DCMIEx
00056   * @{
00057   */
00058
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup DCMIEx_Exported_Types DCMIEx Exported Types
00062   * @{
00063   */
00064 /**
00065   * @brief   DCMIEx Embedded Synchronisation CODE Init structure definition
00066   */
00067 typedef struct
00068 {
00069   uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
00070   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
00071   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
00072   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
00073 }DCMI_CodesInitTypeDef;
00074
00075 /**
00076   * @brief   DCMI Init structure definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
00081                                              This parameter can be a value of @ref DCMI_Synchronization_Mode */
00082
00083   uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
00084                                              This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
00085
00086   uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
00087                                              This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
00088
00089   uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
00090                                              This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
00091
00092   uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
00093                                              This parameter can be a value of @ref DCMI_Capture_Rate         */
00094
00095   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
00096                                              This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
00097
00098   DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                */
00099
00100   uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
00101                                              This parameter can be a value of @ref DCMI_MODE_JPEG            */
00102
00103   uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface
00104                                             This parameter can be a value of @ref DCMIEx_Byte_Select_Mode      */
00105
00106   uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd
00107                                             This parameter can be a value of @ref DCMIEx_Byte_Select_Start     */
00108
00109   uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface
00110                                             This parameter can be a value of @ref DCMIEx_Line_Select_Mode      */
00111
00112   uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd
00113                                             This parameter can be a value of @ref DCMIEx_Line_Select_Start     */
00114 }DCMI_InitTypeDef;
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Exported constants --------------------------------------------------------*/
00121 /** @defgroup DCMIEx_Exported_Constants DCMIEx Exported Constants
00122   * @{
00123   */
00124
00125 /** @defgroup DCMIEx_Byte_Select_Mode DCMIEx Byte Select Mode
00126   * @{
00127   */
00128 #define DCMI_BSM_ALL                 ((uint32_t)0x00000000) /*!< Interface captures all received data */
00129 #define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
00130 #define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
00131 #define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
00132
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup DCMIEx_Byte_Select_Start DCMIEx Byte Select Start
00138   * @{
00139   */
00140 #define DCMI_OEBS_ODD               ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
00141 #define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
00142
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup DCMIEx_Line_Select_Mode DCMIEx Line Select Mode
00148   * @{
00149   */
00150 #define DCMI_LSM_ALL                 ((uint32_t)0x00000000) /*!< Interface captures all received lines */
00151 #define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup DCMIEx_Line_Select_Start DCMIEx Line Select Start
00158   * @{
00159   */
00160 #define DCMI_OELS_ODD               ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
00161 #define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 /* Exported macro ------------------------------------------------------------*/
00172 /* Exported functions --------------------------------------------------------*/
00173 /* Private types -------------------------------------------------------------*/
00174 /* Private variables ---------------------------------------------------------*/
00175 /* Private constants ---------------------------------------------------------*/
00176 /* Private macro -------------------------------------------------------------*/
00177 /** @defgroup DCMIEx_Private_Macros DCMIEx Private Macros
00178   * @{
00179   */
00180 #define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
00181                                        ((MODE) == DCMI_BSM_OTHER) || \
00182                                        ((MODE) == DCMI_BSM_ALTERNATE_4) || \
00183                                        ((MODE) == DCMI_BSM_ALTERNATE_2))
00184
00185 #define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
00186                                             ((POLARITY) == DCMI_OEBS_EVEN))
00187
00188 #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
00189                                        ((MODE) == DCMI_LSM_ALTERNATE_2))
00190
00191 #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
00192                                             ((POLARITY) == DCMI_OELS_EVEN))
00193 /**
00194   * @}
00195   */
00196
00197 /* Private functions ---------------------------------------------------------*/
00198
00199 /**
00200   * @}
00201   */
00202
00203 /**
00204   * @}
00205   */
00206
00207 #ifdef __cplusplus
00208 }
00209 #endif
00210
00211 #endif /* __STM32F7xx_HAL_DCMI_H */
00212
00213 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma2d.c Source File

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stm32f7xx_hal_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dma2d.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   DMA2D HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the DMA2D peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#) Program the required configuration through following parameters:
00021           the Transfer Mode, the output color mode and the output offset using
00022           HAL_DMA2D_Init() function.
00023
00024       (#) Program the required configuration through following parameters:
00025           the input color mode, the input color, input alpha value, alpha mode
00026           and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
00027           or/and background layer.
00028
00029      *** Polling mode IO operation ***
00030      =================================
00031     [..]
00032        (+) Configure the pdata, Destination and data length and Enable
00033            the transfer using HAL_DMA2D_Start()
00034        (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
00035            user can specify the value of timeout according to his end application.
00036
00037      *** Interrupt mode IO operation ***
00038      ===================================
00039      [..]
00040        (#) Configure the pdata, Destination and data length and Enable
00041            the transfer using HAL_DMA2D_Start_IT()
00042        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
00043        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
00044            add his own function by customization of function pointer XferCpltCallback and
00045            XferErrorCallback (i.e a member of DMA2D handle structure).
00046
00047          -@-   In Register-to-Memory transfer mode, the pdata parameter is the register
00048                color, in Memory-to-memory or memory-to-memory with pixel format
00049                conversion the pdata is the source address.
00050
00051          -@-   Configure the foreground source address, the background source address,
00052                the Destination and data length and Enable the transfer using
00053                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
00054                in interrupt mode.
00055
00056          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
00057                are used if the memory to memory with blending transfer mode is selected.
00058
00059       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
00060           HAL_DMA2D_EnableCLUT() functions.
00061
00062       (#) Optionally, configure and enable LineInterrupt using the following function:
00063           HAL_DMA2D_ProgramLineEvent().
00064
00065       (#) The transfer can be suspended, continued and aborted using the following
00066           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
00067
00068       (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()
00069
00070      *** DMA2D HAL driver macros list ***
00071      =============================================
00072      [..]
00073        Below the list of most used macros in DMA2D HAL driver :
00074
00075       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
00076       (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
00077       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
00078       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
00079       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
00080       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
00081       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
00082
00083      [..]
00084       (@) You can refer to the DMA2D HAL driver header file for more useful macros
00085
00086   @endverbatim
00087   ******************************************************************************
00088   * @attention
00089   *
00090   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00091   *
00092   * Redistribution and use in source and binary forms, with or without modification,
00093   * are permitted provided that the following conditions are met:
00094   *   1. Redistributions of source code must retain the above copyright notice,
00095   *      this list of conditions and the following disclaimer.
00096   *   2. Redistributions in binary form must reproduce the above copyright notice,
00097   *      this list of conditions and the following disclaimer in the documentation
00098   *      and/or other materials provided with the distribution.
00099   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00100   *      may be used to endorse or promote products derived from this software
00101   *      without specific prior written permission.
00102   *
00103   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00104   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00105   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00106   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00107   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00108   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00109   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00110   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00111   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00112   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00113   *
00114   ******************************************************************************
00115   */
00116
00117 /* Includes ------------------------------------------------------------------*/
00118 #include "stm32f7xx_hal.h"
00119
00120 /** @addtogroup STM32F7xx_HAL_Driver
00121   * @{
00122   */
00123 /** @addtogroup DMA2D
00124   * @brief DMA2D HAL module driver
00125   * @{
00126   */
00127
00128 #ifdef HAL_DMA2D_MODULE_ENABLED
00129
00130 /* Private types -------------------------------------------------------------*/
00131 /* Private define ------------------------------------------------------------*/
00132 /** @addtogroup DMA2D_Private_Defines
00133   * @{
00134   */
00135 #define HAL_TIMEOUT_DMA2D_ABORT      ((uint32_t)1000)  /* 1s  */
00136 #define HAL_TIMEOUT_DMA2D_SUSPEND    ((uint32_t)1000)  /* 1s  */
00137 /**
00138   * @}
00139   */
00140
00141 /* Private variables ---------------------------------------------------------*/
00142 /* Private constants ---------------------------------------------------------*/
00143 /* Private macro -------------------------------------------------------------*/
00144 /* Private function prototypes -----------------------------------------------*/
00145 /** @addtogroup DMA2D_Private_Functions_Prototypes
00146   * @{
00147   */
00148 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00149 /**
00150   * @}
00151   */
00152
00153 /* Private functions ---------------------------------------------------------*/
00154 /* Exported functions --------------------------------------------------------*/
00155 /** @addtogroup DMA2D_Exported_Functions
00156   * @{
00157   */
00158
00159 /** @defgroup DMA2D_Group1 Initialization and Configuration functions
00160  *  @brief   Initialization and Configuration functions
00161  *
00162 @verbatim
00163  ===============================================================================
00164                 ##### Initialization and Configuration functions #####
00165  ===============================================================================
00166     [..]  This section provides functions allowing to:
00167       (+) Initialize and configure the DMA2D
00168       (+) De-initialize the DMA2D
00169
00170 @endverbatim
00171   * @{
00172   */
00173
00174 /**
00175   * @brief  Initializes the DMA2D according to the specified
00176   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00177   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00178   *                 the configuration information for the DMA2D.
00179   * @retval HAL status
00180   */
00181 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
00182 {
00183   uint32_t tmp = 0;
00184
00185   /* Check the DMA2D peripheral state */
00186   if(hdma2d == NULL)
00187   {
00188      return HAL_ERROR;
00189   }
00190
00191   /* Check the parameters */
00192   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
00193   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
00194   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
00195   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
00196
00197   if(hdma2d->State == HAL_DMA2D_STATE_RESET)
00198   {
00199     /* Allocate lock resource and initialize it */
00200     hdma2d->Lock = HAL_UNLOCKED;
00201     /* Init the low level hardware */
00202     HAL_DMA2D_MspInit(hdma2d);
00203   }
00204
00205   /* Change DMA2D peripheral state */
00206   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00207
00208 /* DMA2D CR register configuration -------------------------------------------*/
00209   /* Get the CR register value */
00210   tmp = hdma2d->Instance->CR;
00211
00212   /* Clear Mode bits */
00213   tmp &= (uint32_t)~DMA2D_CR_MODE;
00214
00215   /* Prepare the value to be wrote to the CR register */
00216   tmp |= hdma2d->Init.Mode;
00217
00218   /* Write to DMA2D CR register */
00219   hdma2d->Instance->CR = tmp;
00220
00221 /* DMA2D OPFCCR register configuration ---------------------------------------*/
00222   /* Get the OPFCCR register value */
00223   tmp = hdma2d->Instance->OPFCCR;
00224
00225   /* Clear Color Mode bits */
00226   tmp &= (uint32_t)~DMA2D_OPFCCR_CM;
00227
00228   /* Prepare the value to be wrote to the OPFCCR register */
00229   tmp |= hdma2d->Init.ColorMode;
00230
00231   /* Write to DMA2D OPFCCR register */
00232   hdma2d->Instance->OPFCCR = tmp;
00233
00234 /* DMA2D OOR register configuration ------------------------------------------*/
00235   /* Get the OOR register value */
00236   tmp = hdma2d->Instance->OOR;
00237
00238   /* Clear Offset bits */
00239   tmp &= (uint32_t)~DMA2D_OOR_LO;
00240
00241   /* Prepare the value to be wrote to the OOR register */
00242   tmp |= hdma2d->Init.OutputOffset;
00243
00244   /* Write to DMA2D OOR register */
00245   hdma2d->Instance->OOR = tmp;
00246
00247   /* Update error code */
00248   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00249
00250   /* Initialize the DMA2D state*/
00251   hdma2d->State  = HAL_DMA2D_STATE_READY;
00252
00253   return HAL_OK;
00254 }
00255
00256 /**
00257   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
00258   *         values.
00259   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00260   *                 the configuration information for the DMA2D.
00261   * @retval None
00262   */
00263
00264 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
00265 {
00266   /* Check the DMA2D peripheral state */
00267   if(hdma2d == NULL)
00268   {
00269      return HAL_ERROR;
00270   }
00271
00272   /* DeInit the low level hardware */
00273   HAL_DMA2D_MspDeInit(hdma2d);
00274
00275   /* Update error code */
00276   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00277
00278   /* Initialize the DMA2D state*/
00279   hdma2d->State  = HAL_DMA2D_STATE_RESET;
00280
00281   /* Release Lock */
00282   __HAL_UNLOCK(hdma2d);
00283
00284   return HAL_OK;
00285 }
00286
00287 /**
00288   * @brief  Initializes the DMA2D MSP.
00289   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00290   *                 the configuration information for the DMA2D.
00291   * @retval None
00292   */
00293 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
00294 {
00295   /* Prevent unused argument(s) compilation warning */
00296   UNUSED(hdma2d);
00297
00298   /* NOTE : This function Should not be modified, when the callback is needed,
00299             the HAL_DMA2D_MspInit could be implemented in the user file
00300    */
00301 }
00302
00303 /**
00304   * @brief  DeInitializes the DMA2D MSP.
00305   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00306   *                 the configuration information for the DMA2D.
00307   * @retval None
00308   */
00309 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
00310 {
00311   /* Prevent unused argument(s) compilation warning */
00312   UNUSED(hdma2d);
00313
00314   /* NOTE : This function Should not be modified, when the callback is needed,
00315             the HAL_DMA2D_MspDeInit could be implemented in the user file
00316    */
00317 }
00318
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup DMA2D_Group2 IO operation functions
00324  *  @brief   IO operation functions
00325  *
00326 @verbatim
00327  ===============================================================================
00328                       #####  IO operation functions  #####
00329  ===============================================================================
00330     [..]  This section provides functions allowing to:
00331       (+) Configure the pdata, destination address and data size and
00332           Start DMA2D transfer.
00333       (+) Configure the source for foreground and background, destination address
00334           and data size and Start MultiBuffer DMA2D transfer.
00335       (+) Configure the pdata, destination address and data size and
00336           Start DMA2D transfer with interrupt.
00337       (+) Configure the source for foreground and background, destination address
00338           and data size and Start MultiBuffer DMA2D transfer with interrupt.
00339       (+) Abort DMA2D transfer.
00340       (+) Suspend DMA2D transfer.
00341       (+) Continue DMA2D transfer.
00342       (+) Poll for transfer complete.
00343       (+) handle DMA2D interrupt request.
00344
00345 @endverbatim
00346   * @{
00347   */
00348
00349 /**
00350   * @brief  Start the DMA2D Transfer.
00351   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
00352   *                     the configuration information for the DMA2D.
00353   * @param  pdata:      Configure the source memory Buffer address if
00354   *                     the memory to memory or memory to memory with pixel format
00355   *                     conversion DMA2D mode is selected, and configure
00356   *                     the color value if register to memory DMA2D mode is selected.
00357   * @param  DstAddress: The destination memory Buffer address.
00358   * @param  Width:      The width of data to be transferred from source to destination.
00359   * @param  Height:      The height of data to be transferred from source to destination.
00360   * @retval HAL status
00361   */
00362 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00363 {
00364   /* Process locked */
00365   __HAL_LOCK(hdma2d);
00366
00367   /* Change DMA2D peripheral state */
00368   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00369
00370   /* Check the parameters */
00371   assert_param(IS_DMA2D_LINE(Height));
00372   assert_param(IS_DMA2D_PIXEL(Width));
00373
00374   /* Disable the Peripheral */
00375   __HAL_DMA2D_DISABLE(hdma2d);
00376
00377   /* Configure the source, destination address and the data size */
00378   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00379
00380   /* Enable the Peripheral */
00381   __HAL_DMA2D_ENABLE(hdma2d);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Start the DMA2D Transfer with interrupt enabled.
00388   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
00389   *                     the configuration information for the DMA2D.
00390   * @param  pdata:      Configure the source memory Buffer address if
00391   *                     the memory to memory or memory to memory with pixel format
00392   *                     conversion DMA2D mode is selected, and configure
00393   *                     the color value if register to memory DMA2D mode is selected.
00394   * @param  DstAddress: The destination memory Buffer address.
00395   * @param  Width:      The width of data to be transferred from source to destination.
00396   * @param  Height:     The height of data to be transferred from source to destination.
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00400 {
00401   /* Process locked */
00402   __HAL_LOCK(hdma2d);
00403
00404   /* Change DMA2D peripheral state */
00405   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00406
00407   /* Check the parameters */
00408   assert_param(IS_DMA2D_LINE(Height));
00409   assert_param(IS_DMA2D_PIXEL(Width));
00410
00411   /* Disable the Peripheral */
00412   __HAL_DMA2D_DISABLE(hdma2d);
00413
00414   /* Configure the source, destination address and the data size */
00415   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00416
00417   /* Enable the transfer complete interrupt */
00418   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
00419
00420   /* Enable the transfer Error interrupt */
00421   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
00422
00423   /* Enable the Peripheral */
00424   __HAL_DMA2D_ENABLE(hdma2d);
00425
00426   /* Enable the configuration error interrupt */
00427   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
00428
00429   return HAL_OK;
00430 }
00431
00432 /**
00433   * @brief  Start the multi-source DMA2D Transfer.
00434   * @param  hdma2d:      pointer to a DMA2D_HandleTypeDef structure that contains
00435   *                      the configuration information for the DMA2D.
00436   * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
00437   * @param  SrcAddress2: The source memory Buffer address of the background layer.
00438   * @param  DstAddress:  The destination memory Buffer address
00439   * @param  Width:       The width of data to be transferred from source to destination.
00440   * @param  Height:      The height of data to be transferred from source to destination.
00441   * @retval HAL status
00442   */
00443 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00444 {
00445   /* Process locked */
00446   __HAL_LOCK(hdma2d);
00447
00448   /* Change DMA2D peripheral state */
00449   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00450
00451   /* Check the parameters */
00452   assert_param(IS_DMA2D_LINE(Height));
00453   assert_param(IS_DMA2D_PIXEL(Width));
00454
00455   /* Disable the Peripheral */
00456   __HAL_DMA2D_DISABLE(hdma2d);
00457
00458   /* Configure DMA2D Stream source2 address */
00459   hdma2d->Instance->BGMAR = SrcAddress2;
00460
00461   /* Configure the source, destination address and the data size */
00462   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00463
00464   /* Enable the Peripheral */
00465   __HAL_DMA2D_ENABLE(hdma2d);
00466
00467   return HAL_OK;
00468 }
00469
00470 /**
00471   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
00472   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
00473   *                     the configuration information for the DMA2D.
00474   * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
00475   * @param  SrcAddress2: The source memory Buffer address of the background layer.
00476   * @param  DstAddress:  The destination memory Buffer address.
00477   * @param  Width:       The width of data to be transferred from source to destination.
00478   * @param  Height:      The height of data to be transferred from source to destination.
00479   * @retval HAL status
00480   */
00481 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00482 {
00483   /* Process locked */
00484   __HAL_LOCK(hdma2d);
00485
00486   /* Change DMA2D peripheral state */
00487   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00488
00489   /* Check the parameters */
00490   assert_param(IS_DMA2D_LINE(Height));
00491   assert_param(IS_DMA2D_PIXEL(Width));
00492
00493   /* Disable the Peripheral */
00494   __HAL_DMA2D_DISABLE(hdma2d);
00495
00496   /* Configure DMA2D Stream source2 address */
00497   hdma2d->Instance->BGMAR = SrcAddress2;
00498
00499   /* Configure the source, destination address and the data size */
00500   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00501
00502   /* Enable the configuration error interrupt */
00503   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
00504
00505   /* Enable the transfer complete interrupt */
00506   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
00507
00508   /* Enable the transfer Error interrupt */
00509   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
00510
00511   /* Enable the Peripheral */
00512   __HAL_DMA2D_ENABLE(hdma2d);
00513
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @brief  Abort the DMA2D Transfer.
00519   * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
00520   *                  the configuration information for the DMA2D.
00521   * @retval HAL status
00522   */
00523 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
00524 {
00525   uint32_t tickstart = 0;
00526
00527   /* Disable the DMA2D */
00528   __HAL_DMA2D_DISABLE(hdma2d);
00529
00530   /* Get tick */
00531   tickstart = HAL_GetTick();
00532
00533   /* Check if the DMA2D is effectively disabled */
00534   while((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
00535   {
00536     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT)
00537     {
00538       /* Update error code */
00539       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00540
00541       /* Change the DMA2D state */
00542       hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00543
00544       /* Process Unlocked */
00545       __HAL_UNLOCK(hdma2d);
00546
00547       return HAL_TIMEOUT;
00548     }
00549   }
00550   /* Process Unlocked */
00551   __HAL_UNLOCK(hdma2d);
00552
00553   /* Change the DMA2D state*/
00554   hdma2d->State = HAL_DMA2D_STATE_READY;
00555
00556   return HAL_OK;
00557 }
00558
00559 /**
00560   * @brief  Suspend the DMA2D Transfer.
00561   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00562   *                 the configuration information for the DMA2D.
00563   * @retval HAL status
00564   */
00565 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
00566 {
00567   uint32_t tickstart = 0;
00568
00569   /* Suspend the DMA2D transfer */
00570   hdma2d->Instance->CR |= DMA2D_CR_SUSP;
00571
00572   /* Get tick */
00573   tickstart = HAL_GetTick();
00574
00575   /* Check if the DMA2D is effectively suspended */
00576   while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP)
00577   {
00578     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND)
00579     {
00580       /* Update error code */
00581       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00582
00583       /* Change the DMA2D state */
00584       hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00585
00586       return HAL_TIMEOUT;
00587     }
00588   }
00589   /* Change the DMA2D state*/
00590   hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00591
00592   return HAL_OK;
00593 }
00594
00595 /**
00596   * @brief  Resume the DMA2D Transfer.
00597   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00598   *                 the configuration information for the DMA2D.
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
00602 {
00603   /* Resume the DMA2D transfer */
00604   hdma2d->Instance->CR &= ~DMA2D_CR_SUSP;
00605
00606   /* Change the DMA2D state*/
00607   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00608
00609   return HAL_OK;
00610 }
00611
00612 /**
00613   * @brief  Polling for transfer complete or CLUT loading.
00614   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00615   *                 the configuration information for the DMA2D.
00616   * @param  Timeout: Timeout duration
00617   * @retval HAL status
00618   */
00619 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
00620 {
00621   uint32_t tmp, tmp1;
00622   uint32_t tickstart = 0;
00623
00624   /* Polling for DMA2D transfer */
00625   if((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
00626   {
00627    /* Get tick */
00628    tickstart = HAL_GetTick();
00629
00630     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
00631     {
00632       tmp  = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE);
00633       tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE);
00634
00635       if((tmp != RESET) || (tmp1 != RESET))
00636       {
00637         /* Clear the transfer and configuration error flags */
00638         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
00639         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
00640
00641         /* Change DMA2D state */
00642         hdma2d->State= HAL_DMA2D_STATE_ERROR;
00643
00644         /* Process unlocked */
00645         __HAL_UNLOCK(hdma2d);
00646
00647         return HAL_ERROR;
00648       }
00649       /* Check for the Timeout */
00650       if(Timeout != HAL_MAX_DELAY)
00651       {
00652         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00653         {
00654           /* Process unlocked */
00655           __HAL_UNLOCK(hdma2d);
00656
00657           /* Update error code */
00658           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00659
00660           /* Change the DMA2D state */
00661           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00662
00663           return HAL_TIMEOUT;
00664         }
00665       }
00666     }
00667   }
00668   /* Polling for CLUT loading */
00669   if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0)
00670   {
00671     /* Get tick */
00672     tickstart = HAL_GetTick();
00673
00674     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
00675     {
00676       if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
00677       {
00678         /* Clear the transfer and configuration error flags */
00679         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
00680
00681         /* Change DMA2D state */
00682         hdma2d->State= HAL_DMA2D_STATE_ERROR;
00683
00684         return HAL_ERROR;
00685       }
00686       /* Check for the Timeout */
00687       if(Timeout != HAL_MAX_DELAY)
00688       {
00689         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00690         {
00691           /* Update error code */
00692           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00693
00694           /* Change the DMA2D state */
00695           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00696
00697           return HAL_TIMEOUT;
00698         }
00699       }
00700     }
00701   }
00702   /* Clear the transfer complete flag */
00703   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
00704
00705   /* Clear the CLUT loading flag */
00706   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
00707
00708   /* Change DMA2D state */
00709   hdma2d->State = HAL_DMA2D_STATE_READY;
00710
00711   /* Process unlocked */
00712   __HAL_UNLOCK(hdma2d);
00713
00714   return HAL_OK;
00715 }
00716 /**
00717   * @brief  Handles DMA2D interrupt request.
00718   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00719   *                 the configuration information for the DMA2D.
00720   * @retval HAL status
00721   */
00722 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
00723 {
00724   /* Transfer Error Interrupt management ***************************************/
00725   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
00726   {
00727     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)
00728     {
00729       /* Disable the transfer Error interrupt */
00730       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
00731
00732       /* Update error code */
00733       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
00734
00735       /* Clear the transfer error flag */
00736       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
00737
00738       /* Change DMA2D state */
00739       hdma2d->State = HAL_DMA2D_STATE_ERROR;
00740
00741       /* Process Unlocked */
00742       __HAL_UNLOCK(hdma2d);
00743
00744       if(hdma2d->XferErrorCallback != NULL)
00745       {
00746         /* Transfer error Callback */
00747         hdma2d->XferErrorCallback(hdma2d);
00748       }
00749     }
00750   }
00751   /* Configuration Error Interrupt management **********************************/
00752   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
00753   {
00754     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)
00755     {
00756       /* Disable the Configuration Error interrupt */
00757       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
00758
00759       /* Clear the Configuration error flag */
00760       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
00761
00762       /* Update error code */
00763       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
00764
00765       /* Change DMA2D state */
00766       hdma2d->State = HAL_DMA2D_STATE_ERROR;
00767
00768       /* Process Unlocked */
00769       __HAL_UNLOCK(hdma2d);
00770
00771       if(hdma2d->XferErrorCallback != NULL)
00772       {
00773         /* Transfer error Callback */
00774         hdma2d->XferErrorCallback(hdma2d);
00775       }
00776     }
00777   }
00778   /* Transfer Complete Interrupt management ************************************/
00779   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)
00780   {
00781     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)
00782     {
00783       /* Disable the transfer complete interrupt */
00784       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
00785
00786       /* Clear the transfer complete flag */
00787       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
00788
00789       /* Update error code */
00790       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
00791
00792       /* Change DMA2D state */
00793       hdma2d->State = HAL_DMA2D_STATE_READY;
00794
00795       /* Process Unlocked */
00796       __HAL_UNLOCK(hdma2d);
00797
00798       if(hdma2d->XferCpltCallback != NULL)
00799       {
00800         /* Transfer complete Callback */
00801         hdma2d->XferCpltCallback(hdma2d);
00802       }
00803     }
00804   }
00805 }
00806
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup DMA2D_Group3 Peripheral Control functions
00812  *  @brief    Peripheral Control functions
00813  *
00814 @verbatim
00815  ===============================================================================
00816                     ##### Peripheral Control functions #####
00817  ===============================================================================
00818     [..]  This section provides functions allowing to:
00819       (+) Configure the DMA2D foreground or/and background parameters.
00820       (+) Configure the DMA2D CLUT transfer.
00821       (+) Enable DMA2D CLUT.
00822       (+) Disable DMA2D CLUT.
00823       (+) Configure the line watermark
00824
00825 @endverbatim
00826   * @{
00827   */
00828 /**
00829   * @brief  Configure the DMA2D Layer according to the specified
00830   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00831   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00832   *                 the configuration information for the DMA2D.
00833   * @param  LayerIdx: DMA2D Layer index.
00834   *                   This parameter can be one of the following values:
00835   *                   0(background) / 1(foreground)
00836   * @retval HAL status
00837   */
00838 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00839 {
00840   DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
00841
00842   uint32_t tmp = 0;
00843
00844   /* Process locked */
00845   __HAL_LOCK(hdma2d);
00846
00847   /* Change DMA2D peripheral state */
00848   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00849
00850   /* Check the parameters */
00851   assert_param(IS_DMA2D_LAYER(LayerIdx));
00852   assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
00853   if(hdma2d->Init.Mode != DMA2D_R2M)
00854   {
00855     assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
00856     if(hdma2d->Init.Mode != DMA2D_M2M)
00857     {
00858       assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
00859     }
00860   }
00861
00862   /* Configure the background DMA2D layer */
00863   if(LayerIdx == 0)
00864   {
00865     /* DMA2D BGPFCR register configuration -----------------------------------*/
00866     /* Get the BGPFCCR register value */
00867     tmp = hdma2d->Instance->BGPFCCR;
00868
00869     /* Clear Input color mode, alpha value and alpha mode bits */
00870     tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA);
00871
00872     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
00873     {
00874       /* Prepare the value to be wrote to the BGPFCCR register */
00875       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));
00876     }
00877     else
00878     {
00879       /* Prepare the value to be wrote to the BGPFCCR register */
00880       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
00881     }
00882
00883     /* Write to DMA2D BGPFCCR register */
00884     hdma2d->Instance->BGPFCCR = tmp;
00885
00886     /* DMA2D BGOR register configuration -------------------------------------*/
00887     /* Get the BGOR register value */
00888     tmp = hdma2d->Instance->BGOR;
00889
00890     /* Clear colors bits */
00891     tmp &= (uint32_t)~DMA2D_BGOR_LO;
00892
00893     /* Prepare the value to be wrote to the BGOR register */
00894     tmp |= pLayerCfg->InputOffset;
00895
00896     /* Write to DMA2D BGOR register */
00897     hdma2d->Instance->BGOR = tmp;
00898
00899     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
00900     {
00901       /* Prepare the value to be wrote to the BGCOLR register */
00902       tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
00903
00904       /* Write to DMA2D BGCOLR register */
00905       hdma2d->Instance->BGCOLR = tmp;
00906     }
00907   }
00908   /* Configure the foreground DMA2D layer */
00909   else
00910   {
00911     /* DMA2D FGPFCR register configuration -----------------------------------*/
00912     /* Get the FGPFCCR register value */
00913     tmp = hdma2d->Instance->FGPFCCR;
00914
00915     /* Clear Input color mode, alpha value and alpha mode bits */
00916     tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA);
00917
00918     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
00919     {
00920       /* Prepare the value to be wrote to the FGPFCCR register */
00921       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));
00922     }
00923     else
00924     {
00925       /* Prepare the value to be wrote to the FGPFCCR register */
00926       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
00927     }
00928
00929     /* Write to DMA2D FGPFCCR register */
00930     hdma2d->Instance->FGPFCCR = tmp;
00931
00932     /* DMA2D FGOR register configuration -------------------------------------*/
00933     /* Get the FGOR register value */
00934     tmp = hdma2d->Instance->FGOR;
00935
00936     /* Clear colors bits */
00937     tmp &= (uint32_t)~DMA2D_FGOR_LO;
00938
00939     /* Prepare the value to be wrote to the FGOR register */
00940     tmp |= pLayerCfg->InputOffset;
00941
00942     /* Write to DMA2D FGOR register */
00943     hdma2d->Instance->FGOR = tmp;
00944
00945     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
00946     {
00947       /* Prepare the value to be wrote to the FGCOLR register */
00948       tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
00949
00950       /* Write to DMA2D FGCOLR register */
00951       hdma2d->Instance->FGCOLR = tmp;
00952     }
00953   }
00954   /* Initialize the DMA2D state*/
00955   hdma2d->State  = HAL_DMA2D_STATE_READY;
00956
00957   /* Process unlocked */
00958   __HAL_UNLOCK(hdma2d);
00959
00960   return HAL_OK;
00961 }
00962
00963 /**
00964   * @brief  Configure the DMA2D CLUT Transfer.
00965   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
00966   *                   the configuration information for the DMA2D.
00967   * @param  CLUTCfg:  pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00968   *                   the configuration information for the color look up table.
00969   * @param  LayerIdx: DMA2D Layer index.
00970   *                   This parameter can be one of the following values:
00971   *                   0(background) / 1(foreground)
00972   * @retval HAL status
00973   */
00974 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
00975 {
00976   uint32_t tmp = 0, tmp1 = 0;
00977
00978   /* Check the parameters */
00979   assert_param(IS_DMA2D_LAYER(LayerIdx));
00980   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
00981   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
00982
00983   /* Configure the CLUT of the background DMA2D layer */
00984   if(LayerIdx == 0)
00985   {
00986     /* Get the BGCMAR register value */
00987     tmp = hdma2d->Instance->BGCMAR;
00988
00989     /* Clear CLUT address bits */
00990     tmp &= (uint32_t)~DMA2D_BGCMAR_MA;
00991
00992     /* Prepare the value to be wrote to the BGCMAR register */
00993     tmp |= (uint32_t)CLUTCfg.pCLUT;
00994
00995     /* Write to DMA2D BGCMAR register */
00996     hdma2d->Instance->BGCMAR = tmp;
00997
00998     /* Get the BGPFCCR register value */
00999     tmp = hdma2d->Instance->BGPFCCR;
01000
01001     /* Clear CLUT size and CLUT address bits */
01002     tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM);
01003
01004     /* Get the CLUT size */
01005     tmp1 = CLUTCfg.Size << 16;
01006
01007     /* Prepare the value to be wrote to the BGPFCCR register */
01008     tmp |= (CLUTCfg.CLUTColorMode | tmp1);
01009
01010     /* Write to DMA2D BGPFCCR register */
01011     hdma2d->Instance->BGPFCCR = tmp;
01012   }
01013   /* Configure the CLUT of the foreground DMA2D layer */
01014   else
01015   {
01016     /* Get the FGCMAR register value */
01017     tmp = hdma2d->Instance->FGCMAR;
01018
01019     /* Clear CLUT address bits */
01020     tmp &= (uint32_t)~DMA2D_FGCMAR_MA;
01021
01022     /* Prepare the value to be wrote to the FGCMAR register */
01023     tmp |= (uint32_t)CLUTCfg.pCLUT;
01024
01025     /* Write to DMA2D FGCMAR register */
01026     hdma2d->Instance->FGCMAR = tmp;
01027
01028     /* Get the FGPFCCR register value */
01029     tmp = hdma2d->Instance->FGPFCCR;
01030
01031     /* Clear CLUT size and CLUT address bits */
01032     tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM);
01033
01034     /* Get the CLUT size */
01035     tmp1 = CLUTCfg.Size << 8;
01036
01037     /* Prepare the value to be wrote to the FGPFCCR register */
01038     tmp |= (CLUTCfg.CLUTColorMode | tmp1);
01039
01040     /* Write to DMA2D FGPFCCR register */
01041     hdma2d->Instance->FGPFCCR = tmp;
01042   }
01043
01044   return HAL_OK;
01045 }
01046
01047 /**
01048   * @brief  Enable the DMA2D CLUT Transfer.
01049   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
01050   *                   the configuration information for the DMA2D.
01051   * @param  LayerIdx: DMA2D Layer index.
01052   *                   This parameter can be one of the following values:
01053   *                   0(background) / 1(foreground)
01054   * @retval HAL status
01055   */
01056 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01057 {
01058   /* Check the parameters */
01059   assert_param(IS_DMA2D_LAYER(LayerIdx));
01060
01061   if(LayerIdx == 0)
01062   {
01063     /* Enable the CLUT loading for the background */
01064     hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
01065   }
01066   else
01067   {
01068     /* Enable the CLUT loading for the foreground */
01069     hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
01070   }
01071
01072   return HAL_OK;
01073 }
01074
01075 /**
01076   * @brief  Disable the DMA2D CLUT Transfer.
01077   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
01078   *                   the configuration information for the DMA2D.
01079   * @param  LayerIdx: DMA2D Layer index.
01080   *                   This parameter can be one of the following values:
01081   *                   0(background) / 1(foreground)
01082   * @retval HAL status
01083   */
01084 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01085 {
01086   /* Check the parameters */
01087   assert_param(IS_DMA2D_LAYER(LayerIdx));
01088
01089   if(LayerIdx == 0)
01090   {
01091     /* Disable the CLUT loading for the background */
01092     hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;
01093   }
01094   else
01095   {
01096     /* Disable the CLUT loading for the foreground */
01097     hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;
01098   }
01099
01100   return HAL_OK;
01101 }
01102
01103 /**
01104   * @brief  Define the configuration of the line watermark .
01105   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01106   *                 the configuration information for the DMA2D.
01107   * @param  Line:   Line Watermark configuration.
01108   * @retval HAL status
01109   */
01110
01111 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
01112 {
01113   /* Process locked */
01114   __HAL_LOCK(hdma2d);
01115
01116   /* Change DMA2D peripheral state */
01117   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01118
01119   /* Check the parameters */
01120   assert_param(IS_DMA2D_LineWatermark(Line));
01121
01122   /* Sets the Line watermark configuration */
01123   DMA2D->LWR = (uint32_t)Line;
01124
01125   /* Initialize the DMA2D state*/
01126   hdma2d->State = HAL_DMA2D_STATE_READY;
01127
01128   /* Process unlocked */
01129   __HAL_UNLOCK(hdma2d);
01130
01131   return HAL_OK;
01132 }
01133
01134 /**
01135   * @}
01136   */
01137
01138 /** @defgroup DMA2D_Group4 Peripheral State functions
01139  *  @brief    Peripheral State functions
01140  *
01141 @verbatim
01142  ===============================================================================
01143                   ##### Peripheral State and Errors functions #####
01144  ===============================================================================
01145     [..]
01146     This subsection provides functions allowing to :
01147       (+) Check the DMA2D state
01148       (+) Get error code
01149
01150 @endverbatim
01151   * @{
01152   */
01153
01154 /**
01155   * @brief  Return the DMA2D state
01156   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01157   *                 the configuration information for the DMA2D.
01158   * @retval HAL state
01159   */
01160 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
01161 {
01162   return hdma2d->State;
01163 }
01164
01165 /**
01166   * @brief  Return the DMA2D error code
01167   * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
01168   *               the configuration information for DMA2D.
01169   * @retval DMA2D Error Code
01170   */
01171 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
01172 {
01173   return hdma2d->ErrorCode;
01174 }
01175
01176 /**
01177   * @}
01178   */
01179
01180
01181 /**
01182   * @brief  Set the DMA2D Transfer parameter.
01183   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
01184   *                     the configuration information for the specified DMA2D.
01185   * @param  pdata:      The source memory Buffer address
01186   * @param  DstAddress: The destination memory Buffer address
01187   * @param  Width:      The width of data to be transferred from source to destination.
01188   * @param  Height:     The height of data to be transferred from source to destination.
01189   * @retval HAL status
01190   */
01191 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
01192 {
01193   uint32_t tmp = 0;
01194   uint32_t tmp1 = 0;
01195   uint32_t tmp2 = 0;
01196   uint32_t tmp3 = 0;
01197   uint32_t tmp4 = 0;
01198
01199   tmp = Width << 16;
01200
01201   /* Configure DMA2D data size */
01202   hdma2d->Instance->NLR = (Height | tmp);
01203
01204   /* Configure DMA2D destination address */
01205   hdma2d->Instance->OMAR = DstAddress;
01206
01207   /* Register to memory DMA2D mode selected */
01208   if (hdma2d->Init.Mode == DMA2D_R2M)
01209   {
01210     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
01211     tmp2 = pdata & DMA2D_OCOLR_RED_1;
01212     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
01213     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
01214
01215     /* Prepare the value to be wrote to the OCOLR register according to the color mode */
01216     if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)
01217     {
01218       tmp = (tmp3 | tmp2 | tmp1| tmp4);
01219     }
01220     else if (hdma2d->Init.ColorMode == DMA2D_RGB888)
01221     {
01222       tmp = (tmp3 | tmp2 | tmp4);
01223     }
01224     else if (hdma2d->Init.ColorMode == DMA2D_RGB565)
01225     {
01226       tmp2 = (tmp2 >> 19);
01227       tmp3 = (tmp3 >> 10);
01228       tmp4 = (tmp4 >> 3 );
01229       tmp  = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
01230     }
01231     else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)
01232     {
01233       tmp1 = (tmp1 >> 31);
01234       tmp2 = (tmp2 >> 19);
01235       tmp3 = (tmp3 >> 11);
01236       tmp4 = (tmp4 >> 3 );
01237       tmp  = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
01238     }
01239     else /* DMA2D_CMode = DMA2D_ARGB4444 */
01240     {
01241       tmp1 = (tmp1 >> 28);
01242       tmp2 = (tmp2 >> 20);
01243       tmp3 = (tmp3 >> 12);
01244       tmp4 = (tmp4 >> 4 );
01245       tmp  = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
01246     }
01247     /* Write to DMA2D OCOLR register */
01248     hdma2d->Instance->OCOLR = tmp;
01249   }
01250   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
01251   {
01252     /* Configure DMA2D source address */
01253     hdma2d->Instance->FGMAR = pdata;
01254   }
01255 }
01256
01257 /**
01258   * @}
01259   */
01260 #endif /* HAL_DMA2D_MODULE_ENABLED */
01261 /**
01262   * @}
01263   */
01264
01265 /**
01266   * @}
01267   */
01268
01269 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma2d.h Source File

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stm32f7xx_hal_dma2d.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dma2d.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DMA2D HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DMA2D_H
00040 #define __STM32F7xx_HAL_DMA2D_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup DMA2D DMA2D
00054   * @brief DMA2D HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
00060   * @{
00061   */
00062 #define MAX_DMA2D_LAYER  2
00063
00064 /**
00065   * @brief DMA2D color Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t Blue;               /*!< Configures the blue value.
00070                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00071
00072   uint32_t Green;              /*!< Configures the green value.
00073                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00074
00075   uint32_t Red;                /*!< Configures the red value.
00076                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00077 } DMA2D_ColorTypeDef;
00078
00079 /**
00080   * @brief DMA2D CLUT Structure definition
00081   */
00082 typedef struct
00083 {
00084   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
00085
00086   uint32_t CLUTColorMode;           /*!< configures the DMA2D CLUT color mode.
00087                                          This parameter can be one value of @ref DMA2D_CLUT_CM */
00088
00089   uint32_t Size;                    /*!< configures the DMA2D CLUT size.
00090                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
00091 } DMA2D_CLUTCfgTypeDef;
00092
00093 /**
00094   * @brief DMA2D Init structure definition
00095   */
00096 typedef struct
00097 {
00098   uint32_t             Mode;               /*!< configures the DMA2D transfer mode.
00099                                                 This parameter can be one value of @ref DMA2D_Mode */
00100
00101   uint32_t             ColorMode;          /*!< configures the color format of the output image.
00102                                                 This parameter can be one value of @ref DMA2D_Color_Mode */
00103
00104   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
00105                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
00106 } DMA2D_InitTypeDef;
00107
00108 /**
00109   * @brief DMA2D Layer structure definition
00110   */
00111 typedef struct
00112 {
00113   uint32_t             InputOffset;       /*!< configures the DMA2D foreground offset.
00114                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
00115
00116   uint32_t             InputColorMode;    /*!< configures the DMA2D foreground color mode .
00117                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode */
00118
00119   uint32_t             AlphaMode;         /*!< configures the DMA2D foreground alpha mode.
00120                                                This parameter can be one value of @ref DMA2D_ALPHA_MODE */
00121
00122   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
00123                                                This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
00124                                                in case of A8 or A4 color mode (ARGB).
00125                                                Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
00126
00127 } DMA2D_LayerCfgTypeDef;
00128
00129 /**
00130   * @brief  HAL DMA2D State structures definition
00131   */
00132 typedef enum
00133 {
00134   HAL_DMA2D_STATE_RESET             = 0x00,    /*!< DMA2D not yet initialized or disabled       */
00135   HAL_DMA2D_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
00136   HAL_DMA2D_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing              */
00137   HAL_DMA2D_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
00138   HAL_DMA2D_STATE_ERROR             = 0x04,    /*!< DMA2D state error                           */
00139   HAL_DMA2D_STATE_SUSPEND           = 0x05     /*!< DMA2D process is suspended                  */
00140 }HAL_DMA2D_StateTypeDef;
00141
00142 /**
00143   * @brief  DMA2D handle Structure definition
00144   */
00145 typedef struct __DMA2D_HandleTypeDef
00146 {
00147   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D Register base address       */
00148
00149   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters    */
00150
00151   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback  */
00152
00153   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback     */
00154
00155   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */
00156
00157   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D Lock                        */
00158
00159   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state              */
00160
00161   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D Error code                  */
00162 } DMA2D_HandleTypeDef;
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported constants --------------------------------------------------------*/
00168 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
00169   * @{
00170   */
00171
00172 /** @defgroup DMA2D_Error_Code DMA2D Error Code
00173   * @{
00174   */
00175 #define HAL_DMA2D_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
00176 #define HAL_DMA2D_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
00177 #define HAL_DMA2D_ERROR_CE        ((uint32_t)0x00000002)    /*!< Configuration error  */
00178 #define HAL_DMA2D_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup DMA2D_Mode DMA2D Mode
00184   * @{
00185   */
00186 #define DMA2D_M2M                            ((uint32_t)0x00000000)             /*!< DMA2D memory to memory transfer mode */
00187 #define DMA2D_M2M_PFC                        ((uint32_t)0x00010000)             /*!< DMA2D memory to memory with pixel format conversion transfer mode */
00188 #define DMA2D_M2M_BLEND                      ((uint32_t)0x00020000)             /*!< DMA2D memory to memory with blending transfer mode */
00189 #define DMA2D_R2M                            ((uint32_t)0x00030000)             /*!< DMA2D register to memory transfer mode */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup DMA2D_Color_Mode DMA2D Color Mode
00195   * @{
00196   */
00197 #define DMA2D_ARGB8888                       ((uint32_t)0x00000000)             /*!< ARGB8888 DMA2D color mode */
00198 #define DMA2D_RGB888                         ((uint32_t)0x00000001)             /*!< RGB888 DMA2D color mode   */
00199 #define DMA2D_RGB565                         ((uint32_t)0x00000002)             /*!< RGB565 DMA2D color mode   */
00200 #define DMA2D_ARGB1555                       ((uint32_t)0x00000003)             /*!< ARGB1555 DMA2D color mode */
00201 #define DMA2D_ARGB4444                       ((uint32_t)0x00000004)             /*!< ARGB4444 DMA2D color mode */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
00207   * @{
00208   */
00209 #define COLOR_VALUE             ((uint32_t)0x000000FF)                          /*!< color value mask */
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup DMA2D_SIZE DMA2D SIZE
00215   * @{
00216   */
00217 #define DMA2D_PIXEL          (DMA2D_NLR_PL >> 16)                               /*!< DMA2D pixel per line */
00218 #define DMA2D_LINE           DMA2D_NLR_NL                                       /*!< DMA2D number of line */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup DMA2D_Offset DMA2D Offset
00224   * @{
00225   */
00226 #define DMA2D_OFFSET      DMA2D_FGOR_LO            /*!< Line Offset */
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
00232   * @{
00233   */
00234 #define CM_ARGB8888        ((uint32_t)0x00000000)                               /*!< ARGB8888 color mode */
00235 #define CM_RGB888          ((uint32_t)0x00000001)                               /*!< RGB888 color mode */
00236 #define CM_RGB565          ((uint32_t)0x00000002)                               /*!< RGB565 color mode */
00237 #define CM_ARGB1555        ((uint32_t)0x00000003)                               /*!< ARGB1555 color mode */
00238 #define CM_ARGB4444        ((uint32_t)0x00000004)                               /*!< ARGB4444 color mode */
00239 #define CM_L8              ((uint32_t)0x00000005)                               /*!< L8 color mode */
00240 #define CM_AL44            ((uint32_t)0x00000006)                               /*!< AL44 color mode */
00241 #define CM_AL88            ((uint32_t)0x00000007)                               /*!< AL88 color mode */
00242 #define CM_L4              ((uint32_t)0x00000008)                               /*!< L4 color mode */
00243 #define CM_A8              ((uint32_t)0x00000009)                               /*!< A8 color mode */
00244 #define CM_A4              ((uint32_t)0x0000000A)                               /*!< A4 color mode */
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
00250   * @{
00251   */
00252 #define DMA2D_NO_MODIF_ALPHA       ((uint32_t)0x00000000)  /*!< No modification of the alpha channel value */
00253 #define DMA2D_REPLACE_ALPHA        ((uint32_t)0x00000001)  /*!< Replace original alpha channel value by programmed alpha value */
00254 #define DMA2D_COMBINE_ALPHA        ((uint32_t)0x00000002)  /*!< Replace original alpha channel value by programmed alpha value
00255                                                                 with original alpha channel value                              */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
00261   * @{
00262   */
00263 #define DMA2D_CCM_ARGB8888    ((uint32_t)0x00000000)    /*!< ARGB8888 DMA2D C-LUT color mode */
00264 #define DMA2D_CCM_RGB888      ((uint32_t)0x00000001)    /*!< RGB888 DMA2D C-LUT color mode   */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup DMA2D_Size_Clut DMA2D Size Clut
00270   * @{
00271   */
00272 #define DMA2D_CLUT_SIZE    (DMA2D_FGPFCCR_CS >> 8)    /*!< DMA2D C-LUT size */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup DMA2D_DeadTime DMA2D DeadTime
00278   * @{
00279   */
00280 #define LINE_WATERMARK            DMA2D_LWR_LW
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
00286   * @{
00287   */
00288 #define DMA2D_IT_CE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
00289 #define DMA2D_IT_CTC            DMA2D_CR_CTCIE   /*!< C-LUT Transfer Complete Interrupt */
00290 #define DMA2D_IT_CAE            DMA2D_CR_CAEIE   /*!< C-LUT Access Error Interrupt */
00291 #define DMA2D_IT_TW             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
00292 #define DMA2D_IT_TC             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
00293 #define DMA2D_IT_TE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup DMA2D_Flag DMA2D Flag
00299   * @{
00300   */
00301 #define DMA2D_FLAG_CE          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
00302 #define DMA2D_FLAG_CTC         DMA2D_ISR_CTCIF    /*!< C-LUT Transfer Complete Interrupt Flag */
00303 #define DMA2D_FLAG_CAE         DMA2D_ISR_CAEIF    /*!< C-LUT Access Error Interrupt Flag */
00304 #define DMA2D_FLAG_TW          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
00305 #define DMA2D_FLAG_TC          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
00306 #define DMA2D_FLAG_TE          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314 /* Exported macro ------------------------------------------------------------*/
00315 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
00316   * @{
00317   */
00318
00319 /** @brief Reset DMA2D handle state
00320   * @param  __HANDLE__: specifies the DMA2D handle.
00321   * @retval None
00322   */
00323 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
00324
00325 /**
00326   * @brief  Enable the DMA2D.
00327   * @param  __HANDLE__: DMA2D handle
00328   * @retval None.
00329   */
00330 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
00331
00332 /**
00333   * @brief  Disable the DMA2D.
00334   * @param  __HANDLE__: DMA2D handle
00335   * @retval None.
00336   */
00337 #define __HAL_DMA2D_DISABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
00338
00339 /* Interrupt & Flag management */
00340 /**
00341   * @brief  Get the DMA2D pending flags.
00342   * @param  __HANDLE__: DMA2D handle
00343   * @param  __FLAG__: Get the specified flag.
00344   *          This parameter can be any combination of the following values:
00345   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00346   *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
00347   *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
00348   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00349   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00350   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00351   * @retval The state of FLAG.
00352   */
00353 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00354
00355 /**
00356   * @brief  Clears the DMA2D pending flags.
00357   * @param  __HANDLE__: DMA2D handle
00358   * @param  __FLAG__: specifies the flag to clear.
00359   *          This parameter can be any combination of the following values:
00360   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00361   *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
00362   *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
00363   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00364   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00365   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00366   * @retval None
00367   */
00368 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
00369
00370 /**
00371   * @brief  Enables the specified DMA2D interrupts.
00372   * @param  __HANDLE__: DMA2D handle
00373   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
00374   *          This parameter can be any combination of the following values:
00375   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00376   *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
00377   *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
00378   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00379   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00380   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00381   * @retval None
00382   */
00383 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00384
00385 /**
00386   * @brief  Disables the specified DMA2D interrupts.
00387   * @param  __HANDLE__: DMA2D handle
00388   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
00389   *          This parameter can be any combination of the following values:
00390   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00391   *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
00392   *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
00393   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00394   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00395   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00396   * @retval None
00397   */
00398 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00399
00400 /**
00401   * @brief  Checks whether the specified DMA2D interrupt has occurred or not.
00402   * @param  __HANDLE__: DMA2D handle
00403   * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
00404   *          This parameter can be one of the following values:
00405   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00406   *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
00407   *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
00408   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00409   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00410   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00411   * @retval The state of INTERRUPT.
00412   */
00413 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00414 /**
00415   * @}
00416   */
00417
00418 /* Exported functions --------------------------------------------------------*/
00419 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
00420   * @{
00421   */
00422 /* Initialization and de-initialization functions *******************************/
00423 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
00424 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
00425 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
00426 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
00427
00428 /* IO operation functions *******************************************************/
00429 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00430 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
00431 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00432 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00433 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
00434 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
00435 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
00436 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
00437 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
00438
00439 /* Peripheral Control functions *************************************************/
00440 HAL_StatusTypeDef  HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00441 HAL_StatusTypeDef  HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00442 HAL_StatusTypeDef  HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00443 HAL_StatusTypeDef  HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00444 HAL_StatusTypeDef  HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
00445
00446 /* Peripheral State functions ***************************************************/
00447 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
00448 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
00449 /**
00450   * @}
00451   */
00452
00453 /* Private types -------------------------------------------------------------*/
00454 /** @defgroup DMA2D_Private_Types DMA2D Private Types
00455   * @{
00456   */
00457
00458 /**
00459   * @}
00460   */
00461
00462 /* Private defines -------------------------------------------------------------*/
00463 /** @defgroup DMA2D_Private_Defines DMA2D Private Defines
00464   * @{
00465   */
00466
00467 /**
00468   * @}
00469   */
00470
00471 /* Private variables ---------------------------------------------------------*/
00472 /** @defgroup DMA2D_Private_Variables DMA2D Private Variables
00473   * @{
00474   */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /* Private constants ---------------------------------------------------------*/
00481 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
00482   * @{
00483   */
00484
00485 /**
00486   * @}
00487   */
00488
00489 /* Private macros ------------------------------------------------------------*/
00490 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
00491   * @{
00492   */
00493 #define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= MAX_DMA2D_LAYER)
00494 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
00495                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
00496 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888)   || \
00497                                                ((MODE_ARGB) == DMA2D_RGB565)   || ((MODE_ARGB) == DMA2D_ARGB1555) || \
00498                                                ((MODE_ARGB) == DMA2D_ARGB4444))
00499 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= COLOR_VALUE)
00500 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
00501 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
00502 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
00503 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888)   || \
00504                                                ((INPUT_CM) == CM_RGB565)   || ((INPUT_CM) == CM_ARGB1555) || \
00505                                                ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8)       || \
00506                                                ((INPUT_CM) == CM_AL44)     || ((INPUT_CM) == CM_AL88)     || \
00507                                                ((INPUT_CM) == CM_L4)       || ((INPUT_CM) == CM_A8)       || \
00508                                                ((INPUT_CM) == CM_A4))
00509 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
00510                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
00511                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
00512 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
00513 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
00514 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
00515 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
00516                                                ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
00517                                                ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
00518 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
00519                                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
00520                                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
00521 /**
00522   * @}
00523   */
00524
00525 /* Private functions prototypes ---------------------------------------------------------*/
00526 /** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
00527   * @{
00528   */
00529
00530 /**
00531   * @}
00532   */
00533
00534 /* Private functions ---------------------------------------------------------*/
00535 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
00536   * @{
00537   */
00538
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546
00547 /**
00548   * @}
00549   */
00550
00551
00552 #ifdef __cplusplus
00553 }
00554 #endif
00555
00556 #endif /* __STM32F7xx_HAL_DMA2D_H */
00557
00558
00559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma.c Source File

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stm32f7xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   DMA HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the Direct Memory Access (DMA) peripheral:
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and errors functions
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019    (#) Enable and configure the peripheral to be connected to the DMA Stream
00020        (except for internal SRAM/FLASH memories: no initialization is
00021        necessary) please refer to Reference manual for connection between peripherals
00022        and DMA requests .
00023
00024    (#) For a given Stream, program the required configuration through the following parameters:
00025        Transfer Direction, Source and Destination data formats,
00026        Circular, Normal or peripheral flow control mode, Stream Priority level,
00027        Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
00028        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
00029
00030      *** Polling mode IO operation ***
00031      =================================
00032     [..]
00033           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00034               address and destination address and the Length of data to be transferred
00035           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00036               case a fixed Timeout can be configured by User depending from his application.
00037
00038      *** Interrupt mode IO operation ***
00039      ===================================
00040     [..]
00041           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00042           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00043           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00044               Source address and destination address and the Length of data to be transferred. In this
00045               case the DMA interrupt is configured
00046           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00047           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00048               add his own function by customization of function pointer XferCpltCallback and
00049               XferErrorCallback (i.e a member of DMA handle structure).
00050     [..]
00051      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00052          detection.
00053
00054      (#) Use HAL_DMA_Abort() function to abort the current transfer
00055
00056      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00057
00058      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
00059            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
00060            Half-Word data size for the peripheral to access its data register and set Word data size
00061            for the Memory to gain in access time. Each two half words will be packed and written in
00062            a single access to a Word in the Memory).
00063
00064      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
00065            and Destination. In this case the Peripheral Data Size will be applied to both Source
00066            and Destination.
00067
00068      *** DMA HAL driver macros list ***
00069      =============================================
00070      [..]
00071        Below the list of most used macros in DMA HAL driver.
00072
00073       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
00074       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
00075       (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
00076       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
00077       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
00078       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
00079
00080      [..]
00081       (@) You can refer to the DMA HAL driver header file for more useful macros
00082
00083   @endverbatim
00084   ******************************************************************************
00085   * @attention
00086   *
00087   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00088   *
00089   * Redistribution and use in source and binary forms, with or without modification,
00090   * are permitted provided that the following conditions are met:
00091   *   1. Redistributions of source code must retain the above copyright notice,
00092   *      this list of conditions and the following disclaimer.
00093   *   2. Redistributions in binary form must reproduce the above copyright notice,
00094   *      this list of conditions and the following disclaimer in the documentation
00095   *      and/or other materials provided with the distribution.
00096   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00097   *      may be used to endorse or promote products derived from this software
00098   *      without specific prior written permission.
00099   *
00100   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00101   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00102   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00103   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00104   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00105   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00106   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00107   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00108   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00109   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00110   *
00111   ******************************************************************************
00112   */
00113
00114 /* Includes ------------------------------------------------------------------*/
00115 #include "stm32f7xx_hal.h"
00116
00117 /** @addtogroup STM32F7xx_HAL_Driver
00118   * @{
00119   */
00120
00121 /** @defgroup DMA DMA
00122   * @brief DMA HAL module driver
00123   * @{
00124   */
00125
00126 #ifdef HAL_DMA_MODULE_ENABLED
00127
00128 /* Private types -------------------------------------------------------------*/
00129 typedef struct
00130 {
00131   __IO uint32_t ISR;   /*!< DMA interrupt status register */
00132   __IO uint32_t Reserved0;
00133   __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
00134 } DMA_Base_Registers;
00135
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private constants ---------------------------------------------------------*/
00138 /** @addtogroup DMA_Private_Constants
00139  * @{
00140  */
00141  #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000)  /* 1s */
00142 /**
00143   * @}
00144   */
00145 /* Private macros ------------------------------------------------------------*/
00146 /* Private functions ---------------------------------------------------------*/
00147 /** @addtogroup DMA_Private_Functions
00148   * @{
00149   */
00150 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00151 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
00152
00153 /**
00154   * @brief  Sets the DMA Transfer parameter.
00155   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00156   *                     the configuration information for the specified DMA Stream.
00157   * @param  SrcAddress: The source memory Buffer address
00158   * @param  DstAddress: The destination memory Buffer address
00159   * @param  DataLength: The length of data to be transferred from source to destination
00160   * @retval HAL status
00161   */
00162 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00163 {
00164   /* Clear DBM bit */
00165   hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
00166
00167   /* Configure DMA Stream data length */
00168   hdma->Instance->NDTR = DataLength;
00169
00170   /* Peripheral to Memory */
00171   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00172   {
00173     /* Configure DMA Stream destination address */
00174     hdma->Instance->PAR = DstAddress;
00175
00176     /* Configure DMA Stream source address */
00177     hdma->Instance->M0AR = SrcAddress;
00178   }
00179   /* Memory to Peripheral */
00180   else
00181   {
00182     /* Configure DMA Stream source address */
00183     hdma->Instance->PAR = SrcAddress;
00184
00185     /* Configure DMA Stream destination address */
00186     hdma->Instance->M0AR = DstAddress;
00187   }
00188 }
00189
00190 /**
00191   * @}
00192   */
00193
00194 /* Exported functions ---------------------------------------------------------*/
00195 /** @addtogroup DMA_Exported_Functions
00196   * @{
00197   */
00198
00199 /** @addtogroup DMA_Exported_Functions_Group1
00200   *
00201 @verbatim
00202  ===============================================================================
00203              ##### Initialization and de-initialization functions  #####
00204  ===============================================================================
00205     [..]
00206     This section provides functions allowing to initialize the DMA Stream source
00207     and destination addresses, incrementation and data sizes, transfer direction,
00208     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
00209     [..]
00210     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00211     reference manual.
00212
00213 @endverbatim
00214   * @{
00215   */
00216
00217 /**
00218   * @brief  Initializes the DMA according to the specified
00219   *         parameters in the DMA_InitTypeDef and create the associated handle.
00220   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
00221   *               the configuration information for the specified DMA Stream.
00222   * @retval HAL status
00223   */
00224 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00225 {
00226   uint32_t tmp = 0;
00227
00228   /* Check the DMA peripheral state */
00229   if(hdma == NULL)
00230   {
00231     return HAL_ERROR;
00232   }
00233
00234   /* Check the parameters */
00235   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00236   assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
00237   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00238   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00239   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00240   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00241   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00242   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00243   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00244   assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
00245   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
00246      when FIFO mode is enabled */
00247   if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
00248   {
00249     assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
00250     assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
00251     assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
00252   }
00253
00254   /* Change DMA peripheral state */
00255   hdma->State = HAL_DMA_STATE_BUSY;
00256
00257   /* Get the CR register value */
00258   tmp = hdma->Instance->CR;
00259
00260   /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
00261   tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
00262                       DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
00263                       DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
00264                       DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
00265
00266   /* Prepare the DMA Stream configuration */
00267   tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
00268           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00269           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00270           hdma->Init.Mode                | hdma->Init.Priority;
00271
00272   /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
00273   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00274   {
00275     /* Get memory burst and peripheral burst */
00276     tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
00277   }
00278
00279   /* Write to DMA Stream CR register */
00280   hdma->Instance->CR = tmp;
00281
00282   /* Get the FCR register value */
00283   tmp = hdma->Instance->FCR;
00284
00285   /* Clear Direct mode and FIFO threshold bits */
00286   tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
00287
00288   /* Prepare the DMA Stream FIFO configuration */
00289   tmp |= hdma->Init.FIFOMode;
00290
00291   /* the FIFO threshold is not used when the FIFO mode is disabled */
00292   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00293   {
00294     /* Get the FIFO threshold */
00295     tmp |= hdma->Init.FIFOThreshold;
00296   }
00297
00298   /* Write to DMA Stream FCR */
00299   hdma->Instance->FCR = tmp;
00300
00301   /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
00302      DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
00303   DMA_CalcBaseAndBitshift(hdma);
00304
00305   /* Initialize the error code */
00306   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00307
00308   /* Initialize the DMA state */
00309   hdma->State = HAL_DMA_STATE_READY;
00310
00311   return HAL_OK;
00312 }
00313
00314 /**
00315   * @brief  DeInitializes the DMA peripheral
00316   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00317   *               the configuration information for the specified DMA Stream.
00318   * @retval HAL status
00319   */
00320 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00321 {
00322         DMA_Base_Registers *regs;
00323
00324   /* Check the DMA peripheral state */
00325   if(hdma == NULL)
00326   {
00327     return HAL_ERROR;
00328   }
00329
00330   /* Check the DMA peripheral state */
00331   if(hdma->State == HAL_DMA_STATE_BUSY)
00332   {
00333      return HAL_ERROR;
00334   }
00335
00336   /* Disable the selected DMA Streamx */
00337   __HAL_DMA_DISABLE(hdma);
00338
00339   /* Reset DMA Streamx control register */
00340   hdma->Instance->CR   = 0;
00341
00342   /* Reset DMA Streamx number of data to transfer register */
00343   hdma->Instance->NDTR = 0;
00344
00345   /* Reset DMA Streamx peripheral address register */
00346   hdma->Instance->PAR  = 0;
00347
00348   /* Reset DMA Streamx memory 0 address register */
00349   hdma->Instance->M0AR = 0;
00350
00351   /* Reset DMA Streamx memory 1 address register */
00352   hdma->Instance->M1AR = 0;
00353
00354   /* Reset DMA Streamx FIFO control register */
00355   hdma->Instance->FCR  = (uint32_t)0x00000021;
00356
00357   /* Get DMA steam Base Address */
00358   regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00359
00360   /* Clear all interrupt flags at correct offset within the register */
00361   regs->IFCR = 0x3F << hdma->StreamIndex;
00362
00363   /* Initialize the error code */
00364   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00365
00366   /* Initialize the DMA state */
00367   hdma->State = HAL_DMA_STATE_RESET;
00368
00369   /* Release Lock */
00370   __HAL_UNLOCK(hdma);
00371
00372   return HAL_OK;
00373 }
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @addtogroup DMA_Exported_Functions_Group2
00380   *
00381 @verbatim
00382  ===============================================================================
00383                       #####  IO operation functions  #####
00384  ===============================================================================
00385     [..]  This section provides functions allowing to:
00386       (+) Configure the source, destination address and data length and Start DMA transfer
00387       (+) Configure the source, destination address and data length and
00388           Start DMA transfer with interrupt
00389       (+) Abort DMA transfer
00390       (+) Poll for transfer complete
00391       (+) Handle DMA interrupt request
00392
00393 @endverbatim
00394   * @{
00395   */
00396
00397 /**
00398   * @brief  Starts the DMA Transfer.
00399   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00400   *                     the configuration information for the specified DMA Stream.
00401   * @param  SrcAddress: The source memory Buffer address
00402   * @param  DstAddress: The destination memory Buffer address
00403   * @param  DataLength: The length of data to be transferred from source to destination
00404   * @retval HAL status
00405   */
00406 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00407 {
00408   /* Process locked */
00409   __HAL_LOCK(hdma);
00410
00411   /* Change DMA peripheral state */
00412   hdma->State = HAL_DMA_STATE_BUSY;
00413
00414    /* Check the parameters */
00415   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00416
00417   /* Disable the peripheral */
00418   __HAL_DMA_DISABLE(hdma);
00419
00420   /* Configure the source, destination address and the data length */
00421   DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00422
00423   /* Enable the Peripheral */
00424   __HAL_DMA_ENABLE(hdma);
00425
00426   return HAL_OK;
00427 }
00428
00429 /**
00430   * @brief  Start the DMA Transfer with interrupt enabled.
00431   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00432   *                     the configuration information for the specified DMA Stream.
00433   * @param  SrcAddress: The source memory Buffer address
00434   * @param  DstAddress: The destination memory Buffer address
00435   * @param  DataLength: The length of data to be transferred from source to destination
00436   * @retval HAL status
00437   */
00438 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00439 {
00440   /* Process locked */
00441   __HAL_LOCK(hdma);
00442
00443   /* Change DMA peripheral state */
00444   hdma->State = HAL_DMA_STATE_BUSY;
00445
00446    /* Check the parameters */
00447   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00448
00449   /* Disable the peripheral */
00450   __HAL_DMA_DISABLE(hdma);
00451
00452   /* Configure the source, destination address and the data length */
00453   DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00454
00455   /* Enable all interrupts */
00456   hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
00457   hdma->Instance->FCR |= DMA_IT_FE;
00458
00459    /* Enable the Peripheral */
00460   __HAL_DMA_ENABLE(hdma);
00461
00462   return HAL_OK;
00463 }
00464
00465 /**
00466   * @brief  Aborts the DMA Transfer.
00467   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00468   *                 the configuration information for the specified DMA Stream.
00469   *
00470   * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
00471   *        effectively disabled is added. If a Stream is disabled
00472   *        while a data transfer is ongoing, the current data will be transferred
00473   *        and the Stream will be effectively disabled only after the transfer of
00474   *        this single data is finished.
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00478 {
00479   uint32_t tickstart = 0;
00480
00481   /* Disable the stream */
00482   __HAL_DMA_DISABLE(hdma);
00483
00484   /* Get tick */
00485   tickstart = HAL_GetTick();
00486
00487   /* Check if the DMA Stream is effectively disabled */
00488   while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
00489   {
00490     /* Check for the Timeout */
00491     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
00492     {
00493       /* Update error code */
00494       hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
00495
00496       /* Process Unlocked */
00497       __HAL_UNLOCK(hdma);
00498
00499       /* Change the DMA state */
00500       hdma->State = HAL_DMA_STATE_TIMEOUT;
00501
00502       return HAL_TIMEOUT;
00503     }
00504   }
00505   /* Process Unlocked */
00506   __HAL_UNLOCK(hdma);
00507
00508   /* Change the DMA state*/
00509   hdma->State = HAL_DMA_STATE_READY;
00510
00511   return HAL_OK;
00512 }
00513
00514 /**
00515   * @brief  Polling for transfer complete.
00516   * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
00517   *                        the configuration information for the specified DMA Stream.
00518   * @param  CompleteLevel: Specifies the DMA level complete.
00519   * @param  Timeout:       Timeout duration.
00520   * @retval HAL status
00521   */
00522 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
00523 {
00524   uint32_t temp, tmp, tmp1, tmp2;
00525   uint32_t tickstart = 0;
00526
00527   /* calculate DMA base and stream number */
00528   DMA_Base_Registers *regs;
00529
00530   regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
00531
00532   /* Get the level transfer complete flag */
00533   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00534   {
00535     /* Transfer Complete flag */
00536                 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00537   }
00538   else
00539   {
00540     /* Half Transfer Complete flag */
00541                 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00542   }
00543
00544   /* Get tick */
00545   tickstart = HAL_GetTick();
00546
00547   while((regs->ISR & temp) == RESET)
00548   {
00549     tmp  = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
00550     tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
00551     tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
00552     if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
00553     {
00554       if(tmp != RESET)
00555       {
00556         /* Update error code */
00557         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
00558
00559         /* Clear the transfer error flag */
00560         regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
00561       }
00562       if(tmp1 != RESET)
00563       {
00564         /* Update error code */
00565         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
00566
00567         /* Clear the FIFO error flag */
00568         regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
00569       }
00570       if(tmp2 != RESET)
00571       {
00572         /* Update error code */
00573         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
00574
00575         /* Clear the Direct Mode error flag */
00576         regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
00577       }
00578       /* Change the DMA state */
00579       hdma->State= HAL_DMA_STATE_ERROR;
00580
00581       /* Process Unlocked */
00582       __HAL_UNLOCK(hdma);
00583
00584       return HAL_ERROR;
00585     }
00586     /* Check for the Timeout */
00587     if(Timeout != HAL_MAX_DELAY)
00588     {
00589       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00590       {
00591         /* Update error code */
00592         hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
00593
00594         /* Change the DMA state */
00595         hdma->State = HAL_DMA_STATE_TIMEOUT;
00596
00597         /* Process Unlocked */
00598         __HAL_UNLOCK(hdma);
00599
00600         return HAL_TIMEOUT;
00601       }
00602     }
00603   }
00604
00605   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00606   {
00607     /* Clear the half transfer and transfer complete flags */
00608     regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
00609
00610     /* Multi_Buffering mode enabled */
00611     if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
00612     {
00613       /* Current memory buffer used is Memory 0 */
00614       if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
00615       {
00616         /* Change DMA peripheral state */
00617         hdma->State = HAL_DMA_STATE_READY_MEM0;
00618       }
00619       /* Current memory buffer used is Memory 1 */
00620       else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
00621       {
00622         /* Change DMA peripheral state */
00623         hdma->State = HAL_DMA_STATE_READY_MEM1;
00624       }
00625     }
00626     else
00627     {
00628       /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
00629          are complete) */
00630       hdma->State = HAL_DMA_STATE_READY_MEM0;
00631     }
00632     /* Process Unlocked */
00633     __HAL_UNLOCK(hdma);
00634   }
00635   else
00636   {
00637     /* Clear the half transfer complete flag */
00638     regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00639
00640     /* Multi_Buffering mode enabled */
00641     if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
00642     {
00643       /* Current memory buffer used is Memory 0 */
00644       if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
00645       {
00646         /* Change DMA peripheral state */
00647         hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00648       }
00649       /* Current memory buffer used is Memory 1 */
00650       else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
00651       {
00652         /* Change DMA peripheral state */
00653         hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
00654       }
00655     }
00656     else
00657     {
00658       /* Change DMA peripheral state */
00659       hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00660     }
00661   }
00662   return HAL_OK;
00663 }
00664
00665 /**
00666   * @brief  Handles DMA interrupt request.
00667   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00668   *               the configuration information for the specified DMA Stream.
00669   * @retval None
00670   */
00671 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00672 {
00673   /* calculate DMA base and stream number */
00674   DMA_Base_Registers *regs;
00675
00676   regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
00677
00678   /* Transfer Error Interrupt management ***************************************/
00679   if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
00680   {
00681     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
00682     {
00683       /* Disable the transfer error interrupt */
00684       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
00685
00686       /* Clear the transfer error flag */
00687       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
00688
00689       /* Update error code */
00690       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
00691
00692       /* Change the DMA state */
00693       hdma->State = HAL_DMA_STATE_ERROR;
00694
00695       /* Process Unlocked */
00696       __HAL_UNLOCK(hdma);
00697
00698       if(hdma->XferErrorCallback != NULL)
00699       {
00700         /* Transfer error callback */
00701         hdma->XferErrorCallback(hdma);
00702       }
00703     }
00704   }
00705   /* FIFO Error Interrupt management ******************************************/
00706   if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
00707   {
00708     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
00709     {
00710       /* Disable the FIFO Error interrupt */
00711       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
00712
00713       /* Clear the FIFO error flag */
00714       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
00715
00716       /* Update error code */
00717       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
00718
00719       /* Change the DMA state */
00720       hdma->State = HAL_DMA_STATE_ERROR;
00721
00722       /* Process Unlocked */
00723       __HAL_UNLOCK(hdma);
00724
00725       if(hdma->XferErrorCallback != NULL)
00726       {
00727         /* Transfer error callback */
00728         hdma->XferErrorCallback(hdma);
00729       }
00730     }
00731   }
00732   /* Direct Mode Error Interrupt management ***********************************/
00733   if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
00734   {
00735     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
00736     {
00737       /* Disable the direct mode Error interrupt */
00738       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
00739
00740       /* Clear the direct mode error flag */
00741       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
00742
00743       /* Update error code */
00744       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
00745
00746       /* Change the DMA state */
00747       hdma->State = HAL_DMA_STATE_ERROR;
00748
00749       /* Process Unlocked */
00750       __HAL_UNLOCK(hdma);
00751
00752       if(hdma->XferErrorCallback != NULL)
00753       {
00754         /* Transfer error callback */
00755         hdma->XferErrorCallback(hdma);
00756       }
00757     }
00758   }
00759   /* Half Transfer Complete Interrupt management ******************************/
00760   if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
00761   {
00762     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
00763     {
00764       /* Multi_Buffering mode enabled */
00765       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
00766       {
00767         /* Clear the half transfer complete flag */
00768         regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00769
00770         /* Current memory buffer used is Memory 0 */
00771         if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
00772         {
00773           /* Change DMA peripheral state */
00774           hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00775         }
00776         /* Current memory buffer used is Memory 1 */
00777         else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
00778         {
00779           /* Change DMA peripheral state */
00780           hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
00781         }
00782       }
00783       else
00784       {
00785         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00786         if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
00787         {
00788           /* Disable the half transfer interrupt */
00789           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00790         }
00791         /* Clear the half transfer complete flag */
00792         regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00793
00794         /* Change DMA peripheral state */
00795         hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00796       }
00797
00798       if(hdma->XferHalfCpltCallback != NULL)
00799       {
00800         /* Half transfer callback */
00801         hdma->XferHalfCpltCallback(hdma);
00802       }
00803     }
00804   }
00805   /* Transfer Complete Interrupt management ***********************************/
00806   if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
00807   {
00808     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
00809     {
00810       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
00811       {
00812         /* Clear the transfer complete flag */
00813         regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00814
00815         /* Current memory buffer used is Memory 1 */
00816         if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
00817         {
00818           if(hdma->XferM1CpltCallback != NULL)
00819           {
00820             /* Transfer complete Callback for memory1 */
00821             hdma->XferM1CpltCallback(hdma);
00822           }
00823         }
00824         /* Current memory buffer used is Memory 0 */
00825         else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
00826         {
00827           if(hdma->XferCpltCallback != NULL)
00828           {
00829             /* Transfer complete Callback for memory0 */
00830             hdma->XferCpltCallback(hdma);
00831           }
00832         }
00833       }
00834       /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
00835       else
00836       {
00837         if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
00838         {
00839           /* Disable the transfer complete interrupt */
00840           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
00841         }
00842         /* Clear the transfer complete flag */
00843         regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00844
00845         /* Update error code */
00846         hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
00847
00848         /* Change the DMA state */
00849         hdma->State = HAL_DMA_STATE_READY_MEM0;
00850
00851         /* Process Unlocked */
00852         __HAL_UNLOCK(hdma);
00853
00854         if(hdma->XferCpltCallback != NULL)
00855         {
00856           /* Transfer complete callback */
00857           hdma->XferCpltCallback(hdma);
00858         }
00859       }
00860     }
00861   }
00862 }
00863
00864
00865 /**
00866   * @}
00867   */
00868
00869 /** @addtogroup DMA_Exported_Functions_Group3
00870   *
00871 @verbatim
00872  ===============================================================================
00873                     ##### State and Errors functions #####
00874  ===============================================================================
00875     [..]
00876     This subsection provides functions allowing to
00877       (+) Check the DMA state
00878       (+) Get error code
00879
00880 @endverbatim
00881   * @{
00882   */
00883
00884 /**
00885   * @brief  Returns the DMA state.
00886   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00887   *               the configuration information for the specified DMA Stream.
00888   * @retval HAL state
00889   */
00890 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00891 {
00892   return hdma->State;
00893 }
00894
00895 /**
00896   * @brief  Return the DMA error code
00897   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
00898   *              the configuration information for the specified DMA Stream.
00899   * @retval DMA Error Code
00900   */
00901 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00902 {
00903   return hdma->ErrorCode;
00904 }
00905
00906 /**
00907   * @}
00908   */
00909
00910 /**
00911   * @brief  Returns the DMA Stream base address depending on stream number
00912   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00913   *                     the configuration information for the specified DMA Stream.
00914   * @retval Stream base address
00915   */
00916 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
00917 {
00918   uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
00919
00920   /* lookup table for necessary bitshift of flags within status registers */
00921   static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
00922   hdma->StreamIndex = flagBitshiftOffset[stream_number];
00923
00924   if (stream_number > 3)
00925   {
00926     /* return pointer to HISR and HIFCR */
00927     hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
00928   }
00929   else
00930   {
00931     /* return pointer to LISR and LIFCR */
00932     hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
00933   }
00934
00935   return hdma->StreamBaseAddress;
00936 }
00937 /**
00938   * @}
00939   */
00940
00941 #endif /* HAL_DMA_MODULE_ENABLED */
00942 /**
00943   * @}
00944   */
00945
00946 /**
00947   * @}
00948   */
00949
00950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma.h Source File

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stm32f7xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DMA_H
00040 #define __STM32F7xx_HAL_DMA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @brief    DMA Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  DMA Configuration Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
00070                                       This parameter can be a value of @ref DMA_Channel_selection                    */
00071
00072   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
00073                                       from memory to memory or from peripheral to memory.
00074                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
00075
00076   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
00077                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
00078
00079   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
00080                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
00081
00082   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
00083                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
00084
00085   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
00086                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
00087
00088   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
00089                                       This parameter can be a value of @ref DMA_mode
00090                                       @note The circular buffer mode cannot be used if the memory-to-memory
00091                                             data transfer is configured on the selected Stream                        */
00092
00093   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
00094                                       This parameter can be a value of @ref DMA_Priority_level                       */
00095
00096   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
00097                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
00098                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
00099                                             memory-to-memory data transfer is configured on the selected stream       */
00100
00101   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
00102                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
00103
00104   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
00105                                       It specifies the amount of data to be transferred in a single non interruptible
00106                                       transaction.
00107                                       This parameter can be a value of @ref DMA_Memory_burst
00108                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00109
00110   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
00111                                       It specifies the amount of data to be transferred in a single non interruptible
00112                                       transaction.
00113                                       This parameter can be a value of @ref DMA_Peripheral_burst
00114                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00115 }DMA_InitTypeDef;
00116
00117 /**
00118   * @brief  HAL DMA State structures definition
00119   */
00120 typedef enum
00121 {
00122   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
00123   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
00124   HAL_DMA_STATE_READY_MEM0        = 0x11,  /*!< DMA Mem0 process success            */
00125   HAL_DMA_STATE_READY_MEM1        = 0x21,  /*!< DMA Mem1 process success            */
00126   HAL_DMA_STATE_READY_HALF_MEM0   = 0x31,  /*!< DMA Mem0 Half process success       */
00127   HAL_DMA_STATE_READY_HALF_MEM1   = 0x41,  /*!< DMA Mem1 Half process success       */
00128   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
00129   HAL_DMA_STATE_BUSY_MEM0         = 0x12,  /*!< DMA Mem0 process is ongoing         */
00130   HAL_DMA_STATE_BUSY_MEM1         = 0x22,  /*!< DMA Mem1 process is ongoing         */
00131   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
00132   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
00133 }HAL_DMA_StateTypeDef;
00134
00135 /**
00136   * @brief  HAL DMA Error Code structure definition
00137   */
00138 typedef enum
00139 {
00140   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
00141   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
00142 }HAL_DMA_LevelCompleteTypeDef;
00143
00144 /**
00145   * @brief  DMA handle Structure definition
00146   */
00147 typedef struct __DMA_HandleTypeDef
00148 {
00149   DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
00150
00151   DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */
00152
00153   HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */
00154
00155   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
00156
00157   void                       *Parent;                                                      /*!< Parent object state                    */
00158
00159   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
00160
00161   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
00162
00163   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
00164
00165   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
00166
00167  __IO uint32_t              ErrorCode;                                                    /*!< DMA Error code                          */
00168
00169  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
00170
00171  uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
00172
00173 }DMA_HandleTypeDef;
00174
00175 /**
00176   * @}
00177   */
00178
00179
00180 /* Exported constants --------------------------------------------------------*/
00181
00182 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00183   * @brief    DMA Exported constants
00184   * @{
00185   */
00186
00187 /** @defgroup DMA_Error_Code DMA Error Code
00188   * @brief    DMA Error Code
00189   * @{
00190   */
00191 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
00192 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
00193 #define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002)    /*!< FIFO error           */
00194 #define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004)    /*!< Direct Mode error    */
00195 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup DMA_Channel_selection DMA Channel selection
00201   * @brief    DMA channel selection
00202   * @{
00203   */
00204 #define DMA_CHANNEL_0        ((uint32_t)0x00000000)  /*!< DMA Channel 0 */
00205 #define DMA_CHANNEL_1        ((uint32_t)0x02000000)  /*!< DMA Channel 1 */
00206 #define DMA_CHANNEL_2        ((uint32_t)0x04000000)  /*!< DMA Channel 2 */
00207 #define DMA_CHANNEL_3        ((uint32_t)0x06000000)  /*!< DMA Channel 3 */
00208 #define DMA_CHANNEL_4        ((uint32_t)0x08000000)  /*!< DMA Channel 4 */
00209 #define DMA_CHANNEL_5        ((uint32_t)0x0A000000)  /*!< DMA Channel 5 */
00210 #define DMA_CHANNEL_6        ((uint32_t)0x0C000000)  /*!< DMA Channel 6 */
00211 #define DMA_CHANNEL_7        ((uint32_t)0x0E000000)  /*!< DMA Channel 7 */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00217   * @brief    DMA data transfer direction
00218   * @{
00219   */
00220 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
00221 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
00222 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00228   * @brief    DMA peripheral incremented mode
00229   * @{
00230   */
00231 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
00232 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode disable */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00238   * @brief    DMA memory incremented mode
00239   * @{
00240   */
00241 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
00242 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode disable */
00243 /**
00244   * @}
00245   */
00246
00247
00248 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00249   * @brief    DMA peripheral data size
00250   * @{
00251   */
00252 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
00253 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
00254 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
00255 /**
00256   * @}
00257   */
00258
00259
00260 /** @defgroup DMA_Memory_data_size DMA Memory data size
00261   * @brief    DMA memory data size
00262   * @{
00263   */
00264 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
00265 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
00266 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup DMA_mode DMA mode
00272   * @brief    DMA mode
00273   * @{
00274   */
00275 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
00276 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
00277 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
00278 /**
00279   * @}
00280   */
00281
00282
00283 /** @defgroup DMA_Priority_level DMA Priority level
00284   * @brief    DMA priority levels
00285   * @{
00286   */
00287 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level: Low       */
00288 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
00289 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
00290 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
00291 /**
00292   * @}
00293   */
00294
00295
00296 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
00297   * @brief    DMA FIFO direct mode
00298   * @{
00299   */
00300 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000)       /*!< FIFO mode disable */
00301 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
00307   * @brief    DMA FIFO level
00308   * @{
00309   */
00310 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000)       /*!< FIFO threshold 1 quart full configuration  */
00311 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
00312 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
00313 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup DMA_Memory_burst DMA Memory burst
00319   * @brief    DMA memory burst
00320   * @{
00321   */
00322 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000)
00323 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
00324 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
00325 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
00326 /**
00327   * @}
00328   */
00329
00330
00331 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
00332   * @brief    DMA peripheral burst
00333   * @{
00334   */
00335 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000)
00336 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
00337 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
00338 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00344   * @brief    DMA interrupts definition
00345   * @{
00346   */
00347 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
00348 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
00349 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
00350 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
00351 #define DMA_IT_FE                         ((uint32_t)0x00000080)
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup DMA_flag_definitions DMA flag definitions
00357   * @brief    DMA flag definitions
00358   * @{
00359   */
00360 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001)
00361 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004)
00362 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008)
00363 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010)
00364 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020)
00365 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040)
00366 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100)
00367 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200)
00368 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400)
00369 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800)
00370 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000)
00371 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000)
00372 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000)
00373 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000)
00374 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000)
00375 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000)
00376 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000)
00377 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000)
00378 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000)
00379 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000)
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /* Exported macro ------------------------------------------------------------*/
00389
00390 /** @brief Reset DMA handle state
00391   * @param  __HANDLE__: specifies the DMA handle.
00392   * @retval None
00393   */
00394 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00395
00396 /**
00397   * @brief  Return the current DMA Stream FIFO filled level.
00398   * @param  __HANDLE__: DMA handle
00399   * @retval The FIFO filling state.
00400   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
00401   *                                              and not empty.
00402   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
00403   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
00404   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
00405   *           - DMA_FIFOStatus_Empty: when FIFO is empty
00406   *           - DMA_FIFOStatus_Full: when FIFO is full
00407   */
00408 #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
00409
00410 /**
00411   * @brief  Enable the specified DMA Stream.
00412   * @param  __HANDLE__: DMA handle
00413   * @retval None
00414   */
00415 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
00416
00417 /**
00418   * @brief  Disable the specified DMA Stream.
00419   * @param  __HANDLE__: DMA handle
00420   * @retval None
00421   */
00422 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
00423
00424 /* Interrupt & Flag management */
00425
00426 /**
00427   * @brief  Return the current DMA Stream transfer complete flag.
00428   * @param  __HANDLE__: DMA handle
00429   * @retval The specified transfer complete flag index.
00430   */
00431 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00432 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
00433  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
00434  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
00435  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
00436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
00437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
00438  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
00439  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
00440  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
00441  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
00442  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
00443  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
00444    DMA_FLAG_TCIF3_7)
00445
00446 /**
00447   * @brief  Return the current DMA Stream half transfer complete flag.
00448   * @param  __HANDLE__: DMA handle
00449   * @retval The specified half transfer complete flag index.
00450   */
00451 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00452 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
00453  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
00454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
00455  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
00456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
00457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
00458  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
00459  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
00460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
00461  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
00462  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
00463  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
00464    DMA_FLAG_HTIF3_7)
00465
00466 /**
00467   * @brief  Return the current DMA Stream transfer error flag.
00468   * @param  __HANDLE__: DMA handle
00469   * @retval The specified transfer error flag index.
00470   */
00471 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00472 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
00473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
00474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
00475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
00476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
00477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
00478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
00479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
00480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
00481  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
00482  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
00483  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
00484    DMA_FLAG_TEIF3_7)
00485
00486 /**
00487   * @brief  Return the current DMA Stream FIFO error flag.
00488   * @param  __HANDLE__: DMA handle
00489   * @retval The specified FIFO error flag index.
00490   */
00491 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
00492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
00493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
00494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
00495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
00496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
00497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
00498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
00499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
00500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
00501  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
00502  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
00503  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
00504    DMA_FLAG_FEIF3_7)
00505
00506 /**
00507   * @brief  Return the current DMA Stream direct mode error flag.
00508   * @param  __HANDLE__: DMA handle
00509   * @retval The specified direct mode error flag index.
00510   */
00511 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
00512 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
00513  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
00514  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
00515  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
00516  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
00517  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
00518  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
00519  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
00520  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
00521  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
00522  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
00523  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
00524    DMA_FLAG_DMEIF3_7)
00525
00526 /**
00527   * @brief  Get the DMA Stream pending flags.
00528   * @param  __HANDLE__: DMA handle
00529   * @param  __FLAG__: Get the specified flag.
00530   *          This parameter can be any combination of the following values:
00531   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00532   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00533   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00534   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00535   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00536   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00537   * @retval The state of FLAG (SET or RESET).
00538   */
00539 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00540 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
00541  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
00542  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
00543
00544 /**
00545   * @brief  Clear the DMA Stream pending flags.
00546   * @param  __HANDLE__: DMA handle
00547   * @param  __FLAG__: specifies the flag to clear.
00548   *          This parameter can be any combination of the following values:
00549   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00550   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00551   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00552   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00553   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00554   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00555   * @retval None
00556   */
00557 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00558 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
00559  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
00560  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
00561
00562 /**
00563   * @brief  Enable the specified DMA Stream interrupts.
00564   * @param  __HANDLE__: DMA handle
00565   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00566   *        This parameter can be any combination of the following values:
00567   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
00568   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
00569   *           @arg DMA_IT_TE: Transfer error interrupt mask.
00570   *           @arg DMA_IT_FE: FIFO error interrupt mask.
00571   *           @arg DMA_IT_DME: Direct mode error interrupt.
00572   * @retval None
00573   */
00574 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
00575 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
00576
00577 /**
00578   * @brief  Disable the specified DMA Stream interrupts.
00579   * @param  __HANDLE__: DMA handle
00580   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00581   *         This parameter can be any combination of the following values:
00582   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
00583   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
00584   *            @arg DMA_IT_TE: Transfer error interrupt mask.
00585   *            @arg DMA_IT_FE: FIFO error interrupt mask.
00586   *            @arg DMA_IT_DME: Direct mode error interrupt.
00587   * @retval None
00588   */
00589 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
00590 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
00591
00592 /**
00593   * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
00594   * @param  __HANDLE__: DMA handle
00595   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00596   *         This parameter can be one of the following values:
00597   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
00598   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
00599   *            @arg DMA_IT_TE: Transfer error interrupt mask.
00600   *            @arg DMA_IT_FE: FIFO error interrupt mask.
00601   *            @arg DMA_IT_DME: Direct mode error interrupt.
00602   * @retval The state of DMA_IT.
00603   */
00604 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
00605                                                         ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
00606                                                         ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
00607
00608 /**
00609   * @brief  Writes the number of data units to be transferred on the DMA Stream.
00610   * @param  __HANDLE__: DMA handle
00611   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
00612   *          Number of data items depends only on the Peripheral data format.
00613   *
00614   * @note   If Peripheral data format is Bytes: number of data units is equal
00615   *         to total number of bytes to be transferred.
00616   *
00617   * @note   If Peripheral data format is Half-Word: number of data units is
00618   *         equal to total number of bytes to be transferred / 2.
00619   *
00620   * @note   If Peripheral data format is Word: number of data units is equal
00621   *         to total  number of bytes to be transferred / 4.
00622   *
00623   * @retval The number of remaining data units in the current DMAy Streamx transfer.
00624   */
00625 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
00626
00627 /**
00628   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
00629   * @param  __HANDLE__: DMA handle
00630   *
00631   * @retval The number of remaining data units in the current DMA Stream transfer.
00632   */
00633 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
00634
00635
00636 /* Include DMA HAL Extension module */
00637 #include "stm32f7xx_hal_dma_ex.h"
00638
00639 /* Exported functions --------------------------------------------------------*/
00640
00641 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00642   * @brief    DMA Exported functions
00643   * @{
00644   */
00645
00646 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00647   * @brief   Initialization and de-initialization functions
00648   * @{
00649   */
00650 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00651 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
00657   * @brief   I/O operation functions
00658   * @{
00659   */
00660 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00661 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00662 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00663 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00664 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
00670   * @brief    Peripheral State functions
00671   * @{
00672   */
00673 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00674 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00675 /**
00676   * @}
00677   */
00678 /**
00679   * @}
00680   */
00681 /* Private Constants -------------------------------------------------------------*/
00682 /** @defgroup DMA_Private_Constants DMA Private Constants
00683   * @brief    DMA private defines and constants
00684   * @{
00685   */
00686 /**
00687   * @}
00688   */
00689
00690 /* Private macros ------------------------------------------------------------*/
00691 /** @defgroup DMA_Private_Macros DMA Private Macros
00692   * @brief    DMA private macros
00693   * @{
00694   */
00695 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
00696                                  ((CHANNEL) == DMA_CHANNEL_1) || \
00697                                  ((CHANNEL) == DMA_CHANNEL_2) || \
00698                                  ((CHANNEL) == DMA_CHANNEL_3) || \
00699                                  ((CHANNEL) == DMA_CHANNEL_4) || \
00700                                  ((CHANNEL) == DMA_CHANNEL_5) || \
00701                                  ((CHANNEL) == DMA_CHANNEL_6) || \
00702                                  ((CHANNEL) == DMA_CHANNEL_7))
00703
00704 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00705                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00706                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00707
00708 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00709
00710 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00711                                             ((STATE) == DMA_PINC_DISABLE))
00712
00713 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00714                                         ((STATE) == DMA_MINC_DISABLE))
00715
00716 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00717                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00718                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00719
00720 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00721                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00722                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00723
00724 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00725                            ((MODE) == DMA_CIRCULAR) || \
00726                            ((MODE) == DMA_PFCTRL))
00727
00728 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00729                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00730                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00731                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00732
00733 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
00734                                        ((STATE) == DMA_FIFOMODE_ENABLE))
00735
00736 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
00737                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
00738                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
00739                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
00740
00741 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
00742                                     ((BURST) == DMA_MBURST_INC4)   || \
00743                                     ((BURST) == DMA_MBURST_INC8)   || \
00744                                     ((BURST) == DMA_MBURST_INC16))
00745
00746 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
00747                                         ((BURST) == DMA_PBURST_INC4)   || \
00748                                         ((BURST) == DMA_PBURST_INC8)   || \
00749                                         ((BURST) == DMA_PBURST_INC16))
00750 /**
00751   * @}
00752   */
00753
00754 /* Private functions ---------------------------------------------------------*/
00755 /** @defgroup DMA_Private_Functions DMA Private Functions
00756   * @brief    DMA private  functions
00757   * @{
00758   */
00759 /**
00760   * @}
00761   */
00762
00763 /**
00764   * @}
00765   */
00766
00767 /**
00768   * @}
00769   */
00770
00771 #ifdef __cplusplus
00772 }
00773 #endif
00774
00775 #endif /* __STM32F7xx_HAL_DMA_H */
00776
00777 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma_ex.c Source File

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stm32f7xx_hal_dma_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   DMA Extension HAL module driver
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the DMA Extension peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017   The DMA Extension HAL driver can be used as follows:
00018    (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
00019        for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
00020
00021      -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
00022      -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
00023      -@-  In Multi (Double) buffer mode, it is possible to update the base address for
00024           the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
00025
00026   @endverbatim
00027   ******************************************************************************
00028   * @attention
00029   *
00030   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00031   *
00032   * Redistribution and use in source and binary forms, with or without modification,
00033   * are permitted provided that the following conditions are met:
00034   *   1. Redistributions of source code must retain the above copyright notice,
00035   *      this list of conditions and the following disclaimer.
00036   *   2. Redistributions in binary form must reproduce the above copyright notice,
00037   *      this list of conditions and the following disclaimer in the documentation
00038   *      and/or other materials provided with the distribution.
00039   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00040   *      may be used to endorse or promote products derived from this software
00041   *      without specific prior written permission.
00042   *
00043   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00044   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00045   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00046   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00047   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00048   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00049   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00050   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00051   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00052   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00053   *
00054   ******************************************************************************
00055   */
00056
00057 /* Includes ------------------------------------------------------------------*/
00058 #include "stm32f7xx_hal.h"
00059
00060 /** @addtogroup STM32F7xx_HAL_Driver
00061   * @{
00062   */
00063
00064 /** @defgroup DMAEx DMAEx
00065   * @brief DMA Extended HAL module driver
00066   * @{
00067   */
00068
00069 #ifdef HAL_DMA_MODULE_ENABLED
00070
00071 /* Private types -------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private Constants ---------------------------------------------------------*/
00074 /* Private macros ------------------------------------------------------------*/
00075 /* Private functions ---------------------------------------------------------*/
00076 /** @addtogroup DMAEx_Private_Functions
00077   * @{
00078   */
00079
00080 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00081
00082 /**
00083   * @brief  Set the DMA Transfer parameter.
00084   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00085   *                     the configuration information for the specified DMA Stream.
00086   * @param  SrcAddress: The source memory Buffer address
00087   * @param  DstAddress: The destination memory Buffer address
00088   * @param  DataLength: The length of data to be transferred from source to destination
00089   * @retval HAL status
00090   */
00091 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00092 {
00093   /* Configure DMA Stream data length */
00094   hdma->Instance->NDTR = DataLength;
00095
00096   /* Peripheral to Memory */
00097   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00098   {
00099     /* Configure DMA Stream destination address */
00100     hdma->Instance->PAR = DstAddress;
00101
00102     /* Configure DMA Stream source address */
00103     hdma->Instance->M0AR = SrcAddress;
00104   }
00105   /* Memory to Peripheral */
00106   else
00107   {
00108     /* Configure DMA Stream source address */
00109     hdma->Instance->PAR = SrcAddress;
00110
00111     /* Configure DMA Stream destination address */
00112     hdma->Instance->M0AR = DstAddress;
00113   }
00114 }
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Exported functions ---------------------------------------------------------*/
00121
00122 /** @addtogroup DMAEx_Exported_Functions
00123   * @{
00124   */
00125
00126
00127 /** @addtogroup DMAEx_Exported_Functions_Group1
00128   *
00129 @verbatim
00130  ===============================================================================
00131                 #####  Extended features functions  #####
00132  ===============================================================================
00133     [..]  This section provides functions allowing to:
00134       (+) Configure the source, destination address and data length and
00135           Start MultiBuffer DMA transfer
00136       (+) Configure the source, destination address and data length and
00137           Start MultiBuffer DMA transfer with interrupt
00138       (+) Change on the fly the memory0 or memory1 address.
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144
00145 /**
00146   * @brief  Starts the multi_buffer DMA Transfer.
00147   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00148   *                     the configuration information for the specified DMA Stream.
00149   * @param  SrcAddress: The source memory Buffer address
00150   * @param  DstAddress: The destination memory Buffer address
00151   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00152   * @param  DataLength: The length of data to be transferred from source to destination
00153   * @retval HAL status
00154   */
00155 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00156 {
00157   /* Process Locked */
00158   __HAL_LOCK(hdma);
00159
00160   /* Current memory buffer used is Memory 0 */
00161   if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
00162   {
00163     hdma->State = HAL_DMA_STATE_BUSY_MEM0;
00164   }
00165   /* Current memory buffer used is Memory 1 */
00166   else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
00167   {
00168     hdma->State = HAL_DMA_STATE_BUSY_MEM1;
00169   }
00170
00171    /* Check the parameters */
00172   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00173
00174   /* Disable the peripheral */
00175   __HAL_DMA_DISABLE(hdma);
00176
00177   /* Enable the double buffer mode */
00178   hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
00179
00180   /* Configure DMA Stream destination address */
00181   hdma->Instance->M1AR = SecondMemAddress;
00182
00183   /* Configure the source, destination address and the data length */
00184   DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00185
00186   /* Enable the peripheral */
00187   __HAL_DMA_ENABLE(hdma);
00188
00189   return HAL_OK;
00190 }
00191
00192 /**
00193   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
00194   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00195   *                     the configuration information for the specified DMA Stream.
00196   * @param  SrcAddress: The source memory Buffer address
00197   * @param  DstAddress: The destination memory Buffer address
00198   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00199   * @param  DataLength: The length of data to be transferred from source to destination
00200   * @retval HAL status
00201   */
00202 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00203 {
00204   /* Process Locked */
00205   __HAL_LOCK(hdma);
00206
00207   /* Current memory buffer used is Memory 0 */
00208   if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
00209   {
00210     hdma->State = HAL_DMA_STATE_BUSY_MEM0;
00211   }
00212   /* Current memory buffer used is Memory 1 */
00213   else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
00214   {
00215     hdma->State = HAL_DMA_STATE_BUSY_MEM1;
00216   }
00217
00218   /* Check the parameters */
00219   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00220
00221   /* Disable the peripheral */
00222   __HAL_DMA_DISABLE(hdma);
00223
00224   /* Enable the Double buffer mode */
00225   hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
00226
00227   /* Configure DMA Stream destination address */
00228   hdma->Instance->M1AR = SecondMemAddress;
00229
00230   /* Configure the source, destination address and the data length */
00231   DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00232
00233   /* Enable the transfer complete interrupt */
00234   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
00235
00236   /* Enable the Half transfer interrupt */
00237   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
00238
00239   /* Enable the transfer Error interrupt */
00240   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
00241
00242   /* Enable the fifo Error interrupt */
00243   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
00244
00245   /* Enable the direct mode Error interrupt */
00246   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
00247
00248   /* Enable the peripheral */
00249   __HAL_DMA_ENABLE(hdma);
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  Change the memory0 or memory1 address on the fly.
00256   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00257   *                     the configuration information for the specified DMA Stream.
00258   * @param  Address:    The new address
00259   * @param  memory:     the memory to be changed, This parameter can be one of
00260   *                     the following values:
00261   *                      MEMORY0 /
00262   *                      MEMORY1
00263   * @note   The MEMORY0 address can be changed only when the current transfer use
00264   *         MEMORY1 and the MEMORY1 address can be changed only when the current
00265   *         transfer use MEMORY0.
00266   * @retval HAL status
00267   */
00268 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
00269 {
00270   if(memory == MEMORY0)
00271   {
00272     /* change the memory0 address */
00273     hdma->Instance->M0AR = Address;
00274   }
00275   else
00276   {
00277     /* change the memory1 address */
00278     hdma->Instance->M1AR = Address;
00279   }
00280
00281   return HAL_OK;
00282 }
00283
00284 /**
00285   * @}
00286   */
00287
00288 /**
00289   * @}
00290   */
00291
00292 #endif /* HAL_DMA_MODULE_ENABLED */
00293 /**
00294   * @}
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_dma_ex.h Source File

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  • STM32F7xx_HAL_Driver
  • Inc
stm32f7xx_hal_dma_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of DMA HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_DMA_EX_H
00040 #define __STM32F7xx_HAL_DMA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00059   * @brief DMAEx Exported types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL DMA Memory definition
00065   */
00066 typedef enum
00067 {
00068   MEMORY0      = 0x00,    /*!< Memory 0     */
00069   MEMORY1      = 0x01,    /*!< Memory 1     */
00070
00071 }HAL_DMA_MemoryTypeDef;
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported functions --------------------------------------------------------*/
00078 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00079   * @brief   DMAEx Exported functions
00080   * @{
00081   */
00082
00083 /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
00084   * @brief   Extended features functions
00085   * @{
00086   */
00087
00088 /* IO operation functions *******************************************************/
00089 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00090 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00091 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
00092
00093 /**
00094   * @}
00095   */
00096 /**
00097   * @}
00098   */
00099
00100 /* Private functions ---------------------------------------------------------*/
00101 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
00102   * @brief DMAEx Private functions
00103   * @{
00104   */
00105 /**
00106   * @}
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 #ifdef __cplusplus
00118 }
00119 #endif
00120
00121 #endif /* __STM32F7xx_HAL_DMA_H */
00122
00123 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_eth.c Source File

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  • STM32F7xx_HAL_Driver
  • Src
stm32f7xx_hal_eth.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_eth.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   ETH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Ethernet (ETH) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#)Declare a ETH_HandleTypeDef handle structure, for example:
00021          ETH_HandleTypeDef  heth;
00022
00023       (#)Fill parameters of Init structure in heth handle
00024
00025       (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
00026
00027       (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
00028           (##) Enable the Ethernet interface clock using
00029                (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
00030                (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
00031                (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
00032
00033           (##) Initialize the related GPIO clocks
00034           (##) Configure Ethernet pin-out
00035           (##) Configure Ethernet NVIC interrupt (IT mode)
00036
00037       (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
00038           (##) HAL_ETH_DMATxDescListInit(); for Transmission process
00039           (##) HAL_ETH_DMARxDescListInit(); for Reception process
00040
00041       (#)Enable MAC and DMA transmission and reception:
00042           (##) HAL_ETH_Start();
00043
00044       (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
00045          the frame to MAC TX FIFO:
00046          (##) HAL_ETH_TransmitFrame();
00047
00048       (#)Poll for a received frame in ETH RX DMA Descriptors and get received
00049          frame parameters
00050          (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
00051
00052       (#) Get a received frame when an ETH RX interrupt occurs:
00053          (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
00054
00055       (#) Communicate with external PHY device:
00056          (##) Read a specific register from the PHY
00057               HAL_ETH_ReadPHYRegister();
00058          (##) Write data to a specific RHY register:
00059               HAL_ETH_WritePHYRegister();
00060
00061       (#) Configure the Ethernet MAC after ETH peripheral initialization
00062           HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
00063
00064       (#) Configure the Ethernet DMA after ETH peripheral initialization
00065           HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
00066
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00072   *
00073   * Redistribution and use in source and binary forms, with or without modification,
00074   * are permitted provided that the following conditions are met:
00075   *   1. Redistributions of source code must retain the above copyright notice,
00076   *      this list of conditions and the following disclaimer.
00077   *   2. Redistributions in binary form must reproduce the above copyright notice,
00078   *      this list of conditions and the following disclaimer in the documentation
00079   *      and/or other materials provided with the distribution.
00080   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00081   *      may be used to endorse or promote products derived from this software
00082   *      without specific prior written permission.
00083   *
00084   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00085   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00086   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00087   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00088   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00089   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00090   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00091   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00092   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00093   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00094   *
00095   ******************************************************************************
00096   */
00097
00098 /* Includes ------------------------------------------------------------------*/
00099 #include "stm32f7xx_hal.h"
00100
00101 /** @addtogroup STM32F7xx_HAL_Driver
00102   * @{
00103   */
00104
00105 /** @defgroup ETH ETH
00106   * @brief ETH HAL module driver
00107   * @{
00108   */
00109
00110 #ifdef HAL_ETH_MODULE_ENABLED
00111
00112 /* Private typedef -----------------------------------------------------------*/
00113 /* Private define ------------------------------------------------------------*/
00114 /** @defgroup ETH_Private_Constants ETH Private Constants
00115   * @{
00116   */
00117 #define LINKED_STATE_TIMEOUT_VALUE          ((uint32_t)2000)  /* 2000 ms */
00118 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE    ((uint32_t)1000)  /* 1000 ms */
00119
00120 /**
00121   * @}
00122   */
00123 /* Private macro -------------------------------------------------------------*/
00124 /* Private variables ---------------------------------------------------------*/
00125 /* Private function prototypes -----------------------------------------------*/
00126 /** @defgroup ETH_Private_Functions ETH Private Functions
00127   * @{
00128   */
00129 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
00130 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
00131 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
00132 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
00133 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
00134 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
00135 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
00136 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
00137 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
00138 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
00139 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
00140
00141 /**
00142   * @}
00143   */
00144 /* Private functions ---------------------------------------------------------*/
00145
00146 /** @defgroup ETH_Exported_Functions ETH Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
00151   *  @brief   Initialization and Configuration functions
00152   *
00153   @verbatim
00154   ===============================================================================
00155             ##### Initialization and de-initialization functions #####
00156   ===============================================================================
00157   [..]  This section provides functions allowing to:
00158       (+) Initialize and configure the Ethernet peripheral
00159       (+) De-initialize the Ethernet peripheral
00160
00161   @endverbatim
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  Initializes the Ethernet MAC and DMA according to default
00167   *         parameters.
00168   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00169   *         the configuration information for ETHERNET module
00170   * @retval HAL status
00171   */
00172 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
00173 {
00174   uint32_t tempreg = 0, phyreg = 0;
00175   uint32_t hclk = 60000000;
00176   uint32_t tickstart = 0;
00177   uint32_t err = ETH_SUCCESS;
00178
00179   /* Check the ETH peripheral state */
00180   if(heth == NULL)
00181   {
00182     return HAL_ERROR;
00183   }
00184
00185   /* Check parameters */
00186   assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
00187   assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
00188   assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
00189   assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
00190
00191   if(heth->State == HAL_ETH_STATE_RESET)
00192   {
00193     /* Allocate lock resource and initialize it */
00194     heth->Lock = HAL_UNLOCKED;
00195     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
00196     HAL_ETH_MspInit(heth);
00197   }
00198
00199   /* Enable SYSCFG Clock */
00200   __HAL_RCC_SYSCFG_CLK_ENABLE();
00201
00202   /* Select MII or RMII Mode*/
00203   SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
00204   SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
00205
00206   /* Ethernet Software reset */
00207   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
00208   /* After reset all the registers holds their respective reset values */
00209   (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
00210
00211   /* Wait for software reset */
00212   while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
00213   {
00214   }
00215
00216   /*-------------------------------- MAC Initialization ----------------------*/
00217   /* Get the ETHERNET MACMIIAR value */
00218   tempreg = (heth->Instance)->MACMIIAR;
00219   /* Clear CSR Clock Range CR[2:0] bits */
00220   tempreg &= ETH_MACMIIAR_CR_MASK;
00221
00222   /* Get hclk frequency value */
00223   hclk = HAL_RCC_GetHCLKFreq();
00224
00225   /* Set CR bits depending on hclk value */
00226   if((hclk >= 20000000)&&(hclk < 35000000))
00227   {
00228     /* CSR Clock Range between 20-35 MHz */
00229     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
00230   }
00231   else if((hclk >= 35000000)&&(hclk < 60000000))
00232   {
00233     /* CSR Clock Range between 35-60 MHz */
00234     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
00235   }
00236   else if((hclk >= 60000000)&&(hclk < 100000000))
00237   {
00238     /* CSR Clock Range between 60-100 MHz */
00239     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
00240   }
00241   else if((hclk >= 100000000)&&(hclk < 150000000))
00242   {
00243     /* CSR Clock Range between 100-150 MHz */
00244     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
00245   }
00246   else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */
00247   {
00248     /* CSR Clock Range between 150-216 MHz */
00249     tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
00250   }
00251
00252   /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
00253   (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
00254
00255   /*-------------------- PHY initialization and configuration ----------------*/
00256   /* Put the PHY in reset mode */
00257   if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
00258   {
00259     /* In case of write timeout */
00260     err = ETH_ERROR;
00261
00262     /* Config MAC and DMA */
00263     ETH_MACDMAConfig(heth, err);
00264
00265     /* Set the ETH peripheral state to READY */
00266     heth->State = HAL_ETH_STATE_READY;
00267
00268     /* Return HAL_ERROR */
00269     return HAL_ERROR;
00270   }
00271
00272   /* Delay to assure PHY reset */
00273   HAL_Delay(PHY_RESET_DELAY);
00274
00275   if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
00276   {
00277     /* Get tick */
00278     tickstart = HAL_GetTick();
00279
00280     /* We wait for linked status */
00281     do
00282     {
00283       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
00284
00285       /* Check for the Timeout */
00286       if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
00287       {
00288         /* In case of write timeout */
00289         err = ETH_ERROR;
00290
00291         /* Config MAC and DMA */
00292         ETH_MACDMAConfig(heth, err);
00293
00294         heth->State= HAL_ETH_STATE_READY;
00295
00296         /* Process Unlocked */
00297         __HAL_UNLOCK(heth);
00298
00299         return HAL_TIMEOUT;
00300       }
00301     } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
00302
00303
00304     /* Enable Auto-Negotiation */
00305     if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
00306     {
00307       /* In case of write timeout */
00308       err = ETH_ERROR;
00309
00310       /* Config MAC and DMA */
00311       ETH_MACDMAConfig(heth, err);
00312
00313       /* Set the ETH peripheral state to READY */
00314       heth->State = HAL_ETH_STATE_READY;
00315
00316       /* Return HAL_ERROR */
00317       return HAL_ERROR;
00318     }
00319
00320     /* Get tick */
00321     tickstart = HAL_GetTick();
00322
00323     /* Wait until the auto-negotiation will be completed */
00324     do
00325     {
00326       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
00327
00328       /* Check for the Timeout */
00329       if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
00330       {
00331         /* In case of write timeout */
00332         err = ETH_ERROR;
00333
00334         /* Config MAC and DMA */
00335         ETH_MACDMAConfig(heth, err);
00336
00337         heth->State= HAL_ETH_STATE_READY;
00338
00339         /* Process Unlocked */
00340         __HAL_UNLOCK(heth);
00341
00342         return HAL_TIMEOUT;
00343       }
00344
00345     } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
00346
00347     /* Read the result of the auto-negotiation */
00348     if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
00349     {
00350       /* In case of write timeout */
00351       err = ETH_ERROR;
00352
00353       /* Config MAC and DMA */
00354       ETH_MACDMAConfig(heth, err);
00355
00356       /* Set the ETH peripheral state to READY */
00357       heth->State = HAL_ETH_STATE_READY;
00358
00359       /* Return HAL_ERROR */
00360       return HAL_ERROR;
00361     }
00362
00363     /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
00364     if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
00365     {
00366       /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
00367       (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
00368     }
00369     else
00370     {
00371       /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
00372       (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
00373     }
00374     /* Configure the MAC with the speed fixed by the auto-negotiation process */
00375     if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
00376     {
00377       /* Set Ethernet speed to 10M following the auto-negotiation */
00378       (heth->Init).Speed = ETH_SPEED_10M;
00379     }
00380     else
00381     {
00382       /* Set Ethernet speed to 100M following the auto-negotiation */
00383       (heth->Init).Speed = ETH_SPEED_100M;
00384     }
00385   }
00386   else /* AutoNegotiation Disable */
00387   {
00388     /* Check parameters */
00389     assert_param(IS_ETH_SPEED(heth->Init.Speed));
00390     assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
00391
00392     /* Set MAC Speed and Duplex Mode */
00393     if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
00394                                                 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
00395     {
00396       /* In case of write timeout */
00397       err = ETH_ERROR;
00398
00399       /* Config MAC and DMA */
00400       ETH_MACDMAConfig(heth, err);
00401
00402       /* Set the ETH peripheral state to READY */
00403       heth->State = HAL_ETH_STATE_READY;
00404
00405       /* Return HAL_ERROR */
00406       return HAL_ERROR;
00407     }
00408
00409     /* Delay to assure PHY configuration */
00410     HAL_Delay(PHY_CONFIG_DELAY);
00411   }
00412
00413   /* Config MAC and DMA */
00414   ETH_MACDMAConfig(heth, err);
00415
00416   /* Set ETH HAL State to Ready */
00417   heth->State= HAL_ETH_STATE_READY;
00418
00419   /* Return function status */
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief  De-Initializes the ETH peripheral.
00425   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00426   *         the configuration information for ETHERNET module
00427   * @retval HAL status
00428   */
00429 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
00430 {
00431   /* Set the ETH peripheral state to BUSY */
00432   heth->State = HAL_ETH_STATE_BUSY;
00433
00434   /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
00435   HAL_ETH_MspDeInit(heth);
00436
00437   /* Set ETH HAL state to Disabled */
00438   heth->State= HAL_ETH_STATE_RESET;
00439
00440   /* Release Lock */
00441   __HAL_UNLOCK(heth);
00442
00443   /* Return function status */
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @brief  Initializes the DMA Tx descriptors in chain mode.
00449   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00450   *         the configuration information for ETHERNET module
00451   * @param  DMATxDescTab: Pointer to the first Tx desc list
00452   * @param  TxBuff: Pointer to the first TxBuffer list
00453   * @param  TxBuffCount: Number of the used Tx desc in the list
00454   * @retval HAL status
00455   */
00456 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
00457 {
00458   uint32_t i = 0;
00459   ETH_DMADescTypeDef *dmatxdesc;
00460
00461   /* Process Locked */
00462   __HAL_LOCK(heth);
00463
00464   /* Set the ETH peripheral state to BUSY */
00465   heth->State = HAL_ETH_STATE_BUSY;
00466
00467   /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
00468   heth->TxDesc = DMATxDescTab;
00469
00470   /* Fill each DMATxDesc descriptor with the right values */
00471   for(i=0; i < TxBuffCount; i++)
00472   {
00473     /* Get the pointer on the ith member of the Tx Desc list */
00474     dmatxdesc = DMATxDescTab + i;
00475
00476     /* Set Second Address Chained bit */
00477     dmatxdesc->Status = ETH_DMATXDESC_TCH;
00478
00479     /* Set Buffer1 address pointer */
00480     dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
00481
00482     if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
00483     {
00484       /* Set the DMA Tx descriptors checksum insertion */
00485       dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
00486     }
00487
00488     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
00489     if(i < (TxBuffCount-1))
00490     {
00491       /* Set next descriptor address register with next descriptor base address */
00492       dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
00493     }
00494     else
00495     {
00496       /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
00497       dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
00498     }
00499   }
00500
00501   /* Set Transmit Descriptor List Address Register */
00502   (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
00503
00504   /* Set ETH HAL State to Ready */
00505   heth->State= HAL_ETH_STATE_READY;
00506
00507   /* Process Unlocked */
00508   __HAL_UNLOCK(heth);
00509
00510   /* Return function status */
00511   return HAL_OK;
00512 }
00513
00514 /**
00515   * @brief  Initializes the DMA Rx descriptors in chain mode.
00516   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00517   *         the configuration information for ETHERNET module
00518   * @param  DMARxDescTab: Pointer to the first Rx desc list
00519   * @param  RxBuff: Pointer to the first RxBuffer list
00520   * @param  RxBuffCount: Number of the used Rx desc in the list
00521   * @retval HAL status
00522   */
00523 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
00524 {
00525   uint32_t i = 0;
00526   ETH_DMADescTypeDef *DMARxDesc;
00527
00528   /* Process Locked */
00529   __HAL_LOCK(heth);
00530
00531   /* Set the ETH peripheral state to BUSY */
00532   heth->State = HAL_ETH_STATE_BUSY;
00533
00534   /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
00535   heth->RxDesc = DMARxDescTab;
00536
00537   /* Fill each DMARxDesc descriptor with the right values */
00538   for(i=0; i < RxBuffCount; i++)
00539   {
00540     /* Get the pointer on the ith member of the Rx Desc list */
00541     DMARxDesc = DMARxDescTab+i;
00542
00543     /* Set Own bit of the Rx descriptor Status */
00544     DMARxDesc->Status = ETH_DMARXDESC_OWN;
00545
00546     /* Set Buffer1 size and Second Address Chained bit */
00547     DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
00548
00549     /* Set Buffer1 address pointer */
00550     DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
00551
00552     if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
00553     {
00554       /* Enable Ethernet DMA Rx Descriptor interrupt */
00555       DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
00556     }
00557
00558     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
00559     if(i < (RxBuffCount-1))
00560     {
00561       /* Set next descriptor address register with next descriptor base address */
00562       DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
00563     }
00564     else
00565     {
00566       /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
00567       DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
00568     }
00569   }
00570
00571   /* Set Receive Descriptor List Address Register */
00572   (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
00573
00574   /* Set ETH HAL State to Ready */
00575   heth->State= HAL_ETH_STATE_READY;
00576
00577   /* Process Unlocked */
00578   __HAL_UNLOCK(heth);
00579
00580   /* Return function status */
00581   return HAL_OK;
00582 }
00583
00584 /**
00585   * @brief  Initializes the ETH MSP.
00586   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00587   *         the configuration information for ETHERNET module
00588   * @retval None
00589   */
00590 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
00591 {
00592   /* Prevent unused argument(s) compilation warning */
00593   UNUSED(heth);
00594
00595   /* NOTE : This function Should not be modified, when the callback is needed,
00596   the HAL_ETH_MspInit could be implemented in the user file
00597   */
00598 }
00599
00600 /**
00601   * @brief  DeInitializes ETH MSP.
00602   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00603   *         the configuration information for ETHERNET module
00604   * @retval None
00605   */
00606 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
00607 {
00608   /* Prevent unused argument(s) compilation warning */
00609   UNUSED(heth);
00610
00611   /* NOTE : This function Should not be modified, when the callback is needed,
00612   the HAL_ETH_MspDeInit could be implemented in the user file
00613   */
00614 }
00615
00616 /**
00617   * @}
00618   */
00619
00620 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
00621   *  @brief   Data transfers functions
00622   *
00623   @verbatim
00624   ==============================================================================
00625                           ##### IO operation functions #####
00626   ==============================================================================
00627   [..]  This section provides functions allowing to:
00628         (+) Transmit a frame
00629             HAL_ETH_TransmitFrame();
00630         (+) Receive a frame
00631             HAL_ETH_GetReceivedFrame();
00632             HAL_ETH_GetReceivedFrame_IT();
00633         (+) Read from an External PHY register
00634             HAL_ETH_ReadPHYRegister();
00635         (+) Write to an External PHY register
00636             HAL_ETH_WritePHYRegister();
00637
00638   @endverbatim
00639
00640   * @{
00641   */
00642
00643 /**
00644   * @brief  Sends an Ethernet frame.
00645   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00646   *         the configuration information for ETHERNET module
00647   * @param  FrameLength: Amount of data to be sent
00648   * @retval HAL status
00649   */
00650 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
00651 {
00652   uint32_t bufcount = 0, size = 0, i = 0;
00653
00654   /* Process Locked */
00655   __HAL_LOCK(heth);
00656
00657   /* Set the ETH peripheral state to BUSY */
00658   heth->State = HAL_ETH_STATE_BUSY;
00659
00660   if (FrameLength == 0)
00661   {
00662     /* Set ETH HAL state to READY */
00663     heth->State = HAL_ETH_STATE_READY;
00664
00665     /* Process Unlocked */
00666     __HAL_UNLOCK(heth);
00667
00668     return  HAL_ERROR;
00669   }
00670
00671   /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
00672   if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
00673   {
00674     /* OWN bit set */
00675     heth->State = HAL_ETH_STATE_BUSY_TX;
00676
00677     /* Process Unlocked */
00678     __HAL_UNLOCK(heth);
00679
00680     return HAL_ERROR;
00681   }
00682
00683   /* Get the number of needed Tx buffers for the current frame */
00684   if (FrameLength > ETH_TX_BUF_SIZE)
00685   {
00686     bufcount = FrameLength/ETH_TX_BUF_SIZE;
00687     if (FrameLength % ETH_TX_BUF_SIZE)
00688     {
00689       bufcount++;
00690     }
00691   }
00692   else
00693   {
00694     bufcount = 1;
00695   }
00696   if (bufcount == 1)
00697   {
00698     /* Set LAST and FIRST segment */
00699     heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
00700     /* Set frame size */
00701     heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
00702     /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
00703     heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
00704     /* Point to next descriptor */
00705     heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
00706   }
00707   else
00708   {
00709     for (i=0; i< bufcount; i++)
00710     {
00711       /* Clear FIRST and LAST segment bits */
00712       heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
00713
00714       if (i == 0)
00715       {
00716         /* Setting the first segment bit */
00717         heth->TxDesc->Status |= ETH_DMATXDESC_FS;
00718       }
00719
00720       /* Program size */
00721       heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
00722
00723       if (i == (bufcount-1))
00724       {
00725         /* Setting the last segment bit */
00726         heth->TxDesc->Status |= ETH_DMATXDESC_LS;
00727         size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
00728         heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
00729       }
00730
00731       /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
00732       heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
00733       /* point to next descriptor */
00734       heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
00735     }
00736   }
00737
00738   /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
00739   if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
00740   {
00741     /* Clear TBUS ETHERNET DMA flag */
00742     (heth->Instance)->DMASR = ETH_DMASR_TBUS;
00743     /* Resume DMA transmission*/
00744     (heth->Instance)->DMATPDR = 0;
00745   }
00746
00747   /* Set ETH HAL State to Ready */
00748   heth->State = HAL_ETH_STATE_READY;
00749
00750   /* Process Unlocked */
00751   __HAL_UNLOCK(heth);
00752
00753   /* Return function status */
00754   return HAL_OK;
00755 }
00756
00757 /**
00758   * @brief  Checks for received frames.
00759   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00760   *         the configuration information for ETHERNET module
00761   * @retval HAL status
00762   */
00763 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
00764 {
00765   uint32_t framelength = 0;
00766
00767   /* Process Locked */
00768   __HAL_LOCK(heth);
00769
00770   /* Check the ETH state to BUSY */
00771   heth->State = HAL_ETH_STATE_BUSY;
00772
00773   /* Check if segment is not owned by DMA */
00774   /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
00775   if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
00776   {
00777     /* Check if last segment */
00778     if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
00779     {
00780       /* increment segment count */
00781       (heth->RxFrameInfos).SegCount++;
00782
00783       /* Check if last segment is first segment: one segment contains the frame */
00784       if ((heth->RxFrameInfos).SegCount == 1)
00785       {
00786         (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
00787       }
00788
00789       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
00790
00791       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
00792       framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
00793       heth->RxFrameInfos.length = framelength;
00794
00795       /* Get the address of the buffer start address */
00796       heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
00797       /* point to next descriptor */
00798       heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
00799
00800       /* Set HAL State to Ready */
00801       heth->State = HAL_ETH_STATE_READY;
00802
00803       /* Process Unlocked */
00804       __HAL_UNLOCK(heth);
00805
00806       /* Return function status */
00807       return HAL_OK;
00808     }
00809     /* Check if first segment */
00810     else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
00811     {
00812       (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
00813       (heth->RxFrameInfos).LSRxDesc = NULL;
00814       (heth->RxFrameInfos).SegCount = 1;
00815       /* Point to next descriptor */
00816       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00817     }
00818     /* Check if intermediate segment */
00819     else
00820     {
00821       (heth->RxFrameInfos).SegCount++;
00822       /* Point to next descriptor */
00823       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00824     }
00825   }
00826
00827   /* Set ETH HAL State to Ready */
00828   heth->State = HAL_ETH_STATE_READY;
00829
00830   /* Process Unlocked */
00831   __HAL_UNLOCK(heth);
00832
00833   /* Return function status */
00834   return HAL_ERROR;
00835 }
00836
00837 /**
00838   * @brief  Gets the Received frame in interrupt mode.
00839   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00840   *         the configuration information for ETHERNET module
00841   * @retval HAL status
00842   */
00843 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
00844 {
00845   uint32_t descriptorscancounter = 0;
00846
00847   /* Process Locked */
00848   __HAL_LOCK(heth);
00849
00850   /* Set ETH HAL State to BUSY */
00851   heth->State = HAL_ETH_STATE_BUSY;
00852
00853   /* Scan descriptors owned by CPU */
00854   while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
00855   {
00856     /* Just for security */
00857     descriptorscancounter++;
00858
00859     /* Check if first segment in frame */
00860     /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
00861     if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
00862     {
00863       heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
00864       heth->RxFrameInfos.SegCount = 1;
00865       /* Point to next descriptor */
00866       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00867     }
00868     /* Check if intermediate segment */
00869     /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
00870     else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
00871     {
00872       /* Increment segment count */
00873       (heth->RxFrameInfos.SegCount)++;
00874       /* Point to next descriptor */
00875       heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
00876     }
00877     /* Should be last segment */
00878     else
00879     {
00880       /* Last segment */
00881       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
00882
00883       /* Increment segment count */
00884       (heth->RxFrameInfos.SegCount)++;
00885
00886       /* Check if last segment is first segment: one segment contains the frame */
00887       if ((heth->RxFrameInfos.SegCount) == 1)
00888       {
00889         heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
00890       }
00891
00892       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
00893       heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
00894
00895       /* Get the address of the buffer start address */
00896       heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
00897
00898       /* Point to next descriptor */
00899       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00900
00901       /* Set HAL State to Ready */
00902       heth->State = HAL_ETH_STATE_READY;
00903
00904       /* Process Unlocked */
00905       __HAL_UNLOCK(heth);
00906
00907       /* Return function status */
00908       return HAL_OK;
00909     }
00910   }
00911
00912   /* Set HAL State to Ready */
00913   heth->State = HAL_ETH_STATE_READY;
00914
00915   /* Process Unlocked */
00916   __HAL_UNLOCK(heth);
00917
00918   /* Return function status */
00919   return HAL_ERROR;
00920 }
00921
00922 /**
00923   * @brief  This function handles ETH interrupt request.
00924   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00925   *         the configuration information for ETHERNET module
00926   * @retval HAL status
00927   */
00928 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
00929 {
00930   /* Frame received */
00931   if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
00932   {
00933     /* Receive complete callback */
00934     HAL_ETH_RxCpltCallback(heth);
00935
00936      /* Clear the Eth DMA Rx IT pending bits */
00937     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
00938
00939     /* Set HAL State to Ready */
00940     heth->State = HAL_ETH_STATE_READY;
00941
00942     /* Process Unlocked */
00943     __HAL_UNLOCK(heth);
00944
00945   }
00946   /* Frame transmitted */
00947   else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
00948   {
00949     /* Transfer complete callback */
00950     HAL_ETH_TxCpltCallback(heth);
00951
00952     /* Clear the Eth DMA Tx IT pending bits */
00953     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
00954
00955     /* Set HAL State to Ready */
00956     heth->State = HAL_ETH_STATE_READY;
00957
00958     /* Process Unlocked */
00959     __HAL_UNLOCK(heth);
00960   }
00961
00962   /* Clear the interrupt flags */
00963   __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
00964
00965   /* ETH DMA Error */
00966   if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
00967   {
00968     /* Ethernet Error callback */
00969     HAL_ETH_ErrorCallback(heth);
00970
00971     /* Clear the interrupt flags */
00972     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
00973
00974     /* Set HAL State to Ready */
00975     heth->State = HAL_ETH_STATE_READY;
00976
00977     /* Process Unlocked */
00978     __HAL_UNLOCK(heth);
00979   }
00980 }
00981
00982 /**
00983   * @brief  Tx Transfer completed callbacks.
00984   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00985   *         the configuration information for ETHERNET module
00986   * @retval None
00987   */
00988 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
00989 {
00990   /* Prevent unused argument(s) compilation warning */
00991   UNUSED(heth);
00992
00993   /* NOTE : This function Should not be modified, when the callback is needed,
00994   the HAL_ETH_TxCpltCallback could be implemented in the user file
00995   */
00996 }
00997
00998 /**
00999   * @brief  Rx Transfer completed callbacks.
01000   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01001   *         the configuration information for ETHERNET module
01002   * @retval None
01003   */
01004 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
01005 {
01006   /* Prevent unused argument(s) compilation warning */
01007   UNUSED(heth);
01008
01009   /* NOTE : This function Should not be modified, when the callback is needed,
01010   the HAL_ETH_TxCpltCallback could be implemented in the user file
01011   */
01012 }
01013
01014 /**
01015   * @brief  Ethernet transfer error callbacks
01016   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01017   *         the configuration information for ETHERNET module
01018   * @retval None
01019   */
01020 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
01021 {
01022   /* Prevent unused argument(s) compilation warning */
01023   UNUSED(heth);
01024
01025   /* NOTE : This function Should not be modified, when the callback is needed,
01026   the HAL_ETH_TxCpltCallback could be implemented in the user file
01027   */
01028 }
01029
01030 /**
01031   * @brief  Reads a PHY register
01032   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01033   *         the configuration information for ETHERNET module
01034   * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
01035   *                This parameter can be one of the following values:
01036   *                   PHY_BCR: Transceiver Basic Control Register,
01037   *                   PHY_BSR: Transceiver Basic Status Register.
01038   *                   More PHY register could be read depending on the used PHY
01039   * @param RegValue: PHY register value
01040   * @retval HAL status
01041   */
01042 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
01043 {
01044   uint32_t tmpreg = 0;
01045   uint32_t tickstart = 0;
01046
01047   /* Check parameters */
01048   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
01049
01050   /* Check the ETH peripheral state */
01051   if(heth->State == HAL_ETH_STATE_BUSY_RD)
01052   {
01053     return HAL_BUSY;
01054   }
01055   /* Set ETH HAL State to BUSY_RD */
01056   heth->State = HAL_ETH_STATE_BUSY_RD;
01057
01058   /* Get the ETHERNET MACMIIAR value */
01059   tmpreg = heth->Instance->MACMIIAR;
01060
01061   /* Keep only the CSR Clock Range CR[2:0] bits value */
01062   tmpreg &= ~ETH_MACMIIAR_CR_MASK;
01063
01064   /* Prepare the MII address register value */
01065   tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address   */
01066   tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                   /* Set the PHY register address */
01067   tmpreg &= ~ETH_MACMIIAR_MW;                                           /* Set the read mode            */
01068   tmpreg |= ETH_MACMIIAR_MB;                                            /* Set the MII Busy bit         */
01069
01070   /* Write the result value into the MII Address register */
01071   heth->Instance->MACMIIAR = tmpreg;
01072
01073   /* Get tick */
01074   tickstart = HAL_GetTick();
01075
01076   /* Check for the Busy flag */
01077   while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
01078   {
01079     /* Check for the Timeout */
01080     if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
01081     {
01082       heth->State= HAL_ETH_STATE_READY;
01083
01084       /* Process Unlocked */
01085       __HAL_UNLOCK(heth);
01086
01087       return HAL_TIMEOUT;
01088     }
01089
01090     tmpreg = heth->Instance->MACMIIAR;
01091   }
01092
01093   /* Get MACMIIDR value */
01094   *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
01095
01096   /* Set ETH HAL State to READY */
01097   heth->State = HAL_ETH_STATE_READY;
01098
01099   /* Return function status */
01100   return HAL_OK;
01101 }
01102
01103 /**
01104   * @brief  Writes to a PHY register.
01105   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01106   *         the configuration information for ETHERNET module
01107   * @param  PHYReg: PHY register address, is the index of one of the 32 PHY register.
01108   *          This parameter can be one of the following values:
01109   *             PHY_BCR: Transceiver Control Register.
01110   *             More PHY register could be written depending on the used PHY
01111   * @param  RegValue: the value to write
01112   * @retval HAL status
01113   */
01114 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
01115 {
01116   uint32_t tmpreg = 0;
01117   uint32_t tickstart = 0;
01118
01119   /* Check parameters */
01120   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
01121
01122   /* Check the ETH peripheral state */
01123   if(heth->State == HAL_ETH_STATE_BUSY_WR)
01124   {
01125     return HAL_BUSY;
01126   }
01127   /* Set ETH HAL State to BUSY_WR */
01128   heth->State = HAL_ETH_STATE_BUSY_WR;
01129
01130   /* Get the ETHERNET MACMIIAR value */
01131   tmpreg = heth->Instance->MACMIIAR;
01132
01133   /* Keep only the CSR Clock Range CR[2:0] bits value */
01134   tmpreg &= ~ETH_MACMIIAR_CR_MASK;
01135
01136   /* Prepare the MII register address value */
01137   tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
01138   tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                 /* Set the PHY register address */
01139   tmpreg |= ETH_MACMIIAR_MW;                                          /* Set the write mode */
01140   tmpreg |= ETH_MACMIIAR_MB;                                          /* Set the MII Busy bit */
01141
01142   /* Give the value to the MII data register */
01143   heth->Instance->MACMIIDR = (uint16_t)RegValue;
01144
01145   /* Write the result value into the MII Address register */
01146   heth->Instance->MACMIIAR = tmpreg;
01147
01148   /* Get tick */
01149   tickstart = HAL_GetTick();
01150
01151   /* Check for the Busy flag */
01152   while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
01153   {
01154     /* Check for the Timeout */
01155     if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
01156     {
01157       heth->State= HAL_ETH_STATE_READY;
01158
01159       /* Process Unlocked */
01160       __HAL_UNLOCK(heth);
01161
01162       return HAL_TIMEOUT;
01163     }
01164
01165     tmpreg = heth->Instance->MACMIIAR;
01166   }
01167
01168   /* Set ETH HAL State to READY */
01169   heth->State = HAL_ETH_STATE_READY;
01170
01171   /* Return function status */
01172   return HAL_OK;
01173 }
01174
01175 /**
01176   * @}
01177   */
01178
01179 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
01180  *  @brief    Peripheral Control functions
01181  *
01182 @verbatim
01183  ===============================================================================
01184                   ##### Peripheral Control functions #####
01185  ===============================================================================
01186     [..]  This section provides functions allowing to:
01187       (+) Enable MAC and DMA transmission and reception.
01188           HAL_ETH_Start();
01189       (+) Disable MAC and DMA transmission and reception.
01190           HAL_ETH_Stop();
01191       (+) Set the MAC configuration in runtime mode
01192           HAL_ETH_ConfigMAC();
01193       (+) Set the DMA configuration in runtime mode
01194           HAL_ETH_ConfigDMA();
01195
01196 @endverbatim
01197   * @{
01198   */
01199
01200  /**
01201   * @brief  Enables Ethernet MAC and DMA reception/transmission
01202   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01203   *         the configuration information for ETHERNET module
01204   * @retval HAL status
01205   */
01206 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
01207 {
01208   /* Process Locked */
01209   __HAL_LOCK(heth);
01210
01211   /* Set the ETH peripheral state to BUSY */
01212   heth->State = HAL_ETH_STATE_BUSY;
01213
01214   /* Enable transmit state machine of the MAC for transmission on the MII */
01215   ETH_MACTransmissionEnable(heth);
01216
01217   /* Enable receive state machine of the MAC for reception from the MII */
01218   ETH_MACReceptionEnable(heth);
01219
01220   /* Flush Transmit FIFO */
01221   ETH_FlushTransmitFIFO(heth);
01222
01223   /* Start DMA transmission */
01224   ETH_DMATransmissionEnable(heth);
01225
01226   /* Start DMA reception */
01227   ETH_DMAReceptionEnable(heth);
01228
01229   /* Set the ETH state to READY*/
01230   heth->State= HAL_ETH_STATE_READY;
01231
01232   /* Process Unlocked */
01233   __HAL_UNLOCK(heth);
01234
01235   /* Return function status */
01236   return HAL_OK;
01237 }
01238
01239 /**
01240   * @brief  Stop Ethernet MAC and DMA reception/transmission
01241   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01242   *         the configuration information for ETHERNET module
01243   * @retval HAL status
01244   */
01245 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
01246 {
01247   /* Process Locked */
01248   __HAL_LOCK(heth);
01249
01250   /* Set the ETH peripheral state to BUSY */
01251   heth->State = HAL_ETH_STATE_BUSY;
01252
01253   /* Stop DMA transmission */
01254   ETH_DMATransmissionDisable(heth);
01255
01256   /* Stop DMA reception */
01257   ETH_DMAReceptionDisable(heth);
01258
01259   /* Disable receive state machine of the MAC for reception from the MII */
01260   ETH_MACReceptionDisable(heth);
01261
01262   /* Flush Transmit FIFO */
01263   ETH_FlushTransmitFIFO(heth);
01264
01265   /* Disable transmit state machine of the MAC for transmission on the MII */
01266   ETH_MACTransmissionDisable(heth);
01267
01268   /* Set the ETH state*/
01269   heth->State = HAL_ETH_STATE_READY;
01270
01271   /* Process Unlocked */
01272   __HAL_UNLOCK(heth);
01273
01274   /* Return function status */
01275   return HAL_OK;
01276 }
01277
01278 /**
01279   * @brief  Set ETH MAC Configuration.
01280   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01281   *         the configuration information for ETHERNET module
01282   * @param  macconf: MAC Configuration structure
01283   * @retval HAL status
01284   */
01285 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
01286 {
01287   uint32_t tmpreg = 0;
01288
01289   /* Process Locked */
01290   __HAL_LOCK(heth);
01291
01292   /* Set the ETH peripheral state to BUSY */
01293   heth->State= HAL_ETH_STATE_BUSY;
01294
01295   assert_param(IS_ETH_SPEED(heth->Init.Speed));
01296   assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
01297
01298   if (macconf != NULL)
01299   {
01300     /* Check the parameters */
01301     assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
01302     assert_param(IS_ETH_JABBER(macconf->Jabber));
01303     assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
01304     assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
01305     assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
01306     assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
01307     assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
01308     assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
01309     assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
01310     assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
01311     assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
01312     assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
01313     assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
01314     assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
01315     assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
01316     assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
01317     assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
01318     assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
01319     assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
01320     assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
01321     assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
01322     assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
01323     assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
01324     assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
01325     assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
01326     assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
01327     assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
01328
01329     /*------------------------ ETHERNET MACCR Configuration --------------------*/
01330     /* Get the ETHERNET MACCR value */
01331     tmpreg = (heth->Instance)->MACCR;
01332     /* Clear WD, PCE, PS, TE and RE bits */
01333     tmpreg &= ETH_MACCR_CLEAR_MASK;
01334
01335     tmpreg |= (uint32_t)(macconf->Watchdog |
01336                          macconf->Jabber |
01337                          macconf->InterFrameGap |
01338                          macconf->CarrierSense |
01339                          (heth->Init).Speed |
01340                          macconf->ReceiveOwn |
01341                          macconf->LoopbackMode |
01342                          (heth->Init).DuplexMode |
01343                          macconf->ChecksumOffload |
01344                          macconf->RetryTransmission |
01345                          macconf->AutomaticPadCRCStrip |
01346                          macconf->BackOffLimit |
01347                          macconf->DeferralCheck);
01348
01349     /* Write to ETHERNET MACCR */
01350     (heth->Instance)->MACCR = (uint32_t)tmpreg;
01351
01352     /* Wait until the write operation will be taken into account :
01353     at least four TX_CLK/RX_CLK clock cycles */
01354     tmpreg = (heth->Instance)->MACCR;
01355     HAL_Delay(ETH_REG_WRITE_DELAY);
01356     (heth->Instance)->MACCR = tmpreg;
01357
01358     /*----------------------- ETHERNET MACFFR Configuration --------------------*/
01359     /* Write to ETHERNET MACFFR */
01360     (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
01361                                           macconf->SourceAddrFilter |
01362                                           macconf->PassControlFrames |
01363                                           macconf->BroadcastFramesReception |
01364                                           macconf->DestinationAddrFilter |
01365                                           macconf->PromiscuousMode |
01366                                           macconf->MulticastFramesFilter |
01367                                           macconf->UnicastFramesFilter);
01368
01369      /* Wait until the write operation will be taken into account :
01370      at least four TX_CLK/RX_CLK clock cycles */
01371      tmpreg = (heth->Instance)->MACFFR;
01372      HAL_Delay(ETH_REG_WRITE_DELAY);
01373      (heth->Instance)->MACFFR = tmpreg;
01374
01375      /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
01376      /* Write to ETHERNET MACHTHR */
01377      (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
01378
01379      /* Write to ETHERNET MACHTLR */
01380      (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
01381      /*----------------------- ETHERNET MACFCR Configuration --------------------*/
01382
01383      /* Get the ETHERNET MACFCR value */
01384      tmpreg = (heth->Instance)->MACFCR;
01385      /* Clear xx bits */
01386      tmpreg &= ETH_MACFCR_CLEAR_MASK;
01387
01388      tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
01389                           macconf->ZeroQuantaPause |
01390                           macconf->PauseLowThreshold |
01391                           macconf->UnicastPauseFrameDetect |
01392                           macconf->ReceiveFlowControl |
01393                           macconf->TransmitFlowControl);
01394
01395      /* Write to ETHERNET MACFCR */
01396      (heth->Instance)->MACFCR = (uint32_t)tmpreg;
01397
01398      /* Wait until the write operation will be taken into account :
01399      at least four TX_CLK/RX_CLK clock cycles */
01400      tmpreg = (heth->Instance)->MACFCR;
01401      HAL_Delay(ETH_REG_WRITE_DELAY);
01402      (heth->Instance)->MACFCR = tmpreg;
01403
01404      /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
01405      (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
01406                                               macconf->VLANTagIdentifier);
01407
01408       /* Wait until the write operation will be taken into account :
01409       at least four TX_CLK/RX_CLK clock cycles */
01410       tmpreg = (heth->Instance)->MACVLANTR;
01411       HAL_Delay(ETH_REG_WRITE_DELAY);
01412       (heth->Instance)->MACVLANTR = tmpreg;
01413   }
01414   else /* macconf == NULL : here we just configure Speed and Duplex mode */
01415   {
01416     /*------------------------ ETHERNET MACCR Configuration --------------------*/
01417     /* Get the ETHERNET MACCR value */
01418     tmpreg = (heth->Instance)->MACCR;
01419
01420     /* Clear FES and DM bits */
01421     tmpreg &= ~((uint32_t)0x00004800);
01422
01423     tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
01424
01425     /* Write to ETHERNET MACCR */
01426     (heth->Instance)->MACCR = (uint32_t)tmpreg;
01427
01428     /* Wait until the write operation will be taken into account:
01429     at least four TX_CLK/RX_CLK clock cycles */
01430     tmpreg = (heth->Instance)->MACCR;
01431     HAL_Delay(ETH_REG_WRITE_DELAY);
01432     (heth->Instance)->MACCR = tmpreg;
01433   }
01434
01435   /* Set the ETH state to Ready */
01436   heth->State= HAL_ETH_STATE_READY;
01437
01438   /* Process Unlocked */
01439   __HAL_UNLOCK(heth);
01440
01441   /* Return function status */
01442   return HAL_OK;
01443 }
01444
01445 /**
01446   * @brief  Sets ETH DMA Configuration.
01447   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01448   *         the configuration information for ETHERNET module
01449   * @param  dmaconf: DMA Configuration structure
01450   * @retval HAL status
01451   */
01452 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
01453 {
01454   uint32_t tmpreg = 0;
01455
01456   /* Process Locked */
01457   __HAL_LOCK(heth);
01458
01459   /* Set the ETH peripheral state to BUSY */
01460   heth->State= HAL_ETH_STATE_BUSY;
01461
01462   /* Check parameters */
01463   assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
01464   assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
01465   assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
01466   assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
01467   assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
01468   assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
01469   assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
01470   assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
01471   assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
01472   assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
01473   assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
01474   assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
01475   assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
01476   assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
01477   assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
01478   assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
01479
01480   /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
01481   /* Get the ETHERNET DMAOMR value */
01482   tmpreg = (heth->Instance)->DMAOMR;
01483   /* Clear xx bits */
01484   tmpreg &= ETH_DMAOMR_CLEAR_MASK;
01485
01486   tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
01487                        dmaconf->ReceiveStoreForward |
01488                        dmaconf->FlushReceivedFrame |
01489                        dmaconf->TransmitStoreForward |
01490                        dmaconf->TransmitThresholdControl |
01491                        dmaconf->ForwardErrorFrames |
01492                        dmaconf->ForwardUndersizedGoodFrames |
01493                        dmaconf->ReceiveThresholdControl |
01494                        dmaconf->SecondFrameOperate);
01495
01496   /* Write to ETHERNET DMAOMR */
01497   (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
01498
01499   /* Wait until the write operation will be taken into account:
01500   at least four TX_CLK/RX_CLK clock cycles */
01501   tmpreg = (heth->Instance)->DMAOMR;
01502   HAL_Delay(ETH_REG_WRITE_DELAY);
01503   (heth->Instance)->DMAOMR = tmpreg;
01504
01505   /*----------------------- ETHERNET DMABMR Configuration --------------------*/
01506   (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
01507                                          dmaconf->FixedBurst |
01508                                          dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
01509                                          dmaconf->TxDMABurstLength |
01510                                          dmaconf->EnhancedDescriptorFormat |
01511                                          (dmaconf->DescriptorSkipLength << 2) |
01512                                          dmaconf->DMAArbitration |
01513                                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
01514
01515    /* Wait until the write operation will be taken into account:
01516       at least four TX_CLK/RX_CLK clock cycles */
01517    tmpreg = (heth->Instance)->DMABMR;
01518    HAL_Delay(ETH_REG_WRITE_DELAY);
01519    (heth->Instance)->DMABMR = tmpreg;
01520
01521    /* Set the ETH state to Ready */
01522    heth->State= HAL_ETH_STATE_READY;
01523
01524    /* Process Unlocked */
01525    __HAL_UNLOCK(heth);
01526
01527    /* Return function status */
01528    return HAL_OK;
01529 }
01530
01531 /**
01532   * @}
01533   */
01534
01535 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
01536   *  @brief   Peripheral State functions
01537   *
01538   @verbatim
01539   ===============================================================================
01540                          ##### Peripheral State functions #####
01541   ===============================================================================
01542   [..]
01543   This subsection permits to get in run-time the status of the peripheral
01544   and the data flow.
01545        (+) Get the ETH handle state:
01546            HAL_ETH_GetState();
01547
01548
01549   @endverbatim
01550   * @{
01551   */
01552
01553 /**
01554   * @brief  Return the ETH HAL state
01555   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01556   *         the configuration information for ETHERNET module
01557   * @retval HAL state
01558   */
01559 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
01560 {
01561   /* Return ETH state */
01562   return heth->State;
01563 }
01564
01565 /**
01566   * @}
01567   */
01568
01569 /**
01570   * @}
01571   */
01572
01573 /** @addtogroup ETH_Private_Functions
01574   * @{
01575   */
01576
01577 /**
01578   * @brief  Configures Ethernet MAC and DMA with default parameters.
01579   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01580   *         the configuration information for ETHERNET module
01581   * @param  err: Ethernet Init error
01582   * @retval HAL status
01583   */
01584 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
01585 {
01586   ETH_MACInitTypeDef macinit;
01587   ETH_DMAInitTypeDef dmainit;
01588   uint32_t tmpreg = 0;
01589
01590   if (err != ETH_SUCCESS) /* Auto-negotiation failed */
01591   {
01592     /* Set Ethernet duplex mode to Full-duplex */
01593     (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
01594
01595     /* Set Ethernet speed to 100M */
01596     (heth->Init).Speed = ETH_SPEED_100M;
01597   }
01598
01599   /* Ethernet MAC default initialization **************************************/
01600   macinit.Watchdog = ETH_WATCHDOG_ENABLE;
01601   macinit.Jabber = ETH_JABBER_ENABLE;
01602   macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
01603   macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
01604   macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
01605   macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
01606   if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
01607   {
01608     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
01609   }
01610   else
01611   {
01612     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
01613   }
01614   macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
01615   macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
01616   macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
01617   macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
01618   macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
01619   macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
01620   macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
01621   macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
01622   macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
01623   macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
01624   macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
01625   macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
01626   macinit.HashTableHigh = 0x0;
01627   macinit.HashTableLow = 0x0;
01628   macinit.PauseTime = 0x0;
01629   macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
01630   macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
01631   macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
01632   macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
01633   macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
01634   macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
01635   macinit.VLANTagIdentifier = 0x0;
01636
01637   /*------------------------ ETHERNET MACCR Configuration --------------------*/
01638   /* Get the ETHERNET MACCR value */
01639   tmpreg = (heth->Instance)->MACCR;
01640   /* Clear WD, PCE, PS, TE and RE bits */
01641   tmpreg &= ETH_MACCR_CLEAR_MASK;
01642   /* Set the WD bit according to ETH Watchdog value */
01643   /* Set the JD: bit according to ETH Jabber value */
01644   /* Set the IFG bit according to ETH InterFrameGap value */
01645   /* Set the DCRS bit according to ETH CarrierSense value */
01646   /* Set the FES bit according to ETH Speed value */
01647   /* Set the DO bit according to ETH ReceiveOwn value */
01648   /* Set the LM bit according to ETH LoopbackMode value */
01649   /* Set the DM bit according to ETH Mode value */
01650   /* Set the IPCO bit according to ETH ChecksumOffload value */
01651   /* Set the DR bit according to ETH RetryTransmission value */
01652   /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
01653   /* Set the BL bit according to ETH BackOffLimit value */
01654   /* Set the DC bit according to ETH DeferralCheck value */
01655   tmpreg |= (uint32_t)(macinit.Watchdog |
01656                        macinit.Jabber |
01657                        macinit.InterFrameGap |
01658                        macinit.CarrierSense |
01659                        (heth->Init).Speed |
01660                        macinit.ReceiveOwn |
01661                        macinit.LoopbackMode |
01662                        (heth->Init).DuplexMode |
01663                        macinit.ChecksumOffload |
01664                        macinit.RetryTransmission |
01665                        macinit.AutomaticPadCRCStrip |
01666                        macinit.BackOffLimit |
01667                        macinit.DeferralCheck);
01668
01669   /* Write to ETHERNET MACCR */
01670   (heth->Instance)->MACCR = (uint32_t)tmpreg;
01671
01672   /* Wait until the write operation will be taken into account:
01673      at least four TX_CLK/RX_CLK clock cycles */
01674   tmpreg = (heth->Instance)->MACCR;
01675   HAL_Delay(ETH_REG_WRITE_DELAY);
01676   (heth->Instance)->MACCR = tmpreg;
01677
01678   /*----------------------- ETHERNET MACFFR Configuration --------------------*/
01679   /* Set the RA bit according to ETH ReceiveAll value */
01680   /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
01681   /* Set the PCF bit according to ETH PassControlFrames value */
01682   /* Set the DBF bit according to ETH BroadcastFramesReception value */
01683   /* Set the DAIF bit according to ETH DestinationAddrFilter value */
01684   /* Set the PR bit according to ETH PromiscuousMode value */
01685   /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
01686   /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
01687   /* Write to ETHERNET MACFFR */
01688   (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
01689                                         macinit.SourceAddrFilter |
01690                                         macinit.PassControlFrames |
01691                                         macinit.BroadcastFramesReception |
01692                                         macinit.DestinationAddrFilter |
01693                                         macinit.PromiscuousMode |
01694                                         macinit.MulticastFramesFilter |
01695                                         macinit.UnicastFramesFilter);
01696
01697    /* Wait until the write operation will be taken into account:
01698       at least four TX_CLK/RX_CLK clock cycles */
01699    tmpreg = (heth->Instance)->MACFFR;
01700    HAL_Delay(ETH_REG_WRITE_DELAY);
01701    (heth->Instance)->MACFFR = tmpreg;
01702
01703    /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
01704    /* Write to ETHERNET MACHTHR */
01705    (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
01706
01707    /* Write to ETHERNET MACHTLR */
01708    (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
01709    /*----------------------- ETHERNET MACFCR Configuration -------------------*/
01710
01711    /* Get the ETHERNET MACFCR value */
01712    tmpreg = (heth->Instance)->MACFCR;
01713    /* Clear xx bits */
01714    tmpreg &= ETH_MACFCR_CLEAR_MASK;
01715
01716    /* Set the PT bit according to ETH PauseTime value */
01717    /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
01718    /* Set the PLT bit according to ETH PauseLowThreshold value */
01719    /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
01720    /* Set the RFE bit according to ETH ReceiveFlowControl value */
01721    /* Set the TFE bit according to ETH TransmitFlowControl value */
01722    tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
01723                         macinit.ZeroQuantaPause |
01724                         macinit.PauseLowThreshold |
01725                         macinit.UnicastPauseFrameDetect |
01726                         macinit.ReceiveFlowControl |
01727                         macinit.TransmitFlowControl);
01728
01729    /* Write to ETHERNET MACFCR */
01730    (heth->Instance)->MACFCR = (uint32_t)tmpreg;
01731
01732    /* Wait until the write operation will be taken into account:
01733    at least four TX_CLK/RX_CLK clock cycles */
01734    tmpreg = (heth->Instance)->MACFCR;
01735    HAL_Delay(ETH_REG_WRITE_DELAY);
01736    (heth->Instance)->MACFCR = tmpreg;
01737
01738    /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
01739    /* Set the ETV bit according to ETH VLANTagComparison value */
01740    /* Set the VL bit according to ETH VLANTagIdentifier value */
01741    (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
01742                                             macinit.VLANTagIdentifier);
01743
01744     /* Wait until the write operation will be taken into account:
01745        at least four TX_CLK/RX_CLK clock cycles */
01746     tmpreg = (heth->Instance)->MACVLANTR;
01747     HAL_Delay(ETH_REG_WRITE_DELAY);
01748     (heth->Instance)->MACVLANTR = tmpreg;
01749
01750     /* Ethernet DMA default initialization ************************************/
01751     dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
01752     dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
01753     dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
01754     dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
01755     dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
01756     dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
01757     dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
01758     dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
01759     dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
01760     dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
01761     dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
01762     dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
01763     dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
01764     dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
01765     dmainit.DescriptorSkipLength = 0x0;
01766     dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
01767
01768     /* Get the ETHERNET DMAOMR value */
01769     tmpreg = (heth->Instance)->DMAOMR;
01770     /* Clear xx bits */
01771     tmpreg &= ETH_DMAOMR_CLEAR_MASK;
01772
01773     /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
01774     /* Set the RSF bit according to ETH ReceiveStoreForward value */
01775     /* Set the DFF bit according to ETH FlushReceivedFrame value */
01776     /* Set the TSF bit according to ETH TransmitStoreForward value */
01777     /* Set the TTC bit according to ETH TransmitThresholdControl value */
01778     /* Set the FEF bit according to ETH ForwardErrorFrames value */
01779     /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
01780     /* Set the RTC bit according to ETH ReceiveThresholdControl value */
01781     /* Set the OSF bit according to ETH SecondFrameOperate value */
01782     tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
01783                          dmainit.ReceiveStoreForward |
01784                          dmainit.FlushReceivedFrame |
01785                          dmainit.TransmitStoreForward |
01786                          dmainit.TransmitThresholdControl |
01787                          dmainit.ForwardErrorFrames |
01788                          dmainit.ForwardUndersizedGoodFrames |
01789                          dmainit.ReceiveThresholdControl |
01790                          dmainit.SecondFrameOperate);
01791
01792     /* Write to ETHERNET DMAOMR */
01793     (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
01794
01795     /* Wait until the write operation will be taken into account:
01796        at least four TX_CLK/RX_CLK clock cycles */
01797     tmpreg = (heth->Instance)->DMAOMR;
01798     HAL_Delay(ETH_REG_WRITE_DELAY);
01799     (heth->Instance)->DMAOMR = tmpreg;
01800
01801     /*----------------------- ETHERNET DMABMR Configuration ------------------*/
01802     /* Set the AAL bit according to ETH AddressAlignedBeats value */
01803     /* Set the FB bit according to ETH FixedBurst value */
01804     /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
01805     /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
01806     /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
01807     /* Set the DSL bit according to ETH DesciptorSkipLength value */
01808     /* Set the PR and DA bits according to ETH DMAArbitration value */
01809     (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
01810                                           dmainit.FixedBurst |
01811                                           dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
01812                                           dmainit.TxDMABurstLength |
01813                                           dmainit.EnhancedDescriptorFormat |
01814                                           (dmainit.DescriptorSkipLength << 2) |
01815                                           dmainit.DMAArbitration |
01816                                           ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
01817
01818      /* Wait until the write operation will be taken into account:
01819         at least four TX_CLK/RX_CLK clock cycles */
01820      tmpreg = (heth->Instance)->DMABMR;
01821      HAL_Delay(ETH_REG_WRITE_DELAY);
01822      (heth->Instance)->DMABMR = tmpreg;
01823
01824      if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
01825      {
01826        /* Enable the Ethernet Rx Interrupt */
01827        __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
01828      }
01829
01830      /* Initialize MAC address in ethernet MAC */
01831      ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
01832 }
01833
01834 /**
01835   * @brief  Configures the selected MAC address.
01836   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01837   *         the configuration information for ETHERNET module
01838   * @param  MacAddr: The MAC address to configure
01839   *          This parameter can be one of the following values:
01840   *             @arg ETH_MAC_Address0: MAC Address0
01841   *             @arg ETH_MAC_Address1: MAC Address1
01842   *             @arg ETH_MAC_Address2: MAC Address2
01843   *             @arg ETH_MAC_Address3: MAC Address3
01844   * @param  Addr: Pointer to MAC address buffer data (6 bytes)
01845   * @retval HAL status
01846   */
01847 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
01848 {
01849   uint32_t tmpreg;
01850
01851   /* Check the parameters */
01852   assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
01853
01854   /* Calculate the selected MAC address high register */
01855   tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
01856   /* Load the selected MAC address high register */
01857   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
01858   /* Calculate the selected MAC address low register */
01859   tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
01860
01861   /* Load the selected MAC address low register */
01862   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
01863 }
01864
01865 /**
01866   * @brief  Enables the MAC transmission.
01867   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01868   *         the configuration information for ETHERNET module
01869   * @retval None
01870   */
01871 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
01872 {
01873   __IO uint32_t tmpreg = 0;
01874
01875   /* Enable the MAC transmission */
01876   (heth->Instance)->MACCR |= ETH_MACCR_TE;
01877
01878   /* Wait until the write operation will be taken into account:
01879      at least four TX_CLK/RX_CLK clock cycles */
01880   tmpreg = (heth->Instance)->MACCR;
01881   HAL_Delay(ETH_REG_WRITE_DELAY);
01882   (heth->Instance)->MACCR = tmpreg;
01883 }
01884
01885 /**
01886   * @brief  Disables the MAC transmission.
01887   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01888   *         the configuration information for ETHERNET module
01889   * @retval None
01890   */
01891 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
01892 {
01893   __IO uint32_t tmpreg = 0;
01894
01895   /* Disable the MAC transmission */
01896   (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
01897
01898   /* Wait until the write operation will be taken into account:
01899      at least four TX_CLK/RX_CLK clock cycles */
01900   tmpreg = (heth->Instance)->MACCR;
01901   HAL_Delay(ETH_REG_WRITE_DELAY);
01902   (heth->Instance)->MACCR = tmpreg;
01903 }
01904
01905 /**
01906   * @brief  Enables the MAC reception.
01907   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01908   *         the configuration information for ETHERNET module
01909   * @retval None
01910   */
01911 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
01912 {
01913   __IO uint32_t tmpreg = 0;
01914
01915   /* Enable the MAC reception */
01916   (heth->Instance)->MACCR |= ETH_MACCR_RE;
01917
01918   /* Wait until the write operation will be taken into account:
01919      at least four TX_CLK/RX_CLK clock cycles */
01920   tmpreg = (heth->Instance)->MACCR;
01921   HAL_Delay(ETH_REG_WRITE_DELAY);
01922   (heth->Instance)->MACCR = tmpreg;
01923 }
01924
01925 /**
01926   * @brief  Disables the MAC reception.
01927   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01928   *         the configuration information for ETHERNET module
01929   * @retval None
01930   */
01931 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
01932 {
01933   __IO uint32_t tmpreg = 0;
01934
01935   /* Disable the MAC reception */
01936   (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
01937
01938   /* Wait until the write operation will be taken into account:
01939      at least four TX_CLK/RX_CLK clock cycles */
01940   tmpreg = (heth->Instance)->MACCR;
01941   HAL_Delay(ETH_REG_WRITE_DELAY);
01942   (heth->Instance)->MACCR = tmpreg;
01943 }
01944
01945 /**
01946   * @brief  Enables the DMA transmission.
01947   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01948   *         the configuration information for ETHERNET module
01949   * @retval None
01950   */
01951 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
01952 {
01953   /* Enable the DMA transmission */
01954   (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
01955 }
01956
01957 /**
01958   * @brief  Disables the DMA transmission.
01959   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01960   *         the configuration information for ETHERNET module
01961   * @retval None
01962   */
01963 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
01964 {
01965   /* Disable the DMA transmission */
01966   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
01967 }
01968
01969 /**
01970   * @brief  Enables the DMA reception.
01971   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01972   *         the configuration information for ETHERNET module
01973   * @retval None
01974   */
01975 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
01976 {
01977   /* Enable the DMA reception */
01978   (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
01979 }
01980
01981 /**
01982   * @brief  Disables the DMA reception.
01983   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01984   *         the configuration information for ETHERNET module
01985   * @retval None
01986   */
01987 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
01988 {
01989   /* Disable the DMA reception */
01990   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
01991 }
01992
01993 /**
01994   * @brief  Clears the ETHERNET transmit FIFO.
01995   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01996   *         the configuration information for ETHERNET module
01997   * @retval None
01998   */
01999 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
02000 {
02001   __IO uint32_t tmpreg = 0;
02002
02003   /* Set the Flush Transmit FIFO bit */
02004   (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
02005
02006   /* Wait until the write operation will be taken into account:
02007      at least four TX_CLK/RX_CLK clock cycles */
02008   tmpreg = (heth->Instance)->DMAOMR;
02009   HAL_Delay(ETH_REG_WRITE_DELAY);
02010   (heth->Instance)->DMAOMR = tmpreg;
02011 }
02012
02013 /**
02014   * @}
02015   */
02016
02017 #endif /* HAL_ETH_MODULE_ENABLED */
02018 /**
02019   * @}
02020   */
02021
02022 /**
02023   * @}
02024   */
02025
02026 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_eth.h Source File

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stm32f7xx_hal_eth.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_eth.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of ETH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_ETH_H
00040 #define __STM32F7xx_HAL_ETH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ETH
00054   * @{
00055   */
00056
00057 /** @addtogroup ETH_Private_Macros
00058   * @{
00059   */
00060 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
00061 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
00062                                      ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
00063 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
00064                              ((SPEED) == ETH_SPEED_100M))
00065 #define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \
00066                                   ((MODE) == ETH_MODE_HALFDUPLEX))
00067 #define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
00068                                  ((MODE) == ETH_RXINTERRUPT_MODE))
00069 #define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
00070                                       ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
00071 #define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
00072                                               ((MODE) == ETH_MEDIA_INTERFACE_RMII))
00073 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
00074                               ((CMD) == ETH_WATCHDOG_DISABLE))
00075 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
00076                             ((CMD) == ETH_JABBER_DISABLE))
00077 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
00078                                      ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
00079                                      ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
00080                                      ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
00081                                      ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
00082                                      ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
00083                                      ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
00084                                      ((GAP) == ETH_INTERFRAMEGAP_40BIT))
00085 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
00086                                    ((CMD) == ETH_CARRIERSENCE_DISABLE))
00087 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
00088                                  ((CMD) == ETH_RECEIVEOWN_DISABLE))
00089 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
00090                                    ((CMD) == ETH_LOOPBACKMODE_DISABLE))
00091 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
00092                                       ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
00093 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
00094                                         ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
00095 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
00096                                             ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
00097 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
00098                                      ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
00099                                      ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
00100                                      ((LIMIT) == ETH_BACKOFFLIMIT_1))
00101 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
00102                                     ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
00103 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
00104                                  ((CMD) == ETH_RECEIVEAll_DISABLE))
00105 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
00106                                         ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
00107                                         ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
00108 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
00109                                      ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
00110                                      ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
00111 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
00112                                                 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
00113 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
00114                                                 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
00115 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
00116                                       ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
00117 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
00118                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
00119                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
00120                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
00121 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
00122                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
00123                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
00124 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
00125 #define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
00126                                         ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
00127 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
00128                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
00129                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
00130                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
00131 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
00132                                                 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
00133 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
00134                                          ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
00135 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
00136                                           ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
00137 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
00138                                                 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
00139 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
00140 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
00141                                          ((ADDRESS) == ETH_MAC_ADDRESS1) || \
00142                                          ((ADDRESS) == ETH_MAC_ADDRESS2) || \
00143                                          ((ADDRESS) == ETH_MAC_ADDRESS3))
00144 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
00145                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \
00146                                         ((ADDRESS) == ETH_MAC_ADDRESS3))
00147 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
00148                                            ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
00149 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
00150                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
00151                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
00152                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
00153                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
00154                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
00155 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
00156                                                ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
00157 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
00158                                            ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
00159 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
00160                                          ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
00161 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
00162                                             ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
00163 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
00164                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
00165                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
00166                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
00167                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
00168                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
00169                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
00170                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
00171 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
00172                                           ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
00173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
00174                                                     ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
00175 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
00176                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
00177                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
00178                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
00179 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
00180                                           ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
00181 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
00182                                            ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
00183 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
00184                                  ((CMD) == ETH_FIXEDBURST_DISABLE))
00185 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
00186                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
00187                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
00188                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
00189                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
00190                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
00191                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
00192                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
00193                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
00194                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
00195                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
00196                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
00197 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
00198                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
00199                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
00200                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
00201                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
00202                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
00203                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
00204                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
00205                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
00206                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
00207                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
00208                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
00209 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
00210 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
00211                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
00212                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
00213                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
00214                                                        ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
00215 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
00216                                          ((FLAG) == ETH_DMATXDESC_IC) || \
00217                                          ((FLAG) == ETH_DMATXDESC_LS) || \
00218                                          ((FLAG) == ETH_DMATXDESC_FS) || \
00219                                          ((FLAG) == ETH_DMATXDESC_DC) || \
00220                                          ((FLAG) == ETH_DMATXDESC_DP) || \
00221                                          ((FLAG) == ETH_DMATXDESC_TTSE) || \
00222                                          ((FLAG) == ETH_DMATXDESC_TER) || \
00223                                          ((FLAG) == ETH_DMATXDESC_TCH) || \
00224                                          ((FLAG) == ETH_DMATXDESC_TTSS) || \
00225                                          ((FLAG) == ETH_DMATXDESC_IHE) || \
00226                                          ((FLAG) == ETH_DMATXDESC_ES) || \
00227                                          ((FLAG) == ETH_DMATXDESC_JT) || \
00228                                          ((FLAG) == ETH_DMATXDESC_FF) || \
00229                                          ((FLAG) == ETH_DMATXDESC_PCE) || \
00230                                          ((FLAG) == ETH_DMATXDESC_LCA) || \
00231                                          ((FLAG) == ETH_DMATXDESC_NC) || \
00232                                          ((FLAG) == ETH_DMATXDESC_LCO) || \
00233                                          ((FLAG) == ETH_DMATXDESC_EC) || \
00234                                          ((FLAG) == ETH_DMATXDESC_VF) || \
00235                                          ((FLAG) == ETH_DMATXDESC_CC) || \
00236                                          ((FLAG) == ETH_DMATXDESC_ED) || \
00237                                          ((FLAG) == ETH_DMATXDESC_UF) || \
00238                                          ((FLAG) == ETH_DMATXDESC_DB))
00239 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
00240                                             ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
00241 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
00242                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
00243                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
00244                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
00245 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
00246 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
00247                                          ((FLAG) == ETH_DMARXDESC_AFM) || \
00248                                          ((FLAG) == ETH_DMARXDESC_ES) || \
00249                                          ((FLAG) == ETH_DMARXDESC_DE) || \
00250                                          ((FLAG) == ETH_DMARXDESC_SAF) || \
00251                                          ((FLAG) == ETH_DMARXDESC_LE) || \
00252                                          ((FLAG) == ETH_DMARXDESC_OE) || \
00253                                          ((FLAG) == ETH_DMARXDESC_VLAN) || \
00254                                          ((FLAG) == ETH_DMARXDESC_FS) || \
00255                                          ((FLAG) == ETH_DMARXDESC_LS) || \
00256                                          ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
00257                                          ((FLAG) == ETH_DMARXDESC_LC) || \
00258                                          ((FLAG) == ETH_DMARXDESC_FT) || \
00259                                          ((FLAG) == ETH_DMARXDESC_RWT) || \
00260                                          ((FLAG) == ETH_DMARXDESC_RE) || \
00261                                          ((FLAG) == ETH_DMARXDESC_DBE) || \
00262                                          ((FLAG) == ETH_DMARXDESC_CE) || \
00263                                          ((FLAG) == ETH_DMARXDESC_MAMPCE))
00264 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
00265                                           ((BUFFER) == ETH_DMARXDESC_BUFFER2))
00266 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
00267                                    ((FLAG) == ETH_PMT_FLAG_MPR))
00268 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
00269 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
00270                                    ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
00271                                    ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
00272                                    ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
00273                                    ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
00274                                    ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
00275                                    ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
00276                                    ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
00277                                    ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
00278                                    ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
00279                                    ((FLAG) == ETH_DMA_FLAG_T))
00280 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
00281 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
00282                                ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
00283                                ((IT) == ETH_MAC_IT_PMT))
00284 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
00285                                    ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
00286                                    ((FLAG) == ETH_MAC_FLAG_PMT))
00287 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
00288 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
00289                                ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
00290                                ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
00291                                ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
00292                                ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
00293                                ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
00294                                ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
00295                                ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
00296                                ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
00297 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
00298                                            ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
00299 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
00300                            ((IT) != 0x00))
00301 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
00302                                ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
00303                                ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
00304 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
00305                                                 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
00306
00307
00308 /**
00309   * @}
00310   */
00311
00312 /** @addtogroup ETH_Private_Defines
00313   * @{
00314   */
00315 /* Delay to wait when writing to some Ethernet registers */
00316 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
00317
00318 /* ETHERNET Errors */
00319 #define  ETH_SUCCESS            ((uint32_t)0)
00320 #define  ETH_ERROR              ((uint32_t)1)
00321
00322 /* ETHERNET DMA Tx descriptors Collision Count Shift */
00323 #define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3)
00324
00325 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
00326 #define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
00327
00328 /* ETHERNET DMA Rx descriptors Frame Length Shift */
00329 #define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16)
00330
00331 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
00332 #define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
00333
00334 /* ETHERNET DMA Rx descriptors Frame length Shift */
00335 #define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)
00336
00337 /* ETHERNET MAC address offsets */
00338 #define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40)  /* ETHERNET MAC address high offset */
00339 #define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44)  /* ETHERNET MAC address low offset */
00340
00341 /* ETHERNET MACMIIAR register Mask */
00342 #define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
00343
00344 /* ETHERNET MACCR register Mask */
00345 #define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)
00346
00347 /* ETHERNET MACFCR register Mask */
00348 #define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
00349
00350 /* ETHERNET DMAOMR register Mask */
00351 #define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
00352
00353 /* ETHERNET Remote Wake-up frame register length */
00354 #define ETH_WAKEUP_REGISTER_LENGTH      8
00355
00356 /* ETHERNET Missed frames counter Shift */
00357 #define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
00358  /**
00359   * @}
00360   */
00361
00362 /* Exported types ------------------------------------------------------------*/
00363 /** @defgroup ETH_Exported_Types ETH Exported Types
00364   * @{
00365   */
00366
00367 /**
00368   * @brief  HAL State structures definition
00369   */
00370 typedef enum
00371 {
00372   HAL_ETH_STATE_RESET             = 0x00,    /*!< Peripheral not yet Initialized or disabled         */
00373   HAL_ETH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
00374   HAL_ETH_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
00375   HAL_ETH_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
00376   HAL_ETH_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
00377   HAL_ETH_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00378   HAL_ETH_STATE_BUSY_WR           = 0x42,    /*!< Write process is ongoing                           */
00379   HAL_ETH_STATE_BUSY_RD           = 0x82,    /*!< Read process is ongoing                            */
00380   HAL_ETH_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
00381   HAL_ETH_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                       */
00382 }HAL_ETH_StateTypeDef;
00383
00384 /**
00385   * @brief  ETH Init Structure definition
00386   */
00387
00388 typedef struct
00389 {
00390   uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
00391                                                            The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
00392                                                            and the mode (half/full-duplex).
00393                                                            This parameter can be a value of @ref ETH_AutoNegotiation */
00394
00395   uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.
00396                                                            This parameter can be a value of @ref ETH_Speed */
00397
00398   uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
00399                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
00400
00401   uint16_t             PhyAddress;                /*!< Ethernet PHY address.
00402                                                            This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
00403
00404   uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
00405
00406   uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
00407                                                            This parameter can be a value of @ref ETH_Rx_Mode */
00408
00409   uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software.
00410                                                          This parameter can be a value of @ref ETH_Checksum_Mode */
00411
00412   uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface.
00413                                                          This parameter can be a value of @ref ETH_Media_Interface */
00414
00415 } ETH_InitTypeDef;
00416
00417
00418  /**
00419   * @brief  ETH MAC Configuration Structure definition
00420   */
00421
00422 typedef struct
00423 {
00424   uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer
00425                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
00426                                                            When disabled, the MAC can receive up to 16384 bytes.
00427                                                            This parameter can be a value of @ref ETH_Watchdog */
00428
00429   uint32_t             Jabber;                    /*!< Selects or not Jabber timer
00430                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
00431                                                            When disabled, the MAC can send up to 16384 bytes.
00432                                                            This parameter can be a value of @ref ETH_Jabber */
00433
00434   uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.
00435                                                            This parameter can be a value of @ref ETH_Inter_Frame_Gap */
00436
00437   uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.
00438                                                            This parameter can be a value of @ref ETH_Carrier_Sense */
00439
00440   uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,
00441                                                            ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
00442                                                            in Half-Duplex mode.
00443                                                            This parameter can be a value of @ref ETH_Receive_Own */
00444
00445   uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.
00446                                                            This parameter can be a value of @ref ETH_Loop_Back_Mode */
00447
00448   uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
00449                                                            This parameter can be a value of @ref ETH_Checksum_Offload */
00450
00451   uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
00452                                                            when a collision occurs (Half-Duplex mode).
00453                                                            This parameter can be a value of @ref ETH_Retry_Transmission */
00454
00455   uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
00456                                                            This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
00457
00458   uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.
00459                                                            This parameter can be a value of @ref ETH_Back_Off_Limit */
00460
00461   uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).
00462                                                            This parameter can be a value of @ref ETH_Deferral_Check */
00463
00464   uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).
00465                                                            This parameter can be a value of @ref ETH_Receive_All */
00466
00467   uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.
00468                                                            This parameter can be a value of @ref ETH_Source_Addr_Filter */
00469
00470   uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
00471                                                            This parameter can be a value of @ref ETH_Pass_Control_Frames */
00472
00473   uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.
00474                                                            This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
00475
00476   uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.
00477                                                            This parameter can be a value of @ref ETH_Destination_Addr_Filter */
00478
00479   uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
00480                                                            This parameter can be a value of @ref ETH_Promiscuous_Mode */
00481
00482   uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
00483                                                            This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
00484
00485   uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
00486                                                            This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
00487
00488   uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.
00489                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
00490
00491   uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.
00492                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */
00493
00494   uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
00495                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
00496
00497   uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
00498                                                            This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
00499
00500   uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
00501                                                            automatic retransmission of PAUSE Frame.
00502                                                            This parameter can be a value of @ref ETH_Pause_Low_Threshold */
00503
00504   uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
00505                                                            unicast address and unique multicast address).
00506                                                            This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
00507
00508   uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
00509                                                            disable its transmitter for a specified time (Pause Time)
00510                                                            This parameter can be a value of @ref ETH_Receive_Flow_Control */
00511
00512   uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
00513                                                            or the MAC back-pressure operation (Half-Duplex mode)
00514                                                            This parameter can be a value of @ref ETH_Transmit_Flow_Control */
00515
00516   uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
00517                                                            comparison and filtering.
00518                                                            This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
00519
00520   uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
00521
00522 } ETH_MACInitTypeDef;
00523
00524
00525 /**
00526   * @brief  ETH DMA Configuration Structure definition
00527   */
00528
00529 typedef struct
00530 {
00531  uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
00532                                                              This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
00533
00534   uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
00535                                                              This parameter can be a value of @ref ETH_Receive_Store_Forward */
00536
00537   uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
00538                                                              This parameter can be a value of @ref ETH_Flush_Received_Frame */
00539
00540   uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
00541                                                              This parameter can be a value of @ref ETH_Transmit_Store_Forward */
00542
00543   uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
00544                                                              This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
00545
00546   uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.
00547                                                              This parameter can be a value of @ref ETH_Forward_Error_Frames */
00548
00549   uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
00550                                                              and length less than 64 bytes) including pad-bytes and CRC)
00551                                                              This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
00552
00553   uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
00554                                                              This parameter can be a value of @ref ETH_Receive_Threshold_Control */
00555
00556   uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
00557                                                              frame of Transmit data even before obtaining the status for the first frame.
00558                                                              This parameter can be a value of @ref ETH_Second_Frame_Operate */
00559
00560   uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.
00561                                                              This parameter can be a value of @ref ETH_Address_Aligned_Beats */
00562
00563   uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
00564                                                              This parameter can be a value of @ref ETH_Fixed_Burst */
00565
00566   uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
00567                                                              This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
00568
00569   uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
00570                                                              This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
00571
00572   uint32_t             EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.
00573                                                              This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
00574
00575   uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
00576                                                              This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
00577
00578   uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
00579                                                              This parameter can be a value of @ref ETH_DMA_Arbitration */
00580 } ETH_DMAInitTypeDef;
00581
00582
00583 /**
00584   * @brief  ETH DMA Descriptors data structure definition
00585   */
00586
00587 typedef struct
00588 {
00589   __IO uint32_t   Status;           /*!< Status */
00590
00591   uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
00592
00593   uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
00594
00595   uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
00596
00597   /*!< Enhanced ETHERNET DMA PTP Descriptors */
00598   uint32_t   ExtendedStatus;        /*!< Extended status for PTP receive descriptor */
00599
00600   uint32_t   Reserved1;             /*!< Reserved */
00601
00602   uint32_t   TimeStampLow;          /*!< Time Stamp Low value for transmit and receive */
00603
00604   uint32_t   TimeStampHigh;         /*!< Time Stamp High value for transmit and receive */
00605
00606 } ETH_DMADescTypeDef;
00607
00608
00609 /**
00610   * @brief  Received Frame Informations structure definition
00611   */
00612 typedef struct
00613 {
00614   ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */
00615
00616   ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */
00617
00618   uint32_t  SegCount;                    /*!< Segment count */
00619
00620   uint32_t length;                       /*!< Frame length */
00621
00622   uint32_t buffer;                       /*!< Frame buffer */
00623
00624 } ETH_DMARxFrameInfos;
00625
00626
00627 /**
00628   * @brief  ETH Handle Structure definition
00629   */
00630
00631 typedef struct
00632 {
00633   ETH_TypeDef                *Instance;     /*!< Register base address       */
00634
00635   ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */
00636
00637   uint32_t                   LinkStatus;    /*!< Ethernet link status        */
00638
00639   ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */
00640
00641   ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */
00642
00643   ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */
00644
00645   __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */
00646
00647   HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */
00648
00649 } ETH_HandleTypeDef;
00650
00651  /**
00652   * @}
00653   */
00654
00655 /* Exported constants --------------------------------------------------------*/
00656 /** @defgroup ETH_Exported_Constants ETH Exported Constants
00657   * @{
00658   */
00659
00660 /** @defgroup ETH_Buffers_setting ETH Buffers setting
00661   * @{
00662   */
00663 #define ETH_MAX_PACKET_SIZE    ((uint32_t)1524)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
00664 #define ETH_HEADER               ((uint32_t)14)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
00665 #define ETH_CRC                   ((uint32_t)4)    /*!< Ethernet CRC */
00666 #define ETH_EXTRA                 ((uint32_t)2)    /*!< Extra bytes in some cases */
00667 #define ETH_VLAN_TAG              ((uint32_t)4)    /*!< optional 802.1q VLAN Tag */
00668 #define ETH_MIN_ETH_PAYLOAD       ((uint32_t)46)    /*!< Minimum Ethernet payload size */
00669 #define ETH_MAX_ETH_PAYLOAD       ((uint32_t)1500)    /*!< Maximum Ethernet payload size */
00670 #define ETH_JUMBO_FRAME_PAYLOAD   ((uint32_t)9000)    /*!< Jumbo frame payload size */
00671
00672  /* Ethernet driver receive buffers are organized in a chained linked-list, when
00673     an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
00674     to the driver receive buffers memory.
00675
00676     Depending on the size of the received ethernet packet and the size of
00677     each ethernet driver receive buffer, the received packet can take one or more
00678     ethernet driver receive buffer.
00679
00680     In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
00681     and the total count of the driver receive buffers ETH_RXBUFNB.
00682
00683     The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
00684     example, they can be reconfigured in the application layer to fit the application
00685     needs */
00686
00687 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
00688    packet */
00689 #ifndef ETH_RX_BUF_SIZE
00690  #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE
00691 #endif
00692
00693 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
00694 #ifndef ETH_RXBUFNB
00695  #define ETH_RXBUFNB             ((uint32_t)5     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
00696 #endif
00697
00698
00699  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
00700     an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
00701     driver transmit buffers memory to the TxFIFO.
00702
00703     Depending on the size of the Ethernet packet to be transmitted and the size of
00704     each ethernet driver transmit buffer, the packet to be transmitted can take
00705     one or more ethernet driver transmit buffer.
00706
00707     In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
00708     and the total count of the driver transmit buffers ETH_TXBUFNB.
00709
00710     The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
00711     example, they can be reconfigured in the application layer to fit the application
00712     needs */
00713
00714 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
00715    packet */
00716 #ifndef ETH_TX_BUF_SIZE
00717  #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
00718 #endif
00719
00720 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
00721 #ifndef ETH_TXBUFNB
00722  #define ETH_TXBUFNB             ((uint32_t)5      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
00723 #endif
00724
00725  /**
00726   * @}
00727   */
00728
00729 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
00730   * @{
00731   */
00732
00733 /*
00734    DMA Tx Descriptor
00735   -----------------------------------------------------------------------------------------------
00736   TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
00737   -----------------------------------------------------------------------------------------------
00738   TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
00739   -----------------------------------------------------------------------------------------------
00740   TDES2 |                         Buffer1 Address [31:0]                                         |
00741   -----------------------------------------------------------------------------------------------
00742   TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
00743   -----------------------------------------------------------------------------------------------
00744 */
00745
00746 /**
00747   * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
00748   */
00749 #define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
00750 #define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
00751 #define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
00752 #define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
00753 #define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
00754 #define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
00755 #define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
00756 #define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
00757 #define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */
00758 #define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */
00759 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
00760 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
00761 #define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
00762 #define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
00763 #define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
00764 #define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
00765 #define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
00766 #define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
00767 #define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
00768 #define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
00769 #define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */
00770 #define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */
00771 #define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
00772 #define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
00773 #define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
00774 #define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
00775 #define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
00776 #define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
00777 #define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
00778
00779 /**
00780   * @brief  Bit definition of TDES1 register
00781   */
00782 #define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
00783 #define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
00784
00785 /**
00786   * @brief  Bit definition of TDES2 register
00787   */
00788 #define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
00789
00790 /**
00791   * @brief  Bit definition of TDES3 register
00792   */
00793 #define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
00794
00795   /*---------------------------------------------------------------------------------------------
00796   TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
00797   -----------------------------------------------------------------------------------------------
00798   TDES7 |                         Transmit Time Stamp High [31:0]                                |
00799   ----------------------------------------------------------------------------------------------*/
00800
00801 /* Bit definition of TDES6 register */
00802  #define ETH_DMAPTPTXDESC_TTSL  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp Low */
00803
00804 /* Bit definition of TDES7 register */
00805  #define ETH_DMAPTPTXDESC_TTSH  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp High */
00806
00807 /**
00808   * @}
00809   */
00810 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
00811   * @{
00812   */
00813
00814 /*
00815   DMA Rx Descriptor
00816   --------------------------------------------------------------------------------------------------------------------
00817   RDES0 | OWN(31) |                                             Status [30:0]                                          |
00818   ---------------------------------------------------------------------------------------------------------------------
00819   RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
00820   ---------------------------------------------------------------------------------------------------------------------
00821   RDES2 |                                       Buffer1 Address [31:0]                                                 |
00822   ---------------------------------------------------------------------------------------------------------------------
00823   RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
00824   ---------------------------------------------------------------------------------------------------------------------
00825 */
00826
00827 /**
00828   * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
00829   */
00830 #define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
00831 #define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
00832 #define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
00833 #define ETH_DMARXDESC_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
00834 #define ETH_DMARXDESC_DE          ((uint32_t)0x00004000)  /*!< Descriptor error: no more descriptors for receive frame  */
00835 #define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
00836 #define ETH_DMARXDESC_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
00837 #define ETH_DMARXDESC_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
00838 #define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
00839 #define ETH_DMARXDESC_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
00840 #define ETH_DMARXDESC_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */
00841 #define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */
00842 #define ETH_DMARXDESC_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
00843 #define ETH_DMARXDESC_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
00844 #define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
00845 #define ETH_DMARXDESC_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
00846 #define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
00847 #define ETH_DMARXDESC_CE          ((uint32_t)0x00000002)  /*!< CRC error */
00848 #define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
00849
00850 /**
00851   * @brief  Bit definition of RDES1 register
00852   */
00853 #define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
00854 #define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
00855 #define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
00856 #define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
00857 #define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
00858
00859 /**
00860   * @brief  Bit definition of RDES2 register
00861   */
00862 #define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
00863
00864 /**
00865   * @brief  Bit definition of RDES3 register
00866   */
00867 #define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
00868
00869 /*---------------------------------------------------------------------------------------------------------------------
00870   RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
00871   ---------------------------------------------------------------------------------------------------------------------
00872   RDES5 |                                            Reserved[31:0]                                                    |
00873   ---------------------------------------------------------------------------------------------------------------------
00874   RDES6 |                                       Receive Time Stamp Low [31:0]                                          |
00875   ---------------------------------------------------------------------------------------------------------------------
00876   RDES7 |                                       Receive Time Stamp High [31:0]                                         |
00877   --------------------------------------------------------------------------------------------------------------------*/
00878
00879 /* Bit definition of RDES4 register */
00880 #define ETH_DMAPTPRXDESC_PTPV     ((uint32_t)0x00002000)  /* PTP Version */
00881 #define ETH_DMAPTPRXDESC_PTPFT    ((uint32_t)0x00001000)  /* PTP Frame Type */
00882 #define ETH_DMAPTPRXDESC_PTPMT    ((uint32_t)0x00000F00)  /* PTP Message Type */
00883   #define ETH_DMAPTPRXDESC_PTPMT_SYNC                      ((uint32_t)0x00000100)  /* SYNC message (all clock types) */
00884   #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  ((uint32_t)0x00000200)  /* FollowUp message (all clock types) */
00885   #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  ((uint32_t)0x00000300)  /* DelayReq message (all clock types) */
00886   #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 ((uint32_t)0x00000400)  /* DelayResp message (all clock types) */
00887   #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        ((uint32_t)0x00000500)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
00888   #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          ((uint32_t)0x00000600)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */
00889   #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
00890 #define ETH_DMAPTPRXDESC_IPV6PR   ((uint32_t)0x00000080)  /* IPv6 Packet Received */
00891 #define ETH_DMAPTPRXDESC_IPV4PR   ((uint32_t)0x00000040)  /* IPv4 Packet Received */
00892 #define ETH_DMAPTPRXDESC_IPCB  ((uint32_t)0x00000020)  /* IP Checksum Bypassed */
00893 #define ETH_DMAPTPRXDESC_IPPE  ((uint32_t)0x00000010)  /* IP Payload Error */
00894 #define ETH_DMAPTPRXDESC_IPHE  ((uint32_t)0x00000008)  /* IP Header Error */
00895 #define ETH_DMAPTPRXDESC_IPPT  ((uint32_t)0x00000007)  /* IP Payload Type */
00896   #define ETH_DMAPTPRXDESC_IPPT_UDP                 ((uint32_t)0x00000001)  /* UDP payload encapsulated in the IP datagram */
00897   #define ETH_DMAPTPRXDESC_IPPT_TCP                 ((uint32_t)0x00000002)  /* TCP payload encapsulated in the IP datagram */
00898   #define ETH_DMAPTPRXDESC_IPPT_ICMP                ((uint32_t)0x00000003)  /* ICMP payload encapsulated in the IP datagram */
00899
00900 /* Bit definition of RDES6 register */
00901 #define ETH_DMAPTPRXDESC_RTSL  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp Low */
00902
00903 /* Bit definition of RDES7 register */
00904 #define ETH_DMAPTPRXDESC_RTSH  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp High */
00905 /**
00906   * @}
00907   */
00908  /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
00909   * @{
00910   */
00911 #define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001)
00912 #define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000)
00913
00914 /**
00915   * @}
00916   */
00917 /** @defgroup ETH_Speed ETH Speed
00918   * @{
00919   */
00920 #define ETH_SPEED_10M        ((uint32_t)0x00000000)
00921 #define ETH_SPEED_100M       ((uint32_t)0x00004000)
00922
00923 /**
00924   * @}
00925   */
00926 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
00927   * @{
00928   */
00929 #define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800)
00930 #define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000)
00931 /**
00932   * @}
00933   */
00934 /** @defgroup ETH_Rx_Mode ETH Rx Mode
00935   * @{
00936   */
00937 #define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000)
00938 #define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001)
00939 /**
00940   * @}
00941   */
00942
00943 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
00944   * @{
00945   */
00946 #define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000)
00947 #define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001)
00948 /**
00949   * @}
00950   */
00951
00952 /** @defgroup ETH_Media_Interface ETH Media Interface
00953   * @{
00954   */
00955 #define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000)
00956 #define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
00957 /**
00958   * @}
00959   */
00960
00961 /** @defgroup ETH_Watchdog ETH Watchdog
00962   * @{
00963   */
00964 #define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000)
00965 #define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000)
00966 /**
00967   * @}
00968   */
00969
00970 /** @defgroup ETH_Jabber ETH Jabber
00971   * @{
00972   */
00973 #define ETH_JABBER_ENABLE    ((uint32_t)0x00000000)
00974 #define ETH_JABBER_DISABLE   ((uint32_t)0x00400000)
00975 /**
00976   * @}
00977   */
00978
00979 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
00980   * @{
00981   */
00982 #define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
00983 #define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
00984 #define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
00985 #define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
00986 #define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
00987 #define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
00988 #define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
00989 #define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
00990 /**
00991   * @}
00992   */
00993
00994 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
00995   * @{
00996   */
00997 #define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000)
00998 #define ETH_CARRIERSENCE_DISABLE  ((uint32_t)0x00010000)
00999 /**
01000   * @}
01001   */
01002
01003 /** @defgroup ETH_Receive_Own ETH Receive Own
01004   * @{
01005   */
01006 #define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000)
01007 #define ETH_RECEIVEOWN_DISABLE    ((uint32_t)0x00002000)
01008 /**
01009   * @}
01010   */
01011
01012 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
01013   * @{
01014   */
01015 #define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000)
01016 #define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000)
01017 /**
01018   * @}
01019   */
01020
01021 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
01022   * @{
01023   */
01024 #define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400)
01025 #define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000)
01026 /**
01027   * @}
01028   */
01029
01030 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
01031   * @{
01032   */
01033 #define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000)
01034 #define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200)
01035 /**
01036   * @}
01037   */
01038
01039 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
01040   * @{
01041   */
01042 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080)
01043 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000)
01044 /**
01045   * @}
01046   */
01047
01048 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
01049   * @{
01050   */
01051 #define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000)
01052 #define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020)
01053 #define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040)
01054 #define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060)
01055 /**
01056   * @}
01057   */
01058
01059 /** @defgroup ETH_Deferral_Check ETH Deferral Check
01060   * @{
01061   */
01062 #define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010)
01063 #define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000)
01064 /**
01065   * @}
01066   */
01067
01068 /** @defgroup ETH_Receive_All ETH Receive All
01069   * @{
01070   */
01071 #define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000)
01072 #define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000)
01073 /**
01074   * @}
01075   */
01076
01077 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
01078   * @{
01079   */
01080 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200)
01081 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300)
01082 #define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000)
01083 /**
01084   * @}
01085   */
01086
01087 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
01088   * @{
01089   */
01090 #define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
01091 #define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
01092 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */
01093 /**
01094   * @}
01095   */
01096
01097 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
01098   * @{
01099   */
01100 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000)
01101 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020)
01102 /**
01103   * @}
01104   */
01105
01106 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
01107   * @{
01108   */
01109 #define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000)
01110 #define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008)
01111 /**
01112   * @}
01113   */
01114
01115 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
01116   * @{
01117   */
01118 #define ETH_PROMISCUOUS_MODE_ENABLE     ((uint32_t)0x00000001)
01119 #define ETH_PROMISCUOUS_MODE_DISABLE    ((uint32_t)0x00000000)
01120 /**
01121   * @}
01122   */
01123
01124 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
01125   * @{
01126   */
01127 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404)
01128 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004)
01129 #define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000)
01130 #define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010)
01131 /**
01132   * @}
01133   */
01134
01135 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
01136   * @{
01137   */
01138 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
01139 #define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002)
01140 #define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000)
01141 /**
01142   * @}
01143   */
01144
01145 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
01146   * @{
01147   */
01148 #define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000)
01149 #define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080)
01150 /**
01151   * @}
01152   */
01153
01154 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
01155   * @{
01156   */
01157 #define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
01158 #define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
01159 #define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
01160 #define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
01161 /**
01162   * @}
01163   */
01164
01165 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
01166   * @{
01167   */
01168 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008)
01169 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
01170 /**
01171   * @}
01172   */
01173
01174 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
01175   * @{
01176   */
01177 #define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004)
01178 #define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000)
01179 /**
01180   * @}
01181   */
01182
01183 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
01184   * @{
01185   */
01186 #define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002)
01187 #define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000)
01188 /**
01189   * @}
01190   */
01191
01192 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
01193   * @{
01194   */
01195 #define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000)
01196 #define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000)
01197 /**
01198   * @}
01199   */
01200
01201 /** @defgroup ETH_MAC_addresses ETH MAC addresses
01202   * @{
01203   */
01204 #define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000)
01205 #define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008)
01206 #define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010)
01207 #define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018)
01208 /**
01209   * @}
01210   */
01211
01212 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
01213   * @{
01214   */
01215 #define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000)
01216 #define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008)
01217 /**
01218   * @}
01219   */
01220
01221 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
01222   * @{
01223   */
01224 #define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
01225 #define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
01226 #define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
01227 #define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
01228 #define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
01229 #define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
01230 /**
01231   * @}
01232   */
01233
01234 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
01235   * @{
01236   */
01237 #define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
01238 #define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
01239 #define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
01240 #define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
01241 #define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
01242 #define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
01243 #define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
01244 #define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
01245 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
01246 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
01247 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
01248 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
01249 #define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
01250 #define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
01251 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
01252 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
01253 #define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
01254 #define ETH_MAC_READCONTROLLER_IDLE            ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
01255 #define ETH_MAC_READCONTROLLER_READING_DATA    ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
01256 #define ETH_MAC_READCONTROLLER_READING_STATUS  ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
01257 #define ETH_MAC_READCONTROLLER_FLUSHING       ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
01258 #define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
01259 #define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
01260 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
01261 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
01262 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
01263 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
01264 /**
01265   * @}
01266   */
01267
01268 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
01269   * @{
01270   */
01271 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000)
01272 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000)
01273 /**
01274   * @}
01275   */
01276
01277 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
01278   * @{
01279   */
01280 #define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000)
01281 #define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000)
01282 /**
01283   * @}
01284   */
01285
01286 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
01287   * @{
01288   */
01289 #define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000)
01290 #define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000)
01291 /**
01292   * @}
01293   */
01294
01295 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
01296   * @{
01297   */
01298 #define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000)
01299 #define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000)
01300 /**
01301   * @}
01302   */
01303
01304 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
01305   * @{
01306   */
01307 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
01308 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
01309 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
01310 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
01311 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
01312 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
01313 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
01314 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
01315 /**
01316   * @}
01317   */
01318
01319 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
01320   * @{
01321   */
01322 #define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080)
01323 #define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000)
01324 /**
01325   * @}
01326   */
01327
01328 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
01329   * @{
01330   */
01331 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040)
01332 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000)
01333 /**
01334   * @}
01335   */
01336
01337 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
01338   * @{
01339   */
01340 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
01341 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
01342 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
01343 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
01344 /**
01345   * @}
01346   */
01347
01348 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
01349   * @{
01350   */
01351 #define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004)
01352 #define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000)
01353 /**
01354   * @}
01355   */
01356
01357 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
01358   * @{
01359   */
01360 #define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000)
01361 #define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000)
01362 /**
01363   * @}
01364   */
01365
01366 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
01367   * @{
01368   */
01369 #define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000)
01370 #define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000)
01371 /**
01372   * @}
01373   */
01374
01375 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
01376   * @{
01377   */
01378 #define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
01379 #define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
01380 #define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
01381 #define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
01382 #define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
01383 #define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
01384 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
01385 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
01386 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
01387 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
01388 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
01389 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
01390 /**
01391   * @}
01392   */
01393
01394 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
01395   * @{
01396   */
01397 #define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
01398 #define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
01399 #define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
01400 #define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
01401 #define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
01402 #define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
01403 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
01404 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
01405 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
01406 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
01407 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
01408 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
01409 /**
01410   * @}
01411   */
01412
01413 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
01414   * @{
01415   */
01416 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              ((uint32_t)0x00000080)
01417 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             ((uint32_t)0x00000000)
01418 /**
01419   * @}
01420   */
01421
01422 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
01423   * @{
01424   */
01425 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000)
01426 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000)
01427 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000)
01428 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000)
01429 #define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002)
01430 /**
01431   * @}
01432   */
01433
01434 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
01435   * @{
01436   */
01437 #define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000)  /*!< Last Segment */
01438 #define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000)  /*!< First Segment */
01439 /**
01440   * @}
01441   */
01442
01443 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
01444   * @{
01445   */
01446 #define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
01447 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
01448 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
01449 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
01450 /**
01451   * @}
01452   */
01453
01454 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
01455   * @{
01456   */
01457 #define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
01458 #define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
01459 /**
01460   * @}
01461   */
01462
01463 /** @defgroup ETH_PMT_Flags ETH PMT Flags
01464   * @{
01465   */
01466 #define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Pointer Reset */
01467 #define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
01468 #define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
01469 /**
01470   * @}
01471   */
01472
01473 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
01474   * @{
01475   */
01476 #define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
01477 #define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
01478 #define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
01479 /**
01480   * @}
01481   */
01482
01483 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
01484   * @{
01485   */
01486 #define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
01487 #define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
01488 #define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
01489 /**
01490   * @}
01491   */
01492
01493 /** @defgroup ETH_MAC_Flags ETH MAC Flags
01494   * @{
01495   */
01496 #define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
01497 #define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
01498 #define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
01499 #define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
01500 #define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
01501 /**
01502   * @}
01503   */
01504
01505 /** @defgroup ETH_DMA_Flags ETH DMA Flags
01506   * @{
01507   */
01508 #define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
01509 #define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
01510 #define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
01511 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
01512 #define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000)  /*!< Error bits 0-write transfer, 1-read transfer */
01513 #define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
01514 #define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
01515 #define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
01516 #define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
01517 #define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
01518 #define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
01519 #define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
01520 #define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
01521 #define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
01522 #define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
01523 #define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
01524 #define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
01525 #define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
01526 #define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
01527 #define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
01528 #define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
01529 /**
01530   * @}
01531   */
01532
01533 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
01534   * @{
01535   */
01536 #define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
01537 #define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
01538 #define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
01539 #define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
01540 #define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
01541 /**
01542   * @}
01543   */
01544
01545 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
01546   * @{
01547   */
01548 #define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
01549 #define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
01550 #define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
01551 #define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
01552 #define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
01553 #define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
01554 #define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
01555 #define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
01556 #define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
01557 #define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
01558 #define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
01559 #define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
01560 #define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
01561 #define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
01562 #define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
01563 #define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
01564 #define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
01565 #define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
01566 /**
01567   * @}
01568   */
01569
01570 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
01571   * @{
01572   */
01573 #define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
01574 #define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
01575 #define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
01576 #define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
01577 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000)  /*!< Suspended - Tx Descriptor unavailable */
01578 #define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
01579
01580 /**
01581   * @}
01582   */
01583
01584
01585 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
01586   * @{
01587   */
01588 #define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
01589 #define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
01590 #define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
01591 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000)  /*!< Suspended - Rx Descriptor unavailable */
01592 #define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
01593 #define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000)  /*!< Running - queuing the receive frame into host memory */
01594
01595 /**
01596   * @}
01597   */
01598
01599 /** @defgroup ETH_DMA_overflow ETH DMA overflow
01600   * @{
01601   */
01602 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
01603 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
01604 /**
01605   * @}
01606   */
01607
01608 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
01609   * @{
01610   */
01611 #define ETH_EXTI_LINE_WAKEUP              ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the ETH EXTI Line */
01612
01613 /**
01614   * @}
01615   */
01616
01617 /**
01618   * @}
01619   */
01620
01621 /* Exported macro ------------------------------------------------------------*/
01622 /** @defgroup ETH_Exported_Macros ETH Exported Macros
01623  *  @brief macros to handle interrupts and specific clock configurations
01624  * @{
01625  */
01626
01627 /** @brief Reset ETH handle state
01628   * @param  __HANDLE__: specifies the ETH handle.
01629   * @retval None
01630   */
01631 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
01632
01633 /**
01634   * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
01635   * @param  __HANDLE__: ETH Handle
01636   * @param  __FLAG__: specifies the flag of TDES0 to check.
01637   * @retval the ETH_DMATxDescFlag (SET or RESET).
01638   */
01639 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
01640
01641 /**
01642   * @brief  Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
01643   * @param  __HANDLE__: ETH Handle
01644   * @param  __FLAG__: specifies the flag of RDES0 to check.
01645   * @retval the ETH_DMATxDescFlag (SET or RESET).
01646   */
01647 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
01648
01649 /**
01650   * @brief  Enables the specified DMA Rx Desc receive interrupt.
01651   * @param  __HANDLE__: ETH Handle
01652   * @retval None
01653   */
01654 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
01655
01656 /**
01657   * @brief  Disables the specified DMA Rx Desc receive interrupt.
01658   * @param  __HANDLE__: ETH Handle
01659   * @retval None
01660   */
01661 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
01662
01663 /**
01664   * @brief  Set the specified DMA Rx Desc Own bit.
01665   * @param  __HANDLE__: ETH Handle
01666   * @retval None
01667   */
01668 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
01669
01670 /**
01671   * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
01672   * @param  __HANDLE__: ETH Handle
01673   * @retval The Transmit descriptor collision counter value.
01674   */
01675 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
01676
01677 /**
01678   * @brief  Set the specified DMA Tx Desc Own bit.
01679   * @param  __HANDLE__: ETH Handle
01680   * @retval None
01681   */
01682 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
01683
01684 /**
01685   * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
01686   * @param  __HANDLE__: ETH Handle
01687   * @retval None
01688   */
01689 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
01690
01691 /**
01692   * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
01693   * @param  __HANDLE__: ETH Handle
01694   * @retval None
01695   */
01696 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
01697
01698 /**
01699   * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
01700   * @param  __HANDLE__: ETH Handle
01701   * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
01702   *   This parameter can be one of the following values:
01703   *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
01704   *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
01705   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
01706   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
01707   * @retval None
01708   */
01709 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
01710
01711 /**
01712   * @brief  Enables the DMA Tx Desc CRC.
01713   * @param  __HANDLE__: ETH Handle
01714   * @retval None
01715   */
01716 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
01717
01718 /**
01719   * @brief  Disables the DMA Tx Desc CRC.
01720   * @param  __HANDLE__: ETH Handle
01721   * @retval None
01722   */
01723 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
01724
01725 /**
01726   * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
01727   * @param  __HANDLE__: ETH Handle
01728   * @retval None
01729   */
01730 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
01731
01732 /**
01733   * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
01734   * @param  __HANDLE__: ETH Handle
01735   * @retval None
01736   */
01737 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
01738
01739 /**
01740  * @brief  Enables the specified ETHERNET MAC interrupts.
01741   * @param  __HANDLE__   : ETH Handle
01742   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01743   *   enabled or disabled.
01744   *   This parameter can be any combination of the following values:
01745   *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
01746   *     @arg ETH_MAC_IT_PMT : PMT interrupt
01747   * @retval None
01748   */
01749 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
01750
01751 /**
01752   * @brief  Disables the specified ETHERNET MAC interrupts.
01753   * @param  __HANDLE__   : ETH Handle
01754   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01755   *   enabled or disabled.
01756   *   This parameter can be any combination of the following values:
01757   *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
01758   *     @arg ETH_MAC_IT_PMT : PMT interrupt
01759   * @retval None
01760   */
01761 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
01762
01763 /**
01764   * @brief  Initiate a Pause Control Frame (Full-duplex only).
01765   * @param  __HANDLE__: ETH Handle
01766   * @retval None
01767   */
01768 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
01769
01770 /**
01771   * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
01772   * @param  __HANDLE__: ETH Handle
01773   * @retval The new state of flow control busy status bit (SET or RESET).
01774   */
01775 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
01776
01777 /**
01778   * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
01779   * @param  __HANDLE__: ETH Handle
01780   * @retval None
01781   */
01782 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
01783
01784 /**
01785   * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
01786   * @param  __HANDLE__: ETH Handle
01787   * @retval None
01788   */
01789 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
01790
01791 /**
01792   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
01793   * @param  __HANDLE__: ETH Handle
01794   * @param  __FLAG__: specifies the flag to check.
01795   *   This parameter can be one of the following values:
01796   *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
01797   *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
01798   *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag
01799   *     @arg ETH_MAC_FLAG_MMC  : MMC flag
01800   *     @arg ETH_MAC_FLAG_PMT  : PMT flag
01801   * @retval The state of ETHERNET MAC flag.
01802   */
01803 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
01804
01805 /**
01806   * @brief  Enables the specified ETHERNET DMA interrupts.
01807   * @param  __HANDLE__   : ETH Handle
01808   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01809   *   enabled @ref ETH_DMA_Interrupts
01810   * @retval None
01811   */
01812 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
01813
01814 /**
01815   * @brief  Disables the specified ETHERNET DMA interrupts.
01816   * @param  __HANDLE__   : ETH Handle
01817   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01818   *   disabled. @ref ETH_DMA_Interrupts
01819   * @retval None
01820   */
01821 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
01822
01823 /**
01824   * @brief  Clears the ETHERNET DMA IT pending bit.
01825   * @param  __HANDLE__   : ETH Handle
01826   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
01827   * @retval None
01828   */
01829 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
01830
01831 /**
01832   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01833 * @param  __HANDLE__: ETH Handle
01834   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
01835   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
01836   */
01837 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
01838
01839 /**
01840   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01841   * @param  __HANDLE__: ETH Handle
01842   * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
01843   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
01844   */
01845 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))
01846
01847 /**
01848   * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
01849   * @param  __HANDLE__: ETH Handle
01850   * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
01851   *   This parameter can be one of the following values:
01852   *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
01853   *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
01854   * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
01855   */
01856 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
01857
01858 /**
01859   * @brief  Set the DMA Receive status watchdog timer register value
01860   * @param  __HANDLE__: ETH Handle
01861   * @param  __VALUE__: DMA Receive status watchdog timer register value
01862   * @retval None
01863   */
01864 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
01865
01866 /**
01867   * @brief  Enables any unicast packet filtered by the MAC address
01868   *   recognition to be a wake-up frame.
01869   * @param  __HANDLE__: ETH Handle.
01870   * @retval None
01871   */
01872 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
01873
01874 /**
01875   * @brief  Disables any unicast packet filtered by the MAC address
01876   *   recognition to be a wake-up frame.
01877   * @param  __HANDLE__: ETH Handle.
01878   * @retval None
01879   */
01880 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
01881
01882 /**
01883   * @brief  Enables the MAC Wake-Up Frame Detection.
01884   * @param  __HANDLE__: ETH Handle.
01885   * @retval None
01886   */
01887 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
01888
01889 /**
01890   * @brief  Disables the MAC Wake-Up Frame Detection.
01891   * @param  __HANDLE__: ETH Handle.
01892   * @retval None
01893   */
01894 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
01895
01896 /**
01897   * @brief  Enables the MAC Magic Packet Detection.
01898   * @param  __HANDLE__: ETH Handle.
01899   * @retval None
01900   */
01901 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
01902
01903 /**
01904   * @brief  Disables the MAC Magic Packet Detection.
01905   * @param  __HANDLE__: ETH Handle.
01906   * @retval None
01907   */
01908 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
01909
01910 /**
01911   * @brief  Enables the MAC Power Down.
01912   * @param  __HANDLE__: ETH Handle
01913   * @retval None
01914   */
01915 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
01916
01917 /**
01918   * @brief  Disables the MAC Power Down.
01919   * @param  __HANDLE__: ETH Handle
01920   * @retval None
01921   */
01922 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
01923
01924 /**
01925   * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
01926   * @param  __HANDLE__: ETH Handle.
01927   * @param  __FLAG__: specifies the flag to check.
01928   *   This parameter can be one of the following values:
01929   *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
01930   *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
01931   *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
01932   * @retval The new state of ETHERNET PMT Flag (SET or RESET).
01933   */
01934 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
01935
01936 /**
01937   * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
01938   * @param   __HANDLE__: ETH Handle.
01939   * @retval None
01940   */
01941 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
01942
01943 /**
01944   * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
01945   * @param  __HANDLE__: ETH Handle.
01946   * @retval None
01947   */
01948 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
01949                                                                           (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
01950
01951 /**
01952   * @brief  Enables the MMC Counter Freeze.
01953   * @param  __HANDLE__: ETH Handle.
01954   * @retval None
01955   */
01956 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
01957
01958 /**
01959   * @brief  Disables the MMC Counter Freeze.
01960   * @param  __HANDLE__: ETH Handle.
01961   * @retval None
01962   */
01963 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
01964
01965 /**
01966   * @brief  Enables the MMC Reset On Read.
01967   * @param  __HANDLE__: ETH Handle.
01968   * @retval None
01969   */
01970 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
01971
01972 /**
01973   * @brief  Disables the MMC Reset On Read.
01974   * @param  __HANDLE__: ETH Handle.
01975   * @retval None
01976   */
01977 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
01978
01979 /**
01980   * @brief  Enables the MMC Counter Stop Rollover.
01981   * @param  __HANDLE__: ETH Handle.
01982   * @retval None
01983   */
01984 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
01985
01986 /**
01987   * @brief  Disables the MMC Counter Stop Rollover.
01988   * @param  __HANDLE__: ETH Handle.
01989   * @retval None
01990   */
01991 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
01992
01993 /**
01994   * @brief  Resets the MMC Counters.
01995   * @param   __HANDLE__: ETH Handle.
01996   * @retval None
01997   */
01998 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
01999
02000 /**
02001   * @brief  Enables the specified ETHERNET MMC Rx interrupts.
02002   * @param   __HANDLE__: ETH Handle.
02003   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
02004   *   This parameter can be one of the following values:
02005   *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
02006   *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
02007   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
02008   * @retval None
02009   */
02010 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
02011 /**
02012   * @brief  Disables the specified ETHERNET MMC Rx interrupts.
02013   * @param   __HANDLE__: ETH Handle.
02014   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
02015   *   This parameter can be one of the following values:
02016   *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
02017   *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
02018   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
02019   * @retval None
02020   */
02021 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
02022 /**
02023   * @brief  Enables the specified ETHERNET MMC Tx interrupts.
02024   * @param   __HANDLE__: ETH Handle.
02025   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
02026   *   This parameter can be one of the following values:
02027   *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
02028   *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
02029   *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
02030   * @retval None
02031   */
02032 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
02033
02034 /**
02035   * @brief  Disables the specified ETHERNET MMC Tx interrupts.
02036   * @param   __HANDLE__: ETH Handle.
02037   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
02038   *   This parameter can be one of the following values:
02039   *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
02040   *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
02041   *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
02042   * @retval None
02043   */
02044 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
02045
02046 /**
02047   * @brief  Enables the ETH External interrupt line.
02048   * @retval None
02049   */
02050 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
02051
02052 /**
02053   * @brief  Disables the ETH External interrupt line.
02054   * @retval None
02055   */
02056 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
02057
02058 /**
02059   * @brief Enable event on ETH External event line.
02060   * @retval None.
02061   */
02062 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()  EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
02063
02064 /**
02065   * @brief Disable event on ETH External event line
02066   * @retval None.
02067   */
02068 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
02069
02070 /**
02071   * @brief  Get flag of the ETH External interrupt line.
02072   * @retval None
02073   */
02074 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
02075
02076 /**
02077   * @brief  Clear flag of the ETH External interrupt line.
02078   * @retval None
02079   */
02080 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
02081
02082 /**
02083   * @brief  Enables rising edge trigger to the ETH External interrupt line.
02084   * @retval None
02085   */
02086 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
02087
02088 /**
02089   * @brief  Disables the rising edge trigger to the ETH External interrupt line.
02090   * @retval None
02091   */
02092 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
02093
02094 /**
02095   * @brief  Enables falling edge trigger to the ETH External interrupt line.
02096   * @retval None
02097   */
02098 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
02099
02100 /**
02101   * @brief  Disables falling edge trigger to the ETH External interrupt line.
02102   * @retval None
02103   */
02104 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
02105
02106 /**
02107   * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.
02108   * @retval None
02109   */
02110 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
02111                                                               EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
02112
02113 /**
02114   * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.
02115   * @retval None
02116   */
02117 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
02118                                                                EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
02119
02120 /**
02121   * @brief Generate a Software interrupt on selected EXTI line.
02122   * @retval None.
02123   */
02124 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()                  EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
02125
02126 /**
02127   * @}
02128   */
02129 /* Exported functions --------------------------------------------------------*/
02130
02131 /** @addtogroup ETH_Exported_Functions
02132   * @{
02133   */
02134
02135 /* Initialization and de-initialization functions  ****************************/
02136
02137 /** @addtogroup ETH_Exported_Functions_Group1
02138   * @{
02139   */
02140 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
02141 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
02142 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
02143 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
02144 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
02145 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
02146
02147 /**
02148   * @}
02149   */
02150 /* IO operation functions  ****************************************************/
02151
02152 /** @addtogroup ETH_Exported_Functions_Group2
02153   * @{
02154   */
02155 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
02156 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
02157 /* Communication with PHY functions*/
02158 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
02159 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
02160 /* Non-Blocking mode: Interrupt */
02161 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
02162 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
02163 /* Callback in non blocking modes (Interrupt) */
02164 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
02165 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
02166 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
02167 /**
02168   * @}
02169   */
02170
02171 /* Peripheral Control functions  **********************************************/
02172
02173 /** @addtogroup ETH_Exported_Functions_Group3
02174   * @{
02175   */
02176
02177 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
02178 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
02179 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
02180 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
02181 /**
02182   * @}
02183   */
02184
02185 /* Peripheral State functions  ************************************************/
02186
02187 /** @addtogroup ETH_Exported_Functions_Group4
02188   * @{
02189   */
02190 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
02191 /**
02192   * @}
02193   */
02194
02195 /**
02196   * @}
02197   */
02198
02199 /**
02200   * @}
02201   */
02202
02203 /**
02204   * @}
02205   */
02206 #ifdef __cplusplus
02207 }
02208 #endif
02209
02210 #endif /* __STM32F7xx_HAL_ETH_H */
02211
02212
02213
02214 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash.c Source File

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stm32f7xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the internal FLASH memory:
00010   *           + Program operations functions
00011   *           + Memory Control functions
00012   *           + Peripheral Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### FLASH peripheral features #####
00017   ==============================================================================
00018
00019   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00020        to the Flash memory. It implements the erase and program Flash memory operations
00021        and the read and write protection mechanisms.
00022
00023   [..] The Flash memory interface accelerates code execution with a system of instruction
00024        prefetch and cache lines.
00025
00026   [..] The FLASH main features are:
00027       (+) Flash memory read operations
00028       (+) Flash memory program/erase operations
00029       (+) Read / write protections
00030       (+) Prefetch on I-Code
00031       (+) 64 cache lines of 128 bits on I-Code
00032       (+) 8 cache lines of 128 bits on D-Code
00033
00034                      ##### How to use this driver #####
00035   ==============================================================================
00036     [..]
00037       This driver provides functions and macros to configure and program the FLASH
00038       memory of all STM32F7xx devices.
00039
00040       (#) FLASH Memory IO Programming functions:
00041            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00042                 HAL_FLASH_Lock() functions
00043            (++) Program functions: byte, half word, word and double word
00044            (++) There Two modes of programming :
00045             (+++) Polling mode using HAL_FLASH_Program() function
00046             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00047
00048       (#) Interrupts and flags management functions :
00049            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00050            (++) Wait for last FLASH operation according to its status
00051            (++) Get error flag status by calling HAL_SetErrorCode()
00052     [..]
00053       In addition to these functions, this driver includes a set of macros allowing
00054       to handle the following operations:
00055        (+) Set the latency
00056        (+) Enable/Disable the prefetch buffer
00057        (+) Enable/Disable the Instruction cache and the Data cache
00058        (+) Reset the Instruction cache and the Data cache
00059        (+) Enable/Disable the FLASH interrupts
00060        (+) Monitor the FLASH flags status
00061     [..]
00062         (@) For any Flash memory program operation (erase or program), the CPU clock frequency
00063         (HCLK) must be at least 1MHz.
00064         (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
00065             a Flash memory operation.
00066     (@) Any attempt to read the Flash memory while it is being written or erased, causes the
00067             bus to stall. Read operations are processed correctly once the program operation has
00068                 completed. This means that code or data fetches cannot be performed while a write/erase
00069                 operation is ongoing.
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32f7xx_hal.h"
00104
00105 /** @addtogroup STM32F7xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup FLASH FLASH
00110   * @brief FLASH HAL module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_FLASH_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @addtogroup FLASH_Private_Constants
00119   * @{
00120   */
00121 #define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
00122 #define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */
00123 /**
00124   * @}
00125   */
00126 /* Private macro -------------------------------------------------------------*/
00127 /* Private variables ---------------------------------------------------------*/
00128 /** @addtogroup FLASH_Private_Variables
00129   * @{
00130   */
00131 /* Variable used for Erase sectors under interruption */
00132 FLASH_ProcessTypeDef pFlash;
00133 /**
00134   * @}
00135   */
00136
00137 /* Private function prototypes -----------------------------------------------*/
00138 /** @addtogroup FLASH_Private_Functions
00139   * @{
00140   */
00141 /* Program operations */
00142 static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
00143 static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
00144 static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
00145 static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
00146 static void   FLASH_SetErrorCode(void);
00147
00148 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported functions --------------------------------------------------------*/
00154 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00155   * @{
00156   */
00157
00158 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00159  *  @brief   Programming operation functions
00160  *
00161 @verbatim
00162  ===============================================================================
00163                   ##### Programming operation functions #####
00164  ===============================================================================
00165     [..]
00166     This subsection provides a set of functions allowing to manage the FLASH
00167     program operations.
00168
00169 @endverbatim
00170   * @{
00171   */
00172
00173 /**
00174   * @brief  Program byte, halfword, word or double word at a specified address
00175   * @param  TypeProgram:  Indicate the way to program at a specified address.
00176   *                           This parameter can be a value of @ref FLASH_Type_Program
00177   * @param  Address:  specifies the address to be programmed.
00178   * @param  Data: specifies the data to be programmed
00179   *
00180   * @retval HAL_StatusTypeDef HAL Status
00181   */
00182 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00183 {
00184   HAL_StatusTypeDef status = HAL_ERROR;
00185
00186   /* Process Locked */
00187   __HAL_LOCK(&pFlash);
00188
00189   /* Check the parameters */
00190   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00191
00192   /* Wait for last operation to be completed */
00193   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00194
00195   if(status == HAL_OK)
00196   {
00197     switch(TypeProgram)
00198     {
00199       case FLASH_TYPEPROGRAM_BYTE :
00200       {
00201         /*Program byte (8-bit) at a specified address.*/
00202         FLASH_Program_Byte(Address, (uint8_t) Data);
00203         break;
00204       }
00205
00206       case FLASH_TYPEPROGRAM_HALFWORD :
00207       {
00208         /*Program halfword (16-bit) at a specified address.*/
00209         FLASH_Program_HalfWord(Address, (uint16_t) Data);
00210         break;
00211       }
00212
00213       case FLASH_TYPEPROGRAM_WORD :
00214       {
00215         /*Program word (32-bit) at a specified address.*/
00216         FLASH_Program_Word(Address, (uint32_t) Data);
00217         break;
00218       }
00219
00220       case FLASH_TYPEPROGRAM_DOUBLEWORD :
00221       {
00222         /*Program double word (64-bit) at a specified address.*/
00223         FLASH_Program_DoubleWord(Address, Data);
00224         break;
00225       }
00226       default :
00227         break;
00228     }
00229     /* Wait for last operation to be completed */
00230     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00231
00232     /* If the program operation is completed, disable the PG Bit */
00233     FLASH->CR &= (~FLASH_CR_PG);
00234   }
00235
00236   /* Process Unlocked */
00237   __HAL_UNLOCK(&pFlash);
00238
00239   return status;
00240 }
00241
00242 /**
00243   * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
00244   * @param  TypeProgram:  Indicate the way to program at a specified address.
00245   *                           This parameter can be a value of @ref FLASH_Type_Program
00246   * @param  Address:  specifies the address to be programmed.
00247   * @param  Data: specifies the data to be programmed
00248   *
00249   * @retval HAL Status
00250   */
00251 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00252 {
00253   HAL_StatusTypeDef status = HAL_OK;
00254
00255   /* Process Locked */
00256   __HAL_LOCK(&pFlash);
00257
00258   /* Check the parameters */
00259   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00260
00261   /* Enable End of FLASH Operation interrupt */
00262   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
00263
00264   /* Enable Error source interrupt */
00265   __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
00266
00267   /* Clear pending flags (if any) */
00268   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
00269                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
00270
00271   pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
00272   pFlash.Address = Address;
00273
00274   switch(TypeProgram)
00275   {
00276     case FLASH_TYPEPROGRAM_BYTE :
00277     {
00278       /*Program byte (8-bit) at a specified address.*/
00279       FLASH_Program_Byte(Address, (uint8_t) Data);
00280       break;
00281     }
00282
00283     case FLASH_TYPEPROGRAM_HALFWORD :
00284     {
00285       /*Program halfword (16-bit) at a specified address.*/
00286       FLASH_Program_HalfWord(Address, (uint16_t) Data);
00287       break;
00288     }
00289
00290     case FLASH_TYPEPROGRAM_WORD :
00291     {
00292       /*Program word (32-bit) at a specified address.*/
00293       FLASH_Program_Word(Address, (uint32_t) Data);
00294       break;
00295     }
00296
00297     case FLASH_TYPEPROGRAM_DOUBLEWORD :
00298     {
00299       /*Program double word (64-bit) at a specified address.*/
00300       FLASH_Program_DoubleWord(Address, Data);
00301       break;
00302     }
00303     default :
00304       break;
00305   }
00306   return status;
00307 }
00308
00309 /**
00310   * @brief This function handles FLASH interrupt request.
00311   * @retval None
00312   */
00313 void HAL_FLASH_IRQHandler(void)
00314 {
00315   uint32_t temp = 0;
00316
00317   /* If the program operation is completed, disable the PG Bit */
00318   FLASH->CR &= (~FLASH_CR_PG);
00319
00320   /* If the erase operation is completed, disable the SER Bit */
00321   FLASH->CR &= (~FLASH_CR_SER);
00322   FLASH->CR &= SECTOR_MASK;
00323
00324   /* if the erase operation is completed, disable the MER Bit */
00325   FLASH->CR &= (~FLASH_MER_BIT);
00326
00327   /* Check FLASH End of Operation flag  */
00328   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
00329   {
00330     switch (pFlash.ProcedureOnGoing)
00331     {
00332       case FLASH_PROC_SECTERASE :
00333       {
00334         /* Nb of sector to erased can be decreased */
00335         pFlash.NbSectorsToErase--;
00336
00337         /* Check if there are still sectors to erase */
00338         if(pFlash.NbSectorsToErase != 0)
00339         {
00340           temp = pFlash.Sector;
00341           /* Indicate user which sector has been erased */
00342           HAL_FLASH_EndOfOperationCallback(temp);
00343
00344           /* Clear pending flags (if any) */
00345           __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00346
00347           /* Increment sector number */
00348           temp = ++pFlash.Sector;
00349           FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
00350         }
00351         else
00352         {
00353           /* No more sectors to Erase, user callback can be called.*/
00354           /* Reset Sector and stop Erase sectors procedure */
00355           pFlash.Sector = temp = 0xFFFFFFFF;
00356           /* FLASH EOP interrupt user callback */
00357           HAL_FLASH_EndOfOperationCallback(temp);
00358           /* Sector Erase procedure is completed */
00359           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00360           /* Clear FLASH End of Operation pending bit */
00361           __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00362         }
00363         break;
00364       }
00365
00366       case FLASH_PROC_MASSERASE :
00367       {
00368         /* MassErase ended. Return the selected bank : in this product we don't have Banks */
00369         /* FLASH EOP interrupt user callback */
00370         HAL_FLASH_EndOfOperationCallback(0);
00371         /* MAss Erase procedure is completed */
00372         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00373         /* Clear FLASH End of Operation pending bit */
00374         __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00375         break;
00376       }
00377
00378       case FLASH_PROC_PROGRAM :
00379       {
00380         /*Program ended. Return the selected address*/
00381         /* FLASH EOP interrupt user callback */
00382         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00383         /* Programming procedure is completed */
00384         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00385         /* Clear FLASH End of Operation pending bit */
00386         __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00387         break;
00388       }
00389       default :
00390         break;
00391     }
00392   }
00393
00394   /* Check FLASH operation error flags */
00395   if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR  | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)
00396   {
00397     switch (pFlash.ProcedureOnGoing)
00398     {
00399       case FLASH_PROC_SECTERASE :
00400       {
00401         /* return the faulty sector */
00402         temp = pFlash.Sector;
00403         pFlash.Sector = 0xFFFFFFFF;
00404         break;
00405       }
00406       case FLASH_PROC_MASSERASE :
00407       {
00408         /* No return in case of Mass Erase */
00409         temp = 0;
00410         break;
00411       }
00412       case FLASH_PROC_PROGRAM :
00413       {
00414         /*return the faulty address*/
00415         temp = pFlash.Address;
00416         break;
00417       }
00418     default :
00419       break;
00420     }
00421     /*Save the Error code*/
00422     FLASH_SetErrorCode();
00423
00424     /* FLASH error interrupt user callback */
00425     HAL_FLASH_OperationErrorCallback(temp);
00426     /* Clear FLASH error pending bits */
00427     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR  | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR );
00428
00429     /*Stop the procedure ongoing */
00430     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00431   }
00432
00433   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00434   {
00435     /* Disable End of FLASH Operation interrupt */
00436     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
00437
00438     /* Disable Error source interrupt */
00439     __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
00440
00441     /* Process Unlocked */
00442     __HAL_UNLOCK(&pFlash);
00443   }
00444
00445 }
00446
00447 /**
00448   * @brief  FLASH end of operation interrupt callback
00449   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00450   *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
00451   *                                  all the selected sectors have been erased)
00452   *                 - Program      : Address which was selected for data program
00453   *                 - Mass Erase   : No return value expected
00454   * @retval None
00455   */
00456 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00457 {
00458   /* Prevent unused argument(s) compilation warning */
00459 __IO uint32_t tmpreg = 0x00;
00460   UNUSED(tmpreg);
00461   /* NOTE : This function Should not be modified, when the callback is needed,
00462   the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00463   */
00464 }
00465
00466 /**
00467   * @brief  FLASH operation error interrupt callback
00468   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00469   *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
00470   *                                  all the selected sectors have been erased)
00471   *                 - Program      : Address which was selected for data program
00472   *                 - Mass Erase   : No return value expected
00473   * @retval None
00474   */
00475 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00476 {
00477   /* Prevent unused argument(s) compilation warning */
00478 __IO uint32_t tmpreg = 0x00;
00479   UNUSED(tmpreg);
00480   /* NOTE : This function Should not be modified, when the callback is needed,
00481   the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00482    */
00483 }
00484
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00490  *  @brief   management functions
00491  *
00492 @verbatim
00493  ===============================================================================
00494                       ##### Peripheral Control functions #####
00495  ===============================================================================
00496     [..]
00497     This subsection provides a set of functions allowing to control the FLASH
00498     memory operations.
00499
00500 @endverbatim
00501   * @{
00502   */
00503
00504 /**
00505   * @brief  Unlock the FLASH control register access
00506   * @retval HAL Status
00507   */
00508 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00509 {
00510   if((FLASH->CR & FLASH_CR_LOCK) != RESET)
00511   {
00512     /* Authorize the FLASH Registers access */
00513     FLASH->KEYR = FLASH_KEY1;
00514     FLASH->KEYR = FLASH_KEY2;
00515   }
00516   else
00517   {
00518     return HAL_ERROR;
00519   }
00520
00521   return HAL_OK;
00522 }
00523
00524 /**
00525   * @brief  Locks the FLASH control register access
00526   * @retval HAL Status
00527   */
00528 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00529 {
00530   /* Set the LOCK Bit to lock the FLASH Registers access */
00531   FLASH->CR |= FLASH_CR_LOCK;
00532
00533   return HAL_OK;
00534 }
00535
00536 /**
00537   * @brief  Unlock the FLASH Option Control Registers access.
00538   * @retval HAL Status
00539   */
00540 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00541 {
00542   if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
00543   {
00544     /* Authorizes the Option Byte register programming */
00545     FLASH->OPTKEYR = FLASH_OPT_KEY1;
00546     FLASH->OPTKEYR = FLASH_OPT_KEY2;
00547   }
00548   else
00549   {
00550     return HAL_ERROR;
00551   }
00552
00553   return HAL_OK;
00554 }
00555
00556 /**
00557   * @brief  Lock the FLASH Option Control Registers access.
00558   * @retval HAL Status
00559   */
00560 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00561 {
00562   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00563   FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
00564
00565   return HAL_OK;
00566 }
00567
00568 /**
00569   * @brief  Launch the option byte loading.
00570   * @retval HAL Status
00571   */
00572 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00573 {
00574   /* Set the OPTSTRT bit in OPTCR register */
00575   FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
00576
00577   /* Wait for last operation to be completed */
00578   return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
00579 }
00580
00581 /**
00582   * @}
00583   */
00584
00585 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00586  *  @brief   Peripheral Errors functions
00587  *
00588 @verbatim
00589  ===============================================================================
00590                 ##### Peripheral Errors functions #####
00591  ===============================================================================
00592     [..]
00593     This subsection permits to get in run-time Errors of the FLASH peripheral.
00594
00595 @endverbatim
00596   * @{
00597   */
00598
00599 /**
00600   * @brief  Get the specific FLASH error flag.
00601   * @retval FLASH_ErrorCode: The returned value can be:
00602   *            @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag
00603   *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
00604   *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
00605   *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag
00606   *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
00607   */
00608 uint32_t HAL_FLASH_GetError(void)
00609 {
00610    return pFlash.ErrorCode;
00611 }
00612
00613 /**
00614   * @}
00615   */
00616
00617 /**
00618   * @brief  Wait for a FLASH operation to complete.
00619   * @param  Timeout: maximum flash operationtimeout
00620   * @retval HAL Status
00621   */
00622 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00623 {
00624   uint32_t tickstart = 0;
00625
00626   /* Clear Error Code */
00627   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00628
00629   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00630      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00631      flag will be set */
00632   /* Get tick */
00633   tickstart = HAL_GetTick();
00634
00635   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
00636   {
00637     if(Timeout != HAL_MAX_DELAY)
00638     {
00639       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00640       {
00641         return HAL_TIMEOUT;
00642       }
00643     }
00644   }
00645
00646   if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
00647                            FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)
00648   {
00649     /*Save the error code*/
00650     FLASH_SetErrorCode();
00651     return HAL_ERROR;
00652   }
00653
00654   /* If there is an error flag set */
00655   return HAL_OK;
00656
00657 }
00658
00659 /**
00660   * @brief  Program a double word (64-bit) at a specified address.
00661   * @note   This function must be used when the device voltage range is from
00662   *         2.7V to 3.6V and an External Vpp is present.
00663   *
00664   * @note   If an erase and a program operations are requested simultaneously,
00665   *         the erase operation is performed before the program one.
00666   *
00667   * @param  Address: specifies the address to be programmed.
00668   * @param  Data: specifies the data to be programmed.
00669   * @retval None
00670   */
00671 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
00672 {
00673   /* Check the parameters */
00674   assert_param(IS_FLASH_ADDRESS(Address));
00675
00676   /* If the previous operation is completed, proceed to program the new data */
00677   FLASH->CR &= CR_PSIZE_MASK;
00678   FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
00679   FLASH->CR |= FLASH_CR_PG;
00680
00681   *(__IO uint64_t*)Address = Data;
00682
00683   /* Data synchronous Barrier (DSB) Just after the write operation
00684      This will force the CPU to respect the sequence of instruction (no optimization).*/
00685   __DSB();
00686 }
00687
00688
00689 /**
00690   * @brief  Program word (32-bit) at a specified address.
00691   * @note   This function must be used when the device voltage range is from
00692   *         2.7V to 3.6V.
00693   *
00694   * @note   If an erase and a program operations are requested simultaneously,
00695   *         the erase operation is performed before the program one.
00696   *
00697   * @param  Address: specifies the address to be programmed.
00698   * @param  Data: specifies the data to be programmed.
00699   * @retval None
00700   */
00701 static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
00702 {
00703   /* Check the parameters */
00704   assert_param(IS_FLASH_ADDRESS(Address));
00705
00706   /* If the previous operation is completed, proceed to program the new data */
00707   FLASH->CR &= CR_PSIZE_MASK;
00708   FLASH->CR |= FLASH_PSIZE_WORD;
00709   FLASH->CR |= FLASH_CR_PG;
00710
00711   *(__IO uint32_t*)Address = Data;
00712
00713   /* Data synchronous Barrier (DSB) Just after the write operation
00714      This will force the CPU to respect the sequence of instruction (no optimization).*/
00715   __DSB();
00716 }
00717
00718 /**
00719   * @brief  Program a half-word (16-bit) at a specified address.
00720   * @note   This function must be used when the device voltage range is from
00721   *         2.7V to 3.6V.
00722   *
00723   * @note   If an erase and a program operations are requested simultaneously,
00724   *         the erase operation is performed before the program one.
00725   *
00726   * @param  Address: specifies the address to be programmed.
00727   * @param  Data: specifies the data to be programmed.
00728   * @retval None
00729   */
00730 static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
00731 {
00732   /* Check the parameters */
00733   assert_param(IS_FLASH_ADDRESS(Address));
00734
00735   /* If the previous operation is completed, proceed to program the new data */
00736   FLASH->CR &= CR_PSIZE_MASK;
00737   FLASH->CR |= FLASH_PSIZE_HALF_WORD;
00738   FLASH->CR |= FLASH_CR_PG;
00739
00740   *(__IO uint16_t*)Address = Data;
00741
00742   /* Data synchronous Barrier (DSB) Just after the write operation
00743      This will force the CPU to respect the sequence of instruction (no optimization).*/
00744   __DSB();
00745
00746 }
00747
00748 /**
00749   * @brief  Program byte (8-bit) at a specified address.
00750   * @note   This function must be used when the device voltage range is from
00751   *         2.7V to 3.6V.
00752   *
00753   * @note   If an erase and a program operations are requested simultaneously,
00754   *         the erase operation is performed before the program one.
00755   *
00756   * @param  Address: specifies the address to be programmed.
00757   * @param  Data: specifies the data to be programmed.
00758   * @retval None
00759   */
00760 static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
00761 {
00762   /* Check the parameters */
00763   assert_param(IS_FLASH_ADDRESS(Address));
00764
00765   /* If the previous operation is completed, proceed to program the new data */
00766   FLASH->CR &= CR_PSIZE_MASK;
00767   FLASH->CR |= FLASH_PSIZE_BYTE;
00768   FLASH->CR |= FLASH_CR_PG;
00769
00770   *(__IO uint8_t*)Address = Data;
00771
00772   /* Data synchronous Barrier (DSB) Just after the write operation
00773      This will force the CPU to respect the sequence of instruction (no optimization).*/
00774   __DSB();
00775 }
00776
00777 /**
00778   * @brief  Set the specific FLASH error flag.
00779   * @retval None
00780   */
00781 static void FLASH_SetErrorCode(void)
00782 {
00783   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
00784   {
00785    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
00786   }
00787
00788   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
00789   {
00790    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
00791   }
00792
00793   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
00794   {
00795     pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
00796   }
00797
00798   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)
00799   {
00800     pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
00801   }
00802
00803   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
00804   {
00805     pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
00806   }
00807 }
00808
00809 /**
00810   * @}
00811   */
00812
00813 #endif /* HAL_FLASH_MODULE_ENABLED */
00814
00815 /**
00816   * @}
00817   */
00818
00819 /**
00820   * @}
00821   */
00822
00823 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash.h Source File

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stm32f7xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of FLASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_FLASH_H
00040 #define __STM32F7xx_HAL_FLASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASH
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Procedure structure definition
00064   */
00065 typedef enum
00066 {
00067   FLASH_PROC_NONE = 0,
00068   FLASH_PROC_SECTERASE,
00069   FLASH_PROC_MASSERASE,
00070   FLASH_PROC_PROGRAM
00071 } FLASH_ProcedureTypeDef;
00072
00073
00074 /**
00075   * @brief  FLASH handle Structure definition
00076   */
00077 typedef struct
00078 {
00079   __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /* Internal variable to indicate which procedure is ongoing or not in IT context */
00080
00081   __IO uint32_t               NbSectorsToErase;   /* Internal variable to save the remaining sectors to erase in IT context        */
00082
00083   __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context     */
00084
00085   __IO uint32_t               Sector;             /* Internal variable to define the current sector which is erasing               */
00086
00087   __IO uint32_t               Address;            /* Internal variable to save address selected for program                        */
00088
00089   HAL_LockTypeDef             Lock;               /* FLASH locking object                                                          */
00090
00091   __IO uint32_t               ErrorCode;          /* FLASH error code                                                              */
00092
00093 }FLASH_ProcessTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00101   * @{
00102   */
00103
00104 /** @defgroup FLASH_Error_Code FLASH Error Code
00105   * @brief    FLASH Error Code
00106   * @{
00107   */
00108 #define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000)    /*!< No error                      */
00109 #define HAL_FLASH_ERROR_ERS          ((uint32_t)0x00000002)    /*!< Programming Sequence error    */
00110 #define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004)    /*!< Programming Parallelism error */
00111 #define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008)    /*!< Programming Alignment error   */
00112 #define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010)    /*!< Write protection error        */
00113 #define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020)    /*!< Operation Error               */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup FLASH_Type_Program FLASH Type Program
00119   * @{
00120   */
00121 #define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00)  /*!< Program byte (8-bit) at a specified address           */
00122 #define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01)  /*!< Program a half-word (16-bit) at a specified address   */
00123 #define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02)  /*!< Program a word (32-bit) at a specified address        */
00124 #define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03)  /*!< Program a double word (64-bit) at a specified address */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup FLASH_Flag_definition FLASH Flag definition
00130   * @brief Flag definition
00131   * @{
00132   */
00133 #define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
00134 #define FLASH_FLAG_OPERR               FLASH_SR_OPERR          /*!< FLASH operation Error flag                */
00135 #define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
00136 #define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
00137 #define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
00138 #define FLASH_FLAG_ERSERR              FLASH_SR_ERSERR         /*!< FLASH Erasing Sequence error flag         */
00139 #define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
00145   * @brief FLASH Interrupt definition
00146   * @{
00147   */
00148 #define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
00149 #define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source                  */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
00155   * @{
00156   */
00157 #define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
00158 #define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)
00159 #define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)
00160 #define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)
00161 #define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup FLASH_Keys FLASH Keys
00167   * @{
00168   */
00169 #define FLASH_KEY1               ((uint32_t)0x45670123)
00170 #define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
00171 #define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
00172 #define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /* Exported macro ------------------------------------------------------------*/
00182 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00183   * @{
00184   */
00185 /**
00186   * @brief  Set the FLASH Latency.
00187   * @param  __LATENCY__: FLASH Latency
00188   *         The value of this parameter depend on device used within the same series
00189   * @retval none
00190   */
00191 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
00192                   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
00193
00194 /**
00195   * @brief  Get the FLASH Latency.
00196   * @retval FLASH Latency
00197   *          The value of this parameter depend on device used within the same series
00198   */
00199 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
00200
00201 /**
00202   * @brief  Enable the FLASH prefetch buffer.
00203   * @retval none
00204   */
00205 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
00206
00207 /**
00208   * @brief  Disable the FLASH prefetch buffer.
00209   * @retval none
00210   */
00211 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
00212
00213 /**
00214   * @brief  Enable the FLASH Adaptive Real-Time memory accelerator.
00215   * @note   The ART accelerator is available only for flash access on ITCM interface.
00216   * @retval none
00217   */
00218 #define __HAL_FLASH_ART_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
00219
00220 /**
00221   * @brief  Disable the FLASH Adaptive Real-Time memory accelerator.
00222   * @retval none
00223   */
00224 #define __HAL_FLASH_ART_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
00225
00226 /**
00227   * @brief  Resets the FLASH Adaptive Real-Time memory accelerator.
00228   * @note   This function must be used only when the Adaptive Real-Time memory accelerator
00229   *         is disabled.
00230   * @retval None
00231   */
00232 #define __HAL_FLASH_ART_RESET()  (FLASH->ACR |= FLASH_ACR_ARTRST)
00233
00234 /**
00235   * @brief  Enable the specified FLASH interrupt.
00236   * @param  __INTERRUPT__ : FLASH interrupt
00237   *         This parameter can be any combination of the following values:
00238   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00239   *     @arg FLASH_IT_ERR: Error Interrupt
00240   * @retval none
00241   */
00242 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
00243
00244 /**
00245   * @brief  Disable the specified FLASH interrupt.
00246   * @param  __INTERRUPT__ : FLASH interrupt
00247   *         This parameter can be any combination of the following values:
00248   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00249   *     @arg FLASH_IT_ERR: Error Interrupt
00250   * @retval none
00251   */
00252 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
00253
00254 /**
00255   * @brief  Get the specified FLASH flag status.
00256   * @param  __FLAG__: specifies the FLASH flag to check.
00257   *          This parameter can be one of the following values:
00258   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
00259   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
00260   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
00261   *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
00262   *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
00263   *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
00264   *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
00265   * @retval The new state of __FLAG__ (SET or RESET).
00266   */
00267 #define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
00268
00269 /**
00270   * @brief  Clear the specified FLASH flag.
00271   * @param  __FLAG__: specifies the FLASH flags to clear.
00272   *          This parameter can be any combination of the following values:
00273   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
00274   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
00275   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
00276   *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
00277   *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
00278   *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
00279   * @retval none
00280   */
00281 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
00282 /**
00283   * @}
00284   */
00285
00286 /* Include FLASH HAL Extension module */
00287 #include "stm32f7xx_hal_flash_ex.h"
00288
00289 /* Exported functions --------------------------------------------------------*/
00290 /** @addtogroup FLASH_Exported_Functions
00291   * @{
00292   */
00293 /** @addtogroup FLASH_Exported_Functions_Group1
00294   * @{
00295   */
00296 /* Program operation functions  ***********************************************/
00297 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00298 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00299 /* FLASH IRQ handler method */
00300 void HAL_FLASH_IRQHandler(void);
00301 /* Callbacks in non blocking modes */
00302 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00303 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00304 /**
00305   * @}
00306   */
00307
00308 /** @addtogroup FLASH_Exported_Functions_Group2
00309   * @{
00310   */
00311 /* Peripheral Control functions  **********************************************/
00312 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
00313 HAL_StatusTypeDef HAL_FLASH_Lock(void);
00314 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
00315 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
00316 /* Option bytes control */
00317 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
00318 /**
00319   * @}
00320   */
00321
00322 /** @addtogroup FLASH_Exported_Functions_Group3
00323   * @{
00324   */
00325 /* Peripheral State functions  ************************************************/
00326 uint32_t HAL_FLASH_GetError(void);
00327 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335 /* Private types -------------------------------------------------------------*/
00336 /* Private variables ---------------------------------------------------------*/
00337 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00338   * @{
00339   */
00340
00341 /**
00342   * @}
00343   */
00344 /* Private constants ---------------------------------------------------------*/
00345 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00346   * @{
00347   */
00348
00349 /**
00350   * @brief   OPTCR register byte 1 (Bits[15:8]) base address
00351   */
00352 #define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
00353
00354 /**
00355   * @}
00356   */
00357
00358 /* Private macros ------------------------------------------------------------*/
00359 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00360   * @{
00361   */
00362
00363 /** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
00364   * @{
00365   */
00366 #define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
00367                                     ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
00368                                     ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
00369                                     ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
00370 /**
00371   * @}
00372   */
00373
00374 /**
00375   * @}
00376   */
00377
00378 /* Private functions ---------------------------------------------------------*/
00379 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00380   * @{
00381   */
00382
00383 /**
00384   * @}
00385   */
00386
00387 /**
00388   * @}
00389   */
00390
00391 /**
00392   * @}
00393   */
00394
00395 #ifdef __cplusplus
00396 }
00397 #endif
00398
00399 #endif /* __STM32F7xx_HAL_FLASH_H */
00400
00401 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash_ex.c Source File

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stm32f7xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Extended FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the FLASH extension peripheral:
00010   *           + Extended programming operations functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                    ##### Flash Extension features #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and
00018        devices contains the following additional features
00019
00020        (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
00021            capability (RWW)
00022        (+) Dual bank memory organization
00023        (+) PCROP protection for all banks
00024
00025                       ##### How to use this driver #####
00026   ==============================================================================
00027   [..] This driver provides functions to configure and program the FLASH memory
00028        of all STM32F7xx devices. It includes
00029       (#) FLASH Memory Erase functions:
00030            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00031                 HAL_FLASH_Lock() functions
00032            (++) Erase function: Erase sector, erase all sectors
00033            (++) There are two modes of erase :
00034              (+++) Polling Mode using HAL_FLASHEx_Erase()
00035              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00036
00037       (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
00038            (++) Set/Reset the write protection
00039            (++) Set the Read protection Level
00040            (++) Set the BOR level
00041            (++) Program the user Option Bytes
00042       (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
00043        (++) Extended space (bank 2) erase function
00044        (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
00045        (++) Dual Boot activation
00046        (++) Write protection configuration for bank 2
00047        (++) PCROP protection configuration and control for both banks
00048
00049   @endverbatim
00050   ******************************************************************************
00051   * @attention
00052   *
00053   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00054   *
00055   * Redistribution and use in source and binary forms, with or without modification,
00056   * are permitted provided that the following conditions are met:
00057   *   1. Redistributions of source code must retain the above copyright notice,
00058   *      this list of conditions and the following disclaimer.
00059   *   2. Redistributions in binary form must reproduce the above copyright notice,
00060   *      this list of conditions and the following disclaimer in the documentation
00061   *      and/or other materials provided with the distribution.
00062   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00063   *      may be used to endorse or promote products derived from this software
00064   *      without specific prior written permission.
00065   *
00066   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00067   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00068   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00069   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00070   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00071   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00072   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00073   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00074   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00075   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00076   *
00077   ******************************************************************************
00078   */
00079
00080 /* Includes ------------------------------------------------------------------*/
00081 #include "stm32f7xx_hal.h"
00082
00083 /** @addtogroup STM32F7xx_HAL_Driver
00084   * @{
00085   */
00086
00087 /** @defgroup FLASHEx FLASHEx
00088   * @brief FLASH HAL Extension module driver
00089   * @{
00090   */
00091
00092 #ifdef HAL_FLASH_MODULE_ENABLED
00093
00094 /* Private typedef -----------------------------------------------------------*/
00095 /* Private define ------------------------------------------------------------*/
00096 /** @addtogroup FLASHEx_Private_Constants
00097   * @{
00098   */
00099 #define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
00100 #define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */
00101 /**
00102   * @}
00103   */
00104
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /** @addtogroup FLASHEx_Private_Variables
00108   * @{
00109   */
00110 extern FLASH_ProcessTypeDef pFlash;
00111 /**
00112   * @}
00113   */
00114
00115 /* Private function prototypes -----------------------------------------------*/
00116 /** @addtogroup FLASHEx_Private_Functions
00117   * @{
00118   */
00119 /* Option bytes control */
00120 static void               FLASH_MassErase(uint8_t VoltageRange);
00121 static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);
00122 static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);
00123 static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
00124 static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
00125 static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
00126 static HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
00127 static uint32_t           FLASH_OB_GetUser(void);
00128 static uint32_t           FLASH_OB_GetWRP(void);
00129 static uint8_t            FLASH_OB_GetRDP(void);
00130 static uint32_t           FLASH_OB_GetBOR(void);
00131 static uint32_t           FLASH_OB_GetBootAddress(uint32_t BootOption);
00132
00133 extern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
00134 /**
00135   * @}
00136   */
00137
00138 /* Exported functions --------------------------------------------------------*/
00139 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
00140   * @{
00141   */
00142
00143 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00144  *  @brief   Extended IO operation functions
00145  *
00146 @verbatim
00147  ===============================================================================
00148                 ##### Extended programming operation functions #####
00149  ===============================================================================
00150     [..]
00151     This subsection provides a set of functions allowing to manage the Extension FLASH
00152     programming operations Operations.
00153
00154 @endverbatim
00155   * @{
00156   */
00157 /**
00158   * @brief  Perform a mass erase or erase the specified FLASH memory sectors
00159   * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
00160   *         contains the configuration information for the erasing.
00161   *
00162   * @param[out]  SectorError: pointer to variable  that
00163   *         contains the configuration information on faulty sector in case of error
00164   *         (0xFFFFFFFF means that all the sectors have been correctly erased)
00165   *
00166   * @retval HAL Status
00167   */
00168 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
00169 {
00170   HAL_StatusTypeDef status = HAL_ERROR;
00171   uint32_t index = 0;
00172
00173   /* Process Locked */
00174   __HAL_LOCK(&pFlash);
00175
00176   /* Check the parameters */
00177   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00178
00179   /* Wait for last operation to be completed */
00180   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00181
00182   if(status == HAL_OK)
00183   {
00184     /*Initialization of SectorError variable*/
00185     *SectorError = 0xFFFFFFFF;
00186
00187     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00188     {
00189       /*Mass erase to be done*/
00190       FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
00191
00192       /* Wait for last operation to be completed */
00193       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00194
00195       /* if the erase operation is completed, disable the MER Bit */
00196       FLASH->CR &= (~FLASH_MER_BIT);
00197     }
00198     else
00199     {
00200       /* Check the parameters */
00201       assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
00202
00203       /* Erase by sector by sector to be done*/
00204       for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
00205       {
00206         FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
00207
00208         /* Wait for last operation to be completed */
00209         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00210
00211         /* If the erase operation is completed, disable the SER Bit */
00212         FLASH->CR &= (~FLASH_CR_SER);
00213         FLASH->CR &= SECTOR_MASK;
00214
00215         if(status != HAL_OK)
00216         {
00217           /* In case of error, stop erase procedure and return the faulty sector*/
00218           *SectorError = index;
00219           break;
00220         }
00221       }
00222     }
00223   }
00224
00225   /* Process Unlocked */
00226   __HAL_UNLOCK(&pFlash);
00227
00228   return status;
00229 }
00230
00231 /**
00232   * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
00233   * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
00234   *         contains the configuration information for the erasing.
00235   *
00236   * @retval HAL Status
00237   */
00238 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00239 {
00240   HAL_StatusTypeDef status = HAL_OK;
00241
00242   /* Process Locked */
00243   __HAL_LOCK(&pFlash);
00244
00245   /* Check the parameters */
00246   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00247
00248   /* Enable End of FLASH Operation interrupt */
00249   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
00250
00251   /* Enable Error source interrupt */
00252   __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
00253
00254   /* Clear pending flags (if any) */
00255   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
00256                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
00257
00258   if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00259   {
00260     /*Mass erase to be done*/
00261     pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
00262     FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
00263   }
00264   else
00265   {
00266     /* Erase by sector to be done*/
00267
00268     /* Check the parameters */
00269     assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
00270
00271     pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
00272     pFlash.NbSectorsToErase = pEraseInit->NbSectors;
00273     pFlash.Sector = pEraseInit->Sector;
00274     pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
00275
00276     /*Erase 1st sector and wait for IT*/
00277     FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
00278   }
00279
00280   return status;
00281 }
00282
00283 /**
00284   * @brief  Program option bytes
00285   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
00286   *         contains the configuration information for the programming.
00287   *
00288   * @retval HAL Status
00289   */
00290 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00291 {
00292   HAL_StatusTypeDef status = HAL_ERROR;
00293
00294   /* Process Locked */
00295   __HAL_LOCK(&pFlash);
00296
00297   /* Check the parameters */
00298   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00299
00300   /* Write protection configuration */
00301   if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
00302   {
00303     assert_param(IS_WRPSTATE(pOBInit->WRPState));
00304     if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
00305     {
00306       /*Enable of Write protection on the selected Sector*/
00307       status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
00308     }
00309     else
00310     {
00311       /*Disable of Write protection on the selected Sector*/
00312       status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
00313     }
00314   }
00315
00316   /* Read protection configuration */
00317   if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
00318   {
00319     status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
00320   }
00321
00322   /* USER  configuration */
00323   if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
00324   {
00325     status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
00326                                  pOBInit->USERConfig & OB_IWDG_SW,
00327                                  pOBInit->USERConfig & OB_STOP_NO_RST,
00328                                  pOBInit->USERConfig & OB_STDBY_NO_RST,
00329                                  pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
00330                                  pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
00331   }
00332
00333   /* BOR Level  configuration */
00334   if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
00335   {
00336     status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
00337   }
00338
00339   /* Boot 0 Address configuration */
00340   if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
00341   {
00342     status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
00343   }
00344
00345   /* Boot 1 Address configuration */
00346   if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
00347   {
00348     status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
00349   }
00350
00351   /* Process Unlocked */
00352   __HAL_UNLOCK(&pFlash);
00353
00354   return status;
00355 }
00356
00357 /**
00358   * @brief   Get the Option byte configuration
00359   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
00360   *         contains the configuration information for the programming.
00361   *
00362   * @retval None
00363   */
00364 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00365 {
00366   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
00367                         OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
00368
00369   /*Get WRP*/
00370   pOBInit->WRPSector = FLASH_OB_GetWRP();
00371
00372   /*Get RDP Level*/
00373   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00374
00375   /*Get USER*/
00376   pOBInit->USERConfig = FLASH_OB_GetUser();
00377
00378   /*Get BOR Level*/
00379   pOBInit->BORLevel = FLASH_OB_GetBOR();
00380
00381   /*Get Boot Address when Boot pin = 0 */
00382   pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
00383
00384   /*Get Boot Address when Boot pin = 1 */
00385   pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
00386 }
00387
00388 /**
00389   * @}
00390   */
00391
00392 /**
00393   * @brief  Full erase of FLASH memory sectors
00394   * @param  VoltageRange: The device voltage range which defines the erase parallelism.
00395   *          This parameter can be one of the following values:
00396   *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
00397   *                                  the operation will be done by byte (8-bit)
00398   *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
00399   *                                  the operation will be done by half word (16-bit)
00400   *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
00401   *                                  the operation will be done by word (32-bit)
00402   *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
00403   *                                  the operation will be done by double word (64-bit)
00404   *
00405   * @retval HAL Status
00406   */
00407 static void FLASH_MassErase(uint8_t VoltageRange)
00408 {
00409   uint32_t tmp_psize = 0;
00410
00411   /* Check the parameters */
00412   assert_param(IS_VOLTAGERANGE(VoltageRange));
00413
00414   /* if the previous operation is completed, proceed to erase all sectors */
00415   FLASH->CR &= CR_PSIZE_MASK;
00416   FLASH->CR |= tmp_psize;
00417   FLASH->CR |= FLASH_CR_MER;
00418   FLASH->CR |= FLASH_CR_STRT;
00419   /* Data synchronous Barrier (DSB) Just after the write operation
00420      This will force the CPU to respect the sequence of instruction (no optimization).*/
00421   __DSB();
00422 }
00423
00424 /**
00425   * @brief  Erase the specified FLASH memory sector
00426   * @param  Sector: FLASH sector to erase
00427   *         The value of this parameter depend on device used within the same series
00428   * @param  VoltageRange: The device voltage range which defines the erase parallelism.
00429   *          This parameter can be one of the following values:
00430   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
00431   *                                  the operation will be done by byte (8-bit)
00432   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
00433   *                                  the operation will be done by half word (16-bit)
00434   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
00435   *                                  the operation will be done by word (32-bit)
00436   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
00437   *                                  the operation will be done by double word (64-bit)
00438   *
00439   * @retval None
00440   */
00441 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
00442 {
00443   uint32_t tmp_psize = 0;
00444
00445   /* Check the parameters */
00446   assert_param(IS_FLASH_SECTOR(Sector));
00447   assert_param(IS_VOLTAGERANGE(VoltageRange));
00448
00449   if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
00450   {
00451      tmp_psize = FLASH_PSIZE_BYTE;
00452   }
00453   else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
00454   {
00455     tmp_psize = FLASH_PSIZE_HALF_WORD;
00456   }
00457   else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
00458   {
00459     tmp_psize = FLASH_PSIZE_WORD;
00460   }
00461   else
00462   {
00463     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
00464   }
00465
00466   /* If the previous operation is completed, proceed to erase the sector */
00467   FLASH->CR &= CR_PSIZE_MASK;
00468   FLASH->CR |= tmp_psize;
00469   FLASH->CR &= SECTOR_MASK;
00470   FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
00471   FLASH->CR |= FLASH_CR_STRT;
00472
00473   /* Data synchronous Barrier (DSB) Just after the write operation
00474      This will force the CPU to respect the sequence of instruction (no optimization).*/
00475   __DSB();
00476 }
00477
00478 /**
00479   * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
00480   *
00481   * @note   When the memory read protection level is selected (RDP level = 1),
00482   *         it is not possible to program or erase the flash sector i if CortexM7
00483   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00484   *
00485   * @param  WRPSector: specifies the sector(s) to be write protected.
00486   *          This parameter can be one of the following values:
00487   *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
00488   *            @arg OB_WRP_SECTOR_All
00489   *
00490   * @retval HAL FLASH State
00491   */
00492 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
00493 {
00494   HAL_StatusTypeDef status = HAL_OK;
00495
00496   /* Check the parameters */
00497   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00498
00499   /* Wait for last operation to be completed */
00500   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00501
00502   if(status == HAL_OK)
00503   {
00504     /*Write protection enabled on sectors */
00505     FLASH->OPTCR &= (~WRPSector);
00506   }
00507
00508   return status;
00509 }
00510
00511 /**
00512   * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
00513   *
00514   * @note   When the memory read protection level is selected (RDP level = 1),
00515   *         it is not possible to program or erase the flash sector i if CortexM4
00516   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00517   *
00518   * @param  WRPSector: specifies the sector(s) to be write protected.
00519   *          This parameter can be one of the following values:
00520   *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
00521   *            @arg OB_WRP_Sector_All
00522   *
00523   *
00524   * @retval HAL Status
00525   */
00526 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
00527 {
00528   HAL_StatusTypeDef status = HAL_OK;
00529
00530   /* Check the parameters */
00531   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00532
00533   /* Wait for last operation to be completed */
00534   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00535
00536   if(status == HAL_OK)
00537   {
00538     /* Write protection disabled on sectors */
00539     FLASH->OPTCR |= (WRPSector);
00540   }
00541
00542   return status;
00543 }
00544
00545 /**
00546   * @brief  Set the read protection level.
00547   * @param  Level: specifies the read protection level.
00548   *          This parameter can be one of the following values:
00549   *            @arg OB_RDP_LEVEL_0: No protection
00550   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
00551   *            @arg OB_RDP_LEVEL_2: Full chip protection
00552   *
00553   * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
00554   *
00555   * @retval HAL Status
00556   */
00557 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
00558 {
00559   HAL_StatusTypeDef status = HAL_OK;
00560
00561   /* Check the parameters */
00562   assert_param(IS_OB_RDP_LEVEL(Level));
00563
00564   /* Wait for last operation to be completed */
00565   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00566
00567   if(status == HAL_OK)
00568   {
00569     *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
00570   }
00571
00572   return status;
00573 }
00574
00575 /**
00576   * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
00577   * @param  Wwdg: Selects the IWDG mode
00578   *          This parameter can be one of the following values:
00579   *            @arg OB_WWDG_SW: Software WWDG selected
00580   *            @arg OB_WWDG_HW: Hardware WWDG selected
00581   * @param  Iwdg: Selects the WWDG mode
00582   *          This parameter can be one of the following values:
00583   *            @arg OB_IWDG_SW: Software IWDG selected
00584   *            @arg OB_IWDG_HW: Hardware IWDG selected
00585   * @param  Stop: Reset event when entering STOP mode.
00586   *          This parameter  can be one of the following values:
00587   *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
00588   *            @arg OB_STOP_RST: Reset generated when entering in STOP
00589   * @param  Stdby: Reset event when entering Standby mode.
00590   *          This parameter  can be one of the following values:
00591   *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
00592   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
00593   * @param  Iwdgstop: Independent watchdog counter freeze in Stop mode.
00594   *          This parameter  can be one of the following values:
00595   *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
00596   *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
00597   * @param  Iwdgstdby: Independent watchdog counter freeze in standby mode.
00598   *          This parameter  can be one of the following values:
00599   *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
00600   *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
00601   * @retval HAL Status
00602   */
00603 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
00604 {
00605   uint32_t useroptionmask = 0x00;
00606   uint32_t useroptionvalue = 0x00;
00607
00608   HAL_StatusTypeDef status = HAL_OK;
00609
00610   /* Check the parameters */
00611   assert_param(IS_OB_WWDG_SOURCE(Wwdg));
00612   assert_param(IS_OB_IWDG_SOURCE(Iwdg));
00613   assert_param(IS_OB_STOP_SOURCE(Stop));
00614   assert_param(IS_OB_STDBY_SOURCE(Stdby));
00615   assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
00616   assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
00617
00618   /* Wait for last operation to be completed */
00619   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00620
00621   if(status == HAL_OK)
00622   {
00623     useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
00624                       FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
00625
00626     useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
00627
00628     /* Update User Option Byte */
00629     MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
00630   }
00631
00632   return status;
00633
00634 }
00635
00636 /**
00637   * @brief  Set the BOR Level.
00638   * @param  Level: specifies the Option Bytes BOR Reset Level.
00639   *          This parameter can be one of the following values:
00640   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
00641   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
00642   *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
00643   *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
00644   * @retval HAL Status
00645   */
00646 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
00647 {
00648   /* Check the parameters */
00649   assert_param(IS_OB_BOR_LEVEL(Level));
00650
00651   /* Set the BOR Level */
00652   MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
00653
00654   return HAL_OK;
00655
00656 }
00657
00658 /**
00659   * @brief  Configure Boot base address.
00660   *
00661   * @param   BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
00662   *          This parameter can be one of the following values:
00663   *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
00664   *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
00665   * @param   Address: specifies Boot base address
00666   *          This parameter can be one of the following values:
00667   *            @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
00668   *            @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
00669   *            @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
00670   *            @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
00671   *            @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
00672   *            @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
00673   *            @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
00674   *
00675   * @retval HAL Status
00676   */
00677 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
00678 {
00679   HAL_StatusTypeDef status = HAL_OK;
00680
00681   /* Check the parameters */
00682   assert_param(IS_OB_BOOT_ADDRESS(Address));
00683
00684   /* Wait for last operation to be completed */
00685   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00686
00687   if(status == HAL_OK)
00688   {
00689     if(BootOption == OPTIONBYTE_BOOTADDR_0)
00690     {
00691       MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
00692     }
00693     else
00694     {
00695       MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
00696     }
00697   }
00698
00699   return status;
00700 }
00701
00702 /**
00703   * @brief  Return the FLASH User Option Byte value.
00704   * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
00705   *         and RST_STDBY(Bit2).
00706   */
00707 static uint32_t FLASH_OB_GetUser(void)
00708 {
00709   /* Return the User Option Byte */
00710   return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
00711 }
00712
00713 /**
00714   * @brief  Return the FLASH Write Protection Option Bytes value.
00715   * @retval uint32_t FLASH Write Protection Option Bytes value
00716   */
00717 static uint32_t FLASH_OB_GetWRP(void)
00718 {
00719   /* Return the FLASH write protection Register value */
00720   return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
00721 }
00722
00723 /**
00724   * @brief  Returns the FLASH Read Protection level.
00725   * @retval FlagStatus FLASH ReadOut Protection Status:
00726   *         This parameter can be one of the following values:
00727   *            @arg OB_RDP_LEVEL_0: No protection
00728   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
00729   *            @arg OB_RDP_LEVEL_2: Full chip protection
00730   */
00731 static uint8_t FLASH_OB_GetRDP(void)
00732 {
00733   uint8_t readstatus = OB_RDP_LEVEL_0;
00734
00735   if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
00736   {
00737     readstatus = OB_RDP_LEVEL_0;
00738   }
00739   else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
00740   {
00741     readstatus = OB_RDP_LEVEL_2;
00742   }
00743   else
00744   {
00745     readstatus = OB_RDP_LEVEL_1;
00746   }
00747
00748   return readstatus;
00749 }
00750
00751 /**
00752   * @brief  Returns the FLASH BOR level.
00753   * @retval uint32_t The FLASH BOR level:
00754   *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
00755   *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
00756   *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
00757   *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V
00758   */
00759 static uint32_t FLASH_OB_GetBOR(void)
00760 {
00761   /* Return the FLASH BOR level */
00762   return ((uint32_t)(FLASH->OPTCR & 0x0C));
00763 }
00764
00765 /**
00766   * @brief  Configure Boot base address.
00767   *
00768   * @param   BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
00769   *          This parameter can be one of the following values:
00770   *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
00771   *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
00772   *
00773   * @retval uint32_t Boot Base Address:
00774   *            - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
00775   *            - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
00776   *            - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
00777   *            - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
00778   *            - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
00779   *            - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
00780   *            - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
00781   */
00782 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
00783 {
00784   uint32_t Address = 0;
00785
00786         /* Return the Boot base Address */
00787   if(BootOption == OPTIONBYTE_BOOTADDR_0)
00788   {
00789     Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
00790         }
00791   else
00792         {
00793                 Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
00794         }
00795
00796   return Address;
00797 }
00798
00799 /**
00800   * @}
00801   */
00802
00803 #endif /* HAL_FLASH_MODULE_ENABLED */
00804
00805 /**
00806   * @}
00807   */
00808
00809 /**
00810   * @}
00811   */
00812
00813 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_flash_ex.h Source File

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stm32f7xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of FLASH HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_FLASH_EX_H
00040 #define __STM32F7xx_HAL_FLASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASHEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Erase structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t TypeErase;   /*!< Mass erase or sector Erase.
00068                              This parameter can be a value of @ref FLASHEx_Type_Erase */
00069
00070   uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
00071                              This parameter must be a value of @ref FLASHEx_Sectors */
00072
00073   uint32_t NbSectors;   /*!< Number of sectors to be erased.
00074                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
00075
00076   uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
00077                              This parameter must be a value of @ref FLASHEx_Voltage_Range */
00078
00079 } FLASH_EraseInitTypeDef;
00080
00081 /**
00082   * @brief  FLASH Option Bytes Program structure definition
00083   */
00084 typedef struct
00085 {
00086   uint32_t OptionType;   /*!< Option byte to be configured.
00087                               This parameter can be a value of @ref FLASHEx_Option_Type */
00088
00089   uint32_t WRPState;     /*!< Write protection activation or deactivation.
00090                               This parameter can be a value of @ref FLASHEx_WRP_State */
00091
00092   uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.
00093                               The value of this parameter depend on device used within the same series */
00094
00095   uint32_t RDPLevel;     /*!< Set the read protection level.
00096                               This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
00097
00098   uint32_t BORLevel;     /*!< Set the BOR Level.
00099                               This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
00100
00101   uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
00102                               IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */
00103
00104   uint32_t BootAddr0;    /*!< Boot base address when Boot pin = 0.
00105                               This parameter can be a value of @ref FLASHEx_Boot_Address */
00106
00107   uint32_t BootAddr1;    /*!< Boot base address when Boot pin = 1.
00108                               This parameter can be a value of @ref FLASHEx_Boot_Address */
00109
00110 } FLASH_OBProgramInitTypeDef;
00111
00112 /**
00113   * @}
00114   */
00115 /* Exported constants --------------------------------------------------------*/
00116
00117 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
00122   * @{
00123   */
00124 #define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00)  /*!< Sectors erase only          */
00125 #define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01)  /*!< Flash Mass erase activation */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
00131   * @{
00132   */
00133 #define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00)  /*!< Device operating range: 1.8V to 2.1V                */
00134 #define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01)  /*!< Device operating range: 2.1V to 2.7V                */
00135 #define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02)  /*!< Device operating range: 2.7V to 3.6V                */
00136 #define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup FLASHEx_WRP_State FLASH WRP State
00142   * @{
00143   */
00144 #define OB_WRPSTATE_DISABLE       ((uint32_t)0x00)  /*!< Disable the write protection of the desired bank 1 sectors */
00145 #define OB_WRPSTATE_ENABLE        ((uint32_t)0x01)  /*!< Enable the write protection of the desired bank 1 sectors  */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup FLASHEx_Option_Type FLASH Option Type
00151   * @{
00152   */
00153 #define OPTIONBYTE_WRP         ((uint32_t)0x01)  /*!< WRP option byte configuration  */
00154 #define OPTIONBYTE_RDP         ((uint32_t)0x02)  /*!< RDP option byte configuration  */
00155 #define OPTIONBYTE_USER        ((uint32_t)0x04)  /*!< USER option byte configuration */
00156 #define OPTIONBYTE_BOR         ((uint32_t)0x08)  /*!< BOR option byte configuration  */
00157 #define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10)  /*!< Boot 0 Address configuration   */
00158 #define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20)  /*!< Boot 1 Address configuration   */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
00164   * @{
00165   */
00166 #define OB_RDP_LEVEL_0       ((uint8_t)0xAA)
00167 #define OB_RDP_LEVEL_1       ((uint8_t)0x55)
00168 #define OB_RDP_LEVEL_2       ((uint8_t)0xCC)   /*!< Warning: When enabling read protection level 2
00169                                                   it s no more possible to go back to level 1 or 0 */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
00175   * @{
00176   */
00177 #define OB_WWDG_SW           ((uint32_t)0x10)  /*!< Software WWDG selected */
00178 #define OB_WWDG_HW           ((uint32_t)0x00)  /*!< Hardware WWDG selected */
00179 /**
00180   * @}
00181   */
00182
00183
00184 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
00185   * @{
00186   */
00187 #define OB_IWDG_SW           ((uint32_t)0x20)  /*!< Software IWDG selected */
00188 #define OB_IWDG_HW           ((uint32_t)0x00)  /*!< Hardware IWDG selected */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
00194   * @{
00195   */
00196 #define OB_STOP_NO_RST       ((uint32_t)0x40) /*!< No reset generated when entering in STOP */
00197 #define OB_STOP_RST          ((uint32_t)0x00) /*!< Reset generated when entering in STOP    */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
00203   * @{
00204   */
00205 #define OB_STDBY_NO_RST      ((uint32_t)0x80) /*!< No reset generated when entering in STANDBY */
00206 #define OB_STDBY_RST         ((uint32_t)0x00) /*!< Reset generated when entering in STANDBY    */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
00212   * @{
00213   */
00214 #define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */
00215 #define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x80000000) /*!< IWDG counter active in STOP mode */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
00221   * @{
00222   */
00223 #define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */
00224 #define OB_IWDG_STDBY_ACTIVE      ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
00230   * @{
00231   */
00232 #define OB_BOR_LEVEL3          ((uint32_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
00233 #define OB_BOR_LEVEL2          ((uint32_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
00234 #define OB_BOR_LEVEL1          ((uint32_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
00235 #define OB_BOR_OFF             ((uint32_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
00242   * @{
00243   */
00244 #define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000)  /*!< Boot from ITCM RAM (0x00000000)                 */
00245 #define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040)  /*!< Boot from System memory bootloader (0x00100000) */
00246 #define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080)  /*!< Boot from Flash on ITCM interface (0x00200000)  */
00247 #define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000)  /*!< Boot from Flash on AXIM interface (0x08000000)  */
00248 #define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000)  /*!< Boot from DTCM RAM (0x20000000)                 */
00249 #define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004)  /*!< Boot from SRAM1 (0x20010000)                    */
00250 #define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013)  /*!< Boot from SRAM2 (0x2004C000)                    */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup FLASH_Latency FLASH Latency
00256   * @{
00257   */
00258 #define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
00259 #define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
00260 #define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
00261 #define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
00262 #define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
00263 #define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
00264 #define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
00265 #define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
00266 #define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
00267 #define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
00268 #define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
00269 #define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
00270 #define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
00271 #define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
00272 #define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
00273 #define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
00279   * @{
00280   */
00281 #define FLASH_MER_BIT     (FLASH_CR_MER) /*!< MER bit to clear */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup FLASHEx_Sectors FLASH Sectors
00287   * @{
00288   */
00289 #define FLASH_SECTOR_0     ((uint32_t)0) /*!< Sector Number 0   */
00290 #define FLASH_SECTOR_1     ((uint32_t)1) /*!< Sector Number 1   */
00291 #define FLASH_SECTOR_2     ((uint32_t)2) /*!< Sector Number 2   */
00292 #define FLASH_SECTOR_3     ((uint32_t)3) /*!< Sector Number 3   */
00293 #define FLASH_SECTOR_4     ((uint32_t)4) /*!< Sector Number 4   */
00294 #define FLASH_SECTOR_5     ((uint32_t)5) /*!< Sector Number 5   */
00295 #define FLASH_SECTOR_6     ((uint32_t)6) /*!< Sector Number 6   */
00296 #define FLASH_SECTOR_7     ((uint32_t)7) /*!< Sector Number 7   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
00303   * @{
00304   */
00305 #define OB_WRP_SECTOR_0       ((uint32_t)0x00010000) /*!< Write protection of Sector0     */
00306 #define OB_WRP_SECTOR_1       ((uint32_t)0x00020000) /*!< Write protection of Sector1     */
00307 #define OB_WRP_SECTOR_2       ((uint32_t)0x00040000) /*!< Write protection of Sector2     */
00308 #define OB_WRP_SECTOR_3       ((uint32_t)0x00080000) /*!< Write protection of Sector3     */
00309 #define OB_WRP_SECTOR_4       ((uint32_t)0x00100000) /*!< Write protection of Sector4     */
00310 #define OB_WRP_SECTOR_5       ((uint32_t)0x00200000) /*!< Write protection of Sector5     */
00311 #define OB_WRP_SECTOR_6       ((uint32_t)0x00400000) /*!< Write protection of Sector6     */
00312 #define OB_WRP_SECTOR_7       ((uint32_t)0x00800000) /*!< Write protection of Sector7     */
00313 #define OB_WRP_SECTOR_All     ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /**
00320   * @}
00321   */
00322
00323 /* Exported macro ------------------------------------------------------------*/
00324 /* Exported functions --------------------------------------------------------*/
00325 /** @addtogroup FLASHEx_Exported_Functions
00326   * @{
00327   */
00328
00329 /** @addtogroup FLASHEx_Exported_Functions_Group1
00330   * @{
00331   */
00332 /* Extension Program operation functions  *************************************/
00333 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
00334 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00335 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00336 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00337
00338 /**
00339   * @}
00340   */
00341
00342 /**
00343   * @}
00344   */
00345 /* Private types -------------------------------------------------------------*/
00346 /* Private variables ---------------------------------------------------------*/
00347 /* Private constants ---------------------------------------------------------*/
00348 /** @defgroup FLASHEx_Private_Constants FLASH Private Constants
00349   * @{
00350   */
00351 #define FLASH_SECTOR_TOTAL  8
00352 /**
00353   * @}
00354   */
00355
00356 /* Private macros ------------------------------------------------------------*/
00357 /** @defgroup FLASHEx_Private_Macros FLASH Private Macros
00358   * @{
00359   */
00360
00361 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
00362   * @{
00363   */
00364
00365 #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
00366                                   ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00367
00368 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
00369                                ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
00370                                ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
00371                                ((RANGE) == FLASH_VOLTAGE_RANGE_4))
00372
00373 #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
00374                            ((VALUE) == OB_WRPSTATE_ENABLE))
00375
00376 #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
00377                                           OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
00378
00379 #define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM)   || \
00380                                      ((ADDRESS) == OB_BOOTADDR_SYSTEM)     || \
00381                                      ((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \
00382                                      ((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \
00383                                      ((ADDRESS) == OB_BOOTADDR_DTCM_RAM)   || \
00384                                      ((ADDRESS) == OB_BOOTADDR_SRAM1)      || \
00385                                      ((ADDRESS) == OB_BOOTADDR_SRAM2))
00386
00387 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0)   ||\
00388                                 ((LEVEL) == OB_RDP_LEVEL_1)   ||\
00389                                 ((LEVEL) == OB_RDP_LEVEL_2))
00390
00391 #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
00392
00393 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00394
00395 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
00396
00397 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
00398
00399 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
00400
00401 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
00402
00403 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
00404                                 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
00405
00406 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
00407                                    ((LATENCY) == FLASH_LATENCY_1)  || \
00408                                    ((LATENCY) == FLASH_LATENCY_2)  || \
00409                                    ((LATENCY) == FLASH_LATENCY_3)  || \
00410                                    ((LATENCY) == FLASH_LATENCY_4)  || \
00411                                    ((LATENCY) == FLASH_LATENCY_5)  || \
00412                                    ((LATENCY) == FLASH_LATENCY_6)  || \
00413                                    ((LATENCY) == FLASH_LATENCY_7)  || \
00414                                    ((LATENCY) == FLASH_LATENCY_8)  || \
00415                                    ((LATENCY) == FLASH_LATENCY_9)  || \
00416                                    ((LATENCY) == FLASH_LATENCY_10) || \
00417                                    ((LATENCY) == FLASH_LATENCY_11) || \
00418                                    ((LATENCY) == FLASH_LATENCY_12) || \
00419                                    ((LATENCY) == FLASH_LATENCY_13) || \
00420                                    ((LATENCY) == FLASH_LATENCY_14) || \
00421                                    ((LATENCY) == FLASH_LATENCY_15))
00422
00423 #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
00424
00425 #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
00426
00427 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00428                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00429                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
00430                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
00431
00432 #define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))
00433
00434 /**
00435   * @}
00436   */
00437
00438 /**
00439   * @}
00440   */
00441
00442 /* Private functions ---------------------------------------------------------*/
00443 /** @defgroup FLASHEx_Private_Functions FLASH Private Functions
00444   * @{
00445   */
00446 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
00447 /**
00448   * @}
00449   */
00450
00451 /**
00452   * @}
00453   */
00454
00455 /**
00456   * @}
00457   */
00458
00459 #ifdef __cplusplus
00460 }
00461 #endif
00462
00463 #endif /* __STM32F7xx_HAL_FLASH_EX_H */
00464
00465 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_gpio.c Source File

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stm32f7xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   GPIO HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### GPIO Peripheral features #####
00016   ==============================================================================
00017   [..]
00018   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
00019   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
00020   in several modes:
00021   (+) Input mode
00022   (+) Analog mode
00023   (+) Output mode
00024   (+) Alternate function mode
00025   (+) External interrupt/event lines
00026
00027   [..]
00028   During and just after reset, the alternate functions and external interrupt
00029   lines are not active and the I/O ports are configured in input floating mode.
00030
00031   [..]
00032   All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00033   activated or not.
00034
00035   [..]
00036   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00037   type and the IO speed can be selected depending on the VDD value.
00038
00039   [..]
00040   All ports have external interrupt/event capability. To use external interrupt
00041   lines, the port must be configured in input mode. All available GPIO pins are
00042   connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00043
00044   [..]
00045   The external interrupt/event controller consists of up to 23 edge detectors
00046   (16 lines are connected to GPIO) for generating event/interrupt requests (each
00047   input line can be independently configured to select the type (interrupt or event)
00048   and the corresponding trigger event (rising or falling or both). Each line can
00049   also be masked independently.
00050
00051                      ##### How to use this driver #####
00052   ==============================================================================
00053   [..]
00054     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00055
00056     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00057         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00058         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00059              structure.
00060         (++) In case of Output or alternate function mode selection: the speed is
00061              configured through "Speed" member from GPIO_InitTypeDef structure.
00062         (++) In alternate mode is selection, the alternate function connected to the IO
00063              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00064         (++) Analog mode is required when a pin is to be used as ADC channel
00065              or DAC output.
00066         (++) In case of external interrupt/event selection the "Mode" member from
00067              GPIO_InitTypeDef structure select the type (interrupt or event) and
00068              the corresponding trigger event (rising or falling or both).
00069
00070     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00071         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00072         HAL_NVIC_EnableIRQ().
00073
00074     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00075
00076     (#) To set/reset the level of a pin configured in output mode use
00077         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00078
00079     (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00080
00081
00082     (#) During and just after reset, the alternate functions are not
00083         active and the GPIO pins are configured in input floating mode (except JTAG
00084         pins).
00085
00086     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00087         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00088         priority over the GPIO function.
00089
00090     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00091         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
00092         The HSE has priority over the GPIO function.
00093
00094   @endverbatim
00095   ******************************************************************************
00096   * @attention
00097   *
00098   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00099   *
00100   * Redistribution and use in source and binary forms, with or without modification,
00101   * are permitted provided that the following conditions are met:
00102   *   1. Redistributions of source code must retain the above copyright notice,
00103   *      this list of conditions and the following disclaimer.
00104   *   2. Redistributions in binary form must reproduce the above copyright notice,
00105   *      this list of conditions and the following disclaimer in the documentation
00106   *      and/or other materials provided with the distribution.
00107   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00108   *      may be used to endorse or promote products derived from this software
00109   *      without specific prior written permission.
00110   *
00111   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00112   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00113   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00114   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00115   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00116   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00117   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00118   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00119   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00120   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00121   *
00122   ******************************************************************************
00123   */
00124
00125 /* Includes ------------------------------------------------------------------*/
00126 #include "stm32f7xx_hal.h"
00127
00128 /** @addtogroup STM32F7xx_HAL_Driver
00129   * @{
00130   */
00131
00132 /** @defgroup GPIO GPIO
00133   * @brief GPIO HAL module driver
00134   * @{
00135   */
00136
00137 #ifdef HAL_GPIO_MODULE_ENABLED
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
00142   * @{
00143   */
00144 #define GPIO_MODE             ((uint32_t)0x00000003)
00145 #define EXTI_MODE             ((uint32_t)0x10000000)
00146 #define GPIO_MODE_IT          ((uint32_t)0x00010000)
00147 #define GPIO_MODE_EVT         ((uint32_t)0x00020000)
00148 #define RISING_EDGE           ((uint32_t)0x00100000)
00149 #define FALLING_EDGE          ((uint32_t)0x00200000)
00150 #define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
00151
00152 #define GPIO_NUMBER           ((uint32_t)16)
00153 /**
00154   * @}
00155   */
00156 /* Private macro -------------------------------------------------------------*/
00157 /* Private variables ---------------------------------------------------------*/
00158 /* Private function prototypes -----------------------------------------------*/
00159 /* Private functions ---------------------------------------------------------*/
00160 /* Exported functions --------------------------------------------------------*/
00161 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00162   * @{
00163   */
00164
00165 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
00166  *  @brief    Initialization and Configuration functions
00167  *
00168 @verbatim
00169  ===============================================================================
00170               ##### Initialization and de-initialization functions #####
00171  ===============================================================================
00172   [..]
00173     This section provides functions allowing to initialize and de-initialize the GPIOs
00174     to be ready for use.
00175
00176 @endverbatim
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00182   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00183   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00184   *         the configuration information for the specified GPIO peripheral.
00185   * @retval None
00186   */
00187 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00188 {
00189   uint32_t position = 0x00;
00190   uint32_t ioposition = 0x00;
00191   uint32_t iocurrent = 0x00;
00192   uint32_t temp = 0x00;
00193
00194   /* Check the parameters */
00195   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00196   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00197   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00198   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00199
00200   /* Configure the port pins */
00201   for(position = 0; position < GPIO_NUMBER; position++)
00202   {
00203     /* Get the IO position */
00204     ioposition = ((uint32_t)0x01) << position;
00205     /* Get the current IO position */
00206     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
00207
00208     if(iocurrent == ioposition)
00209     {
00210       /*--------------------- GPIO Mode Configuration ------------------------*/
00211       /* In case of Alternate function mode selection */
00212       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00213       {
00214         /* Check the Alternate function parameter */
00215         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00216
00217         /* Configure Alternate function mapped with the current IO */
00218         temp = GPIOx->AFR[position >> 3];
00219         temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
00220         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
00221         GPIOx->AFR[position >> 3] = temp;
00222       }
00223
00224       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00225       temp = GPIOx->MODER;
00226       temp &= ~(GPIO_MODER_MODER0 << (position * 2));
00227       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
00228       GPIOx->MODER = temp;
00229
00230       /* In case of Output or Alternate function mode selection */
00231       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00232          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00233       {
00234         /* Check the Speed parameter */
00235         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00236         /* Configure the IO Speed */
00237         temp = GPIOx->OSPEEDR;
00238         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
00239         temp |= (GPIO_Init->Speed << (position * 2));
00240         GPIOx->OSPEEDR = temp;
00241
00242         /* Configure the IO Output Type */
00243         temp = GPIOx->OTYPER;
00244         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
00245         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
00246         GPIOx->OTYPER = temp;
00247       }
00248
00249       /* Activate the Pull-up or Pull down resistor for the current IO */
00250       temp = GPIOx->PUPDR;
00251       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
00252       temp |= ((GPIO_Init->Pull) << (position * 2));
00253       GPIOx->PUPDR = temp;
00254
00255       /*--------------------- EXTI Mode Configuration ------------------------*/
00256       /* Configure the External Interrupt or event for the current IO */
00257       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00258       {
00259         /* Enable SYSCFG Clock */
00260         __HAL_RCC_SYSCFG_CLK_ENABLE();
00261
00262         temp = SYSCFG->EXTICR[position >> 2];
00263         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
00264         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
00265         SYSCFG->EXTICR[position >> 2] = temp;
00266
00267         /* Clear EXTI line configuration */
00268         temp = EXTI->IMR;
00269         temp &= ~((uint32_t)iocurrent);
00270         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00271         {
00272           temp |= iocurrent;
00273         }
00274         EXTI->IMR = temp;
00275
00276         temp = EXTI->EMR;
00277         temp &= ~((uint32_t)iocurrent);
00278         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00279         {
00280           temp |= iocurrent;
00281         }
00282         EXTI->EMR = temp;
00283
00284         /* Clear Rising Falling edge configuration */
00285         temp = EXTI->RTSR;
00286         temp &= ~((uint32_t)iocurrent);
00287         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00288         {
00289           temp |= iocurrent;
00290         }
00291         EXTI->RTSR = temp;
00292
00293         temp = EXTI->FTSR;
00294         temp &= ~((uint32_t)iocurrent);
00295         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00296         {
00297           temp |= iocurrent;
00298         }
00299         EXTI->FTSR = temp;
00300       }
00301     }
00302   }
00303 }
00304
00305 /**
00306   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
00307   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00308   * @param  GPIO_Pin: specifies the port bit to be written.
00309   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00310   * @retval None
00311   */
00312 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00313 {
00314   uint32_t position;
00315   uint32_t ioposition = 0x00;
00316   uint32_t iocurrent = 0x00;
00317   uint32_t tmp = 0x00;
00318
00319   /* Check the parameters */
00320   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00321
00322   /* Configure the port pins */
00323   for(position = 0; position < GPIO_NUMBER; position++)
00324   {
00325     /* Get the IO position */
00326     ioposition = ((uint32_t)0x01) << position;
00327     /* Get the current IO position */
00328     iocurrent = (GPIO_Pin) & ioposition;
00329
00330     if(iocurrent == ioposition)
00331     {
00332       /*------------------------- GPIO Mode Configuration --------------------*/
00333       /* Configure IO Direction in Input Floating Mode */
00334       GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
00335
00336       /* Configure the default Alternate Function in current IO */
00337       GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
00338
00339       /* Configure the default value for IO Speed */
00340       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
00341
00342       /* Configure the default value IO Output Type */
00343       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
00344
00345       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00346       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
00347
00348       /*------------------------- EXTI Mode Configuration --------------------*/
00349       tmp = SYSCFG->EXTICR[position >> 2];
00350       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
00351       if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
00352       {
00353         /* Configure the External Interrupt or event for the current IO */
00354         tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
00355         SYSCFG->EXTICR[position >> 2] &= ~tmp;
00356
00357         /* Clear EXTI line configuration */
00358         EXTI->IMR &= ~((uint32_t)iocurrent);
00359         EXTI->EMR &= ~((uint32_t)iocurrent);
00360
00361         /* Clear Rising Falling edge configuration */
00362         EXTI->RTSR &= ~((uint32_t)iocurrent);
00363         EXTI->FTSR &= ~((uint32_t)iocurrent);
00364           }
00365     }
00366   }
00367 }
00368
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00374  *  @brief   GPIO Read and Write
00375  *
00376 @verbatim
00377  ===============================================================================
00378                        ##### IO operation functions #####
00379  ===============================================================================
00380
00381 @endverbatim
00382   * @{
00383   */
00384
00385 /**
00386   * @brief  Reads the specified input port pin.
00387   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00388   * @param  GPIO_Pin: specifies the port bit to read.
00389   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00390   * @retval The input port pin value.
00391   */
00392 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00393 {
00394   GPIO_PinState bitstatus;
00395
00396   /* Check the parameters */
00397   assert_param(IS_GPIO_PIN(GPIO_Pin));
00398
00399   if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00400   {
00401     bitstatus = GPIO_PIN_SET;
00402   }
00403   else
00404   {
00405     bitstatus = GPIO_PIN_RESET;
00406   }
00407   return bitstatus;
00408 }
00409
00410 /**
00411   * @brief  Sets or clears the selected data port bit.
00412   *
00413   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
00414   *         accesses. In this way, there is no risk of an IRQ occurring between
00415   *         the read and the modify access.
00416   *
00417   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
00418   * @param  GPIO_Pin: specifies the port bit to be written.
00419   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00420   * @param  PinState: specifies the value to be written to the selected bit.
00421   *          This parameter can be one of the GPIO_PinState enum values:
00422   *            @arg GPIO_PIN_RESET: to clear the port pin
00423   *            @arg GPIO_PIN_SET: to set the port pin
00424   * @retval None
00425   */
00426 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00427 {
00428   /* Check the parameters */
00429   assert_param(IS_GPIO_PIN(GPIO_Pin));
00430   assert_param(IS_GPIO_PIN_ACTION(PinState));
00431
00432   if(PinState != GPIO_PIN_RESET)
00433   {
00434     GPIOx->BSRR = GPIO_Pin;
00435   }
00436   else
00437   {
00438     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
00439   }
00440 }
00441
00442 /**
00443   * @brief  Toggles the specified GPIO pins.
00444   * @param  GPIOx: Where x can be (A..I) to select the GPIO peripheral.
00445   * @param  GPIO_Pin: Specifies the pins to be toggled.
00446   * @retval None
00447   */
00448 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00449 {
00450   /* Check the parameters */
00451   assert_param(IS_GPIO_PIN(GPIO_Pin));
00452
00453   GPIOx->ODR ^= GPIO_Pin;
00454 }
00455
00456 /**
00457   * @brief  Locks GPIO Pins configuration registers.
00458   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00459   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00460   * @note   The configuration of the locked GPIO pins can no longer be modified
00461   *         until the next reset.
00462   * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family
00463   * @param  GPIO_Pin: specifies the port bit to be locked.
00464   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00465   * @retval None
00466   */
00467 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00468 {
00469   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00470
00471   /* Check the parameters */
00472   assert_param(IS_GPIO_PIN(GPIO_Pin));
00473
00474   /* Apply lock key write sequence */
00475   tmp |= GPIO_Pin;
00476   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00477   GPIOx->LCKR = tmp;
00478   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00479   GPIOx->LCKR = GPIO_Pin;
00480   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00481   GPIOx->LCKR = tmp;
00482   /* Read LCKK bit*/
00483   tmp = GPIOx->LCKR;
00484
00485  if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
00486   {
00487     return HAL_OK;
00488   }
00489   else
00490   {
00491     return HAL_ERROR;
00492   }
00493 }
00494
00495 /**
00496   * @brief  This function handles EXTI interrupt request.
00497   * @param  GPIO_Pin: Specifies the pins connected EXTI line
00498   * @retval None
00499   */
00500 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00501 {
00502   /* EXTI line interrupt detected */
00503   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
00504   {
00505     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00506     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00507   }
00508 }
00509
00510 /**
00511   * @brief  EXTI line detection callbacks.
00512   * @param  GPIO_Pin: Specifies the pins connected EXTI line
00513   * @retval None
00514   */
00515 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00516 {
00517   /* Prevent unused argument(s) compilation warning */
00518 __IO uint32_t tmpreg = 0x00;
00519   UNUSED(tmpreg);
00520
00521   /* NOTE: This function Should not be modified, when the callback is needed,
00522            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00523    */
00524 }
00525
00526 /**
00527   * @}
00528   */
00529
00530
00531 /**
00532   * @}
00533   */
00534
00535 #endif /* HAL_GPIO_MODULE_ENABLED */
00536 /**
00537   * @}
00538   */
00539
00540 /**
00541   * @}
00542   */
00543
00544 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_gpio.h Source File

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stm32f7xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of GPIO HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_GPIO_H
00040 #define __STM32F7xx_HAL_GPIO_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup GPIO
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief GPIO Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
00068                            This parameter can be any value of @ref GPIO_pins_define */
00069
00070   uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
00071                            This parameter can be a value of @ref GPIO_mode_define */
00072
00073   uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00074                            This parameter can be a value of @ref GPIO_pull_define */
00075
00076   uint32_t Speed;     /*!< Specifies the speed for the selected pins.
00077                            This parameter can be a value of @ref GPIO_speed_define */
00078
00079   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
00080                             This parameter can be a value of @ref GPIO_Alternate_function_selection */
00081 }GPIO_InitTypeDef;
00082
00083 /**
00084   * @brief  GPIO Bit SET and Bit RESET enumeration
00085   */
00086 typedef enum
00087 {
00088   GPIO_PIN_RESET = 0,
00089   GPIO_PIN_SET
00090 }GPIO_PinState;
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096
00097 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup GPIO_pins_define GPIO pins define
00102   * @{
00103   */
00104 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00105 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00106 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00107 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00108 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00109 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00110 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00111 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00112 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00113 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00114 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00115 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00116 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00117 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00118 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00119 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00120 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00121
00122 #define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup GPIO_mode_define GPIO mode define
00128   * @brief GPIO Configuration Mode
00129   *        Elements values convention: 0xX0yz00YZ
00130   *           - X  : GPIO mode or EXTI Mode
00131   *           - y  : External IT or Event trigger detection
00132   *           - z  : IO configuration on External IT or Event
00133   *           - Y  : Output type (Push Pull or Open Drain)
00134   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00135   * @{
00136   */
00137 #define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
00138 #define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
00139 #define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
00140 #define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
00141 #define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
00142
00143 #define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
00144
00145 #define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00146 #define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00147 #define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00148
00149 #define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
00150 #define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
00151 #define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup GPIO_speed_define  GPIO speed define
00157   * @brief GPIO Output Maximum frequency
00158   * @{
00159   */
00160 #define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000)  /*!< Low speed     */
00161 #define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001)  /*!< Medium speed  */
00162 #define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002)  /*!< Fast speed    */
00163 #define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003)  /*!< High speed    */
00164 /**
00165   * @}
00166   */
00167
00168  /** @defgroup GPIO_pull_define GPIO pull define
00169    * @brief GPIO Pull-Up or Pull-Down Activation
00170    * @{
00171    */
00172 #define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
00173 #define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
00174 #define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
00175 /**
00176   * @}
00177   */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported macro ------------------------------------------------------------*/
00184 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00185   * @{
00186   */
00187
00188 /**
00189   * @brief  Checks whether the specified EXTI line flag is set or not.
00190   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00191   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00192   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00193   */
00194 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
00195
00196 /**
00197   * @brief  Clears the EXTI's line pending flags.
00198   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00199   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00200   * @retval None
00201   */
00202 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
00203
00204 /**
00205   * @brief  Checks whether the specified EXTI line is asserted or not.
00206   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00207   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00208   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00209   */
00210 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
00211
00212 /**
00213   * @brief  Clears the EXTI's line pending bits.
00214   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00215   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00216   * @retval None
00217   */
00218 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
00219
00220 /**
00221   * @brief  Generates a Software interrupt on selected EXTI line.
00222   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00223   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00224   * @retval None
00225   */
00226 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
00227 /**
00228   * @}
00229   */
00230
00231 /* Include GPIO HAL Extension module */
00232 #include "stm32f7xx_hal_gpio_ex.h"
00233
00234 /* Exported functions --------------------------------------------------------*/
00235 /** @addtogroup GPIO_Exported_Functions
00236   * @{
00237   */
00238
00239 /** @addtogroup GPIO_Exported_Functions_Group1
00240   * @{
00241   */
00242 /* Initialization and de-initialization functions *****************************/
00243 void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00244 void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00245 /**
00246   * @}
00247   */
00248
00249 /** @addtogroup GPIO_Exported_Functions_Group2
00250   * @{
00251   */
00252 /* IO operation functions *****************************************************/
00253 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00254 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00255 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00256 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00257 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00258 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00259
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @}
00266   */
00267 /* Private types -------------------------------------------------------------*/
00268 /* Private variables ---------------------------------------------------------*/
00269 /* Private constants ---------------------------------------------------------*/
00270 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00271   * @{
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /* Private macros ------------------------------------------------------------*/
00279 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00280   * @{
00281   */
00282 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00283 #define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
00284 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
00285                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
00286                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
00287                             ((MODE) == GPIO_MODE_AF_PP)              ||\
00288                             ((MODE) == GPIO_MODE_AF_OD)              ||\
00289                             ((MODE) == GPIO_MODE_IT_RISING)          ||\
00290                             ((MODE) == GPIO_MODE_IT_FALLING)         ||\
00291                             ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
00292                             ((MODE) == GPIO_MODE_EVT_RISING)         ||\
00293                             ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
00294                             ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
00295                             ((MODE) == GPIO_MODE_ANALOG))
00296 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \
00297                               ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
00298 #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
00299                             ((PULL) == GPIO_PULLDOWN))
00300 /**
00301   * @}
00302   */
00303
00304 /* Private functions ---------------------------------------------------------*/
00305 /** @defgroup GPIO_Private_Functions GPIO Private Functions
00306   * @{
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 #ifdef __cplusplus
00322 }
00323 #endif
00324
00325 #endif /* __STM32F7xx_HAL_GPIO_H */
00326
00327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_gpio_ex.h Source File

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stm32f7xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of GPIO HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_GPIO_EX_H
00040 #define __STM32F7xx_HAL_GPIO_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup GPIOEx GPIOEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
00065   * @{
00066   */
00067
00068 /**
00069   * @brief   AF 0 selection
00070   */
00071 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
00072 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00073 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00074 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
00075
00076 /**
00077   * @brief   AF 1 selection
00078   */
00079 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
00080 #define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
00081
00082 /**
00083   * @brief   AF 2 selection
00084   */
00085 #define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
00086 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
00087 #define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
00088
00089 /**
00090   * @brief   AF 3 selection
00091   */
00092 #define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
00093 #define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
00094 #define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
00095 #define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
00096 #define GPIO_AF3_LPTIM1        ((uint8_t)0x03)  /* LPTIM1 Alternate Function mapping */
00097 #define GPIO_AF3_CEC           ((uint8_t)0x03)  /* CEC Alternate Function mapping */
00098
00099 /**
00100   * @brief   AF 4 selection
00101   */
00102 #define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
00103 #define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
00104 #define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
00105 #define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping */
00106 #define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping */
00107
00108 /**
00109   * @brief   AF 5 selection
00110   */
00111 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
00112 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
00113 #define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
00114 #define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
00115 #define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
00116 #define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
00117
00118 /**
00119   * @brief   AF 6 selection
00120   */
00121 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
00122 #define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
00123
00124 /**
00125   * @brief   AF 7 selection
00126   */
00127 #define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
00128 #define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
00129 #define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
00130 #define GPIO_AF7_UART5         ((uint8_t)0x07)  /* UART5 Alternate Function mapping      */
00131 #define GPIO_AF7_SPDIFRX       ((uint8_t)0x07)  /* SPDIF-RX Alternate Function mapping   */
00132 #define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping       */
00133 #define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping       */
00134 /**
00135   * @brief   AF 8 selection
00136   */
00137 #define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
00138 #define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
00139 #define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
00140 #define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
00141 #define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
00142 #define GPIO_AF8_SPDIFRX       ((uint8_t)0x08)  /* SPIDIF-RX Alternate Function mapping  */
00143 #define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping  */
00144
00145
00146 /**
00147   * @brief   AF 9 selection
00148   */
00149 #define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
00150 #define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
00151 #define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
00152 #define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
00153 #define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
00154 #define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping */
00155 #if defined(STM32F746xx) || defined(STM32F756xx)
00156 #define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
00157 #endif /* STM32F746xx || STM32F756xx */
00158 /**
00159   * @brief   AF 10 selection
00160   */
00161 #define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
00162 #define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
00163 #define GPIO_AF10_QUADSPI       ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
00164 #define GPIO_AF10_SAI2          ((uint8_t)0xA)  /* SAI2 Alternate Function mapping */
00165
00166 /**
00167   * @brief   AF 11 selection
00168   */
00169 #define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
00170
00171 /**
00172   * @brief   AF 12 selection
00173   */
00174 #define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
00175 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
00176 #define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping                     */
00177
00178 /**
00179   * @brief   AF 13 selection
00180   */
00181 #define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
00182
00183 #if defined(STM32F746xx) || defined(STM32F756xx)
00184 /**
00185   * @brief   AF 14 selection
00186   */
00187 #define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
00188 #endif /* STM32F746xx || STM32F756xx */
00189 /**
00190   * @brief   AF 15 selection
00191   */
00192 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
00193
00194
00195 /**
00196   * @}
00197   */
00198
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported macro ------------------------------------------------------------*/
00204 /** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
00205   * @{
00206   */
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported functions --------------------------------------------------------*/
00212 /** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
00213   * @{
00214   */
00215 /**
00216   * @}
00217   */
00218 /* Private types -------------------------------------------------------------*/
00219 /* Private variables ---------------------------------------------------------*/
00220 /* Private constants ---------------------------------------------------------*/
00221 /** @defgroup GPIOEx_Private_Constants GPIO Private Constants
00222   * @{
00223   */
00224
00225 /**
00226   * @brief   GPIO pin available on the platform
00227   */
00228 /* Defines the available pins per GPIOs */
00229 #define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
00230 #define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
00231 #define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
00232 #define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
00233 #define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
00234 #define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
00235 #define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
00236 #define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
00237 #define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
00238 #define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
00239 #define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
00240                               GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
00241
00242 /**
00243   * @}
00244   */
00245
00246 /* Private macros ------------------------------------------------------------*/
00247 /** @defgroup GPIOEx_Private_Macros GPIO Private Macros
00248   * @{
00249   */
00250 /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
00251   * @{
00252   */
00253 #define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
00254                                               ((__GPIOx__) == (GPIOB))? 1U :\
00255                                               ((__GPIOx__) == (GPIOC))? 2U :\
00256                                               ((__GPIOx__) == (GPIOD))? 3U :\
00257                                               ((__GPIOx__) == (GPIOE))? 4U :\
00258                                               ((__GPIOx__) == (GPIOF))? 5U :\
00259                                               ((__GPIOx__) == (GPIOG))? 6U :\
00260                                               ((__GPIOx__) == (GPIOH))? 7U :\
00261                                               ((__GPIOx__) == (GPIOI))? 8U :\
00262                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
00263 /**
00264   * @}
00265   */
00266
00267 #define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
00268            ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
00269             (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
00270             (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
00271             (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
00272             (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
00273             (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
00274                         (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
00275                         (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
00276                         (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
00277                         (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
00278                         (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
00279 /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
00280   * @{
00281   */
00282 #if defined(STM32F756xx) || defined(STM32F746xx)
00283 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
00284                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
00285                           ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \
00286                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
00287                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
00288                           ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
00289                           ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
00290                           ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
00291                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
00292                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
00293                           ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
00294                           ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
00295                           ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
00296                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
00297                           ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \
00298                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \
00299                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \
00300                           ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \
00301                           ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \
00302                           ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \
00303                           ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \
00304                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \
00305                           ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
00306                           ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
00307                           ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \
00308                           ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
00309                           ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
00310                           ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \
00311                           ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \
00312                           ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF14_LTDC))
00313 #elif defined(STM32F745xx)
00314 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
00315                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
00316                           ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \
00317                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
00318                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
00319                           ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
00320                           ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
00321                           ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
00322                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
00323                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
00324                           ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
00325                           ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
00326                           ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
00327                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
00328                           ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \
00329                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \
00330                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \
00331                           ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \
00332                           ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \
00333                           ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \
00334                           ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \
00335                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \
00336                           ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
00337                           ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
00338                           ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF10_OTG_FS)    || \
00339                           ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
00340                           ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
00341                           ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \
00342                           ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT))
00343 #endif /* STM32F756xx || STM32F746xx */
00344 /**
00345   * @}
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /* Private functions ---------------------------------------------------------*/
00353 /** @defgroup GPIOEx_Private_Functions GPIO Private Functions
00354   * @{
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 #ifdef __cplusplus
00370 }
00371 #endif
00372
00373 #endif /* __STM32F7xx_HAL_GPIO_EX_H */
00374
00375 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash.c Source File

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stm32f7xx_hal_hash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_hash.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   HASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the HASH peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + HASH/HMAC Processing functions by algorithm using polling mode
00012   *           + HASH/HMAC functions by algorithm using interrupt mode
00013   *           + HASH/HMAC functions by algorithm using DMA mode
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021     The HASH HAL driver can be used as follows:
00022     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
00023         (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
00024         (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
00025             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
00026             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
00027             (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
00028         (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
00029             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00030             (+++) Configure and enable one DMA stream one for managing data transfer from
00031                 memory to peripheral (input stream). Managing data transfer from
00032                 peripheral to memory can be performed only using CPU
00033             (+++) Associate the initialized DMA handle to the HASH DMA handle
00034                 using  __HAL_LINKDMA()
00035             (+++) Configure the priority and enable the NVIC for the transfer complete
00036                 interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00037     (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
00038         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
00039         (##) For HMAC, the encryption key.
00040         (##) For HMAC, the key size used for encryption.
00041     (#)Three processing functions are available:
00042         (##) Polling mode: processing APIs are blocking functions
00043              i.e. they process the data and wait till the digest computation is finished
00044              e.g. HAL_HASH_SHA1_Start()
00045         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00046                 i.e. they process the data under interrupt
00047                 e.g. HAL_HASH_SHA1_Start_IT()
00048         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00049              not used for data transfer i.e. the data transfer is ensured by DMA
00050                 e.g. HAL_HASH_SHA1_Start_DMA()
00051     (#)When the processing function is called at first time after HAL_HASH_Init()
00052        the HASH peripheral is initialized and processes the buffer in input.
00053        After that, the digest computation is started.
00054        When processing multi-buffer use the accumulate function to write the
00055        data in the peripheral without starting the digest computation. In last
00056        buffer use the start function to input the last buffer ans start the digest
00057        computation.
00058        (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
00059        (##) write (n-1)th data buffer in the peripheral without starting the digest computation
00060        (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
00061     (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
00062     (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
00063        After that, call the finish function in order to get the digest value
00064        e.g. HAL_HASH_SHA1_Finish()
00065     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
00066
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00072   *
00073   * Redistribution and use in source and binary forms, with or without modification,
00074   * are permitted provided that the following conditions are met:
00075   *   1. Redistributions of source code must retain the above copyright notice,
00076   *      this list of conditions and the following disclaimer.
00077   *   2. Redistributions in binary form must reproduce the above copyright notice,
00078   *      this list of conditions and the following disclaimer in the documentation
00079   *      and/or other materials provided with the distribution.
00080   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00081   *      may be used to endorse or promote products derived from this software
00082   *      without specific prior written permission.
00083   *
00084   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00085   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00086   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00087   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00088   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00089   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00090   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00091   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00092   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00093   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00094   *
00095   ******************************************************************************
00096   */
00097
00098 /* Includes ------------------------------------------------------------------*/
00099 #include "stm32f7xx_hal.h"
00100
00101 /** @addtogroup STM32F7xx_HAL_Driver
00102   * @{
00103   */
00104
00105 #if defined(STM32F756xx)
00106
00107 /** @defgroup HASH HASH
00108   * @brief HASH HAL module driver.
00109   * @{
00110   */
00111 #ifdef HAL_HASH_MODULE_ENABLED
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 /* Private macro -------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118 /** @defgroup HASH_Private_Functions HASH Private Functions
00119   * @{
00120   */
00121 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
00122 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
00123 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
00124 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
00125 /**
00126   * @}
00127   */
00128
00129 /* Private functions ---------------------------------------------------------*/
00130 /** @addtogroup HASH_Private_Functions
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  DMA HASH Input Data complete callback.
00136   * @param  hdma: DMA handle
00137   * @retval None
00138   */
00139 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
00140 {
00141   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00142   uint32_t inputaddr = 0;
00143   uint32_t buffersize = 0;
00144
00145   if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
00146   {
00147     /* Disable the DMA transfer */
00148     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00149
00150     /* Change HASH peripheral state */
00151     hhash->State = HAL_HASH_STATE_READY;
00152
00153     /* Call Input data transfer complete callback */
00154     HAL_HASH_InCpltCallback(hhash);
00155   }
00156   else
00157   {
00158     /* Increment Interrupt counter */
00159     hhash->HashInCount++;
00160     /* Disable the DMA transfer before starting the next transfer */
00161     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00162
00163     if(hhash->HashInCount <= 2)
00164     {
00165       /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
00166       if(hhash->HashInCount == 1)
00167       {
00168         inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00169         buffersize = hhash->HashBuffSize;
00170       }
00171       /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
00172       else if(hhash->HashInCount == 2)
00173       {
00174         inputaddr = (uint32_t)hhash->Init.pKey;
00175         buffersize = hhash->Init.KeySize;
00176       }
00177       /* Configure the number of valid bits in last word of the message */
00178       MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
00179
00180       /* Set the HASH DMA transfer complete */
00181       hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
00182
00183       /* Enable the DMA In DMA Stream */
00184       HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
00185
00186       /* Enable DMA requests */
00187       HASH->CR |= (HASH_CR_DMAE);
00188     }
00189     else
00190     {
00191       /* Disable the DMA transfer */
00192       HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00193
00194       /* Reset the InCount */
00195       hhash->HashInCount = 0;
00196
00197       /* Change HASH peripheral state */
00198       hhash->State = HAL_HASH_STATE_READY;
00199
00200       /* Call Input data transfer complete callback */
00201       HAL_HASH_InCpltCallback(hhash);
00202     }
00203   }
00204 }
00205
00206 /**
00207   * @brief  DMA HASH communication error callback.
00208   * @param  hdma: DMA handle
00209   * @retval None
00210   */
00211 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
00212 {
00213   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00214   hhash->State= HAL_HASH_STATE_READY;
00215   HAL_HASH_ErrorCallback(hhash);
00216 }
00217
00218 /**
00219   * @brief  Writes the input buffer in data register.
00220   * @param  pInBuffer: Pointer to input buffer
00221   * @param  Size: The size of input buffer
00222   * @retval None
00223   */
00224 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
00225 {
00226   uint32_t buffercounter;
00227   uint32_t inputaddr = (uint32_t) pInBuffer;
00228
00229   for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
00230   {
00231     HASH->DIN = *(uint32_t*)inputaddr;
00232     inputaddr+=4;
00233   }
00234 }
00235
00236 /**
00237   * @brief  Provides the message digest result.
00238   * @param  pMsgDigest: Pointer to the message digest
00239   * @param  Size: The size of the message digest in bytes
00240   * @retval None
00241   */
00242 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
00243 {
00244   uint32_t msgdigest = (uint32_t)pMsgDigest;
00245
00246   switch(Size)
00247   {
00248   case 16:
00249     /* Read the message digest */
00250     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00251     msgdigest+=4;
00252     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00253     msgdigest+=4;
00254     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00255     msgdigest+=4;
00256     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00257     break;
00258   case 20:
00259     /* Read the message digest */
00260     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00261     msgdigest+=4;
00262     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00263     msgdigest+=4;
00264     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00265     msgdigest+=4;
00266     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00267     msgdigest+=4;
00268     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
00269     break;
00270   case 28:
00271     /* Read the message digest */
00272     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00273     msgdigest+=4;
00274     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00275     msgdigest+=4;
00276     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00277     msgdigest+=4;
00278     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00279     msgdigest+=4;
00280     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
00281     msgdigest+=4;
00282     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
00283     msgdigest+=4;
00284     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
00285     break;
00286   case 32:
00287     /* Read the message digest */
00288     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00289     msgdigest+=4;
00290     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00291     msgdigest+=4;
00292     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00293     msgdigest+=4;
00294     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00295     msgdigest+=4;
00296     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
00297     msgdigest+=4;
00298     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
00299     msgdigest+=4;
00300     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
00301     msgdigest+=4;
00302     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
00303     break;
00304   default:
00305     break;
00306   }
00307 }
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Exported functions --------------------------------------------------------*/
00314 /** @addtogroup HASH_Exported_Functions
00315   * @{
00316   */
00317
00318
00319 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
00320  *  @brief    Initialization and Configuration functions.
00321  *
00322 @verbatim
00323  ===============================================================================
00324               ##### Initialization and de-initialization functions #####
00325  ===============================================================================
00326     [..]  This section provides functions allowing to:
00327       (+) Initialize the HASH according to the specified parameters
00328           in the HASH_InitTypeDef and creates the associated handle.
00329       (+) DeInitialize the HASH peripheral.
00330       (+) Initialize the HASH MSP.
00331       (+) DeInitialize HASH MSP.
00332
00333 @endverbatim
00334   * @{
00335   */
00336
00337 /**
00338   * @brief  Initializes the HASH according to the specified parameters in the
00339             HASH_HandleTypeDef and creates the associated handle.
00340   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00341   *         the configuration information for HASH module
00342   * @retval HAL status
00343   */
00344 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
00345 {
00346   /* Check the hash handle allocation */
00347   if(hhash == NULL)
00348   {
00349     return HAL_ERROR;
00350   }
00351
00352   /* Check the parameters */
00353   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
00354
00355   if(hhash->State == HAL_HASH_STATE_RESET)
00356   {
00357     /* Allocate lock resource and initialize it */
00358     hhash->Lock = HAL_UNLOCKED;
00359     /* Init the low level hardware */
00360     HAL_HASH_MspInit(hhash);
00361   }
00362
00363   /* Change the HASH state */
00364   hhash->State = HAL_HASH_STATE_BUSY;
00365
00366   /* Reset HashInCount, HashBuffSize and HashITCounter */
00367   hhash->HashInCount = 0;
00368   hhash->HashBuffSize = 0;
00369   hhash->HashITCounter = 0;
00370
00371   /* Set the data type */
00372   HASH->CR |= (uint32_t) (hhash->Init.DataType);
00373
00374   /* Change the HASH state */
00375   hhash->State = HAL_HASH_STATE_READY;
00376
00377   /* Set the default HASH phase */
00378   hhash->Phase = HAL_HASH_PHASE_READY;
00379
00380   /* Return function status */
00381   return HAL_OK;
00382 }
00383
00384 /**
00385   * @brief  DeInitializes the HASH peripheral.
00386   * @note   This API must be called before starting a new processing.
00387   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00388   *         the configuration information for HASH module
00389   * @retval HAL status
00390   */
00391 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
00392 {
00393   /* Check the HASH handle allocation */
00394   if(hhash == NULL)
00395   {
00396     return HAL_ERROR;
00397   }
00398
00399   /* Change the HASH state */
00400   hhash->State = HAL_HASH_STATE_BUSY;
00401
00402   /* Set the default HASH phase */
00403   hhash->Phase = HAL_HASH_PHASE_READY;
00404
00405   /* Reset HashInCount, HashBuffSize and HashITCounter */
00406   hhash->HashInCount = 0;
00407   hhash->HashBuffSize = 0;
00408   hhash->HashITCounter = 0;
00409
00410   /* DeInit the low level hardware */
00411   HAL_HASH_MspDeInit(hhash);
00412
00413   /* Change the HASH state */
00414   hhash->State = HAL_HASH_STATE_RESET;
00415
00416   /* Release Lock */
00417   __HAL_UNLOCK(hhash);
00418
00419   /* Return function status */
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief  Initializes the HASH MSP.
00425   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00426   *         the configuration information for HASH module
00427   * @retval None
00428   */
00429 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
00430 {
00431   /* Prevent unused argument(s) compilation warning */
00432   UNUSED(hhash);
00433
00434   /* NOTE: This function Should not be modified, when the callback is needed,
00435            the HAL_HASH_MspInit could be implemented in the user file
00436    */
00437 }
00438
00439 /**
00440   * @brief  DeInitializes HASH MSP.
00441   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00442   *         the configuration information for HASH module
00443   * @retval None
00444   */
00445 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
00446 {
00447   /* Prevent unused argument(s) compilation warning */
00448   UNUSED(hhash);
00449
00450   /* NOTE: This function Should not be modified, when the callback is needed,
00451            the HAL_HASH_MspDeInit could be implemented in the user file
00452    */
00453 }
00454
00455 /**
00456   * @brief  Input data transfer complete callback.
00457   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00458   *         the configuration information for HASH module
00459   * @retval None
00460   */
00461  __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
00462 {
00463   /* Prevent unused argument(s) compilation warning */
00464   UNUSED(hhash);
00465
00466   /* NOTE: This function Should not be modified, when the callback is needed,
00467            the HAL_HASH_InCpltCallback could be implemented in the user file
00468    */
00469 }
00470
00471 /**
00472   * @brief  Data transfer Error callback.
00473   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00474   *         the configuration information for HASH module
00475   * @retval None
00476   */
00477  __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
00478 {
00479   /* Prevent unused argument(s) compilation warning */
00480   UNUSED(hhash);
00481
00482   /* NOTE: This function Should not be modified, when the callback is needed,
00483            the HAL_HASH_ErrorCallback could be implemented in the user file
00484    */
00485 }
00486
00487 /**
00488   * @brief  Digest computation complete callback. It is used only with interrupt.
00489   * @note   This callback is not relevant with DMA.
00490   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00491   *         the configuration information for HASH module
00492   * @retval None
00493   */
00494  __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
00495 {
00496   /* Prevent unused argument(s) compilation warning */
00497   UNUSED(hhash);
00498
00499   /* NOTE: This function Should not be modified, when the callback is needed,
00500            the HAL_HASH_DgstCpltCallback could be implemented in the user file
00501    */
00502 }
00503
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
00509  *  @brief   processing functions using polling mode
00510  *
00511 @verbatim
00512  ===============================================================================
00513               ##### HASH processing using polling mode functions#####
00514  ===============================================================================
00515     [..]  This section provides functions allowing to calculate in polling mode
00516           the hash value using one of the following algorithms:
00517       (+) MD5
00518       (+) SHA1
00519
00520 @endverbatim
00521   * @{
00522   */
00523
00524 /**
00525   * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
00526             The digest is available in pOutBuffer.
00527   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00528   *         the configuration information for HASH module
00529   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00530   * @param  Size: Length of the input buffer in bytes.
00531   *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
00532   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
00533   *          and appending the input buffer is no more possible.
00534   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
00535   * @param  Timeout: Timeout value
00536   * @retval HAL status
00537   */
00538 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00539 {
00540   uint32_t tickstart = 0;
00541
00542   /* Process Locked */
00543   __HAL_LOCK(hhash);
00544
00545   /* Change the HASH state */
00546   hhash->State = HAL_HASH_STATE_BUSY;
00547
00548   /* Check if initialization phase has already been performed */
00549   if(hhash->Phase == HAL_HASH_PHASE_READY)
00550   {
00551     /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
00552        the message digest of a new message */
00553     HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
00554   }
00555
00556   /* Set the phase */
00557   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00558
00559   /* Configure the number of valid bits in last word of the message */
00560   __HAL_HASH_SET_NBVALIDBITS(Size);
00561
00562   /* Write input buffer in data register */
00563   HASH_WriteData(pInBuffer, Size);
00564
00565   /* Start the digest calculation */
00566   __HAL_HASH_START_DIGEST();
00567
00568   /* Get tick */
00569   tickstart = HAL_GetTick();
00570
00571   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
00572   {
00573     /* Check for the Timeout */
00574     if(Timeout != HAL_MAX_DELAY)
00575     {
00576       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00577       {
00578         /* Change state */
00579         hhash->State = HAL_HASH_STATE_TIMEOUT;
00580
00581         /* Process Unlocked */
00582         __HAL_UNLOCK(hhash);
00583
00584         return HAL_TIMEOUT;
00585       }
00586     }
00587   }
00588
00589   /* Read the message digest */
00590   HASH_GetDigest(pOutBuffer, 16);
00591
00592   /* Change the HASH state */
00593   hhash->State = HAL_HASH_STATE_READY;
00594
00595   /* Process Unlocked */
00596   __HAL_UNLOCK(hhash);
00597
00598   /* Return function status */
00599   return HAL_OK;
00600 }
00601
00602 /**
00603   * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
00604   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00605   *         the configuration information for HASH module
00606   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00607   * @param  Size: Length of the input buffer in bytes.
00608   *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
00609   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
00610   *          and appending the input buffer is no more possible.
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00614 {
00615   /* Process Locked */
00616   __HAL_LOCK(hhash);
00617
00618   /* Change the HASH state */
00619   hhash->State = HAL_HASH_STATE_BUSY;
00620
00621   /* Check if initialization phase has already been performed */
00622   if(hhash->Phase == HAL_HASH_PHASE_READY)
00623   {
00624     /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
00625        the message digest of a new message */
00626     HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
00627   }
00628
00629   /* Set the phase */
00630   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00631
00632   /* Configure the number of valid bits in last word of the message */
00633   __HAL_HASH_SET_NBVALIDBITS(Size);
00634
00635   /* Write input buffer in data register */
00636   HASH_WriteData(pInBuffer, Size);
00637
00638   /* Change the HASH state */
00639   hhash->State = HAL_HASH_STATE_READY;
00640
00641   /* Process Unlocked */
00642   __HAL_UNLOCK(hhash);
00643
00644   /* Return function status */
00645   return HAL_OK;
00646 }
00647
00648 /**
00649   * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
00650             The digest is available in pOutBuffer.
00651   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00652   *         the configuration information for HASH module
00653   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00654   * @param  Size: Length of the input buffer in bytes.
00655   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00656   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00657   * @param  Timeout: Timeout value
00658   * @retval HAL status
00659   */
00660 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00661 {
00662   uint32_t tickstart = 0;
00663
00664   /* Process Locked */
00665   __HAL_LOCK(hhash);
00666
00667   /* Change the HASH state */
00668   hhash->State = HAL_HASH_STATE_BUSY;
00669
00670   /* Check if initialization phase has already been performed */
00671   if(hhash->Phase == HAL_HASH_PHASE_READY)
00672   {
00673     /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
00674        the message digest of a new message */
00675     HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
00676   }
00677
00678   /* Set the phase */
00679   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00680
00681   /* Configure the number of valid bits in last word of the message */
00682   __HAL_HASH_SET_NBVALIDBITS(Size);
00683
00684   /* Write input buffer in data register */
00685   HASH_WriteData(pInBuffer, Size);
00686
00687   /* Start the digest calculation */
00688   __HAL_HASH_START_DIGEST();
00689
00690   /* Get tick */
00691   tickstart = HAL_GetTick();
00692
00693   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
00694     {
00695       /* Check for the Timeout */
00696       if(Timeout != HAL_MAX_DELAY)
00697       {
00698         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00699         {
00700           /* Change state */
00701           hhash->State = HAL_HASH_STATE_TIMEOUT;
00702
00703           /* Process Unlocked */
00704           __HAL_UNLOCK(hhash);
00705
00706           return HAL_TIMEOUT;
00707         }
00708       }
00709     }
00710
00711   /* Read the message digest */
00712   HASH_GetDigest(pOutBuffer, 20);
00713
00714   /* Change the HASH state */
00715   hhash->State = HAL_HASH_STATE_READY;
00716
00717   /* Process Unlocked */
00718   __HAL_UNLOCK(hhash);
00719
00720   /* Return function status */
00721   return HAL_OK;
00722 }
00723
00724 /**
00725   * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
00726   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00727   *         the configuration information for HASH module
00728   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00729   * @param  Size: Length of the input buffer in bytes.
00730   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00731   * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
00732   * @retval HAL status
00733   */
00734 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00735 {
00736   /* Check the parameters */
00737   assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
00738
00739   /* Process Locked */
00740   __HAL_LOCK(hhash);
00741
00742   /* Change the HASH state */
00743   hhash->State = HAL_HASH_STATE_BUSY;
00744
00745   /* Check if initialization phase has already been performed */
00746   if(hhash->Phase == HAL_HASH_PHASE_READY)
00747   {
00748     /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
00749        the message digest of a new message */
00750     HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
00751   }
00752
00753   /* Set the phase */
00754   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00755
00756   /* Configure the number of valid bits in last word of the message */
00757   __HAL_HASH_SET_NBVALIDBITS(Size);
00758
00759   /* Write input buffer in data register */
00760   HASH_WriteData(pInBuffer, Size);
00761
00762   /* Change the HASH state */
00763   hhash->State = HAL_HASH_STATE_READY;
00764
00765   /* Process Unlocked */
00766   __HAL_UNLOCK(hhash);
00767
00768   /* Return function status */
00769   return HAL_OK;
00770 }
00771
00772 /**
00773   * @}
00774   */
00775
00776 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
00777  *  @brief   processing functions using interrupt mode.
00778  *
00779 @verbatim
00780  ===============================================================================
00781               ##### HASH processing using interrupt mode functions #####
00782  ===============================================================================
00783     [..]  This section provides functions allowing to calculate in interrupt mode
00784           the hash value using one of the following algorithms:
00785       (+) MD5
00786       (+) SHA1
00787
00788 @endverbatim
00789   * @{
00790   */
00791
00792 /**
00793   * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
00794   *         The digest is available in pOutBuffer.
00795   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00796   *         the configuration information for HASH module
00797   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00798   * @param  Size: Length of the input buffer in bytes.
00799   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00800   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
00801   * @retval HAL status
00802   */
00803 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00804 {
00805   uint32_t inputaddr;
00806   uint32_t outputaddr;
00807   uint32_t buffercounter;
00808   uint32_t inputcounter;
00809
00810   /* Process Locked */
00811   __HAL_LOCK(hhash);
00812
00813   if(hhash->State == HAL_HASH_STATE_READY)
00814   {
00815     /* Change the HASH state */
00816     hhash->State = HAL_HASH_STATE_BUSY;
00817
00818     hhash->HashInCount = Size;
00819     hhash->pHashInBuffPtr = pInBuffer;
00820     hhash->pHashOutBuffPtr = pOutBuffer;
00821
00822     /* Check if initialization phase has already been performed */
00823     if(hhash->Phase == HAL_HASH_PHASE_READY)
00824     {
00825       /* Select the SHA1 mode */
00826       HASH->CR |= HASH_ALGOSELECTION_MD5;
00827       /* Reset the HASH processor core, so that the HASH will be ready to compute
00828          the message digest of a new message */
00829       HASH->CR |= HASH_CR_INIT;
00830     }
00831
00832     /* Reset interrupt counter */
00833     hhash->HashITCounter = 0;
00834
00835     /* Set the phase */
00836     hhash->Phase = HAL_HASH_PHASE_PROCESS;
00837
00838     /* Process Unlocked */
00839     __HAL_UNLOCK(hhash);
00840
00841     /* Enable Interrupts */
00842     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
00843
00844     /* Return function status */
00845     return HAL_OK;
00846   }
00847   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
00848   {
00849     outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
00850     /* Read the Output block from the Output FIFO */
00851     *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
00852     outputaddr+=4;
00853     *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
00854     outputaddr+=4;
00855     *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
00856     outputaddr+=4;
00857     *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
00858
00859     if(hhash->HashInCount == 0)
00860     {
00861       /* Disable Interrupts */
00862       HASH->IMR = 0;
00863       /* Change the HASH state */
00864       hhash->State = HAL_HASH_STATE_READY;
00865       /* Call digest computation complete callback */
00866       HAL_HASH_DgstCpltCallback(hhash);
00867
00868       /* Process Unlocked */
00869       __HAL_UNLOCK(hhash);
00870
00871       /* Return function status */
00872       return HAL_OK;
00873     }
00874   }
00875
00876   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
00877   {
00878     if(hhash->HashInCount >= 68)
00879     {
00880       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00881       /* Write the Input block in the Data IN register */
00882       for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
00883       {
00884         HASH->DIN = *(uint32_t*)inputaddr;
00885         inputaddr+=4;
00886       }
00887       if(hhash->HashITCounter == 0)
00888       {
00889         HASH->DIN = *(uint32_t*)inputaddr;
00890
00891         if(hhash->HashInCount >= 68)
00892         {
00893           /* Decrement buffer counter */
00894           hhash->HashInCount -= 68;
00895           hhash->pHashInBuffPtr+= 68;
00896         }
00897         else
00898         {
00899           hhash->HashInCount = 0;
00900           hhash->pHashInBuffPtr+= hhash->HashInCount;
00901         }
00902         /* Set Interrupt counter */
00903         hhash->HashITCounter = 1;
00904       }
00905       else
00906       {
00907         /* Decrement buffer counter */
00908         hhash->HashInCount -= 64;
00909         hhash->pHashInBuffPtr+= 64;
00910       }
00911     }
00912     else
00913     {
00914       /* Get the buffer address */
00915       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00916       /* Get the buffer counter */
00917       inputcounter = hhash->HashInCount;
00918       /* Disable Interrupts */
00919       HASH->IMR &= ~(HASH_IT_DINI);
00920       /* Configure the number of valid bits in last word of the message */
00921       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
00922
00923       if((inputcounter > 4) && (inputcounter%4))
00924       {
00925         inputcounter = (inputcounter+4-inputcounter%4);
00926       }
00927       else if ((inputcounter < 4) && (inputcounter != 0))
00928       {
00929         inputcounter = 4;
00930       }
00931
00932       /* Write the Input block in the Data IN register */
00933       for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
00934       {
00935         HASH->DIN = *(uint32_t*)inputaddr;
00936         inputaddr+=4;
00937       }
00938       /* Start the digest calculation */
00939       __HAL_HASH_START_DIGEST();
00940       /* Reset buffer counter */
00941       hhash->HashInCount = 0;
00942       /* Call Input data transfer complete callback */
00943       HAL_HASH_InCpltCallback(hhash);
00944     }
00945   }
00946
00947   /* Process Unlocked */
00948   __HAL_UNLOCK(hhash);
00949
00950   /* Return function status */
00951   return HAL_OK;
00952 }
00953
00954 /**
00955   * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
00956   *         The digest is available in pOutBuffer.
00957   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00958   *         the configuration information for HASH module
00959   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00960   * @param  Size: Length of the input buffer in bytes.
00961   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00962   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00963   * @retval HAL status
00964   */
00965 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00966 {
00967   uint32_t inputaddr;
00968   uint32_t outputaddr;
00969   uint32_t buffercounter;
00970   uint32_t inputcounter;
00971
00972   /* Process Locked */
00973   __HAL_LOCK(hhash);
00974
00975   if(hhash->State == HAL_HASH_STATE_READY)
00976   {
00977     /* Change the HASH state */
00978     hhash->State = HAL_HASH_STATE_BUSY;
00979
00980     hhash->HashInCount = Size;
00981     hhash->pHashInBuffPtr = pInBuffer;
00982     hhash->pHashOutBuffPtr = pOutBuffer;
00983
00984     /* Check if initialization phase has already been performed */
00985     if(hhash->Phase == HAL_HASH_PHASE_READY)
00986     {
00987       /* Select the SHA1 mode */
00988       HASH->CR |= HASH_ALGOSELECTION_SHA1;
00989       /* Reset the HASH processor core, so that the HASH will be ready to compute
00990          the message digest of a new message */
00991       HASH->CR |= HASH_CR_INIT;
00992     }
00993
00994     /* Reset interrupt counter */
00995     hhash->HashITCounter = 0;
00996
00997     /* Set the phase */
00998     hhash->Phase = HAL_HASH_PHASE_PROCESS;
00999
01000     /* Process Unlocked */
01001     __HAL_UNLOCK(hhash);
01002
01003     /* Enable Interrupts */
01004     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
01005
01006     /* Return function status */
01007     return HAL_OK;
01008   }
01009   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
01010   {
01011     outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
01012     /* Read the Output block from the Output FIFO */
01013     *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
01014     outputaddr+=4;
01015     *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
01016     outputaddr+=4;
01017     *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
01018     outputaddr+=4;
01019     *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
01020     outputaddr+=4;
01021     *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
01022     if(hhash->HashInCount == 0)
01023     {
01024       /* Disable Interrupts */
01025       HASH->IMR = 0;
01026       /* Change the HASH state */
01027       hhash->State = HAL_HASH_STATE_READY;
01028       /* Call digest computation complete callback */
01029       HAL_HASH_DgstCpltCallback(hhash);
01030
01031       /* Process Unlocked */
01032       __HAL_UNLOCK(hhash);
01033
01034       /* Return function status */
01035       return HAL_OK;
01036     }
01037   }
01038   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01039   {
01040     if(hhash->HashInCount >= 68)
01041     {
01042       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01043       /* Write the Input block in the Data IN register */
01044       for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
01045       {
01046         HASH->DIN = *(uint32_t*)inputaddr;
01047         inputaddr+=4;
01048       }
01049       if(hhash->HashITCounter == 0)
01050       {
01051         HASH->DIN = *(uint32_t*)inputaddr;
01052
01053         if(hhash->HashInCount >= 68)
01054         {
01055           /* Decrement buffer counter */
01056           hhash->HashInCount -= 68;
01057           hhash->pHashInBuffPtr+= 68;
01058         }
01059         else
01060         {
01061           hhash->HashInCount = 0;
01062           hhash->pHashInBuffPtr+= hhash->HashInCount;
01063         }
01064         /* Set Interrupt counter */
01065         hhash->HashITCounter = 1;
01066       }
01067       else
01068       {
01069         /* Decrement buffer counter */
01070         hhash->HashInCount -= 64;
01071         hhash->pHashInBuffPtr+= 64;
01072       }
01073     }
01074     else
01075     {
01076       /* Get the buffer address */
01077       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01078       /* Get the buffer counter */
01079       inputcounter = hhash->HashInCount;
01080       /* Disable Interrupts */
01081       HASH->IMR &= ~(HASH_IT_DINI);
01082       /* Configure the number of valid bits in last word of the message */
01083       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
01084
01085       if((inputcounter > 4) && (inputcounter%4))
01086       {
01087         inputcounter = (inputcounter+4-inputcounter%4);
01088       }
01089       else if ((inputcounter < 4) && (inputcounter != 0))
01090       {
01091         inputcounter = 4;
01092       }
01093       /* Write the Input block in the Data IN register */
01094       for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
01095       {
01096         HASH->DIN = *(uint32_t*)inputaddr;
01097         inputaddr+=4;
01098       }
01099       /* Start the digest calculation */
01100       __HAL_HASH_START_DIGEST();
01101       /* Reset buffer counter */
01102       hhash->HashInCount = 0;
01103       /* Call Input data transfer complete callback */
01104       HAL_HASH_InCpltCallback(hhash);
01105     }
01106   }
01107
01108   /* Process Unlocked */
01109   __HAL_UNLOCK(hhash);
01110
01111   /* Return function status */
01112   return HAL_OK;
01113 }
01114
01115 /**
01116   * @brief This function handles HASH interrupt request.
01117   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01118   *         the configuration information for HASH module
01119   * @retval None
01120   */
01121 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
01122 {
01123   switch(HASH->CR & HASH_CR_ALGO)
01124   {
01125     case HASH_ALGOSELECTION_MD5:
01126        HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
01127     break;
01128
01129     case HASH_ALGOSELECTION_SHA1:
01130       HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
01131     break;
01132
01133     default:
01134     break;
01135   }
01136 }
01137
01138 /**
01139   * @}
01140   */
01141
01142 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
01143  *  @brief   processing functions using DMA mode.
01144  *
01145 @verbatim
01146  ===============================================================================
01147               ##### HASH processing using DMA mode functions #####
01148  ===============================================================================
01149     [..]  This section provides functions allowing to calculate in DMA mode
01150           the hash value using one of the following algorithms:
01151       (+) MD5
01152       (+) SHA1
01153
01154 @endverbatim
01155   * @{
01156   */
01157
01158 /**
01159   * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to
01160             control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
01161   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01162   *         the configuration information for HASH module
01163   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01164   * @param  Size: Length of the input buffer in bytes.
01165   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01166   * @retval HAL status
01167   */
01168 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01169 {
01170   uint32_t inputaddr  = (uint32_t)pInBuffer;
01171
01172    /* Process Locked */
01173   __HAL_LOCK(hhash);
01174
01175   /* Change the HASH state */
01176   hhash->State = HAL_HASH_STATE_BUSY;
01177
01178   /* Check if initialization phase has already been performed */
01179   if(hhash->Phase == HAL_HASH_PHASE_READY)
01180   {
01181     /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
01182        the message digest of a new message */
01183     HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
01184   }
01185
01186   /* Configure the number of valid bits in last word of the message */
01187   __HAL_HASH_SET_NBVALIDBITS(Size);
01188
01189   /* Set the phase */
01190   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01191
01192   /* Set the HASH DMA transfer complete callback */
01193   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01194   /* Set the DMA error callback */
01195   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01196
01197   /* Enable the DMA In DMA Stream */
01198   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
01199
01200   /* Enable DMA requests */
01201   HASH->CR |= (HASH_CR_DMAE);
01202
01203    /* Process Unlocked */
01204   __HAL_UNLOCK(hhash);
01205
01206   /* Return function status */
01207   return HAL_OK;
01208 }
01209
01210 /**
01211   * @brief  Returns the computed digest in MD5 mode
01212   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01213   *         the configuration information for HASH module
01214   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
01215   * @param  Timeout: Timeout value
01216   * @retval HAL status
01217   */
01218 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01219 {
01220   uint32_t tickstart = 0;
01221
01222    /* Process Locked */
01223   __HAL_LOCK(hhash);
01224
01225   /* Change HASH peripheral state */
01226   hhash->State = HAL_HASH_STATE_BUSY;
01227
01228   /* Get tick */
01229   tickstart = HAL_GetTick();
01230
01231   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01232   {
01233     /* Check for the Timeout */
01234     if(Timeout != HAL_MAX_DELAY)
01235     {
01236       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01237       {
01238         /* Change state */
01239         hhash->State = HAL_HASH_STATE_TIMEOUT;
01240
01241         /* Process Unlocked */
01242         __HAL_UNLOCK(hhash);
01243
01244         return HAL_TIMEOUT;
01245       }
01246     }
01247   }
01248
01249   /* Read the message digest */
01250   HASH_GetDigest(pOutBuffer, 16);
01251
01252   /* Change HASH peripheral state */
01253   hhash->State = HAL_HASH_STATE_READY;
01254
01255    /* Process Unlocked */
01256   __HAL_UNLOCK(hhash);
01257
01258   /* Return function status */
01259   return HAL_OK;
01260 }
01261
01262 /**
01263   * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to
01264             control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
01265   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01266   *         the configuration information for HASH module
01267   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01268   * @param  Size: Length of the input buffer in bytes.
01269   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01270   * @retval HAL status
01271   */
01272 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01273 {
01274   uint32_t inputaddr  = (uint32_t)pInBuffer;
01275
01276    /* Process Locked */
01277   __HAL_LOCK(hhash);
01278
01279   /* Change the HASH state */
01280   hhash->State = HAL_HASH_STATE_BUSY;
01281
01282   /* Check if initialization phase has already been performed */
01283   if(hhash->Phase == HAL_HASH_PHASE_READY)
01284   {
01285     /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
01286        the message digest of a new message */
01287     HASH->CR |= HASH_ALGOSELECTION_SHA1;
01288     HASH->CR |= HASH_CR_INIT;
01289   }
01290
01291   /* Configure the number of valid bits in last word of the message */
01292   __HAL_HASH_SET_NBVALIDBITS(Size);
01293
01294   /* Set the phase */
01295   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01296
01297   /* Set the HASH DMA transfer complete callback */
01298   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01299   /* Set the DMA error callback */
01300   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01301
01302   /* Enable the DMA In DMA Stream */
01303   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
01304
01305   /* Enable DMA requests */
01306   HASH->CR |= (HASH_CR_DMAE);
01307
01308    /* Process Unlocked */
01309   __HAL_UNLOCK(hhash);
01310
01311   /* Return function status */
01312   return HAL_OK;
01313 }
01314
01315 /**
01316   * @brief  Returns the computed digest in SHA1 mode.
01317   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01318   *         the configuration information for HASH module
01319   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01320   * @param  Timeout: Timeout value
01321   * @retval HAL status
01322   */
01323 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01324 {
01325   uint32_t tickstart = 0;
01326
01327    /* Process Locked */
01328   __HAL_LOCK(hhash);
01329
01330   /* Change HASH peripheral state */
01331   hhash->State = HAL_HASH_STATE_BUSY;
01332
01333   /* Get tick */
01334   tickstart = HAL_GetTick();
01335   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01336   {
01337     /* Check for the Timeout */
01338     if(Timeout != HAL_MAX_DELAY)
01339     {
01340       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01341       {
01342         /* Change state */
01343         hhash->State = HAL_HASH_STATE_TIMEOUT;
01344
01345         /* Process Unlocked */
01346         __HAL_UNLOCK(hhash);
01347
01348         return HAL_TIMEOUT;
01349       }
01350     }
01351   }
01352
01353   /* Read the message digest */
01354   HASH_GetDigest(pOutBuffer, 20);
01355
01356   /* Change HASH peripheral state */
01357   hhash->State = HAL_HASH_STATE_READY;
01358
01359    /* Process UnLock */
01360   __HAL_UNLOCK(hhash);
01361
01362   /* Return function status */
01363   return HAL_OK;
01364 }
01365
01366
01367 /**
01368   * @}
01369   */
01370
01371 /** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
01372  *  @brief   HMAC processing functions using polling mode .
01373  *
01374 @verbatim
01375  ===============================================================================
01376               ##### HMAC processing using polling mode functions #####
01377  ===============================================================================
01378     [..]  This section provides functions allowing to calculate in polling mode
01379           the HMAC value using one of the following algorithms:
01380       (+) MD5
01381       (+) SHA1
01382
01383 @endverbatim
01384   * @{
01385   */
01386
01387 /**
01388   * @brief  Initializes the HASH peripheral in HMAC MD5 mode
01389   *         then processes pInBuffer. The digest is available in pOutBuffer
01390   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01391   *         the configuration information for HASH module
01392   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01393   * @param  Size: Length of the input buffer in bytes.
01394   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01395   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01396   * @param  Timeout: Timeout value
01397   * @retval HAL status
01398   */
01399 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
01400 {
01401   uint32_t tickstart = 0;
01402
01403    /* Process Locked */
01404   __HAL_LOCK(hhash);
01405
01406   /* Change the HASH state */
01407   hhash->State = HAL_HASH_STATE_BUSY;
01408
01409   /* Check if initialization phase has already been performed */
01410   if(hhash->Phase == HAL_HASH_PHASE_READY)
01411   {
01412     /* Check if key size is greater than 64 bytes */
01413     if(hhash->Init.KeySize > 64)
01414     {
01415       /* Select the HMAC MD5 mode */
01416       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01417     }
01418     else
01419     {
01420       /* Select the HMAC MD5 mode */
01421       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01422     }
01423   }
01424
01425   /* Set the phase */
01426   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01427
01428   /************************** STEP 1 ******************************************/
01429   /* Configure the number of valid bits in last word of the message */
01430   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01431
01432   /* Write input buffer in data register */
01433   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01434
01435   /* Start the digest calculation */
01436   __HAL_HASH_START_DIGEST();
01437
01438   /* Get tick */
01439   tickstart = HAL_GetTick();
01440
01441   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01442   {
01443     /* Check for the Timeout */
01444     if(Timeout != HAL_MAX_DELAY)
01445     {
01446       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01447       {
01448         /* Change state */
01449         hhash->State = HAL_HASH_STATE_TIMEOUT;
01450
01451         /* Process Unlocked */
01452         __HAL_UNLOCK(hhash);
01453
01454         return HAL_TIMEOUT;
01455       }
01456     }
01457   }
01458   /************************** STEP 2 ******************************************/
01459   /* Configure the number of valid bits in last word of the message */
01460   __HAL_HASH_SET_NBVALIDBITS(Size);
01461
01462   /* Write input buffer in data register */
01463   HASH_WriteData(pInBuffer, Size);
01464
01465   /* Start the digest calculation */
01466   __HAL_HASH_START_DIGEST();
01467
01468   /* Get tick */
01469   tickstart = HAL_GetTick();
01470
01471   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01472   {
01473     /* Check for the Timeout */
01474     if(Timeout != HAL_MAX_DELAY)
01475     {
01476       if((HAL_GetTick() - tickstart ) > Timeout)
01477       {
01478         /* Change state */
01479         hhash->State = HAL_HASH_STATE_TIMEOUT;
01480
01481         /* Process Unlocked */
01482         __HAL_UNLOCK(hhash);
01483
01484         return HAL_TIMEOUT;
01485       }
01486     }
01487   }
01488   /************************** STEP 3 ******************************************/
01489   /* Configure the number of valid bits in last word of the message */
01490   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01491
01492   /* Write input buffer in data register */
01493   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01494
01495   /* Start the digest calculation */
01496   __HAL_HASH_START_DIGEST();
01497
01498   /* Get tick */
01499   tickstart = HAL_GetTick();
01500
01501   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01502   {
01503     /* Check for the Timeout */
01504     if(Timeout != HAL_MAX_DELAY)
01505     {
01506       if((HAL_GetTick() - tickstart ) > Timeout)
01507       {
01508         /* Change state */
01509         hhash->State = HAL_HASH_STATE_TIMEOUT;
01510
01511         /* Process Unlocked */
01512         __HAL_UNLOCK(hhash);
01513
01514         return HAL_TIMEOUT;
01515       }
01516     }
01517   }
01518
01519   /* Read the message digest */
01520   HASH_GetDigest(pOutBuffer, 16);
01521
01522   /* Change the HASH state */
01523   hhash->State = HAL_HASH_STATE_READY;
01524
01525   /* Process Unlocked */
01526   __HAL_UNLOCK(hhash);
01527
01528   /* Return function status */
01529   return HAL_OK;
01530 }
01531
01532 /**
01533   * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
01534   *         then processes pInBuffer. The digest is available in pOutBuffer.
01535   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01536   *         the configuration information for HASH module
01537   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01538   * @param   Size: Length of the input buffer in bytes.
01539   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01540   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01541   * @param  Timeout: Timeout value
01542   * @retval HAL status
01543   */
01544 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
01545 {
01546   uint32_t tickstart = 0;
01547
01548   /* Process Locked */
01549   __HAL_LOCK(hhash);
01550
01551   /* Change the HASH state */
01552   hhash->State = HAL_HASH_STATE_BUSY;
01553
01554   /* Check if initialization phase has already been performed */
01555   if(hhash->Phase == HAL_HASH_PHASE_READY)
01556   {
01557     /* Check if key size is greater than 64 bytes */
01558     if(hhash->Init.KeySize > 64)
01559     {
01560       /* Select the HMAC SHA1 mode */
01561       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01562     }
01563     else
01564     {
01565       /* Select the HMAC SHA1 mode */
01566       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01567     }
01568   }
01569
01570   /* Set the phase */
01571   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01572
01573   /************************** STEP 1 ******************************************/
01574   /* Configure the number of valid bits in last word of the message */
01575   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01576
01577   /* Write input buffer in data register */
01578   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01579
01580   /* Start the digest calculation */
01581   __HAL_HASH_START_DIGEST();
01582
01583   /* Get tick */
01584   tickstart = HAL_GetTick();
01585
01586   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01587   {
01588     /* Check for the Timeout */
01589     if(Timeout != HAL_MAX_DELAY)
01590     {
01591       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01592       {
01593         /* Change state */
01594         hhash->State = HAL_HASH_STATE_TIMEOUT;
01595
01596         /* Process Unlocked */
01597         __HAL_UNLOCK(hhash);
01598
01599         return HAL_TIMEOUT;
01600       }
01601     }
01602   }
01603   /************************** STEP 2 ******************************************/
01604   /* Configure the number of valid bits in last word of the message */
01605   __HAL_HASH_SET_NBVALIDBITS(Size);
01606
01607   /* Write input buffer in data register */
01608   HASH_WriteData(pInBuffer, Size);
01609
01610   /* Start the digest calculation */
01611   __HAL_HASH_START_DIGEST();
01612
01613   /* Get tick */
01614   tickstart = HAL_GetTick();
01615
01616   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01617   {
01618     /* Check for the Timeout */
01619     if(Timeout != HAL_MAX_DELAY)
01620     {
01621       if((HAL_GetTick() - tickstart ) > Timeout)
01622       {
01623         /* Change state */
01624         hhash->State = HAL_HASH_STATE_TIMEOUT;
01625
01626         /* Process Unlocked */
01627         __HAL_UNLOCK(hhash);
01628
01629         return HAL_TIMEOUT;
01630       }
01631     }
01632   }
01633   /************************** STEP 3 ******************************************/
01634   /* Configure the number of valid bits in last word of the message */
01635   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01636
01637   /* Write input buffer in data register */
01638   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01639
01640   /* Start the digest calculation */
01641   __HAL_HASH_START_DIGEST();
01642
01643   /* Get tick */
01644   tickstart = HAL_GetTick();
01645
01646   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01647   {
01648     /* Check for the Timeout */
01649     if(Timeout != HAL_MAX_DELAY)
01650     {
01651       if((HAL_GetTick() - tickstart ) > Timeout)
01652       {
01653         /* Change state */
01654         hhash->State = HAL_HASH_STATE_TIMEOUT;
01655
01656         /* Process Unlocked */
01657         __HAL_UNLOCK(hhash);
01658
01659         return HAL_TIMEOUT;
01660       }
01661     }
01662   }
01663   /* Read the message digest */
01664   HASH_GetDigest(pOutBuffer, 20);
01665
01666   /* Change the HASH state */
01667   hhash->State = HAL_HASH_STATE_READY;
01668
01669   /* Process Unlocked */
01670   __HAL_UNLOCK(hhash);
01671
01672   /* Return function status */
01673   return HAL_OK;
01674 }
01675
01676 /**
01677   * @}
01678   */
01679
01680 /** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
01681  *  @brief   HMAC processing functions using DMA mode .
01682  *
01683 @verbatim
01684  ===============================================================================
01685                 ##### HMAC processing using DMA mode functions #####
01686  ===============================================================================
01687     [..]  This section provides functions allowing to calculate in DMA mode
01688           the HMAC value using one of the following algorithms:
01689       (+) MD5
01690       (+) SHA1
01691
01692 @endverbatim
01693   * @{
01694   */
01695
01696 /**
01697   * @brief  Initializes the HASH peripheral in HMAC MD5 mode
01698   *         then enables DMA to control data transfer.
01699   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01700   *         the configuration information for HASH module
01701   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01702   * @param  Size: Length of the input buffer in bytes.
01703   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01704   * @retval HAL status
01705   */
01706 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01707 {
01708   uint32_t inputaddr  = 0;
01709
01710    /* Process Locked */
01711   __HAL_LOCK(hhash);
01712
01713   /* Change the HASH state */
01714   hhash->State = HAL_HASH_STATE_BUSY;
01715
01716   /* Save buffer pointer and size in handle */
01717   hhash->pHashInBuffPtr = pInBuffer;
01718   hhash->HashBuffSize = Size;
01719   hhash->HashInCount = 0;
01720
01721   /* Check if initialization phase has already been performed */
01722   if(hhash->Phase == HAL_HASH_PHASE_READY)
01723   {
01724     /* Check if key size is greater than 64 bytes */
01725     if(hhash->Init.KeySize > 64)
01726     {
01727       /* Select the HMAC MD5 mode */
01728       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01729     }
01730     else
01731     {
01732       /* Select the HMAC MD5 mode */
01733       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01734     }
01735   }
01736
01737   /* Set the phase */
01738   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01739
01740   /* Configure the number of valid bits in last word of the message */
01741   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01742
01743   /* Get the key address */
01744   inputaddr = (uint32_t)(hhash->Init.pKey);
01745
01746   /* Set the HASH DMA transfer complete callback */
01747   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01748   /* Set the DMA error callback */
01749   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01750
01751   /* Enable the DMA In DMA Stream */
01752   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
01753   /* Enable DMA requests */
01754   HASH->CR |= (HASH_CR_DMAE);
01755
01756   /* Process Unlocked */
01757   __HAL_UNLOCK(hhash);
01758
01759   /* Return function status */
01760   return HAL_OK;
01761 }
01762
01763 /**
01764   * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
01765   *         then enables DMA to control data transfer.
01766   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01767   *         the configuration information for HASH module
01768   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01769   * @param  Size: Length of the input buffer in bytes.
01770   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01771   * @retval HAL status
01772   */
01773 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01774 {
01775   uint32_t inputaddr  = 0;
01776
01777   /* Process Locked */
01778   __HAL_LOCK(hhash);
01779
01780   /* Change the HASH state */
01781   hhash->State = HAL_HASH_STATE_BUSY;
01782
01783   /* Save buffer pointer and size in handle */
01784   hhash->pHashInBuffPtr = pInBuffer;
01785   hhash->HashBuffSize = Size;
01786   hhash->HashInCount = 0;
01787
01788   /* Check if initialization phase has already been performed */
01789   if(hhash->Phase == HAL_HASH_PHASE_READY)
01790   {
01791     /* Check if key size is greater than 64 bytes */
01792     if(hhash->Init.KeySize > 64)
01793     {
01794       /* Select the HMAC SHA1 mode */
01795       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01796     }
01797     else
01798     {
01799       /* Select the HMAC SHA1 mode */
01800       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01801     }
01802   }
01803
01804   /* Set the phase */
01805   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01806
01807   /* Configure the number of valid bits in last word of the message */
01808   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01809
01810   /* Get the key address */
01811   inputaddr = (uint32_t)(hhash->Init.pKey);
01812
01813   /* Set the HASH DMA transfer complete callback */
01814   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01815   /* Set the DMA error callback */
01816   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01817
01818   /* Enable the DMA In DMA Stream */
01819   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
01820   /* Enable DMA requests */
01821   HASH->CR |= (HASH_CR_DMAE);
01822
01823   /* Process Unlocked */
01824   __HAL_UNLOCK(hhash);
01825
01826   /* Return function status */
01827   return HAL_OK;
01828 }
01829
01830 /**
01831   * @}
01832   */
01833
01834 /** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
01835  *  @brief   Peripheral State functions.
01836  *
01837 @verbatim
01838  ===============================================================================
01839                       ##### Peripheral State functions #####
01840  ===============================================================================
01841     [..]
01842     This subsection permits to get in run-time the status of the peripheral.
01843
01844 @endverbatim
01845   * @{
01846   */
01847
01848 /**
01849   * @brief return the HASH state
01850   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01851   *         the configuration information for HASH module
01852   * @retval HAL state
01853   */
01854 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
01855 {
01856   return hhash->State;
01857 }
01858
01859 /**
01860   * @}
01861   */
01862
01863 /**
01864   * @}
01865   */
01866
01867 #endif /* HAL_HASH_MODULE_ENABLED */
01868
01869 /**
01870   * @}
01871   */
01872 #endif /* STM32F756xx */
01873
01874 /**
01875   * @}
01876   */
01877
01878 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash.h Source File

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stm32f7xx_hal_hash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_hash.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of HASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_HASH_H
00040 #define __STM32F7xx_HAL_HASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F756xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HASH
00055   * @brief HASH HAL module driver
00056   *  @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup HASH_Exported_Types HASH Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
00065   * @{
00066   */
00067
00068 typedef struct
00069 {
00070   uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00071                            This parameter can be a value of @ref HASH_Data_Type */
00072
00073   uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */
00074
00075   uint8_t* pKey;      /*!< The key is used only in HMAC operation               */
00076 }HASH_InitTypeDef;
00077
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
00083   * @{
00084   */
00085
00086 typedef enum
00087 {
00088   HAL_HASH_STATE_RESET     = 0x00,  /*!< HASH not yet initialized or disabled */
00089   HAL_HASH_STATE_READY     = 0x01,  /*!< HASH initialized and ready for use   */
00090   HAL_HASH_STATE_BUSY      = 0x02,  /*!< HASH internal process is ongoing     */
00091   HAL_HASH_STATE_TIMEOUT   = 0x03,  /*!< HASH timeout state                   */
00092   HAL_HASH_STATE_ERROR     = 0x04   /*!< HASH error state                     */
00093 }HAL_HASH_StateTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
00100   * @{
00101   */
00102
00103 typedef enum
00104 {
00105   HAL_HASH_PHASE_READY     = 0x01,  /*!< HASH peripheral is ready for initialization */
00106   HAL_HASH_PHASE_PROCESS   = 0x02,  /*!< HASH peripheral is in processing phase      */
00107 }HAL_HASHPhaseTypeDef;
00108
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
00114   * @{
00115   */
00116
00117 typedef struct
00118 {
00119       HASH_InitTypeDef           Init;              /*!< HASH required parameters       */
00120
00121       uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */
00122
00123       uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */
00124
00125      __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */
00126
00127      __IO uint32_t               HashInCount;       /*!< Counter of inputed data        */
00128
00129      __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */
00130
00131       HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */
00132
00133       HAL_HASH_PhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
00134
00135       DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */
00136
00137       HAL_LockTypeDef            Lock;              /*!< HASH locking object            */
00138
00139      __IO HAL_HASH_StateTypeDef  State;             /*!< HASH peripheral state          */
00140 } HASH_HandleTypeDef;
00141
00142 /**
00143   * @}
00144   */
00145
00146
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported constants --------------------------------------------------------*/
00152 /** @defgroup HASH_Exported_Constants HASH Exported Constants
00153   * @{
00154   */
00155
00156 /** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
00157   * @{
00158   */
00159 #define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000)  /*!< HASH function is SHA1   */
00160 #define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1      /*!< HASH function is SHA224 */
00161 #define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO        /*!< HASH function is SHA256 */
00162 #define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
00168   * @{
00169   */
00170 #define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000)  /*!< Algorithm is HASH */
00171 #define HASH_ALGOMODE_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup HASH_Data_Type HASH Data Type
00177   * @{
00178   */
00179 #define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
00180 #define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
00181 #define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
00182 #define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
00188   * @brief HASH HMAC Long key used only for HMAC mode
00189   * @{
00190   */
00191 #define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000)  /*!< HMAC Key is <= 64 bytes */
00192 #define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
00198   * @{
00199   */
00200 #define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
00201 #define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
00202 #define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
00203 #define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
00204 #define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
00210   * @{
00211   */
00212 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
00213 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
00214 /**
00215   * @}
00216   */
00217
00218 /**
00219   * @}
00220   */
00221
00222 /* Exported macro ------------------------------------------------------------*/
00223 /** @defgroup HASH_Exported_Macros HASH Exported Macros
00224   * @{
00225   */
00226
00227 /** @brief Reset HASH handle state
00228   * @param  __HANDLE__: specifies the HASH handle.
00229   * @retval None
00230   */
00231 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
00232
00233 /** @brief  Check whether the specified HASH flag is set or not.
00234   * @param  __FLAG__: specifies the flag to check.
00235   *         This parameter can be one of the following values:
00236   *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
00237   *            @arg HASH_FLAG_DCIS: Digest calculation complete
00238   *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
00239   *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
00240   *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
00241   * @retval The new state of __FLAG__ (TRUE or FALSE).
00242   */
00243 #define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
00244                                                            ((HASH->SR & (__FLAG__)) == (__FLAG__)))
00245
00246 /**
00247   * @brief  Enable the multiple DMA mode.
00248   *         This feature is available only in STM32F429x and STM32F439x devices.
00249   * @retval None
00250   */
00251 #define __HAL_HASH_SET_MDMAT()          HASH->CR |= HASH_CR_MDMAT
00252
00253 /**
00254   * @brief  Disable the multiple DMA mode.
00255   * @retval None
00256   */
00257 #define __HAL_HASH_RESET_MDMAT()        HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
00258
00259 /**
00260   * @brief  Start the digest computation
00261   * @retval None
00262   */
00263 #define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL
00264
00265 /**
00266   * @brief Set the number of valid bits in last word written in Data register
00267   * @param  SIZE: size in byte of last data written in Data register.
00268   * @retval None
00269 */
00270 #define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
00271                                             HASH->STR |= 8 * ((SIZE) % 4);\
00272                                            }while(0)
00273
00274 /**
00275   * @}
00276   */
00277
00278 /* Include HASH HAL Extension module */
00279 #include "stm32f7xx_hal_hash_ex.h"
00280 /* Exported functions --------------------------------------------------------*/
00281
00282 /** @defgroup HASH_Exported_Functions HASH Exported Functions
00283   * @{
00284   */
00285
00286 /** @addtogroup HASH_Exported_Functions_Group1
00287   * @{
00288   */
00289 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
00290 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
00291 /**
00292   * @}
00293   */
00294
00295 /** @addtogroup HASH_Exported_Functions_Group2
00296   * @{
00297   */
00298 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00299 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00300 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00301 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00302 /**
00303   * @}
00304   */
00305
00306 /** @addtogroup HASH_Exported_Functions_Group3
00307   * @{
00308   */
00309 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00310 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00311 /**
00312   * @}
00313   */
00314
00315 /** @addtogroup HASH_Exported_Functions_Group4
00316   * @{
00317   */
00318 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00319 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00320 /**
00321   * @}
00322   */
00323
00324 /** @addtogroup HASH_Exported_Functions_Group5
00325   * @{
00326   */
00327 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00328 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00329 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00330 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00331 /**
00332   * @}
00333   */
00334
00335 /** @addtogroup HASH_Exported_Functions_Group6
00336   * @{
00337   */
00338 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00339 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00340 /**
00341   * @}
00342   */
00343
00344 /** @addtogroup HASH_Exported_Functions_Group7
00345   * @{
00346   */
00347 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
00348 /**
00349   * @}
00350   */
00351
00352 /** @addtogroup HASH_Exported_Functions_Group8
00353   * @{
00354   */
00355 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
00356 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
00357 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
00358 void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
00359 void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
00360 void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
00361 /**
00362   * @}
00363   */
00364
00365  /**
00366   * @}
00367   */
00368
00369  /* Private types -------------------------------------------------------------*/
00370 /** @defgroup HASH_Private_Types HASH Private Types
00371   * @{
00372   */
00373
00374 /**
00375   * @}
00376   */
00377
00378 /* Private variables ---------------------------------------------------------*/
00379 /** @defgroup HASH_Private_Variables HASH Private Variables
00380   * @{
00381   */
00382
00383 /**
00384   * @}
00385   */
00386
00387 /* Private constants ---------------------------------------------------------*/
00388 /** @defgroup HASH_Private_Constants HASH Private Constants
00389   * @{
00390   */
00391
00392 /**
00393   * @}
00394   */
00395
00396 /* Private macros ------------------------------------------------------------*/
00397 /** @defgroup HASH_Private_Macros HASH Private Macros
00398   * @{
00399   */
00400 #define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1)   || \
00401                                                   ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
00402                                                   ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
00403                                                   ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
00404
00405
00406 #define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
00407                                         ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
00408
00409
00410 #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
00411                                         ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
00412                                         ((__DATATYPE__) == HASH_DATATYPE_8B) || \
00413                                         ((__DATATYPE__) == HASH_DATATYPE_1B))
00414
00415
00416 #define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
00417                                            ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
00418
00419 #define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
00420
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Private functions ---------------------------------------------------------*/
00427 /** @defgroup HASH_Private_Functions HASH Private Functions
00428   * @{
00429   */
00430
00431 /**
00432   * @}
00433   */
00434
00435 /**
00436   * @}
00437   */
00438 #endif /* STM32F756xx */
00439 /**
00440   * @}
00441   */
00442
00443 #ifdef __cplusplus
00444 }
00445 #endif
00446
00447
00448 #endif /* __STM32F7xx_HAL_HASH_H */
00449
00450 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash_ex.c Source File

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stm32f7xx_hal_hash_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_hash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   HASH HAL Extension module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of HASH peripheral:
00010   *           + Extended HASH processing functions based on SHA224 Algorithm
00011   *           + Extended HASH processing functions based on SHA256 Algorithm
00012   *
00013   @verbatim
00014   ==============================================================================
00015                      ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018     The HASH HAL driver can be used as follows:
00019     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
00020         (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
00021         (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
00022             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
00023             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
00024             (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
00025         (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
00026             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00027             (+++) Configure and enable one DMA stream one for managing data transfer from
00028                 memory to peripheral (input stream). Managing data transfer from
00029                 peripheral to memory can be performed only using CPU
00030             (+++) Associate the initialized DMA handle to the HASH DMA handle
00031                 using  __HAL_LINKDMA()
00032             (+++) Configure the priority and enable the NVIC for the transfer complete
00033                 interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00034     (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
00035         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
00036         (##) For HMAC, the encryption key.
00037         (##) For HMAC, the key size used for encryption.
00038     (#)Three processing functions are available:
00039         (##) Polling mode: processing APIs are blocking functions
00040              i.e. they process the data and wait till the digest computation is finished
00041              e.g. HAL_HASHEx_SHA224_Start()
00042         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00043                 i.e. they process the data under interrupt
00044                 e.g. HAL_HASHEx_SHA224_Start_IT()
00045         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00046              not used for data transfer i.e. the data transfer is ensured by DMA
00047                 e.g. HAL_HASHEx_SHA224_Start_DMA()
00048     (#)When the processing function is called at first time after HAL_HASH_Init()
00049        the HASH peripheral is initialized and processes the buffer in input.
00050        After that, the digest computation is started.
00051        When processing multi-buffer use the accumulate function to write the
00052        data in the peripheral without starting the digest computation. In last
00053        buffer use the start function to input the last buffer ans start the digest
00054        computation.
00055        (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
00056        (##)  write (n-1)th data buffer in the peripheral without starting the digest computation
00057        (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
00058     (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
00059     (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
00060        After that, call the finish function in order to get the digest value
00061        e.g. HAL_HASHEx_SHA224_Finish()
00062     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00069   *
00070   * Redistribution and use in source and binary forms, with or without modification,
00071   * are permitted provided that the following conditions are met:
00072   *   1. Redistributions of source code must retain the above copyright notice,
00073   *      this list of conditions and the following disclaimer.
00074   *   2. Redistributions in binary form must reproduce the above copyright notice,
00075   *      this list of conditions and the following disclaimer in the documentation
00076   *      and/or other materials provided with the distribution.
00077   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00078   *      may be used to endorse or promote products derived from this software
00079   *      without specific prior written permission.
00080   *
00081   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00082   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00083   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00084   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00085   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00086   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00087   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00088   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00089   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00090   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00091   *
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32f7xx_hal.h"
00097
00098 /** @addtogroup STM32F7xx_HAL_Driver
00099   * @{
00100   */
00101 #if defined(STM32F756xx)
00102
00103 /** @defgroup HASHEx HASHEx
00104   * @brief HASH Extension HAL module driver.
00105   * @{
00106   */
00107
00108 #ifdef HAL_HASH_MODULE_ENABLED
00109
00110 /* Private typedef -----------------------------------------------------------*/
00111 /* Private define ------------------------------------------------------------*/
00112 /* Private macro -------------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 /* Private function prototypes -----------------------------------------------*/
00115 /** @addtogroup HASHEx_Private_Functions
00116   * @{
00117   */
00118 static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
00119 static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
00120 static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
00121 static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
00122 /**
00123   * @}
00124   */
00125
00126 /* Private functions ---------------------------------------------------------*/
00127
00128 /** @addtogroup HASHEx_Private_Functions
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Writes the input buffer in data register.
00134   * @param  pInBuffer: Pointer to input buffer
00135   * @param  Size: The size of input buffer
00136   * @retval None
00137   */
00138 static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
00139 {
00140   uint32_t buffercounter;
00141   uint32_t inputaddr = (uint32_t) pInBuffer;
00142
00143   for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
00144   {
00145     HASH->DIN = *(uint32_t*)inputaddr;
00146     inputaddr+=4;
00147   }
00148 }
00149
00150 /**
00151   * @brief  Provides the message digest result.
00152   * @param  pMsgDigest: Pointer to the message digest
00153   * @param  Size: The size of the message digest in bytes
00154   * @retval None
00155   */
00156 static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
00157 {
00158   uint32_t msgdigest = (uint32_t)pMsgDigest;
00159
00160   switch(Size)
00161   {
00162   case 16:
00163     /* Read the message digest */
00164     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00165     msgdigest+=4;
00166     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00167     msgdigest+=4;
00168     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00169     msgdigest+=4;
00170     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00171     break;
00172   case 20:
00173     /* Read the message digest */
00174     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00175     msgdigest+=4;
00176     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00177     msgdigest+=4;
00178     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00179     msgdigest+=4;
00180     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00181     msgdigest+=4;
00182     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
00183     break;
00184   case 28:
00185     /* Read the message digest */
00186     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00187     msgdigest+=4;
00188     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00189     msgdigest+=4;
00190     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00191     msgdigest+=4;
00192     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00193     msgdigest+=4;
00194     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
00195     msgdigest+=4;
00196     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
00197     msgdigest+=4;
00198     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
00199     break;
00200   case 32:
00201     /* Read the message digest */
00202     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
00203     msgdigest+=4;
00204     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
00205     msgdigest+=4;
00206     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
00207     msgdigest+=4;
00208     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
00209     msgdigest+=4;
00210     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
00211     msgdigest+=4;
00212     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
00213     msgdigest+=4;
00214     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
00215     msgdigest+=4;
00216     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
00217     break;
00218   default:
00219     break;
00220   }
00221 }
00222
00223 /**
00224   * @brief  DMA HASH Input Data complete callback.
00225   * @param  hdma: DMA handle
00226   * @retval None
00227   */
00228 static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
00229 {
00230   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00231   uint32_t inputaddr = 0;
00232   uint32_t buffersize = 0;
00233
00234   if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
00235   {
00236     /* Disable the DMA transfer */
00237     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00238
00239     /* Change HASH peripheral state */
00240     hhash->State = HAL_HASH_STATE_READY;
00241
00242     /* Call Input data transfer complete callback */
00243     HAL_HASH_InCpltCallback(hhash);
00244   }
00245   else
00246   {
00247     /* Increment Interrupt counter */
00248     hhash->HashInCount++;
00249     /* Disable the DMA transfer before starting the next transfer */
00250     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00251
00252     if(hhash->HashInCount <= 2)
00253     {
00254       /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
00255       if(hhash->HashInCount == 1)
00256       {
00257         inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00258         buffersize = hhash->HashBuffSize;
00259       }
00260       /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
00261       else if(hhash->HashInCount == 2)
00262       {
00263         inputaddr = (uint32_t)hhash->Init.pKey;
00264         buffersize = hhash->Init.KeySize;
00265       }
00266       /* Configure the number of valid bits in last word of the message */
00267       MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
00268
00269       /* Set the HASH DMA transfer complete */
00270       hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
00271
00272       /* Enable the DMA In DMA Stream */
00273       HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
00274
00275       /* Enable DMA requests */
00276       HASH->CR |= (HASH_CR_DMAE);
00277     }
00278     else
00279     {
00280       /* Disable the DMA transfer */
00281       HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00282
00283       /* Reset the InCount */
00284       hhash->HashInCount = 0;
00285
00286       /* Change HASH peripheral state */
00287       hhash->State = HAL_HASH_STATE_READY;
00288
00289       /* Call Input data transfer complete callback */
00290       HAL_HASH_InCpltCallback(hhash);
00291     }
00292   }
00293 }
00294
00295 /**
00296   * @brief  DMA HASH communication error callback.
00297   * @param  hdma: DMA handle
00298   * @retval None
00299   */
00300 static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
00301 {
00302   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00303   hhash->State= HAL_HASH_STATE_READY;
00304   HAL_HASH_ErrorCallback(hhash);
00305 }
00306
00307  /**
00308   * @}
00309   */
00310
00311 /* Exported functions --------------------------------------------------------*/
00312 /** @addtogroup HASHEx_Exported_Functions
00313   * @{
00314   */
00315
00316 /** @defgroup  HASHEx_Group1 HASH processing functions
00317  *  @brief   processing functions using polling mode
00318  *
00319 @verbatim
00320  ===============================================================================
00321               ##### HASH processing using polling mode functions #####
00322  ===============================================================================
00323     [..]  This section provides functions allowing to calculate in polling mode
00324           the hash value using one of the following algorithms:
00325       (+) SHA224
00326       (+) SHA256
00327
00328 @endverbatim
00329   * @{
00330   */
00331
00332 /**
00333   * @brief  Initializes the HASH peripheral in SHA224 mode
00334   *         then processes pInBuffer. The digest is available in pOutBuffer
00335   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00336   *         the configuration information for HASH module
00337   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00338   * @param  Size: Length of the input buffer in bytes.
00339   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00340   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
00341   * @param  Timeout: Specify Timeout value
00342   * @retval HAL status
00343   */
00344 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00345 {
00346   uint32_t tickstart = 0;
00347
00348   /* Process Locked */
00349   __HAL_LOCK(hhash);
00350
00351   /* Change the HASH state */
00352   hhash->State = HAL_HASH_STATE_BUSY;
00353
00354   /* Check if initialization phase has already been performed */
00355   if(hhash->Phase == HAL_HASH_PHASE_READY)
00356   {
00357     /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
00358        the message digest of a new message */
00359     HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
00360   }
00361
00362   /* Set the phase */
00363   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00364
00365   /* Configure the number of valid bits in last word of the message */
00366   __HAL_HASH_SET_NBVALIDBITS(Size);
00367
00368   /* Write input buffer in data register */
00369   HASHEx_WriteData(pInBuffer, Size);
00370
00371   /* Start the digest calculation */
00372   __HAL_HASH_START_DIGEST();
00373
00374   /* Get tick */
00375   tickstart = HAL_GetTick();
00376
00377   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00378   {
00379     /* Check for the Timeout */
00380     if(Timeout != HAL_MAX_DELAY)
00381     {
00382       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00383       {
00384         /* Change state */
00385         hhash->State = HAL_HASH_STATE_TIMEOUT;
00386
00387         /* Process Unlocked */
00388         __HAL_UNLOCK(hhash);
00389
00390         return HAL_TIMEOUT;
00391       }
00392     }
00393   }
00394
00395   /* Read the message digest */
00396   HASHEx_GetDigest(pOutBuffer, 28);
00397
00398   /* Change the HASH state */
00399   hhash->State = HAL_HASH_STATE_READY;
00400
00401   /* Process Unlocked */
00402   __HAL_UNLOCK(hhash);
00403
00404   /* Return function status */
00405   return HAL_OK;
00406 }
00407
00408 /**
00409   * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
00410             The digest is available in pOutBuffer.
00411   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00412   *         the configuration information for HASH module
00413   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00414   * @param  Size: Length of the input buffer in bytes.
00415   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00416   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
00417   * @param  Timeout: Specify Timeout value
00418   * @retval HAL status
00419   */
00420 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00421 {
00422   uint32_t tickstart = 0;
00423
00424   /* Process Locked */
00425   __HAL_LOCK(hhash);
00426
00427   /* Change the HASH state */
00428   hhash->State = HAL_HASH_STATE_BUSY;
00429
00430   /* Check if initialization phase has already been performed */
00431   if(hhash->Phase == HAL_HASH_PHASE_READY)
00432   {
00433     /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
00434        the message digest of a new message */
00435     HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
00436   }
00437
00438   /* Set the phase */
00439   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00440
00441   /* Configure the number of valid bits in last word of the message */
00442   __HAL_HASH_SET_NBVALIDBITS(Size);
00443
00444   /* Write input buffer in data register */
00445   HASHEx_WriteData(pInBuffer, Size);
00446
00447   /* Start the digest calculation */
00448   __HAL_HASH_START_DIGEST();
00449
00450   /* Get tick */
00451   tickstart = HAL_GetTick();
00452
00453   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00454   {
00455     /* Check for the Timeout */
00456     if(Timeout != HAL_MAX_DELAY)
00457     {
00458       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00459       {
00460         /* Change state */
00461         hhash->State = HAL_HASH_STATE_TIMEOUT;
00462
00463         /* Process Unlocked */
00464         __HAL_UNLOCK(hhash);
00465
00466         return HAL_TIMEOUT;
00467       }
00468     }
00469   }
00470
00471   /* Read the message digest */
00472   HASHEx_GetDigest(pOutBuffer, 32);
00473
00474   /* Change the HASH state */
00475   hhash->State = HAL_HASH_STATE_READY;
00476
00477   /* Process Unlocked */
00478   __HAL_UNLOCK(hhash);
00479
00480   /* Return function status */
00481   return HAL_OK;
00482 }
00483
00484
00485 /**
00486   * @brief  Initializes the HASH peripheral in SHA224 mode
00487   *         then processes pInBuffer. The digest is available in pOutBuffer
00488   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00489   *         the configuration information for HASH module
00490   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00491   * @param  Size: Length of the input buffer in bytes.
00492   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00493   * @retval HAL status
00494   */
00495 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00496 {
00497   /* Process Locked */
00498   __HAL_LOCK(hhash);
00499
00500   /* Change the HASH state */
00501   hhash->State = HAL_HASH_STATE_BUSY;
00502
00503   /* Check if initialization phase has already been performed */
00504   if(hhash->Phase == HAL_HASH_PHASE_READY)
00505   {
00506     /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
00507        the message digest of a new message */
00508     HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
00509   }
00510
00511   /* Set the phase */
00512   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00513
00514   /* Configure the number of valid bits in last word of the message */
00515   __HAL_HASH_SET_NBVALIDBITS(Size);
00516
00517   /* Write input buffer in data register */
00518   HASHEx_WriteData(pInBuffer, Size);
00519
00520   /* Change the HASH state */
00521   hhash->State = HAL_HASH_STATE_READY;
00522
00523   /* Process Unlocked */
00524   __HAL_UNLOCK(hhash);
00525
00526   /* Return function status */
00527   return HAL_OK;
00528 }
00529
00530
00531 /**
00532   * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
00533             The digest is available in pOutBuffer.
00534   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00535   *         the configuration information for HASH module
00536   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00537   * @param  Size: Length of the input buffer in bytes.
00538   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00542 {
00543    /* Process Locked */
00544   __HAL_LOCK(hhash);
00545
00546   /* Change the HASH state */
00547   hhash->State = HAL_HASH_STATE_BUSY;
00548
00549   /* Check if initialization phase has already been performed */
00550   if(hhash->Phase == HAL_HASH_PHASE_READY)
00551   {
00552     /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
00553        the message digest of a new message */
00554     HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
00555   }
00556
00557   /* Set the phase */
00558   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00559
00560   /* Configure the number of valid bits in last word of the message */
00561   __HAL_HASH_SET_NBVALIDBITS(Size);
00562
00563   /* Write input buffer in data register */
00564   HASHEx_WriteData(pInBuffer, Size);
00565
00566   /* Change the HASH state */
00567   hhash->State = HAL_HASH_STATE_READY;
00568
00569   /* Process Unlocked */
00570   __HAL_UNLOCK(hhash);
00571
00572   /* Return function status */
00573   return HAL_OK;
00574 }
00575
00576
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
00582  *  @brief   HMAC processing functions using polling mode .
00583  *
00584 @verbatim
00585  ===============================================================================
00586             ##### HMAC processing using polling mode functions #####
00587  ===============================================================================
00588     [..]  This section provides functions allowing to calculate in polling mode
00589           the HMAC value using one of the following algorithms:
00590       (+) SHA224
00591       (+) SHA256
00592
00593 @endverbatim
00594   * @{
00595   */
00596
00597 /**
00598   * @brief  Initializes the HASH peripheral in HMAC SHA224 mode
00599   *         then processes pInBuffer. The digest is available in pOutBuffer.
00600   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00601   *         the configuration information for HASH module
00602   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00603   * @param  Size: Length of the input buffer in bytes.
00604   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00605   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00606   * @param  Timeout: Timeout value
00607   * @retval HAL status
00608   */
00609 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00610 {
00611   uint32_t tickstart = 0;
00612
00613    /* Process Locked */
00614   __HAL_LOCK(hhash);
00615
00616   /* Change the HASH state */
00617   hhash->State = HAL_HASH_STATE_BUSY;
00618
00619   /* Check if initialization phase has already been performed */
00620   if(hhash->Phase == HAL_HASH_PHASE_READY)
00621   {
00622     /* Check if key size is greater than 64 bytes */
00623     if(hhash->Init.KeySize > 64)
00624     {
00625       /* Select the HMAC SHA224 mode */
00626       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
00627     }
00628     else
00629     {
00630       /* Select the HMAC SHA224 mode */
00631       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
00632     }
00633   }
00634
00635   /* Set the phase */
00636   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00637
00638   /************************** STEP 1 ******************************************/
00639   /* Configure the number of valid bits in last word of the message */
00640   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00641
00642   /* Write input buffer in data register */
00643   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00644
00645   /* Start the digest calculation */
00646   __HAL_HASH_START_DIGEST();
00647
00648   /* Get tick */
00649   tickstart = HAL_GetTick();
00650
00651   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00652   {
00653     /* Check for the Timeout */
00654     if(Timeout != HAL_MAX_DELAY)
00655     {
00656       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00657       {
00658         /* Change state */
00659         hhash->State = HAL_HASH_STATE_TIMEOUT;
00660
00661         /* Process Unlocked */
00662         __HAL_UNLOCK(hhash);
00663
00664         return HAL_TIMEOUT;
00665       }
00666     }
00667   }
00668   /************************** STEP 2 ******************************************/
00669   /* Configure the number of valid bits in last word of the message */
00670   __HAL_HASH_SET_NBVALIDBITS(Size);
00671
00672   /* Write input buffer in data register */
00673   HASHEx_WriteData(pInBuffer, Size);
00674
00675   /* Start the digest calculation */
00676   __HAL_HASH_START_DIGEST();
00677
00678   /* Get tick */
00679   tickstart = HAL_GetTick();
00680
00681   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00682   {
00683     /* Check for the Timeout */
00684     if(Timeout != HAL_MAX_DELAY)
00685     {
00686       if((HAL_GetTick() - tickstart ) > Timeout)
00687       {
00688         /* Change state */
00689         hhash->State = HAL_HASH_STATE_TIMEOUT;
00690
00691         /* Process Unlocked */
00692         __HAL_UNLOCK(hhash);
00693
00694         return HAL_TIMEOUT;
00695       }
00696     }
00697   }
00698   /************************** STEP 3 ******************************************/
00699   /* Configure the number of valid bits in last word of the message */
00700   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00701
00702   /* Write input buffer in data register */
00703   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00704
00705   /* Start the digest calculation */
00706   __HAL_HASH_START_DIGEST();
00707
00708   /* Get tick */
00709   tickstart = HAL_GetTick();
00710
00711   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00712   {
00713     /* Check for the Timeout */
00714     if(Timeout != HAL_MAX_DELAY)
00715     {
00716       if((HAL_GetTick() - tickstart ) > Timeout)
00717       {
00718         /* Change state */
00719         hhash->State = HAL_HASH_STATE_TIMEOUT;
00720
00721         /* Process Unlocked */
00722         __HAL_UNLOCK(hhash);
00723
00724         return HAL_TIMEOUT;
00725       }
00726     }
00727   }
00728   /* Read the message digest */
00729   HASHEx_GetDigest(pOutBuffer, 28);
00730
00731   /* Change the HASH state */
00732   hhash->State = HAL_HASH_STATE_READY;
00733
00734   /* Process Unlocked */
00735   __HAL_UNLOCK(hhash);
00736
00737   /* Return function status */
00738   return HAL_OK;
00739 }
00740
00741 /**
00742   * @brief  Initializes the HASH peripheral in HMAC SHA256 mode
00743   *         then processes pInBuffer. The digest is available in pOutBuffer
00744   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00745   *         the configuration information for HASH module
00746   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00747   * @param  Size: Length of the input buffer in bytes.
00748   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00749   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00750   * @param  Timeout: Timeout value
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00754 {
00755   uint32_t tickstart = 0;
00756
00757   /* Process Locked */
00758   __HAL_LOCK(hhash);
00759
00760   /* Change the HASH state */
00761   hhash->State = HAL_HASH_STATE_BUSY;
00762
00763   /* Check if initialization phase has already been performed */
00764   if(hhash->Phase == HAL_HASH_PHASE_READY)
00765   {
00766     /* Check if key size is greater than 64 bytes */
00767     if(hhash->Init.KeySize > 64)
00768     {
00769       /* Select the HMAC SHA256 mode */
00770       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
00771     }
00772     else
00773     {
00774       /* Select the HMAC SHA256 mode */
00775       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
00776     }
00777     /* Reset the HASH processor core, so that the HASH will be ready to compute
00778        the message digest of a new message */
00779     HASH->CR |= HASH_CR_INIT;
00780   }
00781
00782   /* Set the phase */
00783   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00784
00785   /************************** STEP 1 ******************************************/
00786   /* Configure the number of valid bits in last word of the message */
00787   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00788
00789   /* Write input buffer in data register */
00790   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00791
00792   /* Start the digest calculation */
00793   __HAL_HASH_START_DIGEST();
00794
00795   /* Get tick */
00796   tickstart = HAL_GetTick();
00797
00798   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00799   {
00800     /* Check for the Timeout */
00801     if(Timeout != HAL_MAX_DELAY)
00802     {
00803       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00804       {
00805         /* Change state */
00806         hhash->State = HAL_HASH_STATE_TIMEOUT;
00807
00808         /* Process Unlocked */
00809         __HAL_UNLOCK(hhash);
00810
00811         return HAL_TIMEOUT;
00812       }
00813     }
00814   }
00815   /************************** STEP 2 ******************************************/
00816   /* Configure the number of valid bits in last word of the message */
00817   __HAL_HASH_SET_NBVALIDBITS(Size);
00818
00819   /* Write input buffer in data register */
00820   HASHEx_WriteData(pInBuffer, Size);
00821
00822   /* Start the digest calculation */
00823   __HAL_HASH_START_DIGEST();
00824
00825   /* Get tick */
00826   tickstart = HAL_GetTick();
00827
00828   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00829   {
00830     /* Check for the Timeout */
00831     if(Timeout != HAL_MAX_DELAY)
00832     {
00833       if((HAL_GetTick() - tickstart ) > Timeout)
00834       {
00835         /* Change state */
00836         hhash->State = HAL_HASH_STATE_TIMEOUT;
00837
00838         /* Process Unlocked */
00839         __HAL_UNLOCK(hhash);
00840
00841         return HAL_TIMEOUT;
00842       }
00843     }
00844   }
00845   /************************** STEP 3 ******************************************/
00846   /* Configure the number of valid bits in last word of the message */
00847   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00848
00849   /* Write input buffer in data register */
00850   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00851
00852   /* Start the digest calculation */
00853   __HAL_HASH_START_DIGEST();
00854
00855   /* Get tick */
00856   tickstart = HAL_GetTick();
00857
00858   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00859   {
00860     /* Check for the Timeout */
00861     if(Timeout != HAL_MAX_DELAY)
00862     {
00863       if((HAL_GetTick() - tickstart ) > Timeout)
00864       {
00865         /* Change state */
00866         hhash->State = HAL_HASH_STATE_TIMEOUT;
00867
00868         /* Process Unlocked */
00869         __HAL_UNLOCK(hhash);
00870
00871         return HAL_TIMEOUT;
00872       }
00873     }
00874   }
00875   /* Read the message digest */
00876   HASHEx_GetDigest(pOutBuffer, 32);
00877
00878   /* Change the HASH state */
00879   hhash->State = HAL_HASH_STATE_READY;
00880
00881    /* Process Unlocked */
00882   __HAL_UNLOCK(hhash);
00883
00884   /* Return function status */
00885   return HAL_OK;
00886 }
00887
00888 /**
00889   * @}
00890   */
00891
00892 /** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
00893  *  @brief   processing functions using interrupt mode.
00894  *
00895 @verbatim
00896  ===============================================================================
00897               ##### HASH processing using interrupt functions #####
00898  ===============================================================================
00899     [..]  This section provides functions allowing to calculate in interrupt mode
00900           the hash value using one of the following algorithms:
00901       (+) SHA224
00902       (+) SHA256
00903
00904 @endverbatim
00905   * @{
00906   */
00907
00908 /**
00909   * @brief  Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
00910   *         The digest is available in pOutBuffer.
00911   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00912   *         the configuration information for HASH module
00913   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00914   * @param  Size: Length of the input buffer in bytes.
00915   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00916   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00917   * @retval HAL status
00918   */
00919 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00920 {
00921   uint32_t inputaddr;
00922   uint32_t buffercounter;
00923   uint32_t inputcounter;
00924
00925   /* Process Locked */
00926   __HAL_LOCK(hhash);
00927
00928   if(hhash->State == HAL_HASH_STATE_READY)
00929   {
00930     /* Change the HASH state */
00931     hhash->State = HAL_HASH_STATE_BUSY;
00932
00933     hhash->HashInCount = Size;
00934     hhash->pHashInBuffPtr = pInBuffer;
00935     hhash->pHashOutBuffPtr = pOutBuffer;
00936
00937     /* Check if initialization phase has already been performed */
00938     if(hhash->Phase == HAL_HASH_PHASE_READY)
00939     {
00940       /* Select the SHA224 mode */
00941       HASH->CR |= HASH_ALGOSELECTION_SHA224;
00942       /* Reset the HASH processor core, so that the HASH will be ready to compute
00943          the message digest of a new message */
00944       HASH->CR |= HASH_CR_INIT;
00945     }
00946     /* Reset interrupt counter */
00947     hhash->HashITCounter = 0;
00948     /* Set the phase */
00949     hhash->Phase = HAL_HASH_PHASE_PROCESS;
00950
00951     /* Process Unlocked */
00952     __HAL_UNLOCK(hhash);
00953
00954     /* Enable Interrupts */
00955     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
00956
00957     /* Return function status */
00958     return HAL_OK;
00959   }
00960   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
00961   {
00962     /* Read the message digest */
00963     HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);
00964     if(hhash->HashInCount == 0)
00965     {
00966       /* Disable Interrupts */
00967       HASH->IMR = 0;
00968       /* Change the HASH state */
00969       hhash->State = HAL_HASH_STATE_READY;
00970       /* Call digest computation complete callback */
00971       HAL_HASH_DgstCpltCallback(hhash);
00972       /* Process Unlocked */
00973       __HAL_UNLOCK(hhash);
00974
00975       /* Return function status */
00976       return HAL_OK;
00977     }
00978   }
00979   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
00980   {
00981     if(hhash->HashInCount >= 68)
00982     {
00983       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00984       /* Write the Input block in the Data IN register */
00985       for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
00986       {
00987         HASH->DIN = *(uint32_t*)inputaddr;
00988         inputaddr+=4;
00989       }
00990       if(hhash->HashITCounter == 0)
00991       {
00992         HASH->DIN = *(uint32_t*)inputaddr;
00993         if(hhash->HashInCount >= 68)
00994         {
00995           /* Decrement buffer counter */
00996           hhash->HashInCount -= 68;
00997           hhash->pHashInBuffPtr+= 68;
00998         }
00999         else
01000         {
01001            hhash->HashInCount = 0;
01002           hhash->pHashInBuffPtr+= hhash->HashInCount;
01003         }
01004         /* Set Interrupt counter */
01005         hhash->HashITCounter = 1;
01006       }
01007       else
01008       {
01009         /* Decrement buffer counter */
01010         hhash->HashInCount -= 64;
01011         hhash->pHashInBuffPtr+= 64;
01012       }
01013     }
01014     else
01015     {
01016       /* Get the buffer address */
01017       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01018       /* Get the buffer counter */
01019       inputcounter = hhash->HashInCount;
01020       /* Disable Interrupts */
01021       HASH->IMR &= ~(HASH_IT_DINI);
01022       /* Configure the number of valid bits in last word of the message */
01023       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
01024
01025       if((inputcounter > 4) && (inputcounter%4))
01026       {
01027         inputcounter = (inputcounter+4-inputcounter%4);
01028       }
01029       else if ((inputcounter < 4) && (inputcounter != 0))
01030       {
01031         inputcounter = 4;
01032       }
01033       /* Write the Input block in the Data IN register */
01034       for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
01035       {
01036         HASH->DIN = *(uint32_t*)inputaddr;
01037         inputaddr+=4;
01038       }
01039       /* Start the digest calculation */
01040       __HAL_HASH_START_DIGEST();
01041       /* Reset buffer counter */
01042       hhash->HashInCount = 0;
01043       /* Call Input data transfer complete callback */
01044       HAL_HASH_InCpltCallback(hhash);
01045     }
01046   }
01047
01048   /* Process Unlocked */
01049   __HAL_UNLOCK(hhash);
01050
01051   /* Return function status */
01052   return HAL_OK;
01053 }
01054
01055
01056 /**
01057   * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
01058   *         The digest is available in pOutBuffer.
01059   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01060   *         the configuration information for HASH module
01061   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01062   * @param  Size: Length of the input buffer in bytes.
01063   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01064   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
01068 {
01069   uint32_t inputaddr;
01070   uint32_t buffercounter;
01071   uint32_t inputcounter;
01072
01073   /* Process Locked */
01074   __HAL_LOCK(hhash);
01075
01076   if(hhash->State == HAL_HASH_STATE_READY)
01077   {
01078     /* Change the HASH state */
01079     hhash->State = HAL_HASH_STATE_BUSY;
01080
01081     hhash->HashInCount = Size;
01082     hhash->pHashInBuffPtr = pInBuffer;
01083     hhash->pHashOutBuffPtr = pOutBuffer;
01084
01085     /* Check if initialization phase has already been performed */
01086     if(hhash->Phase == HAL_HASH_PHASE_READY)
01087     {
01088       /* Select the SHA256 mode */
01089       HASH->CR |= HASH_ALGOSELECTION_SHA256;
01090       /* Reset the HASH processor core, so that the HASH will be ready to compute
01091          the message digest of a new message */
01092       HASH->CR |= HASH_CR_INIT;
01093     }
01094
01095     /* Reset interrupt counter */
01096     hhash->HashITCounter = 0;
01097
01098     /* Set the phase */
01099     hhash->Phase = HAL_HASH_PHASE_PROCESS;
01100
01101     /* Process Unlocked */
01102     __HAL_UNLOCK(hhash);
01103
01104     /* Enable Interrupts */
01105     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
01106
01107     /* Return function status */
01108     return HAL_OK;
01109   }
01110   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
01111   {
01112     /* Read the message digest */
01113     HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);
01114     if(hhash->HashInCount == 0)
01115     {
01116       /* Disable Interrupts */
01117       HASH->IMR = 0;
01118       /* Change the HASH state */
01119       hhash->State = HAL_HASH_STATE_READY;
01120       /* Call digest computation complete callback */
01121       HAL_HASH_DgstCpltCallback(hhash);
01122
01123       /* Process Unlocked */
01124       __HAL_UNLOCK(hhash);
01125
01126       /* Return function status */
01127       return HAL_OK;
01128     }
01129   }
01130   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01131   {
01132     if(hhash->HashInCount >= 68)
01133     {
01134       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01135       /* Write the Input block in the Data IN register */
01136       for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
01137       {
01138         HASH->DIN = *(uint32_t*)inputaddr;
01139         inputaddr+=4;
01140       }
01141       if(hhash->HashITCounter == 0)
01142       {
01143         HASH->DIN = *(uint32_t*)inputaddr;
01144
01145         if(hhash->HashInCount >= 68)
01146         {
01147           /* Decrement buffer counter */
01148           hhash->HashInCount -= 68;
01149           hhash->pHashInBuffPtr+= 68;
01150         }
01151         else
01152         {
01153           hhash->HashInCount = 0;
01154           hhash->pHashInBuffPtr+= hhash->HashInCount;
01155         }
01156         /* Set Interrupt counter */
01157         hhash->HashITCounter = 1;
01158       }
01159       else
01160       {
01161         /* Decrement buffer counter */
01162         hhash->HashInCount -= 64;
01163         hhash->pHashInBuffPtr+= 64;
01164       }
01165     }
01166     else
01167     {
01168       /* Get the buffer address */
01169       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01170       /* Get the buffer counter */
01171       inputcounter = hhash->HashInCount;
01172       /* Disable Interrupts */
01173       HASH->IMR &= ~(HASH_IT_DINI);
01174       /* Configure the number of valid bits in last word of the message */
01175       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
01176
01177       if((inputcounter > 4) && (inputcounter%4))
01178       {
01179         inputcounter = (inputcounter+4-inputcounter%4);
01180       }
01181       else if ((inputcounter < 4) && (inputcounter != 0))
01182       {
01183         inputcounter = 4;
01184       }
01185
01186       /* Write the Input block in the Data IN register */
01187       for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
01188       {
01189         HASH->DIN = *(uint32_t*)inputaddr;
01190         inputaddr+=4;
01191       }
01192       /* Start the digest calculation */
01193       __HAL_HASH_START_DIGEST();
01194       /* Reset buffer counter */
01195       hhash->HashInCount = 0;
01196       /* Call Input data transfer complete callback */
01197       HAL_HASH_InCpltCallback(hhash);
01198     }
01199   }
01200
01201   /* Process Unlocked */
01202   __HAL_UNLOCK(hhash);
01203
01204   /* Return function status */
01205   return HAL_OK;
01206 }
01207
01208 /**
01209   * @brief This function handles HASH interrupt request.
01210   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01211   *         the configuration information for HASH module
01212   * @retval None
01213   */
01214 void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
01215 {
01216   switch(HASH->CR & HASH_CR_ALGO)
01217   {
01218
01219     case HASH_ALGOSELECTION_SHA224:
01220        HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);
01221     break;
01222
01223     case HASH_ALGOSELECTION_SHA256:
01224       HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);
01225     break;
01226
01227     default:
01228     break;
01229   }
01230 }
01231
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
01237  *  @brief   processing functions using DMA mode.
01238  *
01239 @verbatim
01240  ===============================================================================
01241                 ##### HASH processing using DMA functions #####
01242  ===============================================================================
01243     [..]  This section provides functions allowing to calculate in DMA mode
01244           the hash value using one of the following algorithms:
01245       (+) SHA224
01246       (+) SHA256
01247
01248 @endverbatim
01249   * @{
01250   */
01251
01252
01253 /**
01254   * @brief  Initializes the HASH peripheral in SHA224 mode then enables DMA to
01255             control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
01256   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01257   *         the configuration information for HASH module
01258   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01259   * @param  Size: Length of the input buffer in bytes.
01260   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01261   * @retval HAL status
01262   */
01263 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01264 {
01265   uint32_t inputaddr  = (uint32_t)pInBuffer;
01266
01267    /* Process Locked */
01268   __HAL_LOCK(hhash);
01269
01270   /* Change the HASH state */
01271   hhash->State = HAL_HASH_STATE_BUSY;
01272
01273   /* Check if initialization phase has already been performed */
01274   if(hhash->Phase == HAL_HASH_PHASE_READY)
01275   {
01276     /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
01277        the message digest of a new message */
01278     HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
01279   }
01280
01281   /* Configure the number of valid bits in last word of the message */
01282   __HAL_HASH_SET_NBVALIDBITS(Size);
01283
01284   /* Set the phase */
01285   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01286
01287   /* Set the HASH DMA transfer complete callback */
01288   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01289   /* Set the DMA error callback */
01290   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01291
01292   /* Enable the DMA In DMA Stream */
01293   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
01294
01295   /* Enable DMA requests */
01296   HASH->CR |= (HASH_CR_DMAE);
01297
01298    /* Process Unlocked */
01299   __HAL_UNLOCK(hhash);
01300
01301   /* Return function status */
01302   return HAL_OK;
01303 }
01304
01305 /**
01306   * @brief  Returns the computed digest in SHA224
01307   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01308   *         the configuration information for HASH module
01309   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
01310   * @param  Timeout: Timeout value
01311   * @retval HAL status
01312   */
01313 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01314 {
01315   uint32_t tickstart = 0;
01316
01317   /* Process Locked */
01318   __HAL_LOCK(hhash);
01319
01320   /* Change HASH peripheral state */
01321   hhash->State = HAL_HASH_STATE_BUSY;
01322
01323   /* Get tick */
01324   tickstart = HAL_GetTick();
01325
01326   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01327   {
01328     /* Check for the Timeout */
01329     if(Timeout != HAL_MAX_DELAY)
01330     {
01331       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01332       {
01333         /* Change state */
01334         hhash->State = HAL_HASH_STATE_TIMEOUT;
01335
01336         /* Process Unlocked */
01337         __HAL_UNLOCK(hhash);
01338
01339         return HAL_TIMEOUT;
01340       }
01341     }
01342   }
01343
01344   /* Read the message digest */
01345   HASHEx_GetDigest(pOutBuffer, 28);
01346
01347   /* Change HASH peripheral state */
01348   hhash->State = HAL_HASH_STATE_READY;
01349
01350    /* Process Unlocked */
01351   __HAL_UNLOCK(hhash);
01352
01353   /* Return function status */
01354   return HAL_OK;
01355 }
01356
01357 /**
01358   * @brief  Initializes the HASH peripheral in SHA256 mode then enables DMA to
01359             control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
01360   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01361   *         the configuration information for HASH module
01362   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01363   * @param  Size: Length of the input buffer in bytes.
01364   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01365   * @retval HAL status
01366   */
01367 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01368 {
01369   uint32_t inputaddr  = (uint32_t)pInBuffer;
01370
01371    /* Process Locked */
01372   __HAL_LOCK(hhash);
01373
01374   /* Change the HASH state */
01375   hhash->State = HAL_HASH_STATE_BUSY;
01376
01377   /* Check if initialization phase has already been performed */
01378   if(hhash->Phase == HAL_HASH_PHASE_READY)
01379   {
01380     /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
01381        the message digest of a new message */
01382     HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
01383   }
01384
01385   /* Configure the number of valid bits in last word of the message */
01386   __HAL_HASH_SET_NBVALIDBITS(Size);
01387
01388   /* Set the phase */
01389   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01390
01391   /* Set the HASH DMA transfer complete callback */
01392   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01393   /* Set the DMA error callback */
01394   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01395
01396   /* Enable the DMA In DMA Stream */
01397   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
01398
01399   /* Enable DMA requests */
01400   HASH->CR |= (HASH_CR_DMAE);
01401
01402    /* Process UnLock */
01403   __HAL_UNLOCK(hhash);
01404
01405   /* Return function status */
01406   return HAL_OK;
01407 }
01408
01409 /**
01410   * @brief  Returns the computed digest in SHA256.
01411   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01412   *         the configuration information for HASH module
01413   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
01414   * @param  Timeout: Timeout value
01415   * @retval HAL status
01416   */
01417 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01418 {
01419   uint32_t tickstart = 0;
01420
01421    /* Process Locked */
01422   __HAL_LOCK(hhash);
01423
01424   /* Change HASH peripheral state */
01425   hhash->State = HAL_HASH_STATE_BUSY;
01426
01427   /* Get tick */
01428   tickstart = HAL_GetTick();
01429
01430   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01431   {
01432     /* Check for the Timeout */
01433     if(Timeout != HAL_MAX_DELAY)
01434     {
01435       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01436       {
01437         /* Change state */
01438         hhash->State = HAL_HASH_STATE_TIMEOUT;
01439
01440         /* Process Unlocked */
01441         __HAL_UNLOCK(hhash);
01442
01443         return HAL_TIMEOUT;
01444       }
01445     }
01446   }
01447
01448   /* Read the message digest */
01449   HASHEx_GetDigest(pOutBuffer, 32);
01450
01451   /* Change HASH peripheral state */
01452   hhash->State = HAL_HASH_STATE_READY;
01453
01454    /* Process Unlocked */
01455   __HAL_UNLOCK(hhash);
01456
01457   /* Return function status */
01458   return HAL_OK;
01459 }
01460
01461
01462 /**
01463   * @}
01464   */
01465 /** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
01466  *  @brief   HMAC processing functions using DMA mode .
01467  *
01468 @verbatim
01469  ===============================================================================
01470                 ##### HMAC processing using DMA functions #####
01471  ===============================================================================
01472     [..]  This section provides functions allowing to calculate in DMA mode
01473           the HMAC value using one of the following algorithms:
01474       (+) SHA224
01475       (+) SHA256
01476
01477 @endverbatim
01478   * @{
01479   */
01480
01481 /**
01482   * @brief  Initializes the HASH peripheral in HMAC SHA224 mode
01483   *         then enables DMA to control data transfer.
01484   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01485   *         the configuration information for HASH module
01486   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01487   * @param  Size: Length of the input buffer in bytes.
01488   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01489   * @retval HAL status
01490   */
01491 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01492 {
01493   uint32_t inputaddr;
01494
01495   /* Process Locked */
01496   __HAL_LOCK(hhash);
01497
01498   /* Change the HASH state */
01499   hhash->State = HAL_HASH_STATE_BUSY;
01500
01501   /* Save buffer pointer and size in handle */
01502   hhash->pHashInBuffPtr = pInBuffer;
01503   hhash->HashBuffSize = Size;
01504   hhash->HashInCount = 0;
01505
01506   /* Check if initialization phase has already been performed */
01507   if(hhash->Phase == HAL_HASH_PHASE_READY)
01508   {
01509     /* Check if key size is greater than 64 bytes */
01510     if(hhash->Init.KeySize > 64)
01511     {
01512       /* Select the HMAC SHA224 mode */
01513       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01514     }
01515     else
01516     {
01517       /* Select the HMAC SHA224 mode */
01518       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01519     }
01520   }
01521
01522   /* Set the phase */
01523   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01524
01525   /* Configure the number of valid bits in last word of the message */
01526   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01527
01528   /* Get the key address */
01529   inputaddr = (uint32_t)(hhash->Init.pKey);
01530
01531   /* Set the HASH DMA transfer complete callback */
01532   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01533   /* Set the DMA error callback */
01534   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01535
01536   /* Enable the DMA In DMA Stream */
01537   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
01538   /* Enable DMA requests */
01539   HASH->CR |= (HASH_CR_DMAE);
01540
01541   /* Process Unlocked */
01542   __HAL_UNLOCK(hhash);
01543
01544   /* Return function status */
01545   return HAL_OK;
01546 }
01547
01548 /**
01549   * @brief  Initializes the HASH peripheral in HMAC SHA256 mode
01550   *         then enables DMA to control data transfer.
01551   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01552   *         the configuration information for HASH module
01553   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01554   * @param  Size: Length of the input buffer in bytes.
01555   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01556   * @retval HAL status
01557   */
01558 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01559 {
01560   uint32_t inputaddr;
01561
01562   /* Process Locked */
01563   __HAL_LOCK(hhash);
01564
01565   /* Change the HASH state */
01566   hhash->State = HAL_HASH_STATE_BUSY;
01567
01568   /* Save buffer pointer and size in handle */
01569   hhash->pHashInBuffPtr = pInBuffer;
01570   hhash->HashBuffSize = Size;
01571   hhash->HashInCount = 0;
01572
01573   /* Check if initialization phase has already been performed */
01574   if(hhash->Phase == HAL_HASH_PHASE_READY)
01575   {
01576     /* Check if key size is greater than 64 bytes */
01577     if(hhash->Init.KeySize > 64)
01578     {
01579       /* Select the HMAC SHA256 mode */
01580       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
01581     }
01582     else
01583     {
01584       /* Select the HMAC SHA256 mode */
01585       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
01586     }
01587     /* Reset the HASH processor core, so that the HASH will be ready to compute
01588        the message digest of a new message */
01589     HASH->CR |= HASH_CR_INIT;
01590   }
01591
01592   /* Set the phase */
01593   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01594
01595   /* Configure the number of valid bits in last word of the message */
01596   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01597
01598   /* Get the key address */
01599   inputaddr = (uint32_t)(hhash->Init.pKey);
01600
01601   /* Set the HASH DMA transfer complete callback */
01602   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01603   /* Set the DMA error callback */
01604   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01605
01606   /* Enable the DMA In DMA Stream */
01607   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
01608   /* Enable DMA requests */
01609   HASH->CR |= (HASH_CR_DMAE);
01610
01611   /* Process Unlocked */
01612   __HAL_UNLOCK(hhash);
01613
01614   /* Return function status */
01615   return HAL_OK;
01616 }
01617
01618 /**
01619   * @}
01620   */
01621
01622 /**
01623   * @}
01624   */
01625 #endif /* HAL_HASH_MODULE_ENABLED */
01626
01627 /**
01628   * @}
01629   */
01630 #endif /* STM32F756xx */
01631
01632 /**
01633   * @}
01634   */
01635
01636 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hash_ex.h Source File

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stm32f7xx_hal_hash_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_hash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of HASH HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_HASH_EX_H
00040 #define __STM32F7xx_HAL_HASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F756xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HASHEx
00055   * @brief HASHEx HAL Extension module driver
00056   *  @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061 /* Exported macro ------------------------------------------------------------*/
00062 /* Exported functions --------------------------------------------------------*/
00063
00064 /** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
00065   * @{
00066   */
00067
00068 /** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
00069   * @{
00070   */
00071
00072 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00073 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00074 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00075 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
00082   * @{
00083   */
00084
00085 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00086 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00087
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using  functions
00093   * @{
00094   */
00095
00096 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00097 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
00104   * @{
00105   */
00106
00107 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00108 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00109 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00110 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00111
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
00117   * @{
00118   */
00119
00120 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00121 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
00127   * @{
00128   */
00129
00130 void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140  /* Private types -------------------------------------------------------------*/
00141 /** @defgroup HASHEx_Private_Types HASHEx Private Types
00142   * @{
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /* Private variables ---------------------------------------------------------*/
00150 /** @defgroup HASHEx_Private_Variables HASHEx Private Variables
00151   * @{
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /* Private constants ---------------------------------------------------------*/
00159 /** @defgroup HASHEx_Private_Constants HASHEx Private Constants
00160   * @{
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Private macros ------------------------------------------------------------*/
00168 /** @defgroup HASHEx_Private_Macros HASHEx Private Macros
00169   * @{
00170   */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Private functions ---------------------------------------------------------*/
00177 /** @defgroup HASHEx_Private_Functions HASHEx Private Functions
00178   * @{
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188 #endif /* STM32F756xx */
00189 /**
00190   * @}
00191   */
00192
00193 #ifdef __cplusplus
00194 }
00195 #endif
00196
00197 #endif /* __STM32F7xx_HAL_HASH_EX_H */
00198
00199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hcd.c Source File

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stm32f7xx_hal_hcd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   HCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00021        HCD_HandleTypeDef  hhcd;
00022
00023     (#)Fill parameters of Init structure in HCD handle
00024
00025     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00026
00027     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00028         (##) Enable the HCD/USB Low Level interface clock using the following macros
00029              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00030              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
00031              (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
00032
00033         (##) Initialize the related GPIO clocks
00034         (##) Configure HCD pin-out
00035         (##) Configure HCD NVIC interrupt
00036
00037     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00038         (##) hhcd.pData = phost;
00039
00040     (#)Enable HCD transmission and reception:
00041         (##) HAL_HCD_Start();
00042
00043   @endverbatim
00044   ******************************************************************************
00045   * @attention
00046   *
00047   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00048   *
00049   * Redistribution and use in source and binary forms, with or without modification,
00050   * are permitted provided that the following conditions are met:
00051   *   1. Redistributions of source code must retain the above copyright notice,
00052   *      this list of conditions and the following disclaimer.
00053   *   2. Redistributions in binary form must reproduce the above copyright notice,
00054   *      this list of conditions and the following disclaimer in the documentation
00055   *      and/or other materials provided with the distribution.
00056   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00057   *      may be used to endorse or promote products derived from this software
00058   *      without specific prior written permission.
00059   *
00060   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00061   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00062   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00063   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00064   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00065   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00066   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00067   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00068   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00069   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00070   *
00071   ******************************************************************************
00072   */
00073
00074 /* Includes ------------------------------------------------------------------*/
00075 #include "stm32f7xx_hal.h"
00076
00077 /** @addtogroup STM32F7xx_HAL_Driver
00078   * @{
00079   */
00080
00081 /** @defgroup HCD HCD
00082   * @brief HCD HAL module driver
00083   * @{
00084   */
00085
00086 #ifdef HAL_HCD_MODULE_ENABLED
00087
00088 /* Private typedef -----------------------------------------------------------*/
00089 /* Private define ------------------------------------------------------------*/
00090 /* Private macro -------------------------------------------------------------*/
00091 /* Private variables ---------------------------------------------------------*/
00092 /* Private function ----------------------------------------------------------*/
00093 /** @defgroup HCD_Private_Functions HCD Private Functions
00094   * @{
00095   */
00096 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00097 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00098 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
00099 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported functions --------------------------------------------------------*/
00105 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00106   * @{
00107   */
00108
00109 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00110  *  @brief    Initialization and Configuration functions
00111  *
00112 @verbatim
00113  ===============================================================================
00114           ##### Initialization and de-initialization functions #####
00115  ===============================================================================
00116     [..]  This section provides functions allowing to:
00117
00118 @endverbatim
00119   * @{
00120   */
00121
00122 /**
00123   * @brief  Initialize the host driver.
00124   * @param  hhcd: HCD handle
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00128 {
00129   /* Check the HCD handle allocation */
00130   if(hhcd == NULL)
00131   {
00132     return HAL_ERROR;
00133   }
00134
00135   /* Check the parameters */
00136   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00137
00138   hhcd->State = HAL_HCD_STATE_BUSY;
00139
00140   /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00141   HAL_HCD_MspInit(hhcd);
00142
00143   /* Disable the Interrupts */
00144  __HAL_HCD_DISABLE(hhcd);
00145
00146  /*Init the Core (common init.) */
00147  USB_CoreInit(hhcd->Instance, hhcd->Init);
00148
00149  /* Force Host Mode*/
00150  USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
00151
00152  /* Init Host */
00153  USB_HostInit(hhcd->Instance, hhcd->Init);
00154
00155  hhcd->State= HAL_HCD_STATE_READY;
00156
00157  return HAL_OK;
00158 }
00159
00160 /**
00161   * @brief  Initialize a host channel.
00162   * @param  hhcd: HCD handle
00163   * @param  ch_num: Channel number.
00164   *         This parameter can be a value from 1 to 15
00165   * @param  epnum: Endpoint number.
00166   *          This parameter can be a value from 1 to 15
00167   * @param  dev_address : Current device address
00168   *          This parameter can be a value from 0 to 255
00169   * @param  speed: Current device speed.
00170   *          This parameter can be one of these values:
00171   *            HCD_SPEED_HIGH: High speed mode,
00172   *            HCD_SPEED_FULL: Full speed mode,
00173   *            HCD_SPEED_LOW: Low speed mode
00174   * @param  ep_type: Endpoint Type.
00175   *          This parameter can be one of these values:
00176   *            EP_TYPE_CTRL: Control type,
00177   *            EP_TYPE_ISOC: Isochronous type,
00178   *            EP_TYPE_BULK: Bulk type,
00179   *            EP_TYPE_INTR: Interrupt type
00180   * @param  mps: Max Packet Size.
00181   *          This parameter can be a value from 0 to32K
00182   * @retval HAL status
00183   */
00184 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00185                                   uint8_t ch_num,
00186                                   uint8_t epnum,
00187                                   uint8_t dev_address,
00188                                   uint8_t speed,
00189                                   uint8_t ep_type,
00190                                   uint16_t mps)
00191 {
00192   HAL_StatusTypeDef status = HAL_OK;
00193
00194   __HAL_LOCK(hhcd);
00195
00196   hhcd->hc[ch_num].dev_addr = dev_address;
00197   hhcd->hc[ch_num].max_packet = mps;
00198   hhcd->hc[ch_num].ch_num = ch_num;
00199   hhcd->hc[ch_num].ep_type = ep_type;
00200   hhcd->hc[ch_num].ep_num = epnum & 0x7F;
00201   hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
00202   hhcd->hc[ch_num].speed = speed;
00203
00204   status =  USB_HC_Init(hhcd->Instance,
00205                         ch_num,
00206                         epnum,
00207                         dev_address,
00208                         speed,
00209                         ep_type,
00210                         mps);
00211   __HAL_UNLOCK(hhcd);
00212
00213   return status;
00214 }
00215
00216 /**
00217   * @brief  Halt a host channel.
00218   * @param  hhcd: HCD handle
00219   * @param  ch_num: Channel number.
00220   *         This parameter can be a value from 1 to 15
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00224 {
00225   HAL_StatusTypeDef status = HAL_OK;
00226
00227   __HAL_LOCK(hhcd);
00228   USB_HC_Halt(hhcd->Instance, ch_num);
00229   __HAL_UNLOCK(hhcd);
00230
00231   return status;
00232 }
00233
00234 /**
00235   * @brief  DeInitialize the host driver.
00236   * @param  hhcd: HCD handle
00237   * @retval HAL status
00238   */
00239 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00240 {
00241   /* Check the HCD handle allocation */
00242   if(hhcd == NULL)
00243   {
00244     return HAL_ERROR;
00245   }
00246
00247   hhcd->State = HAL_HCD_STATE_BUSY;
00248
00249   /* DeInit the low level hardware */
00250   HAL_HCD_MspDeInit(hhcd);
00251
00252    __HAL_HCD_DISABLE(hhcd);
00253
00254   hhcd->State = HAL_HCD_STATE_RESET;
00255
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Initialize the HCD MSP.
00261   * @param  hhcd: HCD handle
00262   * @retval None
00263   */
00264 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hhcd);
00268
00269   /* NOTE : This function Should not be modified, when the callback is needed,
00270             the HAL_HCD_MspInit could be implemented in the user file
00271    */
00272 }
00273
00274 /**
00275   * @brief  DeInitialize the HCD MSP.
00276   * @param  hhcd: HCD handle
00277   * @retval None
00278   */
00279 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00280 {
00281   /* Prevent unused argument(s) compilation warning */
00282   UNUSED(hhcd);
00283
00284   /* NOTE : This function Should not be modified, when the callback is needed,
00285             the HAL_HCD_MspDeInit could be implemented in the user file
00286    */
00287 }
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
00294   *  @brief   HCD IO operation functions
00295   *
00296 @verbatim
00297  ===============================================================================
00298                       ##### IO operation functions #####
00299  ===============================================================================
00300  [..] This subsection provides a set of functions allowing to manage the USB Host Data
00301     Transfer
00302
00303 @endverbatim
00304   * @{
00305   */
00306
00307 /**
00308   * @brief  Submit a new URB for processing.
00309   * @param  hhcd: HCD handle
00310   * @param  ch_num: Channel number.
00311   *         This parameter can be a value from 1 to 15
00312   * @param  direction: Channel number.
00313   *          This parameter can be one of these values:
00314   *           0 : Output / 1 : Input
00315   * @param  ep_type: Endpoint Type.
00316   *          This parameter can be one of these values:
00317   *            EP_TYPE_CTRL: Control type/
00318   *            EP_TYPE_ISOC: Isochronous type/
00319   *            EP_TYPE_BULK: Bulk type/
00320   *            EP_TYPE_INTR: Interrupt type/
00321   * @param  token: Endpoint Type.
00322   *          This parameter can be one of these values:
00323   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00324   * @param  pbuff: pointer to URB data
00325   * @param  length: Length of URB data
00326   * @param  do_ping: activate do ping protocol (for high speed only).
00327   *          This parameter can be one of these values:
00328   *           0 : do ping inactive / 1 : do ping active
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00332                                             uint8_t ch_num,
00333                                             uint8_t direction ,
00334                                             uint8_t ep_type,
00335                                             uint8_t token,
00336                                             uint8_t* pbuff,
00337                                             uint16_t length,
00338                                             uint8_t do_ping)
00339 {
00340   hhcd->hc[ch_num].ep_is_in = direction;
00341   hhcd->hc[ch_num].ep_type  = ep_type;
00342
00343   if(token == 0)
00344   {
00345     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
00346   }
00347   else
00348   {
00349     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00350   }
00351
00352   /* Manage Data Toggle */
00353   switch(ep_type)
00354   {
00355   case EP_TYPE_CTRL:
00356     if((token == 1) && (direction == 0)) /*send data */
00357     {
00358       if ( length == 0 )
00359       { /* For Status OUT stage, Length==0, Status Out PID = 1 */
00360         hhcd->hc[ch_num].toggle_out = 1;
00361       }
00362
00363       /* Set the Data Toggle bit as per the Flag */
00364       if ( hhcd->hc[ch_num].toggle_out == 0)
00365       { /* Put the PID 0 */
00366         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00367       }
00368       else
00369       { /* Put the PID 1 */
00370         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00371       }
00372       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00373       {
00374         hhcd->hc[ch_num].do_ping = do_ping;
00375       }
00376     }
00377     break;
00378
00379   case EP_TYPE_BULK:
00380     if(direction == 0)
00381     {
00382       /* Set the Data Toggle bit as per the Flag */
00383       if ( hhcd->hc[ch_num].toggle_out == 0)
00384       { /* Put the PID 0 */
00385         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00386       }
00387       else
00388       { /* Put the PID 1 */
00389         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00390       }
00391       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00392       {
00393         hhcd->hc[ch_num].do_ping = do_ping;
00394       }
00395     }
00396     else
00397     {
00398       if( hhcd->hc[ch_num].toggle_in == 0)
00399       {
00400         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00401       }
00402       else
00403       {
00404         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00405       }
00406     }
00407
00408     break;
00409   case EP_TYPE_INTR:
00410     if(direction == 0)
00411     {
00412       /* Set the Data Toggle bit as per the Flag */
00413       if ( hhcd->hc[ch_num].toggle_out == 0)
00414       { /* Put the PID 0 */
00415         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00416       }
00417       else
00418       { /* Put the PID 1 */
00419         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00420       }
00421     }
00422     else
00423     {
00424       if( hhcd->hc[ch_num].toggle_in == 0)
00425       {
00426         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00427       }
00428       else
00429       {
00430         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00431       }
00432     }
00433     break;
00434
00435   case EP_TYPE_ISOC:
00436     hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00437     break;
00438   }
00439
00440   hhcd->hc[ch_num].xfer_buff = pbuff;
00441   hhcd->hc[ch_num].xfer_len  = length;
00442   hhcd->hc[ch_num].urb_state =   URB_IDLE;
00443   hhcd->hc[ch_num].xfer_count = 0 ;
00444   hhcd->hc[ch_num].ch_num = ch_num;
00445   hhcd->hc[ch_num].state = HC_IDLE;
00446
00447   return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
00448 }
00449
00450 /**
00451   * @brief  Handle HCD interrupt request.
00452   * @param  hhcd: HCD handle
00453   * @retval None
00454   */
00455 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00456 {
00457   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00458   uint32_t i = 0 , interrupt = 0;
00459
00460   /* ensure that we are in device mode */
00461   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
00462   {
00463     /* avoid spurious interrupt */
00464     if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
00465     {
00466       return;
00467     }
00468
00469     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00470     {
00471      /* incorrect mode, acknowledge the interrupt */
00472       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00473     }
00474
00475     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
00476     {
00477      /* incorrect mode, acknowledge the interrupt */
00478       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
00479     }
00480
00481     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
00482     {
00483      /* incorrect mode, acknowledge the interrupt */
00484       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
00485     }
00486
00487     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
00488     {
00489      /* incorrect mode, acknowledge the interrupt */
00490       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
00491     }
00492
00493     /* Handle Host Disconnect Interrupts */
00494     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
00495     {
00496
00497       /* Cleanup HPRT */
00498       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
00499         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
00500
00501       /* Handle Host Port Interrupts */
00502       HAL_HCD_Disconnect_Callback(hhcd);
00503        USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
00504       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
00505     }
00506
00507     /* Handle Host Port Interrupts */
00508     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
00509     {
00510       HCD_Port_IRQHandler (hhcd);
00511     }
00512
00513     /* Handle Host SOF Interrupts */
00514     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
00515     {
00516       HAL_HCD_SOF_Callback(hhcd);
00517       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
00518     }
00519
00520     /* Handle Host channel Interrupts */
00521     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
00522     {
00523       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
00524       for (i = 0; i < hhcd->Init.Host_channels ; i++)
00525       {
00526         if (interrupt & (1 << i))
00527         {
00528           if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
00529           {
00530             HCD_HC_IN_IRQHandler (hhcd, i);
00531           }
00532           else
00533           {
00534             HCD_HC_OUT_IRQHandler (hhcd, i);
00535           }
00536         }
00537       }
00538       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
00539     }
00540
00541         /* Handle Rx Queue Level Interrupts */
00542     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
00543     {
00544       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00545
00546       HCD_RXQLVL_IRQHandler (hhcd);
00547
00548       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00549     }
00550   }
00551 }
00552
00553 /**
00554   * @brief  SOF callback.
00555   * @param  hhcd: HCD handle
00556   * @retval None
00557   */
00558 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00559 {
00560   /* Prevent unused argument(s) compilation warning */
00561   UNUSED(hhcd);
00562
00563   /* NOTE : This function Should not be modified, when the callback is needed,
00564             the HAL_HCD_SOF_Callback could be implemented in the user file
00565    */
00566 }
00567
00568 /**
00569   * @brief Connection Event callback.
00570   * @param  hhcd: HCD handle
00571   * @retval None
00572   */
00573 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00574 {
00575   /* Prevent unused argument(s) compilation warning */
00576   UNUSED(hhcd);
00577
00578   /* NOTE : This function Should not be modified, when the callback is needed,
00579             the HAL_HCD_Connect_Callback could be implemented in the user file
00580    */
00581 }
00582
00583 /**
00584   * @brief  Disconnection Event callback.
00585   * @param  hhcd: HCD handle
00586   * @retval None
00587   */
00588 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00589 {
00590   /* Prevent unused argument(s) compilation warning */
00591   UNUSED(hhcd);
00592
00593   /* NOTE : This function Should not be modified, when the callback is needed,
00594             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00595    */
00596 }
00597
00598 /**
00599   * @brief  Notify URB state change callback.
00600   * @param  hhcd: HCD handle
00601   * @param  chnum: Channel number.
00602   *         This parameter can be a value from 1 to 15
00603   * @param  urb_state:
00604   *          This parameter can be one of these values:
00605   *            URB_IDLE/
00606   *            URB_DONE/
00607   *            URB_NOTREADY/
00608   *            URB_NYET/
00609   *            URB_ERROR/
00610   *            URB_STALL/
00611   * @retval None
00612   */
00613 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
00614 {
00615   /* Prevent unused argument(s) compilation warning */
00616   UNUSED(hhcd);
00617
00618   /* NOTE : This function Should not be modified, when the callback is needed,
00619             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00620    */
00621 }
00622
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
00628  *  @brief   Management functions
00629  *
00630 @verbatim
00631  ===============================================================================
00632                       ##### Peripheral Control functions #####
00633  ===============================================================================
00634     [..]
00635     This subsection provides a set of functions allowing to control the HCD data
00636     transfers.
00637
00638 @endverbatim
00639   * @{
00640   */
00641
00642 /**
00643   * @brief  Start the host driver.
00644   * @param  hhcd: HCD handle
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
00648 {
00649   __HAL_LOCK(hhcd);
00650   __HAL_HCD_ENABLE(hhcd);
00651   USB_DriveVbus(hhcd->Instance, 1);
00652   __HAL_UNLOCK(hhcd);
00653   return HAL_OK;
00654 }
00655
00656 /**
00657   * @brief  Stop the host driver.
00658   * @param  hhcd: HCD handle
00659   * @retval HAL status
00660   */
00661
00662 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
00663 {
00664   __HAL_LOCK(hhcd);
00665   USB_StopHost(hhcd->Instance);
00666   __HAL_UNLOCK(hhcd);
00667   return HAL_OK;
00668 }
00669
00670 /**
00671   * @brief  Reset the host port.
00672   * @param  hhcd: HCD handle
00673   * @retval HAL status
00674   */
00675 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
00676 {
00677   return (USB_ResetPort(hhcd->Instance));
00678 }
00679
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
00685  *  @brief   Peripheral State functions
00686  *
00687 @verbatim
00688  ===============================================================================
00689                       ##### Peripheral State functions #####
00690  ===============================================================================
00691     [..]
00692     This subsection permits to get in run-time the status of the peripheral
00693     and the data flow.
00694
00695 @endverbatim
00696   * @{
00697   */
00698
00699 /**
00700   * @brief  Return the HCD handle state.
00701   * @param  hhcd: HCD handle
00702   * @retval HAL state
00703   */
00704 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
00705 {
00706   return hhcd->State;
00707 }
00708
00709 /**
00710   * @brief  Return  URB state for a channel.
00711   * @param  hhcd: HCD handle
00712   * @param  chnum: Channel number.
00713   *         This parameter can be a value from 1 to 15
00714   * @retval URB state.
00715   *          This parameter can be one of these values:
00716   *            URB_IDLE/
00717   *            URB_DONE/
00718   *            URB_NOTREADY/
00719   *            URB_NYET/
00720   *            URB_ERROR/
00721   *            URB_STALL
00722   */
00723 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00724 {
00725   return hhcd->hc[chnum].urb_state;
00726 }
00727
00728
00729 /**
00730   * @brief  Return the last host transfer size.
00731   * @param  hhcd: HCD handle
00732   * @param  chnum: Channel number.
00733   *         This parameter can be a value from 1 to 15
00734   * @retval last transfer size in byte
00735   */
00736 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00737 {
00738   return hhcd->hc[chnum].xfer_count;
00739 }
00740
00741 /**
00742   * @brief  Return the Host Channel state.
00743   * @param  hhcd: HCD handle
00744   * @param  chnum: Channel number.
00745   *         This parameter can be a value from 1 to 15
00746   * @retval Host channel state
00747   *          This parameter can be one of these values:
00748   *            HC_IDLE/
00749   *            HC_XFRC/
00750   *            HC_HALTED/
00751   *            HC_NYET/
00752   *            HC_NAK/
00753   *            HC_STALL/
00754   *            HC_XACTERR/
00755   *            HC_BBLERR/
00756   *            HC_DATATGLERR
00757   */
00758 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00759 {
00760   return hhcd->hc[chnum].state;
00761 }
00762
00763 /**
00764   * @brief  Return the current Host frame number.
00765   * @param  hhcd: HCD handle
00766   * @retval Current Host frame number
00767   */
00768 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
00769 {
00770   return (USB_GetCurrentFrame(hhcd->Instance));
00771 }
00772
00773 /**
00774   * @brief  Return the Host enumeration speed.
00775   * @param  hhcd: HCD handle
00776   * @retval Enumeration speed
00777   */
00778 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
00779 {
00780   return (USB_GetHostSpeed(hhcd->Instance));
00781 }
00782
00783 /**
00784   * @}
00785   */
00786
00787 /**
00788   * @}
00789   */
00790
00791 /** @addtogroup HCD_Private_Functions
00792   * @{
00793   */
00794 /**
00795   * @brief  Handle Host Channel IN interrupt requests.
00796   * @param  hhcd: HCD handle
00797   * @param  chnum: Channel number.
00798   *         This parameter can be a value from 1 to 15
00799   * @retval none
00800   */
00801 static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00802 {
00803   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00804   uint32_t tmpreg = 0;
00805
00806   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00807   {
00808     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00809     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00810   }
00811   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00812   {
00813     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00814   }
00815
00816   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00817   {
00818     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00819     hhcd->hc[chnum].state = HC_STALL;
00820     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00821     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00822     USB_HC_Halt(hhcd->Instance, chnum);
00823   }
00824   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
00825   {
00826     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00827     USB_HC_Halt(hhcd->Instance, chnum);
00828     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00829     hhcd->hc[chnum].state = HC_DATATGLERR;
00830     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
00831   }
00832
00833   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00834   {
00835     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00836     USB_HC_Halt(hhcd->Instance, chnum);
00837     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00838   }
00839
00840   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00841   {
00842
00843     if (hhcd->Init.dma_enable)
00844     {
00845       hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
00846                                (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
00847     }
00848
00849     hhcd->hc[chnum].state = HC_XFRC;
00850     hhcd->hc[chnum].ErrCnt = 0;
00851     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00852
00853
00854     if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00855         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00856     {
00857       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00858       USB_HC_Halt(hhcd->Instance, chnum);
00859       __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00860
00861     }
00862     else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00863     {
00864       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
00865       hhcd->hc[chnum].urb_state = URB_DONE;
00866       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00867     }
00868     hhcd->hc[chnum].toggle_in ^= 1;
00869
00870   }
00871   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
00872   {
00873     __HAL_HCD_MASK_HALT_HC_INT(chnum);
00874
00875     if(hhcd->hc[chnum].state == HC_XFRC)
00876     {
00877       hhcd->hc[chnum].urb_state  = URB_DONE;
00878     }
00879
00880     else if (hhcd->hc[chnum].state == HC_STALL)
00881     {
00882       hhcd->hc[chnum].urb_state  = URB_STALL;
00883     }
00884
00885     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
00886             (hhcd->hc[chnum].state == HC_DATATGLERR))
00887     {
00888       if(hhcd->hc[chnum].ErrCnt++ > 3)
00889       {
00890         hhcd->hc[chnum].ErrCnt = 0;
00891         hhcd->hc[chnum].urb_state = URB_ERROR;
00892       }
00893       else
00894       {
00895         hhcd->hc[chnum].urb_state = URB_NOTREADY;
00896       }
00897
00898       /* re-activate the channel  */
00899       tmpreg = USBx_HC(chnum)->HCCHAR;
00900       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00901       tmpreg |= USB_OTG_HCCHAR_CHENA;
00902       USBx_HC(chnum)->HCCHAR = tmpreg;
00903     }
00904     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
00905     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00906   }
00907
00908   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00909   {
00910     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00911      hhcd->hc[chnum].ErrCnt++;
00912      hhcd->hc[chnum].state = HC_XACTERR;
00913      USB_HC_Halt(hhcd->Instance, chnum);
00914      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
00915   }
00916   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00917   {
00918     if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00919     {
00920       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00921       USB_HC_Halt(hhcd->Instance, chnum);
00922     }
00923     else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00924          (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00925     {
00926       /* re-activate the channel  */
00927       tmpreg = USBx_HC(chnum)->HCCHAR;
00928       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00929       tmpreg |= USB_OTG_HCCHAR_CHENA;
00930       USBx_HC(chnum)->HCCHAR = tmpreg;
00931     }
00932     hhcd->hc[chnum].state = HC_NAK;
00933     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00934   }
00935 }
00936
00937 /**
00938   * @brief  Handle Host Channel OUT interrupt requests.
00939   * @param  hhcd: HCD handle
00940   * @param  chnum: Channel number.
00941   *         This parameter can be a value from 1 to 15
00942   * @retval none
00943   */
00944 static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00945 {
00946   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00947   uint32_t tmpreg = 0;
00948
00949   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00950   {
00951     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00952     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00953   }
00954   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00955   {
00956     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00957
00958     if( hhcd->hc[chnum].do_ping == 1)
00959     {
00960       hhcd->hc[chnum].state = HC_NYET;
00961       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00962       USB_HC_Halt(hhcd->Instance, chnum);
00963       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
00964     }
00965   }
00966
00967   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
00968   {
00969     hhcd->hc[chnum].state = HC_NYET;
00970     hhcd->hc[chnum].ErrCnt= 0;
00971     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00972     USB_HC_Halt(hhcd->Instance, chnum);
00973     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
00974
00975   }
00976
00977   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00978   {
00979     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00980     USB_HC_Halt(hhcd->Instance, chnum);
00981     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00982   }
00983
00984   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00985   {
00986       hhcd->hc[chnum].ErrCnt = 0;
00987     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00988     USB_HC_Halt(hhcd->Instance, chnum);
00989     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00990     hhcd->hc[chnum].state = HC_XFRC;
00991
00992   }
00993
00994   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00995   {
00996     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00997     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00998     USB_HC_Halt(hhcd->Instance, chnum);
00999     hhcd->hc[chnum].state = HC_STALL;
01000   }
01001
01002   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
01003   {
01004     hhcd->hc[chnum].ErrCnt = 0;
01005     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01006     USB_HC_Halt(hhcd->Instance, chnum);
01007     hhcd->hc[chnum].state = HC_NAK;
01008     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01009   }
01010
01011   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
01012   {
01013     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01014     USB_HC_Halt(hhcd->Instance, chnum);
01015     hhcd->hc[chnum].state = HC_XACTERR;
01016      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
01017   }
01018
01019   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
01020   {
01021     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01022     USB_HC_Halt(hhcd->Instance, chnum);
01023     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01024     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
01025     hhcd->hc[chnum].state = HC_DATATGLERR;
01026   }
01027
01028
01029   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
01030   {
01031     __HAL_HCD_MASK_HALT_HC_INT(chnum);
01032
01033     if(hhcd->hc[chnum].state == HC_XFRC)
01034     {
01035       hhcd->hc[chnum].urb_state  = URB_DONE;
01036       if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
01037       {
01038         hhcd->hc[chnum].toggle_out ^= 1;
01039       }
01040     }
01041     else if (hhcd->hc[chnum].state == HC_NAK)
01042     {
01043       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01044     }
01045
01046     else if (hhcd->hc[chnum].state == HC_NYET)
01047     {
01048       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01049       hhcd->hc[chnum].do_ping = 0;
01050     }
01051
01052     else if (hhcd->hc[chnum].state == HC_STALL)
01053     {
01054       hhcd->hc[chnum].urb_state  = URB_STALL;
01055     }
01056
01057     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
01058             (hhcd->hc[chnum].state == HC_DATATGLERR))
01059     {
01060       if(hhcd->hc[chnum].ErrCnt++ > 3)
01061       {
01062         hhcd->hc[chnum].ErrCnt = 0;
01063         hhcd->hc[chnum].urb_state = URB_ERROR;
01064       }
01065       else
01066       {
01067         hhcd->hc[chnum].urb_state = URB_NOTREADY;
01068       }
01069
01070       /* re-activate the channel  */
01071       tmpreg = USBx_HC(chnum)->HCCHAR;
01072       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01073       tmpreg |= USB_OTG_HCCHAR_CHENA;
01074       USBx_HC(chnum)->HCCHAR = tmpreg;
01075     }
01076
01077     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
01078     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
01079   }
01080 }
01081
01082 /**
01083   * @brief  Handle Rx Queue Level interrupt requests.
01084   * @param  hhcd: HCD handle
01085   * @retval none
01086   */
01087 static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
01088 {
01089   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01090   uint8_t                       channelnum =0;
01091   uint32_t                      pktsts;
01092   uint32_t                      pktcnt;
01093   uint32_t                      temp = 0;
01094   uint32_t tmpreg = 0;
01095
01096   temp = hhcd->Instance->GRXSTSP ;
01097   channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;
01098   pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;
01099   pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;
01100
01101   switch (pktsts)
01102   {
01103   case GRXSTS_PKTSTS_IN:
01104     /* Read the data into the host buffer. */
01105     if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))
01106     {
01107
01108       USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
01109
01110       /*manage multiple Xfer */
01111       hhcd->hc[channelnum].xfer_buff += pktcnt;
01112       hhcd->hc[channelnum].xfer_count  += pktcnt;
01113
01114       if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
01115       {
01116         /* re-activate the channel when more packets are expected */
01117         tmpreg = USBx_HC(channelnum)->HCCHAR;
01118         tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01119         tmpreg |= USB_OTG_HCCHAR_CHENA;
01120         USBx_HC(channelnum)->HCCHAR = tmpreg;
01121         hhcd->hc[channelnum].toggle_in ^= 1;
01122       }
01123     }
01124     break;
01125
01126   case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
01127     break;
01128   case GRXSTS_PKTSTS_IN_XFER_COMP:
01129   case GRXSTS_PKTSTS_CH_HALTED:
01130   default:
01131     break;
01132   }
01133 }
01134
01135 /**
01136   * @brief  Handle Host Port interrupt requests.
01137   * @param  hhcd: HCD handle
01138   * @retval None
01139   */
01140 static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
01141 {
01142   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01143   __IO uint32_t hprt0, hprt0_dup;
01144
01145   /* Handle Host Port Interrupts */
01146   hprt0 = USBx_HPRT0;
01147   hprt0_dup = USBx_HPRT0;
01148
01149   hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01150                  USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01151
01152   /* Check whether Port Connect detected */
01153   if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
01154   {
01155     if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
01156     {
01157       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01158       HAL_HCD_Connect_Callback(hhcd);
01159     }
01160     hprt0_dup  |= USB_OTG_HPRT_PCDET;
01161
01162   }
01163
01164   /* Check whether Port Enable Changed */
01165   if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
01166   {
01167     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
01168
01169     if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
01170     {
01171       if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
01172       {
01173         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
01174         {
01175           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
01176         }
01177         else
01178         {
01179           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
01180         }
01181       }
01182       else
01183       {
01184         if(hhcd->Init.speed == HCD_SPEED_FULL)
01185         {
01186           USBx_HOST->HFIR = (uint32_t)60000;
01187         }
01188       }
01189       HAL_HCD_Connect_Callback(hhcd);
01190
01191       if(hhcd->Init.speed == HCD_SPEED_HIGH)
01192       {
01193         USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01194       }
01195     }
01196     else
01197     {
01198       /* Cleanup HPRT */
01199       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01200         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01201
01202       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01203     }
01204   }
01205
01206   /* Check For an overcurrent */
01207   if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
01208   {
01209     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
01210   }
01211
01212   /* Clear Port Interrupts */
01213   USBx_HPRT0 = hprt0_dup;
01214 }
01215
01216 /**
01217   * @}
01218   */
01219
01220 /**
01221   * @}
01222   */
01223
01224 #endif /* HAL_HCD_MODULE_ENABLED */
01225 /**
01226   * @}
01227   */
01228
01229 /**
01230   * @}
01231   */
01232
01233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_hcd.h Source File

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stm32f7xx_hal_hcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of HCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_HCD_H
00040 #define __STM32F7xx_HAL_HCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_usb.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup HCD HCD
00054   * @brief HCD HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup HCD_Exported_Types HCD Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   HAL_HCD_STATE_RESET    = 0x00,
00069   HAL_HCD_STATE_READY    = 0x01,
00070   HAL_HCD_STATE_ERROR    = 0x02,
00071   HAL_HCD_STATE_BUSY     = 0x03,
00072   HAL_HCD_STATE_TIMEOUT  = 0x04
00073 } HCD_StateTypeDef;
00074
00075 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
00076 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
00077 typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;
00078 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
00079 typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
00085   * @{
00086   */
00087 typedef struct
00088 {
00089   HCD_TypeDef               *Instance;  /*!< Register base address    */
00090   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00091   HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
00092   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00093   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00094   void                      *pData;     /*!< Pointer Stack Handler    */
00095 } HCD_HandleTypeDef;
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00106   * @{
00107   */
00108
00109 /** @defgroup HCD_Speed HCD Speed
00110   * @{
00111   */
00112 #define HCD_SPEED_HIGH               0
00113 #define HCD_SPEED_LOW                2
00114 #define HCD_SPEED_FULL               3
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup HCD_PHY_Module HCD PHY Module
00120   * @{
00121   */
00122 #define HCD_PHY_ULPI                 1
00123 #define HCD_PHY_EMBEDDED             2
00124 /**
00125   * @}
00126   */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported macro ------------------------------------------------------------*/
00133 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00134  *  @brief macros to handle interrupts and specific clock configurations
00135  * @{
00136  */
00137 #define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
00138 #define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
00139
00140 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00141 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00142 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
00143
00144 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
00145 #define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
00146 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
00147 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
00148 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported functions --------------------------------------------------------*/
00154 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
00155   * @{
00156   */
00157
00158 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00159   * @{
00160   */
00161 HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00162 HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
00163 HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00164                                   uint8_t ch_num,
00165                                   uint8_t epnum,
00166                                   uint8_t dev_address,
00167                                   uint8_t speed,
00168                                   uint8_t ep_type,
00169                                   uint16_t mps);
00170
00171 HAL_StatusTypeDef   HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00172 void                HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00173 void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00174 /**
00175   * @}
00176   */
00177
00178 /* I/O operation functions  ***************************************************/
00179 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
00180   * @{
00181   */
00182 HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00183                                                  uint8_t pipe,
00184                                                  uint8_t direction ,
00185                                                  uint8_t ep_type,
00186                                                  uint8_t token,
00187                                                  uint8_t* pbuff,
00188                                                  uint16_t length,
00189                                                  uint8_t do_ping);
00190
00191  /* Non-Blocking mode: Interrupt */
00192 void                    HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00193 void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00194 void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00195 void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00196 void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00197                                                             uint8_t chnum,
00198                                                             HCD_URBStateTypeDef urb_state);
00199 /**
00200   * @}
00201   */
00202
00203 /* Peripheral Control functions  **********************************************/
00204 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
00205   * @{
00206   */
00207 HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00208 HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00209 HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00210 /**
00211   * @}
00212   */
00213
00214 /* Peripheral State functions  ************************************************/
00215 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
00216   * @{
00217   */
00218 HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00219 HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00220 uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00221 HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00222 uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00223 uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00224 /**
00225   * @}
00226   */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /* Private macros ------------------------------------------------------------*/
00233 /** @defgroup HCD_Private_Macros HCD Private Macros
00234  * @{
00235  */
00236 /** @defgroup HCD_Instance_definition HCD Instance definition
00237   * @{
00238   */
00239 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
00240                                        ((INSTANCE) == USB_OTG_HS))
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /* Private functions prototypes ----------------------------------------------*/
00250 /** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
00251   * @{
00252   */
00253
00254 /**
00255   * @}
00256   */
00257
00258 /* Private functions ---------------------------------------------------------*/
00259 /** @defgroup HCD_Private_Functions HCD Private Functions
00260   * @{
00261   */
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 #ifdef __cplusplus
00276 }
00277 #endif
00278
00279 #endif /* __STM32F7xx_HAL_HCD_H */
00280
00281 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c.c Source File

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stm32f7xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   I2C HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019     The I2C HAL driver can be used as follows:
00020
00021     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00022         I2C_HandleTypeDef  hi2c;
00023
00024     (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
00025         (##) Enable the I2Cx interface clock
00026         (##) I2C pins configuration
00027             (+++) Enable the clock for the I2C GPIOs
00028             (+++) Configure I2C pins as alternate function open-drain
00029         (##) NVIC configuration if you need to use interrupt process
00030             (+++) Configure the I2Cx interrupt priority
00031             (+++) Enable the NVIC I2C IRQ Channel
00032         (##) DMA Configuration if you need to use DMA process
00033             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
00034             (+++) Enable the DMAx interface clock using
00035             (+++) Configure the DMA handle parameters
00036             (+++) Configure the DMA Tx or Rx Stream
00037             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
00039
00040     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00041         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00042
00043     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00044         (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
00045
00046     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00047
00048     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00049
00050     *** Polling mode IO operation ***
00051     =================================
00052     [..]
00053       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00054       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00055       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00056       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00057
00058     *** Polling mode IO MEM operation ***
00059     =====================================
00060     [..]
00061       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00062       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00063
00064
00065     *** Interrupt mode IO operation ***
00066     ===================================
00067     [..]
00068       (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
00069       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can
00070            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
00071       (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
00072       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can
00073            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
00074       (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
00075       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can
00076            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
00077       (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
00078       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can
00079            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
00080       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00081            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00082
00083     *** Interrupt mode IO MEM operation ***
00084     =======================================
00085     [..]
00086       (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
00087           HAL_I2C_Mem_Write_IT()
00088       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback is executed and user can
00089            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
00090       (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
00091           HAL_I2C_Mem_Read_IT()
00092       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback is executed and user can
00093            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
00094       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00095            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00096
00097     *** DMA mode IO operation ***
00098     ==============================
00099     [..]
00100       (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
00101           HAL_I2C_Master_Transmit_DMA()
00102       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can
00103            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
00104       (+) Receive in master mode an amount of data in non blocking mode (DMA) using
00105           HAL_I2C_Master_Receive_DMA()
00106       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can
00107            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
00108       (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
00109           HAL_I2C_Slave_Transmit_DMA()
00110       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can
00111            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
00112       (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
00113           HAL_I2C_Slave_Receive_DMA()
00114       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can
00115            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
00116       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00117            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00118
00119     *** DMA mode IO MEM operation ***
00120     =================================
00121     [..]
00122       (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
00123           HAL_I2C_Mem_Write_DMA()
00124       (+) At Memory end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
00125            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
00126       (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
00127           HAL_I2C_Mem_Read_DMA()
00128       (+) At Memory end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
00129            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
00130       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00131            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00132
00133
00134      *** I2C HAL driver macros list ***
00135      ==================================
00136      [..]
00137        Below the list of most used macros in I2C HAL driver.
00138
00139       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00140       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00141       (+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not
00142       (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
00143       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00144       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00145
00146      [..]
00147        (@) You can refer to the I2C HAL driver header file for more useful macros
00148
00149   @endverbatim
00150   ******************************************************************************
00151   * @attention
00152   *
00153   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00154   *
00155   * Redistribution and use in source and binary forms, with or without modification,
00156   * are permitted provided that the following conditions are met:
00157   *   1. Redistributions of source code must retain the above copyright notice,
00158   *      this list of conditions and the following disclaimer.
00159   *   2. Redistributions in binary form must reproduce the above copyright notice,
00160   *      this list of conditions and the following disclaimer in the documentation
00161   *      and/or other materials provided with the distribution.
00162   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00163   *      may be used to endorse or promote products derived from this software
00164   *      without specific prior written permission.
00165   *
00166   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00167   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00168   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00169   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00170   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00171   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00172   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00173   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00174   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00175   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00176   *
00177   ******************************************************************************
00178   */
00179
00180 /* Includes ------------------------------------------------------------------*/
00181 #include "stm32f7xx_hal.h"
00182
00183 /** @addtogroup STM32F7xx_HAL_Driver
00184   * @{
00185   */
00186
00187 /** @defgroup I2C I2C HAL module driver
00188   * @brief I2C HAL module driver
00189   * @{
00190   */
00191
00192 #ifdef HAL_I2C_MODULE_ENABLED
00193
00194 /* Private typedef -----------------------------------------------------------*/
00195 /* Private constants ---------------------------------------------------------*/
00196 /** @addtogroup I2C_Private_Constants I2C Private Constants
00197   * @{
00198   */
00199 #define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
00200 #define I2C_TIMEOUT_ADDR    ((uint32_t)10000)       /* 10 s  */
00201 #define I2C_TIMEOUT_BUSY    ((uint32_t)25)          /* 25 ms */
00202 #define I2C_TIMEOUT_DIR     ((uint32_t)25)          /* 25 ms */
00203 #define I2C_TIMEOUT_RXNE    ((uint32_t)25)          /* 25 ms */
00204 #define I2C_TIMEOUT_STOPF   ((uint32_t)25)          /* 25 ms */
00205 #define I2C_TIMEOUT_TC      ((uint32_t)25)          /* 25 ms */
00206 #define I2C_TIMEOUT_TCR     ((uint32_t)25)          /* 25 ms */
00207 #define I2C_TIMEOUT_TXIS    ((uint32_t)25)          /* 25 ms */
00208 #define I2C_TIMEOUT_FLAG    ((uint32_t)25)          /* 25 ms */
00209 /**
00210   * @}
00211   */
00212
00213 /* Private macro -------------------------------------------------------------*/
00214 /* Private variables ---------------------------------------------------------*/
00215 /* Private function prototypes -----------------------------------------------*/
00216 /** @addtogroup I2C_Private_Functions I2C Private Functions
00217   * @{
00218   */
00219 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00220 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00221 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00222 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00223 static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
00224 static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
00225 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00226
00227 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
00228 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
00229 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00230 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00231 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00232 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00233 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00234
00235 static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
00236 static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);
00237
00238 static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);
00239 static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);
00240
00241 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00242 /**
00243   * @}
00244   */
00245
00246 /* Exported functions --------------------------------------------------------*/
00247
00248 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00249   * @{
00250   */
00251
00252 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00253  *  @brief    Initialization and Configuration functions
00254  *
00255 @verbatim
00256  ===============================================================================
00257               ##### Initialization and de-initialization functions #####
00258  ===============================================================================
00259     [..]  This subsection provides a set of functions allowing to initialize and
00260           de-initialize the I2Cx peripheral:
00261
00262       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00263           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00264
00265       (+) Call the function HAL_I2C_Init() to configure the selected device with
00266           the selected configuration:
00267         (++) Clock Timing
00268         (++) Own Address 1
00269         (++) Addressing mode (Master, Slave)
00270         (++) Dual Addressing mode
00271         (++) Own Address 2
00272         (++) Own Address 2 Mask
00273         (++) General call mode
00274         (++) Nostretch mode
00275
00276       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00277           of the selected I2Cx peripheral.
00278
00279 @endverbatim
00280   * @{
00281   */
00282
00283 /**
00284   * @brief  Initializes the I2C according to the specified parameters
00285   *         in the I2C_InitTypeDef and create the associated handle.
00286   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00287   *                the configuration information for the specified I2C.
00288   * @retval HAL status
00289   */
00290 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00291 {
00292   /* Check the I2C handle allocation */
00293   if(hi2c == NULL)
00294   {
00295     return HAL_ERROR;
00296   }
00297
00298   /* Check the parameters */
00299   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00300   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00301   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00302   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00303   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00304   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00305   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00306   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00307
00308   if(hi2c->State == HAL_I2C_STATE_RESET)
00309   {
00310     /* Allocate lock resource and initialize it */
00311     hi2c->Lock = HAL_UNLOCKED;
00312     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00313     HAL_I2C_MspInit(hi2c);
00314   }
00315
00316   hi2c->State = HAL_I2C_STATE_BUSY;
00317
00318   /* Disable the selected I2C peripheral */
00319   __HAL_I2C_DISABLE(hi2c);
00320
00321   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00322   /* Configure I2Cx: Frequency range */
00323   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00324
00325   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00326   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00327   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00328   if(hi2c->Init.OwnAddress1 != 0)
00329   {
00330     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00331     {
00332       hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00333     }
00334     else /* I2C_ADDRESSINGMODE_10BIT */
00335     {
00336       hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00337     }
00338   }
00339
00340   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00341   /* Configure I2Cx: Addressing Master mode */
00342   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00343   {
00344     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00345   }
00346   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00347   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00348
00349   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00350   /* Configure I2Cx: Dual mode and Own Address2 */
00351   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00352
00353   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00354   /* Configure I2Cx: Generalcall and NoStretch mode */
00355   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00356
00357   /* Enable the selected I2C peripheral */
00358   __HAL_I2C_ENABLE(hi2c);
00359
00360   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00361   hi2c->State = HAL_I2C_STATE_READY;
00362
00363   return HAL_OK;
00364 }
00365
00366 /**
00367   * @brief  DeInitializes the I2C peripheral.
00368   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00369   *                the configuration information for the specified I2C.
00370   * @retval HAL status
00371   */
00372 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00373 {
00374   /* Check the I2C handle allocation */
00375   if(hi2c == NULL)
00376   {
00377     return HAL_ERROR;
00378   }
00379
00380   /* Check the parameters */
00381   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00382
00383   hi2c->State = HAL_I2C_STATE_BUSY;
00384
00385   /* Disable the I2C Peripheral Clock */
00386   __HAL_I2C_DISABLE(hi2c);
00387
00388   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00389   HAL_I2C_MspDeInit(hi2c);
00390
00391   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00392
00393   hi2c->State = HAL_I2C_STATE_RESET;
00394
00395   /* Release Lock */
00396   __HAL_UNLOCK(hi2c);
00397
00398   return HAL_OK;
00399 }
00400
00401 /**
00402   * @brief I2C MSP Init.
00403   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00404   *                the configuration information for the specified I2C.
00405   * @retval None
00406   */
00407  __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00408 {
00409   /* Prevent unused argument(s) compilation warning */
00410   UNUSED(hi2c);
00411
00412   /* NOTE : This function Should not be modified, when the callback is needed,
00413             the HAL_I2C_MspInit could be implemented in the user file
00414    */
00415 }
00416
00417 /**
00418   * @brief I2C MSP DeInit
00419   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00420   *                the configuration information for the specified I2C.
00421   * @retval None
00422   */
00423  __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00424 {
00425   /* Prevent unused argument(s) compilation warning */
00426   UNUSED(hi2c);
00427
00428   /* NOTE : This function Should not be modified, when the callback is needed,
00429             the HAL_I2C_MspDeInit could be implemented in the user file
00430    */
00431 }
00432
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00438  *  @brief   Data transfers functions
00439  *
00440 @verbatim
00441  ===============================================================================
00442                       ##### IO operation functions #####
00443  ===============================================================================
00444     [..]
00445     This subsection provides a set of functions allowing to manage the I2C data
00446     transfers.
00447
00448     (#) There are two modes of transfer:
00449        (++) Blocking mode : The communication is performed in the polling mode.
00450             The status of all data processing is returned by the same function
00451             after finishing transfer.
00452        (++) No-Blocking mode : The communication is performed using Interrupts
00453             or DMA. These functions return the status of the transfer startup.
00454             The end of the data processing will be indicated through the
00455             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00456             using DMA mode.
00457
00458     (#) Blocking mode functions are :
00459         (++) HAL_I2C_Master_Transmit()
00460         (++) HAL_I2C_Master_Receive()
00461         (++) HAL_I2C_Slave_Transmit()
00462         (++) HAL_I2C_Slave_Receive()
00463         (++) HAL_I2C_Mem_Write()
00464         (++) HAL_I2C_Mem_Read()
00465         (++) HAL_I2C_IsDeviceReady()
00466
00467     (#) No-Blocking mode functions with Interrupt are :
00468         (++) HAL_I2C_Master_Transmit_IT()
00469         (++) HAL_I2C_Master_Receive_IT()
00470         (++) HAL_I2C_Slave_Transmit_IT()
00471         (++) HAL_I2C_Slave_Receive_IT()
00472         (++) HAL_I2C_Mem_Write_IT()
00473         (++) HAL_I2C_Mem_Read_IT()
00474
00475     (#) No-Blocking mode functions with DMA are :
00476         (++) HAL_I2C_Master_Transmit_DMA()
00477         (++) HAL_I2C_Master_Receive_DMA()
00478         (++) HAL_I2C_Slave_Transmit_DMA()
00479         (++) HAL_I2C_Slave_Receive_DMA()
00480         (++) HAL_I2C_Mem_Write_DMA()
00481         (++) HAL_I2C_Mem_Read_DMA()
00482
00483     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00484         (++) HAL_I2C_MemTxCpltCallback()
00485         (++) HAL_I2C_MemRxCpltCallback()
00486         (++) HAL_I2C_MasterTxCpltCallback()
00487         (++) HAL_I2C_MasterRxCpltCallback()
00488         (++) HAL_I2C_SlaveTxCpltCallback()
00489         (++) HAL_I2C_SlaveRxCpltCallback()
00490         (++) HAL_I2C_ErrorCallback()
00491
00492 @endverbatim
00493   * @{
00494   */
00495
00496 /**
00497   * @brief  Transmits in master mode an amount of data in blocking mode.
00498   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00499   *                the configuration information for the specified I2C.
00500   * @param  DevAddress: Target device address
00501   * @param  pData: Pointer to data buffer
00502   * @param  Size: Amount of data to be sent
00503   * @param  Timeout: Timeout duration
00504   * @retval HAL status
00505   */
00506 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00507 {
00508   uint32_t sizetmp = 0;
00509
00510   if(hi2c->State == HAL_I2C_STATE_READY)
00511   {
00512     if((pData == NULL ) || (Size == 0))
00513     {
00514       return  HAL_ERROR;
00515     }
00516
00517     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
00518     {
00519       return HAL_BUSY;
00520     }
00521
00522     /* Process Locked */
00523     __HAL_LOCK(hi2c);
00524
00525     hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
00526     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
00527
00528     /* Send Slave Address */
00529     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
00530     /* Size > 255, need to set RELOAD bit */
00531     if(Size > 255)
00532     {
00533       I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
00534       sizetmp = 255;
00535     }
00536     else
00537     {
00538       I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
00539       sizetmp = Size;
00540     }
00541
00542     do
00543     {
00544       /* Wait until TXIS flag is set */
00545       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00546       {
00547         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00548         {
00549           return HAL_ERROR;
00550         }
00551         else
00552         {
00553           return HAL_TIMEOUT;
00554         }
00555       }
00556       /* Write data to TXDR */
00557       hi2c->Instance->TXDR = (*pData++);
00558       sizetmp--;
00559       Size--;
00560
00561       if((sizetmp == 0)&&(Size!=0))
00562       {
00563         /* Wait until TCR flag is set */
00564         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
00565         {
00566           return HAL_TIMEOUT;
00567         }
00568
00569         if(Size > 255)
00570         {
00571           I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00572           sizetmp = 255;
00573         }
00574         else
00575         {
00576           I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00577           sizetmp = Size;
00578         }
00579       }
00580
00581     }while(Size > 0);
00582
00583     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00584     /* Wait until STOPF flag is set */
00585     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00586     {
00587       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00588       {
00589         return HAL_ERROR;
00590       }
00591       else
00592       {
00593         return HAL_TIMEOUT;
00594       }
00595     }
00596
00597     /* Clear STOP Flag */
00598     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00599
00600     /* Clear Configuration Register 2 */
00601     I2C_RESET_CR2(hi2c);
00602
00603     hi2c->State = HAL_I2C_STATE_READY;
00604
00605     /* Process Unlocked */
00606     __HAL_UNLOCK(hi2c);
00607
00608     return HAL_OK;
00609   }
00610   else
00611   {
00612     return HAL_BUSY;
00613   }
00614 }
00615
00616 /**
00617   * @brief  Receives in master mode an amount of data in blocking mode.
00618   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00619   *                the configuration information for the specified I2C.
00620   * @param  DevAddress: Target device address
00621   * @param  pData: Pointer to data buffer
00622   * @param  Size: Amount of data to be sent
00623   * @param  Timeout: Timeout duration
00624   * @retval HAL status
00625   */
00626 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00627 {
00628   uint32_t sizetmp = 0;
00629
00630   if(hi2c->State == HAL_I2C_STATE_READY)
00631   {
00632     if((pData == NULL ) || (Size == 0))
00633     {
00634       return  HAL_ERROR;
00635     }
00636
00637     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
00638     {
00639       return HAL_BUSY;
00640     }
00641
00642     /* Process Locked */
00643     __HAL_LOCK(hi2c);
00644
00645     hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
00646     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
00647
00648     /* Send Slave Address */
00649     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
00650     /* Size > 255, need to set RELOAD bit */
00651     if(Size > 255)
00652     {
00653       I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
00654       sizetmp = 255;
00655     }
00656     else
00657     {
00658       I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
00659       sizetmp = Size;
00660     }
00661
00662     do
00663     {
00664       /* Wait until RXNE flag is set */
00665       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
00666       {
00667         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00668         {
00669           return HAL_ERROR;
00670         }
00671         else
00672         {
00673           return HAL_TIMEOUT;
00674         }
00675           }
00676
00677       /* Write data to RXDR */
00678       (*pData++) =hi2c->Instance->RXDR;
00679       sizetmp--;
00680       Size--;
00681
00682       if((sizetmp == 0)&&(Size!=0))
00683       {
00684         /* Wait until TCR flag is set */
00685         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
00686         {
00687           return HAL_TIMEOUT;
00688         }
00689
00690         if(Size > 255)
00691         {
00692           I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00693           sizetmp = 255;
00694         }
00695         else
00696         {
00697           I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00698           sizetmp = Size;
00699         }
00700       }
00701
00702     }while(Size > 0);
00703
00704     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00705     /* Wait until STOPF flag is set */
00706     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
00707     {
00708       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00709       {
00710         return HAL_ERROR;
00711       }
00712       else
00713       {
00714         return HAL_TIMEOUT;
00715       }
00716     }
00717
00718     /* Clear STOP Flag */
00719     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00720
00721     /* Clear Configuration Register 2 */
00722     I2C_RESET_CR2(hi2c);
00723
00724     hi2c->State = HAL_I2C_STATE_READY;
00725
00726     /* Process Unlocked */
00727     __HAL_UNLOCK(hi2c);
00728
00729     return HAL_OK;
00730   }
00731   else
00732   {
00733     return HAL_BUSY;
00734   }
00735 }
00736
00737 /**
00738   * @brief  Transmits in slave mode an amount of data in blocking mode.
00739   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00740   *                the configuration information for the specified I2C.
00741   * @param  pData: Pointer to data buffer
00742   * @param  Size: Amount of data to be sent
00743   * @param  Timeout: Timeout duration
00744   * @retval HAL status
00745   */
00746 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00747 {
00748   if(hi2c->State == HAL_I2C_STATE_READY)
00749   {
00750     if((pData == NULL ) || (Size == 0))
00751     {
00752       return  HAL_ERROR;
00753     }
00754
00755     /* Process Locked */
00756     __HAL_LOCK(hi2c);
00757
00758     hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
00759     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
00760
00761     /* Enable Address Acknowledge */
00762     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
00763
00764     /* Wait until ADDR flag is set */
00765     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00766     {
00767       /* Disable Address Acknowledge */
00768       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00769       return HAL_TIMEOUT;
00770     }
00771
00772     /* Clear ADDR flag */
00773     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00774
00775     /* If 10bit addressing mode is selected */
00776     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00777     {
00778       /* Wait until ADDR flag is set */
00779       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00780       {
00781         /* Disable Address Acknowledge */
00782         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00783         return HAL_TIMEOUT;
00784       }
00785
00786       /* Clear ADDR flag */
00787       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00788     }
00789
00790     /* Wait until DIR flag is set Transmitter mode */
00791     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
00792     {
00793       /* Disable Address Acknowledge */
00794       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00795       return HAL_TIMEOUT;
00796     }
00797
00798     do
00799     {
00800       /* Wait until TXIS flag is set */
00801       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00802       {
00803         /* Disable Address Acknowledge */
00804         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00805
00806         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00807         {
00808           return HAL_ERROR;
00809         }
00810         else
00811         {
00812           return HAL_TIMEOUT;
00813         }
00814       }
00815
00816       /* Read data from TXDR */
00817       hi2c->Instance->TXDR = (*pData++);
00818       Size--;
00819     }while(Size > 0);
00820
00821     /* Wait until STOP flag is set */
00822     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
00823     {
00824       /* Disable Address Acknowledge */
00825       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00826
00827       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00828       {
00829         /* Normal use case for Transmitter mode */
00830         /* A NACK is generated to confirm the end of transfer */
00831         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00832       }
00833       else
00834       {
00835         return HAL_TIMEOUT;
00836       }
00837     }
00838
00839     /* Clear STOP flag */
00840     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
00841
00842     /* Wait until BUSY flag is reset */
00843     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
00844     {
00845       /* Disable Address Acknowledge */
00846       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00847       return HAL_TIMEOUT;
00848     }
00849
00850     /* Disable Address Acknowledge */
00851     hi2c->Instance->CR2 |= I2C_CR2_NACK;
00852
00853     hi2c->State = HAL_I2C_STATE_READY;
00854
00855     /* Process Unlocked */
00856     __HAL_UNLOCK(hi2c);
00857
00858     return HAL_OK;
00859   }
00860   else
00861   {
00862     return HAL_BUSY;
00863   }
00864 }
00865
00866 /**
00867   * @brief  Receive in slave mode an amount of data in blocking mode
00868   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00869   *                the configuration information for the specified I2C.
00870   * @param  pData: Pointer to data buffer
00871   * @param  Size: Amount of data to be sent
00872   * @param  Timeout: Timeout duration
00873   * @retval HAL status
00874   */
00875 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00876 {
00877   if(hi2c->State == HAL_I2C_STATE_READY)
00878   {
00879     if((pData == NULL ) || (Size == 0))
00880     {
00881       return  HAL_ERROR;
00882     }
00883
00884     /* Process Locked */
00885     __HAL_LOCK(hi2c);
00886
00887     hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
00888     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
00889
00890     /* Enable Address Acknowledge */
00891     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
00892
00893     /* Wait until ADDR flag is set */
00894     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00895     {
00896       /* Disable Address Acknowledge */
00897       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00898       return HAL_TIMEOUT;
00899     }
00900
00901     /* Clear ADDR flag */
00902     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00903
00904     /* Wait until DIR flag is reset Receiver mode */
00905     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK)
00906     {
00907       /* Disable Address Acknowledge */
00908       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00909       return HAL_TIMEOUT;
00910     }
00911
00912     while(Size > 0)
00913     {
00914       /* Wait until RXNE flag is set */
00915       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00916       {
00917         /* Disable Address Acknowledge */
00918         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00919
00920         /* Store Last receive data if any */
00921         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
00922         {
00923           /* Read data from RXDR */
00924           (*pData++) = hi2c->Instance->RXDR;
00925         }
00926
00927         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
00928         {
00929           return HAL_TIMEOUT;
00930         }
00931         else
00932         {
00933           return HAL_ERROR;
00934         }
00935       }
00936
00937       /* Read data from RXDR */
00938       (*pData++) = hi2c->Instance->RXDR;
00939       Size--;
00940     }
00941
00942     /* Wait until STOP flag is set */
00943     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
00944     {
00945       /* Disable Address Acknowledge */
00946       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00947
00948       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00949       {
00950         return HAL_ERROR;
00951       }
00952       else
00953       {
00954         return HAL_TIMEOUT;
00955       }
00956     }
00957
00958     /* Clear STOP flag */
00959     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
00960
00961     /* Wait until BUSY flag is reset */
00962     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
00963     {
00964       /* Disable Address Acknowledge */
00965       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00966       return HAL_TIMEOUT;
00967     }
00968
00969
00970     /* Disable Address Acknowledge */
00971     hi2c->Instance->CR2 |= I2C_CR2_NACK;
00972
00973     hi2c->State = HAL_I2C_STATE_READY;
00974
00975     /* Process Unlocked */
00976     __HAL_UNLOCK(hi2c);
00977
00978     return HAL_OK;
00979   }
00980   else
00981   {
00982     return HAL_BUSY;
00983   }
00984 }
00985
00986 /**
00987   * @brief  Transmit in master mode an amount of data in no-blocking mode with Interrupt
00988   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
00989   *                the configuration information for the specified I2C.
00990   * @param  DevAddress: Target device address
00991   * @param  pData: Pointer to data buffer
00992   * @param  Size: Amount of data to be sent
00993   * @retval HAL status
00994   */
00995 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
00996 {
00997   if(hi2c->State == HAL_I2C_STATE_READY)
00998   {
00999     if((pData == NULL) || (Size == 0))
01000     {
01001       return  HAL_ERROR;
01002     }
01003
01004     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01005     {
01006       return HAL_BUSY;
01007     }
01008
01009     /* Process Locked */
01010     __HAL_LOCK(hi2c);
01011
01012     hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
01013     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01014
01015     hi2c->pBuffPtr = pData;
01016     hi2c->XferCount = Size;
01017     if(Size > 255)
01018     {
01019       hi2c->XferSize = 255;
01020     }
01021     else
01022     {
01023       hi2c->XferSize = Size;
01024     }
01025
01026     /* Send Slave Address */
01027     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
01028     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
01029     {
01030       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
01031     }
01032     else
01033     {
01034       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01035     }
01036
01037     /* Process Unlocked */
01038     __HAL_UNLOCK(hi2c);
01039
01040     /* Note : The I2C interrupts must be enabled after unlocking current process
01041     to avoid the risk of I2C interrupt handle execution before current
01042     process unlock */
01043
01044
01045     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01046     /* possible to enable all of these */
01047     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01048     __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
01049
01050     return HAL_OK;
01051   }
01052   else
01053   {
01054     return HAL_BUSY;
01055   }
01056 }
01057
01058 /**
01059   * @brief  Receive in master mode an amount of data in no-blocking mode with Interrupt
01060   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01061   *                the configuration information for the specified I2C.
01062   * @param  DevAddress: Target device address
01063   * @param  pData: Pointer to data buffer
01064   * @param  Size: Amount of data to be sent
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01068 {
01069   if(hi2c->State == HAL_I2C_STATE_READY)
01070   {
01071     if((pData == NULL) || (Size == 0))
01072     {
01073       return  HAL_ERROR;
01074     }
01075
01076     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01077     {
01078       return HAL_BUSY;
01079     }
01080
01081     /* Process Locked */
01082     __HAL_LOCK(hi2c);
01083
01084     hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
01085     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01086
01087     hi2c->pBuffPtr = pData;
01088     hi2c->XferCount = Size;
01089     if(Size > 255)
01090     {
01091       hi2c->XferSize = 255;
01092     }
01093     else
01094     {
01095       hi2c->XferSize = Size;
01096     }
01097
01098     /* Send Slave Address */
01099     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
01100     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
01101     {
01102       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01103     }
01104     else
01105     {
01106       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01107     }
01108
01109     /* Process Unlocked */
01110     __HAL_UNLOCK(hi2c);
01111
01112     /* Note : The I2C interrupts must be enabled after unlocking current process
01113     to avoid the risk of I2C interrupt handle execution before current
01114     process unlock */
01115
01116     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01117     /* possible to enable all of these */
01118     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01119     __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI );
01120
01121     return HAL_OK;
01122   }
01123   else
01124   {
01125     return HAL_BUSY;
01126   }
01127 }
01128
01129 /**
01130   * @brief  Transmit in slave mode an amount of data in no-blocking mode with Interrupt
01131   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01132   *                the configuration information for the specified I2C.
01133   * @param  pData: Pointer to data buffer
01134   * @param  Size: Amount of data to be sent
01135   * @retval HAL status
01136   */
01137 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01138 {
01139   if(hi2c->State == HAL_I2C_STATE_READY)
01140   {
01141     if((pData == NULL) || (Size == 0))
01142     {
01143       return  HAL_ERROR;
01144     }
01145
01146     /* Process Locked */
01147     __HAL_LOCK(hi2c);
01148
01149     hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
01150     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01151
01152     /* Enable Address Acknowledge */
01153     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01154
01155     hi2c->pBuffPtr = pData;
01156     hi2c->XferSize = Size;
01157     hi2c->XferCount = Size;
01158
01159     /* Process Unlocked */
01160     __HAL_UNLOCK(hi2c);
01161
01162     /* Note : The I2C interrupts must be enabled after unlocking current process
01163     to avoid the risk of I2C interrupt handle execution before current
01164     process unlock */
01165
01166     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01167     /* possible to enable all of these */
01168     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01169     __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI );
01170
01171     return HAL_OK;
01172   }
01173   else
01174   {
01175     return HAL_BUSY;
01176   }
01177 }
01178
01179 /**
01180   * @brief  Receive in slave mode an amount of data in no-blocking mode with Interrupt
01181   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01182   *                the configuration information for the specified I2C.
01183   * @param  pData: Pointer to data buffer
01184   * @param  Size: Amount of data to be sent
01185   * @retval HAL status
01186   */
01187 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01188 {
01189   if(hi2c->State == HAL_I2C_STATE_READY)
01190   {
01191     if((pData == NULL) || (Size == 0))
01192     {
01193       return  HAL_ERROR;
01194     }
01195
01196     /* Process Locked */
01197     __HAL_LOCK(hi2c);
01198
01199     hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
01200     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01201
01202     /* Enable Address Acknowledge */
01203     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01204
01205     hi2c->pBuffPtr = pData;
01206     hi2c->XferSize = Size;
01207     hi2c->XferCount = Size;
01208
01209     /* Process Unlocked */
01210     __HAL_UNLOCK(hi2c);
01211
01212     /* Note : The I2C interrupts must be enabled after unlocking current process
01213     to avoid the risk of I2C interrupt handle execution before current
01214     process unlock */
01215
01216     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01217     /* possible to enable all of these */
01218     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01219     __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI);
01220
01221     return HAL_OK;
01222   }
01223   else
01224   {
01225     return HAL_BUSY;
01226   }
01227 }
01228
01229 /**
01230   * @brief  Transmit in master mode an amount of data in no-blocking mode with DMA
01231   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01232   *                the configuration information for the specified I2C.
01233   * @param  DevAddress: Target device address
01234   * @param  pData: Pointer to data buffer
01235   * @param  Size: Amount of data to be sent
01236   * @retval HAL status
01237   */
01238 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01239 {
01240   if(hi2c->State == HAL_I2C_STATE_READY)
01241   {
01242     if((pData == NULL) || (Size == 0))
01243     {
01244       return  HAL_ERROR;
01245     }
01246
01247     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01248     {
01249       return HAL_BUSY;
01250     }
01251
01252     /* Process Locked */
01253     __HAL_LOCK(hi2c);
01254
01255     hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
01256     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01257
01258     hi2c->pBuffPtr = pData;
01259     hi2c->XferCount = Size;
01260     if(Size > 255)
01261     {
01262       hi2c->XferSize = 255;
01263     }
01264     else
01265     {
01266       hi2c->XferSize = Size;
01267     }
01268
01269     /* Set the I2C DMA transfer complete callback */
01270     hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01271
01272     /* Set the DMA error callback */
01273     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01274
01275     /* Enable the DMA channel */
01276     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01277
01278     /* Send Slave Address */
01279     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
01280     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
01281     {
01282       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
01283     }
01284     else
01285     {
01286       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01287     }
01288
01289     /* Wait until TXIS flag is set */
01290     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
01291     {
01292       /* Disable Address Acknowledge */
01293       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01294
01295       /* Abort DMA */
01296       HAL_DMA_Abort(hi2c->hdmatx);
01297
01298       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01299       {
01300         return HAL_ERROR;
01301       }
01302       else
01303       {
01304         return HAL_TIMEOUT;
01305       }
01306     }
01307
01308     /* Enable DMA Request */
01309     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01310
01311     /* Process Unlocked */
01312     __HAL_UNLOCK(hi2c);
01313
01314     return HAL_OK;
01315   }
01316   else
01317   {
01318     return HAL_BUSY;
01319   }
01320 }
01321
01322 /**
01323   * @brief  Receive in master mode an amount of data in no-blocking mode with DMA
01324   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01325   *                the configuration information for the specified I2C.
01326   * @param  DevAddress: Target device address
01327   * @param  pData: Pointer to data buffer
01328   * @param  Size: Amount of data to be sent
01329   * @retval HAL status
01330   */
01331 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01332 {
01333   if(hi2c->State == HAL_I2C_STATE_READY)
01334   {
01335     if((pData == NULL) || (Size == 0))
01336     {
01337       return  HAL_ERROR;
01338     }
01339
01340     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01341     {
01342       return HAL_BUSY;
01343     }
01344
01345     /* Process Locked */
01346     __HAL_LOCK(hi2c);
01347
01348     hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
01349     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01350
01351     hi2c->pBuffPtr = pData;
01352     hi2c->XferCount = Size;
01353     if(Size > 255)
01354     {
01355       hi2c->XferSize = 255;
01356     }
01357     else
01358     {
01359       hi2c->XferSize = Size;
01360     }
01361
01362     /* Set the I2C DMA transfer complete callback */
01363     hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01364
01365     /* Set the DMA error callback */
01366     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01367
01368     /* Enable the DMA channel */
01369     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01370
01371     /* Send Slave Address */
01372     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
01373     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
01374     {
01375       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01376     }
01377     else
01378     {
01379       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01380     }
01381
01382     /* Wait until RXNE flag is set */
01383     if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
01384     {
01385       /* Abort DMA */
01386       HAL_DMA_Abort(hi2c->hdmarx);
01387
01388       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01389       {
01390         return HAL_ERROR;
01391       }
01392       else
01393       {
01394         return HAL_TIMEOUT;
01395       }
01396         }
01397
01398     /* Enable DMA Request */
01399     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01400
01401     /* Process Unlocked */
01402     __HAL_UNLOCK(hi2c);
01403
01404     return HAL_OK;
01405   }
01406   else
01407   {
01408     return HAL_BUSY;
01409   }
01410 }
01411
01412 /**
01413   * @brief  Transmit in slave mode an amount of data in no-blocking mode with DMA
01414   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01415   *                the configuration information for the specified I2C.
01416   * @param  pData: Pointer to data buffer
01417   * @param  Size: Amount of data to be sent
01418   * @retval HAL status
01419   */
01420 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01421 {
01422   if(hi2c->State == HAL_I2C_STATE_READY)
01423   {
01424     if((pData == NULL) || (Size == 0))
01425     {
01426       return  HAL_ERROR;
01427     }
01428     /* Process Locked */
01429     __HAL_LOCK(hi2c);
01430
01431     hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
01432     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01433
01434     hi2c->pBuffPtr = pData;
01435     hi2c->XferCount = Size;
01436     hi2c->XferSize = Size;
01437
01438     /* Set the I2C DMA transfer complete callback */
01439     hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
01440
01441     /* Set the DMA error callback */
01442     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01443
01444     /* Enable the DMA channel */
01445     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01446
01447     /* Enable Address Acknowledge */
01448     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01449
01450     /* Wait until ADDR flag is set */
01451     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
01452     {
01453       /* Disable Address Acknowledge */
01454       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01455       return HAL_TIMEOUT;
01456     }
01457
01458     /* Clear ADDR flag */
01459     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
01460
01461     /* If 10bits addressing mode is selected */
01462     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
01463     {
01464       /* Wait until ADDR flag is set */
01465       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
01466       {
01467         /* Disable Address Acknowledge */
01468         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01469         return HAL_TIMEOUT;
01470       }
01471
01472       /* Clear ADDR flag */
01473       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
01474     }
01475
01476     /* Wait until DIR flag is set Transmitter mode */
01477     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK)
01478     {
01479       /* Disable Address Acknowledge */
01480       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01481       return HAL_TIMEOUT;
01482     }
01483
01484     /* Enable DMA Request */
01485     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01486
01487     /* Process Unlocked */
01488     __HAL_UNLOCK(hi2c);
01489
01490     return HAL_OK;
01491   }
01492   else
01493   {
01494     return HAL_BUSY;
01495   }
01496 }
01497
01498 /**
01499   * @brief  Receive in slave mode an amount of data in no-blocking mode with DMA
01500   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01501   *                the configuration information for the specified I2C.
01502   * @param  pData: Pointer to data buffer
01503   * @param  Size: Amount of data to be sent
01504   * @retval HAL status
01505   */
01506 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01507 {
01508   if(hi2c->State == HAL_I2C_STATE_READY)
01509   {
01510     if((pData == NULL) || (Size == 0))
01511     {
01512       return  HAL_ERROR;
01513     }
01514     /* Process Locked */
01515     __HAL_LOCK(hi2c);
01516
01517     hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
01518     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01519
01520     hi2c->pBuffPtr = pData;
01521     hi2c->XferSize = Size;
01522     hi2c->XferCount = Size;
01523
01524     /* Set the I2C DMA transfer complete callback */
01525     hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
01526
01527     /* Set the DMA error callback */
01528     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01529
01530     /* Enable the DMA channel */
01531     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
01532
01533     /* Enable Address Acknowledge */
01534     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01535
01536     /* Wait until ADDR flag is set */
01537     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
01538     {
01539       /* Disable Address Acknowledge */
01540       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01541       return HAL_TIMEOUT;
01542     }
01543
01544     /* Clear ADDR flag */
01545     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
01546
01547     /* Wait until DIR flag is set Receiver mode */
01548     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK)
01549     {
01550       /* Disable Address Acknowledge */
01551       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01552       return HAL_TIMEOUT;
01553     }
01554
01555     /* Enable DMA Request */
01556     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01557
01558     /* Process Unlocked */
01559     __HAL_UNLOCK(hi2c);
01560
01561     return HAL_OK;
01562   }
01563   else
01564   {
01565     return HAL_BUSY;
01566   }
01567 }
01568 /**
01569   * @brief  Write an amount of data in blocking mode to a specific memory address
01570   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01571   *                the configuration information for the specified I2C.
01572   * @param  DevAddress: Target device address
01573   * @param  MemAddress: Internal memory address
01574   * @param  MemAddSize: Size of internal memory address
01575   * @param  pData: Pointer to data buffer
01576   * @param  Size: Amount of data to be sent
01577   * @param  Timeout: Timeout duration
01578   * @retval HAL status
01579   */
01580 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01581 {
01582   uint32_t Sizetmp = 0;
01583
01584   /* Check the parameters */
01585   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01586
01587   if(hi2c->State == HAL_I2C_STATE_READY)
01588   {
01589     if((pData == NULL) || (Size == 0))
01590     {
01591       return  HAL_ERROR;
01592     }
01593
01594     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01595     {
01596       return HAL_BUSY;
01597     }
01598
01599     /* Process Locked */
01600     __HAL_LOCK(hi2c);
01601
01602     hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
01603     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01604
01605     /* Send Slave Address and Memory Address */
01606     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
01607     {
01608       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01609       {
01610         /* Process Unlocked */
01611         __HAL_UNLOCK(hi2c);
01612         return HAL_ERROR;
01613       }
01614       else
01615       {
01616         /* Process Unlocked */
01617         __HAL_UNLOCK(hi2c);
01618         return HAL_TIMEOUT;
01619       }
01620     }
01621
01622     /* Set NBYTES to write and reload if size > 255 */
01623     /* Size > 255, need to set RELOAD bit */
01624     if(Size > 255)
01625     {
01626       I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01627       Sizetmp = 255;
01628     }
01629     else
01630     {
01631       I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01632       Sizetmp = Size;
01633     }
01634
01635     do
01636     {
01637       /* Wait until TXIS flag is set */
01638       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
01639       {
01640         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01641         {
01642           return HAL_ERROR;
01643         }
01644         else
01645         {
01646           return HAL_TIMEOUT;
01647         }
01648       }
01649
01650       /* Write data to DR */
01651       hi2c->Instance->TXDR = (*pData++);
01652       Sizetmp--;
01653       Size--;
01654
01655       if((Sizetmp == 0)&&(Size!=0))
01656       {
01657         /* Wait until TCR flag is set */
01658         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
01659         {
01660           return HAL_TIMEOUT;
01661         }
01662
01663
01664         if(Size > 255)
01665         {
01666           I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01667           Sizetmp = 255;
01668         }
01669         else
01670         {
01671           I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01672           Sizetmp = Size;
01673         }
01674       }
01675
01676     }while(Size > 0);
01677
01678     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01679     /* Wait until STOPF flag is reset */
01680     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
01681     {
01682       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01683       {
01684         return HAL_ERROR;
01685       }
01686       else
01687       {
01688         return HAL_TIMEOUT;
01689       }
01690     }
01691
01692     /* Clear STOP Flag */
01693     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01694
01695     /* Clear Configuration Register 2 */
01696     I2C_RESET_CR2(hi2c);
01697
01698     hi2c->State = HAL_I2C_STATE_READY;
01699
01700     /* Process Unlocked */
01701     __HAL_UNLOCK(hi2c);
01702
01703     return HAL_OK;
01704   }
01705   else
01706   {
01707     return HAL_BUSY;
01708   }
01709 }
01710
01711 /**
01712   * @brief  Read an amount of data in blocking mode from a specific memory address
01713   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01714   *                the configuration information for the specified I2C.
01715   * @param  DevAddress: Target device address
01716   * @param  MemAddress: Internal memory address
01717   * @param  MemAddSize: Size of internal memory address
01718   * @param  pData: Pointer to data buffer
01719   * @param  Size: Amount of data to be sent
01720   * @param  Timeout: Timeout duration
01721   * @retval HAL status
01722   */
01723 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01724 {
01725   uint32_t Sizetmp = 0;
01726
01727   /* Check the parameters */
01728   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01729
01730   if(hi2c->State == HAL_I2C_STATE_READY)
01731   {
01732     if((pData == NULL) || (Size == 0))
01733     {
01734       return  HAL_ERROR;
01735     }
01736
01737     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01738     {
01739       return HAL_BUSY;
01740     }
01741
01742     /* Process Locked */
01743     __HAL_LOCK(hi2c);
01744
01745     hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
01746     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01747
01748     /* Send Slave Address and Memory Address */
01749     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
01750     {
01751       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01752       {
01753         /* Process Unlocked */
01754         __HAL_UNLOCK(hi2c);
01755         return HAL_ERROR;
01756       }
01757       else
01758       {
01759         /* Process Unlocked */
01760         __HAL_UNLOCK(hi2c);
01761         return HAL_TIMEOUT;
01762       }
01763     }
01764
01765     /* Send Slave Address */
01766     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
01767     /* Size > 255, need to set RELOAD bit */
01768     if(Size > 255)
01769     {
01770       I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01771       Sizetmp = 255;
01772     }
01773     else
01774     {
01775       I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01776       Sizetmp = Size;
01777     }
01778
01779     do
01780     {
01781       /* Wait until RXNE flag is set */
01782       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
01783       {
01784         return HAL_TIMEOUT;
01785       }
01786
01787       /* Read data from RXDR */
01788       (*pData++) = hi2c->Instance->RXDR;
01789
01790       /* Decrement the Size counter */
01791       Sizetmp--;
01792       Size--;
01793
01794       if((Sizetmp == 0)&&(Size!=0))
01795       {
01796         /* Wait until TCR flag is set */
01797         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
01798         {
01799           return HAL_TIMEOUT;
01800         }
01801
01802         if(Size > 255)
01803         {
01804           I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01805           Sizetmp = 255;
01806         }
01807         else
01808         {
01809           I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01810           Sizetmp = Size;
01811         }
01812       }
01813
01814     }while(Size > 0);
01815
01816     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01817     /* Wait until STOPF flag is reset */
01818     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
01819     {
01820       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01821       {
01822         return HAL_ERROR;
01823       }
01824       else
01825       {
01826         return HAL_TIMEOUT;
01827       }
01828     }
01829
01830     /* Clear STOP Flag */
01831     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01832
01833     /* Clear Configuration Register 2 */
01834     I2C_RESET_CR2(hi2c);
01835
01836     hi2c->State = HAL_I2C_STATE_READY;
01837
01838     /* Process Unlocked */
01839     __HAL_UNLOCK(hi2c);
01840
01841     return HAL_OK;
01842   }
01843   else
01844   {
01845     return HAL_BUSY;
01846   }
01847 }
01848 /**
01849   * @brief  Write an amount of data in no-blocking mode with Interrupt to a specific memory address
01850   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01851   *                the configuration information for the specified I2C.
01852   * @param  DevAddress: Target device address
01853   * @param  MemAddress: Internal memory address
01854   * @param  MemAddSize: Size of internal memory address
01855   * @param  pData: Pointer to data buffer
01856   * @param  Size: Amount of data to be sent
01857   * @retval HAL status
01858   */
01859 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
01860 {
01861   /* Check the parameters */
01862   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01863
01864   if(hi2c->State == HAL_I2C_STATE_READY)
01865   {
01866     if((pData == NULL) || (Size == 0))
01867     {
01868       return  HAL_ERROR;
01869     }
01870
01871     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01872     {
01873       return HAL_BUSY;
01874     }
01875
01876     /* Process Locked */
01877     __HAL_LOCK(hi2c);
01878
01879     hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
01880     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01881
01882     hi2c->pBuffPtr = pData;
01883     hi2c->XferCount = Size;
01884     if(Size > 255)
01885     {
01886       hi2c->XferSize = 255;
01887     }
01888     else
01889     {
01890       hi2c->XferSize = Size;
01891     }
01892
01893     /* Send Slave Address and Memory Address */
01894     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
01895     {
01896       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01897       {
01898         /* Process Unlocked */
01899         __HAL_UNLOCK(hi2c);
01900         return HAL_ERROR;
01901       }
01902       else
01903       {
01904         /* Process Unlocked */
01905         __HAL_UNLOCK(hi2c);
01906         return HAL_TIMEOUT;
01907       }
01908     }
01909
01910     /* Set NBYTES to write and reload if size > 255 */
01911     /* Size > 255, need to set RELOAD bit */
01912     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
01913     {
01914       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01915     }
01916     else
01917     {
01918       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01919     }
01920
01921     /* Process Unlocked */
01922     __HAL_UNLOCK(hi2c);
01923
01924     /* Note : The I2C interrupts must be enabled after unlocking current process
01925     to avoid the risk of I2C interrupt handle execution before current
01926     process unlock */
01927
01928     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01929     /* possible to enable all of these */
01930     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01931     __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
01932
01933     return HAL_OK;
01934   }
01935   else
01936   {
01937     return HAL_BUSY;
01938   }
01939 }
01940
01941 /**
01942   * @brief  Read an amount of data in no-blocking mode with Interrupt from a specific memory address
01943   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
01944   *                the configuration information for the specified I2C.
01945   * @param  DevAddress: Target device address
01946   * @param  MemAddress: Internal memory address
01947   * @param  MemAddSize: Size of internal memory address
01948   * @param  pData: Pointer to data buffer
01949   * @param  Size: Amount of data to be sent
01950   * @retval HAL status
01951   */
01952 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
01953 {
01954   /* Check the parameters */
01955   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01956
01957   if(hi2c->State == HAL_I2C_STATE_READY)
01958   {
01959     if((pData == NULL) || (Size == 0))
01960     {
01961       return  HAL_ERROR;
01962     }
01963
01964     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01965     {
01966       return HAL_BUSY;
01967     }
01968
01969     /* Process Locked */
01970     __HAL_LOCK(hi2c);
01971
01972     hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
01973
01974     hi2c->pBuffPtr = pData;
01975     hi2c->XferCount = Size;
01976     if(Size > 255)
01977     {
01978       hi2c->XferSize = 255;
01979     }
01980     else
01981     {
01982       hi2c->XferSize = Size;
01983     }
01984
01985     /* Send Slave Address and Memory Address */
01986     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
01987     {
01988       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01989       {
01990         /* Process Unlocked */
01991         __HAL_UNLOCK(hi2c);
01992         return HAL_ERROR;
01993       }
01994       else
01995       {
01996         /* Process Unlocked */
01997         __HAL_UNLOCK(hi2c);
01998         return HAL_TIMEOUT;
01999       }
02000     }
02001
02002     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
02003     /* Size > 255, need to set RELOAD bit */
02004     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
02005     {
02006       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
02007     }
02008     else
02009     {
02010       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
02011     }
02012
02013     /* Process Unlocked */
02014     __HAL_UNLOCK(hi2c);
02015
02016     /* Note : The I2C interrupts must be enabled after unlocking current process
02017     to avoid the risk of I2C interrupt handle execution before current
02018     process unlock */
02019
02020     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02021     /* possible to enable all of these */
02022     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02023     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
02024
02025     return HAL_OK;
02026   }
02027   else
02028   {
02029     return HAL_BUSY;
02030   }
02031 }
02032 /**
02033   * @brief  Write an amount of data in no-blocking mode with DMA to a specific memory address
02034   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02035   *                the configuration information for the specified I2C.
02036   * @param  DevAddress: Target device address
02037   * @param  MemAddress: Internal memory address
02038   * @param  MemAddSize: Size of internal memory address
02039   * @param  pData: Pointer to data buffer
02040   * @param  Size: Amount of data to be sent
02041   * @retval HAL status
02042   */
02043 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02044 {
02045   /* Check the parameters */
02046   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02047
02048   if(hi2c->State == HAL_I2C_STATE_READY)
02049   {
02050     if((pData == NULL) || (Size == 0))
02051     {
02052       return  HAL_ERROR;
02053     }
02054
02055     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02056     {
02057       return HAL_BUSY;
02058     }
02059
02060     /* Process Locked */
02061     __HAL_LOCK(hi2c);
02062
02063     hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
02064     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02065
02066     hi2c->pBuffPtr = pData;
02067     hi2c->XferCount = Size;
02068     if(Size > 255)
02069     {
02070       hi2c->XferSize = 255;
02071     }
02072     else
02073     {
02074       hi2c->XferSize = Size;
02075     }
02076
02077     /* Set the I2C DMA transfer complete callback */
02078     hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
02079
02080     /* Set the DMA error callback */
02081     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02082
02083     /* Enable the DMA channel */
02084     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02085
02086     /* Send Slave Address and Memory Address */
02087     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02088     {
02089       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02090       {
02091         /* Process Unlocked */
02092         __HAL_UNLOCK(hi2c);
02093         return HAL_ERROR;
02094       }
02095       else
02096       {
02097         /* Process Unlocked */
02098         __HAL_UNLOCK(hi2c);
02099         return HAL_TIMEOUT;
02100       }
02101     }
02102
02103     /* Send Slave Address */
02104     /* Set NBYTES to write and reload if size > 255 */
02105     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
02106     {
02107       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02108     }
02109     else
02110     {
02111       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02112     }
02113
02114     /* Wait until TXIS flag is set */
02115     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
02116     {
02117       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02118       {
02119         return HAL_ERROR;
02120       }
02121       else
02122       {
02123         return HAL_TIMEOUT;
02124       }
02125     }
02126
02127     /* Enable DMA Request */
02128     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02129
02130     /* Process Unlocked */
02131     __HAL_UNLOCK(hi2c);
02132
02133     return HAL_OK;
02134   }
02135   else
02136   {
02137     return HAL_BUSY;
02138   }
02139 }
02140
02141 /**
02142   * @brief  Reads an amount of data in no-blocking mode with DMA from a specific memory address.
02143   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02144   *                the configuration information for the specified I2C.
02145   * @param  DevAddress: Target device address
02146   * @param  MemAddress: Internal memory address
02147   * @param  MemAddSize: Size of internal memory address
02148   * @param  pData: Pointer to data buffer
02149   * @param  Size: Amount of data to be read
02150   * @retval HAL status
02151   */
02152 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02153 {
02154   /* Check the parameters */
02155   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02156
02157   if(hi2c->State == HAL_I2C_STATE_READY)
02158   {
02159     if((pData == NULL) || (Size == 0))
02160     {
02161       return  HAL_ERROR;
02162     }
02163
02164     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02165     {
02166       return HAL_BUSY;
02167     }
02168
02169     /* Process Locked */
02170     __HAL_LOCK(hi2c);
02171
02172     hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
02173
02174     hi2c->pBuffPtr = pData;
02175     hi2c->XferCount = Size;
02176     if(Size > 255)
02177     {
02178       hi2c->XferSize = 255;
02179     }
02180     else
02181     {
02182       hi2c->XferSize = Size;
02183     }
02184
02185     /* Set the I2C DMA transfer complete callback */
02186     hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
02187
02188     /* Set the DMA error callback */
02189     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02190
02191     /* Enable the DMA channel */
02192     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02193
02194     /* Send Slave Address and Memory Address */
02195     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02196     {
02197       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02198       {
02199         /* Process Unlocked */
02200         __HAL_UNLOCK(hi2c);
02201         return HAL_ERROR;
02202       }
02203       else
02204       {
02205         /* Process Unlocked */
02206         __HAL_UNLOCK(hi2c);
02207         return HAL_TIMEOUT;
02208       }
02209     }
02210
02211     /* Set NBYTES to write and reload if size > 255 and generate RESTART */
02212     if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
02213     {
02214       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
02215     }
02216     else
02217     {
02218       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
02219     }
02220
02221     /* Wait until RXNE flag is set */
02222     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
02223     {
02224       return HAL_TIMEOUT;
02225     }
02226
02227     /* Enable DMA Request */
02228     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02229
02230     /* Process Unlocked */
02231     __HAL_UNLOCK(hi2c);
02232
02233     return HAL_OK;
02234   }
02235   else
02236   {
02237     return HAL_BUSY;
02238   }
02239 }
02240
02241 /**
02242   * @brief  Checks if target device is ready for communication.
02243   * @note   This function is used with Memory devices
02244   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02245   *                the configuration information for the specified I2C.
02246   * @param  DevAddress: Target device address
02247   * @param  Trials: Number of trials
02248   * @param  Timeout: Timeout duration
02249   * @retval HAL status
02250   */
02251 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
02252 {
02253   uint32_t tickstart = 0;
02254
02255   __IO uint32_t I2C_Trials = 0;
02256
02257   if(hi2c->State == HAL_I2C_STATE_READY)
02258   {
02259     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02260     {
02261       return HAL_BUSY;
02262     }
02263
02264     /* Process Locked */
02265     __HAL_LOCK(hi2c);
02266
02267     hi2c->State = HAL_I2C_STATE_BUSY;
02268     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02269
02270     do
02271     {
02272       /* Generate Start */
02273       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
02274
02275       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02276       /* Wait until STOPF flag is set or a NACK flag is set*/
02277       tickstart = HAL_GetTick();
02278       while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
02279       {
02280         if(Timeout != HAL_MAX_DELAY)
02281         {
02282           if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
02283           {
02284             /* Device is ready */
02285             hi2c->State = HAL_I2C_STATE_READY;
02286             /* Process Unlocked */
02287             __HAL_UNLOCK(hi2c);
02288             return HAL_TIMEOUT;
02289           }
02290         }
02291       }
02292
02293       /* Check if the NACKF flag has not been set */
02294       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
02295       {
02296         /* Wait until STOPF flag is reset */
02297         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
02298         {
02299           return HAL_TIMEOUT;
02300         }
02301
02302         /* Clear STOP Flag */
02303         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02304
02305         /* Device is ready */
02306         hi2c->State = HAL_I2C_STATE_READY;
02307
02308         /* Process Unlocked */
02309         __HAL_UNLOCK(hi2c);
02310
02311         return HAL_OK;
02312       }
02313       else
02314       {
02315         /* Wait until STOPF flag is reset */
02316         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
02317         {
02318           return HAL_TIMEOUT;
02319         }
02320
02321         /* Clear NACK Flag */
02322         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02323
02324         /* Clear STOP Flag, auto generated with autoend*/
02325         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02326       }
02327
02328       /* Check if the maximum allowed number of trials has been reached */
02329       if (I2C_Trials++ == Trials)
02330       {
02331         /* Generate Stop */
02332         hi2c->Instance->CR2 |= I2C_CR2_STOP;
02333
02334         /* Wait until STOPF flag is reset */
02335         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
02336         {
02337           return HAL_TIMEOUT;
02338         }
02339
02340         /* Clear STOP Flag */
02341         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02342       }
02343     }while(I2C_Trials < Trials);
02344
02345     hi2c->State = HAL_I2C_STATE_READY;
02346
02347     /* Process Unlocked */
02348     __HAL_UNLOCK(hi2c);
02349
02350     return HAL_TIMEOUT;
02351   }
02352   else
02353   {
02354     return HAL_BUSY;
02355   }
02356 }
02357 /**
02358   * @}
02359   */
02360
02361 /** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
02362  * @{
02363  */
02364
02365 /**
02366   * @brief  This function handles I2C event interrupt request.
02367   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02368   *                the configuration information for the specified I2C.
02369   * @retval None
02370   */
02371 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
02372 {
02373   /* I2C in mode Transmitter ---------------------------------------------------*/
02374   if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET))
02375   {
02376     /* Slave mode selected */
02377     if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)
02378     {
02379       I2C_SlaveTransmit_ISR(hi2c);
02380     }
02381   }
02382
02383   if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET))
02384   {
02385     /* Master mode selected */
02386     if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))
02387     {
02388       I2C_MasterTransmit_ISR(hi2c);
02389     }
02390   }
02391
02392   /* I2C in mode Receiver ----------------------------------------------------*/
02393   if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET))
02394   {
02395     /* Slave mode selected */
02396     if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)
02397     {
02398       I2C_SlaveReceive_ISR(hi2c);
02399     }
02400   }
02401   if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET))
02402   {
02403     /* Master mode selected */
02404     if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
02405     {
02406       I2C_MasterReceive_ISR(hi2c);
02407     }
02408   }
02409 }
02410
02411 /**
02412   * @brief  This function handles I2C error interrupt request.
02413   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02414   *                the configuration information for the specified I2C.
02415   * @retval None
02416   */
02417 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
02418 {
02419   /* I2C Bus error interrupt occurred ------------------------------------*/
02420   if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
02421   {
02422     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
02423
02424     /* Clear BERR flag */
02425     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
02426   }
02427
02428   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02429   if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
02430   {
02431     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
02432
02433     /* Clear OVR flag */
02434     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
02435   }
02436
02437   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
02438   if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
02439   {
02440     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
02441
02442     /* Clear ARLO flag */
02443     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
02444   }
02445
02446   /* Call the Error Callback in case of Error detected */
02447   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
02448   {
02449     hi2c->State = HAL_I2C_STATE_READY;
02450
02451     HAL_I2C_ErrorCallback(hi2c);
02452   }
02453 }
02454
02455 /**
02456   * @brief  Master Tx Transfer completed callbacks.
02457   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02458   *                the configuration information for the specified I2C.
02459   * @retval None
02460   */
02461  __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
02462 {
02463   /* Prevent unused argument(s) compilation warning */
02464   UNUSED(hi2c);
02465
02466   /* NOTE : This function Should not be modified, when the callback is needed,
02467             the HAL_I2C_TxCpltCallback could be implemented in the user file
02468    */
02469 }
02470
02471 /**
02472   * @brief  Master Rx Transfer completed callbacks.
02473   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02474   *                the configuration information for the specified I2C.
02475   * @retval None
02476   */
02477 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
02478 {
02479   /* Prevent unused argument(s) compilation warning */
02480   UNUSED(hi2c);
02481
02482   /* NOTE : This function Should not be modified, when the callback is needed,
02483             the HAL_I2C_TxCpltCallback could be implemented in the user file
02484    */
02485 }
02486
02487 /** @brief  Slave Tx Transfer completed callbacks.
02488   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02489   *                the configuration information for the specified I2C.
02490   * @retval None
02491   */
02492  __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
02493 {
02494   /* Prevent unused argument(s) compilation warning */
02495   UNUSED(hi2c);
02496
02497   /* NOTE : This function Should not be modified, when the callback is needed,
02498             the HAL_I2C_TxCpltCallback could be implemented in the user file
02499    */
02500 }
02501
02502 /**
02503   * @brief  Slave Rx Transfer completed callbacks.
02504   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02505   *                the configuration information for the specified I2C.
02506   * @retval None
02507   */
02508 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
02509 {
02510   /* Prevent unused argument(s) compilation warning */
02511   UNUSED(hi2c);
02512
02513   /* NOTE : This function Should not be modified, when the callback is needed,
02514             the HAL_I2C_TxCpltCallback could be implemented in the user file
02515    */
02516 }
02517
02518 /**
02519   * @brief  Memory Tx Transfer completed callbacks.
02520   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02521   *                the configuration information for the specified I2C.
02522   * @retval None
02523   */
02524  __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
02525 {
02526   /* Prevent unused argument(s) compilation warning */
02527   UNUSED(hi2c);
02528
02529   /* NOTE : This function Should not be modified, when the callback is needed,
02530             the HAL_I2C_TxCpltCallback could be implemented in the user file
02531    */
02532 }
02533
02534 /**
02535   * @brief  Memory Rx Transfer completed callbacks.
02536   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02537   *                the configuration information for the specified I2C.
02538   * @retval None
02539   */
02540 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
02541 {
02542   /* Prevent unused argument(s) compilation warning */
02543   UNUSED(hi2c);
02544
02545   /* NOTE : This function Should not be modified, when the callback is needed,
02546             the HAL_I2C_TxCpltCallback could be implemented in the user file
02547    */
02548 }
02549
02550 /**
02551   * @brief  I2C error callbacks.
02552   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02553   *                the configuration information for the specified I2C.
02554   * @retval None
02555   */
02556  __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
02557 {
02558   /* Prevent unused argument(s) compilation warning */
02559   UNUSED(hi2c);
02560
02561   /* NOTE : This function Should not be modified, when the callback is needed,
02562             the HAL_I2C_ErrorCallback could be implemented in the user file
02563    */
02564 }
02565
02566 /**
02567   * @}
02568   */
02569
02570 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
02571  *  @brief   Peripheral State and Errors functions
02572  *
02573 @verbatim
02574  ===============================================================================
02575             ##### Peripheral State and Errors functions #####
02576  ===============================================================================
02577     [..]
02578     This subsection permit to get in run-time the status of the peripheral
02579     and the data flow.
02580
02581 @endverbatim
02582   * @{
02583   */
02584
02585 /**
02586   * @brief  Returns the I2C state.
02587   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02588   *                the configuration information for the specified I2C.
02589   * @retval HAL state
02590   */
02591 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
02592 {
02593   return hi2c->State;
02594 }
02595
02596 /**
02597   * @brief  Return the I2C error code
02598   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02599   *              the configuration information for the specified I2C.
02600 * @retval I2C Error Code
02601 */
02602 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
02603 {
02604   return hi2c->ErrorCode;
02605 }
02606
02607 /**
02608   * @}
02609   */
02610
02611 /**
02612   * @}
02613   */
02614
02615 /** @addtogroup I2C_Private_Functions
02616   * @{
02617   */
02618
02619 /**
02620   * @brief  Handle Interrupt Flags Master Transmit Mode
02621   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02622   *                the configuration information for the specified I2C.
02623   * @retval HAL status
02624   */
02625 static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
02626 {
02627   uint16_t DevAddress;
02628
02629   /* Process Locked */
02630   __HAL_LOCK(hi2c);
02631
02632   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
02633   {
02634     /* Write data to TXDR */
02635     hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
02636     hi2c->XferSize--;
02637     hi2c->XferCount--;
02638   }
02639   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
02640   {
02641     if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
02642     {
02643       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
02644
02645       if(hi2c->XferCount > 255)
02646       {
02647         I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02648         hi2c->XferSize = 255;
02649       }
02650       else
02651       {
02652         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02653         hi2c->XferSize = hi2c->XferCount;
02654       }
02655     }
02656     else
02657     {
02658       /* Process Unlocked */
02659       __HAL_UNLOCK(hi2c);
02660
02661       /* Wrong size Status regarding TCR flag event */
02662       hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
02663       HAL_I2C_ErrorCallback(hi2c);
02664     }
02665   }
02666   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
02667   {
02668     if(hi2c->XferCount == 0)
02669     {
02670       /* Generate Stop */
02671       hi2c->Instance->CR2 |= I2C_CR2_STOP;
02672     }
02673     else
02674     {
02675       /* Process Unlocked */
02676       __HAL_UNLOCK(hi2c);
02677
02678       /* Wrong size Status regarding TCR flag event */
02679       hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
02680       HAL_I2C_ErrorCallback(hi2c);
02681     }
02682   }
02683   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
02684   {
02685     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
02686     {
02687       /* Clear NACK Flag */
02688       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02689
02690       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
02691     }
02692
02693     /* Disable ERR, TC, STOP, NACK, TXI interrupt */
02694     __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
02695
02696     /* Clear STOP Flag */
02697     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02698
02699     /* Clear Configuration Register 2 */
02700     I2C_RESET_CR2(hi2c);
02701
02702     /* Flush TX register if not empty */
02703     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
02704     {
02705       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
02706     }
02707
02708     /* Call the correct callback to inform upper layer */
02709     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
02710     {
02711       hi2c->State = HAL_I2C_STATE_READY;
02712
02713       /* Process Unlocked */
02714       __HAL_UNLOCK(hi2c);
02715
02716       HAL_I2C_ErrorCallback(hi2c);
02717     }
02718     else
02719     {
02720       if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
02721       {
02722         hi2c->State = HAL_I2C_STATE_READY;
02723
02724         /* Process Unlocked */
02725         __HAL_UNLOCK(hi2c);
02726
02727         HAL_I2C_MemTxCpltCallback(hi2c);
02728       }
02729       else
02730       {
02731         hi2c->State = HAL_I2C_STATE_READY;
02732
02733         /* Process Unlocked */
02734         __HAL_UNLOCK(hi2c);
02735
02736         HAL_I2C_MasterTxCpltCallback(hi2c);
02737       }
02738     }
02739   }
02740   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
02741   {
02742     /* Clear NACK Flag */
02743     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02744
02745     /* Process Unlocked */
02746     __HAL_UNLOCK(hi2c);
02747
02748     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
02749     HAL_I2C_ErrorCallback(hi2c);
02750   }
02751
02752   /* Process Unlocked */
02753   __HAL_UNLOCK(hi2c);
02754
02755   return HAL_OK;
02756 }
02757
02758 /**
02759   * @brief  Handle Interrupt Flags Master Receive Mode
02760   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02761   *                the configuration information for the specified I2C.
02762   * @retval HAL status
02763   */
02764 static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
02765 {
02766   uint16_t DevAddress;
02767
02768   /* Process Locked */
02769   __HAL_LOCK(hi2c);
02770
02771   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
02772   {
02773     /* Read data from RXDR */
02774     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
02775     hi2c->XferSize--;
02776     hi2c->XferCount--;
02777   }
02778   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
02779   {
02780     if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
02781     {
02782       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
02783
02784       if(hi2c->XferCount > 255)
02785       {
02786         I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02787         hi2c->XferSize = 255;
02788       }
02789       else
02790       {
02791         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02792         hi2c->XferSize = hi2c->XferCount;
02793       }
02794     }
02795     else
02796     {
02797       /* Process Unlocked */
02798       __HAL_UNLOCK(hi2c);
02799
02800       /* Wrong size Status regarding TCR flag event */
02801       hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
02802       HAL_I2C_ErrorCallback(hi2c);
02803     }
02804   }
02805   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
02806   {
02807     if(hi2c->XferCount == 0)
02808     {
02809       /* Generate Stop */
02810       hi2c->Instance->CR2 |= I2C_CR2_STOP;
02811     }
02812     else
02813     {
02814       /* Process Unlocked */
02815       __HAL_UNLOCK(hi2c);
02816
02817       /* Wrong size Status regarding TCR flag event */
02818       hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
02819       HAL_I2C_ErrorCallback(hi2c);
02820     }
02821   }
02822   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
02823   {
02824     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
02825     {
02826       /* Clear NACK Flag */
02827       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02828
02829       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
02830     }
02831
02832     /* Disable ERR, TC, STOP, NACK, TXI interrupt */
02833     __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
02834
02835     /* Clear STOP Flag */
02836     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02837
02838     /* Clear Configuration Register 2 */
02839     I2C_RESET_CR2(hi2c);
02840
02841     /* Call the correct callback to inform upper layer */
02842     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
02843     {
02844       hi2c->State = HAL_I2C_STATE_READY;
02845
02846       /* Process Unlocked */
02847       __HAL_UNLOCK(hi2c);
02848
02849       HAL_I2C_ErrorCallback(hi2c);
02850     }
02851     else
02852     {
02853       if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
02854       {
02855         hi2c->State = HAL_I2C_STATE_READY;
02856
02857         /* Process Unlocked */
02858         __HAL_UNLOCK(hi2c);
02859
02860         HAL_I2C_MemRxCpltCallback(hi2c);
02861       }
02862       else
02863       {
02864         hi2c->State = HAL_I2C_STATE_READY;
02865
02866         /* Process Unlocked */
02867         __HAL_UNLOCK(hi2c);
02868
02869         HAL_I2C_MasterRxCpltCallback(hi2c);
02870       }
02871     }
02872   }
02873   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
02874   {
02875     /* Clear NACK Flag */
02876     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02877
02878     /* Process Unlocked */
02879     __HAL_UNLOCK(hi2c);
02880
02881     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
02882     HAL_I2C_ErrorCallback(hi2c);
02883   }
02884
02885   /* Process Unlocked */
02886   __HAL_UNLOCK(hi2c);
02887
02888   return HAL_OK;
02889
02890 }
02891
02892 /**
02893   * @brief  Handle Interrupt Flags Slave Transmit Mode
02894   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02895   *                the configuration information for the specified I2C.
02896   * @retval HAL status
02897   */
02898 static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
02899 {
02900   /* Process locked */
02901   __HAL_LOCK(hi2c);
02902
02903   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
02904   {
02905     /* Check that I2C transfer finished */
02906     /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
02907     /* Mean XferCount == 0*/
02908     /* So clear Flag NACKF only */
02909     if(hi2c->XferCount == 0)
02910     {
02911       /* Clear NACK Flag */
02912       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02913
02914       /* Process Unlocked */
02915       __HAL_UNLOCK(hi2c);
02916     }
02917     else
02918     {
02919       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
02920       /* Clear NACK Flag */
02921       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02922
02923       /* Set ErrorCode corresponding to a Non-Acknowledge */
02924       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
02925
02926       /* Process Unlocked */
02927       __HAL_UNLOCK(hi2c);
02928
02929       /* Call the Error callback to prevent upper layer */
02930       HAL_I2C_ErrorCallback(hi2c);
02931     }
02932   }
02933   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
02934   {
02935     /* Clear ADDR flag */
02936     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
02937   }
02938   /* Check first if STOPF is set          */
02939   /* to prevent a Write Data in TX buffer */
02940   /* which is stuck in TXDR until next    */
02941   /* communication with Master            */
02942   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
02943   {
02944     /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
02945     __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );
02946
02947     /* Disable Address Acknowledge */
02948     hi2c->Instance->CR2 |= I2C_CR2_NACK;
02949
02950     /* Clear STOP Flag */
02951     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02952
02953     hi2c->State = HAL_I2C_STATE_READY;
02954
02955     /* Process Unlocked */
02956     __HAL_UNLOCK(hi2c);
02957
02958     HAL_I2C_SlaveTxCpltCallback(hi2c);
02959   }
02960   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
02961   {
02962     /* Write data to TXDR only if XferCount not reach "0" */
02963     /* A TXIS flag can be set, during STOP treatment      */
02964     if(hi2c->XferCount > 0)
02965     {
02966       /* Write data to TXDR */
02967       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
02968       hi2c->XferCount--;
02969     }
02970   }
02971
02972   /* Process Unlocked */
02973   __HAL_UNLOCK(hi2c);
02974
02975   return HAL_OK;
02976 }
02977
02978 /**
02979   * @brief  Handle Interrupt Flags Slave Receive Mode
02980   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
02981   *                the configuration information for the specified I2C.
02982   * @retval HAL status
02983   */
02984 static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
02985 {
02986   /* Process Locked */
02987   __HAL_LOCK(hi2c);
02988
02989   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
02990   {
02991     /* Clear NACK Flag */
02992     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02993
02994     /* Process Unlocked */
02995     __HAL_UNLOCK(hi2c);
02996
02997     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
02998     HAL_I2C_ErrorCallback(hi2c);
02999   }
03000   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
03001   {
03002     /* Clear ADDR flag */
03003     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03004   }
03005   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
03006   {
03007     /* Read data from RXDR */
03008     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03009     hi2c->XferSize--;
03010     hi2c->XferCount--;
03011   }
03012   else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
03013   {
03014     /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
03015     __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI );
03016
03017     /* Disable Address Acknowledge */
03018     hi2c->Instance->CR2 |= I2C_CR2_NACK;
03019
03020     /* Clear STOP Flag */
03021     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03022
03023     hi2c->State = HAL_I2C_STATE_READY;
03024
03025     /* Process Unlocked */
03026     __HAL_UNLOCK(hi2c);
03027
03028     HAL_I2C_SlaveRxCpltCallback(hi2c);
03029   }
03030
03031   /* Process Unlocked */
03032   __HAL_UNLOCK(hi2c);
03033
03034   return HAL_OK;
03035 }
03036
03037 /**
03038   * @brief  Master sends target device address followed by internal memory address for write request.
03039   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
03040   *                the configuration information for the specified I2C.
03041   * @param  DevAddress: Target device address
03042   * @param  MemAddress: Internal memory address
03043   * @param  MemAddSize: Size of internal memory address
03044   * @param  Timeout: Timeout duration
03045   * @retval HAL status
03046   */
03047 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
03048 {
03049   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
03050
03051   /* Wait until TXIS flag is set */
03052   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
03053   {
03054     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03055     {
03056       return HAL_ERROR;
03057     }
03058     else
03059     {
03060       return HAL_TIMEOUT;
03061     }
03062   }
03063
03064   /* If Memory address size is 8Bit */
03065   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03066   {
03067     /* Send Memory Address */
03068     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03069   }
03070   /* If Memory address size is 16Bit */
03071   else
03072   {
03073     /* Send MSB of Memory Address */
03074     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03075
03076     /* Wait until TXIS flag is set */
03077     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
03078     {
03079       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03080       {
03081         return HAL_ERROR;
03082       }
03083       else
03084       {
03085         return HAL_TIMEOUT;
03086       }
03087     }
03088
03089     /* Send LSB of Memory Address */
03090     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03091   }
03092
03093   /* Wait until TCR flag is set */
03094   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
03095   {
03096     return HAL_TIMEOUT;
03097   }
03098
03099   return HAL_OK;
03100 }
03101
03102 /**
03103   * @brief  Master sends target device address followed by internal memory address for read request.
03104   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
03105   *                the configuration information for the specified I2C.
03106   * @param  DevAddress: Target device address
03107   * @param  MemAddress: Internal memory address
03108   * @param  MemAddSize: Size of internal memory address
03109   * @param  Timeout: Timeout duration
03110   * @retval HAL status
03111   */
03112 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
03113 {
03114   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03115
03116   /* Wait until TXIS flag is set */
03117   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
03118   {
03119     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03120     {
03121       return HAL_ERROR;
03122     }
03123     else
03124     {
03125       return HAL_TIMEOUT;
03126     }
03127   }
03128
03129   /* If Memory address size is 8Bit */
03130   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03131   {
03132     /* Send Memory Address */
03133     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03134   }
03135   /* If Memory address size is 16Bit */
03136   else
03137   {
03138     /* Send MSB of Memory Address */
03139     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03140
03141     /* Wait until TXIS flag is set */
03142     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
03143     {
03144       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03145       {
03146         return HAL_ERROR;
03147       }
03148       else
03149       {
03150         return HAL_TIMEOUT;
03151       }
03152     }
03153
03154     /* Send LSB of Memory Address */
03155     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03156   }
03157
03158   /* Wait until TC flag is set */
03159   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK)
03160   {
03161     return HAL_TIMEOUT;
03162   }
03163
03164   return HAL_OK;
03165 }
03166
03167 /**
03168   * @brief  DMA I2C master transmit process complete callback.
03169   * @param  hdma: DMA handle
03170   * @retval None
03171   */
03172 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
03173 {
03174   uint16_t DevAddress;
03175   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
03176
03177   /* Check if last DMA request was done with RELOAD */
03178   /* Set NBYTES to write and reload if size > 255 */
03179   if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03180   {
03181     /* Wait until TCR flag is set */
03182     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
03183     {
03184       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03185     }
03186
03187     /* Disable DMA Request */
03188     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03189
03190     /* Check if Errors has been detected during transfer */
03191     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03192     {
03193       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03194       /* Wait until STOPF flag is reset */
03195       if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03196       {
03197         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03198         {
03199           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03200         }
03201         else
03202         {
03203           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03204         }
03205       }
03206
03207       /* Clear STOP Flag */
03208       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03209
03210       /* Clear Configuration Register 2 */
03211       I2C_RESET_CR2(hi2c);
03212
03213       hi2c->XferCount = 0;
03214
03215       hi2c->State = HAL_I2C_STATE_READY;
03216       HAL_I2C_ErrorCallback(hi2c);
03217     }
03218     else
03219     {
03220       hi2c->pBuffPtr += hi2c->XferSize;
03221       hi2c->XferCount -= hi2c->XferSize;
03222       if(hi2c->XferCount > 255)
03223       {
03224         hi2c->XferSize = 255;
03225       }
03226       else
03227       {
03228         hi2c->XferSize = hi2c->XferCount;
03229       }
03230
03231       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03232
03233       /* Enable the DMA channel */
03234       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03235
03236       /* Send Slave Address */
03237       /* Set NBYTES to write and reload if size > 255 */
03238       if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03239       {
03240         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03241       }
03242       else
03243       {
03244         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03245       }
03246
03247       /* Wait until TXIS flag is set */
03248       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
03249       {
03250         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03251         /* Wait until STOPF flag is reset */
03252         if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03253         {
03254           if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03255           {
03256             hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03257           }
03258           else
03259           {
03260             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03261           }
03262         }
03263
03264         /* Clear STOP Flag */
03265         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03266
03267         /* Clear Configuration Register 2 */
03268         I2C_RESET_CR2(hi2c);
03269
03270         hi2c->XferCount = 0;
03271
03272         hi2c->State = HAL_I2C_STATE_READY;
03273         HAL_I2C_ErrorCallback(hi2c);
03274       }
03275       else
03276       {
03277         /* Enable DMA Request */
03278         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03279       }
03280     }
03281   }
03282   else
03283   {
03284     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03285     /* Wait until STOPF flag is reset */
03286     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03287     {
03288       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03289       {
03290         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03291       }
03292       else
03293       {
03294         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03295       }
03296     }
03297
03298     /* Clear STOP Flag */
03299     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03300
03301     /* Clear Configuration Register 2 */
03302     I2C_RESET_CR2(hi2c);
03303
03304     /* Disable DMA Request */
03305     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03306
03307     hi2c->XferCount = 0;
03308
03309     hi2c->State = HAL_I2C_STATE_READY;
03310
03311     /* Check if Errors has been detected during transfer */
03312     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03313     {
03314       HAL_I2C_ErrorCallback(hi2c);
03315     }
03316     else
03317     {
03318       HAL_I2C_MasterTxCpltCallback(hi2c);
03319     }
03320   }
03321 }
03322
03323 /**
03324   * @brief  DMA I2C slave transmit process complete callback.
03325   * @param  hdma: DMA handle
03326   * @retval None
03327   */
03328 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
03329 {
03330   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
03331
03332   /* Wait until STOP flag is set */
03333   if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03334   {
03335     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03336     {
03337       /* Normal Use case, a AF is generated by master */
03338       /* to inform slave the end of transfer */
03339       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03340     }
03341     else
03342     {
03343       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03344     }
03345   }
03346
03347   /* Clear STOP flag */
03348   __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
03349
03350   /* Wait until BUSY flag is reset */
03351   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
03352   {
03353     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03354   }
03355
03356   /* Disable DMA Request */
03357   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03358
03359   hi2c->XferCount = 0;
03360
03361   hi2c->State = HAL_I2C_STATE_READY;
03362
03363   /* Check if Errors has been detected during transfer */
03364   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03365   {
03366     HAL_I2C_ErrorCallback(hi2c);
03367   }
03368   else
03369   {
03370     HAL_I2C_SlaveTxCpltCallback(hi2c);
03371   }
03372 }
03373
03374 /**
03375   * @brief DMA I2C master receive process complete callback
03376   * @param  hdma: DMA handle
03377   * @retval None
03378   */
03379 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
03380 {
03381   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
03382   uint16_t DevAddress;
03383
03384   /* Check if last DMA request was done with RELOAD */
03385   /* Set NBYTES to write and reload if size > 255 */
03386   if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03387   {
03388     /* Wait until TCR flag is set */
03389     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
03390     {
03391       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03392     }
03393
03394     /* Disable DMA Request */
03395     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03396
03397     /* Check if Errors has been detected during transfer */
03398     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03399     {
03400       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03401       /* Wait until STOPF flag is reset */
03402       if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03403       {
03404         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03405         {
03406           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03407         }
03408         else
03409         {
03410           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03411         }
03412       }
03413
03414       /* Clear STOP Flag */
03415       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03416
03417       /* Clear Configuration Register 2 */
03418       I2C_RESET_CR2(hi2c);
03419
03420       hi2c->XferCount = 0;
03421
03422       hi2c->State = HAL_I2C_STATE_READY;
03423       HAL_I2C_ErrorCallback(hi2c);
03424     }
03425     else
03426     {
03427       hi2c->pBuffPtr += hi2c->XferSize;
03428       hi2c->XferCount -= hi2c->XferSize;
03429       if(hi2c->XferCount > 255)
03430       {
03431         hi2c->XferSize = 255;
03432       }
03433       else
03434       {
03435         hi2c->XferSize = hi2c->XferCount;
03436       }
03437
03438       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03439
03440       /* Enable the DMA channel */
03441       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
03442
03443       /* Send Slave Address */
03444       /* Set NBYTES to write and reload if size > 255 */
03445       if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03446       {
03447         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03448       }
03449       else
03450       {
03451         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03452       }
03453
03454       /* Wait until RXNE flag is set */
03455       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
03456       {
03457         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03458       }
03459
03460       /* Check if Errors has been detected during transfer */
03461       if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03462       {
03463         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03464         /* Wait until STOPF flag is reset */
03465         if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03466         {
03467           if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03468           {
03469             hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03470           }
03471           else
03472           {
03473             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03474           }
03475         }
03476
03477         /* Clear STOP Flag */
03478         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03479
03480         /* Clear Configuration Register 2 */
03481         I2C_RESET_CR2(hi2c);
03482
03483         hi2c->XferCount = 0;
03484
03485         hi2c->State = HAL_I2C_STATE_READY;
03486
03487         HAL_I2C_ErrorCallback(hi2c);
03488       }
03489       else
03490       {
03491         /* Enable DMA Request */
03492         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03493       }
03494     }
03495   }
03496   else
03497   {
03498     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03499     /* Wait until STOPF flag is reset */
03500     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03501     {
03502       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03503       {
03504         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03505       }
03506       else
03507       {
03508         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03509       }
03510     }
03511
03512     /* Clear STOP Flag */
03513     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03514
03515     /* Clear Configuration Register 2 */
03516     I2C_RESET_CR2(hi2c);
03517
03518     /* Disable DMA Request */
03519     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03520
03521     hi2c->XferCount = 0;
03522
03523     hi2c->State = HAL_I2C_STATE_READY;
03524
03525     /* Check if Errors has been detected during transfer */
03526     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03527     {
03528       HAL_I2C_ErrorCallback(hi2c);
03529     }
03530     else
03531     {
03532       HAL_I2C_MasterRxCpltCallback(hi2c);
03533     }
03534   }
03535 }
03536
03537 /**
03538   * @brief  DMA I2C slave receive process complete callback.
03539   * @param  hdma: DMA handle
03540   * @retval None
03541   */
03542 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
03543 {
03544   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
03545
03546   /* Wait until STOPF flag is reset */
03547   if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03548   {
03549     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03550     {
03551       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03552     }
03553     else
03554     {
03555       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03556     }
03557   }
03558
03559   /* Clear STOPF flag */
03560   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03561
03562   /* Wait until BUSY flag is reset */
03563   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
03564   {
03565     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03566   }
03567
03568   /* Disable DMA Request */
03569   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03570
03571   /* Disable Address Acknowledge */
03572   hi2c->Instance->CR2 |= I2C_CR2_NACK;
03573
03574   hi2c->XferCount = 0;
03575
03576   hi2c->State = HAL_I2C_STATE_READY;
03577
03578   /* Check if Errors has been detected during transfer */
03579   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03580   {
03581     HAL_I2C_ErrorCallback(hi2c);
03582   }
03583   else
03584   {
03585     HAL_I2C_SlaveRxCpltCallback(hi2c);
03586   }
03587 }
03588
03589 /**
03590   * @brief DMA I2C Memory Write process complete callback
03591   * @param hdma : DMA handle
03592   * @retval None
03593   */
03594 static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
03595 {
03596   uint16_t DevAddress;
03597   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
03598
03599   /* Check if last DMA request was done with RELOAD */
03600   /* Set NBYTES to write and reload if size > 255 */
03601   if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03602   {
03603     /* Wait until TCR flag is set */
03604     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
03605     {
03606       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03607     }
03608
03609     /* Disable DMA Request */
03610     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03611
03612     /* Check if Errors has been detected during transfer */
03613     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03614     {
03615       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03616       /* Wait until STOPF flag is reset */
03617       if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03618       {
03619         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03620         {
03621           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03622         }
03623         else
03624         {
03625           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03626         }
03627       }
03628
03629       /* Clear STOP Flag */
03630       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03631
03632       /* Clear Configuration Register 2 */
03633       I2C_RESET_CR2(hi2c);
03634
03635       hi2c->XferCount = 0;
03636
03637       hi2c->State = HAL_I2C_STATE_READY;
03638       HAL_I2C_ErrorCallback(hi2c);
03639     }
03640     else
03641     {
03642       hi2c->pBuffPtr += hi2c->XferSize;
03643       hi2c->XferCount -= hi2c->XferSize;
03644       if(hi2c->XferCount > 255)
03645       {
03646         hi2c->XferSize = 255;
03647       }
03648       else
03649       {
03650         hi2c->XferSize = hi2c->XferCount;
03651       }
03652
03653       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03654
03655       /* Enable the DMA channel */
03656       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03657
03658       /* Send Slave Address */
03659       /* Set NBYTES to write and reload if size > 255 */
03660       if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03661       {
03662         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03663       }
03664       else
03665       {
03666         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03667       }
03668
03669       /* Wait until TXIS flag is set */
03670       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
03671       {
03672         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03673         /* Wait until STOPF flag is reset */
03674         if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03675         {
03676           if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03677           {
03678             hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03679           }
03680           else
03681           {
03682             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03683           }
03684         }
03685
03686         /* Clear STOP Flag */
03687         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03688
03689         /* Clear Configuration Register 2 */
03690         I2C_RESET_CR2(hi2c);
03691
03692         hi2c->XferCount = 0;
03693
03694         hi2c->State = HAL_I2C_STATE_READY;
03695         HAL_I2C_ErrorCallback(hi2c);
03696       }
03697       else
03698       {
03699         /* Enable DMA Request */
03700         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03701       }
03702     }
03703   }
03704   else
03705   {
03706     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03707     /* Wait until STOPF flag is reset */
03708     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03709     {
03710       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03711       {
03712         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03713       }
03714       else
03715       {
03716         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03717       }
03718     }
03719
03720     /* Clear STOP Flag */
03721     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03722
03723     /* Clear Configuration Register 2 */
03724     I2C_RESET_CR2(hi2c);
03725
03726     /* Disable DMA Request */
03727     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03728
03729     hi2c->XferCount = 0;
03730
03731     hi2c->State = HAL_I2C_STATE_READY;
03732
03733     /* Check if Errors has been detected during transfer */
03734     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03735     {
03736       HAL_I2C_ErrorCallback(hi2c);
03737     }
03738     else
03739     {
03740       HAL_I2C_MemTxCpltCallback(hi2c);
03741     }
03742   }
03743 }
03744
03745 /**
03746   * @brief  DMA I2C Memory Read process complete callback
03747   * @param  hdma: DMA handle
03748   * @retval None
03749   */
03750 static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
03751 {
03752   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
03753   uint16_t DevAddress;
03754
03755   /* Check if last DMA request was done with RELOAD */
03756   /* Set NBYTES to write and reload if size > 255 */
03757   if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03758   {
03759     /* Wait until TCR flag is set */
03760     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
03761     {
03762       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03763     }
03764
03765     /* Disable DMA Request */
03766     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03767
03768     /* Check if Errors has been detected during transfer */
03769     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03770     {
03771       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03772       /* Wait until STOPF flag is reset */
03773       if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03774       {
03775         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03776         {
03777           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03778         }
03779         else
03780         {
03781           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03782         }
03783       }
03784
03785       /* Clear STOP Flag */
03786       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03787
03788       /* Clear Configuration Register 2 */
03789       I2C_RESET_CR2(hi2c);
03790
03791       hi2c->XferCount = 0;
03792
03793       hi2c->State = HAL_I2C_STATE_READY;
03794       HAL_I2C_ErrorCallback(hi2c);
03795     }
03796     else
03797     {
03798       hi2c->pBuffPtr += hi2c->XferSize;
03799       hi2c->XferCount -= hi2c->XferSize;
03800       if(hi2c->XferCount > 255)
03801       {
03802         hi2c->XferSize = 255;
03803       }
03804       else
03805       {
03806         hi2c->XferSize = hi2c->XferCount;
03807       }
03808
03809       DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03810
03811       /* Enable the DMA channel */
03812       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
03813
03814       /* Send Slave Address */
03815       /* Set NBYTES to write and reload if size > 255 */
03816       if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
03817       {
03818         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03819       }
03820       else
03821       {
03822         I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03823       }
03824
03825       /* Wait until RXNE flag is set */
03826       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
03827       {
03828         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03829       }
03830
03831       /* Check if Errors has been detected during transfer */
03832       if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03833       {
03834         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03835         /* Wait until STOPF flag is reset */
03836         if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03837         {
03838           if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03839           {
03840             hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03841           }
03842           else
03843           {
03844             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03845           }
03846         }
03847
03848         /* Clear STOP Flag */
03849         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03850
03851         /* Clear Configuration Register 2 */
03852         I2C_RESET_CR2(hi2c);
03853
03854         hi2c->XferCount = 0;
03855
03856         hi2c->State = HAL_I2C_STATE_READY;
03857         HAL_I2C_ErrorCallback(hi2c);
03858       }
03859       else
03860       {
03861         /* Enable DMA Request */
03862         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03863       }
03864     }
03865   }
03866   else
03867   {
03868     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03869     /* Wait until STOPF flag is reset */
03870     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
03871     {
03872       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03873       {
03874         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03875       }
03876       else
03877       {
03878         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03879       }
03880     }
03881
03882     /* Clear STOP Flag */
03883     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03884
03885     /* Clear Configuration Register 2 */
03886     I2C_RESET_CR2(hi2c);
03887
03888     /* Disable DMA Request */
03889     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03890
03891     hi2c->XferCount = 0;
03892
03893     hi2c->State = HAL_I2C_STATE_READY;
03894
03895     /* Check if Errors has been detected during transfer */
03896     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03897     {
03898       HAL_I2C_ErrorCallback(hi2c);
03899     }
03900     else
03901     {
03902       HAL_I2C_MemRxCpltCallback(hi2c);
03903     }
03904   }
03905 }
03906
03907 /**
03908   * @brief  DMA I2C communication error callback.
03909   * @param hdma : DMA handle
03910   * @retval None
03911   */
03912 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
03913 {
03914   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
03915
03916   /* Disable Acknowledge */
03917   hi2c->Instance->CR2 |= I2C_CR2_NACK;
03918
03919   hi2c->XferCount = 0;
03920
03921   hi2c->State = HAL_I2C_STATE_READY;
03922
03923   hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03924
03925   HAL_I2C_ErrorCallback(hi2c);
03926 }
03927
03928 /**
03929   * @brief  This function handles I2C Communication Timeout.
03930   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
03931   *                the configuration information for the specified I2C.
03932   * @param  Flag: specifies the I2C flag to check.
03933   * @param  Status: The new Flag status (SET or RESET).
03934   * @param  Timeout: Timeout duration
03935   * @retval HAL status
03936   */
03937 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
03938 {
03939   uint32_t tickstart = HAL_GetTick();
03940
03941   /* Wait until flag is set */
03942   if(Status == RESET)
03943   {
03944     while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
03945     {
03946       /* Check for the Timeout */
03947       if(Timeout != HAL_MAX_DELAY)
03948       {
03949         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
03950         {
03951           hi2c->State= HAL_I2C_STATE_READY;
03952           /* Process Unlocked */
03953           __HAL_UNLOCK(hi2c);
03954           return HAL_TIMEOUT;
03955         }
03956       }
03957     }
03958   }
03959   else
03960   {
03961     while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
03962     {
03963       /* Check for the Timeout */
03964       if(Timeout != HAL_MAX_DELAY)
03965       {
03966         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
03967         {
03968           hi2c->State= HAL_I2C_STATE_READY;
03969           /* Process Unlocked */
03970           __HAL_UNLOCK(hi2c);
03971           return HAL_TIMEOUT;
03972         }
03973       }
03974     }
03975   }
03976   return HAL_OK;
03977 }
03978
03979 /**
03980   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
03981   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
03982   *                the configuration information for the specified I2C.
03983   * @param  Timeout: Timeout duration
03984   * @retval HAL status
03985   */
03986 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
03987 {
03988   uint32_t tickstart = HAL_GetTick();
03989
03990   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
03991   {
03992     /* Check if a NACK is detected */
03993     if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
03994     {
03995       return HAL_ERROR;
03996     }
03997
03998     /* Check for the Timeout */
03999     if(Timeout != HAL_MAX_DELAY)
04000     {
04001       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
04002       {
04003         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04004         hi2c->State= HAL_I2C_STATE_READY;
04005
04006         /* Process Unlocked */
04007         __HAL_UNLOCK(hi2c);
04008
04009         return HAL_TIMEOUT;
04010       }
04011     }
04012   }
04013   return HAL_OK;
04014 }
04015
04016 /**
04017   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
04018   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
04019   *                the configuration information for the specified I2C.
04020   * @param  Timeout: Timeout duration
04021   * @retval HAL status
04022   */
04023 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04024 {
04025   uint32_t tickstart = 0x00;
04026   tickstart = HAL_GetTick();
04027
04028   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04029   {
04030     /* Check if a NACK is detected */
04031     if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
04032     {
04033       return HAL_ERROR;
04034     }
04035
04036     /* Check for the Timeout */
04037     if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
04038     {
04039       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04040       hi2c->State= HAL_I2C_STATE_READY;
04041
04042       /* Process Unlocked */
04043       __HAL_UNLOCK(hi2c);
04044
04045       return HAL_TIMEOUT;
04046     }
04047   }
04048   return HAL_OK;
04049 }
04050
04051 /**
04052   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
04053   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
04054   *                the configuration information for the specified I2C.
04055   * @param  Timeout: Timeout duration
04056   * @retval HAL status
04057   */
04058 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04059 {
04060   uint32_t tickstart = 0x00;
04061   tickstart = HAL_GetTick();
04062
04063   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
04064   {
04065     /* Check if a NACK is detected */
04066     if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
04067     {
04068       return HAL_ERROR;
04069     }
04070
04071     /* Check if a STOPF is detected */
04072     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
04073     {
04074       /* Clear STOP Flag */
04075       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04076
04077       /* Clear Configuration Register 2 */
04078       I2C_RESET_CR2(hi2c);
04079
04080       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04081       hi2c->State= HAL_I2C_STATE_READY;
04082
04083       /* Process Unlocked */
04084       __HAL_UNLOCK(hi2c);
04085
04086       return HAL_ERROR;
04087     }
04088
04089     /* Check for the Timeout */
04090     if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
04091     {
04092       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04093       hi2c->State= HAL_I2C_STATE_READY;
04094
04095       /* Process Unlocked */
04096       __HAL_UNLOCK(hi2c);
04097
04098       return HAL_TIMEOUT;
04099     }
04100   }
04101   return HAL_OK;
04102 }
04103
04104 /**
04105   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
04106   * @param  hi2c : Pointer to a I2C_HandleTypeDef structure that contains
04107   *                the configuration information for the specified I2C.
04108   * @param  Timeout: Timeout duration
04109   * @retval HAL status
04110   */
04111 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04112 {
04113   uint32_t tickstart = 0x00;
04114   tickstart = HAL_GetTick();
04115
04116   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
04117   {
04118     /* Wait until STOP Flag is reset */
04119     /* AutoEnd should be initiate after AF */
04120     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04121     {
04122       /* Check for the Timeout */
04123       if(Timeout != HAL_MAX_DELAY)
04124       {
04125         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
04126         {
04127           hi2c->State= HAL_I2C_STATE_READY;
04128           /* Process Unlocked */
04129           __HAL_UNLOCK(hi2c);
04130           return HAL_TIMEOUT;
04131         }
04132       }
04133     }
04134
04135     /* Clear NACKF Flag */
04136     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04137
04138     /* Clear STOP Flag */
04139     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04140
04141     /* Flush TX register if not empty */
04142     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
04143     {
04144       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
04145     }
04146
04147     /* Clear Configuration Register 2 */
04148     I2C_RESET_CR2(hi2c);
04149
04150     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
04151     hi2c->State= HAL_I2C_STATE_READY;
04152
04153     /* Process Unlocked */
04154     __HAL_UNLOCK(hi2c);
04155
04156     return HAL_ERROR;
04157   }
04158   return HAL_OK;
04159 }
04160
04161 /**
04162   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
04163   * @param  hi2c: I2C handle.
04164   * @param  DevAddress: specifies the slave address to be programmed.
04165   * @param  Size: specifies the number of bytes to be programmed.
04166   *   This parameter must be a value between 0 and 255.
04167   * @param  Mode: new state of the I2C START condition generation.
04168   *   This parameter can be one of the following values:
04169   *     @arg I2C_RELOAD_MODE: Enable Reload mode .
04170   *     @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
04171   *     @arg I2C_SOFTEND_MODE: Enable Software end mode.
04172   * @param  Request: new state of the I2C START condition generation.
04173   *   This parameter can be one of the following values:
04174   *     @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.
04175   *     @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
04176   *     @arg I2C_GENERATE_START_READ: Generate Restart for read request.
04177   *     @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
04178   * @retval None
04179   */
04180 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
04181 {
04182   uint32_t tmpreg = 0;
04183
04184   /* Check the parameters */
04185   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
04186   assert_param(IS_TRANSFER_MODE(Mode));
04187   assert_param(IS_TRANSFER_REQUEST(Request));
04188
04189   /* Get the CR2 register value */
04190   tmpreg = hi2c->Instance->CR2;
04191
04192   /* clear tmpreg specific bits */
04193   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
04194
04195   /* update tmpreg */
04196   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
04197     (uint32_t)Mode | (uint32_t)Request);
04198
04199   /* update CR2 register */
04200   hi2c->Instance->CR2 = tmpreg;
04201 }
04202
04203 /**
04204   * @}
04205   */
04206
04207 /**
04208   * @}
04209   */
04210
04211 #endif /* HAL_I2C_MODULE_ENABLED */
04212 /**
04213   * @}
04214   */
04215
04216 /**
04217   * @}
04218   */
04219
04220 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c.h Source File

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stm32f7xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of I2C HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_I2C_H
00040 #define __STM32F7xx_HAL_I2C_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2C
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2C_Exported_Types I2C Exported Types
00059   * @{
00060   */
00061
00062 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00063   * @brief  I2C Configuration Structure definition
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00069                                   This parameter calculated by referring to I2C initialization
00070                                          section in Reference manual */
00071
00072   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00073                                   This parameter can be a 7-bit or 10-bit address. */
00074
00075   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00076                                   This parameter can be a value of @ref I2C_addressing_mode */
00077
00078   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00079                                   This parameter can be a value of @ref I2C_dual_addressing_mode */
00080
00081   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00082                                   This parameter can be a 7-bit address. */
00083
00084   uint32_t OwnAddress2Masks;    /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
00085                                   This parameter can be a value of @ref I2C_own_address2_masks */
00086
00087   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00088                                   This parameter can be a value of @ref I2C_general_call_addressing_mode */
00089
00090   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00091                                   This parameter can be a value of @ref I2C_nostretch_mode */
00092
00093 }I2C_InitTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup HAL_state_structure_definition HAL state structure definition
00100   * @brief  HAL State structure definition
00101   * @{
00102   */
00103
00104 typedef enum
00105 {
00106   HAL_I2C_STATE_RESET           = 0x00,  /*!< I2C not yet initialized or disabled         */
00107   HAL_I2C_STATE_READY           = 0x01,  /*!< I2C initialized and ready for use           */
00108   HAL_I2C_STATE_BUSY            = 0x02,  /*!< I2C internal process is ongoing             */
00109   HAL_I2C_STATE_MASTER_BUSY_TX  = 0x12,  /*!< Master Data Transmission process is ongoing */
00110   HAL_I2C_STATE_MASTER_BUSY_RX  = 0x22,  /*!< Master Data Reception process is ongoing    */
00111   HAL_I2C_STATE_SLAVE_BUSY_TX   = 0x32,  /*!< Slave Data Transmission process is ongoing  */
00112   HAL_I2C_STATE_SLAVE_BUSY_RX   = 0x42,  /*!< Slave Data Reception process is ongoing     */
00113   HAL_I2C_STATE_MEM_BUSY_TX     = 0x52,  /*!< Memory Data Transmission process is ongoing */
00114   HAL_I2C_STATE_MEM_BUSY_RX     = 0x62,  /*!< Memory Data Reception process is ongoing    */
00115   HAL_I2C_STATE_TIMEOUT         = 0x03,  /*!< Timeout state                               */
00116   HAL_I2C_STATE_ERROR           = 0x04   /*!< Reception process is ongoing                */
00117 }HAL_I2C_StateTypeDef;
00118
00119 /**
00120   * @}
00121   */
00122
00123 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00124   * @brief  I2C Error Code definition
00125   * @{
00126   */
00127 #define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
00128 #define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001)    /*!< BERR error            */
00129 #define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002)    /*!< ARLO error            */
00130 #define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004)    /*!< ACKF error            */
00131 #define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008)    /*!< OVR error             */
00132 #define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010)    /*!< DMA transfer error    */
00133 #define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
00134 #define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040)    /*!< Size Management error */
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00140   * @brief  I2C handle Structure definition
00141   * @{
00142   */
00143 typedef struct
00144 {
00145   I2C_TypeDef                *Instance;  /*!< I2C registers base address     */
00146
00147   I2C_InitTypeDef            Init;       /*!< I2C communication parameters   */
00148
00149   uint8_t                    *pBuffPtr;  /*!< Pointer to I2C transfer buffer */
00150
00151   uint16_t                   XferSize;   /*!< I2C transfer size              */
00152
00153   __IO uint16_t              XferCount;  /*!< I2C transfer counter           */
00154
00155   DMA_HandleTypeDef          *hdmatx;    /*!< I2C Tx DMA handle parameters   */
00156
00157   DMA_HandleTypeDef          *hdmarx;    /*!< I2C Rx DMA handle parameters   */
00158
00159   HAL_LockTypeDef            Lock;       /*!< I2C locking object             */
00160
00161   __IO HAL_I2C_StateTypeDef  State;      /*!< I2C communication state        */
00162
00163   __IO uint32_t              ErrorCode;  /*!< I2C Error code                   */
00164
00165 }I2C_HandleTypeDef;
00166 /**
00167   * @}
00168   */
00169
00170 /**
00171   * @}
00172   */
00173 /* Exported constants --------------------------------------------------------*/
00174
00175 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup I2C_addressing_mode I2C addressing mode
00180   * @{
00181   */
00182 #define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001)
00183 #define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002)
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
00189   * @{
00190   */
00191 #define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000)
00192 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup I2C_own_address2_masks I2C own address2 masks
00198   * @{
00199   */
00200 #define I2C_OA2_NOMASK                  ((uint8_t)0x00)
00201 #define I2C_OA2_MASK01                  ((uint8_t)0x01)
00202 #define I2C_OA2_MASK02                  ((uint8_t)0x02)
00203 #define I2C_OA2_MASK03                  ((uint8_t)0x03)
00204 #define I2C_OA2_MASK04                  ((uint8_t)0x04)
00205 #define I2C_OA2_MASK05                  ((uint8_t)0x05)
00206 #define I2C_OA2_MASK06                  ((uint8_t)0x06)
00207 #define I2C_OA2_MASK07                  ((uint8_t)0x07)
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
00213   * @{
00214   */
00215 #define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000)
00216 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup I2C_nostretch_mode I2C nostretch mode
00222   * @{
00223   */
00224 #define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000)
00225 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
00231   * @{
00232   */
00233 #define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
00234 #define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002)
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
00240   * @{
00241   */
00242 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00243 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00244 #define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000)
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
00250   * @{
00251   */
00252 #define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000)
00253 #define  I2C_GENERATE_STOP              I2C_CR2_STOP
00254 #define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00255 #define  I2C_GENERATE_START_WRITE       I2C_CR2_START
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00261   * @brief I2C Interrupt definition
00262   *        Elements values convention: 0xXXXXXXXX
00263   *           - XXXXXXXX  : Interrupt control mask
00264   * @{
00265   */
00266 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00267 #define I2C_IT_TCI                      I2C_CR1_TCIE
00268 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00269 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00270 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00271 #define I2C_IT_RXI                      I2C_CR1_RXIE
00272 #define I2C_IT_TXI                      I2C_CR1_TXIE
00273
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup I2C_Flag_definition I2C Flag definition
00279   * @{
00280   */
00281 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00282 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00283 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00284 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00285 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00286 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00287 #define I2C_FLAG_TC                     I2C_ISR_TC
00288 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00289 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00290 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00291 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00292 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00293 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00294 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00295 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00296 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00297 /**
00298   * @}
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 /* Exported macros -----------------------------------------------------------*/
00306
00307 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00308   * @{
00309   */
00310
00311 /** @brief Reset I2C handle state
00312   * @param  __HANDLE__: specifies the I2C Handle.
00313   * @retval None
00314   */
00315 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00316
00317 /** @brief  Enable the specified I2C interrupts.
00318   * @param  __HANDLE__: specifies the I2C Handle.
00319   * @param  __INTERRUPT__: specifies the interrupt source to enable.
00320   *        This parameter can be one of the following values:
00321   *            @arg I2C_IT_ERRI: Errors interrupt enable
00322   *            @arg I2C_IT_TCI: Transfer complete interrupt enable
00323   *            @arg I2C_IT_STOPI: STOP detection interrupt enable
00324   *            @arg I2C_IT_NACKI: NACK received interrupt enable
00325   *            @arg I2C_IT_ADDRI: Address match interrupt enable
00326   *            @arg I2C_IT_RXI: RX interrupt enable
00327   *            @arg I2C_IT_TXI: TX interrupt enable
00328   *
00329   * @retval None
00330   */
00331
00332 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00333
00334 /** @brief  Disable the specified I2C interrupts.
00335   * @param  __HANDLE__: specifies the I2C Handle.
00336   * @param  __INTERRUPT__: specifies the interrupt source to disable.
00337   *        This parameter can be one of the following values:
00338   *            @arg I2C_IT_ERRI: Errors interrupt enable
00339   *            @arg I2C_IT_TCI: Transfer complete interrupt enable
00340   *            @arg I2C_IT_STOPI: STOP detection interrupt enable
00341   *            @arg I2C_IT_NACKI: NACK received interrupt enable
00342   *            @arg I2C_IT_ADDRI: Address match interrupt enable
00343   *            @arg I2C_IT_RXI: RX interrupt enable
00344   *            @arg I2C_IT_TXI: TX interrupt enable
00345   *
00346   * @retval None
00347   */
00348 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00349
00350 /** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
00351   * @param  __HANDLE__: specifies the I2C Handle.
00352   * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
00353   *          This parameter can be one of the following values:
00354   *            @arg I2C_IT_ERRI: Errors interrupt enable
00355   *            @arg I2C_IT_TCI: Transfer complete interrupt enable
00356   *            @arg I2C_IT_STOPI: STOP detection interrupt enable
00357   *            @arg I2C_IT_NACKI: NACK received interrupt enable
00358   *            @arg I2C_IT_ADDRI: Address match interrupt enable
00359   *            @arg I2C_IT_RXI: RX interrupt enable
00360   *            @arg I2C_IT_TXI: TX interrupt enable
00361   *
00362   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00363   */
00364 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00365
00366 /** @brief  Checks whether the specified I2C flag is set or not.
00367   * @param  __HANDLE__: specifies the I2C Handle.
00368   * @param  __FLAG__: specifies the flag to check.
00369   *        This parameter can be one of the following values:
00370   *            @arg I2C_FLAG_TXE:      Transmit data register empty
00371   *            @arg I2C_FLAG_TXIS:     Transmit interrupt status
00372   *            @arg I2C_FLAG_RXNE:     Receive data register not empty
00373   *            @arg I2C_FLAG_ADDR:     Address matched (slave mode)
00374   *            @arg I2C_FLAG_AF:       Acknowledge failure received flag
00375   *            @arg I2C_FLAG_STOPF:    STOP detection flag
00376   *            @arg I2C_FLAG_TC:       Transfer complete (master mode)
00377   *            @arg I2C_FLAG_TCR:      Transfer complete reload
00378   *            @arg I2C_FLAG_BERR:     Bus error
00379   *            @arg I2C_FLAG_ARLO:     Arbitration lost
00380   *            @arg I2C_FLAG_OVR:      Overrun/Underrun
00381   *            @arg I2C_FLAG_PECERR:   PEC error in reception
00382   *            @arg I2C_FLAG_TIMEOUT:  Timeout or Tlow detection flag
00383   *            @arg I2C_FLAG_ALERT:    SMBus alert
00384   *            @arg I2C_FLAG_BUSY:     Bus busy
00385   *            @arg I2C_FLAG_DIR:      Transfer direction (slave mode)
00386   *
00387   * @retval The new state of __FLAG__ (TRUE or FALSE).
00388   */
00389 #define I2C_FLAG_MASK  ((uint32_t)0x0001FFFF)
00390 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
00391
00392 /** @brief  Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
00393   * @param  __HANDLE__: specifies the I2C Handle.
00394   * @param  __FLAG__: specifies the flag to clear.
00395   *          This parameter can be any combination of the following values:
00396   *            @arg I2C_FLAG_ADDR:    Address matched (slave mode)
00397   *            @arg I2C_FLAG_AF:      Acknowledge failure received flag
00398   *            @arg I2C_FLAG_STOPF:   STOP detection flag
00399   *            @arg I2C_FLAG_BERR:    Bus error
00400   *            @arg I2C_FLAG_ARLO:    Arbitration lost
00401   *            @arg I2C_FLAG_OVR:     Overrun/Underrun
00402   *            @arg I2C_FLAG_PECERR:  PEC error in reception
00403   *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
00404   *            @arg I2C_FLAG_ALERT:   SMBus alert
00405   *
00406   * @retval None
00407   */
00408 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))
00409
00410 /** @brief  Enable the specified I2C peripheral.
00411   * @param  __HANDLE__: specifies the I2C Handle.
00412   * @retval None
00413   */
00414 #define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
00415
00416 /** @brief  Disable the specified I2C peripheral.
00417   * @param  __HANDLE__: specifies the I2C Handle.
00418   * @retval None
00419   */
00420 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Include I2C HAL Extension module */
00427 #include "stm32f7xx_hal_i2c_ex.h"
00428
00429 /* Exported functions --------------------------------------------------------*/
00430 /** @addtogroup I2C_Exported_Functions
00431   * @{
00432   */
00433
00434 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00435   * @{
00436   */
00437 /* Initialization and de-initialization functions******************************/
00438 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00439 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
00440 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00441 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00442 /**
00443   * @}
00444   */
00445
00446 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00447   * @{
00448   */
00449 /* IO operation functions  ****************************************************/
00450  /******* Blocking mode: Polling */
00451 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00452 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00453 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00454 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00455 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00456 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00457 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00458
00459  /******* Non-Blocking mode: Interrupt */
00460 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00461 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00462 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00463 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00464 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00465 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00466
00467  /******* Non-Blocking mode: DMA */
00468 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00469 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00470 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00471 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00472 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00473 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00474 /**
00475   * @}
00476   */
00477
00478 /** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00479  * @{
00480  */
00481 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00482 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00483 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00484 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00485 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00486 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00487 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00488 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00489 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00490 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00491 /**
00492   * @}
00493   */
00494
00495 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
00496   * @{
00497   */
00498 /* Peripheral State and Errors functions  *************************************/
00499 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00500 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00501
00502 /**
00503   * @}
00504   */
00505
00506 /**
00507   * @}
00508   */
00509
00510 /* Private constants ---------------------------------------------------------*/
00511 /** @defgroup I2C_Private_Constants I2C Private Constants
00512   * @{
00513   */
00514
00515 /**
00516   * @}
00517   */
00518
00519 /* Private macros ------------------------------------------------------------*/
00520 /** @defgroup I2C_Private_Macro I2C Private Macros
00521   * @{
00522   */
00523
00524 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00525                                           ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00526
00527 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00528                                           ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00529
00530 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00531                                           ((MASK) == I2C_OA2_MASK01) || \
00532                                           ((MASK) == I2C_OA2_MASK02) || \
00533                                           ((MASK) == I2C_OA2_MASK03) || \
00534                                           ((MASK) == I2C_OA2_MASK04) || \
00535                                           ((MASK) == I2C_OA2_MASK05) || \
00536                                           ((MASK) == I2C_OA2_MASK06) || \
00537                                           ((MASK) == I2C_OA2_MASK07))
00538
00539 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00540                                           ((CALL) == I2C_GENERALCALL_ENABLE))
00541
00542 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00543                                           ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00544
00545 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00546                                           ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00547
00548
00549 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00550                                           ((MODE) == I2C_AUTOEND_MODE) || \
00551                                           ((MODE) == I2C_SOFTEND_MODE))
00552
00553 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)         || \
00554                                           ((REQUEST) == I2C_GENERATE_START_READ)  || \
00555                                           ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00556                                           ((REQUEST) == I2C_NO_STARTSTOP))
00557
00558
00559 #define I2C_RESET_CR2(__HANDLE__)       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00560
00561 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
00562 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
00563
00564 #define I2C_MEM_ADD_MSB(__ADDRESS__)    ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
00565 #define I2C_MEM_ADD_LSB(__ADDRESS__)    ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
00566
00567 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__)   (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00568                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00569 /**
00570   * @}
00571   */
00572
00573 /* Private Functions ---------------------------------------------------------*/
00574 /** @defgroup I2C_Private_Functions I2C Private Functions
00575   * @{
00576   */
00577 /* Private functions are defined in stm32f7xx_hal_i2c.c file */
00578 /**
00579   * @}
00580   */
00581
00582 /**
00583   * @}
00584   */
00585
00586 /**
00587   * @}
00588   */
00589
00590 #ifdef __cplusplus
00591 }
00592 #endif
00593
00594
00595 #endif /* __STM32F7xx_HAL_I2C_H */
00596
00597 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00598
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c_ex.c Source File

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stm32f7xx_hal_i2c_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   I2C Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of I2C Extended peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### I2C peripheral Extended features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the I2C interface for STM32L4XX
00018        devices contains the following additional features
00019
00020        (+) Possibility to disable or enable Analog Noise Filter
00021        (+) Use of a configured Digital Noise Filter
00022        (+) Disable or enable wakeup from Stop mode
00023
00024                      ##### How to use this driver #####
00025   ==============================================================================
00026   [..] This driver provides functions to:
00027     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00028     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00029   @endverbatim
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00034   *
00035   * Redistribution and use in source and binary forms, with or without modification,
00036   * are permitted provided that the following conditions are met:
00037   *   1. Redistributions of source code must retain the above copyright notice,
00038   *      this list of conditions and the following disclaimer.
00039   *   2. Redistributions in binary form must reproduce the above copyright notice,
00040   *      this list of conditions and the following disclaimer in the documentation
00041   *      and/or other materials provided with the distribution.
00042   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00043   *      may be used to endorse or promote products derived from this software
00044   *      without specific prior written permission.
00045   *
00046   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00047   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00048   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00049   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00050   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00051   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00052   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00053   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00054   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00055   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00056   *
00057   ******************************************************************************
00058   */
00059
00060 /* Includes ------------------------------------------------------------------*/
00061 #include "stm32f7xx_hal.h"
00062
00063 /** @addtogroup STM32F7xx_HAL_Driver
00064   * @{
00065   */
00066
00067 /** @defgroup I2CEx I2C Extended HAL module driver
00068   * @brief I2C Extended HAL module driver
00069   * @{
00070   */
00071
00072 #ifdef HAL_I2C_MODULE_ENABLED
00073
00074 /* Private typedef -----------------------------------------------------------*/
00075 /* Private define ------------------------------------------------------------*/
00076 /* Private macro -------------------------------------------------------------*/
00077 /* Private variables ---------------------------------------------------------*/
00078 /* Private function prototypes -----------------------------------------------*/
00079 /* Private functions ---------------------------------------------------------*/
00080
00081 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00082   * @{
00083   */
00084
00085 /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
00086   * @brief    Extended features functions
00087  *
00088 @verbatim
00089  ===============================================================================
00090                       ##### Extended features functions #####
00091  ===============================================================================
00092     [..] This section provides functions allowing to:
00093       (+) Configure Noise Filters
00094
00095 @endverbatim
00096   * @{
00097   */
00098
00099 /**
00100   * @brief  Configures I2C Analog noise filter.
00101   * @param  hi2c : pointer to a I2C_HandleTypeDef structure that contains
00102   *                the configuration information for the specified I2Cx peripheral.
00103   * @param  AnalogFilter : new state of the Analog filter.
00104   * @retval HAL status
00105   */
00106 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00107 {
00108   /* Check the parameters */
00109   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00110   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00111
00112   if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
00113      || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
00114   {
00115     return HAL_BUSY;
00116   }
00117
00118   /* Process Locked */
00119   __HAL_LOCK(hi2c);
00120
00121   hi2c->State = HAL_I2C_STATE_BUSY;
00122
00123   /* Disable the selected I2C peripheral */
00124   __HAL_I2C_DISABLE(hi2c);
00125
00126   /* Reset I2Cx ANOFF bit */
00127   hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00128
00129   /* Set analog filter bit*/
00130   hi2c->Instance->CR1 |= AnalogFilter;
00131
00132   __HAL_I2C_ENABLE(hi2c);
00133
00134   hi2c->State = HAL_I2C_STATE_READY;
00135
00136   /* Process Unlocked */
00137   __HAL_UNLOCK(hi2c);
00138
00139   return HAL_OK;
00140 }
00141
00142 /**
00143   * @brief  Configures I2C Digital noise filter.
00144   * @param  hi2c : pointer to a I2C_HandleTypeDef structure that contains
00145   *                the configuration information for the specified I2Cx peripheral.
00146   * @param  DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
00147   * @retval HAL status
00148   */
00149 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00150 {
00151   uint32_t tmpreg = 0;
00152
00153   /* Check the parameters */
00154   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00155   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00156
00157   if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
00158      || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
00159   {
00160     return HAL_BUSY;
00161   }
00162
00163   /* Process Locked */
00164   __HAL_LOCK(hi2c);
00165
00166   hi2c->State = HAL_I2C_STATE_BUSY;
00167
00168   /* Disable the selected I2C peripheral */
00169   __HAL_I2C_DISABLE(hi2c);
00170
00171   /* Get the old register value */
00172   tmpreg = hi2c->Instance->CR1;
00173
00174   /* Reset I2Cx DNF bits [11:8] */
00175   tmpreg &= ~(I2C_CR1_DNF);
00176
00177   /* Set I2Cx DNF coefficient */
00178   tmpreg |= DigitalFilter << 8;
00179
00180   /* Store the new register value */
00181   hi2c->Instance->CR1 = tmpreg;
00182
00183   __HAL_I2C_ENABLE(hi2c);
00184
00185   hi2c->State = HAL_I2C_STATE_READY;
00186
00187   /* Process Unlocked */
00188   __HAL_UNLOCK(hi2c);
00189
00190   return HAL_OK;
00191 }
00192
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 #endif /* HAL_I2C_MODULE_ENABLED */
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2c_ex.h Source File

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  • STM32F7xx_HAL_Driver
  • Inc
stm32f7xx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of I2C HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_I2C_EX_H
00040 #define __STM32F7xx_HAL_I2C_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2CEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
00065   * @{
00066   */
00067 #define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000)
00068 #define I2C_ANALOGFILTER_DISABLE       I2C_CR1_ANFOFF
00069 /**
00070   * @}
00071   */
00072
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported macro ------------------------------------------------------------*/
00079 /* Exported functions --------------------------------------------------------*/
00080
00081 /* Peripheral Control methods  ************************************************/
00082 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00083 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00084 /* Private constants ---------------------------------------------------------*/
00085 /** @defgroup I2C_Private_Constants I2C Private Constants
00086   * @{
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Private macros ------------------------------------------------------------*/
00094 /** @defgroup I2C_Private_Macro I2C Private Macros
00095   * @{
00096   */
00097 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00098                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00099
00100 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
00101 /**
00102   * @}
00103   */
00104
00105 /* Private Functions ---------------------------------------------------------*/
00106 /** @defgroup I2C_Private_Functions I2C Private Functions
00107   * @{
00108   */
00109 /* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
00110 /**
00111   * @}
00112   */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 #ifdef __cplusplus
00123 }
00124 #endif
00125
00126 #endif /* __STM32F7xx_HAL_I2C_EX_H */
00127
00128
00129 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2s.c Source File

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  • STM32F7xx_HAL_Driver
  • Src
stm32f7xx_hal_i2s.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   I2S HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The I2S HAL driver can be used as follows:
00019
00020     (#) Declare a I2S_HandleTypeDef handle structure.
00021     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00022         (##) Enable the SPIx interface clock.
00023         (##) I2S pins configuration:
00024             (+++) Enable the clock for the I2S GPIOs.
00025             (+++) Configure these I2S pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00027              and HAL_I2S_Receive_IT() APIs).
00028             (+++) Configure the I2Sx interrupt priority.
00029             (+++) Enable the NVIC I2S IRQ handle.
00030         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00031              and HAL_I2S_Receive_DMA() APIs:
00032             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00033             (+++) Enable the DMAx interface clock.
00034             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00035             (+++) Configure the DMA Tx/Rx Channel.
00036             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00037             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00038                 DMA Tx/Rx Channel.
00039
00040    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00041        using HAL_I2S_Init() function.
00042
00043    -@- The specific I2S interrupts (Transmission complete interrupt,
00044        RXNE interrupt and Error Interrupts) will be managed using the macros
00045        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00046    -@- Make sure that either:
00047        (+@) I2S clock is configured based on SYSCLK or
00048        (+@) External clock source is configured after setting correctly
00049             the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
00050
00051    (#) Three mode of operations are available within this driver :
00052
00053    *** Polling mode IO operation ***
00054    =================================
00055    [..]
00056      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00057      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00058
00059    *** Interrupt mode IO operation ***
00060    ===================================
00061    [..]
00062      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00063      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00064          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00065      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00066          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00067      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00068      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00069          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00070      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00071          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00072      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00073          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00074
00075    *** DMA mode IO operation ***
00076    ==============================
00077    [..]
00078      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00079      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00080          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00081      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00082          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00083      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00084      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00085          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00086      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00087          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00088      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00089          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00090      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00091      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00092      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00093
00094    *** I2S HAL driver macros list ***
00095    =============================================
00096    [..]
00097      Below the list of most used macros in I2S HAL driver.
00098
00099       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00100       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00101       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00102       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00103       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00104
00105     [..]
00106       (@) You can refer to the I2S HAL driver header file for more useful macros
00107
00108   @endverbatim
00109   ******************************************************************************
00110   * @attention
00111   *
00112   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00113   *
00114   * Redistribution and use in source and binary forms, with or without modification,
00115   * are permitted provided that the following conditions are met:
00116   *   1. Redistributions of source code must retain the above copyright notice,
00117   *      this list of conditions and the following disclaimer.
00118   *   2. Redistributions in binary form must reproduce the above copyright notice,
00119   *      this list of conditions and the following disclaimer in the documentation
00120   *      and/or other materials provided with the distribution.
00121   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00122   *      may be used to endorse or promote products derived from this software
00123   *      without specific prior written permission.
00124   *
00125   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00126   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00127   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00128   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00129   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00130   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00131   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00132   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00133   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00134   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00135   *
00136   ******************************************************************************
00137   */
00138
00139 /* Includes ------------------------------------------------------------------*/
00140 #include "stm32f7xx_hal.h"
00141
00142 /** @addtogroup STM32F7xx_HAL_Driver
00143   * @{
00144   */
00145
00146 /** @defgroup I2S I2S
00147   * @brief I2S HAL module driver
00148   * @{
00149   */
00150
00151 #ifdef HAL_I2S_MODULE_ENABLED
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /* Private macro -------------------------------------------------------------*/
00156 /* Private variables ---------------------------------------------------------*/
00157 /* Private function prototypes -----------------------------------------------*/
00158 /** @defgroup I2S_Private_Functions I2S Private Functions
00159   * @{
00160   */
00161 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00162 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00163 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00164 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00165 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
00166 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
00167 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
00168 static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);
00169 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
00170 /**
00171   * @}
00172   */
00173
00174 /* Exported functions ---------------------------------------------------------*/
00175
00176 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00177   * @{
00178   */
00179
00180 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00181   *  @brief    Initialization and Configuration functions
00182   *
00183 @verbatim
00184  ===============================================================================
00185               ##### Initialization and de-initialization functions #####
00186  ===============================================================================
00187     [..]  This subsection provides a set of functions allowing to initialize and
00188           de-initialize the I2Sx peripheral in simplex mode:
00189
00190       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00191           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00192
00193       (+) Call the function HAL_I2S_Init() to configure the selected device with
00194           the selected configuration:
00195         (++) Mode
00196         (++) Standard
00197         (++) Data Format
00198         (++) MCLK Output
00199         (++) Audio frequency
00200         (++) Polarity
00201         (++) Full duplex mode
00202
00203       (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00204           of the selected I2Sx peripheral.
00205 @endverbatim
00206   * @{
00207   */
00208
00209 /**
00210   * @brief Initializes the I2S according to the specified parameters
00211   *         in the I2S_InitTypeDef and create the associated handle.
00212   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00213   *         the configuration information for I2S module
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00217 {
00218   uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
00219   uint32_t tmp = 0, i2sclk = 0;
00220
00221   /* Check the I2S handle allocation */
00222   if(hi2s == NULL)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   /* Check the parameters */
00228   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00229   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00230   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00231   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00232   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00233   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00234   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00235   assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
00236
00237   if(hi2s->State == HAL_I2S_STATE_RESET)
00238   {
00239     /* Allocate lock resource and initialize it */
00240     hi2s->Lock = HAL_UNLOCKED;
00241     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00242     HAL_I2S_MspInit(hi2s);
00243   }
00244
00245   hi2s->State = HAL_I2S_STATE_BUSY;
00246
00247   /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
00248   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00249   hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00250                                SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00251                                SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
00252   hi2s->Instance->I2SPR = 0x0002;
00253
00254   /* Get the I2SCFGR register value */
00255   tmpreg = hi2s->Instance->I2SCFGR;
00256
00257   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
00258   if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
00259   {
00260     i2sodd = (uint16_t)0;
00261     i2sdiv = (uint16_t)2;
00262   }
00263   /* If the requested audio frequency is not the default, compute the prescaler */
00264   else
00265   {
00266     /* Check the frame length (For the Prescaler computing) *******************/
00267     if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
00268     {
00269       /* Packet length is 16 bits */
00270       packetlength = 1;
00271     }
00272     else
00273     {
00274       /* Packet length is 32 bits */
00275       packetlength = 2;
00276     }
00277
00278     /* Get I2S source Clock frequency  ****************************************/
00279
00280     /* If an external I2S clock has to be used, the specific define should be set
00281     in the project configuration or in the stm32f3xx_conf.h file */
00282     if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
00283     {
00284       /* Set the I2S clock to the external clock  value */
00285       i2sclk = EXTERNAL_CLOCK_VALUE;
00286     }
00287     else
00288     {
00289       /* Get the I2S source clock value */
00290                         i2sclk = I2S_GetClockFreq(hi2s);
00291     }
00292
00293     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00294     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00295     {
00296       /* MCLK output is enabled */
00297       tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
00298     }
00299     else
00300     {
00301       /* MCLK output is disabled */
00302       tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
00303     }
00304
00305     /* Remove the flatting point */
00306     tmp = tmp / 10;
00307
00308     /* Check the parity of the divider */
00309     i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
00310
00311     /* Compute the i2sdiv prescaler */
00312     i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
00313
00314     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00315     i2sodd = (uint16_t) (i2sodd << 8);
00316   }
00317
00318   /* Test if the divider is 1 or 0 or greater than 0xFF */
00319   if((i2sdiv < 2) || (i2sdiv > 0xFF))
00320   {
00321     /* Set the default values */
00322     i2sdiv = 2;
00323     i2sodd = 0;
00324   }
00325
00326   /* Write to SPIx I2SPR register the computed value */
00327   hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
00328
00329   /* Configure the I2S with the I2S_InitStruct values */
00330   tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
00331                        (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
00332                        (uint16_t)hi2s->Init.CPOL))));
00333
00334   /* Write to SPIx I2SCFGR */
00335   hi2s->Instance->I2SCFGR = tmpreg;
00336
00337   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00338   hi2s->State= HAL_I2S_STATE_READY;
00339
00340   return HAL_OK;
00341 }
00342
00343 /**
00344   * @brief DeInitializes the I2S peripheral
00345   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00346   *         the configuration information for I2S module
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00350 {
00351   /* Check the I2S handle allocation */
00352   if(hi2s == NULL)
00353   {
00354     return HAL_ERROR;
00355   }
00356
00357   /* Check the parameters */
00358   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00359
00360   hi2s->State = HAL_I2S_STATE_BUSY;
00361
00362   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00363   HAL_I2S_MspDeInit(hi2s);
00364
00365   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00366   hi2s->State = HAL_I2S_STATE_RESET;
00367
00368   /* Release Lock */
00369   __HAL_UNLOCK(hi2s);
00370
00371   return HAL_OK;
00372 }
00373
00374 /**
00375   * @brief I2S MSP Init
00376   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00377   *         the configuration information for I2S module
00378   * @retval None
00379   */
00380  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00381 {
00382   /* Prevent unused argument(s) compilation warning */
00383   UNUSED(hi2s);
00384
00385   /* NOTE : This function Should not be modified, when the callback is needed,
00386             the HAL_I2S_MspInit could be implemented in the user file
00387    */
00388 }
00389
00390 /**
00391   * @brief I2S MSP DeInit
00392   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00393   *         the configuration information for I2S module
00394   * @retval None
00395   */
00396  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00397 {
00398   /* Prevent unused argument(s) compilation warning */
00399   UNUSED(hi2s);
00400
00401   /* NOTE : This function Should not be modified, when the callback is needed,
00402             the HAL_I2S_MspDeInit could be implemented in the user file
00403    */
00404 }
00405
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions
00411   *  @brief Data transfers functions
00412   *
00413 @verbatim
00414  ===============================================================================
00415                       ##### IO operation functions #####
00416  ===============================================================================
00417     [..]
00418     This subsection provides a set of functions allowing to manage the I2S data
00419     transfers.
00420
00421     (#) There are two modes of transfer:
00422        (++) Blocking mode : The communication is performed in the polling mode.
00423             The status of all data processing is returned by the same function
00424             after finishing transfer.
00425        (++) No-Blocking mode : The communication is performed using Interrupts
00426             or DMA. These functions return the status of the transfer startup.
00427             The end of the data processing will be indicated through the
00428             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00429             using DMA mode.
00430
00431     (#) Blocking mode functions are :
00432         (++) HAL_I2S_Transmit()
00433         (++) HAL_I2S_Receive()
00434
00435     (#) No-Blocking mode functions with Interrupt are :
00436         (++) HAL_I2S_Transmit_IT()
00437         (++) HAL_I2S_Receive_IT()
00438
00439     (#) No-Blocking mode functions with DMA are :
00440         (++) HAL_I2S_Transmit_DMA()
00441         (++) HAL_I2S_Receive_DMA()
00442
00443     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00444         (++) HAL_I2S_TxCpltCallback()
00445         (++) HAL_I2S_RxCpltCallback()
00446         (++) HAL_I2S_ErrorCallback()
00447
00448 @endverbatim
00449   * @{
00450   */
00451
00452 /**
00453   * @brief Transmit an amount of data in blocking mode
00454   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00455   *         the configuration information for I2S module
00456   * @param pData: a 16-bit pointer to data buffer.
00457   * @param Size: number of data sample to be sent:
00458   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00459   *       configuration phase, the Size parameter means the number of 16-bit data length
00460   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00461   *       the Size parameter means the number of 16-bit data length.
00462   * @param  Timeout: Timeout duration
00463   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00464   *       between Master and Slave(example: audio streaming).
00465   * @retval HAL status
00466   */
00467 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00468 {
00469   if((pData == NULL ) || (Size == 0))
00470   {
00471     return  HAL_ERROR;
00472   }
00473
00474   if(hi2s->State == HAL_I2S_STATE_READY)
00475   {
00476     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00477        ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00478     {
00479       hi2s->TxXferSize = (Size << 1);
00480       hi2s->TxXferCount = (Size << 1);
00481     }
00482     else
00483     {
00484       hi2s->TxXferSize = Size;
00485       hi2s->TxXferCount = Size;
00486     }
00487
00488     /* Process Locked */
00489     __HAL_LOCK(hi2s);
00490
00491     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00492     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00493
00494     /* Check if the I2S is already enabled */
00495     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00496     {
00497       /* Enable I2S peripheral */
00498       __HAL_I2S_ENABLE(hi2s);
00499     }
00500
00501     while(hi2s->TxXferCount > 0)
00502     {
00503       hi2s->Instance->DR = (*pData++);
00504       hi2s->TxXferCount--;
00505       /* Wait until TXE flag is set */
00506       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
00507       {
00508         /* Set the error code and execute error callback*/
00509         hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00510         HAL_I2S_ErrorCallback(hi2s);
00511         return HAL_TIMEOUT;
00512       }
00513
00514       /* Check if an underrun occurs */
00515       if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00516       {
00517         /* Set the I2S State ready */
00518         hi2s->State = HAL_I2S_STATE_READY;
00519
00520         /* Process Unlocked */
00521         __HAL_UNLOCK(hi2s);
00522
00523         /* Set the error code and execute error callback*/
00524         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00525         HAL_I2S_ErrorCallback(hi2s);
00526
00527         return HAL_ERROR;
00528       }
00529     }
00530
00531     /* Check if Slave mode is selected */
00532     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
00533     {
00534       /* Wait until Busy flag is reset */
00535       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
00536       {
00537         /* Set the error code and execute error callback*/
00538         hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00539         HAL_I2S_ErrorCallback(hi2s);
00540         return HAL_TIMEOUT;
00541       }
00542     }
00543
00544     hi2s->State = HAL_I2S_STATE_READY;
00545
00546     /* Process Unlocked */
00547     __HAL_UNLOCK(hi2s);
00548
00549     return HAL_OK;
00550   }
00551   else
00552   {
00553     return HAL_BUSY;
00554   }
00555 }
00556
00557 /**
00558   * @brief Receive an amount of data in blocking mode
00559   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00560   *         the configuration information for I2S module
00561   * @param pData: a 16-bit pointer to data buffer.
00562   * @param Size: number of data sample to be sent:
00563   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00564   *       configuration phase, the Size parameter means the number of 16-bit data length
00565   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00566   *       the Size parameter means the number of 16-bit data length.
00567   * @param Timeout: Timeout duration
00568   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00569   *       between Master and Slave(example: audio streaming).
00570   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00571   *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.
00572   * @retval HAL status
00573   */
00574 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00575 {
00576   if((pData == NULL ) || (Size == 0))
00577   {
00578     return  HAL_ERROR;
00579   }
00580
00581   if(hi2s->State == HAL_I2S_STATE_READY)
00582   {
00583     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00584        ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00585     {
00586       hi2s->RxXferSize = (Size << 1);
00587       hi2s->RxXferCount = (Size << 1);
00588     }
00589     else
00590     {
00591       hi2s->RxXferSize = Size;
00592       hi2s->RxXferCount = Size;
00593     }
00594     /* Process Locked */
00595     __HAL_LOCK(hi2s);
00596
00597     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00598     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00599
00600     /* Check if the I2S is already enabled */
00601     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00602     {
00603       /* Enable I2S peripheral */
00604       __HAL_I2S_ENABLE(hi2s);
00605     }
00606
00607     /* Check if Master Receiver mode is selected */
00608     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00609     {
00610       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00611       access to the SPI_SR register. */
00612       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00613     }
00614
00615     /* Receive data */
00616     while(hi2s->RxXferCount > 0)
00617     {
00618       /* Wait until RXNE flag is set */
00619       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
00620       {
00621         /* Set the error code and execute error callback*/
00622         hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
00623         HAL_I2S_ErrorCallback(hi2s);
00624         return HAL_TIMEOUT;
00625       }
00626
00627       /* Check if an overrun occurs */
00628       if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00629       {
00630         /* Set the I2S State ready */
00631         hi2s->State = HAL_I2S_STATE_READY;
00632
00633         /* Process Unlocked */
00634         __HAL_UNLOCK(hi2s);
00635
00636         /* Set the error code and execute error callback*/
00637         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00638         HAL_I2S_ErrorCallback(hi2s);
00639
00640         return HAL_ERROR;
00641       }
00642
00643       (*pData++) = hi2s->Instance->DR;
00644       hi2s->RxXferCount--;
00645     }
00646
00647     hi2s->State = HAL_I2S_STATE_READY;
00648
00649     /* Process Unlocked */
00650     __HAL_UNLOCK(hi2s);
00651
00652     return HAL_OK;
00653   }
00654   else
00655   {
00656     return HAL_BUSY;
00657   }
00658 }
00659
00660 /**
00661   * @brief Transmit an amount of data in non-blocking mode with Interrupt
00662   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00663   *         the configuration information for I2S module
00664   * @param pData: a 16-bit pointer to data buffer.
00665   * @param Size: number of data sample to be sent:
00666   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00667   *       configuration phase, the Size parameter means the number of 16-bit data length
00668   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00669   *       the Size parameter means the number of 16-bit data length.
00670   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00671   *       between Master and Slave(example: audio streaming).
00672   * @retval HAL status
00673   */
00674 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00675 {
00676   if(hi2s->State == HAL_I2S_STATE_READY)
00677   {
00678     if((pData == NULL) || (Size == 0))
00679     {
00680       return  HAL_ERROR;
00681     }
00682
00683     hi2s->pTxBuffPtr = pData;
00684     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00685       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00686     {
00687       hi2s->TxXferSize = (Size << 1);
00688       hi2s->TxXferCount = (Size << 1);
00689     }
00690     else
00691     {
00692       hi2s->TxXferSize = Size;
00693       hi2s->TxXferCount = Size;
00694     }
00695
00696     /* Process Locked */
00697     __HAL_LOCK(hi2s);
00698
00699     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00700     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00701
00702     /* Enable TXE and ERR interrupt */
00703     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00704
00705     /* Check if the I2S is already enabled */
00706     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00707     {
00708       /* Enable I2S peripheral */
00709       __HAL_I2S_ENABLE(hi2s);
00710     }
00711
00712     /* Process Unlocked */
00713     __HAL_UNLOCK(hi2s);
00714
00715     return HAL_OK;
00716   }
00717   else
00718   {
00719     return HAL_BUSY;
00720   }
00721 }
00722
00723 /**
00724   * @brief Receive an amount of data in non-blocking mode with Interrupt
00725   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00726   *         the configuration information for I2S module
00727   * @param pData: a 16-bit pointer to the Receive data buffer.
00728   * @param Size: number of data sample to be sent:
00729   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00730   *       configuration phase, the Size parameter means the number of 16-bit data length
00731   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00732   *       the Size parameter means the number of 16-bit data length.
00733   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00734   *       between Master and Slave(example: audio streaming).
00735   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
00736   * between Master and Slave otherwise the I2S interrupt should be optimized.
00737   * @retval HAL status
00738   */
00739 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00740 {
00741   if(hi2s->State == HAL_I2S_STATE_READY)
00742   {
00743     if((pData == NULL) || (Size == 0))
00744     {
00745       return  HAL_ERROR;
00746     }
00747
00748     hi2s->pRxBuffPtr = pData;
00749     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00750       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00751     {
00752       hi2s->RxXferSize = (Size << 1);
00753       hi2s->RxXferCount = (Size << 1);
00754     }
00755     else
00756     {
00757       hi2s->RxXferSize = Size;
00758       hi2s->RxXferCount = Size;
00759     }
00760     /* Process Locked */
00761     __HAL_LOCK(hi2s);
00762
00763     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00764     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00765
00766     /* Enable TXE and ERR interrupt */
00767     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00768
00769     /* Check if the I2S is already enabled */
00770     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00771     {
00772       /* Enable I2S peripheral */
00773       __HAL_I2S_ENABLE(hi2s);
00774     }
00775
00776     /* Process Unlocked */
00777     __HAL_UNLOCK(hi2s);
00778
00779     return HAL_OK;
00780   }
00781   else
00782   {
00783     return HAL_BUSY;
00784   }
00785 }
00786
00787 /**
00788   * @brief Transmit an amount of data in non-blocking mode with DMA
00789   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00790   *         the configuration information for I2S module
00791   * @param pData: a 16-bit pointer to the Transmit data buffer.
00792   * @param Size: number of data sample to be sent:
00793   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00794   *       configuration phase, the Size parameter means the number of 16-bit data length
00795   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00796   *       the Size parameter means the number of 16-bit data length.
00797   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00798   *       between Master and Slave(example: audio streaming).
00799   * @retval HAL status
00800   */
00801 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00802 {
00803   uint32_t *tmp;
00804
00805   if((pData == NULL) || (Size == 0))
00806   {
00807     return  HAL_ERROR;
00808   }
00809
00810   if(hi2s->State == HAL_I2S_STATE_READY)
00811   {
00812     hi2s->pTxBuffPtr = pData;
00813     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00814       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00815     {
00816       hi2s->TxXferSize = (Size << 1);
00817       hi2s->TxXferCount = (Size << 1);
00818     }
00819     else
00820     {
00821       hi2s->TxXferSize = Size;
00822       hi2s->TxXferCount = Size;
00823     }
00824
00825     /* Process Locked */
00826     __HAL_LOCK(hi2s);
00827
00828     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00829     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00830
00831     /* Set the I2S Tx DMA Half transfer complete callback */
00832     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
00833
00834     /* Set the I2S TxDMA transfer complete callback */
00835     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
00836
00837     /* Set the DMA error callback */
00838     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
00839
00840     /* Enable the Tx DMA Channel */
00841     tmp = (uint32_t*)&pData;
00842     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
00843
00844     /* Check if the I2S is already enabled */
00845     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00846     {
00847       /* Enable I2S peripheral */
00848       __HAL_I2S_ENABLE(hi2s);
00849     }
00850
00851     /* Enable Tx DMA Request */
00852     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00853
00854     /* Process Unlocked */
00855     __HAL_UNLOCK(hi2s);
00856
00857     return HAL_OK;
00858   }
00859   else
00860   {
00861     return HAL_BUSY;
00862   }
00863 }
00864
00865 /**
00866   * @brief Receive an amount of data in non-blocking mode with DMA
00867   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00868   *         the configuration information for I2S module
00869   * @param pData: a 16-bit pointer to the Receive data buffer.
00870   * @param Size: number of data sample to be sent:
00871   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00872   *       configuration phase, the Size parameter means the number of 16-bit data length
00873   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00874   *       the Size parameter means the number of 16-bit data length.
00875   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00876   *       between Master and Slave(example: audio streaming).
00877   * @retval HAL status
00878   */
00879 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00880 {
00881   uint32_t *tmp;
00882
00883   if((pData == NULL) || (Size == 0))
00884   {
00885     return  HAL_ERROR;
00886   }
00887
00888   if(hi2s->State == HAL_I2S_STATE_READY)
00889   {
00890     hi2s->pRxBuffPtr = pData;
00891     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
00892       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
00893     {
00894       hi2s->RxXferSize = (Size << 1);
00895       hi2s->RxXferCount = (Size << 1);
00896     }
00897     else
00898     {
00899       hi2s->RxXferSize = Size;
00900       hi2s->RxXferCount = Size;
00901     }
00902     /* Process Locked */
00903     __HAL_LOCK(hi2s);
00904
00905     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00906     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00907
00908     /* Set the I2S Rx DMA Half transfer complete callback */
00909     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
00910
00911     /* Set the I2S Rx DMA transfer complete callback */
00912     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
00913
00914     /* Set the DMA error callback */
00915     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
00916
00917     /* Check if Master Receiver mode is selected */
00918     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00919     {
00920       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
00921       access to the SPI_SR register. */
00922       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00923     }
00924
00925     /* Enable the Rx DMA Channel */
00926     tmp = (uint32_t*)&pData;
00927     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
00928
00929     /* Check if the I2S is already enabled */
00930     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00931     {
00932       /* Enable I2S peripheral */
00933       __HAL_I2S_ENABLE(hi2s);
00934     }
00935
00936     /* Enable Rx DMA Request */
00937     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00938
00939     /* Process Unlocked */
00940     __HAL_UNLOCK(hi2s);
00941
00942     return HAL_OK;
00943   }
00944   else
00945   {
00946     return HAL_BUSY;
00947   }
00948 }
00949
00950 /**
00951   * @brief Pauses the audio stream playing from the Media.
00952   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00953   *         the configuration information for I2S module
00954   * @retval HAL status
00955   */
00956 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
00957 {
00958   /* Process Locked */
00959   __HAL_LOCK(hi2s);
00960
00961   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00962   {
00963     /* Disable the I2S DMA Tx request */
00964     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00965   }
00966   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00967   {
00968     /* Disable the I2S DMA Rx request */
00969     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00970   }
00971   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00972   {
00973     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
00974     {
00975       /* Disable the I2S DMA Tx request */
00976       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00977     }
00978     else
00979     {
00980       /* Disable the I2S DMA Rx request */
00981       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00982     }
00983   }
00984
00985   /* Process Unlocked */
00986   __HAL_UNLOCK(hi2s);
00987
00988   return HAL_OK;
00989 }
00990
00991 /**
00992   * @brief Resumes the audio stream playing from the Media.
00993   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00994   *         the configuration information for I2S module
00995   * @retval HAL status
00996   */
00997 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
00998 {
00999   /* Process Locked */
01000   __HAL_LOCK(hi2s);
01001
01002   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01003   {
01004     /* Enable the I2S DMA Tx request */
01005     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01006   }
01007   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01008   {
01009     /* Enable the I2S DMA Rx request */
01010     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01011   }
01012
01013   /* If the I2S peripheral is still not enabled, enable it */
01014   if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01015   {
01016     /* Enable I2S peripheral */
01017     __HAL_I2S_ENABLE(hi2s);
01018   }
01019
01020   /* Process Unlocked */
01021   __HAL_UNLOCK(hi2s);
01022
01023   return HAL_OK;
01024 }
01025
01026 /**
01027   * @brief Stops the audio stream playing from the Media.
01028   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01029   *         the configuration information for I2S module
01030   * @retval HAL status
01031   */
01032 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
01033 {
01034   /* Process Locked */
01035   __HAL_LOCK(hi2s);
01036
01037   /* Disable the I2S Tx/Rx DMA requests */
01038   CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01039   CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01040
01041   /* Abort the I2S DMA Channel tx */
01042   if(hi2s->hdmatx != NULL)
01043   {
01044     /* Disable the I2S DMA channel */
01045     __HAL_DMA_DISABLE(hi2s->hdmatx);
01046     HAL_DMA_Abort(hi2s->hdmatx);
01047   }
01048   /* Abort the I2S DMA Channel rx */
01049   if(hi2s->hdmarx != NULL)
01050   {
01051     /* Disable the I2S DMA channel */
01052     __HAL_DMA_DISABLE(hi2s->hdmarx);
01053     HAL_DMA_Abort(hi2s->hdmarx);
01054   }
01055
01056   /* Disable I2S peripheral */
01057   __HAL_I2S_DISABLE(hi2s);
01058
01059   hi2s->State = HAL_I2S_STATE_READY;
01060
01061   /* Process Unlocked */
01062   __HAL_UNLOCK(hi2s);
01063
01064   return HAL_OK;
01065 }
01066
01067 /**
01068   * @brief  This function handles I2S interrupt request.
01069   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01070   *         the configuration information for I2S module
01071   * @retval HAL status
01072   */
01073 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01074 {
01075   __IO uint32_t i2ssr = hi2s->Instance->SR;
01076
01077   if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01078   {
01079     /* I2S in mode Receiver ----------------------------------------------------*/
01080     if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
01081     {
01082       I2S_Receive_IT(hi2s);
01083     }
01084
01085     /* I2S Overrun error interrupt occurred -------------------------------------*/
01086     if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
01087     {
01088       /* Disable RXNE and ERR interrupt */
01089       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01090
01091       /* Set the I2S State ready */
01092       hi2s->State = HAL_I2S_STATE_READY;
01093
01094       /* Set the error code and execute error callback*/
01095       hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
01096       HAL_I2S_ErrorCallback(hi2s);
01097     }
01098   }
01099   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01100   {
01101     /* I2S in mode Transmitter ---------------------------------------------------*/
01102     if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
01103     {
01104       I2S_Transmit_IT(hi2s);
01105     }
01106
01107     /* I2S Underrun error interrupt occurred ------------------------------------*/
01108     if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
01109     {
01110       /* Disable TXE and ERR interrupt */
01111       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01112
01113       /* Set the I2S State ready */
01114       hi2s->State = HAL_I2S_STATE_READY;
01115
01116       /* Set the error code and execute error callback*/
01117       hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
01118       HAL_I2S_ErrorCallback(hi2s);
01119     }
01120   }
01121 }
01122
01123 /**
01124   * @}
01125   */
01126
01127 /**
01128   * @}
01129   */
01130
01131 /** @addtogroup I2S_Private_Functions I2S Private Functions
01132   * @{
01133   */
01134 /**
01135   * @brief This function handles I2S Communication Timeout.
01136   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01137   *         the configuration information for I2S module
01138   * @param Flag: Flag checked
01139   * @param State: Value of the flag expected
01140   * @param Timeout: Duration of the timeout
01141   * @retval HAL status
01142   */
01143 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
01144                                                        uint32_t State, uint32_t Timeout)
01145 {
01146   uint32_t tickstart = 0;
01147
01148   /* Get tick */
01149   tickstart = HAL_GetTick();
01150
01151   /* Wait until flag is set */
01152   if(State == RESET)
01153   {
01154     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
01155     {
01156       if(Timeout != HAL_MAX_DELAY)
01157       {
01158         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01159         {
01160           /* Set the I2S State ready */
01161           hi2s->State= HAL_I2S_STATE_READY;
01162
01163           /* Process Unlocked */
01164           __HAL_UNLOCK(hi2s);
01165
01166           return HAL_TIMEOUT;
01167         }
01168       }
01169     }
01170   }
01171   else
01172   {
01173     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
01174     {
01175       if(Timeout != HAL_MAX_DELAY)
01176       {
01177         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01178         {
01179           /* Set the I2S State ready */
01180           hi2s->State= HAL_I2S_STATE_READY;
01181
01182           /* Process Unlocked */
01183           __HAL_UNLOCK(hi2s);
01184
01185           return HAL_TIMEOUT;
01186         }
01187       }
01188     }
01189   }
01190   return HAL_OK;
01191 }
01192 /**
01193   * @}
01194   */
01195
01196 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
01197   * @{
01198   */
01199
01200 /** @addtogroup  I2S_Exported_Functions_Group2 Input and Output operation functions
01201   * @{
01202   */
01203 /**
01204   * @brief Tx Transfer Half completed callbacks
01205   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01206   *         the configuration information for I2S module
01207   * @retval None
01208   */
01209  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01210 {
01211   /* Prevent unused argument(s) compilation warning */
01212   UNUSED(hi2s);
01213
01214   /* NOTE : This function Should not be modified, when the callback is needed,
01215             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01216    */
01217 }
01218
01219 /**
01220   * @brief Tx Transfer completed callbacks
01221   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01222   *         the configuration information for I2S module
01223   * @retval None
01224   */
01225  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01226 {
01227   /* Prevent unused argument(s) compilation warning */
01228   UNUSED(hi2s);
01229
01230   /* NOTE : This function Should not be modified, when the callback is needed,
01231             the HAL_I2S_TxCpltCallback could be implemented in the user file
01232    */
01233 }
01234
01235 /**
01236   * @brief Rx Transfer half completed callbacks
01237   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01238   *         the configuration information for I2S module
01239   * @retval None
01240   */
01241 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01242 {
01243   /* Prevent unused argument(s) compilation warning */
01244   UNUSED(hi2s);
01245
01246   /* NOTE : This function Should not be modified, when the callback is needed,
01247             the HAL_I2S_RxCpltCallback could be implemented in the user file
01248    */
01249 }
01250
01251 /**
01252   * @brief Rx Transfer completed callbacks
01253   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01254   *         the configuration information for I2S module
01255   * @retval None
01256   */
01257 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01258 {
01259   /* Prevent unused argument(s) compilation warning */
01260   UNUSED(hi2s);
01261
01262   /* NOTE : This function Should not be modified, when the callback is needed,
01263             the HAL_I2S_RxCpltCallback could be implemented in the user file
01264    */
01265 }
01266
01267 /**
01268   * @brief I2S error callbacks
01269   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01270   *         the configuration information for I2S module
01271   * @retval None
01272   */
01273  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01274 {
01275   /* Prevent unused argument(s) compilation warning */
01276   UNUSED(hi2s);
01277
01278   /* NOTE : This function Should not be modified, when the callback is needed,
01279             the HAL_I2S_ErrorCallback could be implemented in the user file
01280    */
01281 }
01282
01283 /**
01284   * @}
01285   */
01286
01287 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01288   *  @brief   Peripheral State functions
01289   *
01290 @verbatim
01291  ===============================================================================
01292                       ##### Peripheral State and Errors functions #####
01293  ===============================================================================
01294     [..]
01295     This subsection permits to get in run-time the status of the peripheral
01296     and the data flow.
01297
01298 @endverbatim
01299   * @{
01300   */
01301
01302 /**
01303   * @brief  Return the I2S state
01304   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01305   *         the configuration information for I2S module
01306   * @retval HAL state
01307   */
01308 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01309 {
01310   return hi2s->State;
01311 }
01312
01313 /**
01314   * @brief  Return the I2S error code
01315   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01316   *         the configuration information for I2S module
01317   * @retval I2S Error Code
01318   */
01319 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01320 {
01321   return hi2s->ErrorCode;
01322 }
01323 /**
01324   * @}
01325   */
01326
01327 /**
01328   * @}
01329   */
01330
01331   /**
01332   * @brief  Get I2S Input Clock based on I2S source clock selection
01333   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01334   *               the configuration information for I2S module.
01335   * @retval I2S Clock Input
01336   */
01337 static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
01338 {
01339   uint32_t tmpreg = 0;
01340   /* This variable used to store the VCO Input (value in Hz) */
01341   uint32_t vcoinput = 0;
01342   /* This variable used to store the I2S_CK_x (value in Hz) */
01343   uint32_t i2sclocksource = 0;
01344
01345   /* Configure I2S Clock based on I2S source clock selection */
01346
01347   /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
01348   switch(hi2s->Init.ClockSource)
01349   {
01350     case I2S_CLOCK_SYSCLK :
01351     {
01352       /* Configure the PLLI2S division factor */
01353       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
01354       if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
01355       {
01356         /* In Case the PLL Source is HSI (Internal Clock) */
01357         vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
01358       }
01359       else
01360       {
01361         /* In Case the PLL Source is HSE (External Clock) */
01362         vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
01363       }
01364
01365       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
01366       /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
01367       tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;
01368       i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
01369
01370       break;
01371     }
01372     case I2S_CLOCK_EXTERNAL :
01373     {
01374       i2sclocksource = EXTERNAL_CLOCK_VALUE;
01375       break;
01376     }
01377     default :
01378     {
01379       break;
01380     }
01381   }
01382
01383   /* the return result is the value of I2S clock */
01384   return i2sclocksource;
01385 }
01386
01387 /** @addtogroup I2S_Private_Functions I2S Private Functions
01388   * @{
01389   */
01390 /**
01391   * @brief DMA I2S transmit process complete callback
01392   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01393   *                the configuration information for the specified DMA module.
01394   * @retval None
01395   */
01396 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01397 {
01398   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01399
01400   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01401   {
01402     hi2s->TxXferCount = 0;
01403
01404     /* Disable Tx DMA Request */
01405     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01406
01407     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01408     {
01409       if(hi2s->RxXferCount == 0)
01410       {
01411         hi2s->State = HAL_I2S_STATE_READY;
01412       }
01413     }
01414     else
01415     {
01416       hi2s->State = HAL_I2S_STATE_READY;
01417     }
01418   }
01419   HAL_I2S_TxCpltCallback(hi2s);
01420 }
01421
01422 /**
01423   * @brief DMA I2S transmit process half complete callback
01424   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01425   *                the configuration information for the specified DMA module.
01426   * @retval None
01427   */
01428 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01429 {
01430   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01431
01432   HAL_I2S_TxHalfCpltCallback(hi2s);
01433 }
01434
01435 /**
01436   * @brief DMA I2S receive process complete callback
01437   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01438   *                the configuration information for the specified DMA module.
01439   * @retval None
01440   */
01441 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01442 {
01443   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01444
01445   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01446   {
01447     /* Disable Rx DMA Request */
01448     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01449
01450     hi2s->RxXferCount = 0;
01451     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01452     {
01453       if(hi2s->TxXferCount == 0)
01454       {
01455         hi2s->State = HAL_I2S_STATE_READY;
01456       }
01457     }
01458     else
01459     {
01460       hi2s->State = HAL_I2S_STATE_READY;
01461     }
01462   }
01463   HAL_I2S_RxCpltCallback(hi2s);
01464 }
01465
01466 /**
01467   * @brief DMA I2S receive process half complete callback
01468   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01469   *                the configuration information for the specified DMA module.
01470   * @retval None
01471   */
01472 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01473 {
01474   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01475
01476   HAL_I2S_RxHalfCpltCallback(hi2s);
01477 }
01478
01479 /**
01480   * @brief DMA I2S communication error callback
01481   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01482   *                the configuration information for the specified DMA module.
01483   * @retval None
01484   */
01485 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01486 {
01487   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01488
01489   /* Disable Rx and Tx DMA Request */
01490   hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01491   hi2s->TxXferCount = 0;
01492   hi2s->RxXferCount = 0;
01493
01494   hi2s->State= HAL_I2S_STATE_READY;
01495
01496   /* Set the error code and execute error callback*/
01497   hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
01498   HAL_I2S_ErrorCallback(hi2s);
01499 }
01500
01501 /**
01502   * @brief Transmit an amount of data in non-blocking mode with Interrupt
01503   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01504   *         the configuration information for I2S module
01505   * @retval None
01506   */
01507 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
01508 {
01509   /* Transmit data */
01510   hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01511   hi2s->TxXferCount--;
01512
01513   if(hi2s->TxXferCount == 0)
01514   {
01515     /* Disable TXE and ERR interrupt */
01516     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01517
01518     hi2s->State = HAL_I2S_STATE_READY;
01519     HAL_I2S_TxCpltCallback(hi2s);
01520   }
01521 }
01522
01523 /**
01524   * @brief Receive an amount of data in non-blocking mode with Interrupt
01525   * @param hi2s: I2S handle
01526   * @retval None
01527   */
01528 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
01529 {
01530   /* Receive data */
01531   (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01532   hi2s->RxXferCount--;
01533
01534   if(hi2s->RxXferCount == 0)
01535   {
01536     /* Disable RXNE and ERR interrupt */
01537     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01538
01539     hi2s->State = HAL_I2S_STATE_READY;
01540     HAL_I2S_RxCpltCallback(hi2s);
01541   }
01542 }
01543 /**
01544   * @}
01545   */
01546
01547 #endif /* HAL_I2S_MODULE_ENABLED */
01548 /**
01549   * @}
01550   */
01551
01552 /**
01553   * @}
01554   */
01555
01556 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_i2s.h Source File

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stm32f7xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of I2S HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_I2S_H
00040 #define __STM32F7xx_HAL_I2S_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2S
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2S_Exported_Types I2S Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief I2S Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;                /*!< Specifies the I2S operating mode.
00068                                      This parameter can be a value of @ref I2S_Mode */
00069
00070   uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
00071                                      This parameter can be a value of @ref I2S_Standard */
00072
00073   uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
00074                                      This parameter can be a value of @ref I2S_Data_Format */
00075
00076   uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
00077                                      This parameter can be a value of @ref I2S_MCLK_Output */
00078
00079   uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
00080                                      This parameter can be a value of @ref I2S_Audio_Frequency */
00081
00082   uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
00083                                      This parameter can be a value of @ref I2S_Clock_Polarity */
00084
00085   uint32_t ClockSource;         /*!< Specifies the I2S Clock Source.
00086                                      This parameter can be a value of @ref I2S_Clock_Source */
00087 }I2S_InitTypeDef;
00088
00089 /**
00090   * @brief  HAL State structures definition
00091   */
00092 typedef enum
00093 {
00094   HAL_I2S_STATE_RESET      = 0x00,  /*!< I2S not yet initialized or disabled                */
00095   HAL_I2S_STATE_READY      = 0x01,  /*!< I2S initialized and ready for use                  */
00096   HAL_I2S_STATE_BUSY       = 0x02,  /*!< I2S internal process is ongoing                    */
00097   HAL_I2S_STATE_BUSY_TX    = 0x03,  /*!< Data Transmission process is ongoing               */
00098   HAL_I2S_STATE_BUSY_RX    = 0x04,  /*!< Data Reception process is ongoing                  */
00099   HAL_I2S_STATE_BUSY_TX_RX = 0x05,  /*!< Data Transmission and Reception process is ongoing */
00100   HAL_I2S_STATE_TIMEOUT    = 0x06,  /*!< I2S timeout state                                  */
00101   HAL_I2S_STATE_ERROR      = 0x07   /*!< I2S error state                                    */
00102
00103 }HAL_I2S_StateTypeDef;
00104
00105 /**
00106   * @brief I2S handle Structure definition
00107   */
00108 typedef struct
00109 {
00110   SPI_TypeDef                *Instance;    /* I2S registers base address */
00111
00112   I2S_InitTypeDef            Init;         /* I2S communication parameters */
00113
00114   uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
00115
00116   __IO uint16_t              TxXferSize;   /* I2S Tx transfer size */
00117
00118   __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter */
00119
00120   uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
00121
00122   __IO uint16_t              RxXferSize;   /* I2S Rx transfer size */
00123
00124   __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter
00125                                               (This field is initialized at the
00126                                                same value as transfer size at the
00127                                                beginning of the transfer and
00128                                                decremented when a sample is received.
00129                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00130
00131   DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters */
00132
00133   DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters */
00134
00135   __IO HAL_LockTypeDef       Lock;         /* I2S locking object */
00136
00137   __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state */
00138
00139   __IO uint32_t  ErrorCode;                /* I2S Error code                 */
00140
00141 }I2S_HandleTypeDef;
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported constants --------------------------------------------------------*/
00147 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00148   * @{
00149   */
00150
00151 /** @defgroup I2S_Error_Defintion I2S_Error_Defintion
00152   *@brief     I2S Error Code
00153   * @{
00154   */
00155 #define HAL_I2S_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error           */
00156 #define HAL_I2S_ERROR_TIMEOUT   ((uint32_t)0x00000001)  /*!< Timeout error      */
00157 #define HAL_I2S_ERROR_OVR       ((uint32_t)0x00000002)  /*!< OVR error          */
00158 #define HAL_I2S_ERROR_UDR       ((uint32_t)0x00000004)  /*!< UDR error          */
00159 #define HAL_I2S_ERROR_DMA       ((uint32_t)0x00000008)  /*!< DMA transfer error */
00160 #define HAL_I2S_ERROR_UNKNOW    ((uint32_t)0x00000010)  /*!< Unknow Error error */
00161
00162 /**
00163   * @}
00164   */
00165 /** @defgroup I2S_Clock_Source I2S Clock Source
00166   * @{
00167   */
00168 #define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001)
00169 #define I2S_CLOCK_SYSCLK                  ((uint32_t)0x00000002)
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup I2S_Mode I2S Mode
00175   * @{
00176   */
00177 #define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000)
00178 #define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100)
00179 #define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200)
00180 #define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300)
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup I2S_Standard I2S Standard
00186   * @{
00187   */
00188 #define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000)
00189 #define I2S_STANDARD_MSB                 ((uint32_t)0x00000010)
00190 #define I2S_STANDARD_LSB                 ((uint32_t)0x00000020)
00191 #define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030)
00192 #define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0)
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup I2S_Data_Format I2S Data Format
00198   * @{
00199   */
00200 #define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000)
00201 #define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001)
00202 #define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003)
00203 #define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005)
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup I2S_MCLK_Output I2S Mclk Output
00209   * @{
00210   */
00211 #define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
00212 #define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00218   * @{
00219   */
00220 #define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
00221 #define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
00222 #define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
00223 #define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
00224 #define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
00225 #define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
00226 #define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
00227 #define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
00228 #define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
00229 #define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
00230 /**
00231   * @}
00232   */
00233
00234
00235 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
00236   * @{
00237   */
00238 #define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
00239 #define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
00245   * @{
00246   */
00247 #define I2S_IT_TXE                      SPI_CR2_TXEIE
00248 #define I2S_IT_RXNE                     SPI_CR2_RXNEIE
00249 #define I2S_IT_ERR                      SPI_CR2_ERRIE
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup I2S_Flags_Definition I2S Flags Definition
00255   * @{
00256   */
00257 #define I2S_FLAG_TXE                    SPI_SR_TXE
00258 #define I2S_FLAG_RXNE                   SPI_SR_RXNE
00259
00260 #define I2S_FLAG_UDR                    SPI_SR_UDR
00261 #define I2S_FLAG_OVR                    SPI_SR_OVR
00262 #define I2S_FLAG_FRE                    SPI_SR_FRE
00263
00264 #define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
00265 #define I2S_FLAG_BSY                    SPI_SR_BSY
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /* Exported macros -----------------------------------------------------------*/
00275 /** @defgroup I2S_Exported_Macros I2S Exported Macros
00276   * @{
00277   */
00278
00279 /** @brief  Reset I2S handle state
00280   * @param  __HANDLE__: specifies the I2S handle.
00281   * @retval None
00282   */
00283 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00284
00285 /** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
00286   * @param  __HANDLE__: specifies the I2S Handle.
00287   * @retval None
00288   */
00289 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
00290 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
00291
00292 /** @brief  Enable or disable the specified I2S interrupts.
00293   * @param  __HANDLE__: specifies the I2S Handle.
00294   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00295   *        This parameter can be one of the following values:
00296   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00297   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00298   *            @arg I2S_IT_ERR: Error interrupt enable
00299   * @retval None
00300   */
00301 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00302 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
00303
00304 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00305   * @param  __HANDLE__: specifies the I2S Handle.
00306   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00307   * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
00308   *          This parameter can be one of the following values:
00309   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00310   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00311   *            @arg I2S_IT_ERR: Error interrupt enable
00312   * @retval The new state of __IT__ (TRUE or FALSE).
00313   */
00314 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00315
00316 /** @brief  Checks whether the specified I2S flag is set or not.
00317   * @param  __HANDLE__: specifies the I2S Handle.
00318   * @param  __FLAG__: specifies the flag to check.
00319   *        This parameter can be one of the following values:
00320   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00321   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00322   *            @arg I2S_FLAG_UDR: Underrun flag
00323   *            @arg I2S_FLAG_OVR: Overrun flag
00324   *            @arg I2S_FLAG_FRE: Frame error flag
00325   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00326   *            @arg I2S_FLAG_BSY: Busy flag
00327   * @retval The new state of __FLAG__ (TRUE or FALSE).
00328   */
00329 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00330
00331 /** @brief Clears the I2S OVR pending flag.
00332   * @param  __HANDLE__: specifies the I2S Handle.
00333   * @retval None
00334   */
00335 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
00336   do{                                           \
00337   __IO uint32_t tmpreg = 0x00;                       \
00338     tmpreg = (__HANDLE__)->Instance->DR;        \
00339     tmpreg = (__HANDLE__)->Instance->SR;        \
00340     UNUSED(tmpreg);                             \
00341   } while(0)
00342
00343 /** @brief Clears the I2S UDR pending flag.
00344   * @param  __HANDLE__: specifies the I2S Handle.
00345   * @retval None
00346   */
00347 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
00348   do{                                             \
00349 __IO uint32_t tmpreg = 0x00;                         \
00350   tmpreg = (__HANDLE__)->Instance->SR;          \
00351   UNUSED(tmpreg);                               \
00352   } while(0)
00353 /**
00354   * @}
00355   */
00356
00357 /* Exported functions --------------------------------------------------------*/
00358 /** @addtogroup I2S_Exported_Functions  I2S Exported Functions
00359   * @{
00360   */
00361
00362 /** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00363   * @{
00364   */
00365
00366 /* Initialization and de-initialization functions *****************************/
00367 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00368 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
00369 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00370 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00371 /**
00372   * @}
00373   */
00374
00375 /** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
00376   * @{
00377   */
00378 /* I/O operation functions  ***************************************************/
00379  /* Blocking mode: Polling */
00380 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00381 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00382
00383  /* Non-Blocking mode: Interrupt */
00384 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00385 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00386 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00387
00388 /* Non-Blocking mode: DMA */
00389 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00390 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00391
00392 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00393 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00394 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00395
00396 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00397 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00398 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00399 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00400 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00401 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00402 /**
00403   * @}
00404   */
00405
00406 /** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
00407   * @{
00408   */
00409 /* Peripheral Control and State functions  ************************************/
00410 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00411 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420
00421 /* Private types -------------------------------------------------------------*/
00422 /* Private variables ---------------------------------------------------------*/
00423 /* Private constants ---------------------------------------------------------*/
00424 /** @defgroup I2S_Private_Constants I2S Private Constants
00425   * @{
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /* Private macros ------------------------------------------------------------*/
00433 /** @defgroup I2S_Private_Macros I2S Private Macros
00434   * @{
00435   */
00436 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
00437                                    ((CLOCK) == I2S_CLOCK_SYSCLK))
00438
00439 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
00440                            ((MODE) == I2S_MODE_SLAVE_RX) || \
00441                            ((MODE) == I2S_MODE_MASTER_TX)|| \
00442                            ((MODE) == I2S_MODE_MASTER_RX))
00443
00444 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
00445                                    ((STANDARD) == I2S_STANDARD_MSB)       || \
00446                                    ((STANDARD) == I2S_STANDARD_LSB)       || \
00447                                    ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
00448                                    ((STANDARD) == I2S_STANDARD_PCM_LONG))
00449
00450 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
00451                                     ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
00452                                     ((FORMAT) == I2S_DATAFORMAT_24B)          || \
00453                                     ((FORMAT) == I2S_DATAFORMAT_32B))
00454
00455 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
00456                                     ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
00457
00458 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
00459                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
00460                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
00461
00462 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
00463                            ((CPOL) == I2S_CPOL_HIGH))
00464 /**
00465   * @}
00466   */
00467
00468 /**
00469   * @}
00470   */
00471
00472 /**
00473   * @}
00474   */
00475
00476 #ifdef __cplusplus
00477 }
00478 #endif
00479
00480
00481 #endif /* __STM32F7xx_HAL_I2S_H */
00482
00483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_irda.c Source File

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stm32f7xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   IRDA HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the IrDA SIR ENDEC block (IrDA):
00010   *           + Initialization and de-initialization methods
00011   *           + IO operation methods
00012   *           + Peripheral Control methods
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The IRDA HAL driver can be used as follows:
00020
00021     (#) Declare a IRDA_HandleTypeDef handle structure.
00022     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
00023         (##) Enable the USARTx interface clock.
00024         (##) IRDA pins configuration:
00025             (+++) Enable the clock for the IRDA GPIOs.
00026             (+++) Configure these IRDA pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00028              and HAL_IRDA_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00032              and HAL_IRDA_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036             (+++) Configure the DMA Tx/Rx Stream.
00037             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
00039
00040     (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
00041         and Mode(Receiver/Transmitter) in the hirda Init structure.
00042
00043     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00044         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00045             by calling the customized HAL_IRDA_MspInit() API.
00046     -@@- The specific IRDA interrupts (Transmission complete interrupt,
00047         RXNE interrupt and Error Interrupts) will be managed using the macros
00048         __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00049
00050     (#) Three operation modes are available within this driver :
00051
00052     *** Polling mode IO operation ***
00053     =================================
00054     [..]
00055       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00056       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00057
00058     *** Interrupt mode IO operation ***
00059     ===================================
00060     [..]
00061       (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
00062       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
00063            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
00064       (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
00065       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
00066            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
00067       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00068            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
00069
00070     *** DMA mode IO operation ***
00071     =============================
00072     [..]
00073       (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00074       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
00075            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
00076       (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00077       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
00078            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
00079       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00080            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
00081
00082     *** IRDA HAL driver macros list ***
00083     ===================================
00084     [..]
00085       Below the list of most used macros in IRDA HAL driver.
00086
00087      (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00088      (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00089      (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
00090      (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
00091      (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
00092      (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
00093
00094      (@) You can refer to the IRDA HAL driver header file for more useful macros
00095
00096   @endverbatim
00097   ******************************************************************************
00098   * @attention
00099   *
00100   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00101   *
00102   * Redistribution and use in source and binary forms, with or without modification,
00103   * are permitted provided that the following conditions are met:
00104   *   1. Redistributions of source code must retain the above copyright notice,
00105   *      this list of conditions and the following disclaimer.
00106   *   2. Redistributions in binary form must reproduce the above copyright notice,
00107   *      this list of conditions and the following disclaimer in the documentation
00108   *      and/or other materials provided with the distribution.
00109   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00110   *      may be used to endorse or promote products derived from this software
00111   *      without specific prior written permission.
00112   *
00113   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00114   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00115   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00116   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00117   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00118   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00119   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00120   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00121   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00122   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00123   *
00124   ******************************************************************************
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32f7xx_hal.h"
00129
00130 /** @addtogroup STM32F7xx_HAL_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup IRDA IRDA
00135   * @brief HAL IRDA module driver
00136   * @{
00137   */
00138 #ifdef HAL_IRDA_MODULE_ENABLED
00139
00140 /* Private typedef -----------------------------------------------------------*/
00141 /* Private define ------------------------------------------------------------*/
00142 /** @addtogroup IRDA_Private_Constants
00143   * @{
00144   */
00145 #define TEACK_REACK_TIMEOUT            1000
00146 #define HAL_IRDA_TXDMA_TIMEOUTVALUE    22000
00147 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00148                                    | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
00149 /**
00150   * @}
00151   */
00152 /* Private macro -------------------------------------------------------------*/
00153 /* Private variables ---------------------------------------------------------*/
00154 /* Private function prototypes -----------------------------------------------*/
00155 /** @addtogroup IRDA_Private_Functions
00156   * @{
00157   */
00158 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00159 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00160 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00161 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00162 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00163 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
00164 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00165 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00166 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00167 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00168 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00169 /**
00170   * @}
00171   */
00172 /* Exported functions --------------------------------------------------------*/
00173 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
00174   * @{
00175   */
00176
00177 /** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
00178   *  @brief    Initialization and Configuration functions
00179   *
00180 @verbatim
00181
00182 ===============================================================================
00183             ##### Initialization and Configuration functions #####
00184  ===============================================================================
00185     [..]
00186     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00187     in IrDA mode.
00188       (+) For the asynchronous mode only these parameters can be configured:
00189         (++) BaudRate
00190         (++) WordLength
00191         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00192              in the data register is transmitted but is changed by the parity bit.
00193              Depending on the frame length defined by the M bit (8-bits or 9-bits),
00194              please refer to Reference manual for possible IRDA frame formats.
00195         (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
00196              not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
00197              specification specifies a minimum of 10 ms delay between transmission and
00198              reception (IrDA is a half duplex protocol).
00199         (++) Mode: Receiver/transmitter modes
00200         (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
00201     [..]
00202     The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
00203     are available in reference manual).
00204
00205 @endverbatim
00206   * @{
00207   */
00208
00209 /**
00210   * @brief  Initializes the IRDA mode according to the specified
00211   *         parameters in the IRDA_InitTypeDef and create the associated handle.
00212   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00213   *                the configuration information for the specified IRDA module.
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00217 {
00218   /* Check the IRDA handle allocation */
00219   if(hirda == NULL)
00220   {
00221     return HAL_ERROR;
00222   }
00223
00224   /* Check the USART/UART associated to the IRDA handle */
00225   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00226
00227   if(hirda->State == HAL_IRDA_STATE_RESET)
00228   {
00229     /* Allocate lock resource and initialize it */
00230     hirda->Lock = HAL_UNLOCKED;
00231     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00232     HAL_IRDA_MspInit(hirda);
00233   }
00234
00235   hirda->State = HAL_IRDA_STATE_BUSY;
00236
00237   /* Disable the Peripheral to update the configuration registers */
00238   __HAL_IRDA_DISABLE(hirda);
00239
00240   /* Set the IRDA Communication parameters */
00241   IRDA_SetConfig(hirda);
00242
00243   /* In IRDA mode, the following bits must be kept cleared:
00244   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00245   - SCEN and HDSEL bits in the USART_CR3 register.*/
00246   hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
00247   hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
00248
00249   /* set the UART/USART in IRDA mode */
00250   hirda->Instance->CR3 |= USART_CR3_IREN;
00251
00252   /* Enable the Peripheral */
00253   __HAL_IRDA_ENABLE(hirda);
00254
00255   /* TEACK and/or REACK to check before moving hirda->State to Ready */
00256   return (IRDA_CheckIdleState(hirda));
00257 }
00258
00259 /**
00260   * @brief  DeInitializes the IRDA peripheral
00261   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00262   *                the configuration information for the specified IRDA module.
00263   * @retval HAL status
00264   */
00265 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00266 {
00267   /* Check the IRDA handle allocation */
00268   if(hirda == NULL)
00269   {
00270     return HAL_ERROR;
00271   }
00272
00273   /* Check the parameters */
00274   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00275
00276   hirda->State = HAL_IRDA_STATE_BUSY;
00277
00278   /* DeInit the low level hardware */
00279   HAL_IRDA_MspDeInit(hirda);
00280   /* Disable the Peripheral */
00281   __HAL_IRDA_DISABLE(hirda);
00282
00283   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00284   hirda->State = HAL_IRDA_STATE_RESET;
00285
00286   /* Release Lock */
00287   __HAL_UNLOCK(hirda);
00288
00289   return HAL_OK;
00290 }
00291
00292 /**
00293   * @brief  IRDA MSP Init.
00294   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00295   *                the configuration information for the specified IRDA module.
00296   * @retval None
00297   */
00298  __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00299 {
00300   /* Prevent unused argument(s) compilation warning */
00301   UNUSED(hirda);
00302
00303   /* NOTE : This function Should not be modified, when the callback is needed,
00304             the HAL_IRDA_MspInit could be implemented in the user file
00305    */
00306 }
00307
00308 /**
00309   * @brief  IRDA MSP DeInit.
00310   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00311   *                the configuration information for the specified IRDA module.
00312   * @retval None
00313   */
00314  __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00315 {
00316   /* Prevent unused argument(s) compilation warning */
00317   UNUSED(hirda);
00318
00319   /* NOTE : This function Should not be modified, when the callback is needed,
00320             the HAL_IRDA_MspDeInit could be implemented in the user file
00321    */
00322 }
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00329   *  @brief   IRDA Transmit/Receive functions
00330   *
00331 @verbatim
00332  ===============================================================================
00333                       ##### IO operation functions #####
00334  ===============================================================================
00335     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00336     [..]
00337     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00338     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00339     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00340     While receiving data, transmission should be avoided as the data to be transmitted
00341     could be corrupted.
00342
00343     (#) There are two modes of transfer:
00344        (++) Blocking mode: the communication is performed in polling mode.
00345             The HAL status of all data processing is returned by the same function
00346             after finishing transfer.
00347        (++) No-Blocking mode: the communication is performed using Interrupts
00348            or DMA, these API's return the HAL status.
00349            The end of the data processing will be indicated through the
00350            dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00351            using DMA mode.
00352            The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00353            will be executed respectively at the end of the Transmit or Receive process
00354            The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00355
00356     (#) Blocking mode API's are :
00357         (++) HAL_IRDA_Transmit()
00358         (++) HAL_IRDA_Receive()
00359
00360     (#) Non-Blocking mode API's with Interrupt are :
00361         (++) HAL_IRDA_Transmit_IT()
00362         (++) HAL_IRDA_Receive_IT()
00363         (++) HAL_IRDA_IRQHandler()
00364         (++) IRDA_Transmit_IT()
00365         (++) IRDA_Receive_IT()
00366
00367     (#) Non-Blocking mode functions with DMA are :
00368         (++) HAL_IRDA_Transmit_DMA()
00369         (++) HAL_IRDA_Receive_DMA()
00370
00371     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00372         (++) HAL_IRDA_TxCpltCallback()
00373         (++) HAL_IRDA_RxCpltCallback()
00374         (++) HAL_IRDA_ErrorCallback()
00375
00376 @endverbatim
00377   * @{
00378   */
00379
00380 /**
00381   * @brief  Sends an amount of data in blocking mode.
00382   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00383   *                the configuration information for the specified IRDA module.
00384   * @param  pData: Pointer to data buffer
00385   * @param  Size: Amount of data to be sent
00386   * @param  Timeout: Specify timeout value
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00390 {
00391    uint16_t* tmp;
00392
00393   if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
00394   {
00395     if((pData == NULL) || (Size == 0))
00396     {
00397       return  HAL_ERROR;
00398     }
00399
00400     /* Process Locked */
00401     __HAL_LOCK(hirda);
00402     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00403
00404     if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
00405     {
00406       hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
00407     }
00408     else
00409     {
00410       hirda->State = HAL_IRDA_STATE_BUSY_TX;
00411     }
00412
00413     hirda->TxXferSize = Size;
00414     hirda->TxXferCount = Size;
00415     while(hirda->TxXferCount > 0)
00416     {
00417       hirda->TxXferCount--;
00418
00419         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
00420         {
00421           return HAL_TIMEOUT;
00422         }
00423       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00424         {
00425           tmp = (uint16_t*) pData;
00426           hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00427           pData +=2;
00428         }
00429         else
00430         {
00431           hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00432         }
00433       }
00434
00435     if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
00436     {
00437       return HAL_TIMEOUT;
00438     }
00439
00440     if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
00441     {
00442       hirda->State = HAL_IRDA_STATE_BUSY_RX;
00443     }
00444     else
00445     {
00446       hirda->State = HAL_IRDA_STATE_READY;
00447     }
00448
00449     /* Process Unlocked */
00450     __HAL_UNLOCK(hirda);
00451
00452     return HAL_OK;
00453   }
00454   else
00455   {
00456     return HAL_BUSY;
00457   }
00458 }
00459
00460 /**
00461   * @brief  Receive an amount of data in blocking mode.
00462   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00463   *                the configuration information for the specified IRDA module.
00464   * @param  pData: Pointer to data buffer
00465   * @param  Size: Amount of data to be received
00466   * @param  Timeout: Specify timeout value
00467   * @retval HAL status
00468   */
00469 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00470 {
00471   uint16_t* tmp;
00472   uint16_t uhMask;
00473
00474   if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
00475   {
00476     if((pData == NULL) || (Size == 0))
00477     {
00478       return  HAL_ERROR;
00479     }
00480
00481     /* Process Locked */
00482     __HAL_LOCK(hirda);
00483     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00484
00485     if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
00486     {
00487       hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
00488     }
00489     else
00490     {
00491       hirda->State = HAL_IRDA_STATE_BUSY_RX;
00492     }
00493
00494     hirda->RxXferSize = Size;
00495     hirda->RxXferCount = Size;
00496
00497     /* Computation of the mask to apply to the RDR register
00498        of the UART associated to the IRDA */
00499     IRDA_MASK_COMPUTATION(hirda);
00500     uhMask = hirda->Mask;
00501
00502     /* Check data remaining to be received */
00503     while(hirda->RxXferCount > 0)
00504     {
00505       hirda->RxXferCount--;
00506
00507       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00508       {
00509         return HAL_TIMEOUT;
00510       }
00511       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00512       {
00513         tmp = (uint16_t*) pData ;
00514         *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
00515         pData +=2;
00516       }
00517       else
00518       {
00519         *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00520       }
00521     }
00522
00523     if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
00524     {
00525       hirda->State = HAL_IRDA_STATE_BUSY_TX;
00526     }
00527     else
00528     {
00529       hirda->State = HAL_IRDA_STATE_READY;
00530     }
00531
00532     /* Process Unlocked */
00533     __HAL_UNLOCK(hirda);
00534
00535     return HAL_OK;
00536   }
00537   else
00538   {
00539     return HAL_BUSY;
00540   }
00541 }
00542
00543 /**
00544   * @brief  Send an amount of data in non blocking mode.
00545   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00546   *                the configuration information for the specified IRDA module.
00547   * @param  pData: Pointer to data buffer
00548   * @param  Size: Amount of data to be sent
00549   * @retval HAL status
00550   */
00551 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00552 {
00553   if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
00554   {
00555     if((pData == NULL) || (Size == 0))
00556     {
00557       return HAL_ERROR;
00558     }
00559
00560     /* Process Locked */
00561     __HAL_LOCK(hirda);
00562
00563     hirda->pTxBuffPtr = pData;
00564     hirda->TxXferSize = Size;
00565     hirda->TxXferCount = Size;
00566
00567     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00568     if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
00569     {
00570       hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
00571     }
00572     else
00573     {
00574       hirda->State = HAL_IRDA_STATE_BUSY_TX;
00575     }
00576
00577     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00578     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
00579
00580     /* Process Unlocked */
00581     __HAL_UNLOCK(hirda);
00582
00583     /* Enable the IRDA Transmit Complete Interrupt */
00584     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
00585
00586     return HAL_OK;
00587   }
00588   else
00589   {
00590     return HAL_BUSY;
00591   }
00592 }
00593
00594 /**
00595   * @brief  Receives an amount of data in non blocking mode.
00596   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00597   *                the configuration information for the specified IRDA module.
00598   * @param  pData: Pointer to data buffer
00599   * @param  Size: Amount of data to be received
00600   * @retval HAL status
00601   */
00602 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00603 {
00604   if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
00605   {
00606     if((pData == NULL) || (Size == 0))
00607     {
00608       return HAL_ERROR;
00609     }
00610
00611     /* Process Locked */
00612   __HAL_LOCK(hirda);
00613
00614     hirda->pRxBuffPtr = pData;
00615     hirda->RxXferSize = Size;
00616     hirda->RxXferCount = Size;
00617
00618     /* Computation of the mask to apply to the RDR register
00619        of the UART associated to the IRDA */
00620     IRDA_MASK_COMPUTATION(hirda);
00621
00622     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00623     if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
00624     {
00625       hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
00626     }
00627     else
00628     {
00629       hirda->State = HAL_IRDA_STATE_BUSY_RX;
00630     }
00631
00632     /* Enable the IRDA Parity Error Interrupt */
00633     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
00634
00635     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00636     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
00637
00638     /* Process Unlocked */
00639     __HAL_UNLOCK(hirda);
00640
00641     /* Enable the IRDA Data Register not empty Interrupt */
00642     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
00643
00644     return HAL_OK;
00645   }
00646   else
00647   {
00648     return HAL_BUSY;
00649   }
00650 }
00651
00652 /**
00653   * @brief  Sends an amount of data in non blocking mode.
00654   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00655   *                the configuration information for the specified IRDA module.
00656   * @param  pData: Pointer to data buffer
00657   * @param  Size: Amount of data to be sent
00658   * @retval HAL status
00659   */
00660 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00661 {
00662   uint32_t *tmp;
00663
00664   if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
00665   {
00666     if((pData == NULL) || (Size == 0))
00667     {
00668       return HAL_ERROR;
00669     }
00670
00671     /* Process Locked */
00672     __HAL_LOCK(hirda);
00673
00674     hirda->pTxBuffPtr = pData;
00675     hirda->TxXferSize = Size;
00676     hirda->TxXferCount = Size;
00677
00678     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00679
00680     if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
00681     {
00682       hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
00683     }
00684     else
00685     {
00686       hirda->State = HAL_IRDA_STATE_BUSY_TX;
00687     }
00688
00689     /* Set the IRDA DMA transfer complete callback */
00690     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
00691
00692     /* Set the IRDA DMA half transfer complete callback */
00693     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
00694
00695     /* Set the DMA error callback */
00696     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
00697
00698     /* Enable the IRDA transmit DMA channel */
00699     tmp = (uint32_t*)&pData;
00700     HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
00701
00702     /* Clear the TC flag in the SR register by writing 0 to it */
00703     __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC);
00704
00705     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00706        in the IRDA CR3 register */
00707     hirda->Instance->CR3 |= USART_CR3_DMAT;
00708
00709     /* Process Unlocked */
00710     __HAL_UNLOCK(hirda);
00711
00712     return HAL_OK;
00713   }
00714   else
00715   {
00716     return HAL_BUSY;
00717   }
00718 }
00719
00720 /**
00721   * @brief  Receives an amount of data in non blocking mode.
00722   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00723   *                the configuration information for the specified IRDA module.
00724   * @param  pData: Pointer to data buffer
00725   * @param  Size: Amount of data to be received
00726   * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
00727   * @retval HAL status
00728   */
00729 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00730 {
00731   uint32_t *tmp;
00732
00733   if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
00734   {
00735     if((pData == NULL) || (Size == 0))
00736     {
00737       return HAL_ERROR;
00738     }
00739
00740     /* Process Locked */
00741     __HAL_LOCK(hirda);
00742
00743     hirda->pRxBuffPtr = pData;
00744     hirda->RxXferSize = Size;
00745
00746     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00747     if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
00748     {
00749       hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
00750     }
00751     else
00752     {
00753       hirda->State = HAL_IRDA_STATE_BUSY_RX;
00754     }
00755
00756     /* Set the IRDA DMA transfer complete callback */
00757     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
00758
00759     /* Set the IRDA DMA half transfer complete callback */
00760     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
00761
00762     /* Set the DMA error callback */
00763     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
00764
00765     /* Enable the DMA channel */
00766     tmp = (uint32_t*)&pData;
00767     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
00768
00769     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00770        in the IRDA CR3 register */
00771      hirda->Instance->CR3 |= USART_CR3_DMAR;
00772
00773      /* Process Unlocked */
00774      __HAL_UNLOCK(hirda);
00775
00776     return HAL_OK;
00777   }
00778   else
00779   {
00780     return HAL_BUSY;
00781   }
00782 }
00783
00784 /**
00785   * @brief Pauses the DMA Transfer.
00786   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00787   *                the configuration information for the specified IRDA module.
00788   * @retval HAL status
00789   */
00790 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
00791 {
00792   /* Process Locked */
00793   __HAL_LOCK(hirda);
00794
00795   if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
00796   {
00797     /* Disable the UART DMA Tx request */
00798     hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
00799   }
00800   else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
00801   {
00802     /* Disable the UART DMA Rx request */
00803     hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
00804   }
00805   else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
00806   {
00807     /* Disable the UART DMA Tx & Rx requests */
00808     hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
00809     hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
00810   }
00811
00812   /* Process Unlocked */
00813   __HAL_UNLOCK(hirda);
00814
00815   return HAL_OK;
00816 }
00817
00818 /**
00819   * @brief Resumes the DMA Transfer.
00820   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00821   *                the configuration information for the specified UART module.
00822   * @retval HAL status
00823   */
00824 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
00825 {
00826   /* Process Locked */
00827   __HAL_LOCK(hirda);
00828
00829   if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
00830   {
00831     /* Enable the UART DMA Tx request */
00832     hirda->Instance->CR3 |= USART_CR3_DMAT;
00833   }
00834   else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
00835   {
00836     /* Clear the Overrun flag before resuming the Rx transfer*/
00837     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
00838
00839     /* Enable the UART DMA Rx request */
00840     hirda->Instance->CR3 |= USART_CR3_DMAR;
00841   }
00842   else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
00843   {
00844     /* Clear the Overrun flag before resuming the Rx transfer*/
00845     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
00846
00847     /* Enable the UART DMA Tx & Rx request */
00848     hirda->Instance->CR3 |= USART_CR3_DMAT;
00849     hirda->Instance->CR3 |= USART_CR3_DMAR;
00850   }
00851
00852   /* Process Unlocked */
00853   __HAL_UNLOCK(hirda);
00854
00855   return HAL_OK;
00856 }
00857
00858 /**
00859   * @brief Stops the DMA Transfer.
00860   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00861   *                the configuration information for the specified UART module.
00862   * @retval HAL status
00863   */
00864 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
00865 {
00866   /* The Lock is not implemented on this API to allow the user application
00867      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
00868      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
00869      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
00870      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
00871      the stream and the corresponding call back is executed. */
00872
00873   /* Disable the UART Tx/Rx DMA requests */
00874   hirda->Instance->CR3 &= ~USART_CR3_DMAT;
00875   hirda->Instance->CR3 &= ~USART_CR3_DMAR;
00876
00877   /* Abort the UART DMA tx channel */
00878   if(hirda->hdmatx != NULL)
00879   {
00880     HAL_DMA_Abort(hirda->hdmatx);
00881   }
00882   /* Abort the UART DMA rx channel */
00883   if(hirda->hdmarx != NULL)
00884   {
00885     HAL_DMA_Abort(hirda->hdmarx);
00886   }
00887
00888   hirda->State = HAL_IRDA_STATE_READY;
00889
00890   return HAL_OK;
00891 }
00892
00893 /**
00894   * @brief  This function handles IRDA interrupt request.
00895   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00896   *                the configuration information for the specified IRDA module.
00897   * @retval None
00898   */
00899 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
00900 {
00901   /* IRDA parity error interrupt occurred -------------------------------------*/
00902   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
00903   {
00904     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
00905
00906     hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
00907     /* Set the IRDA state ready to be able to start again the process */
00908     hirda->State = HAL_IRDA_STATE_READY;
00909   }
00910
00911   /* IRDA frame error interrupt occurred --------------------------------------*/
00912   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
00913   {
00914     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
00915
00916     hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
00917     /* Set the IRDA state ready to be able to start again the process */
00918     hirda->State = HAL_IRDA_STATE_READY;
00919   }
00920
00921   /* IRDA noise error interrupt occurred --------------------------------------*/
00922   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
00923   {
00924     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
00925
00926     hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
00927     /* Set the IRDA state ready to be able to start again the process */
00928     hirda->State = HAL_IRDA_STATE_READY;
00929   }
00930
00931   /* IRDA Over-Run interrupt occurred -----------------------------------------*/
00932   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
00933   {
00934     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
00935
00936     hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
00937     /* Set the IRDA state ready to be able to start again the process */
00938     hirda->State = HAL_IRDA_STATE_READY;
00939   }
00940
00941   /* Call IRDA Error Call back function if need be --------------------------*/
00942   if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
00943   {
00944     HAL_IRDA_ErrorCallback(hirda);
00945   }
00946
00947   /* IRDA in mode Receiver ---------------------------------------------------*/
00948   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
00949   {
00950     IRDA_Receive_IT(hirda);
00951     /* Clear RXNE interrupt flag */
00952     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
00953   }
00954
00955   /* IRDA in mode Transmitter ------------------------------------------------*/
00956  if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
00957   {
00958     IRDA_Transmit_IT(hirda);
00959   }
00960
00961   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
00962  if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
00963   {
00964     IRDA_EndTransmit_IT(hirda);
00965   }
00966 }
00967
00968 /**
00969   * @brief  Tx Transfer complete callbacks.
00970   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00971   *                the configuration information for the specified IRDA module.
00972   * @retval None
00973   */
00974  __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
00975 {
00976   /* Prevent unused argument(s) compilation warning */
00977   UNUSED(hirda);
00978
00979   /* NOTE : This function should not be modified, when the callback is needed,
00980             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
00981    */
00982 }
00983
00984 /**
00985   * @brief  Tx Half Transfer completed callbacks.
00986   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00987   *                the configuration information for the specified USART module.
00988   * @retval None
00989   */
00990  __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
00991 {
00992   /* Prevent unused argument(s) compilation warning */
00993   UNUSED(hirda);
00994
00995   /* NOTE : This function should not be modified, when the callback is needed,
00996             the HAL_IRDA_TxCpltCallback can be implemented in the user file
00997    */
00998 }
00999
01000 /**
01001   * @brief  Rx Transfer complete callbacks.
01002   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01003   *                the configuration information for the specified IRDA module.
01004   * @retval None
01005   */
01006 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01007 {
01008   /* Prevent unused argument(s) compilation warning */
01009   UNUSED(hirda);
01010
01011   /* NOTE : This function should not be modified, when the callback is needed,
01012             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
01013    */
01014 }
01015
01016 /**
01017   * @brief  Rx Half Transfer complete callbacks.
01018   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01019   *                the configuration information for the specified IRDA module.
01020   * @retval None
01021   */
01022 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
01023 {
01024   /* Prevent unused argument(s) compilation warning */
01025   UNUSED(hirda);
01026
01027   /* NOTE : This function should not be modified, when the callback is needed,
01028             the HAL_IRDA_RxCpltCallback can be implemented in the user file
01029    */
01030 }
01031
01032 /**
01033   * @brief IRDA error callbacks.
01034   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01035   *                the configuration information for the specified IRDA module.
01036   * @retval None
01037   */
01038  __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
01039 {
01040   /* Prevent unused argument(s) compilation warning */
01041   UNUSED(hirda);
01042
01043   /* NOTE : This function should not be modified, when the callback is needed,
01044             the HAL_IRDA_ErrorCallback can be implemented in the user file
01045    */
01046 }
01047
01048 /**
01049   * @}
01050   */
01051
01052 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions
01053   *  @brief   IRDA control functions
01054   *
01055 @verbatim
01056  ===============================================================================
01057                       ##### Peripheral Control functions #####
01058  ===============================================================================
01059     [..]
01060     This subsection provides a set of functions allowing to control the IRDA.
01061      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
01062      (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.
01063 @endverbatim
01064   * @{
01065   */
01066
01067 /**
01068   * @brief  Returns the IRDA state.
01069   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01070   *                the configuration information for the specified IRDA module.
01071   * @retval HAL state
01072   */
01073 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
01074 {
01075   return hirda->State;
01076 }
01077
01078 /**
01079   * @brief  Return the IRDA error code
01080   * @param  hirda : pointer to a IRDA_HandleTypeDef structure that contains
01081   *              the configuration information for the specified IRDA.
01082 * @retval IRDA Error Code
01083 */
01084 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
01085 {
01086   return hirda->ErrorCode;
01087 }
01088
01089 /**
01090   * @}
01091   */
01092
01093 /**
01094   * @brief Configure the IRDA peripheral
01095   * @param hirda: irda handle
01096   * @retval None
01097   */
01098 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
01099 {
01100   uint32_t tmpreg      = 0x00000000;
01101   uint32_t clocksource = 0x00000000;
01102
01103   /* Check the communication parameters */
01104   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
01105   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
01106   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
01107   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
01108   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
01109   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
01110   /*-------------------------- USART CR1 Configuration -----------------------*/
01111   /* Configure the IRDA Word Length, Parity and transfer Mode:
01112   Set the M bits according to hirda->Init.WordLength value
01113   Set PCE and PS bits according to hirda->Init.Parity value
01114   Set TE and RE bits according to hirda->Init.Mode value */
01115   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
01116
01117   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
01118
01119   /*-------------------------- USART CR3 Configuration -----------------------*/
01120   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
01121
01122   /*-------------------------- USART GTPR Configuration ----------------------*/
01123   MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);
01124
01125   /*-------------------------- USART BRR Configuration -----------------------*/
01126   IRDA_GETCLOCKSOURCE(hirda, clocksource);
01127   switch (clocksource)
01128   {
01129   case IRDA_CLOCKSOURCE_PCLK1:
01130     hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
01131     break;
01132   case IRDA_CLOCKSOURCE_PCLK2:
01133     hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate);
01134     break;
01135   case IRDA_CLOCKSOURCE_HSI:
01136     hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
01137     break;
01138   case IRDA_CLOCKSOURCE_SYSCLK:
01139     hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
01140     break;
01141   case IRDA_CLOCKSOURCE_LSE:
01142     hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
01143     break;
01144   default:
01145     break;
01146   }
01147 }
01148
01149 /**
01150   * @brief Check the IRDA Idle State
01151   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01152   *                the configuration information for the specified IRDA module.
01153   * @retval HAL status
01154   */
01155 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
01156 {
01157   /* Initialize the IRDA ErrorCode */
01158   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01159
01160   /* Check if the Transmitter is enabled */
01161   if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01162   {
01163     /* Wait until TEACK flag is set */
01164     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
01165     {
01166       hirda->State= HAL_IRDA_STATE_TIMEOUT;
01167       return HAL_TIMEOUT;
01168     }
01169   }
01170   /* Check if the Receiver is enabled */
01171   if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01172   {
01173     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
01174     {
01175       hirda->State= HAL_IRDA_STATE_TIMEOUT;
01176       return HAL_TIMEOUT;
01177     }
01178   }
01179   /* Process Unlocked */
01180   __HAL_UNLOCK(hirda);
01181
01182   /* Initialize the IRDA state*/
01183   hirda->State= HAL_IRDA_STATE_READY;
01184
01185   return HAL_OK;
01186 }
01187
01188 /**
01189   * @brief  This function handles IRDA Communication Timeout.
01190   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01191   *                the configuration information for the specified IRDA module.
01192   * @param  Flag: specifies the IRDA flag to check.
01193   * @param  Status: The new Flag status (SET or RESET).
01194   * @param  Timeout: Timeout duration
01195   * @retval HAL status
01196   */
01197 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01198 {
01199   uint32_t tickstart = 0x00;
01200   tickstart = HAL_GetTick();
01201
01202   /* Wait until flag is set */
01203   if(Status == RESET)
01204   {
01205     while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
01206     {
01207       /* Check for the Timeout */
01208       if(Timeout != HAL_MAX_DELAY)
01209       {
01210         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01211         {
01212           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01213           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01214           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01215           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01216           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01217
01218           hirda->State= HAL_IRDA_STATE_READY;
01219
01220           /* Process Unlocked */
01221           __HAL_UNLOCK(hirda);
01222
01223           return HAL_TIMEOUT;
01224         }
01225       }
01226     }
01227   }
01228   else
01229   {
01230     while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
01231     {
01232       /* Check for the Timeout */
01233       if(Timeout != HAL_MAX_DELAY)
01234       {
01235         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01236         {
01237           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01238           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01239           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01240           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01241           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01242
01243           hirda->State= HAL_IRDA_STATE_READY;
01244
01245           /* Process Unlocked */
01246           __HAL_UNLOCK(hirda);
01247
01248           return HAL_TIMEOUT;
01249         }
01250       }
01251     }
01252   }
01253   return HAL_OK;
01254 }
01255
01256 /**
01257   * @brief  Send an amount of data in non blocking mode.
01258   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01259   *                the configuration information for the specified IRDA module.
01260   * @retval HAL status
01261   */
01262 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
01263 {
01264   uint16_t* tmp;
01265
01266   if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
01267   {
01268     if(hirda->TxXferCount == 0)
01269     {
01270       /* Disable the IRDA Transmit Complete Interrupt */
01271       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01272
01273       if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
01274       {
01275         hirda->State = HAL_IRDA_STATE_BUSY_RX;
01276       }
01277       else
01278       {
01279         /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01280         __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01281
01282         hirda->State = HAL_IRDA_STATE_READY;
01283       }
01284
01285       HAL_IRDA_TxCpltCallback(hirda);
01286
01287       return HAL_OK;
01288     }
01289     else
01290     {
01291       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01292       {
01293         tmp = (uint16_t*) hirda->pTxBuffPtr;
01294         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
01295         hirda->pTxBuffPtr += 2;
01296       }
01297       else
01298       {
01299         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
01300       }
01301       hirda->TxXferCount--;
01302       return HAL_OK;
01303     }
01304   }
01305   else
01306   {
01307     return HAL_BUSY;
01308   }
01309 }
01310
01311 /**
01312   * @brief  Wraps up transmission in non blocking mode.
01313   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01314   *                the configuration information for the specified IRDA module.
01315   * @retval HAL status
01316   */
01317 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
01318 {
01319   /* Disable the IRDA Transmit Complete Interrupt */
01320   __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
01321
01322   /* Check if a receive process is ongoing or not */
01323   if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
01324   {
01325     hirda->State = HAL_IRDA_STATE_BUSY_RX;
01326   }
01327   else
01328   {
01329     /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01330     __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01331
01332     hirda->State = HAL_IRDA_STATE_READY;
01333   }
01334
01335   HAL_IRDA_TxCpltCallback(hirda);
01336
01337   return HAL_OK;
01338 }
01339
01340 /**
01341   * @brief Receive an amount of data in non blocking mode.
01342   *         Function called under interruption only, once
01343   *         interruptions have been enabled by HAL_IRDA_Receive_IT()
01344   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01345   *                the configuration information for the specified IRDA module.
01346   * @retval HAL status
01347   */
01348 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
01349 {
01350   uint16_t* tmp;
01351   uint16_t uhMask = hirda->Mask;
01352
01353   if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
01354   {
01355     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01356     {
01357       tmp = (uint16_t*) hirda->pRxBuffPtr ;
01358       *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
01359       hirda->pRxBuffPtr  +=2;
01360     }
01361     else
01362     {
01363       *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
01364     }
01365
01366     if(--hirda->RxXferCount == 0)
01367     {
01368       while(HAL_IS_BIT_SET(hirda->Instance->ISR, IRDA_FLAG_RXNE))
01369       {
01370       }
01371       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01372
01373       if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
01374       {
01375         hirda->State = HAL_IRDA_STATE_BUSY_TX;
01376       }
01377       else
01378       {
01379         /* Disable the IRDA Parity Error Interrupt */
01380         __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01381
01382         /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01383         __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01384
01385         hirda->State = HAL_IRDA_STATE_READY;
01386       }
01387
01388       HAL_IRDA_RxCpltCallback(hirda);
01389
01390       return HAL_OK;
01391     }
01392
01393     return HAL_OK;
01394   }
01395   else
01396   {
01397     return HAL_BUSY;
01398   }
01399 }
01400
01401 /**
01402   * @brief DMA IRDA Tx transfer completed callback
01403   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01404   *                the configuration information for the specified DMA module.
01405   * @retval None
01406   */
01407 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01408 {
01409   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01410
01411   /* DMA Normal mode*/
01412   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01413   {
01414     hirda->TxXferCount = 0;
01415
01416     /* Disable the DMA transfer for transmit request by setting the DMAT bit
01417        in the IRDA CR3 register */
01418     hirda->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
01419
01420     /* Enable the IRDA Transmit Complete Interrupt */
01421     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
01422   }
01423   /* DMA Circular mode */
01424   else
01425   {
01426    HAL_IRDA_TxCpltCallback(hirda);
01427   }
01428 }
01429
01430 /**
01431   * @brief DMA IRDA receive process half complete callback
01432   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01433   *                the configuration information for the specified DMA module.
01434   * @retval None
01435   */
01436 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
01437 {
01438   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01439
01440   HAL_IRDA_TxHalfCpltCallback(hirda);
01441 }
01442
01443 /**
01444   * @brief DMA IRDA Rx Transfer completed callback
01445   * @param hdma: DMA handle
01446   * @retval None
01447   */
01448 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01449 {
01450   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01451
01452   /* DMA Normal mode */
01453   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01454   {
01455     hirda->RxXferCount = 0;
01456
01457     /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01458        in the IRDA CR3 register */
01459     hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
01460
01461     if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
01462     {
01463       hirda->State = HAL_IRDA_STATE_BUSY_TX;
01464     }
01465     else
01466     {
01467       hirda->State = HAL_IRDA_STATE_READY;
01468     }
01469   }
01470
01471   HAL_IRDA_RxCpltCallback(hirda);
01472 }
01473
01474 /**
01475   * @brief DMA IRDA receive process half complete callback
01476   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01477   *                the configuration information for the specified DMA module.
01478   * @retval None
01479   */
01480 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
01481 {
01482   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01483
01484   HAL_IRDA_RxHalfCpltCallback(hirda);
01485 }
01486
01487 /**
01488   * @brief DMA IRDA communication error callback
01489   * @param hdma: DMA handle
01490   * @retval None
01491   */
01492 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
01493 {
01494   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01495   hirda->RxXferCount = 0;
01496   hirda->TxXferCount = 0;
01497   hirda->State= HAL_IRDA_STATE_READY;
01498   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
01499   HAL_IRDA_ErrorCallback(hirda);
01500 }
01501
01502 /**
01503   * @}
01504   */
01505
01506 /**
01507   * @}
01508   */
01509
01510 #endif /* HAL_IRDA_MODULE_ENABLED */
01511
01512 /**
01513   * @}
01514   */
01515
01516 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01517
Generated on Fri Nov 13 2015 11:37:25 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_irda.h Source File

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stm32f7xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of IRDA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_IRDA_H
00040 #define __STM32F7xx_HAL_IRDA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief IRDA Init Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00067                                            The baud rate register is computed using the following formula:
00068                                               Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
00069
00070   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00071                                            This parameter can be a value of @ref IRDAEx_Word_Length */
00072
00073   uint32_t Parity;                    /*!< Specifies the parity mode.
00074                                            This parameter can be a value of @ref IRDA_Parity
00075                                            @note When parity is enabled, the computed parity is inserted
00076                                                  at the MSB position of the transmitted data (9th bit when
00077                                                  the word length is set to 9 data bits; 8th bit when the
00078                                                  word length is set to 8 data bits). */
00079
00080   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00081                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00082
00083   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00084                                            to achieve low-power frequency.
00085                                            @note Prescaler value 0 is forbidden */
00086
00087   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00088                                            This parameter can be a value of @ref IRDA_Low_Power */
00089 }IRDA_InitTypeDef;
00090
00091 /**
00092   * @brief HAL State structures definition
00093   */
00094 typedef enum
00095 {
00096   HAL_IRDA_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
00097   HAL_IRDA_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
00098   HAL_IRDA_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing */
00099   HAL_IRDA_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
00100   HAL_IRDA_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
00101   HAL_IRDA_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00102   HAL_IRDA_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
00103   HAL_IRDA_STATE_ERROR             = 0x04     /*!< Error */
00104 }HAL_IRDA_StateTypeDef;
00105
00106 /**
00107   * @brief IRDA clock sources definition
00108   */
00109 typedef enum
00110 {
00111   IRDA_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source  */
00112   IRDA_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source  */
00113   IRDA_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source    */
00114   IRDA_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source */
00115   IRDA_CLOCKSOURCE_LSE        = 0x08     /*!< LSE clock source     */
00116 }IRDA_ClockSourceTypeDef;
00117
00118 /**
00119   * @brief  IRDA handle Structure definition
00120   */
00121 typedef struct
00122 {
00123   USART_TypeDef            *Instance;        /* IRDA registers base address        */
00124
00125   IRDA_InitTypeDef         Init;             /* IRDA communication parameters      */
00126
00127   uint8_t                  *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */
00128
00129   uint16_t                 TxXferSize;       /* IRDA Tx Transfer size              */
00130
00131   uint16_t                 TxXferCount;      /* IRDA Tx Transfer Counter           */
00132
00133   uint8_t                  *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */
00134
00135   uint16_t                 RxXferSize;       /* IRDA Rx Transfer size              */
00136
00137   uint16_t                 RxXferCount;      /* IRDA Rx Transfer Counter           */
00138
00139   uint16_t                 Mask;             /* IRDA RX RDR register mask         */
00140
00141   DMA_HandleTypeDef        *hdmatx;          /* IRDA Tx DMA Handle parameters      */
00142
00143   DMA_HandleTypeDef        *hdmarx;          /* IRDA Rx DMA Handle parameters      */
00144
00145   HAL_LockTypeDef          Lock;             /* Locking object                     */
00146
00147   __IO HAL_IRDA_StateTypeDef    State;       /* IRDA communication state           */
00148
00149   __IO uint32_t    ErrorCode;   /* IRDA Error code                    */
00150
00151 }IRDA_HandleTypeDef;
00152
00153 /**
00154   * @}
00155   */
00156
00157 /**
00158   * @brief  IRDA Configuration enumeration values definition
00159   */
00160
00161 /* Exported constants --------------------------------------------------------*/
00162 /** @defgroup IRDA_Exported_Constants IRDA Exported constants
00163   * @{
00164   */
00165 /** @defgroup IRDA_Error_Code IRDA Error Code
00166   * @brief    IRDA Error Code
00167   * @{
00168   */
00169
00170 #define HAL_IRDA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error            */
00171 #define HAL_IRDA_ERROR_PE        ((uint32_t)0x00000001)    /*!< Parity error        */
00172 #define HAL_IRDA_ERROR_NE        ((uint32_t)0x00000002)    /*!< Noise error         */
00173 #define HAL_IRDA_ERROR_FE        ((uint32_t)0x00000004)    /*!< frame error         */
00174 #define HAL_IRDA_ERROR_ORE       ((uint32_t)0x00000008)    /*!< Overrun error       */
00175 #define HAL_IRDA_ERROR_DMA       ((uint32_t)0x00000010)    /*!< DMA transfer error  */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup IRDA_Parity IRDA Parity
00181   * @{
00182   */
00183 #define IRDA_PARITY_NONE                    ((uint32_t)0x0000)
00184 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00185 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00186 /**
00187   * @}
00188   */
00189
00190
00191 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00192   * @{
00193   */
00194 #define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
00195 #define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
00196 #define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup IRDA_Low_Power IRDA Low Power
00202   * @{
00203   */
00204 #define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x0000)
00205 #define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
00206 /**
00207   * @}
00208   */
00209
00210  /** @defgroup IRDA_State IRDA State
00211   * @{
00212   */
00213 #define IRDA_STATE_DISABLE                  ((uint32_t)0x0000)
00214 #define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
00215 /**
00216   * @}
00217   */
00218
00219  /** @defgroup IRDA_Mode IRDA Mode
00220   * @{
00221   */
00222 #define IRDA_MODE_DISABLE                  ((uint32_t)0x0000)
00223 #define IRDA_MODE_ENABLE                   ((uint32_t)USART_CR3_IREN)
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup IRDA_One_Bit IRDA One Bit
00229   * @{
00230   */
00231 #define IRDA_ONE_BIT_SAMPLE_DISABLE          ((uint32_t)0x00000000)
00232 #define IRDA_ONE_BIT_SAMPLE_ENABLE           ((uint32_t)USART_CR3_ONEBIT)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00238   * @{
00239   */
00240 #define IRDA_DMA_TX_DISABLE          ((uint32_t)0x00000000)
00241 #define IRDA_DMA_TX_ENABLE           ((uint32_t)USART_CR3_DMAT)
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup IRDA_DMA_Rx IRDA DMA Rx
00247   * @{
00248   */
00249 #define IRDA_DMA_RX_DISABLE           ((uint32_t)0x0000)
00250 #define IRDA_DMA_RX_ENABLE            ((uint32_t)USART_CR3_DMAR)
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup IRDA_Flags IRDA Flags
00256   *        Elements values convention: 0xXXXX
00257   *           - 0xXXXX  : Flag mask in the ISR register
00258   * @{
00259   */
00260 #define IRDA_FLAG_REACK                     ((uint32_t)0x00400000)
00261 #define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000)
00262 #define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000)
00263 #define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000)
00264 #define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000)
00265 #define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)
00266 #define IRDA_FLAG_TC                        ((uint32_t)0x00000040)
00267 #define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)
00268 #define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)
00269 #define IRDA_FLAG_NE                        ((uint32_t)0x00000004)
00270 #define IRDA_FLAG_FE                        ((uint32_t)0x00000002)
00271 #define IRDA_FLAG_PE                        ((uint32_t)0x00000001)
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition
00277   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00278   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00279   *           - XX  : Interrupt source register (2bits)
00280   *                 - 01: CR1 register
00281   *                 - 10: CR2 register
00282   *                 - 11: CR3 register
00283   *           - ZZZZ  : Flag position in the ISR register(4bits)
00284   * @{
00285   */
00286 #define IRDA_IT_PE                          ((uint16_t)0x0028)
00287 #define IRDA_IT_TXE                         ((uint16_t)0x0727)
00288 #define IRDA_IT_TC                          ((uint16_t)0x0626)
00289 #define IRDA_IT_RXNE                        ((uint16_t)0x0525)
00290 #define IRDA_IT_IDLE                        ((uint16_t)0x0424)
00291
00292
00293
00294 /**       Elements values convention: 000000000XXYYYYYb
00295   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00296   *           - XX  : Interrupt source register (2bits)
00297   *                 - 01: CR1 register
00298   *                 - 10: CR2 register
00299   *                 - 11: CR3 register
00300   */
00301 #define IRDA_IT_ERR                         ((uint16_t)0x0060)
00302
00303 /**       Elements values convention: 0000ZZZZ00000000b
00304   *           - ZZZZ  : Flag position in the ISR register(4bits)
00305   */
00306 #define IRDA_IT_ORE                         ((uint16_t)0x0300)
00307 #define IRDA_IT_NE                          ((uint16_t)0x0200)
00308 #define IRDA_IT_FE                          ((uint16_t)0x0100)
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags
00314   * @{
00315   */
00316 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */
00317 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */
00318 #define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */
00319 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */
00320 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00321 /**
00322   * @}
00323   */
00324
00325
00326
00327 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00328   * @{
00329   */
00330 #define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */
00331 #define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */
00332 #define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338  * @}
00339  */
00340
00341
00342 /* Exported macro ------------------------------------------------------------*/
00343 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00344   * @{
00345   */
00346
00347 /** @brief Reset IRDA handle state
00348   * @param  __HANDLE__: specifies the IRDA Handle.
00349   *         The Handle Instance which can be USART1 or USART2.
00350   * @retval None
00351   */
00352 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
00353
00354 /** @brief  Check whether the specified IRDA flag is set or not.
00355   * @param  __HANDLE__: specifies the IRDA Handle.
00356   *         The Handle Instance which can be USART1 or USART2.
00357   *         UART peripheral
00358   * @param  __FLAG__: specifies the flag to check.
00359   *        This parameter can be one of the following values:
00360   *            @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
00361   *            @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
00362   *            @arg IRDA_FLAG_BUSY:  Busy flag
00363   *            @arg IRDA_FLAG_ABRF:  Auto Baud rate detection flag
00364   *            @arg IRDA_FLAG_ABRE:  Auto Baud rate detection error flag
00365   *            @arg IRDA_FLAG_TXE:   Transmit data register empty flag
00366   *            @arg IRDA_FLAG_TC:    Transmission Complete flag
00367   *            @arg IRDA_FLAG_RXNE:  Receive data register not empty flag
00368   *            @arg IRDA_FLAG_IDLE:  Idle Line detection flag
00369   *            @arg IRDA_FLAG_ORE:   OverRun Error flag
00370   *            @arg IRDA_FLAG_NE:    Noise Error flag
00371   *            @arg IRDA_FLAG_FE:    Framing Error flag
00372   *            @arg IRDA_FLAG_PE:    Parity Error flag
00373   * @retval The new state of __FLAG__ (TRUE or FALSE).
00374   */
00375 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00376
00377 /** @brief  Enable the specified IRDA interrupt.
00378   * @param  __HANDLE__: specifies the IRDA Handle.
00379   *         The Handle Instance which can be USART1 or USART2.
00380   *         UART peripheral
00381   * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
00382   *          This parameter can be one of the following values:
00383   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
00384   *            @arg IRDA_IT_TC:   Transmission complete interrupt
00385   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00386   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00387   *            @arg IRDA_IT_PE:   Parity Error interrupt
00388   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00389   * @retval None
00390   */
00391 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00392                                                           ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00393                                                           ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
00394
00395 /** @brief  Disable the specified IRDA interrupt.
00396   * @param  __HANDLE__: specifies the IRDA Handle.
00397   *         The Handle Instance which can be USART1 or USART2.
00398   * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
00399   *          This parameter can be one of the following values:
00400   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
00401   *            @arg IRDA_IT_TC:   Transmission complete interrupt
00402   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00403   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00404   *            @arg IRDA_IT_PE:   Parity Error interrupt
00405   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00406   * @retval None
00407   */
00408 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00409                                                            ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00410                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
00411
00412 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00413   * @param  __HANDLE__: specifies the IRDA Handle.
00414   *         The Handle Instance which can be USART1 or USART2.
00415   * @param  __IT__: specifies the IRDA interrupt source to check.
00416   *          This parameter can be one of the following values:
00417   *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
00418   *            @arg IRDA_IT_TC:  Transmission complete interrupt
00419   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00420   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00421   *            @arg IRDA_IT_ORE: OverRun Error interrupt
00422   *            @arg IRDA_IT_NE: Noise Error interrupt
00423   *            @arg IRDA_IT_FE: Framing Error interrupt
00424   *            @arg IRDA_IT_PE: Parity Error interrupt
00425   * @retval The new state of __IT__ (TRUE or FALSE).
00426   */
00427 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00428
00429 /** @brief  Check whether the specified IRDA interrupt source is enabled.
00430   * @param  __HANDLE__: specifies the IRDA Handle.
00431   *         The Handle Instance which can be USART1 or USART2.
00432   * @param  __IT__: specifies the IRDA interrupt source to check.
00433   *          This parameter can be one of the following values:
00434   *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
00435   *            @arg IRDA_IT_TC:  Transmission complete interrupt
00436   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00437   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00438   *            @arg IRDA_IT_ORE: OverRun Error interrupt
00439   *            @arg IRDA_IT_NE: Noise Error interrupt
00440   *            @arg IRDA_IT_FE: Framing Error interrupt
00441   *            @arg IRDA_IT_PE: Parity Error interrupt
00442   * @retval The new state of __IT__ (TRUE or FALSE).
00443   */
00444 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
00445                                                           (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
00446
00447 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00448   * @param  __HANDLE__: specifies the IRDA Handle.
00449   *         The Handle Instance which can be USART1 or USART2.
00450   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00451   *                       to clear the corresponding interrupt
00452   *          This parameter can be one of the following values:
00453   *            @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
00454   *            @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
00455   *            @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
00456   *            @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
00457   *            @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
00458   * @retval None
00459   */
00460 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
00461
00462 /** @brief  Set a specific IRDA request flag.
00463   * @param  __HANDLE__: specifies the IRDA Handle.
00464   *         The Handle Instance which can be USART1 or USART2.
00465   * @param  __REQ__: specifies the request flag to set
00466   *          This parameter can be one of the following values:
00467   *            @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
00468   *            @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
00469   *            @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
00470   *
00471   * @retval None
00472   */
00473 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00474
00475 /** @brief  Enable UART/USART associated to IRDA Handle
00476   * @param  __HANDLE__: specifies the IRDA Handle.
00477   *         The Handle Instance which can be USART1 or USART2.
00478   * @retval None
00479   */
00480 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00481
00482 /** @brief  Disable UART/USART associated to IRDA Handle
00483   * @param  __HANDLE__: specifies the IRDA Handle.
00484   *         The Handle Instance which can be USART1 or USART2.
00485   * @retval None
00486   */
00487 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00488
00489 /**
00490   * @}
00491   */
00492
00493 /* Include IRDA HAL Extension module */
00494 #include "stm32f7xx_hal_irda_ex.h"
00495
00496 /* Exported functions --------------------------------------------------------*/
00497 /** @addtogroup IRDA_Exported_Functions IrDA Exported Functions
00498   * @{
00499   */
00500
00501 /** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
00502   * @{
00503   */
00504
00505 /* Initialization and de-initialization functions  ****************************/
00506 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00507 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00508 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00509 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00510 /**
00511   * @}
00512   */
00513
00514 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00515   * @{
00516   */
00517
00518 /* IO operation functions *****************************************************/
00519 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00520 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00521 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00522 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00523 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00524 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00525 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00526 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00527 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00528 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00529 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00530 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00531 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00532 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00533 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00534 /**
00535  * @}
00536  */
00537
00538 /** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions
00539  * @{
00540  */
00541 /* Peripheral State methods  **************************************************/
00542 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00543 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00544 /**
00545   * @}
00546   */
00547
00548 /**
00549   * @}
00550   */
00551
00552 /* Private types -------------------------------------------------------------*/
00553 /* Private variables ---------------------------------------------------------*/
00554 /* Private constants ---------------------------------------------------------*/
00555 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00556   * @{
00557   */
00558
00559 /** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask
00560   * @{
00561   */
00562 #define IRDA_IT_MASK  ((uint16_t)0x001F)
00563 /**
00564   * @}
00565   */
00566 /**
00567   * @}
00568   */
00569
00570 /* Private macros --------------------------------------------------------*/
00571 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
00572   * @{
00573   */
00574
00575 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value
00576   * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
00577   * @retval True or False
00578   */
00579 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
00580
00581 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0
00582   * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
00583   * @retval True or False
00584   */
00585 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
00586
00587 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00588                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00589                                     ((__PARITY__) == IRDA_PARITY_ODD))
00590
00591 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
00592
00593 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00594                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00595
00596 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00597                                   ((__STATE__) == IRDA_STATE_ENABLE))
00598
00599 #define IS_IRDA_MODE(__STATE__)  (((__STATE__) == IRDA_MODE_DISABLE) || \
00600                                   ((__STATE__) == IRDA_MODE_ENABLE))
00601
00602 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)     (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00603                                                ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00604
00605 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00606                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00607
00608 #define IS_IRDA_DMA_RX(__DMARX__)     (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00609                                        ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00610
00611 #define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
00612                                           ((PARAM) == IRDA_SENDBREAK_REQUEST) || \
00613                                           ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
00614                                           ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
00615                                           ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
00616 /**
00617  * @}
00618  */
00619
00620 /* Private functions ---------------------------------------------------------*/
00621 /** @defgroup IRDA_Private_Functions IRDA Private Functions
00622   * @{
00623   */
00624
00625 /**
00626   * @}
00627   */
00628
00629 /**
00630   * @}
00631   */
00632
00633 /**
00634   * @}
00635   */
00636
00637 #ifdef __cplusplus
00638 }
00639 #endif
00640
00641 #endif /* __STM32F7xx_HAL_IRDA_H */
00642
00643 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_irda_ex.h Source File

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stm32f7xx_hal_irda_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of IRDA HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_IRDA_EX_H
00040 #define __STM32F7xx_HAL_IRDA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup IRDAEx_Word_Length IRDAEx Word Length
00064   * @{
00065   */
00066 #define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)
00067 #define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
00068 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)
00069 /**
00070   * @}
00071   */
00072
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported macro ------------------------------------------------------------*/
00079
00080 /* Private macros ------------------------------------------------------------*/
00081
00082 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00083   * @{
00084   */
00085 /** @brief  Reports the IRDA clock source.
00086   * @param  __HANDLE__: specifies the IRDA Handle
00087   * @param  __CLOCKSOURCE__ : output variable
00088   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00089   */
00090 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00091   do {                                                        \
00092     if((__HANDLE__)->Instance == USART1)                      \
00093     {                                                         \
00094        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00095        {                                                      \
00096         case RCC_USART1CLKSOURCE_PCLK2:                       \
00097           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00098           break;                                              \
00099         case RCC_USART1CLKSOURCE_HSI:                         \
00100           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00101           break;                                              \
00102         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00103           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00104           break;                                              \
00105         case RCC_USART1CLKSOURCE_LSE:                         \
00106           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00107           break;                                              \
00108         default:                                              \
00109           break;                                              \
00110        }                                                      \
00111     }                                                         \
00112     else if((__HANDLE__)->Instance == USART2)                 \
00113     {                                                         \
00114        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00115        {                                                      \
00116         case RCC_USART2CLKSOURCE_PCLK1:                       \
00117           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00118           break;                                              \
00119         case RCC_USART2CLKSOURCE_HSI:                         \
00120           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00121           break;                                              \
00122         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00123           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00124           break;                                              \
00125         case RCC_USART2CLKSOURCE_LSE:                         \
00126           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00127           break;                                              \
00128         default:                                              \
00129           break;                                              \
00130        }                                                      \
00131     }                                                         \
00132     else if((__HANDLE__)->Instance == USART3)                 \
00133     {                                                         \
00134        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00135        {                                                      \
00136         case RCC_USART3CLKSOURCE_PCLK1:                       \
00137           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00138           break;                                              \
00139         case RCC_USART3CLKSOURCE_HSI:                         \
00140           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00141           break;                                              \
00142         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00143           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00144           break;                                              \
00145         case RCC_USART3CLKSOURCE_LSE:                         \
00146           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00147           break;                                              \
00148         default:                                              \
00149           break;                                              \
00150        }                                                      \
00151     }                                                         \
00152     else if((__HANDLE__)->Instance == USART6)                 \
00153     {                                                         \
00154        switch(__HAL_RCC_GET_USART6_SOURCE())                  \
00155        {                                                      \
00156         case RCC_USART6CLKSOURCE_PCLK2:                       \
00157           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00158           break;                                              \
00159         case RCC_USART6CLKSOURCE_HSI:                         \
00160           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00161           break;                                              \
00162         case RCC_USART6CLKSOURCE_SYSCLK:                      \
00163           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00164           break;                                              \
00165         case RCC_USART6CLKSOURCE_LSE:                         \
00166           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00167           break;                                              \
00168         default:                                              \
00169           break;                                              \
00170        }                                                      \
00171     }                                                         \
00172         } while(0)
00173
00174 /** @brief  Reports the mask to apply to retrieve the received data
00175   *         according to the word length and to the parity bits activation.
00176   * @param  __HANDLE__: specifies the IRDA Handle
00177   * @retval mask to apply to USART RDR register value.
00178   */
00179 #define IRDA_MASK_COMPUTATION(__HANDLE__)                       \
00180   do {                                                                \
00181   if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
00182   {                                                                   \
00183      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00184      {                                                                \
00185         (__HANDLE__)->Mask = 0x01FF ;                                 \
00186      }                                                                \
00187      else                                                             \
00188      {                                                                \
00189         (__HANDLE__)->Mask = 0x00FF ;                                 \
00190      }                                                                \
00191   }                                                                   \
00192   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
00193   {                                                                   \
00194      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00195      {                                                                \
00196         (__HANDLE__)->Mask = 0x00FF ;                                 \
00197      }                                                                \
00198      else                                                             \
00199      {                                                                \
00200         (__HANDLE__)->Mask = 0x007F ;                                 \
00201      }                                                                \
00202   }                                                                   \
00203   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
00204   {                                                                   \
00205      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00206      {                                                                \
00207         (__HANDLE__)->Mask = 0x007F ;                                 \
00208      }                                                                \
00209      else                                                             \
00210      {                                                                \
00211         (__HANDLE__)->Mask = 0x003F ;                                 \
00212      }                                                                \
00213   }                                                                   \
00214 } while(0)
00215
00216 #define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
00217                                      ((LENGTH) == IRDA_WORDLENGTH_8B) || \
00218                                      ((LENGTH) == IRDA_WORDLENGTH_9B))
00219 /**
00220   * @}
00221   */
00222
00223 /* Exported functions --------------------------------------------------------*/
00224
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 #ifdef __cplusplus
00234 }
00235 #endif
00236
00237 #endif /* __STM32F7xx_HAL_IRDA_EX_H */
00238
00239 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_iwdg.c Source File

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stm32f7xx_hal_iwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   IWDG HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### IWDG Generic features #####
00018   ==============================================================================
00019     [..]
00020     (+) The IWDG can be started by either software or hardware (configurable
00021          through option byte).
00022
00023     (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
00024          thus stays active even if the main clock fails.
00025          Once the IWDG is started, the LSI is forced ON and cannot be disabled
00026          (LSI cannot be disabled too), and the counter starts counting down from
00027          the reset value of 0xFFF. When it reaches the end of count value (0x000)
00028          a system reset is generated.
00029
00030     (+) The IWDG counter should be refreshed at regular intervals, otherwise the
00031          watchdog generates an MCU reset when the counter reaches 0.
00032
00033     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00034          in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00035          IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00036          reset occurs.
00037
00038     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00039          The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
00040          devices provide the capability to measure the LSI frequency (LSI clock
00041          connected internally to TIM16 CH1 input capture). The measured value
00042          can be used to have an IWDG timeout with an acceptable accuracy.
00043
00044
00045                      ##### How to use this driver #####
00046   ==============================================================================
00047     [..]
00048     If Window option is disabled
00049
00050       (+) Use IWDG using HAL_IWDG_Init() function to :
00051          (++) Enable write access to IWDG_PR, IWDG_RLR.
00052          (++) Configure the IWDG prescaler, counter reload value.
00053               This reload value will be loaded in the IWDG counter each time the counter
00054               is reloaded, then the IWDG will start counting down from this value.
00055       (+) Use IWDG using HAL_IWDG_Start() function to :
00056          (++) Reload IWDG counter with value defined in the IWDG_RLR register.
00057          (++) Start the IWDG, when the IWDG is used in software mode (no need
00058               to enable the LSI, it will be enabled by hardware).
00059       (+) Then the application program must refresh the IWDG counter at regular
00060           intervals during normal operation to prevent an MCU reset, using
00061           HAL_IWDG_Refresh() function.
00062     [..]
00063     if Window option is enabled:
00064
00065       (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
00066       (+) Use IWDG using HAL_IWDG_Init() function to :
00067          (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00068          (++) Configure the IWDG prescaler, reload value and window value.
00069       (+) Then the application program must refresh the IWDG counter at regular
00070           intervals during normal operation to prevent an MCU reset, using
00071           HAL_IWDG_Refresh() function.
00072
00073      *** IWDG HAL driver macros list ***
00074      ====================================
00075      [..]
00076        Below the list of most used macros in IWDG HAL driver.
00077
00078       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00079       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
00080       (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
00081       (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
00082       (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
00083
00084   @endverbatim
00085   ******************************************************************************
00086   * @attention
00087   *
00088   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00089   *
00090   * Redistribution and use in source and binary forms, with or without modification,
00091   * are permitted provided that the following conditions are met:
00092   *   1. Redistributions of source code must retain the above copyright notice,
00093   *      this list of conditions and the following disclaimer.
00094   *   2. Redistributions in binary form must reproduce the above copyright notice,
00095   *      this list of conditions and the following disclaimer in the documentation
00096   *      and/or other materials provided with the distribution.
00097   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00098   *      may be used to endorse or promote products derived from this software
00099   *      without specific prior written permission.
00100   *
00101   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00102   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00103   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00104   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00105   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00106   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00107   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00108   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00109   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00110   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00111   *
00112   ******************************************************************************
00113   */
00114
00115 /* Includes ------------------------------------------------------------------*/
00116 #include "stm32f7xx_hal.h"
00117
00118 /** @addtogroup STM32F7xx_HAL_Driver
00119   * @{
00120   */
00121
00122 /** @defgroup IWDG IWDG HAL module driver
00123   * @brief IWDG HAL module driver.
00124   * @{
00125   */
00126
00127 #ifdef HAL_IWDG_MODULE_ENABLED
00128
00129 /* Private typedef -----------------------------------------------------------*/
00130 /* Private define ------------------------------------------------------------*/
00131 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00132   * @{
00133   */
00134
00135 #define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
00136
00137 /**
00138   * @}
00139   */
00140 /* Private macro -------------------------------------------------------------*/
00141 /* Private variables ---------------------------------------------------------*/
00142 /* Private function prototypes -----------------------------------------------*/
00143 /* Exported functions --------------------------------------------------------*/
00144
00145 /** @defgroup IWDG_Exported_Functions IWDG Exported Functions
00146   * @{
00147   */
00148
00149 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
00150  *  @brief    Initialization and Configuration functions.
00151  *
00152 @verbatim
00153  ===============================================================================
00154           ##### Initialization and de-initialization functions #####
00155  ===============================================================================
00156     [..]  This section provides functions allowing to:
00157       (+) Initialize the IWDG according to the specified parameters
00158           in the IWDG_InitTypeDef and create the associated handle
00159       (+) Manage Window option
00160       (+) Initialize the IWDG MSP
00161       (+) DeInitialize IWDG MSP
00162
00163 @endverbatim
00164   * @{
00165   */
00166
00167 /**
00168   * @brief  Initializes the IWDG according to the specified
00169   *         parameters in the IWDG_InitTypeDef and creates the associated handle.
00170   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00171   *                the configuration information for the specified IWDG module.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00175 {
00176   uint32_t tickstart = 0;
00177
00178   /* Check the IWDG handle allocation */
00179   if(hiwdg == NULL)
00180   {
00181     return HAL_ERROR;
00182   }
00183
00184   /* Check the parameters */
00185   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00186   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00187   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00188
00189   /* Check pending flag, if previous update not done, return error */
00190   if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
00191      &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
00192      &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET))
00193   {
00194     return HAL_ERROR;
00195   }
00196
00197   if(hiwdg->State == HAL_IWDG_STATE_RESET)
00198   {
00199     /* Allocate lock resource and initialize it */
00200     hiwdg->Lock = HAL_UNLOCKED;
00201
00202     /* Init the low level hardware */
00203     HAL_IWDG_MspInit(hiwdg);
00204   }
00205
00206   /* Change IWDG peripheral state */
00207   hiwdg->State = HAL_IWDG_STATE_BUSY;
00208
00209   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
00210   /* by writing 0x00005555 in KR */
00211   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00212
00213   /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
00214   MODIFY_REG(hiwdg->Instance->PR, (uint32_t)IWDG_PR_PR, hiwdg->Init.Prescaler);
00215   MODIFY_REG(hiwdg->Instance->RLR, (uint32_t)IWDG_RLR_RL, hiwdg->Init.Reload);
00216
00217   /* check if window option is enabled */
00218   if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
00219   {
00220     tickstart = HAL_GetTick();
00221
00222      /* Wait for register to be updated */
00223     while((uint32_t)(hiwdg->Instance->SR) != RESET)
00224     {
00225       if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
00226       {
00227         /* Set IWDG state */
00228         hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
00229         return HAL_TIMEOUT;
00230       }
00231     }
00232
00233     /* Write to IWDG WINR the IWDG_Window value to compare with */
00234     MODIFY_REG(hiwdg->Instance->WINR, (uint32_t)IWDG_WINR_WIN, hiwdg->Init.Window);
00235   }
00236
00237   /* Change IWDG peripheral state */
00238   hiwdg->State = HAL_IWDG_STATE_READY;
00239
00240   /* Return function status */
00241   return HAL_OK;
00242 }
00243
00244 /**
00245   * @brief  Initializes the IWDG MSP.
00246   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00247   *                the configuration information for the specified IWDG module.
00248   * @retval None
00249   */
00250 __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hiwdg);
00254
00255   /* NOTE : This function should not be modified, when the callback is needed,
00256             the HAL_IWDG_MspInit could be implemented in the user file
00257    */
00258 }
00259
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00265  *  @brief   IO operation functions
00266  *
00267 @verbatim
00268  ===============================================================================
00269                       ##### IO operation functions #####
00270  ===============================================================================
00271     [..]  This section provides functions allowing to:
00272       (+) Start the IWDG.
00273       (+) Refresh the IWDG.
00274
00275 @endverbatim
00276   * @{
00277   */
00278
00279 /**
00280   * @brief  Starts the IWDG.
00281   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00282   *                the configuration information for the specified IWDG module.
00283   * @retval HAL status
00284   */
00285 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
00286 {
00287   uint32_t tickstart = 0;
00288
00289   /* Process locked */
00290   __HAL_LOCK(hiwdg);
00291
00292     /* Change IWDG peripheral state */
00293   hiwdg->State = HAL_IWDG_STATE_BUSY;
00294
00295   /* Reload IWDG counter with value defined in the RLR register */
00296   if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
00297   {
00298     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00299   }
00300
00301   /* Start the IWDG peripheral */
00302   __HAL_IWDG_START(hiwdg);
00303
00304   tickstart = HAL_GetTick();
00305
00306   /* Wait until PVU, RVU, WVU flag are RESET */
00307   while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
00308          &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
00309          &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )
00310   {
00311
00312     if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
00313     {
00314       /* Set IWDG state */
00315       hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
00316
00317       /* Process unlocked */
00318       __HAL_UNLOCK(hiwdg);
00319
00320       return HAL_TIMEOUT;
00321     }
00322   }
00323
00324   /* Change IWDG peripheral state */
00325   hiwdg->State = HAL_IWDG_STATE_READY;
00326
00327   /* Process Unlocked */
00328   __HAL_UNLOCK(hiwdg);
00329
00330   /* Return function status */
00331   return HAL_OK;
00332 }
00333
00334 /**
00335   * @brief  Refreshes the IWDG.
00336   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00337   *                the configuration information for the specified IWDG module.
00338   * @retval HAL status
00339   */
00340 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00341 {
00342   uint32_t tickstart = 0;
00343
00344   /* Process Locked */
00345   __HAL_LOCK(hiwdg);
00346
00347     /* Change IWDG peripheral state */
00348   hiwdg->State = HAL_IWDG_STATE_BUSY;
00349
00350   tickstart = HAL_GetTick();
00351
00352   /* Wait until RVU flag is RESET */
00353   while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
00354   {
00355     if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
00356     {
00357       /* Set IWDG state */
00358       hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
00359
00360        /* Process unlocked */
00361       __HAL_UNLOCK(hiwdg);
00362
00363       return HAL_TIMEOUT;
00364     }
00365   }
00366
00367   /* Reload IWDG counter with value defined in the reload register */
00368   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00369
00370   /* Change IWDG peripheral state */
00371   hiwdg->State = HAL_IWDG_STATE_READY;
00372
00373   /* Process Unlocked */
00374   __HAL_UNLOCK(hiwdg);
00375
00376   /* Return function status */
00377   return HAL_OK;
00378 }
00379
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
00385  *  @brief    Peripheral State functions.
00386  *
00387 @verbatim
00388  ===============================================================================
00389                       ##### Peripheral State functions #####
00390  ===============================================================================
00391     [..]
00392     This subsection permits to get in run-time the status of the peripheral.
00393
00394 @endverbatim
00395   * @{
00396   */
00397
00398 /**
00399   * @brief  Returns the IWDG state.
00400   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00401   *                the configuration information for the specified IWDG module.
00402   * @retval HAL state
00403   */
00404 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
00405 {
00406   return hiwdg->State;
00407 }
00408
00409 /**
00410   * @}
00411   */
00412
00413 /**
00414   * @}
00415   */
00416
00417 #endif /* HAL_IWDG_MODULE_ENABLED */
00418 /**
00419   * @}
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_iwdg.h Source File

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stm32f7xx_hal_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of IWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_IWDG_H
00040 #define __STM32F7xx_HAL_IWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  IWDG HAL State Structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_IWDG_STATE_RESET     = 0x00,  /*!< IWDG not yet initialized or disabled */
00068   HAL_IWDG_STATE_READY     = 0x01,  /*!< IWDG initialized and ready for use   */
00069   HAL_IWDG_STATE_BUSY      = 0x02,  /*!< IWDG internal process is ongoing     */
00070   HAL_IWDG_STATE_TIMEOUT   = 0x03,  /*!< IWDG timeout state                   */
00071   HAL_IWDG_STATE_ERROR     = 0x04   /*!< IWDG error state                     */
00072
00073 }HAL_IWDG_StateTypeDef;
00074
00075 /**
00076   * @brief  IWDG Init structure definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00081                             This parameter can be a value of @ref IWDG_Prescaler */
00082
00083   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00084                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00085
00086   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00087                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00088
00089 } IWDG_InitTypeDef;
00090
00091 /**
00092   * @brief  IWDG Handle Structure definition
00093   */
00094 typedef struct
00095 {
00096   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00097
00098   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00099
00100   HAL_LockTypeDef              Lock;      /*!< IWDG Locking object      */
00101
00102   __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
00103
00104 }IWDG_HandleTypeDef;
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported constants --------------------------------------------------------*/
00111 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00112   * @{
00113   */
00114
00115 /** @defgroup IWDG_Prescaler IWDG Prescaler
00116   * @{
00117   */
00118 #define IWDG_PRESCALER_4                ((uint8_t)0x00)                            /*!< IWDG prescaler set to 4   */
00119 #define IWDG_PRESCALER_8                ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
00120 #define IWDG_PRESCALER_16               ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
00121 #define IWDG_PRESCALER_32               ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
00122 #define IWDG_PRESCALER_64               ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
00123 #define IWDG_PRESCALER_128              ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
00124 #define IWDG_PRESCALER_256              ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup IWDG_Window IWDG Window
00130   * @{
00131   */
00132 #define IWDG_WINDOW_DISABLE             ((uint32_t)0x00000FFF)
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported macros -----------------------------------------------------------*/
00142 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00143   * @{
00144   */
00145
00146 /** @brief Reset IWDG handle state
00147   * @param  __HANDLE__: IWDG handle.
00148   * @retval None
00149   */
00150 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__)   ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
00151
00152 /**
00153   * @brief  Enables the IWDG peripheral.
00154   * @param  __HANDLE__: IWDG handle
00155   * @retval None
00156   */
00157 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00158
00159 /**
00160   * @brief  Reloads IWDG counter with value defined in the reload register
00161   *         (write access to IWDG_PR and IWDG_RLR registers disabled).
00162   * @param  __HANDLE__: IWDG handle
00163   * @retval None
00164   */
00165 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00166
00167 /**
00168   * @brief  Gets the selected IWDG's flag status.
00169   * @param  __HANDLE__: IWDG handle
00170   * @param  __FLAG__: specifies the flag to check.
00171   *         This parameter can be one of the following values:
00172   *            @arg IWDG_FLAG_PVU:  Watchdog counter reload value update flag
00173   *            @arg IWDG_FLAG_RVU:  Watchdog counter prescaler value flag
00174   *            @arg IWDG_FLAG_WVU:  Watchdog counter window value flag
00175   * @retval The new state of __FLAG__ (TRUE or FALSE) .
00176   */
00177 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__)   (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported functions --------------------------------------------------------*/
00184 /** @addtogroup IWDG_Exported_Functions
00185   * @{
00186   */
00187
00188 /** @addtogroup IWDG_Exported_Functions_Group1
00189   * @{
00190   */
00191 /* Initialization/de-initialization functions  ********************************/
00192 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00193 void              HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
00194 /**
00195   * @}
00196   */
00197
00198 /** @addtogroup IWDG_Exported_Functions_Group2
00199   * @{
00200   */
00201 /* I/O operation functions ****************************************************/
00202 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
00203 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00204 /**
00205   * @}
00206   */
00207
00208 /** @addtogroup IWDG_Exported_Functions_Group3
00209   * @{
00210   */
00211 /* Peripheral State functions  ************************************************/
00212 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
00213 /**
00214   * @}
00215   */
00216
00217 /**
00218   * @}
00219   */
00220
00221 /* Private constants ---------------------------------------------------------*/
00222 /** @addtogroup IWDG_Private_Defines
00223   * @{
00224   */
00225 /**
00226   * @brief  IWDG Key Register BitMask
00227   */
00228 #define IWDG_KEY_RELOAD                 ((uint32_t)0x0000AAAA)  /*!< IWDG Reload Counter Enable   */
00229 #define IWDG_KEY_ENABLE                 ((uint32_t)0x0000CCCC)  /*!< IWDG Peripheral Enable       */
00230 #define IWDG_KEY_WRITE_ACCESS_ENABLE    ((uint32_t)0x00005555)  /*!< IWDG KR Write Access Enable  */
00231 #define IWDG_KEY_WRITE_ACCESS_DISABLE   ((uint32_t)0x00000000)  /*!< IWDG KR Write Access Disable */
00232
00233 /**
00234   * @brief  IWDG Flag definition
00235   */
00236 #define IWDG_FLAG_PVU                   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update flag */
00237 #define IWDG_FLAG_RVU                   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update flag    */
00238 #define IWDG_FLAG_WVU                   ((uint32_t)IWDG_SR_WVU)  /*!< Watchdog counter window value update flag    */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /* Private macros ------------------------------------------------------------*/
00245 /** @defgroup IWDG_Private_Macro IWDG Private Macros
00246   * @{
00247   */
00248 /**
00249   * @brief  Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00250   * @param  __HANDLE__: IWDG handle
00251   * @retval None
00252   */
00253 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00254
00255 /**
00256   * @brief  Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00257   * @param  __HANDLE__: IWDG handle
00258   * @retval None
00259   */
00260 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00261
00262 /**
00263   * @brief  Check IWDG prescaler value.
00264   * @param  __PRESCALER__: IWDG prescaler value
00265   * @retval None
00266   */
00267 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00268                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00269                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00270                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00271                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00272                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00273                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00274
00275 /**
00276   * @brief  Check IWDG reload value.
00277   * @param  __RELOAD__: IWDG reload value
00278   * @retval None
00279   */
00280 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= 0xFFF)
00281
00282 /**
00283   * @brief  Check IWDG window value.
00284   * @param  __WINDOW__: IWDG window value
00285   * @retval None
00286   */
00287 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= 0xFFF)
00288
00289 /**
00290   * @}
00291   */
00292
00293 /**
00294   * @}
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301
00302 #ifdef __cplusplus
00303 }
00304 #endif
00305
00306 #endif /* __STM32F7xx_HAL_IWDG_H */
00307
00308 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_lptim.c Source File

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stm32f7xx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   LPTIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00010   *           + Initialization and de-initialization functions.
00011   *           + Start/Stop operation functions in polling mode.
00012   *           + Start/Stop operation functions in interrupt mode.
00013   *           + Reading operation functions.
00014   *           + Peripheral State functions.
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021       The LPTIM HAL driver can be used as follows:
00022
00023       (#)Initialize the LPTIM low level resources by implementing the
00024         HAL_LPTIM_MspInit():
00025          (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
00026          (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00027              (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00028              (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00029              (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00030
00031       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00032          configures mainly:
00033          (##) The instance: LPTIM1.
00034          (##) Clock: the counter clock.
00035                  - Source   : it can be either the ULPTIM input (IN1) or one of
00036                               the internal clock; (APB, LSE, LSI or MSI).
00037                  - Prescaler: select the clock divider.
00038          (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00039                as counter clock source.
00040                  - Polarity:   polarity of the active edge for the counter unit
00041                                if the ULPTIM input is selected.
00042                  - SampleTime: clock sampling time to configure the clock glitch
00043                                filter.
00044          (##) Trigger: How the counter start.
00045                  - Source: trigger can be software or one of the hardware triggers.
00046                  - ActiveEdge : only for hardware trigger.
00047                  - SampleTime : trigger sampling time to configure the trigger
00048                                 glitch filter.
00049          (##) OutputPolarity : 2 opposite polarities are possibles.
00050          (##) UpdateMode: specifies whether the update of the autoreload and
00051               the compare values is done immediately or after the end of current
00052               period.
00053
00054       (#)Six modes are available:
00055
00056          (##) PWM Mode: To generate a PWM signal with specified period and pulse,
00057          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00058          mode.
00059
00060          (##) One Pulse Mode: To generate pulse with specified width in response
00061          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00062          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00063
00064          (##) Set once Mode: In this mode, the output changes the level (from
00065          low level to high level if the output polarity is configured high, else
00066          the opposite) when a compare match occurs. To start this mode, call
00067          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00068          interruption mode.
00069
00070          (##) Encoder Mode: To use the encoder interface call
00071          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00072          interruption mode.
00073
00074          (##) Time out Mode: an active edge on one selected trigger input rests
00075          the counter. The first trigger event will start the timer, any
00076          successive trigger event will reset the counter and the timer will
00077          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00078          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00079
00080          (##) Counter Mode: counter can be used to count external events on
00081          the LPTIM Input1 or it can be used to count internal clock cycles.
00082          To start this mode, call HAL_LPTIM_Counter_Start() or
00083          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00084
00085
00086       (#) User can stop any process by calling the corresponding API:
00087           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00088           already started in interruption mode.
00089
00090        (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
00091
00092   @endverbatim
00093   ******************************************************************************
00094   * @attention
00095   *
00096   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00097   *
00098   * Redistribution and use in source and binary forms, with or without modification,
00099   * are permitted provided that the following conditions are met:
00100   *   1. Redistributions of source code must retain the above copyright notice,
00101   *      this list of conditions and the following disclaimer.
00102   *   2. Redistributions in binary form must reproduce the above copyright notice,
00103   *      this list of conditions and the following disclaimer in the documentation
00104   *      and/or other materials provided with the distribution.
00105   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00106   *      may be used to endorse or promote products derived from this software
00107   *      without specific prior written permission.
00108   *
00109   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00110   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00111   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00112   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00113   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00114   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00115   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00116   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00117   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00118   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00119   *
00120   ******************************************************************************
00121   */
00122
00123 /* Includes ------------------------------------------------------------------*/
00124 #include "stm32f7xx_hal.h"
00125
00126 /** @addtogroup STM32F7xx_HAL_Driver
00127   * @{
00128   */
00129
00130 /** @defgroup LPTIM LPTIM
00131   * @brief LPTIM HAL module driver.
00132   * @{
00133   */
00134
00135 #ifdef HAL_LPTIM_MODULE_ENABLED
00136 /* Private types -------------------------------------------------------------*/
00137 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00138   * @{
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /* Private defines -----------------------------------------------------------*/
00146 /** @defgroup LPTIM_Private_Defines LPTIM Private Defines
00147   * @{
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Private variables ---------------------------------------------------------*/
00155 /** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
00156   * @{
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /* Private constants ---------------------------------------------------------*/
00164 /** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
00165   * @{
00166   */
00167
00168 /**
00169   * @}
00170   */
00171
00172 /* Private macros ------------------------------------------------------------*/
00173 /** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
00174   * @{
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /* Private function prototypes -----------------------------------------------*/
00182 /** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
00183   * @{
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Private functions ---------------------------------------------------------*/
00191 /** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
00192   * @{
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported functions ---------------------------------------------------------*/
00200 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00201   * @{
00202   */
00203
00204 /** @defgroup LPTIM_Group1 Initialization/de-initialization functions
00205  *  @brief    Initialization and Configuration functions.
00206  *
00207 @verbatim
00208   ==============================================================================
00209               ##### Initialization and de-initialization functions #####
00210   ==============================================================================
00211     [..]  This section provides functions allowing to:
00212       (+) Initialize the LPTIM according to the specified parameters in the
00213           LPTIM_InitTypeDef and creates the associated handle.
00214       (+) DeInitialize the LPTIM peripheral.
00215       (+) Initialize the LPTIM MSP.
00216       (+) DeInitialize LPTIM MSP.
00217
00218 @endverbatim
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Initializes the LPTIM according to the specified parameters in the
00224   *         LPTIM_InitTypeDef and creates the associated handle.
00225   * @param  hlptim: LPTIM handle
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00229 {
00230   uint32_t tmpcfgr = 0;
00231
00232   /* Check the LPTIM handle allocation */
00233   if(hlptim == NULL)
00234   {
00235     return HAL_ERROR;
00236   }
00237
00238   /* Check the parameters */
00239   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00240
00241   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00242   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00243   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00244   {
00245     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00246     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00247   }
00248   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00249   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00250   {
00251     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00252     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00253   }
00254   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00255   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00256   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00257
00258   if(hlptim->State == HAL_LPTIM_STATE_RESET)
00259   {
00260     /* Allocate lock resource and initialize it */
00261     hlptim->Lock = HAL_UNLOCKED;
00262     /* Init the low level hardware */
00263     HAL_LPTIM_MspInit(hlptim);
00264   }
00265
00266   /* Change the LPTIM state */
00267   hlptim->State = HAL_LPTIM_STATE_BUSY;
00268
00269   /* Get the LPTIMx CFGR value */
00270   tmpcfgr = hlptim->Instance->CFGR;
00271
00272   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00273   {
00274     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00275   }
00276   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00277   {
00278     tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00279   }
00280
00281   /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00282   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00283                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
00284
00285   /* Set initialization parameters */
00286   tmpcfgr |= (hlptim->Init.Clock.Source    |
00287               hlptim->Init.Clock.Prescaler |
00288               hlptim->Init.OutputPolarity  |
00289               hlptim->Init.UpdateMode      |
00290               hlptim->Init.CounterSource);
00291
00292   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00293   {
00294     tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |
00295                 hlptim->Init.UltraLowPowerClock.SampleTime);
00296   }
00297
00298   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00299   {
00300     /* Enable External trigger and set the trigger source */
00301     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00302                 hlptim->Init.Trigger.ActiveEdge |
00303                 hlptim->Init.Trigger.SampleTime);
00304   }
00305
00306   /* Write to LPTIMx CFGR */
00307   hlptim->Instance->CFGR = tmpcfgr;
00308
00309   /* Change the LPTIM state */
00310   hlptim->State = HAL_LPTIM_STATE_READY;
00311
00312   /* Return function status */
00313   return HAL_OK;
00314 }
00315
00316 /**
00317   * @brief  DeInitializes the LPTIM peripheral.
00318   * @param  hlptim: LPTIM handle
00319   * @retval HAL status
00320   */
00321 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00322 {
00323   /* Check the LPTIM handle allocation */
00324   if(hlptim == NULL)
00325   {
00326     return HAL_ERROR;
00327   }
00328
00329   /* Change the LPTIM state */
00330   hlptim->State = HAL_LPTIM_STATE_BUSY;
00331
00332   /* Disable the LPTIM Peripheral Clock */
00333   __HAL_LPTIM_DISABLE(hlptim);
00334
00335   /* DeInit the low level hardware: CLOCK, NVIC.*/
00336   HAL_LPTIM_MspDeInit(hlptim);
00337
00338   /* Change the LPTIM state */
00339   hlptim->State = HAL_LPTIM_STATE_RESET;
00340
00341   /* Release Lock */
00342   __HAL_UNLOCK(hlptim);
00343
00344   /* Return function status */
00345   return HAL_OK;
00346 }
00347
00348 /**
00349   * @brief  Initializes the LPTIM MSP.
00350   * @param  hlptim: LPTIM handle
00351   * @retval None
00352   */
00353 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hlptim);
00357
00358   /* NOTE : This function Should not be modified, when the callback is needed,
00359             the HAL_LPTIM_MspInit could be implemented in the user file
00360    */
00361 }
00362
00363 /**
00364   * @brief  DeInitializes LPTIM MSP.
00365   * @param  hlptim: LPTIM handle
00366   * @retval None
00367   */
00368 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00369 {
00370   /* Prevent unused argument(s) compilation warning */
00371   UNUSED(hlptim);
00372
00373   /* NOTE : This function Should not be modified, when the callback is needed,
00374             the HAL_LPTIM_MspDeInit could be implemented in the user file
00375    */
00376 }
00377
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
00383  *  @brief   Start-Stop operation functions.
00384  *
00385 @verbatim
00386   ==============================================================================
00387                 ##### LPTIM Start Stop operation functions #####
00388   ==============================================================================
00389     [..]  This section provides functions allowing to:
00390       (+) Start the PWM mode.
00391       (+) Stop the PWM mode.
00392       (+) Start the One pulse mode.
00393       (+) Stop the One pulse mode.
00394       (+) Start the Set once mode.
00395       (+) Stop the Set once mode.
00396       (+) Start the Encoder mode.
00397       (+) Stop the Encoder mode.
00398       (+) Start the Timeout mode.
00399       (+) Stop the Timeout mode.
00400       (+) Start the Counter mode.
00401       (+) Stop the Counter mode.
00402
00403
00404 @endverbatim
00405   * @{
00406   */
00407
00408 /**
00409   * @brief  Starts the LPTIM PWM generation.
00410   * @param  hlptim : LPTIM handle
00411   * @param  Period : Specifies the Autoreload value.
00412   *         This parameter must be a value between 0x0000 and 0xFFFF.
00413   * @param  Pulse : Specifies the compare value.
00414   *         This parameter must be a value between 0x0000 and 0xFFFF.
00415   * @retval HAL status
00416   */
00417 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00418 {
00419   /* Check the parameters */
00420   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00421   assert_param(IS_LPTIM_PERIOD(Period));
00422   assert_param(IS_LPTIM_PULSE(Pulse));
00423
00424   /* Set the LPTIM state */
00425   hlptim->State= HAL_LPTIM_STATE_BUSY;
00426
00427   /* Reset WAVE bit to set PWM mode */
00428   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00429
00430   /* Enable the Peripheral */
00431   __HAL_LPTIM_ENABLE(hlptim);
00432
00433   /* Load the period value in the autoreload register */
00434   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00435
00436   /* Load the pulse value in the compare register */
00437   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00438
00439   /* Start timer in continuous mode */
00440   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00441
00442   /* Change the TIM state*/
00443   hlptim->State= HAL_LPTIM_STATE_READY;
00444
00445   /* Return function status */
00446   return HAL_OK;
00447 }
00448
00449 /**
00450   * @brief  Stops the LPTIM PWM generation.
00451   * @param  hlptim : LPTIM handle
00452   * @retval HAL status
00453   */
00454 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00455 {
00456   /* Check the parameters */
00457   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00458
00459   /* Set the LPTIM state */
00460   hlptim->State= HAL_LPTIM_STATE_BUSY;
00461
00462   /* Disable the Peripheral */
00463   __HAL_LPTIM_DISABLE(hlptim);
00464
00465   /* Change the TIM state*/
00466   hlptim->State= HAL_LPTIM_STATE_READY;
00467
00468   /* Return function status */
00469   return HAL_OK;
00470 }
00471
00472 /**
00473   * @brief  Starts the LPTIM PWM generation in interrupt mode.
00474   * @param  hlptim : LPTIM handle
00475   * @param  Period : Specifies the Autoreload value.
00476   *         This parameter must be a value between 0x0000 and 0xFFFF
00477   * @param  Pulse : Specifies the compare value.
00478   *         This parameter must be a value between 0x0000 and 0xFFFF
00479   * @retval HAL status
00480   */
00481 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00482 {
00483   /* Check the parameters */
00484   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00485   assert_param(IS_LPTIM_PERIOD(Period));
00486   assert_param(IS_LPTIM_PULSE(Pulse));
00487
00488   /* Set the LPTIM state */
00489   hlptim->State= HAL_LPTIM_STATE_BUSY;
00490
00491   /* Reset WAVE bit to set PWM mode */
00492   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00493
00494   /* Enable Autoreload write complete interrupt */
00495   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00496
00497   /* Enable Compare write complete interrupt */
00498   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00499
00500   /* Enable Autoreload match interrupt */
00501   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00502
00503   /* Enable Compare match interrupt */
00504   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00505
00506   /* If external trigger source is used, then enable external trigger interrupt */
00507   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00508   {
00509     /* Enable external trigger interrupt */
00510     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00511   }
00512
00513   /* Enable the Peripheral */
00514   __HAL_LPTIM_ENABLE(hlptim);
00515
00516   /* Load the period value in the autoreload register */
00517   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00518
00519   /* Load the pulse value in the compare register */
00520   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00521
00522   /* Start timer in continuous mode */
00523   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00524
00525   /* Change the TIM state*/
00526   hlptim->State= HAL_LPTIM_STATE_READY;
00527
00528   /* Return function status */
00529   return HAL_OK;
00530 }
00531
00532 /**
00533   * @brief  Stops the LPTIM PWM generation in interrupt mode.
00534   * @param  hlptim : LPTIM handle
00535   * @retval HAL status
00536   */
00537 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00538 {
00539   /* Check the parameters */
00540   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00541
00542   /* Set the LPTIM state */
00543   hlptim->State= HAL_LPTIM_STATE_BUSY;
00544
00545   /* Disable the Peripheral */
00546   __HAL_LPTIM_DISABLE(hlptim);
00547
00548     /* Disable Autoreload write complete interrupt */
00549   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00550
00551   /* Disable Compare write complete interrupt */
00552   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00553
00554   /* Disable Autoreload match interrupt */
00555   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00556
00557   /* Disable Compare match interrupt */
00558   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00559
00560   /* If external trigger source is used, then disable external trigger interrupt */
00561   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00562   {
00563     /* Disable external trigger interrupt */
00564     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00565   }
00566
00567   /* Change the TIM state*/
00568   hlptim->State= HAL_LPTIM_STATE_READY;
00569
00570   /* Return function status */
00571   return HAL_OK;
00572 }
00573
00574 /**
00575   * @brief  Starts the LPTIM One pulse generation.
00576   * @param  hlptim : LPTIM handle
00577   * @param  Period : Specifies the Autoreload value.
00578   *         This parameter must be a value between 0x0000 and 0xFFFF.
00579   * @param  Pulse : Specifies the compare value.
00580   *         This parameter must be a value between 0x0000 and 0xFFFF.
00581   * @retval HAL status
00582   */
00583 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00587   assert_param(IS_LPTIM_PERIOD(Period));
00588   assert_param(IS_LPTIM_PULSE(Pulse));
00589
00590   /* Set the LPTIM state */
00591   hlptim->State= HAL_LPTIM_STATE_BUSY;
00592
00593   /* Reset WAVE bit to set one pulse mode */
00594   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00595
00596   /* Enable the Peripheral */
00597   __HAL_LPTIM_ENABLE(hlptim);
00598
00599   /* Load the period value in the autoreload register */
00600   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00601
00602   /* Load the pulse value in the compare register */
00603   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00604
00605   /* Start timer in continuous mode */
00606   __HAL_LPTIM_START_SINGLE(hlptim);
00607
00608   /* Change the TIM state*/
00609   hlptim->State= HAL_LPTIM_STATE_READY;
00610
00611   /* Return function status */
00612   return HAL_OK;
00613 }
00614
00615 /**
00616   * @brief  Stops the LPTIM One pulse generation.
00617   * @param  hlptim : LPTIM handle
00618   * @retval HAL status
00619   */
00620 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00621 {
00622   /* Check the parameters */
00623   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00624
00625   /* Set the LPTIM state */
00626   hlptim->State= HAL_LPTIM_STATE_BUSY;
00627
00628   /* Disable the Peripheral */
00629   __HAL_LPTIM_DISABLE(hlptim);
00630
00631   /* Change the TIM state*/
00632   hlptim->State= HAL_LPTIM_STATE_READY;
00633
00634   /* Return function status */
00635   return HAL_OK;
00636 }
00637
00638 /**
00639   * @brief  Starts the LPTIM One pulse generation in interrupt mode.
00640   * @param  hlptim : LPTIM handle
00641   * @param  Period : Specifies the Autoreload value.
00642   *         This parameter must be a value between 0x0000 and 0xFFFF.
00643   * @param  Pulse : Specifies the compare value.
00644   *         This parameter must be a value between 0x0000 and 0xFFFF.
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00648 {
00649   /* Check the parameters */
00650   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00651   assert_param(IS_LPTIM_PERIOD(Period));
00652   assert_param(IS_LPTIM_PULSE(Pulse));
00653
00654   /* Set the LPTIM state */
00655   hlptim->State= HAL_LPTIM_STATE_BUSY;
00656
00657   /* Reset WAVE bit to set one pulse mode */
00658   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00659
00660   /* Enable Autoreload write complete interrupt */
00661   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00662
00663   /* Enable Compare write complete interrupt */
00664   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00665
00666   /* Enable Autoreload match interrupt */
00667   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00668
00669   /* Enable Compare match interrupt */
00670   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00671
00672   /* If external trigger source is used, then enable external trigger interrupt */
00673   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00674   {
00675     /* Enable external trigger interrupt */
00676     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00677   }
00678
00679   /* Enable the Peripheral */
00680   __HAL_LPTIM_ENABLE(hlptim);
00681
00682   /* Load the period value in the autoreload register */
00683   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00684
00685   /* Load the pulse value in the compare register */
00686   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00687
00688   /* Start timer in continuous mode */
00689   __HAL_LPTIM_START_SINGLE(hlptim);
00690
00691   /* Change the TIM state*/
00692   hlptim->State= HAL_LPTIM_STATE_READY;
00693
00694   /* Return function status */
00695   return HAL_OK;
00696 }
00697
00698 /**
00699   * @brief  Stops the LPTIM One pulse generation in interrupt mode.
00700   * @param  hlptim : LPTIM handle
00701   * @retval HAL status
00702   */
00703 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00704 {
00705   /* Check the parameters */
00706   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00707
00708   /* Set the LPTIM state */
00709   hlptim->State= HAL_LPTIM_STATE_BUSY;
00710
00711   /* Disable the Peripheral */
00712   __HAL_LPTIM_DISABLE(hlptim);
00713
00714   /* Disable Autoreload write complete interrupt */
00715   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00716
00717   /* Disable Compare write complete interrupt */
00718   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00719
00720   /* Disable Autoreload match interrupt */
00721   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00722
00723   /* Disable Compare match interrupt */
00724   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00725
00726   /* If external trigger source is used, then disable external trigger interrupt */
00727   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00728   {
00729     /* Disable external trigger interrupt */
00730     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00731   }
00732
00733   /* Change the TIM state*/
00734   hlptim->State= HAL_LPTIM_STATE_READY;
00735
00736   /* Return function status */
00737   return HAL_OK;
00738 }
00739
00740 /**
00741   * @brief  Starts the LPTIM in Set once mode.
00742   * @param  hlptim : LPTIM handle
00743   * @param  Period : Specifies the Autoreload value.
00744   *         This parameter must be a value between 0x0000 and 0xFFFF.
00745   * @param  Pulse : Specifies the compare value.
00746   *         This parameter must be a value between 0x0000 and 0xFFFF.
00747   * @retval HAL status
00748   */
00749 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00750 {
00751   /* Check the parameters */
00752   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00753   assert_param(IS_LPTIM_PERIOD(Period));
00754   assert_param(IS_LPTIM_PULSE(Pulse));
00755
00756   /* Set the LPTIM state */
00757   hlptim->State= HAL_LPTIM_STATE_BUSY;
00758
00759   /* Set WAVE bit to enable the set once mode */
00760   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00761
00762   /* Enable the Peripheral */
00763   __HAL_LPTIM_ENABLE(hlptim);
00764
00765   /* Load the period value in the autoreload register */
00766   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00767
00768   /* Load the pulse value in the compare register */
00769   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00770
00771   /* Start timer in continuous mode */
00772   __HAL_LPTIM_START_SINGLE(hlptim);
00773
00774   /* Change the TIM state*/
00775   hlptim->State= HAL_LPTIM_STATE_READY;
00776
00777   /* Return function status */
00778   return HAL_OK;
00779 }
00780
00781 /**
00782   * @brief  Stops the LPTIM Set once mode.
00783   * @param  hlptim : LPTIM handle
00784   * @retval HAL status
00785   */
00786 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00787 {
00788   /* Check the parameters */
00789   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00790
00791   /* Set the LPTIM state */
00792   hlptim->State= HAL_LPTIM_STATE_BUSY;
00793
00794   /* Disable the Peripheral */
00795   __HAL_LPTIM_DISABLE(hlptim);
00796
00797   /* Change the TIM state*/
00798   hlptim->State= HAL_LPTIM_STATE_READY;
00799
00800   /* Return function status */
00801   return HAL_OK;
00802 }
00803
00804 /**
00805   * @brief  Starts the LPTIM Set once mode in interrupt mode.
00806   * @param  hlptim : LPTIM handle
00807   * @param  Period : Specifies the Autoreload value.
00808   *         This parameter must be a value between 0x0000 and 0xFFFF.
00809   * @param  Pulse : Specifies the compare value.
00810   *         This parameter must be a value between 0x0000 and 0xFFFF.
00811   * @retval HAL status
00812   */
00813 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00814 {
00815   /* Check the parameters */
00816   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00817   assert_param(IS_LPTIM_PERIOD(Period));
00818   assert_param(IS_LPTIM_PULSE(Pulse));
00819
00820   /* Set the LPTIM state */
00821   hlptim->State= HAL_LPTIM_STATE_BUSY;
00822
00823   /* Set WAVE bit to enable the set once mode */
00824   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00825
00826   /* Enable Autoreload write complete interrupt */
00827   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00828
00829   /* Enable Compare write complete interrupt */
00830   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00831
00832   /* Enable Autoreload match interrupt */
00833   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00834
00835   /* Enable Compare match interrupt */
00836   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00837
00838   /* If external trigger source is used, then enable external trigger interrupt */
00839   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00840   {
00841     /* Enable external trigger interrupt */
00842     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00843   }
00844
00845   /* Enable the Peripheral */
00846   __HAL_LPTIM_ENABLE(hlptim);
00847
00848   /* Load the period value in the autoreload register */
00849   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00850
00851   /* Load the pulse value in the compare register */
00852   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00853
00854   /* Start timer in continuous mode */
00855   __HAL_LPTIM_START_SINGLE(hlptim);
00856
00857   /* Change the TIM state*/
00858   hlptim->State= HAL_LPTIM_STATE_READY;
00859
00860   /* Return function status */
00861   return HAL_OK;
00862 }
00863
00864 /**
00865   * @brief  Stops the LPTIM Set once mode in interrupt mode.
00866   * @param  hlptim : LPTIM handle
00867   * @retval HAL status
00868   */
00869 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00870 {
00871   /* Check the parameters */
00872   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00873
00874   /* Set the LPTIM state */
00875   hlptim->State= HAL_LPTIM_STATE_BUSY;
00876
00877   /* Disable the Peripheral */
00878   __HAL_LPTIM_DISABLE(hlptim);
00879
00880   /* Disable Autoreload write complete interrupt */
00881   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00882
00883   /* Disable Compare write complete interrupt */
00884   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00885
00886   /* Disable Autoreload match interrupt */
00887   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00888
00889   /* Disable Compare match interrupt */
00890   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00891
00892   /* If external trigger source is used, then disable external trigger interrupt */
00893   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00894   {
00895     /* Disable external trigger interrupt */
00896     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00897   }
00898
00899   /* Change the TIM state*/
00900   hlptim->State= HAL_LPTIM_STATE_READY;
00901
00902   /* Return function status */
00903   return HAL_OK;
00904 }
00905
00906 /**
00907   * @brief  Starts the Encoder interface.
00908   * @param  hlptim : LPTIM handle
00909   * @param  Period : Specifies the Autoreload value.
00910   *         This parameter must be a value between 0x0000 and 0xFFFF.
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00914 {
00915   uint32_t tmpcfgr = 0;
00916
00917   /* Check the parameters */
00918   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00919   assert_param(IS_LPTIM_PERIOD(Period));
00920   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00921   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00922   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00923
00924   /* Set the LPTIM state */
00925   hlptim->State= HAL_LPTIM_STATE_BUSY;
00926
00927   /* Get the LPTIMx CFGR value */
00928   tmpcfgr = hlptim->Instance->CFGR;
00929
00930   /* Clear CKPOL bits */
00931   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
00932
00933   /* Set Input polarity */
00934   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
00935
00936   /* Write to LPTIMx CFGR */
00937   hlptim->Instance->CFGR = tmpcfgr;
00938
00939   /* Set ENC bit to enable the encoder interface */
00940   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
00941
00942   /* Enable the Peripheral */
00943   __HAL_LPTIM_ENABLE(hlptim);
00944
00945   /* Load the period value in the autoreload register */
00946   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00947
00948   /* Start timer in continuous mode */
00949   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00950
00951   /* Change the TIM state*/
00952   hlptim->State= HAL_LPTIM_STATE_READY;
00953
00954   /* Return function status */
00955   return HAL_OK;
00956 }
00957
00958 /**
00959   * @brief  Stops the Encoder interface.
00960   * @param  hlptim : LPTIM handle
00961   * @retval HAL status
00962   */
00963 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
00964 {
00965   /* Check the parameters */
00966   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00967
00968   /* Set the LPTIM state */
00969   hlptim->State= HAL_LPTIM_STATE_BUSY;
00970
00971   /* Disable the Peripheral */
00972   __HAL_LPTIM_DISABLE(hlptim);
00973
00974   /* Reset ENC bit to disable the encoder interface */
00975   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
00976
00977   /* Change the TIM state*/
00978   hlptim->State= HAL_LPTIM_STATE_READY;
00979
00980   /* Return function status */
00981   return HAL_OK;
00982 }
00983
00984 /**
00985   * @brief  Starts the Encoder interface in interrupt mode.
00986   * @param  hlptim : LPTIM handle
00987   * @param  Period : Specifies the Autoreload value.
00988   *         This parameter must be a value between 0x0000 and 0xFFFF.
00989   * @retval HAL status
00990   */
00991 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00992 {
00993   uint32_t tmpcfgr = 0;
00994
00995   /* Check the parameters */
00996   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00997   assert_param(IS_LPTIM_PERIOD(Period));
00998   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00999   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01000   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01001
01002   /* Set the LPTIM state */
01003   hlptim->State= HAL_LPTIM_STATE_BUSY;
01004
01005   /* Configure edge sensitivity for encoder mode */
01006   /* Get the LPTIMx CFGR value */
01007   tmpcfgr = hlptim->Instance->CFGR;
01008
01009   /* Clear CKPOL bits */
01010   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01011
01012   /* Set Input polarity */
01013   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01014
01015   /* Write to LPTIMx CFGR */
01016   hlptim->Instance->CFGR = tmpcfgr;
01017
01018   /* Set ENC bit to enable the encoder interface */
01019   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01020
01021   /* Enable "switch to down direction" interrupt */
01022   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01023
01024   /* Enable "switch to up direction" interrupt */
01025   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01026
01027   /* Enable the Peripheral */
01028   __HAL_LPTIM_ENABLE(hlptim);
01029
01030   /* Load the period value in the autoreload register */
01031   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01032
01033   /* Start timer in continuous mode */
01034   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01035
01036   /* Change the TIM state*/
01037   hlptim->State= HAL_LPTIM_STATE_READY;
01038
01039   /* Return function status */
01040   return HAL_OK;
01041 }
01042
01043 /**
01044   * @brief  Stops the Encoder interface in interrupt mode.
01045   * @param  hlptim : LPTIM handle
01046   * @retval HAL status
01047   */
01048 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01049 {
01050   /* Check the parameters */
01051   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01052
01053   /* Set the LPTIM state */
01054   hlptim->State= HAL_LPTIM_STATE_BUSY;
01055
01056   /* Disable the Peripheral */
01057   __HAL_LPTIM_DISABLE(hlptim);
01058
01059   /* Reset ENC bit to disable the encoder interface */
01060   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01061
01062   /* Disable "switch to down direction" interrupt */
01063   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01064
01065   /* Disable "switch to up direction" interrupt */
01066   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01067
01068   /* Change the TIM state*/
01069   hlptim->State= HAL_LPTIM_STATE_READY;
01070
01071   /* Return function status */
01072   return HAL_OK;
01073 }
01074
01075 /**
01076   * @brief  Starts the Timeout function. The first trigger event will start the
01077   *         timer, any successive trigger event will reset the counter and
01078   *         the timer restarts.
01079   * @param  hlptim : LPTIM handle
01080   * @param  Period : Specifies the Autoreload value.
01081   *         This parameter must be a value between 0x0000 and 0xFFFF.
01082   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01083   *         This parameter must be a value between 0x0000 and 0xFFFF.
01084   * @retval HAL status
01085   */
01086 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01087 {
01088   /* Check the parameters */
01089   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01090   assert_param(IS_LPTIM_PERIOD(Period));
01091   assert_param(IS_LPTIM_PULSE(Timeout));
01092
01093   /* Set the LPTIM state */
01094   hlptim->State= HAL_LPTIM_STATE_BUSY;
01095
01096   /* Set TIMOUT bit to enable the timeout function */
01097   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01098
01099   /* Enable the Peripheral */
01100   __HAL_LPTIM_ENABLE(hlptim);
01101
01102   /* Load the period value in the autoreload register */
01103   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01104
01105   /* Load the Timeout value in the compare register */
01106   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01107
01108   /* Start timer in continuous mode */
01109   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01110
01111   /* Change the TIM state*/
01112   hlptim->State= HAL_LPTIM_STATE_READY;
01113
01114   /* Return function status */
01115   return HAL_OK;
01116 }
01117
01118 /**
01119   * @brief  Stops the Timeout function.
01120   * @param  hlptim : LPTIM handle
01121   * @retval HAL status
01122   */
01123 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01124 {
01125   /* Check the parameters */
01126   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01127
01128   /* Set the LPTIM state */
01129   hlptim->State= HAL_LPTIM_STATE_BUSY;
01130
01131   /* Disable the Peripheral */
01132   __HAL_LPTIM_DISABLE(hlptim);
01133
01134   /* Reset TIMOUT bit to enable the timeout function */
01135   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01136
01137   /* Change the TIM state*/
01138   hlptim->State= HAL_LPTIM_STATE_READY;
01139
01140   /* Return function status */
01141   return HAL_OK;
01142 }
01143
01144 /**
01145   * @brief  Starts the Timeout function in interrupt mode. The first trigger
01146   *         event will start the timer, any successive trigger event will reset
01147   *         the counter and the timer restarts.
01148   * @param  hlptim : LPTIM handle
01149   * @param  Period : Specifies the Autoreload value.
01150   *         This parameter must be a value between 0x0000 and 0xFFFF.
01151   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01152   *         This parameter must be a value between 0x0000 and 0xFFFF.
01153   * @retval HAL status
01154   */
01155 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01156 {
01157   /* Check the parameters */
01158   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01159   assert_param(IS_LPTIM_PERIOD(Period));
01160   assert_param(IS_LPTIM_PULSE(Timeout));
01161
01162   /* Set the LPTIM state */
01163   hlptim->State= HAL_LPTIM_STATE_BUSY;
01164
01165   /* Set TIMOUT bit to enable the timeout function */
01166   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01167
01168   /* Enable Compare match interrupt */
01169   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01170
01171   /* Enable the Peripheral */
01172   __HAL_LPTIM_ENABLE(hlptim);
01173
01174   /* Load the period value in the autoreload register */
01175   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01176
01177   /* Load the Timeout value in the compare register */
01178   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01179
01180   /* Start timer in continuous mode */
01181   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01182
01183   /* Change the TIM state*/
01184   hlptim->State= HAL_LPTIM_STATE_READY;
01185
01186   /* Return function status */
01187   return HAL_OK;
01188 }
01189
01190 /**
01191   * @brief  Stops the Timeout function in interrupt mode.
01192   * @param  hlptim : LPTIM handle
01193   * @retval HAL status
01194   */
01195 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01196 {
01197   /* Check the parameters */
01198   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01199
01200   /* Set the LPTIM state */
01201   hlptim->State= HAL_LPTIM_STATE_BUSY;
01202
01203   /* Disable the Peripheral */
01204   __HAL_LPTIM_DISABLE(hlptim);
01205
01206   /* Reset TIMOUT bit to enable the timeout function */
01207   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01208
01209   /* Disable Compare match interrupt */
01210   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01211
01212   /* Change the TIM state*/
01213   hlptim->State= HAL_LPTIM_STATE_READY;
01214
01215   /* Return function status */
01216   return HAL_OK;
01217 }
01218
01219 /**
01220   * @brief  Starts the Counter mode.
01221   * @param  hlptim : LPTIM handle
01222   * @param  Period : Specifies the Autoreload value.
01223   *         This parameter must be a value between 0x0000 and 0xFFFF.
01224   * @retval HAL status
01225   */
01226 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01227 {
01228   /* Check the parameters */
01229   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01230   assert_param(IS_LPTIM_PERIOD(Period));
01231
01232   /* Set the LPTIM state */
01233   hlptim->State= HAL_LPTIM_STATE_BUSY;
01234
01235   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01236   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01237   {
01238     /* Check if clock is prescaled */
01239     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01240     /* Set clock prescaler to 0 */
01241     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01242   }
01243
01244   /* Enable the Peripheral */
01245   __HAL_LPTIM_ENABLE(hlptim);
01246
01247   /* Load the period value in the autoreload register */
01248   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01249
01250   /* Start timer in continuous mode */
01251   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01252
01253   /* Change the TIM state*/
01254   hlptim->State= HAL_LPTIM_STATE_READY;
01255
01256   /* Return function status */
01257   return HAL_OK;
01258 }
01259
01260 /**
01261   * @brief  Stops the Counter mode.
01262   * @param  hlptim : LPTIM handle
01263   * @retval HAL status
01264   */
01265 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01266 {
01267   /* Check the parameters */
01268   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01269
01270   /* Set the LPTIM state */
01271   hlptim->State= HAL_LPTIM_STATE_BUSY;
01272
01273   /* Disable the Peripheral */
01274   __HAL_LPTIM_DISABLE(hlptim);
01275
01276   /* Change the TIM state*/
01277   hlptim->State= HAL_LPTIM_STATE_READY;
01278
01279   /* Return function status */
01280   return HAL_OK;
01281 }
01282
01283 /**
01284   * @brief  Starts the Counter mode in interrupt mode.
01285   * @param  hlptim : LPTIM handle
01286   * @param  Period : Specifies the Autoreload value.
01287   *         This parameter must be a value between 0x0000 and 0xFFFF.
01288   * @retval HAL status
01289   */
01290 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01291 {
01292   /* Check the parameters */
01293   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01294   assert_param(IS_LPTIM_PERIOD(Period));
01295
01296   /* Set the LPTIM state */
01297   hlptim->State= HAL_LPTIM_STATE_BUSY;
01298
01299   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01300   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01301   {
01302     /* Check if clock is prescaled */
01303     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01304     /* Set clock prescaler to 0 */
01305     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01306   }
01307
01308   /* Enable Autoreload write complete interrupt */
01309   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01310
01311   /* Enable Autoreload match interrupt */
01312   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01313
01314   /* Enable the Peripheral */
01315   __HAL_LPTIM_ENABLE(hlptim);
01316
01317   /* Load the period value in the autoreload register */
01318   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01319
01320   /* Start timer in continuous mode */
01321   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01322
01323   /* Change the TIM state*/
01324   hlptim->State= HAL_LPTIM_STATE_READY;
01325
01326   /* Return function status */
01327   return HAL_OK;
01328 }
01329
01330 /**
01331   * @brief  Stops the Counter mode in interrupt mode.
01332   * @param  hlptim : LPTIM handle
01333   * @retval HAL status
01334   */
01335 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01336 {
01337   /* Check the parameters */
01338   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01339
01340   /* Set the LPTIM state */
01341   hlptim->State= HAL_LPTIM_STATE_BUSY;
01342
01343   /* Disable the Peripheral */
01344   __HAL_LPTIM_DISABLE(hlptim);
01345
01346   /* Disable Autoreload write complete interrupt */
01347   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01348
01349   /* Disable Autoreload match interrupt */
01350   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01351
01352   /* Change the TIM state*/
01353   hlptim->State= HAL_LPTIM_STATE_READY;
01354
01355   /* Return function status */
01356   return HAL_OK;
01357 }
01358
01359 /**
01360   * @}
01361   */
01362
01363 /** @defgroup LPTIM_Group3 LPTIM Read operation functions
01364  *  @brief  Read operation functions.
01365  *
01366 @verbatim
01367   ==============================================================================
01368                   ##### LPTIM Read operation functions #####
01369   ==============================================================================
01370 [..]  This section provides LPTIM Reading functions.
01371       (+) Read the counter value.
01372       (+) Read the period (Auto-reload) value.
01373       (+) Read the pulse (Compare)value.
01374 @endverbatim
01375   * @{
01376   */
01377
01378 /**
01379   * @brief  This function returns the current counter value.
01380   * @param  hlptim: LPTIM handle
01381   * @retval Counter value.
01382   */
01383 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
01384 {
01385     /* Check the parameters */
01386   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01387
01388   return (hlptim->Instance->CNT);
01389 }
01390
01391 /**
01392   * @brief  This function return the current Autoreload (Period) value.
01393   * @param  hlptim: LPTIM handle
01394   * @retval Autoreload value.
01395   */
01396 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
01397 {
01398     /* Check the parameters */
01399   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01400
01401   return (hlptim->Instance->ARR);
01402 }
01403
01404 /**
01405   * @brief  This function return the current Compare (Pulse) value.
01406   * @param  hlptim: LPTIM handle
01407   * @retval Compare value.
01408   */
01409 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
01410 {
01411     /* Check the parameters */
01412   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01413
01414   return (hlptim->Instance->CMP);
01415 }
01416
01417 /**
01418   * @}
01419   */
01420
01421
01422
01423 /** @defgroup LPTIM_Group4 LPTIM IRQ handler
01424  *  @brief  LPTIM  IRQ handler.
01425  *
01426 @verbatim
01427   ==============================================================================
01428                       ##### LPTIM IRQ handler  #####
01429   ==============================================================================
01430 [..]  This section provides LPTIM IRQ handler function.
01431
01432 @endverbatim
01433   * @{
01434   */
01435
01436 /**
01437   * @brief  This function handles LPTIM interrupt request.
01438   * @param  hlptim: LPTIM handle
01439   * @retval None
01440   */
01441 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01442 {
01443   /* Compare match interrupt */
01444   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01445         {
01446     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
01447                 {
01448       /* Clear Compare match flag */
01449       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01450       /* Compare match Callback */
01451       HAL_LPTIM_CompareMatchCallback(hlptim);
01452     }
01453   }
01454
01455   /* Autoreload match interrupt */
01456   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01457         {
01458     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
01459                 {
01460       /* Clear Autoreload match flag */
01461       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01462       /* Autoreload match Callback */
01463       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01464     }
01465   }
01466
01467   /* Trigger detected interrupt */
01468   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01469         {
01470     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
01471                 {
01472       /* Clear Trigger detected flag */
01473       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01474       /* Trigger detected callback */
01475       HAL_LPTIM_TriggerCallback(hlptim);
01476     }
01477   }
01478
01479   /* Compare write interrupt */
01480   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01481         {
01482     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
01483                 {
01484       /* Clear Compare write flag */
01485       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01486       /* Compare write Callback */
01487       HAL_LPTIM_CompareWriteCallback(hlptim);
01488     }
01489   }
01490
01491   /* Autoreload write interrupt */
01492   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01493         {
01494     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
01495                 {
01496       /* Clear Autoreload write flag */
01497       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01498       /* Autoreload write Callback */
01499       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01500     }
01501   }
01502
01503   /* Direction counter changed from Down to Up interrupt */
01504   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01505         {
01506     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
01507                 {
01508       /* Clear Direction counter changed from Down to Up flag */
01509       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01510       /* Direction counter changed from Down to Up Callback */
01511       HAL_LPTIM_DirectionUpCallback(hlptim);
01512     }
01513   }
01514
01515   /* Direction counter changed from Up to Down interrupt */
01516   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01517         {
01518     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
01519                 {
01520       /* Clear Direction counter changed from Up to Down flag */
01521       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01522       /* Direction counter changed from Up to Down Callback */
01523       HAL_LPTIM_DirectionDownCallback(hlptim);
01524     }
01525   }
01526 }
01527
01528 /**
01529   * @brief  Compare match callback in non blocking mode
01530   * @param  hlptim : LPTIM handle
01531   * @retval None
01532   */
01533 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01534 {
01535   /* Prevent unused argument(s) compilation warning */
01536   UNUSED(hlptim);
01537
01538   /* NOTE : This function Should not be modified, when the callback is needed,
01539             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01540    */
01541 }
01542
01543 /**
01544   * @brief  Autoreload match callback in non blocking mode
01545   * @param  hlptim : LPTIM handle
01546   * @retval None
01547   */
01548 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01549 {
01550   /* Prevent unused argument(s) compilation warning */
01551   UNUSED(hlptim);
01552
01553   /* NOTE : This function Should not be modified, when the callback is needed,
01554             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01555    */
01556 }
01557
01558 /**
01559   * @brief  Trigger detected callback in non blocking mode
01560   * @param  hlptim : LPTIM handle
01561   * @retval None
01562   */
01563 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01564 {
01565   /* Prevent unused argument(s) compilation warning */
01566   UNUSED(hlptim);
01567
01568   /* NOTE : This function Should not be modified, when the callback is needed,
01569             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01570    */
01571 }
01572
01573 /**
01574   * @brief  Compare write callback in non blocking mode
01575   * @param  hlptim : LPTIM handle
01576   * @retval None
01577   */
01578 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01579 {
01580   /* Prevent unused argument(s) compilation warning */
01581   UNUSED(hlptim);
01582
01583   /* NOTE : This function Should not be modified, when the callback is needed,
01584             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01585    */
01586 }
01587
01588 /**
01589   * @brief  Autoreload write callback in non blocking mode
01590   * @param  hlptim : LPTIM handle
01591   * @retval None
01592   */
01593 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
01594 {
01595   /* Prevent unused argument(s) compilation warning */
01596   UNUSED(hlptim);
01597
01598   /* NOTE : This function Should not be modified, when the callback is needed,
01599             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
01600    */
01601 }
01602
01603 /**
01604   * @brief  Direction counter changed from Down to Up callback in non blocking mode
01605   * @param  hlptim : LPTIM handle
01606   * @retval None
01607   */
01608 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
01609 {
01610   /* Prevent unused argument(s) compilation warning */
01611   UNUSED(hlptim);
01612
01613   /* NOTE : This function Should not be modified, when the callback is needed,
01614             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
01615    */
01616 }
01617
01618 /**
01619   * @brief  Direction counter changed from Up to Down callback in non blocking mode
01620   * @param  hlptim : LPTIM handle
01621   * @retval None
01622   */
01623 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
01624 {
01625   /* Prevent unused argument(s) compilation warning */
01626   UNUSED(hlptim);
01627
01628   /* NOTE : This function Should not be modified, when the callback is needed,
01629             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
01630    */
01631 }
01632
01633 /**
01634   * @}
01635   */
01636
01637 /** @defgroup LPTIM_Group5 Peripheral State functions
01638  *  @brief   Peripheral State functions.
01639  *
01640 @verbatim
01641   ==============================================================================
01642                       ##### Peripheral State functions #####
01643   ==============================================================================
01644     [..]
01645     This subsection permits to get in run-time the status of the peripheral.
01646
01647 @endverbatim
01648   * @{
01649   */
01650
01651 /**
01652   * @brief  Returns the LPTIM state.
01653   * @param  hlptim: LPTIM handle
01654   * @retval HAL state
01655   */
01656 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
01657 {
01658   return hlptim->State;
01659 }
01660
01661 /**
01662   * @}
01663   */
01664
01665
01666 /**
01667   * @}
01668   */
01669
01670 #endif /* HAL_LPTIM_MODULE_ENABLED */
01671 /**
01672   * @}
01673   */
01674
01675 /**
01676   * @}
01677   */
01678
01679 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_lptim.h Source File

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stm32f7xx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of LPTIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_LPTIM_H
00040 #define __STM32F7xx_HAL_LPTIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup LPTIM LPTIM
00054   * @brief LPTIM HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  LPTIM Clock configuration definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Source;         /*!< Selects the clock source.
00069                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00070
00071   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00072                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00073
00074 }LPTIM_ClockConfigTypeDef;
00075
00076 /**
00077   * @brief  LPTIM Clock configuration definition
00078   */
00079 typedef struct
00080 {
00081   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00082                            if the ULPTIM input is selected.
00083                            Note: This parameter is used only when Ultra low power clock source is used.
00084                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00085                            (one of the Low power oscillator) must be active.
00086                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00087
00088   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00089                            Note: This parameter is used only when Ultra low power clock source is used.
00090                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00091
00092 }LPTIM_ULPClockConfigTypeDef;
00093
00094 /**
00095   * @brief  LPTIM Trigger configuration definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t Source;        /*!< Selects the Trigger source.
00100                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00101
00102   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00103                           Note: This parameter is used only when an external trigger is used.
00104                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00105
00106   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00107                           Note: This parameter is used only when an external trigger is used.
00108                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00109 }LPTIM_TriggerConfigTypeDef;
00110
00111 /**
00112   * @brief  LPTIM Initialization Structure definition
00113   */
00114 typedef struct
00115 {
00116   LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
00117
00118   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
00119
00120   LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
00121
00122   uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
00123                                                     This parameter can be a value of @ref LPTIM_Output_Polarity */
00124
00125   uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare
00126                                                     values is done immediately or after the end of current period.
00127                                                     This parameter can be a value of @ref LPTIM_Updating_Mode */
00128
00129   uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
00130                                                     or each external event.
00131                                                     This parameter can be a value of @ref LPTIM_Counter_Source */
00132
00133 }LPTIM_InitTypeDef;
00134
00135 /**
00136   * @brief  HAL LPTIM State structure definition
00137   */
00138 typedef enum __HAL_LPTIM_StateTypeDef
00139 {
00140   HAL_LPTIM_STATE_RESET            = 0x00,    /*!< Peripheral not yet initialized or disabled  */
00141   HAL_LPTIM_STATE_READY            = 0x01,    /*!< Peripheral Initialized and ready for use    */
00142   HAL_LPTIM_STATE_BUSY             = 0x02,    /*!< An internal process is ongoing              */
00143   HAL_LPTIM_STATE_TIMEOUT          = 0x03,    /*!< Timeout state                               */
00144   HAL_LPTIM_STATE_ERROR            = 0x04     /*!< Internal Process is ongoing                */
00145 }HAL_LPTIM_StateTypeDef;
00146
00147 /**
00148   * @brief  LPTIM handle Structure definition
00149   */
00150 typedef struct
00151 {
00152       LPTIM_TypeDef              *Instance;         /*!< Register base address     */
00153
00154       LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
00155
00156       HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */
00157
00158       HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
00159
00160    __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00161
00162 }LPTIM_HandleTypeDef;
00163
00164 /**
00165   * @}
00166   */
00167
00168 /* Exported constants --------------------------------------------------------*/
00169 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00170   * @{
00171   */
00172
00173 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00174   * @{
00175   */
00176 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00)
00177 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00183   * @{
00184   */
00185 #define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000)
00186 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00187 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00188 #define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
00189 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00190 #define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
00191 #define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
00192 #define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00198   * @{
00199   */
00200
00201 #define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000)
00202 #define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00208   * @{
00209   */
00210 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
00211 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS     LPTIM_CFGR_CKFLT_0
00212 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS     LPTIM_CFGR_CKFLT_1
00213 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS     LPTIM_CFGR_CKFLT
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00219   * @{
00220   */
00221
00222 #define LPTIM_CLOCKPOLARITY_RISING                ((uint32_t)0x00000000)
00223 #define LPTIM_CLOCKPOLARITY_FALLING               LPTIM_CFGR_CKPOL_0
00224 #define LPTIM_CLOCKPOLARITY_RISING_FALLING        LPTIM_CFGR_CKPOL_1
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00230   * @{
00231   */
00232 #define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFF)
00233 #define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000)
00234 #define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
00235 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00236 #define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00237 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00238 #define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00244   * @{
00245   */
00246 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00247 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00248 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00254   * @{
00255   */
00256 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
00257 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00258 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00259 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00265   * @{
00266   */
00267
00268 #define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000)
00269 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00275   * @{
00276   */
00277
00278 #define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000)
00279 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
00285   * @{
00286   */
00287
00288 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00289 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00290 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00291 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00292 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00293 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00294 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00300   * @{
00301   */
00302
00303 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00304 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00305 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00306 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00307 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00308 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00309 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /* Exported macro ------------------------------------------------------------*/
00319 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00320   * @{
00321   */
00322
00323 /** @brief Reset LPTIM handle state
00324   * @param  __HANDLE__: LPTIM handle
00325   * @retval None
00326   */
00327 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00328
00329 /**
00330   * @brief  Enable/Disable the LPTIM peripheral.
00331   * @param  __HANDLE__: LPTIM handle
00332   * @retval None
00333   */
00334 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
00335 #define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
00336
00337 /**
00338   * @brief  Starts the LPTIM peripheral in Continuous or in single mode.
00339   * @param  __HANDLE__: DMA handle
00340   * @retval None
00341   */
00342 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00343 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00344
00345
00346 /**
00347   * @brief  Writes the passed parameter in the Autoreload register.
00348   * @param  __HANDLE__: LPTIM handle
00349   * @param  __VALUE__ : Autoreload value
00350   * @retval None
00351   */
00352 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00353
00354 /**
00355   * @brief  Writes the passed parameter in the Compare register.
00356   * @param  __HANDLE__: LPTIM handle
00357   * @param  __VALUE__ : Compare value
00358   * @retval None
00359   */
00360 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00361
00362 /**
00363   * @brief  Checks whether the specified LPTIM flag is set or not.
00364   * @param  __HANDLE__: LPTIM handle
00365   * @param  __FLAG__  : LPTIM flag to check
00366   *            This parameter can be a value of:
00367   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00368   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00369   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00370   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00371   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00372   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00373   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00374   * @retval The state of the specified flag (SET or RESET).
00375   */
00376 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00377
00378 /**
00379   * @brief  Clears the specified LPTIM flag.
00380   * @param  __HANDLE__: LPTIM handle.
00381   * @param  __FLAG__  : LPTIM flag to clear.
00382   *            This parameter can be a value of:
00383   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00384   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00385   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00386   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00387   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00388   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00389   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00390   * @retval None.
00391   */
00392 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00393
00394 /**
00395   * @brief  Enable the specified LPTIM interrupt.
00396   * @param  __HANDLE__    : LPTIM handle.
00397   * @param  __INTERRUPT__ : LPTIM interrupt to set.
00398   *            This parameter can be a value of:
00399   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00400   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00401   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00402   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00403   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00404   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00405   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00406   * @retval None.
00407   */
00408 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00409
00410  /**
00411   * @brief  Disable the specified LPTIM interrupt.
00412   * @param  __HANDLE__    : LPTIM handle.
00413   * @param  __INTERRUPT__ : LPTIM interrupt to set.
00414   *            This parameter can be a value of:
00415   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00416   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00417   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00418   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00419   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00420   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00421   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00422   * @retval None.
00423   */
00424 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00425
00426     /**
00427   * @brief  Checks whether the specified LPTIM interrupt is set or not.
00428   * @param  __HANDLE__    : LPTIM handle.
00429   * @param  __INTERRUPT__ : LPTIM interrupt to check.
00430   *            This parameter can be a value of:
00431   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00432   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00433   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00434   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00435   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00436   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00437   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00438   * @retval Interrupt status.
00439   */
00440
00441 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00442
00443 /**
00444   * @}
00445   */
00446
00447 /* Exported functions --------------------------------------------------------*/
00448 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00449   * @{
00450   */
00451
00452 /* Initialization/de-initialization functions  ********************************/
00453 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00454 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00455
00456 /* MSP functions  *************************************************************/
00457 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00458 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00459
00460 /* Start/Stop operation functions  *********************************************/
00461 /* ################################# PWM Mode ################################*/
00462 /* Blocking mode: Polling */
00463 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00464 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00465 /* Non-Blocking mode: Interrupt */
00466 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00467 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00468
00469 /* ############################# One Pulse Mode ##############################*/
00470 /* Blocking mode: Polling */
00471 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00472 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00473 /* Non-Blocking mode: Interrupt */
00474 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00475 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00476
00477 /* ############################## Set once Mode ##############################*/
00478 /* Blocking mode: Polling */
00479 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00480 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00481 /* Non-Blocking mode: Interrupt */
00482 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00483 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00484
00485 /* ############################### Encoder Mode ##############################*/
00486 /* Blocking mode: Polling */
00487 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00488 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00489 /* Non-Blocking mode: Interrupt */
00490 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00491 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00492
00493 /* ############################# Time out  Mode ##############################*/
00494 /* Blocking mode: Polling */
00495 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00496 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00497 /* Non-Blocking mode: Interrupt */
00498 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00499 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00500
00501 /* ############################## Counter Mode ###############################*/
00502 /* Blocking mode: Polling */
00503 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00504 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00505 /* Non-Blocking mode: Interrupt */
00506 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00507 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00508
00509 /* Reading operation functions ************************************************/
00510 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
00511 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
00512 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
00513
00514 /* LPTIM IRQ functions  *******************************************************/
00515 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00516
00517 /* CallBack functions  ********************************************************/
00518 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00519 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00520 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00521 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00522 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00523 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00524 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00525
00526 /* Peripheral State functions  ************************************************/
00527 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00528
00529 /**
00530   * @}
00531   */
00532
00533 /* Private types -------------------------------------------------------------*/
00534 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00535   * @{
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /* Private variables ---------------------------------------------------------*/
00543 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00544   * @{
00545   */
00546
00547 /**
00548   * @}
00549   */
00550
00551 /* Private constants ---------------------------------------------------------*/
00552 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00553   * @{
00554   */
00555
00556 /**
00557   * @}
00558   */
00559
00560 /* Private macros ------------------------------------------------------------*/
00561 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00562   * @{
00563   */
00564
00565 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)           (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00566                                                      ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00567
00568 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)     (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00569                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00570                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00571                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00572                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00573                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00574                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00575                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00576 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00577
00578 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)      (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00579                                                      ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00580
00581 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)  (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00582                                                      ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00583                                                      ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00584                                                      ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00585
00586 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)       (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00587                                                      ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00588                                                      ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00589
00590 #define IS_LPTIM_TRG_SOURCE(__TRIG__)               (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00591                                                                                                          ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00592                                                                                                          ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00593                                                                                                          ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00594                                                                                                          ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00595                                                                                                          ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00596                                                                                                          ((__TRIG__) == LPTIM_TRIGSOURCE_5))
00597
00598 #define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)        (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00599                                                      ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00600                                                      ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00601
00602 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)   (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00603                                                      ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00604                                                      ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00605                                                      ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00606
00607 #define IS_LPTIM_UPDATE_MODE(__MODE__)              (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00608                                                      ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00609
00610 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)         (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00611                                                      ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00612
00613 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)         ((__AUTORELOAD__) <= 0x0000FFFF)
00614
00615 #define IS_LPTIM_COMPARE(__COMPARE__)               ((__COMPARE__) <= 0x0000FFFF)
00616
00617 #define IS_LPTIM_PERIOD(PERIOD)               ((PERIOD) <= 0x0000FFFF)
00618
00619 #define IS_LPTIM_PULSE(PULSE)                 ((PULSE) <= 0x0000FFFF)
00620
00621 /**
00622   * @}
00623   */
00624
00625 /* Private functions ---------------------------------------------------------*/
00626 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00627   * @{
00628   */
00629
00630 /**
00631   * @}
00632   */
00633
00634 /**
00635   * @}
00636   */
00637
00638 /**
00639   * @}
00640   */
00641
00642 #ifdef __cplusplus
00643 }
00644 #endif
00645
00646 #endif /* __STM32F7xx_HAL_LPTIM_H */
00647
00648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_ltdc.c Source File

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stm32f7xx_hal_ltdc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_ltdc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   LTDC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the LTDC peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020      (#) Program the required configuration through the following parameters:
00021          the LTDC timing, the horizontal and vertical polarity,
00022          the pixel clock polarity, Data Enable polarity and the LTDC background color value
00023          using HAL_LTDC_Init() function
00024
00025      (#) Program the required configuration through the following parameters:
00026          the pixel format, the blending factors, input alpha value, the window size
00027          and the image size using HAL_LTDC_ConfigLayer() function for foreground
00028          or/and background layer.
00029
00030      (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
00031          HAL_LTDC_EnableCLUT functions.
00032
00033      (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
00034
00035      (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
00036          and HAL_LTDC_EnableColorKeying functions.
00037
00038      (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
00039          function
00040
00041      (#) If needed, reconfigure and change the pixel format value, the alpha value
00042          value, the window size, the window position and the layer start address
00043          for foreground or/and background layer using respectively the following
00044          functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
00045          HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
00046
00047      (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
00048
00049      *** LTDC HAL driver macros list ***
00050      =============================================
00051      [..]
00052        Below the list of most used macros in LTDC HAL driver.
00053
00054       (+) __HAL_LTDC_ENABLE: Enable the LTDC.
00055       (+) __HAL_LTDC_DISABLE: Disable the LTDC.
00056       (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.
00057       (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
00058       (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.
00059       (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
00060       (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
00061       (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
00062       (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
00063       (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
00064
00065      [..]
00066        (@) You can refer to the LTDC HAL driver header file for more useful macros
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f7xx_hal.h"
00101
00102 /** @addtogroup STM32F7xx_HAL_Driver
00103   * @{
00104   */
00105 #if defined (STM32F746xx) || defined (STM32F756xx)
00106
00107 /** @defgroup LTDC LTDC
00108   * @brief LTDC HAL module driver
00109   * @{
00110   */
00111
00112 #ifdef HAL_LTDC_MODULE_ENABLED
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00120 /* Private functions ---------------------------------------------------------*/
00121
00122 /** @defgroup LTDC_Exported_Functions LTDC Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
00127  *  @brief   Initialization and Configuration functions
00128  *
00129 @verbatim
00130  ===============================================================================
00131                 ##### Initialization and Configuration functions #####
00132  ===============================================================================
00133     [..]  This section provides functions allowing to:
00134       (+) Initialize and configure the LTDC
00135       (+) De-initialize the LTDC
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141 /**
00142   * @brief  Initializes the LTDC according to the specified
00143   *         parameters in the LTDC_InitTypeDef and create the associated handle.
00144   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00145   *                the configuration information for the LTDC.
00146   * @retval HAL status
00147   */
00148 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
00149 {
00150   uint32_t tmp = 0, tmp1 = 0;
00151
00152   /* Check the LTDC peripheral state */
00153   if(hltdc == NULL)
00154   {
00155     return HAL_ERROR;
00156   }
00157
00158   /* Check function parameters */
00159   assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
00160   assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
00161   assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
00162   assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
00163   assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
00164   assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
00165   assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
00166   assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
00167   assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
00168   assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
00169   assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
00170   assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
00171   assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
00172
00173   if(hltdc->State == HAL_LTDC_STATE_RESET)
00174   {
00175     /* Allocate lock resource and initialize it */
00176     hltdc->Lock = HAL_UNLOCKED;
00177     /* Init the low level hardware */
00178     HAL_LTDC_MspInit(hltdc);
00179   }
00180
00181   /* Change LTDC peripheral state */
00182   hltdc->State = HAL_LTDC_STATE_BUSY;
00183
00184   /* Configures the HS, VS, DE and PC polarity */
00185   hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
00186   hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
00187   hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
00188
00189   /* Sets Synchronization size */
00190   hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
00191   tmp = (hltdc->Init.HorizontalSync << 16);
00192   hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
00193
00194   /* Sets Accumulated Back porch */
00195   hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
00196   tmp = (hltdc->Init.AccumulatedHBP << 16);
00197   hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
00198
00199   /* Sets Accumulated Active Width */
00200   hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
00201   tmp = (hltdc->Init.AccumulatedActiveW << 16);
00202   hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
00203
00204   /* Sets Total Width */
00205   hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
00206   tmp = (hltdc->Init.TotalWidth << 16);
00207   hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
00208
00209   /* Sets the background color value */
00210   tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);
00211   tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);
00212   hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
00213   hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
00214
00215   /* Enable the transfer Error interrupt */
00216   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);
00217
00218   /* Enable the FIFO underrun interrupt */
00219   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);
00220
00221   /* Enable LTDC by setting LTDCEN bit */
00222   __HAL_LTDC_ENABLE(hltdc);
00223
00224   /* Initialize the error code */
00225   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00226
00227   /* Initialize the LTDC state*/
00228   hltdc->State = HAL_LTDC_STATE_READY;
00229
00230   return HAL_OK;
00231 }
00232
00233 /**
00234   * @brief  Deinitializes the LTDC peripheral registers to their default reset
00235   *         values.
00236   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00237   *                the configuration information for the LTDC.
00238   * @retval None
00239   */
00240
00241 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
00242 {
00243   /* DeInit the low level hardware */
00244   HAL_LTDC_MspDeInit(hltdc);
00245
00246   /* Initialize the error code */
00247   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00248
00249   /* Initialize the LTDC state*/
00250   hltdc->State = HAL_LTDC_STATE_RESET;
00251
00252   /* Release Lock */
00253   __HAL_UNLOCK(hltdc);
00254
00255   return HAL_OK;
00256 }
00257
00258 /**
00259   * @brief  Initializes the LTDC MSP.
00260   * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
00261   *                the configuration information for the LTDC.
00262   * @retval None
00263   */
00264 __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hltdc);
00268
00269   /* NOTE : This function Should not be modified, when the callback is needed,
00270             the HAL_LTDC_MspInit could be implemented in the user file
00271    */
00272 }
00273
00274 /**
00275   * @brief  DeInitializes the LTDC MSP.
00276   * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
00277   *                the configuration information for the LTDC.
00278   * @retval None
00279   */
00280 __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
00281 {
00282   /* Prevent unused argument(s) compilation warning */
00283   UNUSED(hltdc);
00284
00285   /* NOTE : This function Should not be modified, when the callback is needed,
00286             the HAL_LTDC_MspDeInit could be implemented in the user file
00287    */
00288 }
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
00295  *  @brief   IO operation functions
00296  *
00297 @verbatim
00298  ===============================================================================
00299                       #####  IO operation functions  #####
00300  ===============================================================================
00301     [..]  This section provides function allowing to:
00302       (+) Handle LTDC interrupt request
00303
00304 @endverbatim
00305   * @{
00306   */
00307 /**
00308   * @brief  Handles LTDC interrupt request.
00309   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00310   *                the configuration information for the LTDC.
00311   * @retval HAL status
00312   */
00313 void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
00314 {
00315   /* Transfer Error Interrupt management ***************************************/
00316   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)
00317   {
00318     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)
00319     {
00320       /* Disable the transfer Error interrupt */
00321       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
00322
00323       /* Clear the transfer error flag */
00324       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
00325
00326       /* Update error code */
00327       hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
00328
00329       /* Change LTDC state */
00330       hltdc->State = HAL_LTDC_STATE_ERROR;
00331
00332       /* Process unlocked */
00333       __HAL_UNLOCK(hltdc);
00334
00335       /* Transfer error Callback */
00336       HAL_LTDC_ErrorCallback(hltdc);
00337     }
00338   }
00339   /* FIFO underrun Interrupt management ***************************************/
00340   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)
00341   {
00342     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)
00343     {
00344       /* Disable the FIFO underrun interrupt */
00345       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
00346
00347       /* Clear the FIFO underrun flag */
00348       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
00349
00350       /* Update error code */
00351       hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
00352
00353       /* Change LTDC state */
00354       hltdc->State = HAL_LTDC_STATE_ERROR;
00355
00356       /* Process unlocked */
00357       __HAL_UNLOCK(hltdc);
00358
00359       /* Transfer error Callback */
00360       HAL_LTDC_ErrorCallback(hltdc);
00361     }
00362   }
00363   /* Line Interrupt management ************************************************/
00364   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)
00365   {
00366     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)
00367     {
00368       /* Disable the Line interrupt */
00369       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
00370
00371       /* Clear the Line interrupt flag */
00372       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
00373
00374       /* Change LTDC state */
00375       hltdc->State = HAL_LTDC_STATE_READY;
00376
00377       /* Process unlocked */
00378       __HAL_UNLOCK(hltdc);
00379
00380       /* Line interrupt Callback */
00381       HAL_LTDC_LineEvenCallback(hltdc);
00382     }
00383   }
00384 }
00385
00386 /**
00387   * @brief  Error LTDC callback.
00388   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00389   *                the configuration information for the LTDC.
00390   * @retval None
00391   */
00392 __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
00393 {
00394   /* Prevent unused argument(s) compilation warning */
00395   UNUSED(hltdc);
00396
00397   /* NOTE : This function Should not be modified, when the callback is needed,
00398             the HAL_LTDC_ErrorCallback could be implemented in the user file
00399    */
00400 }
00401
00402 /**
00403   * @brief  Line Event callback.
00404   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00405   *                the configuration information for the LTDC.
00406   * @retval None
00407   */
00408 __weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
00409 {
00410   /* Prevent unused argument(s) compilation warning */
00411   UNUSED(hltdc);
00412
00413   /* NOTE : This function Should not be modified, when the callback is needed,
00414             the HAL_LTDC_LineEvenCallback could be implemented in the user file
00415    */
00416 }
00417
00418 /**
00419   * @}
00420   */
00421
00422 /** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
00423  *  @brief    Peripheral Control functions
00424  *
00425 @verbatim
00426  ===============================================================================
00427                     ##### Peripheral Control functions #####
00428  ===============================================================================
00429     [..]  This section provides functions allowing to:
00430       (+) Configure the LTDC foreground or/and background parameters.
00431       (+) Set the active layer.
00432       (+) Configure the color keying.
00433       (+) Configure the C-LUT.
00434       (+) Enable / Disable the color keying.
00435       (+) Enable / Disable the C-LUT.
00436       (+) Update the layer position.
00437       (+) Update the layer size.
00438       (+) Update pixel format on the fly.
00439       (+) Update transparency on the fly.
00440       (+) Update address on the fly.
00441
00442 @endverbatim
00443   * @{
00444   */
00445
00446 /**
00447   * @brief  Configure the LTDC Layer according to the specified
00448   *         parameters in the LTDC_InitTypeDef and create the associated handle.
00449   * @param  hltdc:     pointer to a LTDC_HandleTypeDef structure that contains
00450   *                    the configuration information for the LTDC.
00451   * @param  pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
00452   *                    the configuration information for the Layer.
00453   * @param  LayerIdx:  LTDC Layer index.
00454   *                    This parameter can be one of the following values:
00455   *                    0 or 1
00456   * @retval HAL status
00457   */
00458 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
00459 {
00460   /* Process locked */
00461   __HAL_LOCK(hltdc);
00462
00463   /* Change LTDC peripheral state */
00464   hltdc->State = HAL_LTDC_STATE_BUSY;
00465
00466   /* Check the parameters */
00467   assert_param(IS_LTDC_LAYER(LayerIdx));
00468   assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
00469   assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
00470   assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
00471   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00472   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00473   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00474   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00475   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
00476   assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
00477   assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
00478
00479   /* Copy new layer configuration into handle structure */
00480   hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
00481
00482   /* Configure the LTDC Layer */
00483   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00484
00485   /* Sets the Reload type */
00486   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00487
00488   /* Initialize the LTDC state*/
00489   hltdc->State  = HAL_LTDC_STATE_READY;
00490
00491   /* Process unlocked */
00492   __HAL_UNLOCK(hltdc);
00493
00494   return HAL_OK;
00495 }
00496
00497 /**
00498   * @brief  Configure the color keying.
00499   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00500   *                   the configuration information for the LTDC.
00501   * @param  RGBValue: the color key value
00502   * @param  LayerIdx:  LTDC Layer index.
00503   *                   This parameter can be one of the following values:
00504   *                   0 or 1
00505   * @retval HAL status
00506   */
00507 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
00508 {
00509   /* Process locked */
00510   __HAL_LOCK(hltdc);
00511
00512   /* Change LTDC peripheral state */
00513   hltdc->State = HAL_LTDC_STATE_BUSY;
00514
00515   /* Check the parameters */
00516   assert_param(IS_LTDC_LAYER(LayerIdx));
00517
00518   /* Configures the default color values */
00519   LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
00520   LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
00521
00522   /* Sets the Reload type */
00523   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00524
00525   /* Change the LTDC state*/
00526   hltdc->State = HAL_LTDC_STATE_READY;
00527
00528   /* Process unlocked */
00529   __HAL_UNLOCK(hltdc);
00530
00531   return HAL_OK;
00532 }
00533
00534 /**
00535   * @brief  Load the color lookup table.
00536   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00537   *                   the configuration information for the LTDC.
00538   * @param  pCLUT:    pointer to the color lookup table address.
00539   * @param  CLUTSize: the color lookup table size.
00540   * @param  LayerIdx:  LTDC Layer index.
00541   *                   This parameter can be one of the following values:
00542   *                   0 or 1
00543   * @retval HAL status
00544   */
00545 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
00546 {
00547   uint32_t tmp = 0;
00548   uint32_t counter = 0;
00549   uint32_t pcounter = 0;
00550
00551   /* Process locked */
00552   __HAL_LOCK(hltdc);
00553
00554   /* Change LTDC peripheral state */
00555   hltdc->State = HAL_LTDC_STATE_BUSY;
00556
00557   /* Check the parameters */
00558   assert_param(IS_LTDC_LAYER(LayerIdx));
00559
00560   for(counter = 0; (counter < CLUTSize); counter++)
00561   {
00562     if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
00563     {
00564       tmp  = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
00565     }
00566     else
00567     {
00568       tmp  = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
00569     }
00570     pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
00571     pCLUT = (uint32_t *)pcounter;
00572
00573     /* Specifies the C-LUT address and RGB value */
00574     LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
00575   }
00576
00577   /* Change the LTDC state*/
00578   hltdc->State = HAL_LTDC_STATE_READY;
00579
00580   /* Process unlocked */
00581   __HAL_UNLOCK(hltdc);
00582
00583   return HAL_OK;
00584 }
00585
00586 /**
00587   * @brief  Enable the color keying.
00588   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00589   *                   the configuration information for the LTDC.
00590   * @param  LayerIdx:  LTDC Layer index.
00591   *                   This parameter can be one of the following values:
00592   *                   0 or 1
00593   * @retval  HAL status
00594   */
00595 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00596 {
00597   /* Process locked */
00598   __HAL_LOCK(hltdc);
00599
00600   /* Change LTDC peripheral state */
00601   hltdc->State = HAL_LTDC_STATE_BUSY;
00602
00603   /* Check the parameters */
00604   assert_param(IS_LTDC_LAYER(LayerIdx));
00605
00606   /* Enable LTDC color keying by setting COLKEN bit */
00607   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
00608
00609   /* Sets the Reload type */
00610   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00611
00612   /* Change the LTDC state*/
00613   hltdc->State = HAL_LTDC_STATE_READY;
00614
00615   /* Process unlocked */
00616   __HAL_UNLOCK(hltdc);
00617
00618   return HAL_OK;
00619 }
00620
00621 /**
00622   * @brief  Disable the color keying.
00623   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00624   *                   the configuration information for the LTDC.
00625   * @param  LayerIdx:  LTDC Layer index.
00626   *                   This parameter can be one of the following values:
00627   *                   0 or 1
00628   * @retval  HAL status
00629   */
00630 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00631 {
00632   /* Process locked */
00633   __HAL_LOCK(hltdc);
00634
00635   /* Change LTDC peripheral state */
00636   hltdc->State = HAL_LTDC_STATE_BUSY;
00637
00638   /* Check the parameters */
00639   assert_param(IS_LTDC_LAYER(LayerIdx));
00640
00641   /* Disable LTDC color keying by setting COLKEN bit */
00642   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
00643
00644   /* Sets the Reload type */
00645   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00646
00647   /* Change the LTDC state*/
00648   hltdc->State = HAL_LTDC_STATE_READY;
00649
00650   /* Process unlocked */
00651   __HAL_UNLOCK(hltdc);
00652
00653   return HAL_OK;
00654 }
00655
00656 /**
00657   * @brief  Enable the color lookup table.
00658   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00659   *                   the configuration information for the LTDC.
00660   * @param  LayerIdx:  LTDC Layer index.
00661   *                   This parameter can be one of the following values:
00662   *                   0 or 1
00663   * @retval  HAL status
00664   */
00665 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00666 {
00667
00668   /* Process locked */
00669   __HAL_LOCK(hltdc);
00670
00671   /* Change LTDC peripheral state */
00672   hltdc->State = HAL_LTDC_STATE_BUSY;
00673
00674   /* Check the parameters */
00675   assert_param(IS_LTDC_LAYER(LayerIdx));
00676
00677   /* Disable LTDC color lookup table by setting CLUTEN bit */
00678   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
00679
00680   /* Sets the Reload type */
00681   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00682
00683   /* Change the LTDC state*/
00684   hltdc->State = HAL_LTDC_STATE_READY;
00685
00686   /* Process unlocked */
00687   __HAL_UNLOCK(hltdc);
00688
00689   return HAL_OK;
00690 }
00691
00692 /**
00693   * @brief  Disable the color lookup table.
00694   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00695   *                   the configuration information for the LTDC.
00696   * @param  LayerIdx:  LTDC Layer index.
00697   *                   This parameter can be one of the following values:
00698   *                   0 or 1
00699   * @retval  HAL status
00700   */
00701 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00702 {
00703
00704   /* Process locked */
00705   __HAL_LOCK(hltdc);
00706
00707   /* Change LTDC peripheral state */
00708   hltdc->State = HAL_LTDC_STATE_BUSY;
00709
00710   /* Check the parameters */
00711   assert_param(IS_LTDC_LAYER(LayerIdx));
00712
00713   /* Disable LTDC color lookup table by setting CLUTEN bit */
00714   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
00715
00716   /* Sets the Reload type */
00717   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00718
00719   /* Change the LTDC state*/
00720   hltdc->State = HAL_LTDC_STATE_READY;
00721
00722   /* Process unlocked */
00723   __HAL_UNLOCK(hltdc);
00724
00725   return HAL_OK;
00726 }
00727
00728 /**
00729   * @brief  Enables Dither.
00730   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00731   *                the configuration information for the LTDC.
00732   * @retval  HAL status
00733   */
00734
00735 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
00736 {
00737   /* Process locked */
00738   __HAL_LOCK(hltdc);
00739
00740   /* Change LTDC peripheral state */
00741   hltdc->State = HAL_LTDC_STATE_BUSY;
00742
00743   /* Enable Dither by setting DTEN bit */
00744   LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN;
00745
00746   /* Change the LTDC state*/
00747   hltdc->State = HAL_LTDC_STATE_READY;
00748
00749   /* Process unlocked */
00750   __HAL_UNLOCK(hltdc);
00751
00752   return HAL_OK;
00753 }
00754
00755 /**
00756   * @brief  Disables Dither.
00757   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00758   *                the configuration information for the LTDC.
00759   * @retval  HAL status
00760   */
00761
00762 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
00763 {
00764   /* Process locked */
00765   __HAL_LOCK(hltdc);
00766
00767   /* Change LTDC peripheral state */
00768   hltdc->State = HAL_LTDC_STATE_BUSY;
00769
00770   /* Disable Dither by setting DTEN bit */
00771   LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN;
00772
00773   /* Change the LTDC state*/
00774   hltdc->State = HAL_LTDC_STATE_READY;
00775
00776   /* Process unlocked */
00777   __HAL_UNLOCK(hltdc);
00778
00779   return HAL_OK;
00780 }
00781
00782 /**
00783   * @brief  Set the LTDC window size.
00784   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00785   *                   the configuration information for the LTDC.
00786   * @param  XSize:    LTDC Pixel per line
00787   * @param  YSize:    LTDC Line number
00788   * @param  LayerIdx:  LTDC Layer index.
00789   *                   This parameter can be one of the following values:
00790   *                   0 or 1
00791   * @retval  HAL status
00792   */
00793 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
00794 {
00795   LTDC_LayerCfgTypeDef *pLayerCfg;
00796
00797   /* Process locked */
00798   __HAL_LOCK(hltdc);
00799
00800   /* Change LTDC peripheral state */
00801   hltdc->State = HAL_LTDC_STATE_BUSY;
00802
00803   /* Get layer configuration from handle structure */
00804   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00805
00806   /* Check the parameters (Layers parameters)*/
00807   assert_param(IS_LTDC_LAYER(LayerIdx));
00808   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00809   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00810   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00811   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00812   assert_param(IS_LTDC_CFBLL(XSize));
00813   assert_param(IS_LTDC_CFBLNBR(YSize));
00814
00815   /* update horizontal start/stop */
00816   pLayerCfg->WindowX0 = 0;
00817   pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
00818
00819   /* update vertical start/stop */
00820   pLayerCfg->WindowY0 = 0;
00821   pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
00822
00823   /* Reconfigures the color frame buffer pitch in byte */
00824   pLayerCfg->ImageWidth = XSize;
00825
00826   /* Reconfigures the frame buffer line number */
00827   pLayerCfg->ImageHeight = YSize;
00828
00829   /* Set LTDC parameters */
00830   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00831
00832   /* Sets the Reload type */
00833   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00834
00835   /* Change the LTDC state*/
00836   hltdc->State = HAL_LTDC_STATE_READY;
00837
00838   /* Process unlocked */
00839   __HAL_UNLOCK(hltdc);
00840
00841   return HAL_OK;
00842 }
00843
00844 /**
00845   * @brief  Set the LTDC window position.
00846   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00847   *                   the configuration information for the LTDC.
00848   * @param  X0:       LTDC window X offset
00849   * @param  Y0:       LTDC window Y offset
00850   * @param  LayerIdx:  LTDC Layer index.
00851   *                         This parameter can be one of the following values:
00852   *                         0 or 1
00853   * @retval  HAL status
00854   */
00855 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
00856 {
00857   LTDC_LayerCfgTypeDef *pLayerCfg;
00858
00859   /* Process locked */
00860   __HAL_LOCK(hltdc);
00861
00862   /* Change LTDC peripheral state */
00863   hltdc->State = HAL_LTDC_STATE_BUSY;
00864
00865   /* Get layer configuration from handle structure */
00866   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00867
00868   /* Check the parameters */
00869   assert_param(IS_LTDC_LAYER(LayerIdx));
00870   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00871   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00872   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00873   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00874
00875   /* update horizontal start/stop */
00876   pLayerCfg->WindowX0 = X0;
00877   pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
00878
00879   /* update vertical start/stop */
00880   pLayerCfg->WindowY0 = Y0;
00881   pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
00882
00883   /* Set LTDC parameters */
00884   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00885
00886   /* Sets the Reload type */
00887   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00888
00889   /* Change the LTDC state*/
00890   hltdc->State = HAL_LTDC_STATE_READY;
00891
00892   /* Process unlocked */
00893   __HAL_UNLOCK(hltdc);
00894
00895   return HAL_OK;
00896 }
00897
00898 /**
00899   * @brief  Reconfigure the pixel format.
00900   * @param  hltdc:       pointer to a LTDC_HandleTypeDef structure that contains
00901   *                      the configuration information for the LTDC.
00902   * @param  Pixelformat: new pixel format value.
00903   * @param  LayerIdx:    LTDC Layer index.
00904   *                      This parameter can be one of the following values:
00905   *                      0 or 1.
00906   * @retval  HAL status
00907   */
00908 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
00909 {
00910   LTDC_LayerCfgTypeDef *pLayerCfg;
00911
00912   /* Process locked */
00913   __HAL_LOCK(hltdc);
00914
00915   /* Change LTDC peripheral state */
00916   hltdc->State = HAL_LTDC_STATE_BUSY;
00917
00918   /* Check the parameters */
00919   assert_param(IS_LTDC_LAYER(LayerIdx));
00920   assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
00921
00922   /* Get layer configuration from handle structure */
00923   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00924
00925   /* Reconfigure the pixel format */
00926   pLayerCfg->PixelFormat = Pixelformat;
00927
00928   /* Set LTDC parameters */
00929   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00930
00931   /* Sets the Reload type */
00932   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00933
00934   /* Change the LTDC state*/
00935   hltdc->State = HAL_LTDC_STATE_READY;
00936
00937   /* Process unlocked */
00938   __HAL_UNLOCK(hltdc);
00939
00940   return HAL_OK;
00941 }
00942
00943 /**
00944   * @brief  Reconfigure the layer alpha value.
00945   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00946   *                   the configuration information for the LTDC.
00947   * @param  Alpha:    new alpha value.
00948   * @param  LayerIdx:  LTDC Layer index.
00949   *                   This parameter can be one of the following values:
00950   *                   0 or 1
00951   * @retval  HAL status
00952   */
00953 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
00954 {
00955   LTDC_LayerCfgTypeDef *pLayerCfg;
00956
00957   /* Process locked */
00958   __HAL_LOCK(hltdc);
00959
00960   /* Change LTDC peripheral state */
00961   hltdc->State = HAL_LTDC_STATE_BUSY;
00962
00963   /* Check the parameters */
00964   assert_param(IS_LTDC_ALPHA(Alpha));
00965   assert_param(IS_LTDC_LAYER(LayerIdx));
00966
00967   /* Get layer configuration from handle structure */
00968   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00969
00970   /* Reconfigure the Alpha value */
00971   pLayerCfg->Alpha = Alpha;
00972
00973   /* Set LTDC parameters */
00974   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00975
00976   /* Sets the Reload type */
00977   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00978
00979   /* Change the LTDC state*/
00980   hltdc->State = HAL_LTDC_STATE_READY;
00981
00982   /* Process unlocked */
00983   __HAL_UNLOCK(hltdc);
00984
00985   return HAL_OK;
00986 }
00987 /**
00988   * @brief  Reconfigure the frame buffer Address.
00989   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00990   *                   the configuration information for the LTDC.
00991   * @param  Address:  new address value.
00992   * @param  LayerIdx: LTDC Layer index.
00993   *                   This parameter can be one of the following values:
00994   *                   0 or 1.
00995   * @retval  HAL status
00996   */
00997 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
00998 {
00999   LTDC_LayerCfgTypeDef *pLayerCfg;
01000
01001   /* Process locked */
01002   __HAL_LOCK(hltdc);
01003
01004   /* Change LTDC peripheral state */
01005   hltdc->State = HAL_LTDC_STATE_BUSY;
01006
01007   /* Check the parameters */
01008   assert_param(IS_LTDC_LAYER(LayerIdx));
01009
01010   /* Get layer configuration from handle structure */
01011   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01012
01013   /* Reconfigure the Address */
01014   pLayerCfg->FBStartAdress = Address;
01015
01016   /* Set LTDC parameters */
01017   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01018
01019   /* Sets the Reload type */
01020   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01021
01022   /* Change the LTDC state*/
01023   hltdc->State = HAL_LTDC_STATE_READY;
01024
01025   /* Process unlocked */
01026   __HAL_UNLOCK(hltdc);
01027
01028   return HAL_OK;
01029 }
01030
01031 /**
01032   * @brief  Define the position of the line interrupt .
01033   * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains
01034   *                            the configuration information for the LTDC.
01035   * @param  Line:   Line Interrupt Position.
01036   * @retval  HAL status
01037   */
01038 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
01039 {
01040   /* Process locked */
01041   __HAL_LOCK(hltdc);
01042
01043   /* Change LTDC peripheral state */
01044   hltdc->State = HAL_LTDC_STATE_BUSY;
01045
01046   /* Check the parameters */
01047   assert_param(IS_LTDC_LIPOS(Line));
01048
01049   /* Enable the Line interrupt */
01050   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
01051
01052   /* Sets the Line Interrupt position */
01053   LTDC->LIPCR = (uint32_t)Line;
01054
01055   /* Change the LTDC state*/
01056   hltdc->State = HAL_LTDC_STATE_READY;
01057
01058   /* Process unlocked */
01059   __HAL_UNLOCK(hltdc);
01060
01061   return HAL_OK;
01062 }
01063
01064 /**
01065   * @}
01066   */
01067
01068 /** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
01069  *  @brief    Peripheral State and Errors functions
01070  *
01071 @verbatim
01072  ===============================================================================
01073                   ##### Peripheral State and Errors functions #####
01074  ===============================================================================
01075     [..]
01076     This subsection provides functions allowing to
01077       (+) Check the LTDC state.
01078       (+) Get error code.
01079
01080 @endverbatim
01081   * @{
01082   */
01083
01084 /**
01085   * @brief  Return the LTDC state
01086   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
01087   *                the configuration information for the LTDC.
01088   * @retval HAL state
01089   */
01090 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
01091 {
01092   return hltdc->State;
01093 }
01094
01095 /**
01096 * @brief  Return the LTDC error code
01097 * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
01098   *               the configuration information for the LTDC.
01099 * @retval LTDC Error Code
01100 */
01101 uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
01102 {
01103   return hltdc->ErrorCode;
01104 }
01105
01106 /**
01107   * @}
01108   */
01109
01110 /**
01111   * @brief  Configures the LTDC peripheral
01112   * @param  hltdc   :  Pointer to a LTDC_HandleTypeDef structure that contains
01113   *                   the configuration information for the LTDC.
01114   * @param  pLayerCfg: Pointer LTDC Layer Configuration structure
01115   * @param  LayerIdx:  LTDC Layer index.
01116   *                    This parameter can be one of the following values: 0 or 1
01117   * @retval None
01118   */
01119 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
01120 {
01121   uint32_t tmp = 0;
01122   uint32_t tmp1 = 0;
01123   uint32_t tmp2 = 0;
01124
01125   /* Configures the horizontal start and stop position */
01126   tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);
01127   LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
01128   LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
01129
01130   /* Configures the vertical start and stop position */
01131   tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);
01132   LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
01133   LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);
01134
01135   /* Specifies the pixel format */
01136   LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
01137   LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
01138
01139   /* Configures the default color values */
01140   tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);
01141   tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);
01142   tmp2 = (pLayerCfg->Alpha0 << 24);
01143   LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
01144   LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
01145
01146   /* Specifies the constant alpha value */
01147   LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
01148   LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
01149
01150   /* Specifies the blending factors */
01151   LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
01152   LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
01153
01154   /* Configures the color frame buffer start address */
01155   LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
01156   LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
01157
01158   if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01159   {
01160     tmp = 4;
01161   }
01162   else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01163   {
01164     tmp = 3;
01165   }
01166   else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01167     (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01168       (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01169         (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
01170   {
01171     tmp = 2;
01172   }
01173   else
01174   {
01175     tmp = 1;
01176   }
01177
01178   /* Configures the color frame buffer pitch in byte */
01179   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
01180   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 3));
01181
01182   /* Configures the frame buffer line number */
01183   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
01184   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
01185
01186   /* Enable LTDC_Layer by setting LEN bit */
01187   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
01188 }
01189
01190 /**
01191   * @}
01192   */
01193
01194 #endif /* HAL_LTDC_MODULE_ENABLED */
01195
01196 /**
01197   * @}
01198   */
01199 #endif /* STM32F746xx || STM32F756xx */
01200
01201 /**
01202   * @}
01203   */
01204
01205 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_ltdc.h Source File

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stm32f7xx_hal_ltdc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_ltdc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of LTDC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_LTDC_H
00040 #define __STM32F7xx_HAL_LTDC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F756xx) || defined(STM32F746xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050
00051 /** @addtogroup STM32F7xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @defgroup LTDC LTDC
00056   * @brief LTDC HAL module driver
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup LTDC_Exported_Types LTDC Exported Types
00062   * @{
00063   */
00064 #define MAX_LAYER  2
00065
00066 /**
00067   * @brief  LTDC color structure definition
00068   */
00069 typedef struct
00070 {
00071   uint8_t Blue;                    /*!< Configures the blue value.
00072                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00073
00074   uint8_t Green;                   /*!< Configures the green value.
00075                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00076
00077   uint8_t Red;                     /*!< Configures the red value.
00078                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00079
00080   uint8_t Reserved;                /*!< Reserved 0xFF */
00081 } LTDC_ColorTypeDef;
00082
00083 /**
00084   * @brief  LTDC Init structure definition
00085   */
00086 typedef struct
00087 {
00088   uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
00089                                                       This parameter can be one value of @ref LTDC_HS_POLARITY */
00090
00091   uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
00092                                                       This parameter can be one value of @ref LTDC_VS_POLARITY */
00093
00094   uint32_t            DEPolarity;                /*!< configures the data enable polarity.
00095                                                       This parameter can be one of value of @ref LTDC_DE_POLARITY */
00096
00097   uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.
00098                                                       This parameter can be one of value of @ref LTDC_PC_POLARITY */
00099
00100   uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
00101                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00102
00103   uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
00104                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00105
00106   uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
00107                                                       This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
00108
00109   uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
00110                                                       This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
00111
00112   uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
00113                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
00114
00115   uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
00116                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
00117
00118   uint32_t            TotalWidth;                /*!< configures the total width.
00119                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
00120
00121   uint32_t            TotalHeigh;                /*!< configures the total height.
00122                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
00123
00124   LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
00125 } LTDC_InitTypeDef;
00126
00127 /**
00128   * @brief  LTDC Layer structure definition
00129   */
00130 typedef struct
00131 {
00132   uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
00133                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00134
00135   uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
00136                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00137
00138   uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
00139                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00140
00141   uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
00142                                             This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
00143
00144   uint32_t PixelFormat;                /*!< Specifies the pixel format.
00145                                             This parameter can be one of value of @ref LTDC_Pixelformat */
00146
00147   uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
00148                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00149
00150   uint32_t Alpha0;                     /*!< Configures the default alpha value.
00151                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00152
00153   uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
00154                                             This parameter can be one of value of @ref LTDC_BlendingFactor1 */
00155
00156   uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
00157                                             This parameter can be one of value of @ref LTDC_BlendingFactor2 */
00158
00159   uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
00160
00161   uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
00162                                             This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
00163
00164   uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
00165                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00166
00167   LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
00168 } LTDC_LayerCfgTypeDef;
00169
00170 /**
00171   * @brief  HAL LTDC State structures definition
00172   */
00173 typedef enum
00174 {
00175   HAL_LTDC_STATE_RESET             = 0x00,    /*!< LTDC not yet initialized or disabled */
00176   HAL_LTDC_STATE_READY             = 0x01,    /*!< LTDC initialized and ready for use   */
00177   HAL_LTDC_STATE_BUSY              = 0x02,    /*!< LTDC internal process is ongoing     */
00178   HAL_LTDC_STATE_TIMEOUT           = 0x03,    /*!< LTDC Timeout state                   */
00179   HAL_LTDC_STATE_ERROR             = 0x04     /*!< LTDC state error                     */
00180 }HAL_LTDC_StateTypeDef;
00181
00182 /**
00183   * @brief  LTDC handle Structure definition
00184   */
00185 typedef struct
00186 {
00187   LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
00188
00189   LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
00190
00191   LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
00192
00193   HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
00194
00195   __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
00196
00197   __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
00198
00199 } LTDC_HandleTypeDef;
00200 /**
00201   * @}
00202   */
00203
00204 /* Exported constants --------------------------------------------------------*/
00205 /** @defgroup LTDC_Exported_Constants LTDC Exported Constants
00206   * @{
00207   */
00208
00209 /** @defgroup LTDC_Error_Code LTDC Error Code
00210   * @{
00211   */
00212 #define HAL_LTDC_ERROR_NONE      ((uint32_t)0x00000000)    /*!< LTDC No error             */
00213 #define HAL_LTDC_ERROR_TE        ((uint32_t)0x00000001)    /*!< LTDC Transfer error       */
00214 #define HAL_LTDC_ERROR_FU        ((uint32_t)0x00000002)    /*!< LTDC FIFO Underrun        */
00215 #define HAL_LTDC_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< LTDC Timeout error        */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
00221   * @{
00222   */
00223 #define LTDC_HSPOLARITY_AL                ((uint32_t)0x00000000)                /*!< Horizontal Synchronization is active low. */
00224 #define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
00230   * @{
00231   */
00232 #define LTDC_VSPOLARITY_AL                ((uint32_t)0x00000000)                /*!< Vertical Synchronization is active low. */
00233 #define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
00239   * @{
00240   */
00241 #define LTDC_DEPOLARITY_AL                ((uint32_t)0x00000000)                /*!< Data Enable, is active low. */
00242 #define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
00248   * @{
00249   */
00250 #define LTDC_PCPOLARITY_IPC               ((uint32_t)0x00000000)                /*!< input pixel clock. */
00251 #define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup LTDC_SYNC LTDC SYNC
00257   * @{
00258   */
00259 #define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16)                 /*!< Horizontal synchronization width. */
00260 #define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH                         /*!< Vertical synchronization height. */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
00266   * @{
00267   */
00268 #define LTDC_COLOR                   ((uint32_t)0x000000FF)                     /*!< Color mask */
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
00274   * @{
00275   */
00276 #define LTDC_BLENDING_FACTOR1_CA                       ((uint32_t)0x00000400)   /*!< Blending factor : Cte Alpha */
00277 #define LTDC_BLENDING_FACTOR1_PAxCA                    ((uint32_t)0x00000600)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
00283   * @{
00284   */
00285 #define LTDC_BLENDING_FACTOR2_CA                       ((uint32_t)0x00000005)   /*!< Blending factor : Cte Alpha */
00286 #define LTDC_BLENDING_FACTOR2_PAxCA                    ((uint32_t)0x00000007)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup LTDC_Pixelformat LTDC Pixel format
00292   * @{
00293   */
00294 #define LTDC_PIXEL_FORMAT_ARGB8888                  ((uint32_t)0x00000000)      /*!< ARGB8888 LTDC pixel format */
00295 #define LTDC_PIXEL_FORMAT_RGB888                    ((uint32_t)0x00000001)      /*!< RGB888 LTDC pixel format   */
00296 #define LTDC_PIXEL_FORMAT_RGB565                    ((uint32_t)0x00000002)      /*!< RGB565 LTDC pixel format   */
00297 #define LTDC_PIXEL_FORMAT_ARGB1555                  ((uint32_t)0x00000003)      /*!< ARGB1555 LTDC pixel format */
00298 #define LTDC_PIXEL_FORMAT_ARGB4444                  ((uint32_t)0x00000004)      /*!< ARGB4444 LTDC pixel format */
00299 #define LTDC_PIXEL_FORMAT_L8                        ((uint32_t)0x00000005)      /*!< L8 LTDC pixel format       */
00300 #define LTDC_PIXEL_FORMAT_AL44                      ((uint32_t)0x00000006)      /*!< AL44 LTDC pixel format     */
00301 #define LTDC_PIXEL_FORMAT_AL88                      ((uint32_t)0x00000007)      /*!< AL88 LTDC pixel format     */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup LTDC_Alpha LTDC Alpha
00307   * @{
00308   */
00309 #define LTDC_ALPHA               LTDC_LxCACR_CONSTA                             /*!< LTDC Cte Alpha mask */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup LTDC_LAYER_Config LTDC LAYER Config
00315   * @{
00316   */
00317 #define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16)          /*!< LTDC Layer stop position  */
00318 #define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS                  /*!< LTDC Layer start position */
00319
00320 #define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL                    /*!< LTDC Layer Line length    */
00321 #define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR                 /*!< LTDC Layer Line number    */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup LTDC_Interrupts LTDC Interrupts
00327   * @{
00328   */
00329 #define LTDC_IT_LI                      LTDC_IER_LIE
00330 #define LTDC_IT_FU                      LTDC_IER_FUIE
00331 #define LTDC_IT_TE                      LTDC_IER_TERRIE
00332 #define LTDC_IT_RR                      LTDC_IER_RRIE
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup LTDC_Flag LTDC Flag
00338   * @{
00339   */
00340 #define LTDC_FLAG_LI                     LTDC_ISR_LIF
00341 #define LTDC_FLAG_FU                     LTDC_ISR_FUIF
00342 #define LTDC_FLAG_TE                     LTDC_ISR_TERRIF
00343 #define LTDC_FLAG_RR                     LTDC_ISR_RRIF
00344 /**
00345   * @}
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /* Exported macro ------------------------------------------------------------*/
00353 /** @defgroup LTDC_Exported_Macros LTDC Exported Macros
00354   * @{
00355   */
00356
00357 /** @brief Reset LTDC handle state
00358   * @param  __HANDLE__: specifies the LTDC handle.
00359   * @retval None
00360   */
00361 #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
00362
00363 /**
00364   * @brief  Enable the LTDC.
00365   * @param  __HANDLE__: LTDC handle
00366   * @retval None.
00367   */
00368 #define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
00369
00370 /**
00371   * @brief  Disable the LTDC.
00372   * @param  __HANDLE__: LTDC handle
00373   * @retval None.
00374   */
00375 #define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
00376
00377 /**
00378   * @brief  Enable the LTDC Layer.
00379   * @param  __HANDLE__: LTDC handle
00380   * @param  __LAYER__: Specify the layer to be enabled
00381   *                     This parameter can be 0 or 1
00382   * @retval None.
00383   */
00384 #define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
00385
00386 /**
00387   * @brief  Disable the LTDC Layer.
00388   * @param  __HANDLE__: LTDC handle
00389   * @param  __LAYER__: Specify the layer to be disabled
00390   *                     This parameter can be 0 or 1
00391   * @retval None.
00392   */
00393 #define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
00394
00395 /**
00396   * @brief  Reload  Layer Configuration.
00397   * @param  __HANDLE__: LTDC handle
00398   * @retval None.
00399   */
00400 #define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__)   ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
00401
00402 /* Interrupt & Flag management */
00403 /**
00404   * @brief  Get the LTDC pending flags.
00405   * @param  __HANDLE__: LTDC handle
00406   * @param  __FLAG__: Get the specified flag.
00407   *          This parameter can be any combination of the following values:
00408   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00409   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00410   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00411   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00412   * @retval The state of FLAG (SET or RESET).
00413   */
00414 #define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00415
00416 /**
00417   * @brief  Clears the LTDC pending flags.
00418   * @param  __HANDLE__: LTDC handle
00419   * @param  __FLAG__: specifies the flag to clear.
00420   *          This parameter can be any combination of the following values:
00421   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00422   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00423   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00424   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00425   * @retval None
00426   */
00427 #define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00428
00429 /**
00430   * @brief  Enables the specified LTDC interrupts.
00431   * @param  __HANDLE__: LTDC handle
00432   * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
00433   *          This parameter can be any combination of the following values:
00434   *            @arg LTDC_IT_LI: Line Interrupt flag
00435   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00436   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00437   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00438   * @retval None
00439   */
00440 #define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00441
00442 /**
00443   * @brief  Disables the specified LTDC interrupts.
00444   * @param  __HANDLE__: LTDC handle
00445   * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
00446   *          This parameter can be any combination of the following values:
00447   *            @arg LTDC_IT_LI: Line Interrupt flag
00448   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00449   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00450   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00451   * @retval None
00452   */
00453 #define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00454
00455 /**
00456   * @brief  Checks whether the specified LTDC interrupt has occurred or not.
00457   * @param  __HANDLE__: LTDC handle
00458   * @param  __INTERRUPT__: specifies the LTDC interrupt source to check.
00459   *          This parameter can be one of the following values:
00460   *            @arg LTDC_IT_LI: Line Interrupt flag
00461   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00462   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00463   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00464   * @retval The state of INTERRUPT (SET or RESET).
00465   */
00466 #define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
00467 /**
00468   * @}
00469   */
00470 /* Exported functions --------------------------------------------------------*/
00471 /** @addtogroup LTDC_Exported_Functions
00472   * @{
00473   */
00474 /** @addtogroup LTDC_Exported_Functions_Group1
00475   * @{
00476   */
00477 /* Initialization and de-initialization functions *****************************/
00478 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
00479 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
00480 void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
00481 void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
00482 void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
00483 void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
00484 /**
00485   * @}
00486   */
00487
00488 /** @addtogroup LTDC_Exported_Functions_Group2
00489   * @{
00490   */
00491 /* IO operation functions *****************************************************/
00492 void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
00493 /**
00494   * @}
00495   */
00496
00497 /** @addtogroup LTDC_Exported_Functions_Group3
00498   * @{
00499   */
00500 /* Peripheral Control functions ***********************************************/
00501 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00502 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
00503 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
00504 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
00505 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
00506 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
00507 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
00508 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
00509 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00510 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00511 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00512 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00513 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
00514 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
00515 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
00516 /**
00517   * @}
00518   */
00519
00520 /** @addtogroup LTDC_Exported_Functions_Group4
00521   * @{
00522   */
00523 /* Peripheral State functions *************************************************/
00524 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
00525 uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
00526 /**
00527   * @}
00528   */
00529
00530 /**
00531   * @}
00532   */
00533 /* Private types -------------------------------------------------------------*/
00534 /** @defgroup LTDC_Private_Types LTDC Private Types
00535   * @{
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /* Private variables ---------------------------------------------------------*/
00543 /** @defgroup LTDC_Private_Variables LTDC Private Variables
00544   * @{
00545   */
00546
00547 /**
00548   * @}
00549   */
00550
00551 /* Private constants ---------------------------------------------------------*/
00552 /** @defgroup LTDC_Private_Constants LTDC Private Constants
00553   * @{
00554   */
00555
00556 /**
00557   * @}
00558   */
00559
00560 /* Private macros ------------------------------------------------------------*/
00561 /** @defgroup LTDC_Private_Macros LTDC Private Macros
00562   * @{
00563   */
00564 #define LTDC_LAYER(__HANDLE__, __LAYER__)         ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
00565 #define IS_LTDC_LAYER(LAYER)                      ((LAYER) <= MAX_LAYER)
00566 #define IS_LTDC_HSPOL(HSPOL)                      (((HSPOL) == LTDC_HSPOLARITY_AL) || \
00567                                                    ((HSPOL) == LTDC_HSPOLARITY_AH))
00568 #define IS_LTDC_VSPOL(VSPOL)                      (((VSPOL) == LTDC_VSPOLARITY_AL) || \
00569                                                    ((VSPOL) == LTDC_VSPOLARITY_AH))
00570 #define IS_LTDC_DEPOL(DEPOL)                      (((DEPOL) ==  LTDC_DEPOLARITY_AL) || \
00571                                                    ((DEPOL) ==  LTDC_DEPOLARITY_AH))
00572 #define IS_LTDC_PCPOL(PCPOL)                      (((PCPOL) ==  LTDC_PCPOLARITY_IPC) || \
00573                                                    ((PCPOL) ==  LTDC_PCPOLARITY_IIPC))
00574 #define IS_LTDC_HSYNC(HSYNC)                      ((HSYNC)  <= LTDC_HORIZONTALSYNC)
00575 #define IS_LTDC_VSYNC(VSYNC)                      ((VSYNC)  <= LTDC_VERTICALSYNC)
00576 #define IS_LTDC_AHBP(AHBP)                        ((AHBP)   <= LTDC_HORIZONTALSYNC)
00577 #define IS_LTDC_AVBP(AVBP)                        ((AVBP)   <= LTDC_VERTICALSYNC)
00578 #define IS_LTDC_AAW(AAW)                          ((AAW)    <= LTDC_HORIZONTALSYNC)
00579 #define IS_LTDC_AAH(AAH)                          ((AAH)    <= LTDC_VERTICALSYNC)
00580 #define IS_LTDC_TOTALW(TOTALW)                    ((TOTALW) <= LTDC_HORIZONTALSYNC)
00581 #define IS_LTDC_TOTALH(TOTALH)                    ((TOTALH) <= LTDC_VERTICALSYNC)
00582 #define IS_LTDC_BLUEVALUE(BBLUE)                  ((BBLUE)  <= LTDC_COLOR)
00583 #define IS_LTDC_GREENVALUE(BGREEN)                ((BGREEN) <= LTDC_COLOR)
00584 #define IS_LTDC_REDVALUE(BRED)                    ((BRED)   <= LTDC_COLOR)
00585 #define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
00586                                                    ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
00587 #define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
00588                                                    ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
00589 #define IS_LTDC_PIXEL_FORMAT(Pixelformat)         (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888)   || \
00590                                                    ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565)   || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
00591                                                    ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8)       || \
00592                                                    ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44)     || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
00593 #define IS_LTDC_ALPHA(ALPHA)                      ((ALPHA) <= LTDC_ALPHA)
00594 #define IS_LTDC_HCONFIGST(HCONFIGST)              ((HCONFIGST) <= LTDC_STARTPOSITION)
00595 #define IS_LTDC_HCONFIGSP(HCONFIGSP)              ((HCONFIGSP) <= LTDC_STOPPOSITION)
00596 #define IS_LTDC_VCONFIGST(VCONFIGST)              ((VCONFIGST) <= LTDC_STARTPOSITION)
00597 #define IS_LTDC_VCONFIGSP(VCONFIGSP)              ((VCONFIGSP) <= LTDC_STOPPOSITION)
00598 #define IS_LTDC_CFBP(CFBP)                        ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
00599 #define IS_LTDC_CFBLL(CFBLL)                      ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
00600 #define IS_LTDC_CFBLNBR(CFBLNBR)                  ((CFBLNBR) <= LTDC_LINE_NUMBER)
00601 #define IS_LTDC_LIPOS(LIPOS)                      ((LIPOS) <= 0x7FF)
00602 /**
00603   * @}
00604   */
00605
00606 /* Private functions ---------------------------------------------------------*/
00607 /** @defgroup LTDC_Private_Functions LTDC Private Functions
00608   * @{
00609   */
00610
00611 /**
00612   * @}
00613   */
00614
00615 /**
00616   * @}
00617   */
00618 #endif /* STM32F746xx || STM32F756xx */
00619 /**
00620   * @}
00621   */
00622
00623 #ifdef __cplusplus
00624 }
00625 #endif
00626
00627 #endif /* __STM32F7xx_HAL_LTDC_H */
00628
00629 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nand.c Source File

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stm32f7xx_hal_nand.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   NAND HAL module driver.
00008   *          This file provides a generic firmware to drive NAND memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                          ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NAND flash memories. It uses the FMC/FSMC layer functions to interface
00018       with NAND devices. This driver is used as follows:
00019
00020       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00021           with control and timing parameters for both common and attribute spaces.
00022
00023       (+) Read NAND flash memory maker and device IDs using the function
00024           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NAND flash memory by read/write operations using the functions
00028           HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
00029           to read/write page(s)/spare area(s). These functions use specific device
00030           information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
00031           structure. The read/write address information is contained by the Nand_Address_Typedef
00032           structure passed as parameter.
00033
00034       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00035
00036       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00037           The erase block address information is contained in the Nand_Address_Typedef
00038           structure passed as parameter.
00039
00040       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00041
00042       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00043           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00044           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00045
00046       (+) You can monitor the NAND device HAL state by calling the function
00047           HAL_NAND_GetState()
00048
00049     [..]
00050       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00051           If a NAND flash device contains different operations and/or implementations,
00052           it should be implemented separately.
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32f7xx_hal.h"
00087
00088 /** @addtogroup STM32F7xx_HAL_Driver
00089   * @{
00090   */
00091
00092
00093 #ifdef HAL_NAND_MODULE_ENABLED
00094
00095 /** @defgroup NAND NAND
00096   * @brief NAND HAL module driver
00097   * @{
00098   */
00099
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private Constants ------------------------------------------------------------*/
00102 /* Private macro -------------------------------------------------------------*/
00103 /* Private variables ---------------------------------------------------------*/
00104 /* Private function prototypes -----------------------------------------------*/
00105 /* Exported functions ---------------------------------------------------------*/
00106
00107 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00108   * @{
00109   */
00110
00111 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00112   * @brief    Initialization and Configuration functions
00113   *
00114   @verbatim
00115   ==============================================================================
00116             ##### NAND Initialization and de-initialization functions #####
00117   ==============================================================================
00118   [..]
00119     This section provides functions allowing to initialize/de-initialize
00120     the NAND memory
00121
00122 @endverbatim
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  Perform NAND memory Initialization sequence
00128   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00129   *                the configuration information for NAND module.
00130   * @param  ComSpace_Timing: pointer to Common space timing structure
00131   * @param  AttSpace_Timing: pointer to Attribute space timing structure
00132   * @retval HAL status
00133   */
00134 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00135 {
00136   /* Check the NAND handle state */
00137   if(hnand == NULL)
00138   {
00139      return HAL_ERROR;
00140   }
00141
00142   if(hnand->State == HAL_NAND_STATE_RESET)
00143   {
00144     /* Allocate lock resource and initialize it */
00145     hnand->Lock = HAL_UNLOCKED;
00146     /* Initialize the low level hardware (MSP) */
00147     HAL_NAND_MspInit(hnand);
00148   }
00149
00150   /* Initialize NAND control Interface */
00151   FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00152
00153   /* Initialize NAND common space timing Interface */
00154   FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00155
00156   /* Initialize NAND attribute space timing Interface */
00157   FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00158
00159   /* Enable the NAND device */
00160   __FMC_NAND_ENABLE(hnand->Instance);
00161
00162   /* Update the NAND controller state */
00163   hnand->State = HAL_NAND_STATE_READY;
00164
00165   return HAL_OK;
00166 }
00167
00168 /**
00169   * @brief  Perform NAND memory De-Initialization sequence
00170   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00171   *                the configuration information for NAND module.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00175 {
00176   /* Initialize the low level hardware (MSP) */
00177   HAL_NAND_MspDeInit(hnand);
00178
00179   /* Configure the NAND registers with their reset values */
00180   FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00181
00182   /* Reset the NAND controller state */
00183   hnand->State = HAL_NAND_STATE_RESET;
00184
00185   /* Release Lock */
00186   __HAL_UNLOCK(hnand);
00187
00188   return HAL_OK;
00189 }
00190
00191 /**
00192   * @brief  NAND MSP Init
00193   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00194   *                the configuration information for NAND module.
00195   * @retval None
00196   */
00197 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00198 {
00199   /* Prevent unused argument(s) compilation warning */
00200   UNUSED(hnand);
00201
00202   /* NOTE : This function Should not be modified, when the callback is needed,
00203             the HAL_NAND_MspInit could be implemented in the user file
00204    */
00205 }
00206
00207 /**
00208   * @brief  NAND MSP DeInit
00209   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00210   *                the configuration information for NAND module.
00211   * @retval None
00212   */
00213 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00214 {
00215   /* Prevent unused argument(s) compilation warning */
00216   UNUSED(hnand);
00217
00218   /* NOTE : This function Should not be modified, when the callback is needed,
00219             the HAL_NAND_MspDeInit could be implemented in the user file
00220    */
00221 }
00222
00223
00224 /**
00225   * @brief  This function handles NAND device interrupt request.
00226   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00227   *                the configuration information for NAND module.
00228   * @retval HAL status
00229 */
00230 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00231 {
00232   /* Check NAND interrupt Rising edge flag */
00233   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00234   {
00235     /* NAND interrupt callback*/
00236     HAL_NAND_ITCallback(hnand);
00237
00238     /* Clear NAND interrupt Rising edge pending bit */
00239     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
00240   }
00241
00242   /* Check NAND interrupt Level flag */
00243   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00244   {
00245     /* NAND interrupt callback*/
00246     HAL_NAND_ITCallback(hnand);
00247
00248     /* Clear NAND interrupt Level pending bit */
00249     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
00250   }
00251
00252   /* Check NAND interrupt Falling edge flag */
00253   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00254   {
00255     /* NAND interrupt callback*/
00256     HAL_NAND_ITCallback(hnand);
00257
00258     /* Clear NAND interrupt Falling edge pending bit */
00259     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
00260   }
00261
00262   /* Check NAND interrupt FIFO empty flag */
00263   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00264   {
00265     /* NAND interrupt callback*/
00266     HAL_NAND_ITCallback(hnand);
00267
00268     /* Clear NAND interrupt FIFO empty pending bit */
00269     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
00270   }
00271
00272 }
00273
00274 /**
00275   * @brief  NAND interrupt feature callback
00276   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00277   *                the configuration information for NAND module.
00278   * @retval None
00279   */
00280 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00281 {
00282   /* Prevent unused argument(s) compilation warning */
00283   UNUSED(hnand);
00284
00285   /* NOTE : This function Should not be modified, when the callback is needed,
00286             the HAL_NAND_ITCallback could be implemented in the user file
00287    */
00288 }
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00295   * @brief    Input Output and memory control functions
00296   *
00297   @verbatim
00298   ==============================================================================
00299                     ##### NAND Input and Output functions #####
00300   ==============================================================================
00301   [..]
00302     This section provides functions allowing to use and control the NAND
00303     memory
00304
00305 @endverbatim
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Read the NAND memory electronic signature
00311   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00312   *                the configuration information for NAND module.
00313   * @param  pNAND_ID: NAND ID structure
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00317 {
00318   __IO uint32_t data = 0;
00319   uint32_t deviceAddress = 0;
00320
00321   /* Process Locked */
00322   __HAL_LOCK(hnand);
00323
00324   /* Check the NAND controller state */
00325   if(hnand->State == HAL_NAND_STATE_BUSY)
00326   {
00327      return HAL_BUSY;
00328   }
00329
00330   /* Identify the device address */
00331   deviceAddress = NAND_DEVICE;
00332
00333   /* Update the NAND controller state */
00334   hnand->State = HAL_NAND_STATE_BUSY;
00335
00336   /* Send Read ID command sequence */
00337   *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_READID;
00338   *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00339
00340   /* Read the electronic signature from NAND flash */
00341   data = *(__IO uint32_t *)deviceAddress;
00342
00343   /* Return the data read */
00344   pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00345   pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00346   pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00347   pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00348
00349   /* Update the NAND controller state */
00350   hnand->State = HAL_NAND_STATE_READY;
00351
00352   /* Process unlocked */
00353   __HAL_UNLOCK(hnand);
00354
00355   return HAL_OK;
00356 }
00357
00358 /**
00359   * @brief  NAND memory reset
00360   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00361   *                the configuration information for NAND module.
00362   * @retval HAL status
00363   */
00364 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00365 {
00366   uint32_t deviceAddress = 0;
00367
00368   /* Process Locked */
00369   __HAL_LOCK(hnand);
00370
00371   /* Check the NAND controller state */
00372   if(hnand->State == HAL_NAND_STATE_BUSY)
00373   {
00374      return HAL_BUSY;
00375   }
00376
00377   /* Identify the device address */
00378   deviceAddress = NAND_DEVICE;
00379
00380   /* Update the NAND controller state */
00381   hnand->State = HAL_NAND_STATE_BUSY;
00382
00383   /* Send NAND reset command */
00384   *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
00385
00386
00387   /* Update the NAND controller state */
00388   hnand->State = HAL_NAND_STATE_READY;
00389
00390   /* Process unlocked */
00391   __HAL_UNLOCK(hnand);
00392
00393   return HAL_OK;
00394
00395 }
00396
00397 /**
00398   * @brief  Read Page(s) from NAND memory block
00399   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00400   *                the configuration information for NAND module.
00401   * @param  pAddress : pointer to NAND address structure
00402   * @param  pBuffer : pointer to destination read buffer
00403   * @param  NumPageToRead : number of pages to read from block
00404   * @retval HAL status
00405   */
00406 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00407 {
00408   __IO uint32_t index  = 0;
00409   uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
00410
00411   /* Process Locked */
00412   __HAL_LOCK(hnand);
00413
00414   /* Check the NAND controller state */
00415   if(hnand->State == HAL_NAND_STATE_BUSY)
00416   {
00417      return HAL_BUSY;
00418   }
00419
00420   /* Identify the device address */
00421   deviceAddress = NAND_DEVICE;
00422
00423   /* Update the NAND controller state */
00424   hnand->State = HAL_NAND_STATE_BUSY;
00425
00426   /* NAND raw address calculation */
00427   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00428
00429   /* Page(s) read loop */
00430   while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
00431   {
00432     /* update the buffer size */
00433     size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
00434
00435     /* Send read page command sequence */
00436     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00437
00438     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00439     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00440     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00441     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00442
00443     /* for 512 and 1 GB devices, 4th cycle is required */
00444     if(hnand->Info.BlockNbr >= 1024)
00445     {
00446       *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
00447     }
00448
00449     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00450
00451     /* Get Data into Buffer */
00452     for(index = 0; index < size; index++)
00453     {
00454       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
00455     }
00456
00457     /* Increment read pages number */
00458     numPagesRead++;
00459
00460     /* Decrement pages to read */
00461     NumPageToRead--;
00462
00463     /* Increment the NAND address */
00464     nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
00465
00466   }
00467
00468   /* Update the NAND controller state */
00469   hnand->State = HAL_NAND_STATE_READY;
00470
00471   /* Process unlocked */
00472   __HAL_UNLOCK(hnand);
00473
00474   return HAL_OK;
00475
00476 }
00477
00478 /**
00479   * @brief  Write Page(s) to NAND memory block
00480   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00481   *                the configuration information for NAND module.
00482   * @param  pAddress : pointer to NAND address structure
00483   * @param  pBuffer : pointer to source buffer to write
00484   * @param  NumPageToWrite  : number of pages to write to block
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00488 {
00489   __IO uint32_t index = 0;
00490   uint32_t tickstart = 0;
00491   uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
00492
00493   /* Process Locked */
00494   __HAL_LOCK(hnand);
00495
00496   /* Check the NAND controller state */
00497   if(hnand->State == HAL_NAND_STATE_BUSY)
00498   {
00499      return HAL_BUSY;
00500   }
00501
00502   /* Identify the device address */
00503   deviceAddress = NAND_DEVICE;
00504
00505   /* Update the NAND controller state */
00506   hnand->State = HAL_NAND_STATE_BUSY;
00507
00508   /* NAND raw address calculation */
00509   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00510
00511   /* Page(s) write loop */
00512   while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
00513   {
00514     /* update the buffer size */
00515     size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
00516
00517     /* Send write page command sequence */
00518     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
00519     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
00520
00521     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00522     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00523     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00524     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00525     __DSB();
00526
00527     /* for 512 and 1 GB devices, 4th cycle is required */
00528     if(hnand->Info.BlockNbr >= 1024)
00529     {
00530       *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
00531       __DSB();
00532     }
00533
00534     /* Write data to memory */
00535     for(index = 0; index < size; index++)
00536     {
00537       *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
00538       __DSB();
00539     }
00540
00541     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00542
00543     /* Read status until NAND is ready */
00544     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00545     {
00546       /* Get tick */
00547       tickstart = HAL_GetTick();
00548
00549       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00550       {
00551         return HAL_TIMEOUT;
00552       }
00553     }
00554
00555     /* Increment written pages number */
00556     numPagesWritten++;
00557
00558     /* Decrement pages to write */
00559     NumPageToWrite--;
00560
00561     /* Increment the NAND address */
00562     nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
00563   }
00564
00565   /* Update the NAND controller state */
00566   hnand->State = HAL_NAND_STATE_READY;
00567
00568   /* Process unlocked */
00569   __HAL_UNLOCK(hnand);
00570
00571   return HAL_OK;
00572 }
00573
00574 /**
00575   * @brief  Read Spare area(s) from NAND memory
00576   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00577   *                the configuration information for NAND module.
00578   * @param  pAddress : pointer to NAND address structure
00579   * @param  pBuffer: pointer to source buffer to write
00580   * @param  NumSpareAreaToRead: Number of spare area to read
00581   * @retval HAL status
00582 */
00583 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
00584 {
00585   __IO uint32_t index = 0;
00586   uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
00587
00588   /* Process Locked */
00589   __HAL_LOCK(hnand);
00590
00591   /* Check the NAND controller state */
00592   if(hnand->State == HAL_NAND_STATE_BUSY)
00593   {
00594      return HAL_BUSY;
00595   }
00596
00597   /* Identify the device address */
00598   deviceAddress = NAND_DEVICE;
00599
00600   /* Update the NAND controller state */
00601   hnand->State = HAL_NAND_STATE_BUSY;
00602
00603   /* NAND raw address calculation */
00604   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00605
00606   /* Spare area(s) read loop */
00607   while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
00608   {
00609
00610     /* update the buffer size */
00611     size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
00612
00613     /* Send read spare area command sequence */
00614     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
00615
00616     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00617     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00618     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00619     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00620
00621     /* for 512 and 1 GB devices, 4th cycle is required */
00622     if(hnand->Info.BlockNbr >= 1024)
00623     {
00624       *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
00625     }
00626
00627     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
00628
00629     /* Get Data into Buffer */
00630     for(index = 0; index < size; index++)
00631     {
00632       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
00633     }
00634
00635     /* Increment read spare areas number */
00636     numSpareAreaRead++;
00637
00638     /* Decrement spare areas to read */
00639     NumSpareAreaToRead--;
00640
00641     /* Increment the NAND address */
00642     nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
00643   }
00644
00645   /* Update the NAND controller state */
00646   hnand->State = HAL_NAND_STATE_READY;
00647
00648   /* Process unlocked */
00649   __HAL_UNLOCK(hnand);
00650
00651   return HAL_OK;
00652 }
00653
00654 /**
00655   * @brief  Write Spare area(s) to NAND memory
00656   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00657   *                the configuration information for NAND module.
00658   * @param  pAddress : pointer to NAND address structure
00659   * @param  pBuffer : pointer to source buffer to write
00660   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
00661   * @retval HAL status
00662   */
00663 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
00664 {
00665   __IO uint32_t index = 0;
00666   uint32_t tickstart = 0;
00667   uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
00668
00669   /* Process Locked */
00670   __HAL_LOCK(hnand);
00671
00672   /* Check the NAND controller state */
00673   if(hnand->State == HAL_NAND_STATE_BUSY)
00674   {
00675      return HAL_BUSY;
00676   }
00677
00678   /* Identify the device address */
00679   deviceAddress = NAND_DEVICE;
00680
00681   /* Update the FMC_NAND controller state */
00682   hnand->State = HAL_NAND_STATE_BUSY;
00683
00684   /* NAND raw address calculation */
00685   nandAddress = ARRAY_ADDRESS(pAddress, hnand);
00686
00687   /* Spare area(s) write loop */
00688   while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
00689   {
00690     /* update the buffer size */
00691     size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
00692
00693     /* Send write Spare area command sequence */
00694     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
00695     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
00696
00697     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
00698     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
00699     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
00700     *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
00701     __DSB();
00702     /* for 512 and 1 GB devices, 4th cycle is required */
00703     if(hnand->Info.BlockNbr >= 1024)
00704     {
00705       *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
00706       __DSB();
00707     }
00708
00709     /* Write data to memory */
00710     for(index = 0; index < size; index++)
00711     {
00712       *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
00713       __DSB();
00714     }
00715
00716     *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00717     __DSB();
00718
00719     /* Read status until NAND is ready */
00720     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00721     {
00722       /* Get tick */
00723       tickstart = HAL_GetTick();
00724
00725       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00726       {
00727         return HAL_TIMEOUT;
00728       }
00729     }
00730
00731     /* Increment written spare areas number */
00732     numSpareAreaWritten++;
00733
00734     /* Decrement spare areas to write */
00735     NumSpareAreaTowrite--;
00736
00737     /* Increment the NAND address */
00738     nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
00739   }
00740
00741   /* Update the NAND controller state */
00742   hnand->State = HAL_NAND_STATE_READY;
00743
00744   /* Process unlocked */
00745   __HAL_UNLOCK(hnand);
00746
00747   return HAL_OK;
00748 }
00749
00750 /**
00751   * @brief  NAND memory Block erase
00752   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00753   *                the configuration information for NAND module.
00754   * @param  pAddress : pointer to NAND address structure
00755   * @retval HAL status
00756   */
00757 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
00758 {
00759   uint32_t DeviceAddress = 0;
00760
00761   /* Process Locked */
00762   __HAL_LOCK(hnand);
00763
00764   /* Check the NAND controller state */
00765   if(hnand->State == HAL_NAND_STATE_BUSY)
00766   {
00767      return HAL_BUSY;
00768   }
00769
00770   /* Identify the device address */
00771   DeviceAddress = NAND_DEVICE;
00772
00773   /* Update the NAND controller state */
00774   hnand->State = HAL_NAND_STATE_BUSY;
00775
00776   /* Send Erase block command sequence */
00777   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
00778
00779   *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00780   *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00781   *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00782   __DSB();
00783
00784   /* for 512 and 1 GB devices, 4th cycle is required */
00785   if(hnand->Info.BlockNbr >= 1024)
00786   {
00787     *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00788     __DSB();
00789   }
00790
00791   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
00792   __DSB();
00793
00794   /* Update the NAND controller state */
00795   hnand->State = HAL_NAND_STATE_READY;
00796
00797   /* Process unlocked */
00798   __HAL_UNLOCK(hnand);
00799
00800   return HAL_OK;
00801 }
00802
00803 /**
00804   * @brief  NAND memory read status
00805   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00806   *                the configuration information for NAND module.
00807   * @retval NAND status
00808   */
00809 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
00810 {
00811   uint32_t data = 0;
00812   uint32_t DeviceAddress = 0;
00813
00814   /* Identify the device address */
00815    DeviceAddress = NAND_DEVICE;
00816
00817   /* Send Read status operation command */
00818   *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
00819
00820   /* Read status register data */
00821   data = *(__IO uint8_t *)DeviceAddress;
00822
00823   /* Return the status */
00824   if((data & NAND_ERROR) == NAND_ERROR)
00825   {
00826     return NAND_ERROR;
00827   }
00828   else if((data & NAND_READY) == NAND_READY)
00829   {
00830     return NAND_READY;
00831   }
00832
00833   return NAND_BUSY;
00834 }
00835
00836 /**
00837   * @brief  Increment the NAND memory address
00838   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00839   *                the configuration information for NAND module.
00840   * @param pAddress: pointer to NAND address structure
00841   * @retval The new status of the increment address operation. It can be:
00842   *           - NAND_VALID_ADDRESS: When the new address is valid address
00843   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
00844   */
00845 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
00846 {
00847   uint32_t status = NAND_VALID_ADDRESS;
00848
00849   /* Increment page address */
00850   pAddress->Page++;
00851
00852   /* Check NAND address is valid */
00853   if(pAddress->Page == hnand->Info.BlockSize)
00854   {
00855     pAddress->Page = 0;
00856     pAddress->Block++;
00857
00858     if(pAddress->Block == hnand->Info.ZoneSize)
00859     {
00860       pAddress->Block = 0;
00861       pAddress->Zone++;
00862
00863       if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
00864       {
00865         status = NAND_INVALID_ADDRESS;
00866       }
00867     }
00868   }
00869
00870   return (status);
00871 }
00872 /**
00873   * @}
00874   */
00875
00876 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
00877  *  @brief   management functions
00878  *
00879 @verbatim
00880   ==============================================================================
00881                          ##### NAND Control functions #####
00882   ==============================================================================
00883   [..]
00884     This subsection provides a set of functions allowing to control dynamically
00885     the NAND interface.
00886
00887 @endverbatim
00888   * @{
00889   */
00890
00891
00892 /**
00893   * @brief  Enables dynamically NAND ECC feature.
00894   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00895   *                the configuration information for NAND module.
00896   * @retval HAL status
00897   */
00898 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
00899 {
00900   /* Check the NAND controller state */
00901   if(hnand->State == HAL_NAND_STATE_BUSY)
00902   {
00903      return HAL_BUSY;
00904   }
00905
00906   /* Update the NAND state */
00907   hnand->State = HAL_NAND_STATE_BUSY;
00908
00909   /* Enable ECC feature */
00910   FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
00911
00912   /* Update the NAND state */
00913   hnand->State = HAL_NAND_STATE_READY;
00914
00915   return HAL_OK;
00916 }
00917
00918 /**
00919   * @brief  Disables dynamically FMC_NAND ECC feature.
00920   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00921   *                the configuration information for NAND module.
00922   * @retval HAL status
00923   */
00924 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
00925 {
00926   /* Check the NAND controller state */
00927   if(hnand->State == HAL_NAND_STATE_BUSY)
00928   {
00929      return HAL_BUSY;
00930   }
00931
00932   /* Update the NAND state */
00933   hnand->State = HAL_NAND_STATE_BUSY;
00934
00935   /* Disable ECC feature */
00936   FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
00937
00938   /* Update the NAND state */
00939   hnand->State = HAL_NAND_STATE_READY;
00940
00941   return HAL_OK;
00942 }
00943
00944 /**
00945   * @brief  Disables dynamically NAND ECC feature.
00946   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00947   *                the configuration information for NAND module.
00948   * @param  ECCval: pointer to ECC value
00949   * @param  Timeout: maximum timeout to wait
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
00953 {
00954   HAL_StatusTypeDef status = HAL_OK;
00955
00956   /* Check the NAND controller state */
00957   if(hnand->State == HAL_NAND_STATE_BUSY)
00958   {
00959      return HAL_BUSY;
00960   }
00961
00962   /* Update the NAND state */
00963   hnand->State = HAL_NAND_STATE_BUSY;
00964
00965   /* Get NAND ECC value */
00966   status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
00967
00968   /* Update the NAND state */
00969   hnand->State = HAL_NAND_STATE_READY;
00970
00971   return status;
00972 }
00973
00974 /**
00975   * @}
00976   */
00977
00978
00979 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
00980  *  @brief   Peripheral State functions
00981  *
00982 @verbatim
00983   ==============================================================================
00984                          ##### NAND State functions #####
00985   ==============================================================================
00986   [..]
00987     This subsection permits to get in run-time the status of the NAND controller
00988     and the data flow.
00989
00990 @endverbatim
00991   * @{
00992   */
00993
00994 /**
00995   * @brief  return the NAND state
00996   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00997   *                the configuration information for NAND module.
00998   * @retval HAL state
00999   */
01000 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
01001 {
01002   return hnand->State;
01003 }
01004
01005 /**
01006   * @}
01007   */
01008
01009 /**
01010   * @}
01011   */
01012
01013 #endif /* HAL_NAND_MODULE_ENABLED  */
01014
01015 /**
01016   * @}
01017   */
01018
01019 /**
01020   * @}
01021   */
01022
01023 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nand.h Source File

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stm32f7xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of NAND HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_NAND_H
00040 #define __STM32F7xx_HAL_NAND_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_fmc.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup NAND
00054   * @{
00055   */
00056
00057 /* Exported typedef ----------------------------------------------------------*/
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup NAND_Exported_Types NAND Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL NAND State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
00069   HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
00070   HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
00071   HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
00072 }HAL_NAND_StateTypeDef;
00073
00074 /**
00075   * @brief  NAND Memory electronic signature Structure definition
00076   */
00077 typedef struct
00078 {
00079   /*<! NAND memory electronic signature maker and device IDs */
00080
00081   uint8_t Maker_Id;
00082
00083   uint8_t Device_Id;
00084
00085   uint8_t Third_Id;
00086
00087   uint8_t Fourth_Id;
00088 }NAND_IDTypeDef;
00089
00090 /**
00091   * @brief  NAND Memory address Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint16_t Page;   /*!< NAND memory Page address  */
00096
00097   uint16_t Zone;   /*!< NAND memory Zone address  */
00098
00099   uint16_t Block;  /*!< NAND memory Block address */
00100
00101 }NAND_AddressTypeDef;
00102
00103 /**
00104   * @brief  NAND Memory info Structure definition
00105   */
00106 typedef struct
00107 {
00108   uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
00109
00110   uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
00111
00112   uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
00113
00114   uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
00115
00116   uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
00117 }NAND_InfoTypeDef;
00118
00119 /**
00120   * @brief  NAND handle Structure definition
00121   */
00122 typedef struct
00123 {
00124   FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
00125
00126   FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
00127
00128   HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
00129
00130   __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
00131
00132   NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
00133 }NAND_HandleTypeDef;
00134 /**
00135   * @}
00136   */
00137
00138 /* Exported constants --------------------------------------------------------*/
00139 /* Exported macro ------------------------------------------------------------*/
00140 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00141  * @{
00142  */
00143
00144 /** @brief Reset NAND handle state
00145   * @param  __HANDLE__: specifies the NAND handle.
00146   * @retval None
00147   */
00148 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Exported functions --------------------------------------------------------*/
00155 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00156   * @{
00157   */
00158
00159 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00160   * @{
00161   */
00162
00163 /* Initialization/de-initialization functions  ********************************/
00164 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00165 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00166 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00167 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00168 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00169 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00170
00171 /**
00172   * @}
00173   */
00174
00175 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00176   * @{
00177   */
00178
00179 /* IO operation functions  ****************************************************/
00180 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00181 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00182 HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00183 HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00184 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00185 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00186 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00187 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00188 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00189
00190 /**
00191   * @}
00192   */
00193
00194 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00195   * @{
00196   */
00197
00198 /* NAND Control functions  ****************************************************/
00199 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00200 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00201 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00202
00203 /**
00204   * @}
00205   */
00206
00207 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00208   * @{
00209   */
00210 /* NAND State functions *******************************************************/
00211 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00212 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00213 /**
00214   * @}
00215   */
00216
00217 /**
00218   * @}
00219   */
00220 /* Private types -------------------------------------------------------------*/
00221 /* Private variables ---------------------------------------------------------*/
00222 /* Private constants ---------------------------------------------------------*/
00223 /** @defgroup NAND_Private_Constants NAND Private Constants
00224   * @{
00225   */
00226 #define NAND_DEVICE                ((uint32_t)0x80000000)
00227 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000)
00228
00229 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
00230 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
00231
00232 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
00233 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
00234 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
00235 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
00236
00237 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
00238 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
00239 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
00240 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
00241 #define NAND_CMD_READID            ((uint8_t)0x90)
00242 #define NAND_CMD_STATUS            ((uint8_t)0x70)
00243 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
00244 #define NAND_CMD_RESET             ((uint8_t)0xFF)
00245
00246 /* NAND memory status */
00247 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
00248 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
00249 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
00250 #define NAND_BUSY                  ((uint32_t)0x00000000)
00251 #define NAND_ERROR                 ((uint32_t)0x00000001)
00252 #define NAND_READY                 ((uint32_t)0x00000040)
00253 /**
00254   * @}
00255   */
00256
00257 /* Private macros ------------------------------------------------------------*/
00258 /** @defgroup NAND_Private_Macros NAND Private Macros
00259   * @{
00260   */
00261
00262 /**
00263   * @brief  NAND memory address computation.
00264   * @param  __ADDRESS__: NAND memory address.
00265   * @param  __HANDLE__ : NAND handle.
00266   * @retval NAND Raw address value
00267   */
00268 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00269                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
00270
00271 /**
00272   * @brief  NAND memory address cycling.
00273   * @param  __ADDRESS__: NAND memory address.
00274   * @retval NAND address cycling value.
00275   */
00276 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
00277 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
00278 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
00279 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 #ifdef __cplusplus
00296 }
00297 #endif
00298
00299 #endif /* __STM32F7xx_HAL_NAND_H */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nor.c Source File

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stm32f7xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   NOR HAL module driver.
00008   *          This file provides a generic firmware to drive NOR memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                      ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NOR flash memories. It uses the FMC layer functions to interface
00018       with NOR devices. This driver is used as follows:
00019
00020       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00021           with control and timing parameters for both normal and extended mode.
00022
00023       (+) Read NOR flash memory manufacturer code and device IDs using the function
00024           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NOR flash memory by read/write data unit operations using the functions
00028           HAL_NOR_Read(), HAL_NOR_Program().
00029
00030       (+) Perform NOR flash erase block/chip operations using the functions
00031           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00032
00033       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00034           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00035           structure declared by the function caller.
00036
00037       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00038           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00039
00040       (+) You can monitor the NOR device HAL state by calling the function
00041           HAL_NOR_GetState()
00042     [..]
00043      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00044          If a NOR flash device contains different operations and/or implementations,
00045          it should be implemented separately.
00046
00047      *** NOR HAL driver macros list ***
00048      =============================================
00049      [..]
00050        Below the list of most used macros in NOR HAL driver.
00051
00052       (+) NOR_WRITE : NOR memory write data to specified address
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32f7xx_hal.h"
00087
00088 /** @addtogroup STM32F7xx_HAL_Driver
00089   * @{
00090   */
00091
00092 /** @defgroup NOR NOR
00093   * @brief NOR driver modules
00094   * @{
00095   */
00096 #ifdef HAL_NOR_MODULE_ENABLED
00097
00098 /* Private typedef -----------------------------------------------------------*/
00099 /* Private define ------------------------------------------------------------*/
00100
00101 /** @defgroup NOR_Private_Defines NOR Private Defines
00102   * @{
00103   */
00104
00105 /* Constants to define address to set to write a command */
00106 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00107 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00108 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00109 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00110 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00111 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00112 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00113
00114 /* Constants to define data to program a command */
00115 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00116 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00117 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00118 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00119 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00123 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00124 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00125
00126 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00128 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00129
00130 /* Mask on NOR STATUS REGISTER */
00131 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00132 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Private macro -------------------------------------------------------------*/
00139 /* Private variables ---------------------------------------------------------*/
00140 /* Private functions ---------------------------------------------------------*/
00141 /* Exported functions --------------------------------------------------------*/
00142 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00143   * @{
00144   */
00145
00146 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00147   * @brief    Initialization and Configuration functions
00148   *
00149   @verbatim
00150   ==============================================================================
00151            ##### NOR Initialization and de_initialization functions #####
00152   ==============================================================================
00153   [..]
00154     This section provides functions allowing to initialize/de-initialize
00155     the NOR memory
00156
00157 @endverbatim
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Perform the NOR memory Initialization sequence
00163   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00164   *                the configuration information for NOR module.
00165   * @param  Timing: pointer to NOR control timing structure
00166   * @param  ExtTiming: pointer to NOR extended mode timing structure
00167   * @retval HAL status
00168   */
00169 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00170 {
00171   /* Check the NOR handle parameter */
00172   if(hnor == NULL)
00173   {
00174      return HAL_ERROR;
00175   }
00176
00177   if(hnor->State == HAL_NOR_STATE_RESET)
00178   {
00179     /* Allocate lock resource and initialize it */
00180     hnor->Lock = HAL_UNLOCKED;
00181     /* Initialize the low level hardware (MSP) */
00182     HAL_NOR_MspInit(hnor);
00183   }
00184
00185   /* Initialize NOR control Interface */
00186   FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00187
00188   /* Initialize NOR timing Interface */
00189   FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00190
00191   /* Initialize NOR extended mode timing Interface */
00192   FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00193
00194   /* Enable the NORSRAM device */
00195   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00196
00197   /* Check the NOR controller state */
00198   hnor->State = HAL_NOR_STATE_READY;
00199
00200   return HAL_OK;
00201 }
00202
00203 /**
00204   * @brief  Perform NOR memory De-Initialization sequence
00205   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00206   *                the configuration information for NOR module.
00207   * @retval HAL status
00208   */
00209 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00210 {
00211   /* De-Initialize the low level hardware (MSP) */
00212   HAL_NOR_MspDeInit(hnor);
00213
00214   /* Configure the NOR registers with their reset values */
00215   FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00216
00217   /* Update the NOR controller state */
00218   hnor->State = HAL_NOR_STATE_RESET;
00219
00220   /* Release Lock */
00221   __HAL_UNLOCK(hnor);
00222
00223   return HAL_OK;
00224 }
00225
00226 /**
00227   * @brief  NOR MSP Init
00228   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00229   *                the configuration information for NOR module.
00230   * @retval None
00231   */
00232 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00233 {
00234   /* Prevent unused argument(s) compilation warning */
00235   UNUSED(hnor);
00236
00237   /* NOTE : This function Should not be modified, when the callback is needed,
00238             the HAL_NOR_MspInit could be implemented in the user file
00239    */
00240 }
00241
00242 /**
00243   * @brief  NOR MSP DeInit
00244   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00245   *                the configuration information for NOR module.
00246   * @retval None
00247   */
00248 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00249 {
00250   /* Prevent unused argument(s) compilation warning */
00251   UNUSED(hnor);
00252
00253   /* NOTE : This function Should not be modified, when the callback is needed,
00254             the HAL_NOR_MspDeInit could be implemented in the user file
00255    */
00256 }
00257
00258 /**
00259   * @brief  NOR MSP Wait for Ready/Busy signal
00260   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00261   *                the configuration information for NOR module.
00262   * @param  Timeout: Maximum timeout value
00263   * @retval None
00264   */
00265 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00266 {
00267   /* Prevent unused argument(s) compilation warning */
00268   UNUSED(hnor);
00269
00270   /* NOTE : This function Should not be modified, when the callback is needed,
00271             the HAL_NOR_MspWait could be implemented in the user file
00272    */
00273 }
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00280   * @brief    Input Output and memory control functions
00281   *
00282   @verbatim
00283   ==============================================================================
00284                 ##### NOR Input and Output functions #####
00285   ==============================================================================
00286   [..]
00287     This section provides functions allowing to use and control the NOR memory
00288
00289 @endverbatim
00290   * @{
00291   */
00292
00293 /**
00294   * @brief  Read NOR flash IDs
00295   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00296   *                the configuration information for NOR module.
00297   * @param  pNOR_ID : pointer to NOR ID structure
00298   * @retval HAL status
00299   */
00300 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00301 {
00302   uint32_t deviceaddress = 0;
00303
00304   /* Process Locked */
00305   __HAL_LOCK(hnor);
00306
00307   /* Check the NOR controller state */
00308   if(hnor->State == HAL_NOR_STATE_BUSY)
00309   {
00310      return HAL_BUSY;
00311   }
00312
00313   /* Select the NOR device address */
00314   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00315   {
00316     deviceaddress = NOR_MEMORY_ADRESS1;
00317   }
00318   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00319   {
00320     deviceaddress = NOR_MEMORY_ADRESS2;
00321   }
00322   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00323   {
00324     deviceaddress = NOR_MEMORY_ADRESS3;
00325   }
00326   else /* FMC_NORSRAM_BANK4 */
00327   {
00328     deviceaddress = NOR_MEMORY_ADRESS4;
00329   }
00330
00331   /* Update the NOR controller state */
00332   hnor->State = HAL_NOR_STATE_BUSY;
00333
00334   /* Send read ID command */
00335   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00336   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00337   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00338
00339   /* Read the NOR IDs */
00340   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
00341   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
00342   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
00343   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
00344
00345   /* Check the NOR controller state */
00346   hnor->State = HAL_NOR_STATE_READY;
00347
00348   /* Process unlocked */
00349   __HAL_UNLOCK(hnor);
00350
00351   return HAL_OK;
00352 }
00353
00354 /**
00355   * @brief  Returns the NOR memory to Read mode.
00356   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00357   *                the configuration information for NOR module.
00358   * @retval HAL status
00359   */
00360 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00361 {
00362   uint32_t deviceaddress = 0;
00363
00364   /* Process Locked */
00365   __HAL_LOCK(hnor);
00366
00367   /* Check the NOR controller state */
00368   if(hnor->State == HAL_NOR_STATE_BUSY)
00369   {
00370      return HAL_BUSY;
00371   }
00372
00373   /* Select the NOR device address */
00374   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00375   {
00376     deviceaddress = NOR_MEMORY_ADRESS1;
00377   }
00378   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00379   {
00380     deviceaddress = NOR_MEMORY_ADRESS2;
00381   }
00382   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00383   {
00384     deviceaddress = NOR_MEMORY_ADRESS3;
00385   }
00386   else /* FMC_NORSRAM_BANK4 */
00387   {
00388     deviceaddress = NOR_MEMORY_ADRESS4;
00389   }
00390
00391   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00392
00393   /* Check the NOR controller state */
00394   hnor->State = HAL_NOR_STATE_READY;
00395
00396   /* Process unlocked */
00397   __HAL_UNLOCK(hnor);
00398
00399   return HAL_OK;
00400 }
00401
00402 /**
00403   * @brief  Read data from NOR memory
00404   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00405   *                the configuration information for NOR module.
00406   * @param  pAddress: pointer to Device address
00407   * @param  pData : pointer to read data
00408   * @retval HAL status
00409   */
00410 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00411 {
00412   uint32_t deviceaddress = 0;
00413
00414   /* Process Locked */
00415   __HAL_LOCK(hnor);
00416
00417   /* Check the NOR controller state */
00418   if(hnor->State == HAL_NOR_STATE_BUSY)
00419   {
00420      return HAL_BUSY;
00421   }
00422
00423   /* Select the NOR device address */
00424   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00425   {
00426     deviceaddress = NOR_MEMORY_ADRESS1;
00427   }
00428   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00429   {
00430     deviceaddress = NOR_MEMORY_ADRESS2;
00431   }
00432   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00433   {
00434     deviceaddress = NOR_MEMORY_ADRESS3;
00435   }
00436   else /* FMC_NORSRAM_BANK4 */
00437   {
00438     deviceaddress = NOR_MEMORY_ADRESS4;
00439   }
00440
00441   /* Update the NOR controller state */
00442   hnor->State = HAL_NOR_STATE_BUSY;
00443
00444   /* Send read data command */
00445   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00446   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00447   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
00448
00449   /* Read the data */
00450   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
00451
00452   /* Check the NOR controller state */
00453   hnor->State = HAL_NOR_STATE_READY;
00454
00455   /* Process unlocked */
00456   __HAL_UNLOCK(hnor);
00457
00458   return HAL_OK;
00459 }
00460
00461 /**
00462   * @brief  Program data to NOR memory
00463   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00464   *                the configuration information for NOR module.
00465   * @param  pAddress: Device address
00466   * @param  pData : pointer to the data to write
00467   * @retval HAL status
00468   */
00469 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00470 {
00471   uint32_t deviceaddress = 0;
00472
00473   /* Process Locked */
00474   __HAL_LOCK(hnor);
00475
00476   /* Check the NOR controller state */
00477   if(hnor->State == HAL_NOR_STATE_BUSY)
00478   {
00479      return HAL_BUSY;
00480   }
00481
00482   /* Select the NOR device address */
00483   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00484   {
00485     deviceaddress = NOR_MEMORY_ADRESS1;
00486   }
00487   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00488   {
00489     deviceaddress = NOR_MEMORY_ADRESS2;
00490   }
00491   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00492   {
00493     deviceaddress = NOR_MEMORY_ADRESS3;
00494   }
00495   else /* FMC_NORSRAM_BANK4 */
00496   {
00497     deviceaddress = NOR_MEMORY_ADRESS4;
00498   }
00499
00500   /* Update the NOR controller state */
00501   hnor->State = HAL_NOR_STATE_BUSY;
00502
00503   /* Send program data command */
00504   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00505   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00506   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00507
00508   /* Write the data */
00509   NOR_WRITE(pAddress, *pData);
00510
00511   /* Check the NOR controller state */
00512   hnor->State = HAL_NOR_STATE_READY;
00513
00514   /* Process unlocked */
00515   __HAL_UNLOCK(hnor);
00516
00517   return HAL_OK;
00518 }
00519
00520 /**
00521   * @brief  Reads a half-word buffer from the NOR memory.
00522   * @param  hnor: pointer to the NOR handle
00523   * @param  uwAddress: NOR memory internal address to read from.
00524   * @param  pData: pointer to the buffer that receives the data read from the
00525   *         NOR memory.
00526   * @param  uwBufferSize : number of Half word to read.
00527   * @retval HAL status
00528   */
00529 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00530 {
00531   uint32_t deviceaddress = 0;
00532
00533   /* Process Locked */
00534   __HAL_LOCK(hnor);
00535
00536   /* Check the NOR controller state */
00537   if(hnor->State == HAL_NOR_STATE_BUSY)
00538   {
00539      return HAL_BUSY;
00540   }
00541
00542   /* Select the NOR device address */
00543   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00544   {
00545     deviceaddress = NOR_MEMORY_ADRESS1;
00546   }
00547   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00548   {
00549     deviceaddress = NOR_MEMORY_ADRESS2;
00550   }
00551   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00552   {
00553     deviceaddress = NOR_MEMORY_ADRESS3;
00554   }
00555   else /* FMC_NORSRAM_BANK4 */
00556   {
00557     deviceaddress = NOR_MEMORY_ADRESS4;
00558   }
00559
00560   /* Update the NOR controller state */
00561   hnor->State = HAL_NOR_STATE_BUSY;
00562
00563   /* Send read data command */
00564   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00565   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00566   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
00567
00568   /* Read buffer */
00569   while( uwBufferSize > 0)
00570   {
00571     *pData++ = *(__IO uint16_t *)uwAddress;
00572     uwAddress += 2;
00573     uwBufferSize--;
00574   }
00575
00576   /* Check the NOR controller state */
00577   hnor->State = HAL_NOR_STATE_READY;
00578
00579   /* Process unlocked */
00580   __HAL_UNLOCK(hnor);
00581
00582   return HAL_OK;
00583 }
00584
00585 /**
00586   * @brief  Writes a half-word buffer to the NOR memory. This function must be used
00587             only with S29GL128P NOR memory.
00588   * @param  hnor: pointer to the NOR handle
00589   * @param  uwAddress: NOR memory internal start write address
00590   * @param  pData: pointer to source data buffer.
00591   * @param  uwBufferSize: Size of the buffer to write
00592   * @retval HAL status
00593   */
00594 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00595 {
00596   uint16_t * p_currentaddress = (uint16_t *)NULL;
00597   uint16_t * p_endaddress = (uint16_t *)NULL;
00598   uint32_t lastloadedaddress = 0, deviceaddress = 0;
00599
00600   /* Process Locked */
00601   __HAL_LOCK(hnor);
00602
00603   /* Check the NOR controller state */
00604   if(hnor->State == HAL_NOR_STATE_BUSY)
00605   {
00606      return HAL_BUSY;
00607   }
00608
00609   /* Select the NOR device address */
00610   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00611   {
00612     deviceaddress = NOR_MEMORY_ADRESS1;
00613   }
00614   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00615   {
00616     deviceaddress = NOR_MEMORY_ADRESS2;
00617   }
00618   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00619   {
00620     deviceaddress = NOR_MEMORY_ADRESS3;
00621   }
00622   else /* FMC_NORSRAM_BANK4 */
00623   {
00624     deviceaddress = NOR_MEMORY_ADRESS4;
00625   }
00626
00627   /* Update the NOR controller state */
00628   hnor->State = HAL_NOR_STATE_BUSY;
00629
00630   /* Initialize variables */
00631   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
00632   p_endaddress      = p_currentaddress + (uwBufferSize-1);
00633   lastloadedaddress = (uint32_t)(uwAddress);
00634
00635   /* Issue unlock command sequence */
00636   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00637   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00638
00639   /* Write Buffer Load Command */
00640   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00641   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
00642
00643   /* Load Data into NOR Buffer */
00644   while(p_currentaddress <= p_endaddress)
00645   {
00646     /* Store last loaded address & data value (for polling) */
00647      lastloadedaddress = (uint32_t)p_currentaddress;
00648
00649     NOR_WRITE(p_currentaddress, *pData++);
00650
00651     p_currentaddress ++;
00652   }
00653
00654   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00655
00656   /* Check the NOR controller state */
00657   hnor->State = HAL_NOR_STATE_READY;
00658
00659   /* Process unlocked */
00660   __HAL_UNLOCK(hnor);
00661
00662   return HAL_OK;
00663
00664 }
00665
00666 /**
00667   * @brief  Erase the specified block of the NOR memory
00668   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00669   *                the configuration information for NOR module.
00670   * @param  BlockAddress : Block to erase address
00671   * @param  Address: Device address
00672   * @retval HAL status
00673   */
00674 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00675 {
00676   uint32_t deviceaddress = 0;
00677
00678   /* Process Locked */
00679   __HAL_LOCK(hnor);
00680
00681   /* Check the NOR controller state */
00682   if(hnor->State == HAL_NOR_STATE_BUSY)
00683   {
00684      return HAL_BUSY;
00685   }
00686
00687   /* Select the NOR device address */
00688   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00689   {
00690     deviceaddress = NOR_MEMORY_ADRESS1;
00691   }
00692   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00693   {
00694     deviceaddress = NOR_MEMORY_ADRESS2;
00695   }
00696   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00697   {
00698     deviceaddress = NOR_MEMORY_ADRESS3;
00699   }
00700   else /* FMC_NORSRAM_BANK4 */
00701   {
00702     deviceaddress = NOR_MEMORY_ADRESS4;
00703   }
00704
00705   /* Update the NOR controller state */
00706   hnor->State = HAL_NOR_STATE_BUSY;
00707
00708   /* Send block erase command sequence */
00709   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00710   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00711   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00712   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00713   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00714   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00715
00716   /* Check the NOR memory status and update the controller state */
00717   hnor->State = HAL_NOR_STATE_READY;
00718
00719   /* Process unlocked */
00720   __HAL_UNLOCK(hnor);
00721
00722   return HAL_OK;
00723
00724 }
00725
00726 /**
00727   * @brief  Erase the entire NOR chip.
00728   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00729   *                the configuration information for NOR module.
00730   * @param  Address : Device address
00731   * @retval HAL status
00732   */
00733 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00734 {
00735   uint32_t deviceaddress = 0;
00736
00737   /* Process Locked */
00738   __HAL_LOCK(hnor);
00739
00740   /* Check the NOR controller state */
00741   if(hnor->State == HAL_NOR_STATE_BUSY)
00742   {
00743      return HAL_BUSY;
00744   }
00745
00746   /* Select the NOR device address */
00747   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00748   {
00749     deviceaddress = NOR_MEMORY_ADRESS1;
00750   }
00751   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00752   {
00753     deviceaddress = NOR_MEMORY_ADRESS2;
00754   }
00755   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00756   {
00757     deviceaddress = NOR_MEMORY_ADRESS3;
00758   }
00759   else /* FMC_NORSRAM_BANK4 */
00760   {
00761     deviceaddress = NOR_MEMORY_ADRESS4;
00762   }
00763
00764   /* Update the NOR controller state */
00765   hnor->State = HAL_NOR_STATE_BUSY;
00766
00767   /* Send NOR chip erase command sequence */
00768   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00769   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00770   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00771   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00772   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00773   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00774
00775   /* Check the NOR memory status and update the controller state */
00776   hnor->State = HAL_NOR_STATE_READY;
00777
00778   /* Process unlocked */
00779   __HAL_UNLOCK(hnor);
00780
00781   return HAL_OK;
00782 }
00783
00784 /**
00785   * @brief  Read NOR flash CFI IDs
00786   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00787   *                the configuration information for NOR module.
00788   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
00789   * @retval HAL status
00790   */
00791 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00792 {
00793   uint32_t deviceaddress = 0;
00794
00795   /* Process Locked */
00796   __HAL_LOCK(hnor);
00797
00798   /* Check the NOR controller state */
00799   if(hnor->State == HAL_NOR_STATE_BUSY)
00800   {
00801      return HAL_BUSY;
00802   }
00803
00804   /* Select the NOR device address */
00805   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00806   {
00807     deviceaddress = NOR_MEMORY_ADRESS1;
00808   }
00809   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00810   {
00811     deviceaddress = NOR_MEMORY_ADRESS2;
00812   }
00813   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00814   {
00815     deviceaddress = NOR_MEMORY_ADRESS3;
00816   }
00817   else /* FMC_NORSRAM_BANK4 */
00818   {
00819     deviceaddress = NOR_MEMORY_ADRESS4;
00820   }
00821
00822   /* Update the NOR controller state */
00823   hnor->State = HAL_NOR_STATE_BUSY;
00824
00825   /* Send read CFI query command */
00826   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00827
00828   /* read the NOR CFI information */
00829   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
00830   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
00831   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
00832   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
00833
00834   /* Check the NOR controller state */
00835   hnor->State = HAL_NOR_STATE_READY;
00836
00837   /* Process unlocked */
00838   __HAL_UNLOCK(hnor);
00839
00840   return HAL_OK;
00841 }
00842
00843 /**
00844   * @}
00845   */
00846
00847 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
00848  *  @brief   management functions
00849  *
00850 @verbatim
00851   ==============================================================================
00852                         ##### NOR Control functions #####
00853   ==============================================================================
00854   [..]
00855     This subsection provides a set of functions allowing to control dynamically
00856     the NOR interface.
00857
00858 @endverbatim
00859   * @{
00860   */
00861
00862 /**
00863   * @brief  Enables dynamically NOR write operation.
00864   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00865   *                the configuration information for NOR module.
00866   * @retval HAL status
00867   */
00868 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
00869 {
00870   /* Process Locked */
00871   __HAL_LOCK(hnor);
00872
00873   /* Enable write operation */
00874   FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
00875
00876   /* Update the NOR controller state */
00877   hnor->State = HAL_NOR_STATE_READY;
00878
00879   /* Process unlocked */
00880   __HAL_UNLOCK(hnor);
00881
00882   return HAL_OK;
00883 }
00884
00885 /**
00886   * @brief  Disables dynamically NOR write operation.
00887   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00888   *                the configuration information for NOR module.
00889   * @retval HAL status
00890   */
00891 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
00892 {
00893   /* Process Locked */
00894   __HAL_LOCK(hnor);
00895
00896   /* Update the SRAM controller state */
00897   hnor->State = HAL_NOR_STATE_BUSY;
00898
00899   /* Disable write operation */
00900   FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00901
00902   /* Update the NOR controller state */
00903   hnor->State = HAL_NOR_STATE_PROTECTED;
00904
00905   /* Process unlocked */
00906   __HAL_UNLOCK(hnor);
00907
00908   return HAL_OK;
00909 }
00910
00911 /**
00912   * @}
00913   */
00914
00915 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
00916  *  @brief   Peripheral State functions
00917  *
00918 @verbatim
00919   ==============================================================================
00920                       ##### NOR State functions #####
00921   ==============================================================================
00922   [..]
00923     This subsection permits to get in run-time the status of the NOR controller
00924     and the data flow.
00925
00926 @endverbatim
00927   * @{
00928   */
00929
00930 /**
00931   * @brief  return the NOR controller state
00932   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00933   *                the configuration information for NOR module.
00934   * @retval NOR controller state
00935   */
00936 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
00937 {
00938   return hnor->State;
00939 }
00940
00941 /**
00942   * @brief  Returns the NOR operation status.
00943   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00944   *                the configuration information for NOR module.
00945   * @param  Address: Device address
00946   * @param  Timeout: NOR programming Timeout
00947   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
00948   *         or HAL_NOR_STATUS_TIMEOUT
00949   */
00950 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
00951 {
00952   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
00953   uint16_t tmpSR1 = 0, tmpSR2 = 0;
00954   uint32_t tickstart = 0;
00955
00956   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
00957   HAL_NOR_MspWait(hnor, Timeout);
00958
00959   /* Get the NOR memory operation status -------------------------------------*/
00960
00961   /* Get tick */
00962   tickstart = HAL_GetTick();
00963   while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
00964   {
00965     /* Check for the Timeout */
00966     if(Timeout != HAL_MAX_DELAY)
00967     {
00968       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00969       {
00970         status = HAL_NOR_STATUS_TIMEOUT;
00971       }
00972     }
00973
00974     /* Read NOR status register (DQ6 and DQ5) */
00975     tmpSR1 = *(__IO uint16_t *)Address;
00976     tmpSR2 = *(__IO uint16_t *)Address;
00977
00978     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
00979     if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
00980     {
00981       return HAL_NOR_STATUS_SUCCESS ;
00982     }
00983
00984     if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
00985     {
00986       status = HAL_NOR_STATUS_ONGOING;
00987     }
00988
00989     tmpSR1 = *(__IO uint16_t *)Address;
00990     tmpSR2 = *(__IO uint16_t *)Address;
00991
00992     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
00993     if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
00994     {
00995       return HAL_NOR_STATUS_SUCCESS;
00996     }
00997     if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
00998     {
00999       return HAL_NOR_STATUS_ERROR;
01000     }
01001   }
01002
01003   /* Return the operation status */
01004   return status;
01005 }
01006
01007 /**
01008   * @}
01009   */
01010
01011 /**
01012   * @}
01013   */
01014 #endif /* HAL_NOR_MODULE_ENABLED */
01015 /**
01016   * @}
01017   */
01018
01019 /**
01020   * @}
01021   */
01022
01023 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_nor.h Source File

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stm32f7xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of NOR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_NOR_H
00040 #define __STM32F7xx_HAL_NOR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_fmc.h"
00048
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup NOR
00055   * @{
00056   */
00057
00058 /* Exported typedef ----------------------------------------------------------*/
00059 /** @defgroup NOR_Exported_Types NOR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL SRAM State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
00069   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
00070   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
00071   HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
00072   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
00073 }HAL_NOR_StateTypeDef;
00074
00075 /**
00076   * @brief  FMC NOR Status typedef
00077   */
00078 typedef enum
00079 {
00080   HAL_NOR_STATUS_SUCCESS  = 0,
00081   HAL_NOR_STATUS_ONGOING,
00082   HAL_NOR_STATUS_ERROR,
00083   HAL_NOR_STATUS_TIMEOUT
00084 }HAL_NOR_StatusTypeDef;
00085
00086 /**
00087   * @brief  FMC NOR ID typedef
00088   */
00089 typedef struct
00090 {
00091   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00092
00093   uint16_t Device_Code1;
00094
00095   uint16_t Device_Code2;
00096
00097   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00098                                     These codes can be accessed by performing read operations with specific
00099                                     control signals and addresses set.They can also be accessed by issuing
00100                                     an Auto Select command                                                   */
00101 }NOR_IDTypeDef;
00102
00103 /**
00104   * @brief  FMC NOR CFI typedef
00105   */
00106 typedef struct
00107 {
00108   /*!< Defines the information stored in the memory's Common flash interface
00109        which contains a description of various electrical and timing parameters,
00110        density information and functions supported by the memory                   */
00111
00112   uint16_t CFI_1;
00113
00114   uint16_t CFI_2;
00115
00116   uint16_t CFI_3;
00117
00118   uint16_t CFI_4;
00119 }NOR_CFITypeDef;
00120
00121 /**
00122   * @brief  NOR handle Structure definition
00123   */
00124 typedef struct
00125 {
00126   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00127
00128   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00129
00130   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00131
00132   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00133
00134   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00135
00136 }NOR_HandleTypeDef;
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /* Exported macro ------------------------------------------------------------*/
00143 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00144   * @{
00145   */
00146 /** @brief Reset NOR handle state
00147   * @param  __HANDLE__: specifies the NOR handle.
00148   * @retval None
00149   */
00150 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported functions --------------------------------------------------------*/
00156 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00157   * @{
00158   */
00159
00160 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00161   * @{
00162   */
00163
00164 /* Initialization/de-initialization functions  ********************************/
00165 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00166 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00167 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00168 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00169 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00170 /**
00171   * @}
00172   */
00173
00174 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00175   * @{
00176   */
00177
00178 /* I/O operation functions  ***************************************************/
00179 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00180 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00181 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00182 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00183
00184 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00185 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00186
00187 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00188 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00189 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00190 /**
00191   * @}
00192   */
00193
00194 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
00195   * @{
00196   */
00197
00198 /* NOR Control functions  *****************************************************/
00199 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00200 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00201 /**
00202   * @}
00203   */
00204
00205 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
00206   * @{
00207   */
00208
00209 /* NOR State functions ********************************************************/
00210 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00211 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Private types -------------------------------------------------------------*/
00221 /* Private variables ---------------------------------------------------------*/
00222 /* Private constants ---------------------------------------------------------*/
00223 /** @defgroup NOR_Private_Constants NOR Private Constants
00224   * @{
00225   */
00226 /* NOR device IDs addresses */
00227 #define MC_ADDRESS               ((uint16_t)0x0000)
00228 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
00229 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
00230 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
00231
00232 /* NOR CFI IDs addresses */
00233 #define CFI1_ADDRESS             ((uint16_t)0x61)
00234 #define CFI2_ADDRESS             ((uint16_t)0x62)
00235 #define CFI3_ADDRESS             ((uint16_t)0x63)
00236 #define CFI4_ADDRESS             ((uint16_t)0x64)
00237
00238 /* NOR operation wait timeout */
00239 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
00240
00241 /* NOR memory data width */
00242 #define NOR_MEMORY_8B            ((uint8_t)0x0)
00243 #define NOR_MEMORY_16B           ((uint8_t)0x1)
00244
00245 /* NOR memory device read/write start address */
00246 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)
00247 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)
00248 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)
00249 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)
00250 /**
00251   * @}
00252   */
00253
00254 /* Private macros ------------------------------------------------------------*/
00255 /** @defgroup NOR_Private_Macros NOR Private Macros
00256   * @{
00257   */
00258 /**
00259   * @brief  NOR memory address shifting.
00260   * @param  __NOR_ADDRESS: NOR base address
00261   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
00262   * @param  __ADDRESS__: NOR memory address
00263   * @retval NOR shifted address value
00264   */
00265 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
00266             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)?              \
00267               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
00268               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00269
00270 /**
00271   * @brief  NOR memory write data to specified address.
00272   * @param  __ADDRESS__: NOR memory address
00273   * @param  __DATA__: Data to write
00274   * @retval None
00275   */
00276 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
00277                                                  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
00278                                                  __DSB();                                                    \
00279                                                } while(0)
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 #ifdef __cplusplus
00294 }
00295 #endif
00296
00297 #endif /* __STM32F7xx_HAL_NOR_H */
00298
00299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd.c Source File

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stm32f7xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The PCD HAL driver can be used as follows:
00021
00022      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00023          PCD_HandleTypeDef  hpcd;
00024
00025      (#) Fill parameters of Init structure in HCD handle
00026
00027      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00028
00029      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00030          (##) Enable the PCD/USB Low Level interface clock using
00031               (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00032               (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
00033
00034          (##) Initialize the related GPIO clocks
00035          (##) Configure PCD pin-out
00036          (##) Configure PCD NVIC interrupt
00037
00038      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00039          (##) hpcd.pData = pdev;
00040
00041      (#)Enable PCD transmission and reception:
00042          (##) HAL_PCD_Start();
00043
00044   @endverbatim
00045   ******************************************************************************
00046   * @attention
00047   *
00048   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00049   *
00050   * Redistribution and use in source and binary forms, with or without modification,
00051   * are permitted provided that the following conditions are met:
00052   *   1. Redistributions of source code must retain the above copyright notice,
00053   *      this list of conditions and the following disclaimer.
00054   *   2. Redistributions in binary form must reproduce the above copyright notice,
00055   *      this list of conditions and the following disclaimer in the documentation
00056   *      and/or other materials provided with the distribution.
00057   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00058   *      may be used to endorse or promote products derived from this software
00059   *      without specific prior written permission.
00060   *
00061   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00062   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00063   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00064   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00065   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00066   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00067   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00068   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00069   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00070   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00071   *
00072   ******************************************************************************
00073   */
00074
00075 /* Includes ------------------------------------------------------------------*/
00076 #include "stm32f7xx_hal.h"
00077
00078 /** @addtogroup STM32F7xx_HAL_Driver
00079   * @{
00080   */
00081
00082 /** @defgroup PCD PCD
00083   * @brief PCD HAL module driver
00084   * @{
00085   */
00086
00087 #ifdef HAL_PCD_MODULE_ENABLED
00088
00089 /* Private types -------------------------------------------------------------*/
00090 /* Private variables ---------------------------------------------------------*/
00091 /* Private constants ---------------------------------------------------------*/
00092 /* Private macros ------------------------------------------------------------*/
00093 /** @defgroup PCD_Private_Macros PCD Private Macros
00094   * @{
00095   */
00096 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00097 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00098 /**
00099   * @}
00100   */
00101
00102 /* Private functions prototypes ----------------------------------------------*/
00103 /** @defgroup PCD_Private_Functions PCD Private Functions
00104   * @{
00105   */
00106 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00107 /**
00108   * @}
00109   */
00110
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00113   * @{
00114   */
00115
00116 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00117  *  @brief    Initialization and Configuration functions
00118  *
00119 @verbatim
00120  ===============================================================================
00121             ##### Initialization and de-initialization functions #####
00122  ===============================================================================
00123     [..]  This section provides functions allowing to:
00124
00125 @endverbatim
00126   * @{
00127   */
00128
00129 /**
00130   * @brief  Initializes the PCD according to the specified
00131   *         parameters in the PCD_InitTypeDef and create the associated handle.
00132   * @param  hpcd: PCD handle
00133   * @retval HAL status
00134   */
00135 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00136 {
00137   uint32_t i = 0;
00138
00139   /* Check the PCD handle allocation */
00140   if(hpcd == NULL)
00141   {
00142     return HAL_ERROR;
00143   }
00144
00145   /* Check the parameters */
00146   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00147
00148   hpcd->State = HAL_PCD_STATE_BUSY;
00149
00150   /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00151   HAL_PCD_MspInit(hpcd);
00152
00153   /* Disable the Interrupts */
00154  __HAL_PCD_DISABLE(hpcd);
00155
00156  /*Init the Core (common init.) */
00157  USB_CoreInit(hpcd->Instance, hpcd->Init);
00158
00159  /* Force Device Mode*/
00160  USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
00161
00162  /* Init endpoints structures */
00163  for (i = 0; i < 15 ; i++)
00164  {
00165    /* Init ep structure */
00166    hpcd->IN_ep[i].is_in = 1;
00167    hpcd->IN_ep[i].num = i;
00168    hpcd->IN_ep[i].tx_fifo_num = i;
00169    /* Control until ep is activated */
00170    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00171    hpcd->IN_ep[i].maxpacket =  0;
00172    hpcd->IN_ep[i].xfer_buff = 0;
00173    hpcd->IN_ep[i].xfer_len = 0;
00174  }
00175
00176  for (i = 0; i < 15 ; i++)
00177  {
00178    hpcd->OUT_ep[i].is_in = 0;
00179    hpcd->OUT_ep[i].num = i;
00180    hpcd->IN_ep[i].tx_fifo_num = i;
00181    /* Control until ep is activated */
00182    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00183    hpcd->OUT_ep[i].maxpacket = 0;
00184    hpcd->OUT_ep[i].xfer_buff = 0;
00185    hpcd->OUT_ep[i].xfer_len = 0;
00186
00187    hpcd->Instance->DIEPTXF[i] = 0;
00188  }
00189
00190  /* Init Device */
00191  USB_DevInit(hpcd->Instance, hpcd->Init);
00192
00193  hpcd->State= HAL_PCD_STATE_READY;
00194
00195  /* Activate LPM */
00196  if (hpcd->Init.lpm_enable == 1)
00197  {
00198    HAL_PCDEx_ActivateLPM(hpcd);
00199  }
00200
00201  USB_DevDisconnect (hpcd->Instance);
00202  return HAL_OK;
00203 }
00204
00205 /**
00206   * @brief  DeInitializes the PCD peripheral.
00207   * @param  hpcd: PCD handle
00208   * @retval HAL status
00209   */
00210 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00211 {
00212   /* Check the PCD handle allocation */
00213   if(hpcd == NULL)
00214   {
00215     return HAL_ERROR;
00216   }
00217
00218   hpcd->State = HAL_PCD_STATE_BUSY;
00219
00220   /* Stop Device */
00221   HAL_PCD_Stop(hpcd);
00222
00223   /* DeInit the low level hardware */
00224   HAL_PCD_MspDeInit(hpcd);
00225
00226   hpcd->State = HAL_PCD_STATE_RESET;
00227
00228   return HAL_OK;
00229 }
00230
00231 /**
00232   * @brief  Initializes the PCD MSP.
00233   * @param  hpcd: PCD handle
00234   * @retval None
00235   */
00236 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00237 {
00238   /* Prevent unused argument(s) compilation warning */
00239   UNUSED(hpcd);
00240
00241   /* NOTE : This function Should not be modified, when the callback is needed,
00242             the HAL_PCD_MspInit could be implemented in the user file
00243    */
00244 }
00245
00246 /**
00247   * @brief  DeInitializes PCD MSP.
00248   * @param  hpcd: PCD handle
00249   * @retval None
00250   */
00251 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00252 {
00253   /* Prevent unused argument(s) compilation warning */
00254   UNUSED(hpcd);
00255
00256   /* NOTE : This function Should not be modified, when the callback is needed,
00257             the HAL_PCD_MspDeInit could be implemented in the user file
00258    */
00259 }
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00266  *  @brief   Data transfers functions
00267  *
00268 @verbatim
00269  ===============================================================================
00270                       ##### IO operation functions #####
00271  ===============================================================================
00272     [..]
00273     This subsection provides a set of functions allowing to manage the PCD data
00274     transfers.
00275
00276 @endverbatim
00277   * @{
00278   */
00279
00280 /**
00281   * @brief  Start The USB OTG Device.
00282   * @param  hpcd: PCD handle
00283   * @retval HAL status
00284   */
00285 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00286 {
00287   __HAL_LOCK(hpcd);
00288   USB_DevConnect (hpcd->Instance);
00289   __HAL_PCD_ENABLE(hpcd);
00290   __HAL_UNLOCK(hpcd);
00291   return HAL_OK;
00292 }
00293
00294 /**
00295   * @brief  Stop The USB OTG Device.
00296   * @param  hpcd: PCD handle
00297   * @retval HAL status
00298   */
00299 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00300 {
00301   __HAL_LOCK(hpcd);
00302   __HAL_PCD_DISABLE(hpcd);
00303   USB_StopDevice(hpcd->Instance);
00304   USB_DevDisconnect (hpcd->Instance);
00305   __HAL_UNLOCK(hpcd);
00306   return HAL_OK;
00307 }
00308
00309 /**
00310   * @brief  Handle PCD interrupt request.
00311   * @param  hpcd: PCD handle
00312   * @retval HAL status
00313   */
00314 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00315 {
00316   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00317   uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
00318   uint32_t fifoemptymsk = 0, temp = 0;
00319   USB_OTG_EPTypeDef *ep;
00320
00321   /* ensure that we are in device mode */
00322   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
00323   {
00324     /* avoid spurious interrupt */
00325     if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
00326     {
00327       return;
00328     }
00329
00330     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
00331     {
00332      /* incorrect mode, acknowledge the interrupt */
00333       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
00334     }
00335
00336     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
00337     {
00338       epnum = 0;
00339
00340       /* Read in the device interrupt bits */
00341       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
00342
00343       while ( ep_intr )
00344       {
00345         if (ep_intr & 0x1)
00346         {
00347           epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
00348
00349           if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
00350           {
00351             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
00352
00353             if(hpcd->Init.dma_enable == 1)
00354             {
00355               hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
00356               hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
00357             }
00358
00359             HAL_PCD_DataOutStageCallback(hpcd, epnum);
00360             if(hpcd->Init.dma_enable == 1)
00361             {
00362               if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
00363               {
00364                  /* this is ZLP, so prepare EP0 for next setup */
00365                 USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
00366               }
00367             }
00368           }
00369
00370           if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
00371           {
00372             /* Inform the upper layer that a setup packet is available */
00373             HAL_PCD_SetupStageCallback(hpcd);
00374             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
00375           }
00376
00377           if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
00378           {
00379             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
00380           }
00381           /* Clear Status Phase Received interrupt */
00382           if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
00383           {
00384             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
00385           }
00386         }
00387         epnum++;
00388         ep_intr >>= 1;
00389       }
00390     }
00391
00392     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
00393     {
00394       /* Read in the device interrupt bits */
00395       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
00396
00397       epnum = 0;
00398
00399       while ( ep_intr )
00400       {
00401         if (ep_intr & 0x1) /* In ITR */
00402         {
00403           epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
00404
00405            if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
00406           {
00407             fifoemptymsk = 0x1 << epnum;
00408             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
00409
00410             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
00411
00412             if (hpcd->Init.dma_enable == 1)
00413             {
00414               hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
00415             }
00416
00417             HAL_PCD_DataInStageCallback(hpcd, epnum);
00418
00419             if (hpcd->Init.dma_enable == 1)
00420             {
00421               /* this is ZLP, so prepare EP0 for next setup */
00422               if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
00423               {
00424                 /* prepare to rx more setup packets */
00425                 USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
00426               }
00427             }
00428           }
00429            if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
00430           {
00431             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
00432           }
00433           if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
00434           {
00435             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
00436           }
00437           if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
00438           {
00439             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
00440           }
00441           if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
00442           {
00443             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
00444           }
00445           if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
00446           {
00447             PCD_WriteEmptyTxFifo(hpcd , epnum);
00448           }
00449         }
00450         epnum++;
00451         ep_intr >>= 1;
00452       }
00453     }
00454
00455     /* Handle Resume Interrupt */
00456     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
00457     {
00458       /* Clear the Remote Wake-up Signaling */
00459       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00460
00461       if(hpcd->LPM_State == LPM_L1)
00462       {
00463         hpcd->LPM_State = LPM_L0;
00464         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
00465       }
00466       else
00467       {
00468         HAL_PCD_ResumeCallback(hpcd);
00469       }
00470       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
00471     }
00472
00473     /* Handle Suspend Interrupt */
00474     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
00475     {
00476       if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
00477       {
00478
00479         HAL_PCD_SuspendCallback(hpcd);
00480       }
00481       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
00482     }
00483
00484     /* Handle LPM Interrupt */
00485     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
00486     {
00487       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
00488       if( hpcd->LPM_State == LPM_L0)
00489       {
00490         hpcd->LPM_State = LPM_L1;
00491         hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
00492         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
00493       }
00494       else
00495       {
00496         HAL_PCD_SuspendCallback(hpcd);
00497       }
00498     }
00499
00500     /* Handle Reset Interrupt */
00501     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
00502     {
00503       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00504       USB_FlushTxFifo(hpcd->Instance ,  0 );
00505
00506       for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
00507       {
00508         USBx_INEP(i)->DIEPINT = 0xFF;
00509         USBx_OUTEP(i)->DOEPINT = 0xFF;
00510       }
00511       USBx_DEVICE->DAINT = 0xFFFFFFFF;
00512       USBx_DEVICE->DAINTMSK |= 0x10001;
00513
00514       if(hpcd->Init.use_dedicated_ep1)
00515       {
00516         USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00517         USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00518       }
00519       else
00520       {
00521         USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
00522         USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00523       }
00524
00525       /* Set Default Address to 0 */
00526       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
00527
00528       /* setup EP0 to receive SETUP packets */
00529       USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
00530
00531       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
00532     }
00533
00534     /* Handle Enumeration done Interrupt */
00535     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
00536     {
00537       USB_ActivateSetup(hpcd->Instance);
00538       hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
00539
00540       if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
00541       {
00542         hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
00543         hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;
00544         hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
00545       }
00546       else
00547       {
00548         hpcd->Init.speed            = USB_OTG_SPEED_FULL;
00549         hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;
00550         hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
00551       }
00552
00553       HAL_PCD_ResetCallback(hpcd);
00554
00555       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
00556     }
00557
00558     /* Handle RxQLevel Interrupt */
00559     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
00560     {
00561       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00562       temp = USBx->GRXSTSP;
00563       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
00564
00565       if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
00566       {
00567         if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
00568         {
00569           USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
00570           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00571           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00572         }
00573       }
00574       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
00575       {
00576         USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
00577         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00578       }
00579       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00580     }
00581
00582     /* Handle SOF Interrupt */
00583     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
00584     {
00585       HAL_PCD_SOFCallback(hpcd);
00586       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
00587     }
00588
00589     /* Handle Incomplete ISO IN Interrupt */
00590     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
00591     {
00592       HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
00593       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
00594     }
00595
00596     /* Handle Incomplete ISO OUT Interrupt */
00597     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00598     {
00599       HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
00600       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00601     }
00602
00603     /* Handle Connection event Interrupt */
00604     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
00605     {
00606       HAL_PCD_ConnectCallback(hpcd);
00607       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
00608     }
00609
00610     /* Handle Disconnection event Interrupt */
00611     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
00612     {
00613       temp = hpcd->Instance->GOTGINT;
00614
00615       if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
00616       {
00617         HAL_PCD_DisconnectCallback(hpcd);
00618       }
00619       hpcd->Instance->GOTGINT |= temp;
00620     }
00621   }
00622 }
00623
00624 /**
00625   * @brief  Data OUT stage callback.
00626   * @param  hpcd: PCD handle
00627   * @param  epnum: endpoint number
00628   * @retval None
00629   */
00630  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00631 {
00632   /* Prevent unused argument(s) compilation warning */
00633   UNUSED(hpcd);
00634
00635   /* NOTE : This function Should not be modified, when the callback is needed,
00636             the HAL_PCD_DataOutStageCallback could be implemented in the user file
00637    */
00638 }
00639
00640 /**
00641   * @brief  Data IN stage callback.
00642   * @param  hpcd: PCD handle
00643   * @param  epnum: endpoint number
00644   * @retval None
00645   */
00646  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00647 {
00648   /* Prevent unused argument(s) compilation warning */
00649   UNUSED(hpcd);
00650
00651   /* NOTE : This function Should not be modified, when the callback is needed,
00652             the HAL_PCD_DataInStageCallback could be implemented in the user file
00653    */
00654 }
00655 /**
00656   * @brief  Setup stage callback.
00657   * @param  hpcd: PCD handle
00658   * @retval None
00659   */
00660  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
00661 {
00662   /* Prevent unused argument(s) compilation warning */
00663   UNUSED(hpcd);
00664
00665   /* NOTE : This function Should not be modified, when the callback is needed,
00666             the HAL_PCD_SetupStageCallback could be implemented in the user file
00667    */
00668 }
00669
00670 /**
00671   * @brief  USB Start Of Frame callback.
00672   * @param  hpcd: PCD handle
00673   * @retval None
00674   */
00675  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
00676 {
00677   /* Prevent unused argument(s) compilation warning */
00678   UNUSED(hpcd);
00679
00680   /* NOTE : This function Should not be modified, when the callback is needed,
00681             the HAL_PCD_SOFCallback could be implemented in the user file
00682    */
00683 }
00684
00685 /**
00686   * @brief  USB Reset callback.
00687   * @param  hpcd: PCD handle
00688   * @retval None
00689   */
00690  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
00691 {
00692   /* Prevent unused argument(s) compilation warning */
00693   UNUSED(hpcd);
00694
00695   /* NOTE : This function Should not be modified, when the callback is needed,
00696             the HAL_PCD_ResetCallback could be implemented in the user file
00697    */
00698 }
00699
00700 /**
00701   * @brief  Suspend event callback.
00702   * @param  hpcd: PCD handle
00703   * @retval None
00704   */
00705  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
00706 {
00707   /* Prevent unused argument(s) compilation warning */
00708   UNUSED(hpcd);
00709
00710   /* NOTE : This function Should not be modified, when the callback is needed,
00711             the HAL_PCD_SuspendCallback could be implemented in the user file
00712    */
00713 }
00714
00715 /**
00716   * @brief  Resume event callback.
00717   * @param  hpcd: PCD handle
00718   * @retval None
00719   */
00720  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
00721 {
00722   /* Prevent unused argument(s) compilation warning */
00723   UNUSED(hpcd);
00724
00725   /* NOTE : This function Should not be modified, when the callback is needed,
00726             the HAL_PCD_ResumeCallback could be implemented in the user file
00727    */
00728 }
00729
00730 /**
00731   * @brief  Incomplete ISO OUT callback.
00732   * @param  hpcd: PCD handle
00733   * @param  epnum: endpoint number
00734   * @retval None
00735   */
00736  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00737 {
00738   /* Prevent unused argument(s) compilation warning */
00739   UNUSED(hpcd);
00740
00741   /* NOTE : This function Should not be modified, when the callback is needed,
00742             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
00743    */
00744 }
00745
00746 /**
00747   * @brief  Incomplete ISO IN  callback.
00748   * @param  hpcd: PCD handle
00749   * @param  epnum: endpoint number
00750   * @retval None
00751   */
00752  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00753 {
00754   /* Prevent unused argument(s) compilation warning */
00755   UNUSED(hpcd);
00756
00757   /* NOTE : This function Should not be modified, when the callback is needed,
00758             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
00759    */
00760 }
00761
00762 /**
00763   * @brief  Connection event callback.
00764   * @param  hpcd: PCD handle
00765   * @retval None
00766   */
00767  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
00768 {
00769   /* Prevent unused argument(s) compilation warning */
00770   UNUSED(hpcd);
00771
00772   /* NOTE : This function Should not be modified, when the callback is needed,
00773             the HAL_PCD_ConnectCallback could be implemented in the user file
00774    */
00775 }
00776
00777 /**
00778   * @brief  Disconnection event callback.
00779   * @param  hpcd: PCD handle
00780   * @retval None
00781   */
00782  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
00783 {
00784   /* Prevent unused argument(s) compilation warning */
00785   UNUSED(hpcd);
00786
00787   /* NOTE : This function Should not be modified, when the callback is needed,
00788             the HAL_PCD_DisconnectCallback could be implemented in the user file
00789    */
00790 }
00791
00792 /**
00793   * @}
00794   */
00795
00796 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
00797  *  @brief   management functions
00798  *
00799 @verbatim
00800  ===============================================================================
00801                       ##### Peripheral Control functions #####
00802  ===============================================================================
00803     [..]
00804     This subsection provides a set of functions allowing to control the PCD data
00805     transfers.
00806
00807 @endverbatim
00808   * @{
00809   */
00810
00811 /**
00812   * @brief  Connect the USB device.
00813   * @param  hpcd: PCD handle
00814   * @retval HAL status
00815   */
00816 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
00817 {
00818   __HAL_LOCK(hpcd);
00819   USB_DevConnect(hpcd->Instance);
00820   __HAL_UNLOCK(hpcd);
00821   return HAL_OK;
00822 }
00823
00824 /**
00825   * @brief  Disconnect the USB device.
00826   * @param  hpcd: PCD handle
00827   * @retval HAL status
00828   */
00829 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
00830 {
00831   __HAL_LOCK(hpcd);
00832   USB_DevDisconnect(hpcd->Instance);
00833   __HAL_UNLOCK(hpcd);
00834   return HAL_OK;
00835 }
00836
00837 /**
00838   * @brief  Set the USB Device address.
00839   * @param  hpcd: PCD handle
00840   * @param  address: new device address
00841   * @retval HAL status
00842   */
00843 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
00844 {
00845   __HAL_LOCK(hpcd);
00846   USB_SetDevAddress(hpcd->Instance, address);
00847   __HAL_UNLOCK(hpcd);
00848   return HAL_OK;
00849 }
00850 /**
00851   * @brief  Open and configure an endpoint.
00852   * @param  hpcd: PCD handle
00853   * @param  ep_addr: endpoint address
00854   * @param  ep_mps: endpoint max packet size
00855   * @param  ep_type: endpoint type
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
00859 {
00860   HAL_StatusTypeDef  ret = HAL_OK;
00861   USB_OTG_EPTypeDef *ep;
00862
00863   if ((ep_addr & 0x80) == 0x80)
00864   {
00865     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00866   }
00867   else
00868   {
00869     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00870   }
00871   ep->num   = ep_addr & 0x7F;
00872
00873   ep->is_in = (0x80 & ep_addr) != 0;
00874   ep->maxpacket = ep_mps;
00875   ep->type = ep_type;
00876   if (ep->is_in)
00877   {
00878     /* Assign a Tx FIFO */
00879     ep->tx_fifo_num = ep->num;
00880   }
00881   /* Set initial data PID. */
00882   if (ep_type == EP_TYPE_BULK )
00883   {
00884     ep->data_pid_start = 0;
00885   }
00886
00887   __HAL_LOCK(hpcd);
00888   USB_ActivateEndpoint(hpcd->Instance , ep);
00889   __HAL_UNLOCK(hpcd);
00890   return ret;
00891 }
00892
00893
00894 /**
00895   * @brief  Deactivate an endpoint.
00896   * @param  hpcd: PCD handle
00897   * @param  ep_addr: endpoint address
00898   * @retval HAL status
00899   */
00900 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00901 {
00902   USB_OTG_EPTypeDef *ep;
00903
00904   if ((ep_addr & 0x80) == 0x80)
00905   {
00906     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00907   }
00908   else
00909   {
00910     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00911   }
00912   ep->num   = ep_addr & 0x7F;
00913
00914   ep->is_in = (0x80 & ep_addr) != 0;
00915
00916   __HAL_LOCK(hpcd);
00917   USB_DeactivateEndpoint(hpcd->Instance , ep);
00918   __HAL_UNLOCK(hpcd);
00919   return HAL_OK;
00920 }
00921
00922
00923 /**
00924   * @brief  Receive an amount of data.
00925   * @param  hpcd: PCD handle
00926   * @param  ep_addr: endpoint address
00927   * @param  pBuf: pointer to the reception buffer
00928   * @param  len: amount of data to be received
00929   * @retval HAL status
00930   */
00931 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00932 {
00933   USB_OTG_EPTypeDef *ep;
00934
00935   ep = &hpcd->OUT_ep[ep_addr & 0x7F];
00936
00937   /*setup and start the Xfer */
00938   ep->xfer_buff = pBuf;
00939   ep->xfer_len = len;
00940   ep->xfer_count = 0;
00941   ep->is_in = 0;
00942   ep->num = ep_addr & 0x7F;
00943
00944   if (hpcd->Init.dma_enable == 1)
00945   {
00946     ep->dma_addr = (uint32_t)pBuf;
00947   }
00948
00949   __HAL_LOCK(hpcd);
00950
00951   if ((ep_addr & 0x7F) == 0 )
00952   {
00953     USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00954   }
00955   else
00956   {
00957     USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00958   }
00959   __HAL_UNLOCK(hpcd);
00960
00961   return HAL_OK;
00962 }
00963
00964 /**
00965   * @brief  Get Received Data Size.
00966   * @param  hpcd: PCD handle
00967   * @param  ep_addr: endpoint address
00968   * @retval Data Size
00969   */
00970 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00971 {
00972   return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
00973 }
00974 /**
00975   * @brief  Send an amount of data.
00976   * @param  hpcd: PCD handle
00977   * @param  ep_addr: endpoint address
00978   * @param  pBuf: pointer to the transmission buffer
00979   * @param  len: amount of data to be sent
00980   * @retval HAL status
00981   */
00982 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00983 {
00984   USB_OTG_EPTypeDef *ep;
00985
00986   ep = &hpcd->IN_ep[ep_addr & 0x7F];
00987
00988   /*setup and start the Xfer */
00989   ep->xfer_buff = pBuf;
00990   ep->xfer_len = len;
00991   ep->xfer_count = 0;
00992   ep->is_in = 1;
00993   ep->num = ep_addr & 0x7F;
00994
00995   if (hpcd->Init.dma_enable == 1)
00996   {
00997     ep->dma_addr = (uint32_t)pBuf;
00998   }
00999
01000   __HAL_LOCK(hpcd);
01001
01002   if ((ep_addr & 0x7F) == 0 )
01003   {
01004     USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
01005   }
01006   else
01007   {
01008     USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
01009   }
01010
01011   __HAL_UNLOCK(hpcd);
01012
01013   return HAL_OK;
01014 }
01015
01016 /**
01017   * @brief  Set a STALL condition over an endpoint.
01018   * @param  hpcd: PCD handle
01019   * @param  ep_addr: endpoint address
01020   * @retval HAL status
01021   */
01022 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01023 {
01024   USB_OTG_EPTypeDef *ep;
01025
01026   if ((0x80 & ep_addr) == 0x80)
01027   {
01028     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01029   }
01030   else
01031   {
01032     ep = &hpcd->OUT_ep[ep_addr];
01033   }
01034
01035   ep->is_stall = 1;
01036   ep->num   = ep_addr & 0x7F;
01037   ep->is_in = ((ep_addr & 0x80) == 0x80);
01038
01039
01040   __HAL_LOCK(hpcd);
01041   USB_EPSetStall(hpcd->Instance , ep);
01042   if((ep_addr & 0x7F) == 0)
01043   {
01044     USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
01045   }
01046   __HAL_UNLOCK(hpcd);
01047
01048   return HAL_OK;
01049 }
01050
01051 /**
01052   * @brief  Clear a STALL condition over in an endpoint.
01053   * @param  hpcd: PCD handle
01054   * @param  ep_addr: endpoint address
01055   * @retval HAL status
01056   */
01057 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01058 {
01059   USB_OTG_EPTypeDef *ep;
01060
01061   if ((0x80 & ep_addr) == 0x80)
01062   {
01063     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01064   }
01065   else
01066   {
01067     ep = &hpcd->OUT_ep[ep_addr];
01068   }
01069
01070   ep->is_stall = 0;
01071   ep->num   = ep_addr & 0x7F;
01072   ep->is_in = ((ep_addr & 0x80) == 0x80);
01073
01074   __HAL_LOCK(hpcd);
01075   USB_EPClearStall(hpcd->Instance , ep);
01076   __HAL_UNLOCK(hpcd);
01077
01078   return HAL_OK;
01079 }
01080
01081 /**
01082   * @brief  Flush an endpoint.
01083   * @param  hpcd: PCD handle
01084   * @param  ep_addr: endpoint address
01085   * @retval HAL status
01086   */
01087 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01088 {
01089   __HAL_LOCK(hpcd);
01090
01091   if ((ep_addr & 0x80) == 0x80)
01092   {
01093     USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
01094   }
01095   else
01096   {
01097     USB_FlushRxFifo(hpcd->Instance);
01098   }
01099
01100   __HAL_UNLOCK(hpcd);
01101
01102   return HAL_OK;
01103 }
01104
01105 /**
01106   * @brief  Activate remote wakeup signalling.
01107   * @param  hpcd: PCD handle
01108   * @retval HAL status
01109   */
01110 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01111 {
01112   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01113
01114   if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
01115   {
01116     /* Activate Remote wakeup signaling */
01117     USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
01118   }
01119   return HAL_OK;
01120 }
01121
01122 /**
01123   * @brief  De-activate remote wakeup signalling.
01124   * @param  hpcd: PCD handle
01125   * @retval HAL status
01126   */
01127 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01128 {
01129   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01130
01131   /* De-activate Remote wakeup signaling */
01132    USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
01133   return HAL_OK;
01134 }
01135 /**
01136   * @}
01137   */
01138
01139 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01140  *  @brief   Peripheral State functions
01141  *
01142 @verbatim
01143  ===============================================================================
01144                       ##### Peripheral State functions #####
01145  ===============================================================================
01146     [..]
01147     This subsection permits to get in run-time the status of the peripheral
01148     and the data flow.
01149
01150 @endverbatim
01151   * @{
01152   */
01153
01154 /**
01155   * @brief  Return the PCD handle state.
01156   * @param  hpcd: PCD handle
01157   * @retval HAL state
01158   */
01159 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01160 {
01161   return hpcd->State;
01162 }
01163 /**
01164   * @}
01165   */
01166
01167 /**
01168   * @}
01169   */
01170
01171 /* Private functions ---------------------------------------------------------*/
01172 /** @addtogroup PCD_Private_Functions
01173   * @{
01174   */
01175
01176 /**
01177   * @brief  Check FIFO for the next packet to be loaded.
01178   * @param  hpcd: PCD handle
01179   * @param  epnum : endpoint number
01180   * @retval HAL status
01181   */
01182 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
01183 {
01184   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01185   USB_OTG_EPTypeDef *ep;
01186   int32_t len = 0;
01187   uint32_t len32b;
01188   uint32_t fifoemptymsk = 0;
01189
01190   ep = &hpcd->IN_ep[epnum];
01191   len = ep->xfer_len - ep->xfer_count;
01192
01193   if (len > ep->maxpacket)
01194   {
01195     len = ep->maxpacket;
01196   }
01197
01198
01199   len32b = (len + 3) / 4;
01200
01201   while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
01202           ep->xfer_count < ep->xfer_len &&
01203             ep->xfer_len != 0)
01204   {
01205     /* Write the FIFO */
01206     len = ep->xfer_len - ep->xfer_count;
01207
01208     if (len > ep->maxpacket)
01209     {
01210       len = ep->maxpacket;
01211     }
01212     len32b = (len + 3) / 4;
01213
01214     USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
01215
01216     ep->xfer_buff  += len;
01217     ep->xfer_count += len;
01218   }
01219
01220   if(len <= 0)
01221   {
01222     fifoemptymsk = 0x1 << epnum;
01223     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
01224
01225   }
01226
01227   return HAL_OK;
01228 }
01229
01230 /**
01231   * @}
01232   */
01233
01234 #endif /* HAL_PCD_MODULE_ENABLED */
01235 /**
01236   * @}
01237   */
01238
01239 /**
01240   * @}
01241   */
01242
01243 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd.h Source File

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stm32f7xx_hal_pcd.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_PCD_H
00040 #define __STM32F7xx_HAL_PCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_usb.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PCD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup PCD_Exported_Types PCD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  PCD State structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_PCD_STATE_RESET   = 0x00,
00068   HAL_PCD_STATE_READY   = 0x01,
00069   HAL_PCD_STATE_ERROR   = 0x02,
00070   HAL_PCD_STATE_BUSY    = 0x03,
00071   HAL_PCD_STATE_TIMEOUT = 0x04
00072 } PCD_StateTypeDef;
00073
00074 /* Device LPM suspend state */
00075 typedef enum
00076 {
00077   LPM_L0 = 0x00, /* on */
00078   LPM_L1 = 0x01, /* LPM L1 sleep */
00079   LPM_L2 = 0x02, /* suspend */
00080   LPM_L3 = 0x03, /* off */
00081 }PCD_LPM_StateTypeDef;
00082
00083 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
00084 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
00085 typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
00086
00087 /**
00088   * @brief  PCD Handle Structure definition
00089   */
00090 typedef struct
00091 {
00092   PCD_TypeDef             *Instance;   /*!< Register base address              */
00093   PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
00094   PCD_EPTypeDef           IN_ep[15];  /*!< IN endpoint parameters             */
00095   PCD_EPTypeDef           OUT_ep[15]; /*!< OUT endpoint parameters            */
00096   HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
00097   __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
00098   uint32_t                Setup[12];  /*!< Setup packet buffer                */
00099   PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
00100   uint32_t                BESL;
00101   uint32_t                lpm_active;   /*!< Enable or disable the Link Power Management .
00102                                         This parameter can be set to ENABLE or DISABLE */
00103   void                    *pData;       /*!< Pointer to upper stack Handler */
00104 } PCD_HandleTypeDef;
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Include PCD HAL Extension module */
00111 #include "stm32f7xx_hal_pcd_ex.h"
00112
00113 /* Exported constants --------------------------------------------------------*/
00114 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00115   * @{
00116   */
00117
00118 /** @defgroup PCD_Speed PCD Speed
00119   * @{
00120   */
00121 #define PCD_SPEED_HIGH               0
00122 #define PCD_SPEED_HIGH_IN_FULL       1
00123 #define PCD_SPEED_FULL               2
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup PCD_PHY_Module PCD PHY Module
00129   * @{
00130   */
00131 #define PCD_PHY_ULPI                 1
00132 #define PCD_PHY_EMBEDDED             2
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
00138   * @{
00139   */
00140 #ifndef USBD_HS_TRDT_VALUE
00141  #define USBD_HS_TRDT_VALUE           9
00142 #endif /* USBD_HS_TRDT_VALUE */
00143 #ifndef USBD_FS_TRDT_VALUE
00144  #define USBD_FS_TRDT_VALUE           5
00145 #endif /* USBD_HS_TRDT_VALUE */
00146
00147 /**
00148   * @}
00149   */
00150
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported macros -----------------------------------------------------------*/
00156 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00157  *  @brief macros to handle interrupts and specific clock configurations
00158  * @{
00159  */
00160 #define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
00161 #define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
00162
00163 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00164 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00165 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
00166
00167
00168 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
00169                                                        ~(USB_OTG_PCGCCTL_STOPCLK)
00170
00171 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
00172
00173 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
00174
00175 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE      ((uint32_t)0x08)
00176 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE     ((uint32_t)0x0C)
00177 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10)
00178
00179 #define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE      ((uint32_t)0x08)
00180 #define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE     ((uint32_t)0x0C)
00181 #define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10)
00182
00183 #define USB_OTG_HS_WAKEUP_EXTI_LINE              ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
00184 #define USB_OTG_FS_WAKEUP_EXTI_LINE              ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
00185
00186 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
00187 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
00188 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
00189 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
00190
00191 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00192                                                           EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
00193
00194 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
00195                                                             EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
00196
00197 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()   EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00198                                                                     EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
00199                                                                     EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
00200                                                                     EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
00201
00202 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00203
00204 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
00205 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00206 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
00207 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
00208
00209 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00210                                                           EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
00211
00212
00213 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
00214                                                             EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00215
00216 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00217                                                                    EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00218                                                                    EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00219                                                                    EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
00220
00221 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00222 /**
00223   * @}
00224   */
00225
00226 /* Exported functions --------------------------------------------------------*/
00227 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00228   * @{
00229   */
00230
00231 /* Initialization/de-initialization functions  ********************************/
00232 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00233   * @{
00234   */
00235 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00236 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
00237 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00238 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00239 /**
00240   * @}
00241   */
00242
00243 /* I/O operation functions  ***************************************************/
00244 /* Non-Blocking mode: Interrupt */
00245 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00246   * @{
00247   */
00248 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00249 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00250 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00251
00252 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00253 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00254 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00255 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00256 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00257 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00258 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00259 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00260 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00261 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00262 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00263 /**
00264   * @}
00265   */
00266
00267 /* Peripheral Control functions  **********************************************/
00268 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00269   * @{
00270   */
00271 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00272 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00273 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00274 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00275 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00276 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00277 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00278 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00279 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00280 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00281 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00282 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00283 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00284 /**
00285   * @}
00286   */
00287
00288 /* Peripheral State functions  ************************************************/
00289 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00290   * @{
00291   */
00292 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00293 /**
00294   * @}
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301 /* Private macros ------------------------------------------------------------*/
00302 /** @defgroup PCD_Private_Macros PCD Private Macros
00303  * @{
00304  */
00305 /** @defgroup PCD_Instance_definition PCD Instance definition
00306   * @{
00307   */
00308 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
00309                                        ((INSTANCE) == USB_OTG_HS))
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326 #ifdef __cplusplus
00327 }
00328 #endif
00329
00330
00331 #endif /* __STM32F7xx_HAL_PCD_H */
00332
00333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd_ex.c Source File

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stm32f7xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f7xx_hal.h"
00044
00045 /** @addtogroup STM32F7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PCDEx PCDEx
00050   * @brief PCD Extended HAL module driver
00051   * @{
00052   */
00053 #ifdef HAL_PCD_MODULE_ENABLED
00054
00055 /* Private types -------------------------------------------------------------*/
00056 /* Private variables ---------------------------------------------------------*/
00057 /* Private constants ---------------------------------------------------------*/
00058 /* Private macros ------------------------------------------------------------*/
00059 /* Private functions ---------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061
00062 /** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
00063   * @{
00064   */
00065
00066 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00067   * @brief    PCDEx control functions
00068  *
00069 @verbatim
00070  ===============================================================================
00071                  ##### Extended features functions #####
00072  ===============================================================================
00073     [..]  This section provides functions allowing to:
00074       (+) Update FIFO configuration
00075
00076 @endverbatim
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Set Tx FIFO
00082   * @param  hpcd: PCD handle
00083   * @param  fifo: The number of Tx fifo
00084   * @param  size: Fifo size
00085   * @retval HAL status
00086   */
00087 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
00088 {
00089   uint8_t i = 0;
00090   uint32_t Tx_Offset = 0;
00091
00092   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
00093       When a TxFIFO is not used, the Configuration should be as follows:
00094           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00095          --> Txm can use the space allocated for Txn.
00096          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00097          --> Txn should be configured with the minimum space of 16 words
00098      The FIFO is used optimally when used TxFIFOs are allocated in the top
00099          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
00100      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
00101
00102   Tx_Offset = hpcd->Instance->GRXFSIZ;
00103
00104   if(fifo == 0)
00105   {
00106     hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
00107   }
00108   else
00109   {
00110     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
00111     for (i = 0; i < (fifo - 1); i++)
00112     {
00113       Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
00114     }
00115
00116     /* Multiply Tx_Size by 2 to get higher performance */
00117     hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
00118   }
00119
00120   return HAL_OK;
00121 }
00122
00123 /**
00124   * @brief  Set Rx FIFO
00125   * @param  hpcd: PCD handle
00126   * @param  size: Size of Rx fifo
00127   * @retval HAL status
00128   */
00129 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
00130 {
00131   hpcd->Instance->GRXFSIZ = size;
00132
00133   return HAL_OK;
00134 }
00135
00136 /**
00137   * @brief  Activate LPM Feature
00138   * @param  hpcd: PCD handle
00139   * @retval HAL status
00140   */
00141 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00142 {
00143   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00144
00145   hpcd->lpm_active = ENABLE;
00146   hpcd->LPM_State = LPM_L0;
00147   USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
00148   USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00149
00150   return HAL_OK;
00151 }
00152
00153 /**
00154   * @brief  DeActivate LPM feature.
00155   * @param  hpcd: PCD handle
00156   * @retval HAL status
00157   */
00158 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00159 {
00160   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00161
00162   hpcd->lpm_active = DISABLE;
00163   USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
00164   USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00165
00166   return HAL_OK;
00167 }
00168
00169 /**
00170   * @brief  Send LPM message to user layer callback.
00171   * @param  hpcd: PCD handle
00172   * @param  msg: LPM message
00173   * @retval HAL status
00174   */
00175 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00176 {
00177   /* Prevent unused argument(s) compilation warning */
00178   UNUSED(hpcd);
00179
00180   /* NOTE : This function Should not be modified, when the callback is needed,
00181             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00182    */
00183 }
00184
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 #endif /* HAL_PCD_MODULE_ENABLED */
00194 /**
00195   * @}
00196   */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pcd_ex.h Source File

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stm32f7xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_PCD_EX_H
00040 #define __STM32F7xx_HAL_PCD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PCDEx
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 typedef enum
00058 {
00059   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00060   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00061 }PCD_LPM_MsgTypeDef;
00062
00063 /* Exported constants --------------------------------------------------------*/
00064 /* Exported macros -----------------------------------------------------------*/
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
00067   * @{
00068   */
00069 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00070   * @{
00071   */
00072 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
00073 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
00074 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00075 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00076 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00077
00078 /**
00079   * @}
00080   */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /**
00087   * @}
00088   */
00089
00090 /**
00091   * @}
00092   */
00093
00094 #ifdef __cplusplus
00095 }
00096 #endif
00097
00098
00099 #endif /* __STM32F7xx_HAL_PCD_EX_H */
00100
00101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr.c Source File

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stm32f7xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Power Controller (PWR) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f7xx_hal.h"
00045
00046 /** @addtogroup STM32F7xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup PWR PWR
00051   * @brief PWR HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_PWR_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @addtogroup PWR_Private_Constants
00060   * @{
00061   */
00062
00063 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00064   * @{
00065   */
00066 #define PVD_MODE_IT               ((uint32_t)0x00010000)
00067 #define PVD_MODE_EVT              ((uint32_t)0x00020000)
00068 #define PVD_RISING_EDGE           ((uint32_t)0x00000001)
00069 #define PVD_FALLING_EDGE          ((uint32_t)0x00000002)
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
00075   * @{
00076   */
00077 #define  PWR_EWUP_MASK                          ((uint32_t)0x00003F00)
00078 /**
00079   * @}
00080   */
00081
00082 /**
00083   * @}
00084   */
00085 /* Private macro -------------------------------------------------------------*/
00086 /* Private variables ---------------------------------------------------------*/
00087 /* Private function prototypes -----------------------------------------------*/
00088 /* Private functions ---------------------------------------------------------*/
00089
00090 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00091   * @{
00092   */
00093
00094 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00095   *  @brief    Initialization and de-initialization functions
00096   *
00097 @verbatim
00098  ===============================================================================
00099               ##### Initialization and de-initialization functions #####
00100  ===============================================================================
00101     [..]
00102       After reset, the backup domain (RTC registers, RTC backup data
00103       registers and backup SRAM) is protected against possible unwanted
00104       write accesses.
00105       To enable access to the RTC Domain and RTC registers, proceed as follows:
00106         (+) Enable the Power Controller (PWR) APB1 interface clock using the
00107             __HAL_RCC_PWR_CLK_ENABLE() macro.
00108         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00109
00110 @endverbatim
00111   * @{
00112   */
00113
00114 /**
00115   * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
00116   * @retval None
00117   */
00118 void HAL_PWR_DeInit(void)
00119 {
00120   __HAL_RCC_PWR_FORCE_RESET();
00121   __HAL_RCC_PWR_RELEASE_RESET();
00122 }
00123
00124 /**
00125   * @brief Enables access to the backup domain (RTC registers, RTC
00126   *         backup data registers and backup SRAM).
00127   * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00128   *         Backup Domain Access should be kept enabled.
00129   * @retval None
00130   */
00131 void HAL_PWR_EnableBkUpAccess(void)
00132 {
00133   /* Enable access to RTC and backup registers */
00134   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00135 }
00136
00137 /**
00138   * @brief Disables access to the backup domain (RTC registers, RTC
00139   *         backup data registers and backup SRAM).
00140   * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00141   *         Backup Domain Access should be kept enabled.
00142   * @retval None
00143   */
00144 void HAL_PWR_DisableBkUpAccess(void)
00145 {
00146   /* Disable access to RTC and backup registers */
00147         CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00148 }
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00155   *  @brief Low Power modes configuration functions
00156   *
00157 @verbatim
00158
00159  ===============================================================================
00160                  ##### Peripheral Control functions #####
00161  ===============================================================================
00162
00163     *** PVD configuration ***
00164     =========================
00165     [..]
00166       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00167           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
00168       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
00169           than the PVD threshold. This event is internally connected to the EXTI
00170           line16 and can generate an interrupt if enabled. This is done through
00171           __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
00172       (+) The PVD is stopped in Standby mode.
00173
00174     *** Wake-up pin configuration ***
00175     ================================
00176     [..]
00177       (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
00178           forced in input pull-down configuration and is active on rising edges.
00179       (+) There are to 6 Wake-up pin in the STM32F7 devices family
00180
00181     *** Low Power modes configuration ***
00182     =====================================
00183     [..]
00184       The devices feature 3 low-power modes:
00185       (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
00186       (+) Stop mode: all clocks are stopped, regulator running, regulator
00187           in low power mode
00188       (+) Standby mode: 1.2V domain powered off.
00189
00190    *** Sleep mode ***
00191    ==================
00192     [..]
00193       (+) Entry:
00194         The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
00195               functions with
00196           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00197           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00198
00199       -@@- The Regulator parameter is not used for the STM32F7 family
00200               and is kept as parameter just to maintain compatibility with the
00201               lower power families (STM32L).
00202       (+) Exit:
00203         Any peripheral interrupt acknowledged by the nested vectored interrupt
00204               controller (NVIC) can wake up the device from Sleep mode.
00205
00206    *** Stop mode ***
00207    =================
00208     [..]
00209       In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
00210       and the HSE RC oscillators are disabled. Internal SRAM and register contents
00211       are preserved.
00212       The voltage regulator can be configured either in normal or low-power mode.
00213       To minimize the consumption In Stop mode, FLASH can be powered off before
00214       entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
00215       It can be switched on again by software after exiting the Stop mode using
00216       the HAL_PWREx_DisableFlashPowerDown() function.
00217
00218       (+) Entry:
00219          The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
00220              function with:
00221           (++) Main regulator ON.
00222           (++) Low Power regulator ON.
00223       (+) Exit:
00224         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00225
00226    *** Standby mode ***
00227    ====================
00228     [..]
00229     (+)
00230       The Standby mode allows to achieve the lowest power consumption. It is based
00231       on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
00232       The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
00233       the HSE oscillator are also switched off. SRAM and register contents are lost
00234       except for the RTC registers, RTC backup registers, backup SRAM and Standby
00235       circuitry.
00236
00237       The voltage regulator is OFF.
00238
00239       (++) Entry:
00240         (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
00241       (++) Exit:
00242         (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
00243              wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
00244
00245    *** Auto-wakeup (AWU) from low-power mode ***
00246    =============================================
00247     [..]
00248
00249      (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00250       Wakeup event, a tamper event or a time-stamp event, without depending on
00251       an external interrupt (Auto-wakeup mode).
00252
00253       (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
00254
00255         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00256               configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00257
00258         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00259              is necessary to configure the RTC to detect the tamper or time stamp event using the
00260                 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00261
00262         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00263               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00264
00265 @endverbatim
00266   * @{
00267   */
00268
00269 /**
00270   * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00271   * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
00272   *        information for the PVD.
00273   * @note Refer to the electrical characteristics of your device datasheet for
00274   *         more details about the voltage threshold corresponding to each
00275   *         detection level.
00276   * @retval None
00277   */
00278 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00279 {
00280   /* Check the parameters */
00281   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00282   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00283
00284   /* Set PLS[7:5] bits according to PVDLevel value */
00285   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
00286
00287   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00288   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00289   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00290   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00291   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00292
00293   /* Configure interrupt mode */
00294   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00295   {
00296     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00297   }
00298
00299   /* Configure event mode */
00300   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00301   {
00302     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00303   }
00304
00305   /* Configure the edge */
00306   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00307   {
00308     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00309   }
00310
00311   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00312   {
00313     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00314   }
00315 }
00316
00317 /**
00318   * @brief Enables the Power Voltage Detector(PVD).
00319   * @retval None
00320   */
00321 void HAL_PWR_EnablePVD(void)
00322 {
00323   /* Enable the power voltage detector */
00324         SET_BIT(PWR->CR1, PWR_CR1_PVDE);
00325 }
00326
00327 /**
00328   * @brief Disables the Power Voltage Detector(PVD).
00329   * @retval None
00330   */
00331 void HAL_PWR_DisablePVD(void)
00332 {
00333   /* Disable the power voltage detector */
00334         CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
00335 }
00336
00337 /**
00338   * @brief Enable the WakeUp PINx functionality.
00339   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
00340   *         This parameter can be one of the following legacy values, which sets the default polarity:
00341   *         detection on high level (rising edge):
00342   *           @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
00343   *         or one of the following value where the user can explicitly states the enabled pin and
00344   *         the chosen polarity
00345   *           @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00346   *           @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00347   *           @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00348   *           @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00349   *           @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00350   *           @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
00351   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00352   * @retval None
00353   */
00354 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00355 {
00356   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00357
00358   /* Enable wake-up pin */
00359   SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
00360
00361   /* Specifies the Wake-Up pin polarity for the event detection
00362     (rising or falling edge) */
00363   MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
00364 }
00365
00366 /**
00367   * @brief Disables the WakeUp PINx functionality.
00368   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00369   *         This parameter can be one of the following values:
00370   *           @arg PWR_WAKEUP_PIN1
00371   *           @arg PWR_WAKEUP_PIN2
00372   *           @arg PWR_WAKEUP_PIN3
00373   *           @arg PWR_WAKEUP_PIN4
00374   *           @arg PWR_WAKEUP_PIN5
00375   *           @arg PWR_WAKEUP_PIN6
00376   * @retval None
00377   */
00378 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00379 {
00380   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00381
00382   CLEAR_BIT(PWR->CSR2, WakeUpPinx);
00383 }
00384
00385 /**
00386   * @brief Enters Sleep mode.
00387   *
00388   * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
00389   *
00390   * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
00391   *       systick interrupt when used as time base for Timeout
00392   *
00393   * @param Regulator: Specifies the regulator state in SLEEP mode.
00394   *            This parameter can be one of the following values:
00395   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
00396   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
00397   * @note This parameter is not used for the STM32F7 family and is kept as parameter
00398   *       just to maintain compatibility with the lower power families.
00399   * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
00400   *          This parameter can be one of the following values:
00401   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00402   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00403   * @retval None
00404   */
00405 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00406 {
00407   /* Check the parameters */
00408   assert_param(IS_PWR_REGULATOR(Regulator));
00409   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00410
00411   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00412   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00413
00414   /* Select SLEEP mode entry -------------------------------------------------*/
00415   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00416   {
00417     /* Request Wait For Interrupt */
00418     __WFI();
00419   }
00420   else
00421   {
00422     /* Request Wait For Event */
00423     __SEV();
00424     __WFE();
00425     __WFE();
00426   }
00427 }
00428
00429 /**
00430   * @brief Enters Stop mode.
00431   * @note In Stop mode, all I/O pins keep the same state as in Run mode.
00432   * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
00433   *         the HSI RC oscillator is selected as system clock.
00434   * @note When the voltage regulator operates in low power mode, an additional
00435   *         startup delay is incurred when waking up from Stop mode.
00436   *         By keeping the internal regulator ON during Stop mode, the consumption
00437   *         is higher although the startup time is reduced.
00438   * @param Regulator: Specifies the regulator state in Stop mode.
00439   *          This parameter can be one of the following values:
00440   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
00441   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
00442   * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
00443   *          This parameter can be one of the following values:
00444   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
00445   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
00446   * @retval None
00447   */
00448 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00449 {
00450   uint32_t tmpreg = 0;
00451
00452   /* Check the parameters */
00453   assert_param(IS_PWR_REGULATOR(Regulator));
00454   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00455
00456   /* Select the regulator state in Stop mode ---------------------------------*/
00457   tmpreg = PWR->CR1;
00458   /* Clear PDDS and LPDS bits */
00459   tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
00460
00461   /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
00462   tmpreg |= Regulator;
00463
00464   /* Store the new value */
00465   PWR->CR1 = tmpreg;
00466
00467   /* Set SLEEPDEEP bit of Cortex System Control Register */
00468   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00469
00470   /* Select Stop mode entry --------------------------------------------------*/
00471   if(STOPEntry == PWR_STOPENTRY_WFI)
00472   {
00473     /* Request Wait For Interrupt */
00474     __WFI();
00475   }
00476   else
00477   {
00478     /* Request Wait For Event */
00479     __SEV();
00480     __WFE();
00481     __WFE();
00482   }
00483   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00484   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00485 }
00486
00487 /**
00488   * @brief Enters Standby mode.
00489   * @note In Standby mode, all I/O pins are high impedance except for:
00490   *          - Reset pad (still available)
00491   *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
00492   *            Alarm out, or RTC clock calibration out.
00493   *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
00494   *          - WKUP pins if enabled.
00495   * @retval None
00496   */
00497 void HAL_PWR_EnterSTANDBYMode(void)
00498 {
00499   /* Select Standby mode */
00500   PWR->CR1 |= PWR_CR1_PDDS;
00501
00502   /* Set SLEEPDEEP bit of Cortex System Control Register */
00503   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00504
00505   /* This option is used to ensure that store operations are completed */
00506 #if defined ( __CC_ARM)
00507   __force_stores();
00508 #endif
00509   /* Request Wait For Interrupt */
00510   __WFI();
00511 }
00512
00513 /**
00514   * @brief This function handles the PWR PVD interrupt request.
00515   * @note This API should be called under the PVD_IRQHandler().
00516   * @retval None
00517   */
00518 void HAL_PWR_PVD_IRQHandler(void)
00519 {
00520   /* Check PWR Exti flag */
00521   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
00522   {
00523     /* PWR PVD interrupt user callback */
00524     HAL_PWR_PVDCallback();
00525
00526     /* Clear PWR Exti pending bit */
00527     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
00528   }
00529 }
00530
00531 /**
00532   * @brief  PWR PVD interrupt callback
00533   * @retval None
00534   */
00535 __weak void HAL_PWR_PVDCallback(void)
00536 {
00537   /* Prevent unused argument(s) compilation warning */
00538 __IO uint32_t tmpreg = 0x00;
00539   UNUSED(tmpreg);
00540
00541   /* NOTE : This function Should not be modified, when the callback is needed,
00542             the HAL_PWR_PVDCallback could be implemented in the user file
00543    */
00544 }
00545
00546 /**
00547   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
00548   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00549   *       re-enters SLEEP mode when an interruption handling is over.
00550   *       Setting this bit is useful when the processor is expected to run only on
00551   *       interruptions handling.
00552   * @retval None
00553   */
00554 void HAL_PWR_EnableSleepOnExit(void)
00555 {
00556   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00557   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00558 }
00559
00560 /**
00561   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00562   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00563   *       re-enters SLEEP mode when an interruption handling is over.
00564   * @retval None
00565   */
00566 void HAL_PWR_DisableSleepOnExit(void)
00567 {
00568   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00569   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00570 }
00571
00572 /**
00573   * @brief Enables CORTEX M4 SEVONPEND bit.
00574   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
00575   *       WFE to wake up when an interrupt moves from inactive to pended.
00576   * @retval None
00577   */
00578 void HAL_PWR_EnableSEVOnPend(void)
00579 {
00580   /* Set SEVONPEND bit of Cortex System Control Register */
00581   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00582 }
00583
00584 /**
00585   * @brief Disables CORTEX M4 SEVONPEND bit.
00586   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
00587   *       WFE to wake up when an interrupt moves from inactive to pended.
00588   * @retval None
00589   */
00590 void HAL_PWR_DisableSEVOnPend(void)
00591 {
00592   /* Clear SEVONPEND bit of Cortex System Control Register */
00593   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00594 }
00595
00596 /**
00597   * @}
00598   */
00599
00600 /**
00601   * @}
00602   */
00603
00604 #endif /* HAL_PWR_MODULE_ENABLED */
00605 /**
00606   * @}
00607   */
00608
00609 /**
00610   * @}
00611   */
00612
00613 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr.h Source File

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stm32f7xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of PWR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_PWR_H
00040 #define __STM32F7xx_HAL_PWR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWR
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup PWR_Exported_Types PWR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PWR PVD configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
00069                             This parameter can be a value of @ref PWR_PVD_detection_level */
00070
00071   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00072                            This parameter can be a value of @ref PWR_PVD_Mode */
00073 }PWR_PVDTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
00085   * @{
00086   */
00087 #define PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0
00088 #define PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1
00089 #define PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2
00090 #define PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3
00091 #define PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4
00092 #define PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5
00093 #define PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6
00094 #define PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7/* External input analog voltage
00095                                                           (Compare internally to VREFINT) */
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup PWR_PVD_Mode PWR PVD Mode
00102   * @{
00103   */
00104 #define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
00105 #define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
00106 #define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
00107 #define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00108 #define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
00109 #define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
00110 #define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
00116   * @{
00117   */
00118 #define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000)
00119 #define PWR_LOWPOWERREGULATOR_ON                    PWR_CR1_LPDS
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
00125   * @{
00126   */
00127 #define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
00128 #define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
00134   * @{
00135   */
00136 #define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
00137 #define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
00143   * @{
00144   */
00145 #define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR1_VOS
00146 #define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR1_VOS_1
00147 #define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR1_VOS_0
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup PWR_Flag PWR Flag
00153   * @{
00154   */
00155 #define PWR_FLAG_WU                     PWR_CSR1_WUIF
00156 #define PWR_FLAG_SB                     PWR_CSR1_SBF
00157 #define PWR_FLAG_PVDO                   PWR_CSR1_PVDO
00158 #define PWR_FLAG_BRR                    PWR_CSR1_BRR
00159 #define PWR_FLAG_VOSRDY                 PWR_CSR1_VOSRDY
00160 /**
00161   * @}
00162   */
00163
00164 /**
00165   * @}
00166   */
00167
00168 /* Exported macro ------------------------------------------------------------*/
00169 /** @defgroup PWR_Exported_Macro PWR Exported Macro
00170   * @{
00171   */
00172
00173 /** @brief  macros configure the main internal regulator output voltage.
00174   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00175   *         a tradeoff between performance and power consumption when the device does
00176   *         not operate at the maximum frequency (refer to the datasheets for more details).
00177   *          This parameter can be one of the following values:
00178   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
00179   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
00180   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
00181   * @retval None
00182   */
00183 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00184                                                           __IO uint32_t tmpreg = 0x00;                               \
00185                                                             MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
00186                                                             /* Delay after an RCC peripheral clock enabling */  \
00187                                                             tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
00188                                                             UNUSED(tmpreg);                                     \
00189                                                                                         } while(0)
00190
00191 /** @brief  Check PWR flag is set or not.
00192   * @param  __FLAG__: specifies the flag to check.
00193   *           This parameter can be one of the following values:
00194   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
00195   *                  was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),
00196   *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).
00197   *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
00198   *                  resumed from StandBy mode.
00199   *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
00200   *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
00201   *                  For this reason, this bit is equal to 0 after Standby or reset
00202   *                  until the PVDE bit is set.
00203   *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
00204   *                  when the device wakes up from Standby mode or by a system reset
00205   *                  or power reset.
00206   *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
00207   *                 scaling output selection is ready.
00208   * @retval The new state of __FLAG__ (TRUE or FALSE).
00209   */
00210 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
00211
00212 /** @brief  Clear the PWR's pending flags.
00213   * @param  __FLAG__: specifies the flag to clear.
00214   *          This parameter can be one of the following values:
00215   *            @arg PWR_FLAG_SB: StandBy flag
00216   */
00217 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |=  (__FLAG__) << 2)
00218
00219 /**
00220   * @brief Enable the PVD Exti Line 16.
00221   * @retval None.
00222   */
00223 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
00224
00225 /**
00226   * @brief Disable the PVD EXTI Line 16.
00227   * @retval None.
00228   */
00229 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
00230
00231 /**
00232   * @brief Enable event on PVD Exti Line 16.
00233   * @retval None.
00234   */
00235 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
00236
00237 /**
00238   * @brief Disable event on PVD Exti Line 16.
00239   * @retval None.
00240   */
00241 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
00242
00243 /**
00244   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00245   * @retval None.
00246   */
00247 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00248
00249 /**
00250   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00251   * @retval None.
00252   */
00253 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00254
00255 /**
00256   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00257   * @retval None.
00258   */
00259 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00260
00261
00262 /**
00263   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00264   * @retval None.
00265   */
00266 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00267
00268
00269 /**
00270   * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
00271   * @retval None.
00272   */
00273 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00274
00275 /**
00276   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00277   * @retval None.
00278   */
00279 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00280
00281 /**
00282   * @brief checks whether the specified PVD Exti interrupt flag is set or not.
00283   * @retval EXTI PVD Line Status.
00284   */
00285 #define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
00286
00287 /**
00288   * @brief Clear the PVD Exti flag.
00289   * @retval None.
00290   */
00291 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
00292
00293 /**
00294   * @brief  Generates a Software interrupt on PVD EXTI line.
00295   * @retval None
00296   */
00297 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
00298
00299 /**
00300   * @}
00301   */
00302
00303 /* Include PWR HAL Extension module */
00304 #include "stm32f7xx_hal_pwr_ex.h"
00305
00306 /* Exported functions --------------------------------------------------------*/
00307 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00308   * @{
00309   */
00310
00311 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00312   * @{
00313   */
00314 /* Initialization and de-initialization functions *****************************/
00315 void HAL_PWR_DeInit(void);
00316 void HAL_PWR_EnableBkUpAccess(void);
00317 void HAL_PWR_DisableBkUpAccess(void);
00318 /**
00319   * @}
00320   */
00321
00322 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00323   * @{
00324   */
00325 /* Peripheral Control functions  **********************************************/
00326 /* PVD configuration */
00327 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00328 void HAL_PWR_EnablePVD(void);
00329 void HAL_PWR_DisablePVD(void);
00330
00331 /* WakeUp pins configuration */
00332 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00333 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00334
00335 /* Low Power modes entry */
00336 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00337 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00338 void HAL_PWR_EnterSTANDBYMode(void);
00339
00340 /* Power PVD IRQ Handler */
00341 void HAL_PWR_PVD_IRQHandler(void);
00342 void HAL_PWR_PVDCallback(void);
00343
00344 /* Cortex System Control functions  *******************************************/
00345 void HAL_PWR_EnableSleepOnExit(void);
00346 void HAL_PWR_DisableSleepOnExit(void);
00347 void HAL_PWR_EnableSEVOnPend(void);
00348 void HAL_PWR_DisableSEVOnPend(void);
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 /* Private types -------------------------------------------------------------*/
00358 /* Private variables ---------------------------------------------------------*/
00359 /* Private constants ---------------------------------------------------------*/
00360 /** @defgroup PWR_Private_Constants PWR Private Constants
00361   * @{
00362   */
00363
00364 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
00365   * @{
00366   */
00367 #define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00368 /**
00369   * @}
00370   */
00371
00372 /**
00373   * @}
00374   */
00375 /* Private macros ------------------------------------------------------------*/
00376 /** @defgroup PWR_Private_Macros PWR Private Macros
00377   * @{
00378   */
00379
00380 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
00381   * @{
00382   */
00383 #define IS_PWR_WAKEUP_POLARITY(POLARITY)       (((POLARITY) == PWR_POLARITY_RISINGEDGE)  || \
00384                                                     ((POLARITY) == PWR_POLARITY_FALLINGEDGE))
00385 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00386                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00387                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00388                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00389 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
00390                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
00391                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
00392                               ((MODE) == PWR_PVD_MODE_NORMAL))
00393 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00394                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00395 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00396 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
00397 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00398                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
00399                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
00400
00401 /**
00402   * @}
00403   */
00404
00405 /**
00406   * @}
00407   */
00408
00409 /**
00410   * @}
00411   */
00412
00413 /**
00414   * @}
00415   */
00416
00417 #ifdef __cplusplus
00418 }
00419 #endif
00420
00421
00422 #endif /* __STM32F7xx_HAL_PWR_H */
00423
00424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr_ex.c Source File

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stm32f7xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Extended PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of PWR extension peripheral:
00010   *           + Peripheral Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f7xx_hal.h"
00044
00045 /** @addtogroup STM32F7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PWREx PWREx
00050   * @brief PWR HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_PWR_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @addtogroup PWREx_Private_Constants
00059   * @{
00060   */
00061 #define PWR_OVERDRIVE_TIMEOUT_VALUE  1000
00062 #define PWR_UDERDRIVE_TIMEOUT_VALUE  1000
00063 #define PWR_BKPREG_TIMEOUT_VALUE     1000
00064 #define PWR_VOSRDY_TIMEOUT_VALUE     1000
00065 /**
00066   * @}
00067   */
00068
00069 /* Private macro -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
00074   *  @{
00075   */
00076
00077 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
00078   *  @brief Peripheral Extended features functions
00079   *
00080 @verbatim
00081
00082  ===============================================================================
00083                  ##### Peripheral extended features functions #####
00084  ===============================================================================
00085
00086     *** Main and Backup Regulators configuration ***
00087     ================================================
00088     [..]
00089       (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
00090           the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
00091           retained even in Standby or VBAT mode when the low power backup regulator
00092           is enabled. It can be considered as an internal EEPROM when VBAT is
00093           always present. You can use the HAL_PWREx_EnableBkUpReg() function to
00094           enable the low power backup regulator.
00095
00096       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
00097           the backup SRAM is powered from VDD which replaces the VBAT power supply to
00098           save battery life.
00099
00100       (+) The backup SRAM is not mass erased by a tamper event. It is read
00101           protected to prevent confidential data, such as cryptographic private
00102           key, from being accessed. The backup SRAM can be erased only through
00103           the Flash interface when a protection level change from level 1 to
00104           level 0 is requested.
00105       -@- Refer to the description of Read protection (RDP) in the Flash
00106           programming manual.
00107
00108       (+) The main internal regulator can be configured to have a tradeoff between
00109           performance and power consumption when the device does not operate at
00110           the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
00111           macro which configure VOS bit in PWR_CR register
00112
00113         Refer to the product datasheets for more details.
00114
00115     *** FLASH Power Down configuration ****
00116     =======================================
00117     [..]
00118       (+) By setting the FPDS bit in the PWR_CR register by using the
00119           HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
00120           down mode when the device enters Stop mode. When the Flash memory
00121           is in power down mode, an additional startup delay is incurred when
00122           waking up from Stop mode.
00123
00124     *** Over-Drive and Under-Drive configuration ****
00125     =================================================
00126     [..]
00127        (+) In Run mode: the main regulator has 2 operating modes available:
00128         (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
00129              voltage scaling (scale 1, scale 2 or scale 3)
00130         (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
00131             higher frequency than the normal mode for a given voltage scaling (scale 1,
00132             scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
00133             disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
00134             the sequence described in Reference manual.
00135
00136        (+) In Stop mode: the main regulator or low power regulator supplies a low power
00137            voltage to the 1.2V domain, thus preserving the content of registers
00138            and internal SRAM. 2 operating modes are available:
00139          (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
00140               available when the main regulator or the low power regulator is used in Scale 3 or
00141               low voltage mode.
00142          (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
00143               available when the main regulator or the low power regulator is in low voltage mode.
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149 /**
00150   * @brief Enables the Backup Regulator.
00151   * @retval HAL status
00152   */
00153 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
00154 {
00155   uint32_t tickstart = 0;
00156
00157   /* Enable Backup regulator */
00158   PWR->CSR1 |= PWR_CSR1_BRE;
00159
00160   /* Get tick */
00161   tickstart = HAL_GetTick();
00162
00163   /* Wait till Backup regulator ready flag is set */
00164   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
00165   {
00166     if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
00167     {
00168       return HAL_TIMEOUT;
00169     }
00170   }
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief Disables the Backup Regulator.
00176   * @retval HAL status
00177   */
00178 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
00179 {
00180   uint32_t tickstart = 0;
00181
00182   /* Disable Backup regulator */
00183   PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
00184
00185   /* Get tick */
00186   tickstart = HAL_GetTick();
00187
00188   /* Wait till Backup regulator ready flag is set */
00189   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
00190   {
00191     if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
00192     {
00193       return HAL_TIMEOUT;
00194     }
00195   }
00196   return HAL_OK;
00197 }
00198
00199 /**
00200   * @brief Enables the Flash Power Down in Stop mode.
00201   * @retval None
00202   */
00203 void HAL_PWREx_EnableFlashPowerDown(void)
00204 {
00205   /* Enable the Flash Power Down */
00206   PWR->CR1 |= PWR_CR1_FPDS;
00207 }
00208
00209 /**
00210   * @brief Disables the Flash Power Down in Stop mode.
00211   * @retval None
00212   */
00213 void HAL_PWREx_DisableFlashPowerDown(void)
00214 {
00215   /* Disable the Flash Power Down */
00216   PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
00217 }
00218
00219 /**
00220   * @brief Enables Main Regulator low voltage mode.
00221   * @retval None
00222   */
00223 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
00224 {
00225   /* Enable Main regulator low voltage */
00226   PWR->CR1 |= PWR_CR1_MRUDS;
00227 }
00228
00229 /**
00230   * @brief Disables Main Regulator low voltage mode.
00231   * @retval None
00232   */
00233 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
00234 {
00235   /* Disable Main regulator low voltage */
00236   PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
00237 }
00238
00239 /**
00240   * @brief Enables Low Power Regulator low voltage mode.
00241   * @retval None
00242   */
00243 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
00244 {
00245   /* Enable low power regulator */
00246   PWR->CR1 |= PWR_CR1_LPUDS;
00247 }
00248
00249 /**
00250   * @brief Disables Low Power Regulator low voltage mode.
00251   * @retval None
00252   */
00253 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
00254 {
00255   /* Disable low power regulator */
00256   PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
00257 }
00258
00259 /**
00260   * @brief  Activates the Over-Drive mode.
00261   * @note   This mode allows the CPU and the core logic to operate at a higher frequency
00262   *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
00263   * @note   It is recommended to enter or exit Over-drive mode when the application is not running
00264   *         critical tasks and when the system clock source is either HSI or HSE.
00265   *         During the Over-drive switch activation, no peripheral clocks should be enabled.
00266   *         The peripheral clocks must be enabled once the Over-drive mode is activated.
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
00270 {
00271   uint32_t tickstart = 0;
00272
00273   __HAL_RCC_PWR_CLK_ENABLE();
00274
00275   /* Enable the Over-drive to extend the clock frequency to 216 MHz */
00276   __HAL_PWR_OVERDRIVE_ENABLE();
00277
00278   /* Get tick */
00279   tickstart = HAL_GetTick();
00280
00281   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
00282   {
00283     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00284     {
00285       return HAL_TIMEOUT;
00286     }
00287   }
00288
00289   /* Enable the Over-drive switch */
00290   __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
00291
00292   /* Get tick */
00293   tickstart = HAL_GetTick();
00294
00295   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
00296   {
00297     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00298     {
00299       return HAL_TIMEOUT;
00300     }
00301   }
00302   return HAL_OK;
00303 }
00304
00305 /**
00306   * @brief  Deactivates the Over-Drive mode.
00307   * @note   This mode allows the CPU and the core logic to operate at a higher frequency
00308   *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
00309   * @note   It is recommended to enter or exit Over-drive mode when the application is not running
00310   *         critical tasks and when the system clock source is either HSI or HSE.
00311   *         During the Over-drive switch activation, no peripheral clocks should be enabled.
00312   *         The peripheral clocks must be enabled once the Over-drive mode is activated.
00313   * @retval HAL status
00314   */
00315 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
00316 {
00317   uint32_t tickstart = 0;
00318
00319   __HAL_RCC_PWR_CLK_ENABLE();
00320
00321   /* Disable the Over-drive switch */
00322   __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
00323
00324   /* Get tick */
00325   tickstart = HAL_GetTick();
00326
00327   while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
00328   {
00329     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00330     {
00331       return HAL_TIMEOUT;
00332     }
00333   }
00334
00335   /* Disable the Over-drive */
00336   __HAL_PWR_OVERDRIVE_DISABLE();
00337
00338   /* Get tick */
00339   tickstart = HAL_GetTick();
00340
00341   while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
00342   {
00343     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00344     {
00345       return HAL_TIMEOUT;
00346     }
00347   }
00348
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief  Enters in Under-Drive STOP mode.
00354   *
00355   * @note    This mode can be selected only when the Under-Drive is already active
00356   *
00357   * @note    This mode is enabled only with STOP low power mode.
00358   *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This
00359   *          mode is only available when the main regulator or the low power regulator
00360   *          is in low voltage mode
00361   *
00362   * @note   If the Under-drive mode was enabled, it is automatically disabled after
00363   *         exiting Stop mode.
00364   *         When the voltage regulator operates in Under-drive mode, an additional
00365   *         startup delay is induced when waking up from Stop mode.
00366   *
00367   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
00368   *
00369   * @note   When exiting Stop mode by issuing an interrupt or a wakeup event,
00370   *         the HSI RC oscillator is selected as system clock.
00371   *
00372   * @note   When the voltage regulator operates in low power mode, an additional
00373   *         startup delay is incurred when waking up from Stop mode.
00374   *         By keeping the internal regulator ON during Stop mode, the consumption
00375   *         is higher although the startup time is reduced.
00376   *
00377   * @param  Regulator: specifies the regulator state in STOP mode.
00378   *          This parameter can be one of the following values:
00379   *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode
00380   *                 and Flash memory in power-down when the device is in Stop under-drive mode
00381   *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode
00382   *                and Flash memory in power-down when the device is in Stop under-drive mode
00383   * @param  STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
00384   *          This parameter can be one of the following values:
00385   *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
00386   *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
00387   * @retval None
00388   */
00389 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00390 {
00391   uint32_t tempreg = 0;
00392   uint32_t tickstart = 0;
00393
00394   /* Check the parameters */
00395   assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
00396   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00397
00398   /* Enable Power ctrl clock */
00399   __HAL_RCC_PWR_CLK_ENABLE();
00400   /* Enable the Under-drive Mode ---------------------------------------------*/
00401   /* Clear Under-drive flag */
00402   __HAL_PWR_CLEAR_ODRUDR_FLAG();
00403
00404   /* Enable the Under-drive */
00405   __HAL_PWR_UNDERDRIVE_ENABLE();
00406
00407   /* Get tick */
00408   tickstart = HAL_GetTick();
00409
00410   /* Wait for UnderDrive mode is ready */
00411   while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
00412   {
00413     if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
00414     {
00415       return HAL_TIMEOUT;
00416     }
00417   }
00418
00419   /* Select the regulator state in STOP mode ---------------------------------*/
00420   tempreg = PWR->CR1;
00421   /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
00422   tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
00423
00424   /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
00425   tempreg |= Regulator;
00426
00427   /* Store the new value */
00428   PWR->CR1 = tempreg;
00429
00430   /* Set SLEEPDEEP bit of Cortex System Control Register */
00431   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00432
00433   /* Select STOP mode entry --------------------------------------------------*/
00434   if(STOPEntry == PWR_SLEEPENTRY_WFI)
00435   {
00436     /* Request Wait For Interrupt */
00437     __WFI();
00438   }
00439   else
00440   {
00441     /* Request Wait For Event */
00442     __WFE();
00443   }
00444   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00445   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00446
00447   return HAL_OK;
00448 }
00449
00450 /**
00451   * @brief Returns Voltage Scaling Range.
00452   * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
00453   *            PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
00454   */
00455 uint32_t HAL_PWREx_GetVoltageRange(void)
00456 {
00457   return  (PWR->CR1 & PWR_CR1_VOS);
00458 }
00459
00460 /**
00461   * @brief Configures the main internal regulator output voltage.
00462   * @param  VoltageScaling: specifies the regulator output voltage to achieve
00463   *         a tradeoff between performance and power consumption.
00464   *          This parameter can be one of the following values:
00465   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
00466   *                                                typical output voltage at 1.4 V,
00467   *                                                system frequency up to 216 MHz.
00468   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
00469   *                                                typical output voltage at 1.2 V,
00470   *                                                system frequency up to 180 MHz.
00471   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
00472   *                                                typical output voltage at 1.00 V,
00473   *                                                system frequency up to 151 MHz.
00474   * @note To update the system clock frequency(SYSCLK):
00475   *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
00476   *        - Call the HAL_RCC_OscConfig() to configure the PLL.
00477   *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
00478   *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
00479   * @note The scale can be modified only when the HSI or HSE clock source is selected
00480   *        as system clock source, otherwise the API returns HAL_ERROR.
00481   * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
00482   *       value in the PWR_CR1 register are not taken in account.
00483   * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
00484   * @note The new voltage scale is active only when the PLL is ON.
00485   * @retval HAL Status
00486   */
00487 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00488 {
00489   uint32_t tickstart = 0;
00490
00491   assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
00492
00493   /* Enable Power ctrl clock */
00494   __HAL_RCC_PWR_CLK_ENABLE();
00495
00496   /* Check if the PLL is used as system clock or not */
00497   if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00498   {
00499     /* Disable the main PLL */
00500     __HAL_RCC_PLL_DISABLE();
00501
00502     /* Get Start Tick */
00503     tickstart = HAL_GetTick();
00504     /* Wait till PLL is disabled */
00505     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00506     {
00507       if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00508       {
00509         return HAL_TIMEOUT;
00510       }
00511     }
00512
00513     /* Set Range */
00514     __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
00515
00516     /* Enable the main PLL */
00517     __HAL_RCC_PLL_ENABLE();
00518
00519     /* Get Start Tick */
00520     tickstart = HAL_GetTick();
00521     /* Wait till PLL is ready */
00522     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00523     {
00524       if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00525       {
00526         return HAL_TIMEOUT;
00527       }
00528     }
00529
00530     /* Get Start Tick */
00531     tickstart = HAL_GetTick();
00532     while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
00533     {
00534       if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
00535       {
00536         return HAL_TIMEOUT;
00537       }
00538     }
00539   }
00540   else
00541   {
00542     return HAL_ERROR;
00543   }
00544   return HAL_OK;
00545 }
00546
00547 /**
00548   * @}
00549   */
00550
00551 /**
00552   * @}
00553   */
00554
00555 #endif /* HAL_PWR_MODULE_ENABLED */
00556 /**
00557   * @}
00558   */
00559
00560 /**
00561   * @}
00562   */
00563
00564 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_pwr_ex.h Source File

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stm32f7xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of PWR HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_PWR_EX_H
00040 #define __STM32F7xx_HAL_PWR_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWREx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
00060   * @{
00061   */
00062 /** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins
00063   * @{
00064   */
00065 #define PWR_WAKEUP_PIN1                PWR_CSR2_EWUP1
00066 #define PWR_WAKEUP_PIN2                PWR_CSR2_EWUP2
00067 #define PWR_WAKEUP_PIN3                PWR_CSR2_EWUP3
00068 #define PWR_WAKEUP_PIN4                PWR_CSR2_EWUP4
00069 #define PWR_WAKEUP_PIN5                PWR_CSR2_EWUP5
00070 #define PWR_WAKEUP_PIN6                PWR_CSR2_EWUP6
00071 #define PWR_WAKEUP_PIN1_HIGH           PWR_CSR2_EWUP1
00072 #define PWR_WAKEUP_PIN2_HIGH           PWR_CSR2_EWUP2
00073 #define PWR_WAKEUP_PIN3_HIGH           PWR_CSR2_EWUP3
00074 #define PWR_WAKEUP_PIN4_HIGH           PWR_CSR2_EWUP4
00075 #define PWR_WAKEUP_PIN5_HIGH           PWR_CSR2_EWUP5
00076 #define PWR_WAKEUP_PIN6_HIGH           PWR_CSR2_EWUP6
00077 #define PWR_WAKEUP_PIN1_LOW            (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
00078 #define PWR_WAKEUP_PIN2_LOW            (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
00079 #define PWR_WAKEUP_PIN3_LOW            (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
00080 #define PWR_WAKEUP_PIN4_LOW            (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
00081 #define PWR_WAKEUP_PIN5_LOW            (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
00082 #define PWR_WAKEUP_PIN6_LOW            (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
00083
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
00089   * @{
00090   */
00091 #define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR1_MRUDS
00092 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
00098   * @{
00099   */
00100 #define PWR_FLAG_ODRDY                  PWR_CSR1_ODRDY
00101 #define PWR_FLAG_ODSWRDY                PWR_CSR1_ODSWRDY
00102 #define PWR_FLAG_UDRDY                  PWR_CSR1_UDSWRDY
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
00108   * @{
00109   */
00110 #define PWR_WAKEUP_PIN_FLAG1            PWR_CSR2_WUPF1
00111 #define PWR_WAKEUP_PIN_FLAG2            PWR_CSR2_WUPF2
00112 #define PWR_WAKEUP_PIN_FLAG3            PWR_CSR2_WUPF3
00113 #define PWR_WAKEUP_PIN_FLAG4            PWR_CSR2_WUPF4
00114 #define PWR_WAKEUP_PIN_FLAG5            PWR_CSR2_WUPF5
00115 #define PWR_WAKEUP_PIN_FLAG6            PWR_CSR2_WUPF6
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /* Exported macro ------------------------------------------------------------*/
00125 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro
00126   *  @{
00127   */
00128 /** @brief Macros to enable or disable the Over drive mode.
00129   */
00130 #define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
00131 #define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
00132
00133 /** @brief Macros to enable or disable the Over drive switching.
00134   */
00135 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
00136 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
00137
00138 /** @brief Macros to enable or disable the Under drive mode.
00139   * @note  This mode is enabled only with STOP low power mode.
00140   *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This
00141   *        mode is only available when the main regulator or the low power regulator
00142   *        is in low voltage mode.
00143   * @note  If the Under-drive mode was enabled, it is automatically disabled after
00144   *        exiting Stop mode.
00145   *        When the voltage regulator operates in Under-drive mode, an additional
00146   *        startup delay is induced when waking up from Stop mode.
00147   */
00148 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
00149 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
00150
00151 /** @brief  Check PWR flag is set or not.
00152   * @param  __FLAG__: specifies the flag to check.
00153   *         This parameter can be one of the following values:
00154   *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
00155   *                                 is ready
00156   *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
00157   *                                   switching is ready
00158   *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
00159   *                                 is enabled in Stop mode
00160   * @retval The new state of __FLAG__ (TRUE or FALSE).
00161   */
00162 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
00163
00164 /** @brief Clear the Under-Drive Ready flag.
00165   */
00166 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
00167
00168 /** @brief  Check Wake Up flag is set or not.
00169   * @param  __WUFLAG__: specifies the Wake Up flag to check.
00170   *          This parameter can be one of the following values:
00171   *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
00172   *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
00173   *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
00174   *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
00175   *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
00176   *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
00177   */
00178 #define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
00179
00180 /** @brief  Clear the WakeUp pins flags.
00181   * @param  __WUFLAG__: specifies the Wake Up pin flag to clear.
00182   *          This parameter can be one of the following values:
00183   *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
00184   *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
00185   *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
00186   *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
00187   *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
00188   *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
00189   */
00190 #define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |=  (__WUFLAG__))
00191 /**
00192   * @}
00193   */
00194 /* Exported functions --------------------------------------------------------*/
00195 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
00196   *  @{
00197   */
00198
00199 /** @addtogroup PWREx_Exported_Functions_Group1
00200   * @{
00201   */
00202 uint32_t HAL_PWREx_GetVoltageRange(void);
00203 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00204
00205 void HAL_PWREx_EnableFlashPowerDown(void);
00206 void HAL_PWREx_DisableFlashPowerDown(void);
00207 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
00208 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
00209
00210 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
00211 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
00212 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
00213 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
00214
00215 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
00216 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
00217 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00218
00219 /**
00220   * @}
00221   */
00222
00223 /**
00224   * @}
00225   */
00226 /* Private types -------------------------------------------------------------*/
00227 /* Private variables ---------------------------------------------------------*/
00228 /* Private constants ---------------------------------------------------------*/
00229 /* Private macros ------------------------------------------------------------*/
00230 /** @defgroup PWREx_Private_Macros PWREx Private Macros
00231   * @{
00232   */
00233
00234 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
00235   * @{
00236   */
00237 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
00238                                                 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
00239 #define IS_PWR_WAKEUP_PIN(__PIN__)         (((__PIN__) == PWR_WAKEUP_PIN1)       || \
00240                                             ((__PIN__) == PWR_WAKEUP_PIN2)       || \
00241                                             ((__PIN__) == PWR_WAKEUP_PIN3)       || \
00242                                             ((__PIN__) == PWR_WAKEUP_PIN4)       || \
00243                                             ((__PIN__) == PWR_WAKEUP_PIN5)       || \
00244                                             ((__PIN__) == PWR_WAKEUP_PIN6)               || \
00245                                             ((__PIN__) == PWR_WAKEUP_PIN1_HIGH)  || \
00246                                             ((__PIN__) == PWR_WAKEUP_PIN2_HIGH)  || \
00247                                             ((__PIN__) == PWR_WAKEUP_PIN3_HIGH)  || \
00248                                             ((__PIN__) == PWR_WAKEUP_PIN4_HIGH)  || \
00249                                             ((__PIN__) == PWR_WAKEUP_PIN5_HIGH)  || \
00250                                             ((__PIN__) == PWR_WAKEUP_PIN6_HIGH)  || \
00251                                             ((__PIN__) == PWR_WAKEUP_PIN1_LOW)   || \
00252                                             ((__PIN__) == PWR_WAKEUP_PIN2_LOW)   || \
00253                                             ((__PIN__) == PWR_WAKEUP_PIN3_LOW)   || \
00254                                             ((__PIN__) == PWR_WAKEUP_PIN4_LOW)   || \
00255                                             ((__PIN__) == PWR_WAKEUP_PIN5_LOW)   || \
00256                                             ((__PIN__) == PWR_WAKEUP_PIN6_LOW))
00257 /**
00258   * @}
00259   */
00260
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 #ifdef __cplusplus
00274 }
00275 #endif
00276
00277
00278 #endif /* __STM32F7xx_HAL_PWR_EX_H */
00279
00280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_qspi.c Source File

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stm32f7xx_hal_qspi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   QSPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the QuadSPI interface (QSPI).
00010   *           + Initialization and de-initialization functions
00011   *           + Indirect functional mode management
00012   *           + Memory-mapped functional mode management
00013   *           + Auto-polling functional mode management
00014   *           + Interrupts and flags management
00015   *           + DMA channel configuration for indirect functional mode
00016   *           + Errors management and abort functionality
00017   *
00018   *
00019   @verbatim
00020  ===============================================================================
00021                         ##### How to use this driver #####
00022  ===============================================================================
00023   [..]
00024     *** Initialization ***
00025     ======================
00026     [..]
00027       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00028         (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
00029         (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
00030         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00031         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00032         (++) If interrupt mode is used, enable and configure QuadSPI global
00033             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00034         (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
00035             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
00036             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00037             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00038       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00039           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00040
00041     *** Indirect functional mode ***
00042     ================================
00043     [..]
00044       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00045           functions :
00046          (++) Instruction phase : the mode used and if present the instruction opcode.
00047          (++) Address phase : the mode used and if present the size and the address value.
00048          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00049              bytes values.
00050          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00051          (++) Data phase : the mode used and if present the number of bytes.
00052          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00053              if activated.
00054          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00055       (#) If no data is required for the command, it is sent directly to the memory :
00056          (++) In polling mode, the output of the function is done when the transfer is complete.
00057          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00058       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00059           HAL_QSPI_Transmit_IT() after the command configuration :
00060          (++) In polling mode, the output of the function is done when the transfer is complete.
00061          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00062              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00063          (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
00064              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00065       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00066           HAL_QSPI_Receive_IT() after the command configuration :
00067          (++) In polling mode, the output of the function is done when the transfer is complete.
00068          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00069              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00070          (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
00071              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00072
00073     *** Auto-polling functional mode ***
00074     ====================================
00075     [..]
00076       (#) Configure the command sequence and the auto-polling functional mode using the
00077           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00078          (++) Instruction phase : the mode used and if present the instruction opcode.
00079          (++) Address phase : the mode used and if present the size and the address value.
00080          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00081              bytes values.
00082          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00083          (++) Data phase : the mode used.
00084          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00085              if activated.
00086          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00087          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00088              the polling interval and the automatic stop activation.
00089       (#) After the configuration :
00090          (++) In polling mode, the output of the function is done when the status match is reached. The
00091              automatic stop is activated to avoid an infinite loop.
00092          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00093
00094     *** Memory-mapped functional mode ***
00095     =====================================
00096     [..]
00097       (#) Configure the command sequence and the memory-mapped functional mode using the
00098           HAL_QSPI_MemoryMapped() functions :
00099          (++) Instruction phase : the mode used and if present the instruction opcode.
00100          (++) Address phase : the mode used and the size.
00101          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00102              bytes values.
00103          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00104          (++) Data phase : the mode used.
00105          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00106              if activated.
00107          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00108          (++) The timeout activation and the timeout period.
00109       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00110           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00111
00112     *** Errors management and abort functionality ***
00113     ==================================================
00114     [..]
00115       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
00116       (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
00117       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00118
00119     *** Workarounds linked to Silicon Limitation ***
00120     ====================================================
00121     [..]
00122       (#) Workarounds Implemented inside HAL Driver
00123          (++) Extra data written in the FIFO at the end of a read transfer
00124
00125   @endverbatim
00126   ******************************************************************************
00127   * @attention
00128   *
00129   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00130   *
00131   * Redistribution and use in source and binary forms, with or without modification,
00132   * are permitted provided that the following conditions are met:
00133   *   1. Redistributions of source code must retain the above copyright notice,
00134   *      this list of conditions and the following disclaimer.
00135   *   2. Redistributions in binary form must reproduce the above copyright notice,
00136   *      this list of conditions and the following disclaimer in the documentation
00137   *      and/or other materials provided with the distribution.
00138   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00139   *      may be used to endorse or promote products derived from this software
00140   *      without specific prior written permission.
00141   *
00142   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00143   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00144   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00145   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00146   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00147   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00148   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00149   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00150   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00151   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00152   *
00153   ******************************************************************************
00154   */
00155
00156 /* Includes ------------------------------------------------------------------*/
00157 #include "stm32f7xx_hal.h"
00158
00159 /** @addtogroup STM32F7xx_HAL_Driver
00160   * @{
00161   */
00162
00163 /** @defgroup QSPI QSPI
00164   * @brief HAL QSPI module driver
00165   * @{
00166   */
00167 #ifdef HAL_QSPI_MODULE_ENABLED
00168
00169 /* Private typedef -----------------------------------------------------------*/
00170 /* Private define ------------------------------------------------------------*/
00171 /** @addtogroup QSPI_Private_Constants
00172   * @{
00173   */
00174 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)          /*!<Indirect write mode*/
00175 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00176 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00177 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00178 /**
00179   * @}
00180   */
00181
00182 /* Private macro -------------------------------------------------------------*/
00183 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
00184   * @{
00185   */
00186 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00187                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00188                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00189                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00190 /**
00191   * @}
00192   */
00193
00194 /* Private variables ---------------------------------------------------------*/
00195 /* Private function prototypes -----------------------------------------------*/
00196 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
00197   * @{
00198   */
00199 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
00200 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
00201 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00202 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00203 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
00204 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
00205 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00206 /**
00207   * @}
00208   */
00209
00210 /* Exported functions ---------------------------------------------------------*/
00211
00212 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00213   * @{
00214   */
00215
00216 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00217   *  @brief    Initialization and Configuration functions
00218   *
00219 @verbatim
00220 ===============================================================================
00221             ##### Initialization and Configuration functions #####
00222  ===============================================================================
00223     [..]
00224     This subsection provides a set of functions allowing to :
00225       (+) Initialize the QuadSPI.
00226       (+) De-initialize the QuadSPI.
00227
00228 @endverbatim
00229   * @{
00230   */
00231
00232 /**
00233   * @brief Initializes the QSPI mode according to the specified parameters
00234   *        in the QSPI_InitTypeDef and creates the associated handle.
00235   * @param hqspi: qspi handle
00236   * @retval HAL status
00237   */
00238 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00239 {
00240   HAL_StatusTypeDef status = HAL_ERROR;
00241
00242   /* Check the QSPI handle allocation */
00243   if(hqspi == NULL)
00244   {
00245     return HAL_ERROR;
00246   }
00247
00248   /* Check the parameters */
00249   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
00250   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00251   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00252   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00253   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00254   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00255   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00256   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
00257
00258   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
00259   {
00260     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
00261   }
00262
00263   /* Process locked */
00264   __HAL_LOCK(hqspi);
00265
00266   if(hqspi->State == HAL_QSPI_STATE_RESET)
00267   {
00268     /* Allocate lock resource and initialize it */
00269     hqspi->Lock = HAL_UNLOCKED;
00270
00271     /* Init the low level hardware : GPIO, CLOCK */
00272     HAL_QSPI_MspInit(hqspi);
00273
00274     /* Configure the default timeout for the QSPI memory access */
00275     HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
00276   }
00277
00278   /* Configure QSPI FIFO Threshold */
00279   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
00280
00281   /* Wait till BUSY flag reset */
00282   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
00283
00284    if(status == HAL_OK)
00285   {
00286
00287     /* Configure QSPI Clock Prescaler and Sample Shift */
00288     MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
00289
00290     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00291     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00292                ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00293
00294     /* Enable the QSPI peripheral */
00295     __HAL_QSPI_ENABLE(hqspi);
00296
00297     /* Set QSPI error code to none */
00298     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00299
00300     /* Initialize the QSPI state */
00301     hqspi->State = HAL_QSPI_STATE_READY;
00302   }
00303
00304   /* Release Lock */
00305   __HAL_UNLOCK(hqspi);
00306
00307   /* Return function status */
00308   return status;
00309 }
00310
00311 /**
00312   * @brief DeInitializes the QSPI peripheral
00313   * @param hqspi: qspi handle
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00317 {
00318   /* Check the QSPI handle allocation */
00319   if(hqspi == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Process locked */
00325   __HAL_LOCK(hqspi);
00326
00327   /* Disable the QSPI Peripheral Clock */
00328   __HAL_QSPI_DISABLE(hqspi);
00329
00330   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00331   HAL_QSPI_MspDeInit(hqspi);
00332
00333   /* Set QSPI error code to none */
00334   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00335
00336   /* Initialize the QSPI state */
00337   hqspi->State = HAL_QSPI_STATE_RESET;
00338
00339   /* Release Lock */
00340   __HAL_UNLOCK(hqspi);
00341
00342   return HAL_OK;
00343 }
00344
00345 /**
00346   * @brief QSPI MSP Init
00347   * @param hqspi: QSPI handle
00348   * @retval None
00349   */
00350  __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00351 {
00352   /* Prevent unused argument(s) compilation warning */
00353   UNUSED(hqspi);
00354
00355   /* NOTE : This function should not be modified, when the callback is needed,
00356             the HAL_QSPI_MspInit can be implemented in the user file
00357    */
00358 }
00359
00360 /**
00361   * @brief QSPI MSP DeInit
00362   * @param hqspi: QSPI handle
00363   * @retval None
00364   */
00365  __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00366 {
00367   /* Prevent unused argument(s) compilation warning */
00368   UNUSED(hqspi);
00369
00370   /* NOTE : This function should not be modified, when the callback is needed,
00371             the HAL_QSPI_MspDeInit can be implemented in the user file
00372    */
00373 }
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
00380   *  @brief QSPI Transmit/Receive functions
00381   *
00382 @verbatim
00383  ===============================================================================
00384                       ##### IO operation functions #####
00385  ===============================================================================
00386        [..]
00387     This subsection provides a set of functions allowing to :
00388       (+) Handle the interrupts.
00389       (+) Handle the command sequence.
00390       (+) Transmit data in blocking, interrupt or DMA mode.
00391       (+) Receive data in blocking, interrupt or DMA mode.
00392       (+) Manage the auto-polling functional mode.
00393       (+) Manage the memory-mapped functional mode.
00394
00395 @endverbatim
00396   * @{
00397   */
00398
00399 /**
00400   * @brief This function handles QSPI interrupt request.
00401   * @param hqspi: QSPI handle
00402   * @retval None.
00403   */
00404 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00405 {
00406   __IO uint32_t *data_reg;
00407   uint32_t flag = 0, itsource = 0;
00408
00409   /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
00410   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
00411   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
00412
00413   if((flag != RESET) && (itsource != RESET))
00414   {
00415     data_reg = &hqspi->Instance->DR;
00416
00417     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00418     {
00419       /* Transmission process */
00420       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
00421       {
00422         if (hqspi->TxXferCount > 0)
00423         {
00424           /* Fill the FIFO until it is full */
00425           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00426           hqspi->TxXferCount--;
00427         }
00428         else
00429         {
00430           /* No more data available for the transfer */
00431           break;
00432         }
00433       }
00434     }
00435     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00436     {
00437       /* Receiving Process */
00438       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
00439       {
00440         if (hqspi->RxXferCount > 0)
00441         {
00442           /* Read the FIFO until it is empty */
00443           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00444           hqspi->RxXferCount--;
00445         }
00446         else
00447         {
00448           /* All data have been received for the transfer */
00449           break;
00450         }
00451       }
00452     }
00453
00454     /* FIFO Threshold callback */
00455     HAL_QSPI_FifoThresholdCallback(hqspi);
00456   }
00457
00458   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00459   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
00460   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
00461
00462   if((flag != RESET) && (itsource != RESET))
00463   {
00464     /* Clear interrupt */
00465     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00466
00467     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00468     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00469
00470     /* Transfer complete callback */
00471     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00472     {
00473       /* Clear Busy bit */
00474       HAL_QSPI_Abort(hqspi);
00475
00476       /* TX Complete callback */
00477       HAL_QSPI_TxCpltCallback(hqspi);
00478     }
00479     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00480     {
00481       data_reg = &hqspi->Instance->DR;
00482       while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
00483       {
00484         if (hqspi->RxXferCount > 0)
00485         {
00486           /* Read the last data received in the FIFO until it is empty */
00487           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00488           hqspi->RxXferCount--;
00489         }
00490         else
00491         {
00492           /* All data have been received for the transfer */
00493           break;
00494         }
00495       }
00496
00497       /* Workaround - Extra data written in the FIFO at the end of a read transfer */
00498       HAL_QSPI_Abort(hqspi);
00499
00500       /* RX Complete callback */
00501       HAL_QSPI_RxCpltCallback(hqspi);
00502     }
00503     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00504     {
00505       /* Command Complete callback */
00506       HAL_QSPI_CmdCpltCallback(hqspi);
00507     }
00508
00509     /* Change state of QSPI */
00510     hqspi->State = HAL_QSPI_STATE_READY;
00511   }
00512
00513   /* QSPI Status Match interrupt occurred ------------------------------------*/
00514   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
00515   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
00516
00517   if((flag != RESET) && (itsource != RESET))
00518   {
00519     /* Clear interrupt */
00520     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
00521
00522     /* Check if the automatic poll mode stop is activated */
00523     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
00524     {
00525       /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
00526       __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
00527
00528       /* Change state of QSPI */
00529       hqspi->State = HAL_QSPI_STATE_READY;
00530     }
00531
00532     /* Status match callback */
00533     HAL_QSPI_StatusMatchCallback(hqspi);
00534   }
00535
00536   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00537   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
00538   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
00539
00540   if((flag != RESET) && (itsource != RESET))
00541   {
00542     /* Clear interrupt */
00543     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
00544
00545     /* Disable all the QSPI Interrupts */
00546     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00547
00548     /* Set error code */
00549     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00550
00551     /* Change state of QSPI */
00552     hqspi->State = HAL_QSPI_STATE_ERROR;
00553
00554     /* Error callback */
00555     HAL_QSPI_ErrorCallback(hqspi);
00556   }
00557
00558   /* QSPI Time out interrupt occurred -----------------------------------------*/
00559   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
00560   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
00561
00562   if((flag != RESET) && (itsource != RESET))
00563   {
00564     /* Clear interrupt */
00565     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
00566
00567     /* Time out callback */
00568     HAL_QSPI_TimeOutCallback(hqspi);
00569   }
00570 }
00571
00572 /**
00573   * @brief Sets the command configuration.
00574   * @param hqspi: QSPI handle
00575   * @param cmd : structure that contains the command configuration information
00576   * @param Timeout : Time out duration
00577   * @note   This function is used only in Indirect Read or Write Modes
00578   * @retval HAL status
00579   */
00580 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00581 {
00582   HAL_StatusTypeDef status = HAL_ERROR;
00583
00584   /* Check the parameters */
00585   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00586   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00587   {
00588     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00589   }
00590
00591   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00592   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00593   {
00594     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00595   }
00596
00597   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00598   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00599   {
00600     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00601   }
00602
00603   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00604   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00605
00606   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00607   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00608   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00609
00610   /* Process locked */
00611   __HAL_LOCK(hqspi);
00612
00613  if(hqspi->State == HAL_QSPI_STATE_READY)
00614   {
00615     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00616
00617     /* Update QSPI state */
00618     hqspi->State = HAL_QSPI_STATE_BUSY;
00619
00620     /* Wait till BUSY flag reset */
00621     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
00622
00623     if (status == HAL_OK)
00624     {
00625       /* Call the configuration function */
00626       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00627
00628       if (cmd->DataMode == QSPI_DATA_NONE)
00629       {
00630         /* When there is no data phase, the transfer start as soon as the configuration is done
00631         so wait until TC flag is set to go back in idle state */
00632         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
00633         {
00634           status = HAL_TIMEOUT;
00635         }
00636         else
00637         {
00638           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00639
00640           /* Update QSPI state */
00641           hqspi->State = HAL_QSPI_STATE_READY;
00642         }
00643
00644       }
00645       else
00646       {
00647         /* Update QSPI state */
00648         hqspi->State = HAL_QSPI_STATE_READY;
00649       }
00650     }
00651   }
00652   else
00653   {
00654     status = HAL_BUSY;
00655   }
00656
00657   /* Process unlocked */
00658   __HAL_UNLOCK(hqspi);
00659
00660   /* Return function status */
00661   return status;
00662 }
00663
00664 /**
00665   * @brief Sets the command configuration in interrupt mode.
00666   * @param hqspi: QSPI handle
00667   * @param cmd : structure that contains the command configuration information
00668   * @note   This function is used only in Indirect Read or Write Modes
00669   * @retval HAL status
00670   */
00671 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00672 {
00673   HAL_StatusTypeDef status = HAL_ERROR;
00674
00675   /* Check the parameters */
00676   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00677   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00678   {
00679     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00680   }
00681
00682   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00683   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00684   {
00685     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00686   }
00687
00688   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00689   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00690   {
00691     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00692   }
00693
00694   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00695   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00696
00697   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00698   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00699   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00700
00701   /* Process locked */
00702   __HAL_LOCK(hqspi);
00703
00704    if(hqspi->State == HAL_QSPI_STATE_READY)
00705   {
00706     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00707
00708     /* Update QSPI state */
00709     hqspi->State = HAL_QSPI_STATE_BUSY;
00710
00711     /* Wait till BUSY flag reset */
00712     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
00713
00714     if (status == HAL_OK)
00715     {
00716       if (cmd->DataMode == QSPI_DATA_NONE)
00717       {
00718         /* When there is no data phase, the transfer start as soon as the configuration is done
00719         so activate TC and TE interrupts */
00720         /* Enable the QSPI Transfer Error Interrupt */
00721         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00722       }
00723
00724       /* Call the configuration function */
00725       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00726
00727       if (cmd->DataMode != QSPI_DATA_NONE)
00728       {
00729         /* Update QSPI state */
00730         hqspi->State = HAL_QSPI_STATE_READY;
00731       }
00732     }
00733   }
00734   else
00735   {
00736     status = HAL_BUSY;
00737   }
00738
00739   /* Process unlocked */
00740   __HAL_UNLOCK(hqspi);
00741
00742   /* Return function status */
00743   return status;
00744 }
00745
00746 /**
00747   * @brief Transmit an amount of data in blocking mode.
00748   * @param hqspi: QSPI handle
00749   * @param pData: pointer to data buffer
00750   * @param Timeout : Time out duration
00751   * @note   This function is used only in Indirect Write Mode
00752   * @retval HAL status
00753   */
00754 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00755 {
00756   HAL_StatusTypeDef status = HAL_OK;
00757   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00758
00759   /* Process locked */
00760   __HAL_LOCK(hqspi);
00761
00762   if(hqspi->State == HAL_QSPI_STATE_READY)
00763   {
00764     if(pData != NULL )
00765     {
00766       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00767
00768       /* Update state */
00769       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00770
00771       /* Configure counters and size of the handle */
00772       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00773       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00774       hqspi->pTxBuffPtr = pData;
00775
00776       /* Configure QSPI: CCR register with functional as indirect write */
00777       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00778
00779       while(hqspi->TxXferCount > 0)
00780       {
00781         /* Wait until FT flag is set to send data */
00782         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
00783         {
00784           status = HAL_TIMEOUT;
00785           break;
00786         }
00787
00788         *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00789         hqspi->TxXferCount--;
00790       }
00791
00792       if (status == HAL_OK)
00793       {
00794         /* Wait until TC flag is set to go back in idle state */
00795         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
00796         {
00797           status = HAL_TIMEOUT;
00798         }
00799         else
00800         {
00801           /* Clear Transfer Complete bit */
00802           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00803
00804           /* Clear Busy bit */
00805           status = HAL_QSPI_Abort(hqspi);
00806         }
00807       }
00808
00809       /* Update QSPI state */
00810       hqspi->State = HAL_QSPI_STATE_READY;
00811     }
00812     else
00813     {
00814       status = HAL_ERROR;
00815     }
00816   }
00817   else
00818   {
00819     status = HAL_BUSY;
00820   }
00821
00822   /* Process unlocked */
00823   __HAL_UNLOCK(hqspi);
00824
00825   return status;
00826 }
00827
00828
00829 /**
00830   * @brief Receive an amount of data in blocking mode
00831   * @param hqspi: QSPI handle
00832   * @param pData: pointer to data buffer
00833   * @param Timeout : Time out duration
00834   * @note   This function is used only in Indirect Read Mode
00835   * @retval HAL status
00836   */
00837 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00838 {
00839   HAL_StatusTypeDef status = HAL_OK;
00840   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
00841   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00842
00843   /* Process locked */
00844   __HAL_LOCK(hqspi);
00845
00846   if(hqspi->State == HAL_QSPI_STATE_READY)
00847   {
00848     if(pData != NULL )
00849     {
00850       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00851
00852       /* Update state */
00853       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
00854
00855       /* Configure counters and size of the handle */
00856       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00857       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00858       hqspi->pRxBuffPtr = pData;
00859
00860       /* Configure QSPI: CCR register with functional as indirect read */
00861       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
00862
00863       /* Start the transfer by re-writing the address in AR register */
00864       WRITE_REG(hqspi->Instance->AR, addr_reg);
00865
00866       while(hqspi->RxXferCount > 0)
00867       {
00868         /* Wait until FT or TC flag is set to read received data */
00869         if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
00870         {
00871           status = HAL_TIMEOUT;
00872           break;
00873         }
00874
00875         *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00876         hqspi->RxXferCount--;
00877       }
00878
00879       if (status == HAL_OK)
00880       {
00881         /* Wait until TC flag is set to go back in idle state */
00882         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
00883         {
00884           status = HAL_TIMEOUT;
00885         }
00886         else
00887         {
00888           /* Clear Transfer Complete bit */
00889           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00890
00891           /* Workaround - Extra data written in the FIFO at the end of a read transfer */
00892           status = HAL_QSPI_Abort(hqspi);
00893         }
00894       }
00895
00896       /* Update QSPI state */
00897       hqspi->State = HAL_QSPI_STATE_READY;
00898     }
00899     else
00900     {
00901       status = HAL_ERROR;
00902     }
00903   }
00904   else
00905   {
00906     status = HAL_BUSY;
00907   }
00908
00909   /* Process unlocked */
00910   __HAL_UNLOCK(hqspi);
00911
00912   return status;
00913 }
00914
00915 /**
00916   * @brief  Send an amount of data in interrupt mode
00917   * @param  hqspi: QSPI handle
00918   * @param  pData: pointer to data buffer
00919   * @note   This function is used only in Indirect Write Mode
00920   * @retval HAL status
00921   */
00922 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
00923 {
00924   HAL_StatusTypeDef status = HAL_OK;
00925
00926   /* Process locked */
00927   __HAL_LOCK(hqspi);
00928
00929   if(hqspi->State == HAL_QSPI_STATE_READY)
00930   {
00931     if(pData != NULL )
00932     {
00933       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00934
00935       /* Update state */
00936       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00937
00938       /* Configure counters and size of the handle */
00939       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00940       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00941       hqspi->pTxBuffPtr = pData;
00942
00943       /* Configure QSPI: CCR register with functional as indirect write */
00944       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00945
00946       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
00947       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
00948
00949     }
00950     else
00951     {
00952       status = HAL_ERROR;
00953     }
00954   }
00955   else
00956   {
00957     status = HAL_BUSY;
00958   }
00959
00960   /* Process unlocked */
00961   __HAL_UNLOCK(hqspi);
00962
00963   return status;
00964 }
00965
00966 /**
00967   * @brief  Receive an amount of data in no-blocking mode with Interrupt
00968   * @param  hqspi: QSPI handle
00969   * @param  pData: pointer to data buffer
00970   * @note   This function is used only in Indirect Read Mode
00971   * @retval HAL status
00972   */
00973 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
00974 {
00975   HAL_StatusTypeDef status = HAL_OK;
00976   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
00977
00978   /* Process locked */
00979   __HAL_LOCK(hqspi);
00980
00981   if(hqspi->State == HAL_QSPI_STATE_READY)
00982   {
00983     if(pData != NULL )
00984     {
00985       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00986
00987       /* Update state */
00988       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
00989
00990       /* Configure counters and size of the handle */
00991       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00992       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00993       hqspi->pRxBuffPtr = pData;
00994
00995       /* Configure QSPI: CCR register with functional as indirect read */
00996       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
00997
00998       /* Start the transfer by re-writing the address in AR register */
00999       WRITE_REG(hqspi->Instance->AR, addr_reg);
01000
01001       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01002       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01003     }
01004     else
01005     {
01006       status = HAL_ERROR;
01007     }
01008   }
01009   else
01010   {
01011     status = HAL_BUSY;
01012   }
01013
01014   /* Process unlocked */
01015   __HAL_UNLOCK(hqspi);
01016
01017   return status;
01018 }
01019
01020 /**
01021   * @brief  Sends an amount of data in non blocking mode with DMA.
01022   * @param  hqspi: QSPI handle
01023   * @param  pData: pointer to data buffer
01024   * @note   This function is used only in Indirect Write Mode
01025   * @retval HAL status
01026   */
01027 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01028 {
01029   HAL_StatusTypeDef status = HAL_OK;
01030   uint32_t *tmp;
01031
01032   /* Process locked */
01033   __HAL_LOCK(hqspi);
01034
01035   if(hqspi->State == HAL_QSPI_STATE_READY)
01036   {
01037     if(pData != NULL )
01038     {
01039       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01040
01041       /* Update state */
01042       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01043
01044       /* Configure counters and size of the handle */
01045       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01046       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01047       hqspi->pTxBuffPtr = pData;
01048
01049       /* Configure QSPI: CCR register with functional mode as indirect write */
01050       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01051
01052       /* Set the QSPI DMA transfer complete callback */
01053       hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
01054
01055       /* Set the QSPI DMA Half transfer complete callback */
01056       hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
01057
01058       /* Set the DMA error callback */
01059       hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01060
01061       /* Configure the direction of the DMA */
01062       hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
01063       MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
01064
01065       /* Enable the QSPI transmit DMA Channel */
01066       tmp = (uint32_t*)&pData;
01067       HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
01068
01069       /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01070       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01071     }
01072     else
01073     {
01074       status = HAL_OK;
01075     }
01076   }
01077   else
01078   {
01079     status = HAL_BUSY;
01080   }
01081
01082   /* Process unlocked */
01083   __HAL_UNLOCK(hqspi);
01084
01085   return status;
01086 }
01087
01088 /**
01089   * @brief  Receives an amount of data in non blocking mode with DMA.
01090   * @param  hqspi: QSPI handle
01091   * @param  pData: pointer to data buffer.
01092   * @note   This function is used only in Indirect Read Mode
01093   * @retval HAL status
01094   */
01095 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01096 {
01097   HAL_StatusTypeDef status = HAL_OK;
01098   uint32_t *tmp;
01099   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01100
01101   /* Process locked */
01102   __HAL_LOCK(hqspi);
01103
01104   if(hqspi->State == HAL_QSPI_STATE_READY)
01105   {
01106     if(pData != NULL )
01107     {
01108       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01109
01110       /* Update state */
01111       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01112
01113       /* Configure counters and size of the handle */
01114       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01115       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01116       hqspi->pRxBuffPtr = pData;
01117
01118       /* Set the QSPI DMA transfer complete callback */
01119       hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
01120
01121       /* Set the QSPI DMA Half transfer complete callback */
01122       hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
01123
01124       /* Set the DMA error callback */
01125       hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01126
01127       /* Configure the direction of the DMA */
01128       hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
01129       MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
01130
01131       /* Enable the DMA Channel */
01132       tmp = (uint32_t*)&pData;
01133       HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
01134
01135       /* Configure QSPI: CCR register with functional as indirect read */
01136       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01137
01138       /* Start the transfer by re-writing the address in AR register */
01139       WRITE_REG(hqspi->Instance->AR, addr_reg);
01140
01141       /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01142       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01143     }
01144     else
01145     {
01146       status = HAL_ERROR;
01147     }
01148   }
01149   else
01150   {
01151     status = HAL_BUSY;
01152   }
01153
01154   /* Process unlocked */
01155   __HAL_UNLOCK(hqspi);
01156
01157   return status;
01158 }
01159
01160 /**
01161   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01162   * @param  hqspi: QSPI handle
01163   * @param  cmd: structure that contains the command configuration information.
01164   * @param  cfg: structure that contains the polling configuration information.
01165   * @param  Timeout : Time out duration
01166   * @note   This function is used only in Automatic Polling Mode
01167   * @retval HAL status
01168   */
01169 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01170 {
01171   HAL_StatusTypeDef status = HAL_ERROR;
01172
01173   /* Check the parameters */
01174   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01175   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01176   {
01177     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01178   }
01179
01180   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01181   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01182   {
01183     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01184   }
01185
01186   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01187   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01188   {
01189     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01190   }
01191
01192   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01193   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01194
01195   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01196   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01197   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01198
01199   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01200   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01201   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01202
01203   /* Process locked */
01204   __HAL_LOCK(hqspi);
01205
01206   if(hqspi->State == HAL_QSPI_STATE_READY)
01207   {
01208
01209     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01210
01211     /* Update state */
01212     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01213
01214     /* Wait till BUSY flag reset */
01215     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
01216
01217     if (status == HAL_OK)
01218     {
01219       /* Configure QSPI: PSMAR register with the status match value */
01220       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01221
01222       /* Configure QSPI: PSMKR register with the status mask value */
01223       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01224
01225       /* Configure QSPI: PIR register with the interval value */
01226       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01227
01228       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01229       (otherwise there will be an infinite loop in blocking mode) */
01230       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01231                  (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01232
01233       /* Call the configuration function */
01234       cmd->NbData = cfg->StatusBytesSize;
01235       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01236
01237       /* Wait until SM flag is set to go back in idle state */
01238       if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
01239       {
01240         status = HAL_TIMEOUT;
01241       }
01242       else
01243       {
01244         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01245
01246         /* Update state */
01247         hqspi->State = HAL_QSPI_STATE_READY;
01248       }
01249     }
01250   }
01251   else
01252   {
01253     status = HAL_BUSY;
01254   }
01255   /* Process unlocked */
01256   __HAL_UNLOCK(hqspi);
01257
01258   /* Return function status */
01259   return status;
01260 }
01261
01262 /**
01263 * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01264 * @param  hqspi: QSPI handle
01265 * @param  cmd: structure that contains the command configuration information.
01266 * @param  cfg: structure that contains the polling configuration information.
01267 * @note   This function is used only in Automatic Polling Mode
01268 * @retval HAL status
01269 */
01270 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01271 {
01272   HAL_StatusTypeDef status = HAL_ERROR;
01273
01274   /* Check the parameters */
01275   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01276   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01277   {
01278     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01279   }
01280
01281   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01282   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01283   {
01284     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01285   }
01286
01287   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01288   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01289   {
01290     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01291   }
01292
01293   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01294   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01295
01296   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01297   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01298   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01299
01300   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01301   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01302   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01303   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01304
01305   /* Process locked */
01306   __HAL_LOCK(hqspi);
01307
01308   if(hqspi->State == HAL_QSPI_STATE_READY)
01309   {
01310     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01311
01312     /* Update state */
01313     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01314
01315     /* Wait till BUSY flag reset */
01316     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
01317
01318     if (status == HAL_OK)
01319     {
01320       /* Configure QSPI: PSMAR register with the status match value */
01321       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01322
01323       /* Configure QSPI: PSMKR register with the status mask value */
01324       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01325
01326       /* Configure QSPI: PIR register with the interval value */
01327       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01328
01329       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01330       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01331                  (cfg->MatchMode | cfg->AutomaticStop));
01332
01333       /* Clear interrupt */
01334       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01335
01336       /* Enable the QSPI Transfer Error and status match Interrupt */
01337       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01338
01339       /* Call the configuration function */
01340       cmd->NbData = cfg->StatusBytesSize;
01341       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01342     }
01343   }
01344   else
01345   {
01346     status = HAL_BUSY;
01347   }
01348
01349   /* Process unlocked */
01350   __HAL_UNLOCK(hqspi);
01351
01352   /* Return function status */
01353   return status;
01354 }
01355
01356 /**
01357   * @brief  Configure the Memory Mapped mode.
01358   * @param  hqspi: QSPI handle
01359   * @param  cmd: structure that contains the command configuration information.
01360   * @param  cfg: structure that contains the memory mapped configuration information.
01361   * @note   This function is used only in Memory mapped Mode
01362   * @retval HAL status
01363   */
01364 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01365 {
01366   HAL_StatusTypeDef status = HAL_ERROR;
01367
01368   /* Check the parameters */
01369   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01370   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01371   {
01372   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01373   }
01374
01375   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01376   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01377   {
01378     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01379   }
01380
01381   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01382   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01383   {
01384     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01385   }
01386
01387   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01388   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01389
01390   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01391   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01392   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01393
01394   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01395
01396   /* Process locked */
01397   __HAL_LOCK(hqspi);
01398
01399   if(hqspi->State == HAL_QSPI_STATE_READY)
01400   {
01401     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01402
01403     /* Update state */
01404     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01405
01406     /* Wait till BUSY flag reset */
01407     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
01408
01409   if (status == HAL_OK)
01410   {
01411     /* Configure QSPI: CR register with time out counter enable */
01412     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01413
01414     if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01415     {
01416       assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01417
01418       /* Configure QSPI: LPTR register with the low-power time out value */
01419       WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01420
01421       /* Enable the QSPI TimeOut Interrupt */
01422       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01423     }
01424
01425     /* Call the configuration function */
01426     QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01427
01428     }
01429   }
01430   else
01431   {
01432     status = HAL_BUSY;
01433
01434   }
01435
01436   /* Process unlocked */
01437   __HAL_UNLOCK(hqspi);
01438
01439   /* Return function status */
01440   return status;
01441 }
01442
01443 /**
01444   * @brief  Transfer Error callbacks
01445   * @param  hqspi: QSPI handle
01446   * @retval None
01447   */
01448 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01449 {
01450   /* Prevent unused argument(s) compilation warning */
01451   UNUSED(hqspi);
01452
01453   /* NOTE : This function Should not be modified, when the callback is needed,
01454             the HAL_QSPI_ErrorCallback could be implemented in the user file
01455    */
01456 }
01457
01458 /**
01459   * @brief  Command completed callbacks.
01460   * @param  hqspi: QSPI handle
01461   * @retval None
01462   */
01463 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01464 {
01465   /* Prevent unused argument(s) compilation warning */
01466   UNUSED(hqspi);
01467
01468   /* NOTE: This function Should not be modified, when the callback is needed,
01469            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01470    */
01471 }
01472
01473 /**
01474   * @brief  Rx Transfer completed callbacks.
01475   * @param  hqspi: QSPI handle
01476   * @retval None
01477   */
01478 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01479 {
01480   /* Prevent unused argument(s) compilation warning */
01481   UNUSED(hqspi);
01482
01483   /* NOTE: This function Should not be modified, when the callback is needed,
01484            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01485    */
01486 }
01487
01488 /**
01489   * @brief  Tx Transfer completed callbacks.
01490   * @param  hqspi: QSPI handle
01491   * @retval None
01492   */
01493  __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01494 {
01495   /* Prevent unused argument(s) compilation warning */
01496   UNUSED(hqspi);
01497
01498   /* NOTE: This function Should not be modified, when the callback is needed,
01499            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01500    */
01501 }
01502
01503 /**
01504   * @brief  Rx Half Transfer completed callbacks.
01505   * @param  hqspi: QSPI handle
01506   * @retval None
01507   */
01508 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01509 {
01510   /* Prevent unused argument(s) compilation warning */
01511   UNUSED(hqspi);
01512
01513   /* NOTE: This function Should not be modified, when the callback is needed,
01514            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
01515    */
01516 }
01517
01518 /**
01519   * @brief  Tx Half Transfer completed callbacks.
01520   * @param  hqspi: QSPI handle
01521   * @retval None
01522   */
01523  __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01524 {
01525   /* Prevent unused argument(s) compilation warning */
01526   UNUSED(hqspi);
01527
01528   /* NOTE: This function Should not be modified, when the callback is needed,
01529            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
01530    */
01531 }
01532
01533 /**
01534   * @brief  FIFO Threshold callbacks
01535   * @param  hqspi: QSPI handle
01536   * @retval None
01537   */
01538 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01539 {
01540   /* Prevent unused argument(s) compilation warning */
01541   UNUSED(hqspi);
01542
01543   /* NOTE : This function Should not be modified, when the callback is needed,
01544             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01545    */
01546 }
01547
01548 /**
01549   * @brief  Status Match callbacks
01550   * @param  hqspi: QSPI handle
01551   * @retval None
01552   */
01553 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01554 {
01555   /* Prevent unused argument(s) compilation warning */
01556   UNUSED(hqspi);
01557
01558   /* NOTE : This function Should not be modified, when the callback is needed,
01559             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01560    */
01561 }
01562
01563 /**
01564   * @brief  Timeout callbacks
01565   * @param  hqspi: QSPI handle
01566   * @retval None
01567   */
01568 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01569 {
01570   /* Prevent unused argument(s) compilation warning */
01571   UNUSED(hqspi);
01572
01573   /* NOTE : This function Should not be modified, when the callback is needed,
01574             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01575    */
01576 }
01577
01578 /**
01579   * @}
01580   */
01581
01582 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
01583   *  @brief   QSPI control and State functions
01584   *
01585 @verbatim
01586  ===============================================================================
01587                   ##### Peripheral Control and State functions #####
01588  ===============================================================================
01589     [..]
01590     This subsection provides a set of functions allowing to :
01591       (+) Check in run-time the state of the driver.
01592       (+) Check the error code set during last operation.
01593       (+) Abort any operation.
01594 .....
01595 @endverbatim
01596   * @{
01597   */
01598
01599 /**
01600   * @brief  Return the QSPI state.
01601   * @param  hqspi: QSPI handle
01602   * @retval HAL state
01603   */
01604 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
01605 {
01606   return hqspi->State;
01607 }
01608
01609 /**
01610 * @brief  Return the QSPI error code
01611 * @param  hqspi: QSPI handle
01612 * @retval QSPI Error Code
01613 */
01614 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
01615 {
01616   return hqspi->ErrorCode;
01617 }
01618
01619 /**
01620 * @brief  Abort the current transmission
01621 * @param  hqspi: QSPI handle
01622 * @retval HAL status
01623 */
01624 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
01625 {
01626   HAL_StatusTypeDef status = HAL_ERROR;
01627
01628   /* Configure QSPI: CR register with Abort request */
01629   SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
01630
01631   /* Wait until TC flag is set to go back in idle state */
01632   if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
01633   {
01634     status = HAL_TIMEOUT;
01635   }
01636   else
01637   {
01638     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01639
01640     /* Wait until BUSY flag is reset */
01641     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
01642
01643     /* Update state */
01644     hqspi->State = HAL_QSPI_STATE_READY;
01645   }
01646
01647   return status;
01648 }
01649
01650 /** @brief Set QSPI timeout
01651   * @param  hqspi: QSPI handle.
01652   * @param  Timeout: Timeout for the QSPI memory access.
01653   * @retval None
01654   */
01655 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
01656 {
01657   hqspi->Timeout = Timeout;
01658 }
01659
01660 /**
01661 * @}
01662 */
01663
01664 /* Private functions ---------------------------------------------------------*/
01665
01666 /**
01667   * @brief  DMA QSPI receive process complete callback.
01668   * @param  hdma: DMA handle
01669   * @retval None
01670   */
01671 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
01672 {
01673   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01674   hqspi->RxXferCount = 0;
01675
01676   /* Wait for QSPI TC Flag */
01677   if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
01678   {
01679     /* Time out Occurred */
01680     HAL_QSPI_ErrorCallback(hqspi);
01681   }
01682   else
01683   {
01684     /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01685     CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01686
01687     /* Disable the DMA channel */
01688     HAL_DMA_Abort(hdma);
01689
01690     /* Clear Transfer Complete bit */
01691     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01692
01693     /* Workaround - Extra data written in the FIFO at the end of a read transfer */
01694     HAL_QSPI_Abort(hqspi);
01695
01696     /* Update state */
01697     hqspi->State = HAL_QSPI_STATE_READY;
01698
01699     HAL_QSPI_RxCpltCallback(hqspi);
01700   }
01701 }
01702
01703 /**
01704   * @brief  DMA QSPI transmit process complete callback.
01705   * @param  hdma: DMA handle
01706   * @retval None
01707   */
01708 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
01709 {
01710   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01711   hqspi->TxXferCount = 0;
01712
01713   /* Wait for QSPI TC Flag */
01714   if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
01715   {
01716     /* Time out Occurred */
01717     HAL_QSPI_ErrorCallback(hqspi);
01718   }
01719   else
01720   {
01721     /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01722     CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01723
01724     /* Disable the DMA channel */
01725     HAL_DMA_Abort(hdma);
01726
01727     /* Clear Transfer Complete bit */
01728     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01729
01730     /* Clear Busy bit */
01731     HAL_QSPI_Abort(hqspi);
01732
01733     /* Update state */
01734     hqspi->State = HAL_QSPI_STATE_READY;
01735
01736     HAL_QSPI_TxCpltCallback(hqspi);
01737   }
01738 }
01739
01740 /**
01741   * @brief  DMA QSPI receive process half complete callback
01742   * @param  hdma : DMA handle
01743   * @retval None
01744   */
01745 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01746 {
01747   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01748
01749   HAL_QSPI_RxHalfCpltCallback(hqspi);
01750 }
01751
01752 /**
01753   * @brief  DMA QSPI transmit process half complete callback
01754   * @param  hdma : DMA handle
01755   * @retval None
01756   */
01757 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01758 {
01759   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01760
01761   HAL_QSPI_TxHalfCpltCallback(hqspi);
01762 }
01763
01764 /**
01765   * @brief  DMA QSPI communication error callback.
01766   * @param  hdma: DMA handle
01767   * @retval None
01768   */
01769 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
01770 {
01771   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01772
01773   hqspi->RxXferCount = 0;
01774   hqspi->TxXferCount = 0;
01775   hqspi->State       = HAL_QSPI_STATE_ERROR;
01776   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
01777
01778   HAL_QSPI_ErrorCallback(hqspi);
01779 }
01780
01781 /**
01782   * @brief  This function wait a flag state until time out.
01783   * @param  hqspi: QSPI handle
01784   * @param  Flag: Flag checked
01785   * @param  State: Value of the flag expected
01786   * @param  Timeout: Duration of the time out
01787   * @retval HAL status
01788   */
01789 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
01790                                                         FlagStatus State, uint32_t Timeout)
01791 {
01792   uint32_t tickstart = HAL_GetTick();
01793
01794   /* Wait until flag is in expected state */
01795   while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
01796   {
01797     /* Check for the Timeout */
01798     if (Timeout != HAL_MAX_DELAY)
01799     {
01800       if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
01801       {
01802         hqspi->State     = HAL_QSPI_STATE_ERROR;
01803         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
01804
01805         return HAL_TIMEOUT;
01806       }
01807     }
01808   }
01809   return HAL_OK;
01810 }
01811
01812 /**
01813   * @brief  This function configures the communication registers
01814   * @param  hqspi: QSPI handle
01815   * @param  cmd: structure that contains the command configuration information
01816   * @param  FunctionalMode: functional mode to configured
01817   *           This parameter can be one of the following values:
01818   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
01819   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
01820   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
01821   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
01822   * @retval None
01823   */
01824 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
01825 {
01826   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
01827
01828   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
01829   {
01830     /* Configure QSPI: DLR register with the number of data to read or write */
01831     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
01832   }
01833
01834   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01835   {
01836     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01837     {
01838       /* Configure QSPI: ABR register with alternate bytes value */
01839       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
01840
01841       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01842       {
01843         /*---- Command with instruction, address and alternate bytes ----*/
01844         /* Configure QSPI: CCR register with all communications parameters */
01845         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01846                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
01847                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
01848                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
01849
01850         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01851         {
01852           /* Configure QSPI: AR register with address value */
01853           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01854         }
01855       }
01856       else
01857       {
01858         /*---- Command with instruction and alternate bytes ----*/
01859         /* Configure QSPI: CCR register with all communications parameters */
01860         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01861                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
01862                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
01863                                          cmd->Instruction | FunctionalMode));
01864       }
01865     }
01866     else
01867     {
01868       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01869       {
01870         /*---- Command with instruction and address ----*/
01871         /* Configure QSPI: CCR register with all communications parameters */
01872         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01873                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
01874                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
01875                                          cmd->Instruction | FunctionalMode));
01876
01877         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01878         {
01879           /* Configure QSPI: AR register with address value */
01880           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01881         }
01882       }
01883       else
01884       {
01885         /*---- Command with only instruction ----*/
01886         /* Configure QSPI: CCR register with all communications parameters */
01887         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01888                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
01889                                          cmd->AddressMode | cmd->InstructionMode | cmd->Instruction  |
01890                                          FunctionalMode));
01891       }
01892     }
01893   }
01894   else
01895   {
01896     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01897     {
01898       /* Configure QSPI: ABR register with alternate bytes value */
01899       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
01900
01901       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01902       {
01903         /*---- Command with address and alternate bytes ----*/
01904         /* Configure QSPI: CCR register with all communications parameters */
01905         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01906                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
01907                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
01908                                          cmd->InstructionMode | FunctionalMode));
01909
01910         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01911         {
01912           /* Configure QSPI: AR register with address value */
01913           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01914         }
01915       }
01916       else
01917       {
01918         /*---- Command with only alternate bytes ----*/
01919         /* Configure QSPI: CCR register with all communications parameters */
01920         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01921                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
01922                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
01923                                          FunctionalMode));
01924       }
01925     }
01926     else
01927     {
01928       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01929       {
01930         /*---- Command with only address ----*/
01931         /* Configure QSPI: CCR register with all communications parameters */
01932         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01933                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
01934                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
01935                                          FunctionalMode));
01936
01937         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01938         {
01939           /* Configure QSPI: AR register with address value */
01940           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01941         }
01942       }
01943       else
01944       {
01945         /*---- Command with only data phase ----*/
01946         if (cmd->DataMode != QSPI_DATA_NONE)
01947         {
01948           /* Configure QSPI: CCR register with all communications parameters */
01949           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01950                                            cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
01951                                            cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
01952         }
01953       }
01954     }
01955   }
01956 }
01957 /**
01958   * @}
01959   */
01960
01961 #endif /* HAL_QSPI_MODULE_ENABLED */
01962 /**
01963   * @}
01964   */
01965
01966 /**
01967   * @}
01968   */
01969
01970 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_qspi.h Source File

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stm32f7xx_hal_qspi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of QSPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_QSPI_H
00040 #define __STM32F7xx_HAL_QSPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup QSPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  QSPI Init structure definition
00064   */
00065
00066 typedef struct
00067 {
00068   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00069                                   This parameter can be a number between 0 and 255 */
00070
00071   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00072                                   This parameter can be a value between 1 and 32 */
00073
00074   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00075                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00076                                   This parameter can be a value of @ref QSPI_SampleShifting */
00077
00078   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00079                                   required to address the flash memory. The flash capacity can be up to 4GB
00080                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00081                                   memory-mapped mode is limited to 256MB
00082                                   This parameter can be a number between 0 and 31 */
00083
00084   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00085                                   of clock cycles which the chip select must remain high between commands.
00086                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00087
00088   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00089                                   This parameter can be a value of @ref QSPI_ClockMode */
00090
00091   uint32_t FlashID;            /* Specifies the Flash which will be used,
00092                                   This parameter can be a value of @ref QSPI_Flash_Select */
00093
00094   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00095                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */
00096 }QSPI_InitTypeDef;
00097
00098 /**
00099   * @brief HAL QSPI State structures definition
00100   */
00101 typedef enum
00102 {
00103   HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
00104   HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
00105   HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */
00106   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */
00107   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
00108   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
00109   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
00110   HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
00111 }HAL_QSPI_StateTypeDef;
00112
00113 /**
00114   * @brief  QSPI Handle Structure definition
00115   */
00116 typedef struct
00117 {
00118   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00119   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00120   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00121   __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
00122   __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00123   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00124   __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
00125   __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00126   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
00127   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00128   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00129   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00130   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00131 }QSPI_HandleTypeDef;
00132
00133 /**
00134   * @brief  QSPI Command structure definition
00135   */
00136 typedef struct
00137 {
00138   uint32_t Instruction;        /* Specifies the Instruction to be sent
00139                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00140   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00141                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00142   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00143                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00144   uint32_t AddressSize;        /* Specifies the Address Size
00145                                   This parameter can be a value of @ref QSPI_AddressSize */
00146   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00147                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00148   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00149                                   This parameter can be a number between 0 and 31 */
00150   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00151                                   This parameter can be a value of @ref QSPI_InstructionMode */
00152   uint32_t AddressMode;        /* Specifies the Address Mode
00153                                   This parameter can be a value of @ref QSPI_AddressMode */
00154   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00155                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00156   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00157                                   This parameter can be a value of @ref QSPI_DataMode */
00158   uint32_t NbData;             /* Specifies the number of data to transfer.
00159                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
00160                                   until end of memory)*/
00161   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00162                                   This parameter can be a value of @ref QSPI_DdrMode */
00163   uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of
00164                                   system clock in DDR mode.
00165                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00166   uint32_t SIOOMode;          /* Specifies the send instruction only once mode
00167                                   This parameter can be a value of @ref QSPI_SIOOMode */
00168 }QSPI_CommandTypeDef;
00169
00170 /**
00171   * @brief  QSPI Auto Polling mode configuration structure definition
00172   */
00173 typedef struct
00174 {
00175   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00176                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00177   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00178                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00179   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00180                                   This parameter can be any value between 0 and 0xFFFF */
00181   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00182                                   This parameter can be any value between 1 and 4 */
00183   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00184                                   This parameter can be a value of @ref QSPI_MatchMode */
00185   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00186                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00187 }QSPI_AutoPollingTypeDef;
00188
00189 /**
00190   * @brief  QSPI Memory Mapped mode configuration structure definition
00191   */
00192 typedef struct
00193 {
00194   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00195                                   This parameter can be any value between 0 and 0xFFFF */
00196   uint32_t TimeOutActivation;  /* Specifies if the time out counter is enabled to release the chip select.
00197                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00198 }QSPI_MemoryMappedTypeDef;
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported constants --------------------------------------------------------*/
00204 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00205   * @{
00206   */
00207 /** @defgroup QSPI_ErrorCode QSPI Error Code
00208   * @{
00209   */
00210 #define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error           */
00211 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error      */
00212 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error     */
00213 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00219   * @{
00220   */
00221 #define QSPI_SAMPLE_SHIFTING_NONE           ((uint32_t)0x00000000)        /*!<No clock cycle shift to sample data*/
00222 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE      ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
00228   * @{
00229   */
00230 #define QSPI_CS_HIGH_TIME_1_CYCLE           ((uint32_t)0x00000000)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
00231 #define QSPI_CS_HIGH_TIME_2_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00232 #define QSPI_CS_HIGH_TIME_3_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00233 #define QSPI_CS_HIGH_TIME_4_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00234 #define QSPI_CS_HIGH_TIME_5_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00235 #define QSPI_CS_HIGH_TIME_6_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00236 #define QSPI_CS_HIGH_TIME_7_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00237 #define QSPI_CS_HIGH_TIME_8_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00243   * @{
00244   */
00245 #define QSPI_CLOCK_MODE_0                   ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
00246 #define QSPI_CLOCK_MODE_3                   ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00252   * @{
00253   */
00254 #define QSPI_FLASH_ID_1           ((uint32_t)0x00000000)
00255 #define QSPI_FLASH_ID_2           ((uint32_t)QUADSPI_CR_FSEL)
00256 /**
00257   * @}
00258   */
00259
00260   /** @defgroup QSPI_DualFlash_Mode  QSPI Dual Flash Mode
00261   * @{
00262   */
00263 #define QSPI_DUALFLASH_ENABLE            ((uint32_t)QUADSPI_CR_DFM)
00264 #define QSPI_DUALFLASH_DISABLE           ((uint32_t)0x00000000)
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup QSPI_AddressSize QSPI Address Size
00270   * @{
00271   */
00272 #define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
00273 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00274 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00275 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00281   * @{
00282   */
00283 #define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
00284 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00285 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00286 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00292 * @{
00293 */
00294 #define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
00295 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00296 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00297 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup QSPI_AddressMode QSPI Address Mode
00303 * @{
00304 */
00305 #define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
00306 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00307 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00308 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup QSPI_AlternateBytesMode  QSPI Alternate Bytes Mode
00314 * @{
00315 */
00316 #define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
00317 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00318 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00319 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup QSPI_DataMode QSPI Data Mode
00325   * @{
00326   */
00327 #define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
00328 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00329 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00330 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
00336   * @{
00337   */
00338 #define QSPI_DDR_MODE_DISABLE              ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
00339 #define QSPI_DDR_MODE_ENABLE               ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
00345   * @{
00346   */
00347 #define QSPI_DDR_HHC_ANALOG_DELAY           ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
00348 #define QSPI_DDR_HHC_HALF_CLK_DELAY         ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
00354   * @{
00355   */
00356 #define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
00357 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup QSPI_MatchMode QSPI Match Mode
00363   * @{
00364   */
00365 #define QSPI_MATCH_MODE_AND                 ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
00366 #define QSPI_MATCH_MODE_OR                  ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00372   * @{
00373   */
00374 #define QSPI_AUTOMATIC_STOP_DISABLE        ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
00375 #define QSPI_AUTOMATIC_STOP_ENABLE         ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
00381   * @{
00382   */
00383 #define QSPI_TIMEOUT_COUNTER_DISABLE       ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
00384 #define QSPI_TIMEOUT_COUNTER_ENABLE        ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup QSPI_Flags  QSPI Flags
00390   * @{
00391   */
00392 #define QSPI_FLAG_BUSY                      QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00393 #define QSPI_FLAG_TO                        QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00394 #define QSPI_FLAG_SM                        QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00395 #define QSPI_FLAG_FT                        QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00396 #define QSPI_FLAG_TC                        QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00397 #define QSPI_FLAG_TE                        QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup QSPI_Interrupts  QSPI Interrupts
00403   * @{
00404   */
00405 #define QSPI_IT_TO                          QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00406 #define QSPI_IT_SM                          QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00407 #define QSPI_IT_FT                          QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00408 #define QSPI_IT_TC                          QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00409 #define QSPI_IT_TE                          QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00415   * @{
00416   */
00417 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
00418 /**
00419   * @}
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Exported macros -----------------------------------------------------------*/
00427 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00428   * @{
00429   */
00430
00431 /** @brief Reset QSPI handle state
00432   * @param  __HANDLE__: QSPI handle.
00433   * @retval None
00434   */
00435 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00436
00437 /** @brief  Enable QSPI
00438   * @param  __HANDLE__: specifies the QSPI Handle.
00439   * @retval None
00440   */
00441 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00442
00443 /** @brief  Disable QSPI
00444   * @param  __HANDLE__: specifies the QSPI Handle.
00445   * @retval None
00446   */
00447 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00448
00449 /** @brief  Enables the specified QSPI interrupt.
00450   * @param  __HANDLE__: specifies the QSPI Handle.
00451   * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
00452   *          This parameter can be one of the following values:
00453   *            @arg QSPI_IT_TO: QSPI Time out interrupt
00454   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00455   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00456   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00457   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00458   * @retval None
00459   */
00460 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00461
00462
00463 /** @brief  Disables the specified QSPI interrupt.
00464   * @param  __HANDLE__: specifies the QSPI Handle.
00465   * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
00466   *          This parameter can be one of the following values:
00467   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00468   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00469   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00470   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00471   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00472   * @retval None
00473   */
00474 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00475
00476 /** @brief  Checks whether the specified QSPI interrupt source is enabled.
00477   * @param  __HANDLE__: specifies the QSPI Handle.
00478   * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
00479   *          This parameter can be one of the following values:
00480   *            @arg QSPI_IT_TO: QSPI Time out interrupt
00481   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00482   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00483   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00484   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00485   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00486   */
00487 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00488
00489 /**
00490   * @brief  Get the selected QSPI's flag status.
00491   * @param  __HANDLE__: specifies the QSPI Handle.
00492   * @param  __FLAG__: specifies the QSPI flag to check.
00493   *          This parameter can be one of the following values:
00494   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00495   *            @arg QSPI_FLAG_TO:   QSPI Time out flag
00496   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00497   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00498   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00499   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00500   * @retval None
00501   */
00502 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
00503
00504 /** @brief  Clears the specified QSPI's flag status.
00505   * @param  __HANDLE__: specifies the QSPI Handle.
00506   * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
00507   *          This parameter can be one of the following values:
00508   *            @arg QSPI_FLAG_TO: QSPI Time out flag
00509   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00510   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00511   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00512   * @retval None
00513   */
00514 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00515 /**
00516   * @}
00517   */
00518
00519 /* Exported functions --------------------------------------------------------*/
00520 /** @addtogroup QSPI_Exported_Functions
00521   * @{
00522   */
00523
00524 /** @addtogroup QSPI_Exported_Functions_Group1
00525   * @{
00526   */
00527 /* Initialization/de-initialization functions  ********************************/
00528 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00529 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00530 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00531 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00532 /**
00533   * @}
00534   */
00535
00536 /** @addtogroup QSPI_Exported_Functions_Group2
00537   * @{
00538   */
00539 /* IO operation functions *****************************************************/
00540 /* QSPI IRQ handler method */
00541 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00542
00543 /* QSPI indirect mode */
00544 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00545 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00546 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00547 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00548 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00549 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00550 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00551 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00552
00553 /* QSPI status flag polling mode */
00554 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00555 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00556
00557 /* QSPI memory-mapped mode */
00558 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00559 /**
00560   * @}
00561   */
00562
00563 /** @addtogroup QSPI_Exported_Functions_Group3
00564   * @{
00565   */
00566 /* Callback functions in non-blocking modes ***********************************/
00567 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00568 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00569
00570 /* QSPI indirect mode */
00571 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00572 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00573 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00574 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00575 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00576
00577 /* QSPI status flag polling mode */
00578 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00579
00580 /* QSPI memory-mapped mode */
00581 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00582 /**
00583   * @}
00584   */
00585
00586 /** @addtogroup QSPI_Exported_Functions_Group4
00587   * @{
00588   */
00589 /* Peripheral Control and State functions  ************************************/
00590 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
00591 uint32_t              HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
00592 HAL_StatusTypeDef     HAL_QSPI_Abort   (QSPI_HandleTypeDef *hqspi);
00593 void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00594 /**
00595   * @}
00596   */
00597
00598 /**
00599   * @}
00600   */
00601
00602 /* Private types -------------------------------------------------------------*/
00603 /* Private variables ---------------------------------------------------------*/
00604 /* Private constants ---------------------------------------------------------*/
00605 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00606   * @{
00607   */
00608
00609 /**
00610   * @}
00611   */
00612
00613 /* Private macros ------------------------------------------------------------*/
00614 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00615   * @{
00616   */
00617 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
00618   * @{
00619   */
00620 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER)  ((PRESCALER) <= 0xFF)
00621 /**
00622   * @}
00623   */
00624
00625 /** @defgroup QSPI_FifoThreshold  QSPI Fifo Threshold
00626   * @{
00627   */
00628 #define IS_QSPI_FIFO_THRESHOLD(THR)         (((THR) > 0) && ((THR) <= 32))
00629 /**
00630   * @}
00631   */
00632
00633 #define IS_QSPI_SSHIFT(SSHIFT)              (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00634                                              ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00635
00636 /** @defgroup QSPI_FlashSize QSPI Flash Size
00637   * @{
00638   */
00639 #define IS_QSPI_FLASH_SIZE(FSIZE)           (((FSIZE) <= 31))
00640 /**
00641   * @}
00642   */
00643
00644 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)       (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00645                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00646                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00647                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00648                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00649                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00650                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00651                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00652
00653 #define IS_QSPI_CLOCK_MODE(CLKMODE)         (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00654                                              ((CLKMODE) == QSPI_CLOCK_MODE_3))
00655
00656 #define IS_QSPI_FLASH_ID(FLA)    (((FLA) == QSPI_FLASH_ID_1) || \
00657                                   ((FLA) == QSPI_FLASH_ID_2))
00658
00659 #define IS_QSPI_DUAL_FLASH_MODE(MODE)    (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00660                                           ((MODE) == QSPI_DUALFLASH_DISABLE))
00661
00662
00663 /** @defgroup QSPI_Instruction QSPI Instruction
00664   * @{
00665   */
00666 #define IS_QSPI_INSTRUCTION(INSTRUCTION)    ((INSTRUCTION) <= 0xFF)
00667 /**
00668   * @}
00669   */
00670
00671 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)     (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00672                                              ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00673                                              ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00674                                              ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00675
00676 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)  (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00677                                              ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00678                                              ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00679                                              ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00680
00681
00682 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
00683   * @{
00684   */
00685 #define IS_QSPI_DUMMY_CYCLES(DCY)           ((DCY) <= 31)
00686 /**
00687   * @}
00688   */
00689
00690 #define IS_QSPI_INSTRUCTION_MODE(MODE)      (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00691                                              ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00692                                              ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00693                                              ((MODE) == QSPI_INSTRUCTION_4_LINES))
00694
00695 #define IS_QSPI_ADDRESS_MODE(MODE)          (((MODE) == QSPI_ADDRESS_NONE)    || \
00696                                              ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00697                                              ((MODE) == QSPI_ADDRESS_2_LINES) || \
00698                                              ((MODE) == QSPI_ADDRESS_4_LINES))
00699
00700 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE)  (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00701                                              ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00702                                              ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00703                                              ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00704
00705 #define IS_QSPI_DATA_MODE(MODE)             (((MODE) == QSPI_DATA_NONE)    || \
00706                                              ((MODE) == QSPI_DATA_1_LINE)  || \
00707                                              ((MODE) == QSPI_DATA_2_LINES) || \
00708                                              ((MODE) == QSPI_DATA_4_LINES))
00709
00710 #define IS_QSPI_DDR_MODE(DDR_MODE)          (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00711                                              ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00712
00713 #define IS_QSPI_DDR_HHC(DDR_HHC)            (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00714                                              ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00715
00716 #define IS_QSPI_SIOO_MODE(SIOO_MODE)      (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00717                                              ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00718
00719 /** @defgroup QSPI_Interval QSPI Interval
00720   * @{
00721   */
00722 #define IS_QSPI_INTERVAL(INTERVAL)        ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00723 /**
00724   * @}
00725   */
00726
00727 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
00728   * @{
00729   */
00730 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)   (((SIZE) >= 1) && ((SIZE) <= 4))
00731 /**
00732   * @}
00733   */
00734 #define IS_QSPI_MATCH_MODE(MODE)            (((MODE) == QSPI_MATCH_MODE_AND) || \
00735                                              ((MODE) == QSPI_MATCH_MODE_OR))
00736
00737 #define IS_QSPI_AUTOMATIC_STOP(APMS)        (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00738                                              ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00739
00740 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)    (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00741                                              ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00742
00743 /** @defgroup QSPI_TimeOutPeriod  QSPI TimeOut Period
00744   * @{
00745   */
00746 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)      ((PERIOD) <= 0xFFFF)
00747 /**
00748   * @}
00749   */
00750
00751 #define IS_QSPI_GET_FLAG(FLAG)              (((FLAG) == QSPI_FLAG_BUSY) || \
00752                                              ((FLAG) == QSPI_FLAG_TO)   || \
00753                                              ((FLAG) == QSPI_FLAG_SM)   || \
00754                                              ((FLAG) == QSPI_FLAG_FT)   || \
00755                                              ((FLAG) == QSPI_FLAG_TC)   || \
00756                                              ((FLAG) == QSPI_FLAG_TE))
00757
00758 #define IS_QSPI_IT(IT)                      ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
00759 /**
00760   * @}
00761   */
00762
00763 /* Private functions ---------------------------------------------------------*/
00764 /** @defgroup QSPI_Private_Functions QSPI Private Functions
00765   * @{
00766   */
00767
00768 /**
00769   * @}
00770   */
00771
00772 /**
00773   * @}
00774   */
00775
00776 /**
00777   * @}
00778   */
00779
00780 #ifdef __cplusplus
00781 }
00782 #endif
00783
00784 #endif /* __STM32F7xx_HAL_QSPI_H */
00785
00786 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc.c Source File

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stm32f7xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### RCC specific features #####
00016   ==============================================================================
00017     [..]
00018       After reset the device is running from Internal High Speed oscillator
00019       (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
00020       and I-Cache are disabled, and all peripherals are off except internal
00021       SRAM, Flash and JTAG.
00022       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
00023           all peripherals mapped on these busses are running at HSI speed.
00024       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00025       (+) All GPIOs are in input floating state, except the JTAG pins which
00026           are assigned to be used for debug purpose.
00027
00028     [..]
00029       Once the device started from reset, the user application has to:
00030       (+) Configure the clock source to be used to drive the System clock
00031           (if the application needs higher frequency/performance)
00032       (+) Configure the System clock frequency and Flash settings
00033       (+) Configure the AHB and APB busses prescalers
00034       (+) Enable the clock for the peripheral(s) to be used
00035       (+) Configure the clock source(s) for peripherals which clocks are not
00036           derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
00037
00038                       ##### RCC Limitations #####
00039   ==============================================================================
00040     [..]
00041       A delay between an RCC peripheral clock enable and the effective peripheral
00042       enabling should be taken into account in order to manage the peripheral read/write
00043       from/to registers.
00044       (+) This delay depends on the peripheral mapping.
00045       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
00046           after the clock enable bit is set on the hardware register
00047       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
00048           after the clock enable bit is set on the hardware register
00049
00050     [..]
00051       Implemented Workaround:
00052       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
00053           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00054
00055   @endverbatim
00056   ******************************************************************************
00057   * @attention
00058   *
00059   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00060   *
00061   * Redistribution and use in source and binary forms, with or without modification,
00062   * are permitted provided that the following conditions are met:
00063   *   1. Redistributions of source code must retain the above copyright notice,
00064   *      this list of conditions and the following disclaimer.
00065   *   2. Redistributions in binary form must reproduce the above copyright notice,
00066   *      this list of conditions and the following disclaimer in the documentation
00067   *      and/or other materials provided with the distribution.
00068   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00069   *      may be used to endorse or promote products derived from this software
00070   *      without specific prior written permission.
00071   *
00072   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00073   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00074   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00075   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00076   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00077   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00078   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00079   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00080   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00081   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32f7xx_hal.h"
00088
00089 /** @addtogroup STM32F7xx_HAL_Driver
00090   * @{
00091   */
00092
00093 /** @defgroup RCC RCC
00094   * @brief RCC HAL module driver
00095   * @{
00096   */
00097
00098 #ifdef HAL_RCC_MODULE_ENABLED
00099
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private define ------------------------------------------------------------*/
00102 /* Private macro -------------------------------------------------------------*/
00103 /** @defgroup RCC_Private_Macros RCC Private Macros
00104   * @{
00105   */
00106
00107 #define MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00108 #define MCO1_GPIO_PORT        GPIOA
00109 #define MCO1_PIN              GPIO_PIN_8
00110
00111 #define MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
00112 #define MCO2_GPIO_PORT         GPIOC
00113 #define MCO2_PIN               GPIO_PIN_9
00114
00115 /**
00116   * @}
00117   */
00118 /* Private variables ---------------------------------------------------------*/
00119 /** @defgroup RCC_Private_Variables RCC Private Variables
00120   * @{
00121   */
00122 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Private function prototypes -----------------------------------------------*/
00129 /* Exported functions ---------------------------------------------------------*/
00130
00131 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00132   * @{
00133   */
00134
00135 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00136   *  @brief    Initialization and Configuration functions
00137   *
00138   @verbatim
00139   ===============================================================================
00140 ##### Initialization and de-initialization functions #####
00141   ===============================================================================
00142     [..]
00143       This section provides functions allowing to configure the internal/external oscillators
00144       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
00145       and APB2).
00146
00147     [..] Internal/external clock and PLL configuration
00148       (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
00149           the PLL as System clock source.
00150
00151       (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
00152           clock source.
00153
00154       (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
00155           through the PLL as System clock source. Can be used also as RTC clock source.
00156
00157       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00158
00159       (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
00160         (++) The first output is used to generate the high speed system clock (up to 216 MHz)
00161         (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
00162              the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
00163
00164       (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
00165           and if a HSE clock failure occurs(HSE used directly or through PLL as System
00166           clock source), the System clock is automatically switched to HSI and an interrupt
00167           is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
00168           (Non-Maskable Interrupt) exception vector.
00169
00170       (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
00171           clock (through a configurable prescaler) on PA8 pin.
00172
00173       (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
00174           clock (through a configurable prescaler) on PC9 pin.
00175
00176     [..] System, AHB and APB busses clocks configuration
00177       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00178           HSE and PLL.
00179           The AHB clock (HCLK) is derived from System clock through configurable
00180           prescaler and used to clock the CPU, memory and peripherals mapped
00181           on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00182           from AHB clock through configurable prescalers and used to clock
00183           the peripherals mapped on these busses. You can use
00184           "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00185
00186       -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00187           (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
00188               from an external clock mapped on the I2S_CKIN pin.
00189               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
00190           (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
00191               from an external clock mapped on the I2S_CKIN pin.
00192                You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
00193           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
00194               divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
00195               macros to configure this clock.
00196           (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
00197               to work correctly, while the SDIO require a frequency equal or lower than
00198               to 48. This clock is derived of the main PLL through PLLQ divider.
00199           (+@) IWDG clock which is always the LSI clock.
00200 @endverbatim
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Resets the RCC clock configuration to the default reset state.
00206   * @note   The default reset state of the clock configuration is given below:
00207   *            - HSI ON and used as system clock source
00208   *            - HSE, PLL and PLLI2S OFF
00209   *            - AHB, APB1 and APB2 prescaler set to 1.
00210   *            - CSS, MCO1 and MCO2 OFF
00211   *            - All interrupts disabled
00212   * @note   This function doesn't modify the configuration of the
00213   *            - Peripheral clocks
00214   *            - LSI, LSE and RTC clocks
00215   * @retval None
00216   */
00217 void HAL_RCC_DeInit(void)
00218 {
00219   /* Set HSION bit */
00220   SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
00221
00222   /* Reset CFGR register */
00223   CLEAR_REG(RCC->CFGR);
00224
00225   /* Reset HSEON, CSSON, PLLON, PLLI2S */
00226   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
00227
00228   /* Reset PLLCFGR register */
00229   CLEAR_REG(RCC->PLLCFGR);
00230   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
00231
00232   /* Reset PLLI2SCFGR register */
00233   CLEAR_REG(RCC->PLLI2SCFGR);
00234   SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
00235
00236   /* Reset HSEBYP bit */
00237   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00238
00239   /* Disable all interrupts */
00240   CLEAR_REG(RCC->CIR);
00241 }
00242
00243 /**
00244   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00245   *         RCC_OscInitTypeDef.
00246   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
00247   *         contains the configuration information for the RCC Oscillators.
00248   * @note   The PLL is not disabled when used as system clock.
00249   * @retval HAL status
00250   */
00251 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00252 {
00253   uint32_t tickstart = 0;
00254
00255   /* Check the parameters */
00256   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00257
00258   /*------------------------------- HSE Configuration ------------------------*/
00259   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00260   {
00261     /* Check the parameters */
00262     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00263     /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
00264     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
00265        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
00266     {
00267           if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00268       {
00269         return HAL_ERROR;
00270       }
00271     }
00272     else
00273     {
00274       /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
00275       __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
00276
00277       /* Get Start Tick*/
00278       tickstart = HAL_GetTick();
00279
00280       /* Wait till HSE is disabled */
00281       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00282       {
00283         if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00284         {
00285           return HAL_TIMEOUT;
00286         }
00287       }
00288
00289       /* Set the new HSE configuration ---------------------------------------*/
00290       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00291
00292       /* Check the HSE State */
00293       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00294       {
00295         /* Get Start Tick*/
00296         tickstart = HAL_GetTick();
00297
00298         /* Wait till HSE is ready */
00299         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00300         {
00301           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00302           {
00303             return HAL_TIMEOUT;
00304           }
00305         }
00306       }
00307       else
00308       {
00309         /* Get Start Tick*/
00310         tickstart = HAL_GetTick();
00311
00312         /* Wait till HSE is bypassed or disabled */
00313         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00314         {
00315            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00316           {
00317             return HAL_TIMEOUT;
00318           }
00319         }
00320       }
00321     }
00322   }
00323   /*----------------------------- HSI Configuration --------------------------*/
00324   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00325   {
00326     /* Check the parameters */
00327     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00328     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00329
00330     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00331     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
00332        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
00333     {
00334       /* When HSI is used as system clock it will not disabled */
00335       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
00336       {
00337         return HAL_ERROR;
00338       }
00339       /* Otherwise, just the calibration is allowed */
00340       else
00341       {
00342         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00343         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00344       }
00345     }
00346     else
00347     {
00348       /* Check the HSI State */
00349       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
00350       {
00351         /* Enable the Internal High Speed oscillator (HSI). */
00352         __HAL_RCC_HSI_ENABLE();
00353
00354         /* Get Start Tick*/
00355         tickstart = HAL_GetTick();
00356
00357         /* Wait till HSI is ready */
00358         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00359         {
00360           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00361           {
00362             return HAL_TIMEOUT;
00363           }
00364         }
00365
00366         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00367         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00368       }
00369       else
00370       {
00371         /* Disable the Internal High Speed oscillator (HSI). */
00372         __HAL_RCC_HSI_DISABLE();
00373
00374         /* Get Start Tick*/
00375         tickstart = HAL_GetTick();
00376
00377         /* Wait till HSI is ready */
00378         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
00379         {
00380           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00381           {
00382             return HAL_TIMEOUT;
00383           }
00384         }
00385       }
00386     }
00387   }
00388   /*------------------------------ LSI Configuration -------------------------*/
00389   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00390   {
00391     /* Check the parameters */
00392     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00393
00394     /* Check the LSI State */
00395     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
00396     {
00397       /* Enable the Internal Low Speed oscillator (LSI). */
00398       __HAL_RCC_LSI_ENABLE();
00399
00400       /* Get Start Tick*/
00401       tickstart = HAL_GetTick();
00402
00403       /* Wait till LSI is ready */
00404       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
00405       {
00406         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00407         {
00408           return HAL_TIMEOUT;
00409         }
00410       }
00411     }
00412     else
00413     {
00414       /* Disable the Internal Low Speed oscillator (LSI). */
00415       __HAL_RCC_LSI_DISABLE();
00416
00417       /* Get Start Tick*/
00418       tickstart = HAL_GetTick();
00419
00420       /* Wait till LSI is ready */
00421       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
00422       {
00423         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00424         {
00425           return HAL_TIMEOUT;
00426         }
00427       }
00428     }
00429   }
00430   /*------------------------------ LSE Configuration -------------------------*/
00431   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00432   {
00433     /* Check the parameters */
00434     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00435
00436     /* Enable Power Clock*/
00437     __HAL_RCC_PWR_CLK_ENABLE();
00438
00439     /* Enable write access to Backup domain */
00440     PWR->CR1 |= PWR_CR1_DBP;
00441
00442     /* Wait for Backup domain Write protection disable */
00443     tickstart = HAL_GetTick();
00444
00445     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
00446     {
00447       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
00448       {
00449         return HAL_TIMEOUT;
00450       }
00451     }
00452
00453     /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
00454     __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
00455
00456     /* Get Start Tick*/
00457     tickstart = HAL_GetTick();
00458
00459     /* Wait till LSE is ready */
00460     while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00461     {
00462       if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00463       {
00464         return HAL_TIMEOUT;
00465       }
00466     }
00467
00468     /* Set the new LSE configuration -----------------------------------------*/
00469     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00470     /* Check the LSE State */
00471     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
00472     {
00473       /* Get Start Tick*/
00474       tickstart = HAL_GetTick();
00475
00476       /* Wait till LSE is ready */
00477       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00478       {
00479         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00480         {
00481           return HAL_TIMEOUT;
00482         }
00483       }
00484     }
00485     else
00486     {
00487       /* Get Start Tick*/
00488       tickstart = HAL_GetTick();
00489
00490       /* Wait till LSE is ready */
00491       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00492       {
00493         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00494         {
00495           return HAL_TIMEOUT;
00496         }
00497       }
00498     }
00499   }
00500   /*-------------------------------- PLL Configuration -----------------------*/
00501   /* Check the parameters */
00502   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00503   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00504   {
00505     /* Check if the PLL is used as system clock or not */
00506     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00507     {
00508       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00509       {
00510         /* Check the parameters */
00511         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00512         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00513         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00514         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00515         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00516
00517         /* Disable the main PLL. */
00518         __HAL_RCC_PLL_DISABLE();
00519
00520         /* Get Start Tick*/
00521         tickstart = HAL_GetTick();
00522
00523         /* Wait till PLL is ready */
00524         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00525         {
00526           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00527           {
00528             return HAL_TIMEOUT;
00529           }
00530         }
00531
00532         /* Configure the main PLL clock source, multiplication and division factors. */
00533         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00534                              RCC_OscInitStruct->PLL.PLLM,
00535                              RCC_OscInitStruct->PLL.PLLN,
00536                              RCC_OscInitStruct->PLL.PLLP,
00537                              RCC_OscInitStruct->PLL.PLLQ);
00538         /* Enable the main PLL. */
00539         __HAL_RCC_PLL_ENABLE();
00540
00541         /* Get Start Tick*/
00542         tickstart = HAL_GetTick();
00543
00544         /* Wait till PLL is ready */
00545         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00546         {
00547           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00548           {
00549             return HAL_TIMEOUT;
00550           }
00551         }
00552       }
00553       else
00554       {
00555         /* Disable the main PLL. */
00556         __HAL_RCC_PLL_DISABLE();
00557
00558         /* Get Start Tick*/
00559         tickstart = HAL_GetTick();
00560
00561         /* Wait till PLL is ready */
00562         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00563         {
00564           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00565           {
00566             return HAL_TIMEOUT;
00567           }
00568         }
00569       }
00570     }
00571     else
00572     {
00573       return HAL_ERROR;
00574     }
00575   }
00576   return HAL_OK;
00577 }
00578
00579 /**
00580   * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
00581   *         parameters in the RCC_ClkInitStruct.
00582   * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
00583   *         contains the configuration information for the RCC peripheral.
00584   * @param  FLatency: FLASH Latency, this parameter depend on device selected
00585   *
00586   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00587   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
00588   *
00589   * @note   The HSI is used (enabled by hardware) as system clock source after
00590   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
00591   *         of failure of the HSE used directly or indirectly as system clock
00592   *         (if the Clock Security System CSS is enabled).
00593   *
00594   * @note   A switch from one clock source to another occurs only if the target
00595   *         clock source is ready (clock stable after startup delay or PLL locked).
00596   *         If a clock source which is not yet ready is selected, the switch will
00597   *         occur when the clock source will be ready.
00598   *         You can use HAL_RCC_GetClockConfig() function to know which clock is
00599   *         currently used as system clock source.
00600   * @note   Depending on the device voltage range, the software has to set correctly
00601   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
00602   *         (for more details refer to section above "Initialization/de-initialization functions")
00603   * @retval None
00604   */
00605 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00606 {
00607   uint32_t tickstart = 0;
00608
00609   /* Check the parameters */
00610   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00611   assert_param(IS_FLASH_LATENCY(FLatency));
00612
00613   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00614      must be correctly programmed according to the frequency of the CPU clock
00615      (HCLK) and the supply voltage of the device. */
00616
00617   /* Increasing the CPU frequency */
00618   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
00619   {
00620     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00621     __HAL_FLASH_SET_LATENCY(FLatency);
00622
00623     /* Check that the new number of wait states is taken into account to access the Flash
00624     memory by reading the FLASH_ACR register */
00625     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00626     {
00627       return HAL_ERROR;
00628     }
00629
00630     /*-------------------------- HCLK Configuration --------------------------*/
00631     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00632     {
00633       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00634       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00635     }
00636
00637     /*------------------------- SYSCLK Configuration ---------------------------*/
00638     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00639     {
00640       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00641
00642       /* HSE is selected as System Clock Source */
00643       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00644       {
00645         /* Check the HSE ready flag */
00646         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00647         {
00648           return HAL_ERROR;
00649         }
00650       }
00651       /* PLL is selected as System Clock Source */
00652       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00653       {
00654         /* Check the PLL ready flag */
00655         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00656         {
00657           return HAL_ERROR;
00658         }
00659       }
00660       /* HSI is selected as System Clock Source */
00661       else
00662       {
00663         /* Check the HSI ready flag */
00664         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00665         {
00666           return HAL_ERROR;
00667         }
00668       }
00669
00670       __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
00671       /* Get Start Tick*/
00672       tickstart = HAL_GetTick();
00673
00674       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00675       {
00676         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
00677         {
00678           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00679           {
00680             return HAL_TIMEOUT;
00681           }
00682         }
00683       }
00684       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00685       {
00686         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00687         {
00688           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00689           {
00690             return HAL_TIMEOUT;
00691           }
00692         }
00693       }
00694       else
00695       {
00696         while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
00697         {
00698           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00699           {
00700             return HAL_TIMEOUT;
00701           }
00702         }
00703       }
00704     }
00705   }
00706   /* Decreasing the CPU frequency */
00707   else
00708   {
00709     /*-------------------------- HCLK Configuration --------------------------*/
00710     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00711     {
00712       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00713       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00714     }
00715
00716     /*------------------------- SYSCLK Configuration -------------------------*/
00717     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00718     {
00719       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00720
00721       /* HSE is selected as System Clock Source */
00722       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00723       {
00724         /* Check the HSE ready flag */
00725         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00726         {
00727           return HAL_ERROR;
00728         }
00729       }
00730       /* PLL is selected as System Clock Source */
00731       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00732       {
00733         /* Check the PLL ready flag */
00734         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00735         {
00736           return HAL_ERROR;
00737         }
00738       }
00739       /* HSI is selected as System Clock Source */
00740       else
00741       {
00742         /* Check the HSI ready flag */
00743         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00744         {
00745           return HAL_ERROR;
00746         }
00747       }
00748       __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
00749       /* Get Start Tick*/
00750       tickstart = HAL_GetTick();
00751
00752       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00753       {
00754         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
00755         {
00756           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00757           {
00758             return HAL_TIMEOUT;
00759           }
00760         }
00761       }
00762       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00763       {
00764         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00765         {
00766           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00767           {
00768             return HAL_TIMEOUT;
00769           }
00770         }
00771       }
00772       else
00773       {
00774         while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
00775         {
00776           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00777           {
00778             return HAL_TIMEOUT;
00779           }
00780         }
00781       }
00782     }
00783
00784     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00785     __HAL_FLASH_SET_LATENCY(FLatency);
00786
00787     /* Check that the new number of wait states is taken into account to access the Flash
00788     memory by reading the FLASH_ACR register */
00789     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00790     {
00791       return HAL_ERROR;
00792     }
00793  }
00794
00795   /*-------------------------- PCLK1 Configuration ---------------------------*/
00796   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00797   {
00798     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00799     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00800   }
00801
00802   /*-------------------------- PCLK2 Configuration ---------------------------*/
00803   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00804   {
00805     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00806     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
00807   }
00808
00809   /* Configure the source of time base considering new system clocks settings*/
00810   HAL_InitTick (TICK_INT_PRIORITY);
00811
00812   return HAL_OK;
00813 }
00814
00815 /**
00816   * @}
00817   */
00818
00819 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00820   *  @brief   RCC clocks control functions
00821   *
00822   @verbatim
00823   ===============================================================================
00824                   ##### Peripheral Control functions #####
00825   ===============================================================================
00826     [..]
00827     This subsection provides a set of functions allowing to control the RCC Clocks
00828     frequencies.
00829
00830 @endverbatim
00831   * @{
00832   */
00833
00834 /**
00835   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
00836   * @note   PA8/PC9 should be configured in alternate function mode.
00837   * @param  RCC_MCOx: specifies the output direction for the clock source.
00838   *          This parameter can be one of the following values:
00839   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
00840   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
00841   * @param  RCC_MCOSource: specifies the clock source to output.
00842   *          This parameter can be one of the following values:
00843   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
00844   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
00845   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
00846   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
00847   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
00848   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
00849   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
00850   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
00851   * @param  RCC_MCODiv: specifies the MCOx prescaler.
00852   *          This parameter can be one of the following values:
00853   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
00854   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
00855   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
00856   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
00857   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
00858   * @retval None
00859   */
00860 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00861 {
00862   GPIO_InitTypeDef GPIO_InitStruct;
00863   /* Check the parameters */
00864   assert_param(IS_RCC_MCO(RCC_MCOx));
00865   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
00866   /* RCC_MCO1 */
00867   if(RCC_MCOx == RCC_MCO1)
00868   {
00869     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
00870
00871     /* MCO1 Clock Enable */
00872     MCO1_CLK_ENABLE();
00873
00874     /* Configure the MCO1 pin in alternate function mode */
00875     GPIO_InitStruct.Pin = MCO1_PIN;
00876     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00877     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
00878     GPIO_InitStruct.Pull = GPIO_NOPULL;
00879     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00880     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
00881
00882     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
00883     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
00884   }
00885   else
00886   {
00887     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
00888
00889     /* MCO2 Clock Enable */
00890     MCO2_CLK_ENABLE();
00891
00892     /* Configure the MCO2 pin in alternate function mode */
00893     GPIO_InitStruct.Pin = MCO2_PIN;
00894     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00895     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
00896     GPIO_InitStruct.Pull = GPIO_NOPULL;
00897     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00898     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
00899
00900     /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
00901     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
00902   }
00903 }
00904
00905 /**
00906   * @brief  Enables the Clock Security System.
00907   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00908   *         is automatically disabled and an interrupt is generated to inform the
00909   *         software about the failure (Clock Security System Interrupt, CSSI),
00910   *         allowing the MCU to perform rescue operations. The CSSI is linked to
00911   *         the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
00912   * @retval None
00913   */
00914 void HAL_RCC_EnableCSS(void)
00915 {
00916   SET_BIT(RCC->CR, RCC_CR_CSSON);
00917 }
00918
00919 /**
00920   * @brief  Disables the Clock Security System.
00921   * @retval None
00922   */
00923 void HAL_RCC_DisableCSS(void)
00924 {
00925   CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
00926 }
00927
00928 /**
00929   * @brief  Returns the SYSCLK frequency
00930   *
00931   * @note   The system frequency computed by this function is not the real
00932   *         frequency in the chip. It is calculated based on the predefined
00933   *         constant and the selected clock source:
00934   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00935   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
00936   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
00937   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
00938   * @note     (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
00939   *               16 MHz) but the real value may vary depending on the variations
00940   *               in voltage and temperature.
00941   * @note     (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
00942   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
00943   *                frequency of the crystal used. Otherwise, this function may
00944   *                have wrong result.
00945   *
00946   * @note   The result of this function could be not correct when using fractional
00947   *         value for HSE crystal.
00948   *
00949   * @note   This function can be used by the user application to compute the
00950   *         baudrate for the communication peripherals or configure other parameters.
00951   *
00952   * @note   Each time SYSCLK changes, this function must be called to update the
00953   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
00954   *
00955   *
00956   * @retval SYSCLK frequency
00957   */
00958 uint32_t HAL_RCC_GetSysClockFreq(void)
00959 {
00960   uint32_t pllm = 0, pllvco = 0, pllp = 0;
00961   uint32_t sysclockfreq = 0;
00962
00963   /* Get SYSCLK source -------------------------------------------------------*/
00964   switch (RCC->CFGR & RCC_CFGR_SWS)
00965   {
00966     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
00967     {
00968       sysclockfreq = HSI_VALUE;
00969        break;
00970     }
00971     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
00972     {
00973       sysclockfreq = HSE_VALUE;
00974       break;
00975     }
00976     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */
00977     {
00978       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
00979       SYSCLK = PLL_VCO / PLLP */
00980       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
00981       if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
00982       {
00983         /* HSE used as PLL clock source */
00984         pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
00985       }
00986       else
00987       {
00988         /* HSI used as PLL clock source */
00989         pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
00990       }
00991       pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
00992
00993       sysclockfreq = pllvco/pllp;
00994       break;
00995     }
00996     default:
00997     {
00998       sysclockfreq = HSI_VALUE;
00999       break;
01000     }
01001   }
01002   return sysclockfreq;
01003 }
01004
01005 /**
01006   * @brief  Returns the HCLK frequency
01007   * @note   Each time HCLK changes, this function must be called to update the
01008   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01009   *
01010   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
01011   *         and updated within this function
01012   * @retval HCLK frequency
01013   */
01014 uint32_t HAL_RCC_GetHCLKFreq(void)
01015 {
01016   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
01017   return SystemCoreClock;
01018 }
01019
01020 /**
01021   * @brief  Returns the PCLK1 frequency
01022   * @note   Each time PCLK1 changes, this function must be called to update the
01023   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01024   * @retval PCLK1 frequency
01025   */
01026 uint32_t HAL_RCC_GetPCLK1Freq(void)
01027 {
01028   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01029   return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
01030 }
01031
01032 /**
01033   * @brief  Returns the PCLK2 frequency
01034   * @note   Each time PCLK2 changes, this function must be called to update the
01035   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01036   * @retval PCLK2 frequency
01037   */
01038 uint32_t HAL_RCC_GetPCLK2Freq(void)
01039 {
01040   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
01041   return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
01042 }
01043
01044 /**
01045   * @brief  Configures the RCC_OscInitStruct according to the internal
01046   * RCC configuration registers.
01047   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
01048   * will be configured.
01049   * @retval None
01050   */
01051 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01052 {
01053   /* Set all possible values for the Oscillator type parameter ---------------*/
01054   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
01055
01056   /* Get the HSE configuration -----------------------------------------------*/
01057   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01058   {
01059     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01060   }
01061   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
01062   {
01063     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01064   }
01065   else
01066   {
01067     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01068   }
01069
01070   /* Get the HSI configuration -----------------------------------------------*/
01071   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
01072   {
01073     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01074   }
01075   else
01076   {
01077     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01078   }
01079
01080   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
01081
01082   /* Get the LSE configuration -----------------------------------------------*/
01083   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01084   {
01085     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01086   }
01087   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01088   {
01089     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01090   }
01091   else
01092   {
01093     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01094   }
01095
01096   /* Get the LSI configuration -----------------------------------------------*/
01097   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01098   {
01099     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01100   }
01101   else
01102   {
01103     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01104   }
01105
01106   /* Get the PLL configuration -----------------------------------------------*/
01107   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01108   {
01109     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01110   }
01111   else
01112   {
01113     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01114   }
01115   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01116   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
01117   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
01118   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
01119   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
01120 }
01121
01122 /**
01123   * @brief  Configures the RCC_ClkInitStruct according to the internal
01124   * RCC configuration registers.
01125   * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
01126   * will be configured.
01127   * @param  pFLatency: Pointer on the Flash Latency.
01128   * @retval None
01129   */
01130 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01131 {
01132   /* Set all possible values for the Clock type parameter --------------------*/
01133   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01134
01135   /* Get the SYSCLK configuration --------------------------------------------*/
01136   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01137
01138   /* Get the HCLK configuration ----------------------------------------------*/
01139   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01140
01141   /* Get the APB1 configuration ----------------------------------------------*/
01142   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
01143
01144   /* Get the APB2 configuration ----------------------------------------------*/
01145   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
01146
01147   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01148   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01149 }
01150
01151 /**
01152   * @brief This function handles the RCC CSS interrupt request.
01153   * @note This API should be called under the NMI_Handler().
01154   * @retval None
01155   */
01156 void HAL_RCC_NMI_IRQHandler(void)
01157 {
01158   /* Check RCC CSSF flag  */
01159   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01160   {
01161     /* RCC Clock Security System interrupt user callback */
01162     HAL_RCC_CSSCallback();
01163
01164     /* Clear RCC CSS pending bit */
01165     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01166   }
01167 }
01168
01169 /**
01170   * @brief  RCC Clock Security System interrupt callback
01171   * @retval None
01172   */
01173 __weak void HAL_RCC_CSSCallback(void)
01174 {
01175 __IO uint32_t tmpreg = 0x00;
01176   UNUSED(tmpreg);
01177
01178   /* NOTE : This function Should not be modified, when the callback is needed,
01179             the HAL_RCC_CSSCallback could be implemented in the user file
01180    */
01181 }
01182
01183 /**
01184   * @}
01185   */
01186
01187 /**
01188   * @}
01189   */
01190
01191 #endif /* HAL_RCC_MODULE_ENABLED */
01192 /**
01193   * @}
01194   */
01195
01196 /**
01197   * @}
01198   */
01199
01200 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc.h Source File

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stm32f7xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of RCC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_RCC_H
00040 #define __STM32F7xx_HAL_RCC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup RCC_Exported_Types RCC Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  RCC PLL configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PLLState;   /*!< The new state of the PLL.
00069                             This parameter can be a value of @ref RCC_PLL_Config                      */
00070
00071   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00072                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00073
00074   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00075                             This parameter must be a number between Min_Data = 2 and Max_Data = 63    */
00076
00077   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00078                             This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
00079
00080   uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
00081                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
00082
00083   uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
00084                             This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
00085
00086 }RCC_PLLInitTypeDef;
00087
00088 /**
00089   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
00090   */
00091 typedef struct
00092 {
00093   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00094                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00095
00096   uint32_t HSEState;             /*!< The new state of the HSE.
00097                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00098
00099   uint32_t LSEState;             /*!< The new state of the LSE.
00100                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00101
00102   uint32_t HSIState;             /*!< The new state of the HSI.
00103                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00104
00105   uint32_t HSICalibrationValue;   /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00106                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00107
00108   uint32_t LSIState;             /*!< The new state of the LSI.
00109                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00110
00111   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
00112
00113 }RCC_OscInitTypeDef;
00114
00115 /**
00116   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t ClockType;             /*!< The clock to be configured.
00121                                        This parameter can be a value of @ref RCC_System_Clock_Type */
00122
00123   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
00124                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
00125
00126   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00127                                        This parameter can be a value of @ref RCC_AHB_Clock_Source       */
00128
00129   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00130                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00131
00132   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00133                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00134
00135 }RCC_ClkInitTypeDef;
00136
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00143   * @{
00144   */
00145
00146 /** @defgroup RCC_Oscillator_Type Oscillator Type
00147   * @{
00148   */
00149 #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
00150 #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
00151 #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
00152 #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
00153 #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup RCC_HSE_Config RCC HSE Config
00159   * @{
00160   */
00161 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)
00162 #define RCC_HSE_ON                       RCC_CR_HSEON
00163 #define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup RCC_LSE_Config RCC LSE Config
00169   * @{
00170   */
00171 #define RCC_LSE_OFF                    ((uint32_t)0x00000000)
00172 #define RCC_LSE_ON                     RCC_BDCR_LSEON
00173 #define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup RCC_HSI_Config RCC HSI Config
00179   * @{
00180   */
00181 #define RCC_HSI_OFF                    ((uint32_t)0x00000000)
00182 #define RCC_HSI_ON                     RCC_CR_HSION
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup RCC_LSI_Config RCC LSI Config
00188   * @{
00189   */
00190 #define RCC_LSI_OFF                    ((uint32_t)0x00000000)
00191 #define RCC_LSI_ON                     RCC_CSR_LSION
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup RCC_PLL_Config RCC PLL Config
00197   * @{
00198   */
00199 #define RCC_PLL_NONE                   ((uint32_t)0x00000000)
00200 #define RCC_PLL_OFF                    ((uint32_t)0x00000001)
00201 #define RCC_PLL_ON                     ((uint32_t)0x00000002)
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
00207   * @{
00208   */
00209 #define RCC_PLLP_DIV2                  ((uint32_t)0x00000002)
00210 #define RCC_PLLP_DIV4                  ((uint32_t)0x00000004)
00211 #define RCC_PLLP_DIV6                  ((uint32_t)0x00000006)
00212 #define RCC_PLLP_DIV8                  ((uint32_t)0x00000008)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00218   * @{
00219   */
00220 #define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
00221 #define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
00227   * @{
00228   */
00229 #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001)
00230 #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002)
00231 #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004)
00232 #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
00238   * @{
00239   */
00240 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
00241 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
00242 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
00243 /**
00244   * @}
00245   */
00246
00247
00248 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00249   * @{
00250   */
00251 #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00252 #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00253 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
00259   * @{
00260   */
00261 #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
00262 #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
00263 #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
00264 #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
00265 #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
00266 #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
00267 #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
00268 #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
00269 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
00275   * @{
00276   */
00277 #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
00278 #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
00279 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
00280 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
00281 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
00287   * @{
00288   */
00289 #define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100)
00290 #define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200)
00291 #define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300)
00292 #define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300)
00293 #define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300)
00294 #define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300)
00295 #define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300)
00296 #define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300)
00297 #define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300)
00298 #define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300)
00299 #define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300)
00300 #define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300)
00301 #define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300)
00302 #define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300)
00303 #define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300)
00304 #define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300)
00305 #define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300)
00306 #define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300)
00307 #define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300)
00308 #define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300)
00309 #define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300)
00310 #define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300)
00311 #define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300)
00312 #define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300)
00313 #define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300)
00314 #define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300)
00315 #define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300)
00316 #define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300)
00317 #define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300)
00318 #define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300)
00319 #define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300)
00320 #define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300)
00321 /**
00322   * @}
00323   */
00324
00325
00326
00327 /** @defgroup RCC_MCO_Index RCC MCO Index
00328   * @{
00329   */
00330 #define RCC_MCO1                         ((uint32_t)0x00000000)
00331 #define RCC_MCO2                         ((uint32_t)0x00000001)
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
00337   * @{
00338   */
00339 #define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000)
00340 #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
00341 #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
00342 #define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
00348   * @{
00349   */
00350 #define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000)
00351 #define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
00352 #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
00353 #define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
00359   * @{
00360   */
00361 #define RCC_MCODIV_1                    ((uint32_t)0x00000000)
00362 #define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
00363 #define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
00364 #define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00365 #define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup RCC_Interrupt RCC Interrupt
00371   * @{
00372   */
00373 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
00374 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
00375 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
00376 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
00377 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
00378 #define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
00379 #define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40)
00380 #define RCC_IT_CSS                       ((uint8_t)0x80)
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup RCC_Flag RCC Flags
00386   *        Elements values convention: 0XXYYYYYb
00387   *           - YYYYY  : Flag position in the register
00388   *           - 0XX  : Register index
00389   *                 - 01: CR register
00390   *                 - 10: BDCR register
00391   *                 - 11: CSR register
00392   * @{
00393   */
00394 /* Flags in the CR register */
00395 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
00396 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
00397 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
00398 #define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
00399 #define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3C)
00400
00401 /* Flags in the BDCR register */
00402 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
00403
00404 /* Flags in the CSR register */
00405 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
00406 #define RCC_FLAG_BORRST                  ((uint8_t)0x79)
00407 #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
00408 #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
00409 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
00410 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
00411 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
00412 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
00418   * @{
00419   */
00420 #define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000)
00421 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_1
00422 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_0
00423 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /* Exported macro ------------------------------------------------------------*/
00433 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00434   * @{
00435   */
00436
00437 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
00438   * @brief  Enable or disable the AHB1 peripheral clock.
00439   * @note   After reset, the peripheral clock (used for registers read/write access)
00440   *         is disabled and the application software has to enable this clock before
00441   *         using it.
00442   * @{
00443   */
00444 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
00445                                       __IO uint32_t tmpreg = 0x00; \
00446                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
00447                                         /* Delay after an RCC peripheral clock enabling */ \
00448                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
00449                                         UNUSED(tmpreg); \
00450                                       } while(0)
00451
00452 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
00453                                       __IO uint32_t tmpreg = 0x00; \
00454                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00455                                         /* Delay after an RCC peripheral clock enabling */ \
00456                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00457                                         UNUSED(tmpreg); \
00458                                       } while(0)
00459
00460 #define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
00461 #define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
00462
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
00468   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
00469   * @note   After reset, the peripheral clock (used for registers read/write access)
00470   *         is disabled and the application software has to enable this clock before
00471   *         using it.
00472   * @{
00473   */
00474 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
00475                                       __IO uint32_t tmpreg = 0x00; \
00476                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00477                                         /* Delay after an RCC peripheral clock enabling */ \
00478                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00479                                         UNUSED(tmpreg); \
00480                                       } while(0)
00481
00482 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
00483                                       __IO uint32_t tmpreg = 0x00; \
00484                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00485                                         /* Delay after an RCC peripheral clock enabling */ \
00486                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00487                                         UNUSED(tmpreg); \
00488                                       } while(0)
00489
00490 #define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
00491 #define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
00492 /**
00493   * @}
00494   */
00495
00496 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
00497   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
00498   * @note   After reset, the peripheral clock (used for registers read/write access)
00499   *         is disabled and the application software has to enable this clock before
00500   *         using it.
00501   * @{
00502   */
00503 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
00504                                       __IO uint32_t tmpreg = 0x00; \
00505                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
00506                                         /* Delay after an RCC peripheral clock enabling */ \
00507                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
00508                                         UNUSED(tmpreg); \
00509                                       } while(0)
00510
00511 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
00512
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
00518   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
00519   * @note   After reset, the peripheral clock (used for registers read/write access)
00520   *         is disabled and the application software has to enable this clock before
00521   *         using it.
00522   * @{
00523   */
00524 #define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
00525 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
00526
00527 #define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
00528 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable  Status
00534   * @brief  Get the enable or disable status of the APB1 peripheral clock.
00535   * @note   After reset, the peripheral clock (used for registers read/write access)
00536   *         is disabled and the application software has to enable this clock before
00537   *         using it.
00538   * @{
00539   */
00540 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
00541 #define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
00542
00543 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
00544 #define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
00550   * @brief  EGet the enable or disable status of the APB2 peripheral clock.
00551   * @note   After reset, the peripheral clock (used for registers read/write access)
00552   *         is disabled and the application software has to enable this clock before
00553   *         using it.
00554   * @{
00555   */
00556 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
00557 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
00563   * @brief  Force or release AHB peripheral reset.
00564   * @{
00565   */
00566 #define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFF)
00567 #define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
00568 #define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
00569
00570 #define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00)
00571 #define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
00572 #define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
00578   * @brief  Force or release APB1 peripheral reset.
00579   * @{
00580   */
00581 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFF)
00582 #define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
00583 #define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
00584
00585 #define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00)
00586 #define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
00587 #define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
00588 /**
00589   * @}
00590   */
00591
00592 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
00593   * @brief  Force or release APB2 peripheral reset.
00594   * @{
00595   */
00596 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFF)
00597 #define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
00598
00599 #define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00)
00600 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
00601
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
00607   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00608   *         power consumption.
00609   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
00610   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00611   * @{
00612   */
00613 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
00614 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
00615
00616 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
00617 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
00618
00619 /** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
00620   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00621   *         power consumption.
00622   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
00623   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00624   */
00625 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
00626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
00627
00628 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
00629 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
00630
00631 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
00632   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00633   *         power consumption.
00634   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
00635   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00636   */
00637 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
00638 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
00639
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
00645   * @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
00646   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00647   *         power consumption.
00648   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
00649   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00650   * @{
00651   */
00652 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
00653 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
00654
00655 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
00656 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
00662   * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
00663   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00664   *         power consumption.
00665   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
00666   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00667   * @{
00668   */
00669 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
00670 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
00671
00672 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
00673 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
00674 /**
00675   * @}
00676   */
00677
00678 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
00679   * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
00680   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00681   *         power consumption.
00682   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
00683   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00684   * @{
00685   */
00686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
00687 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
00688 /**
00689   * @}
00690   */
00691
00692 /** @defgroup RCC_HSI_Configuration HSI Configuration
00693   * @{
00694   */
00695
00696 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
00697   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
00698   *         It is used (enabled by hardware) as system clock source after startup
00699   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
00700   *         of the HSE used directly or indirectly as system clock (if the Clock
00701   *         Security System CSS is enabled).
00702   * @note   HSI can not be stopped if it is used as system clock source. In this case,
00703   *         you have to select another source of the system clock then stop the HSI.
00704   * @note   After enabling the HSI, the application software should wait on HSIRDY
00705   *         flag to be set indicating that HSI clock is stable and can be used as
00706   *         system clock source.
00707   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
00708   *         clock cycles.
00709   */
00710 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
00711 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
00712
00713 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
00714   * @note   The calibration is used to compensate for the variations in voltage
00715   *         and temperature that influence the frequency of the internal HSI RC.
00716   * @param  __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
00717   *         This parameter must be a number between 0 and 0x1F.
00718   */
00719 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
00720         RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup RCC_LSI_Configuration LSI Configuration
00726   * @{
00727   */
00728
00729 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
00730   * @note   After enabling the LSI, the application software should wait on
00731   *         LSIRDY flag to be set indicating that LSI clock is stable and can
00732   *         be used to clock the IWDG and/or the RTC.
00733   * @note   LSI can not be disabled if the IWDG is running.
00734   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
00735   *         clock cycles.
00736   */
00737 #define __HAL_RCC_LSI_ENABLE()  (RCC->CSR |= (RCC_CSR_LSION))
00738 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
00739 /**
00740   * @}
00741   */
00742
00743 /** @defgroup RCC_HSE_Configuration HSE Configuration
00744   * @{
00745   */
00746 /**
00747   * @brief  Macro to configure the External High Speed oscillator (__HSE__).
00748   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
00749   *         software should wait on HSERDY flag to be set indicating that HSE clock
00750   *         is stable and can be used to clock the PLL and/or system clock.
00751   * @note   HSE state can not be changed if it is used directly or through the
00752   *         PLL as system clock. In this case, you have to select another source
00753   *         of the system clock then change the HSE state (ex. disable it).
00754   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
00755   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
00756   *         was previously enabled you have to enable it again after calling this
00757   *         function.
00758   * @param  __STATE__: specifies the new state of the HSE.
00759   *         This parameter can be one of the following values:
00760   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
00761   *                              6 HSE oscillator clock cycles.
00762   *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
00763   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
00764   */
00765 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
00766                     do {                                     \
00767                       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);      \
00768                       if((__STATE__) == RCC_HSE_ON)          \
00769                       {                                      \
00770                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
00771                         SET_BIT(RCC->CR, RCC_CR_HSEON);      \
00772                       }                                      \
00773                       else if((__STATE__) == RCC_HSE_BYPASS) \
00774                       {                                      \
00775                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
00776                         SET_BIT(RCC->CR, RCC_CR_HSEON);      \
00777                       }                                      \
00778                       else                                   \
00779                       {                                      \
00780                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
00781                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
00782                         }                                    \
00783                     } while(0)
00784 /**
00785   * @}
00786   */
00787
00788 /** @defgroup RCC_LSE_Configuration LSE Configuration
00789   * @{
00790   */
00791
00792 /**
00793   * @brief  Macro to configure the External Low Speed oscillator (LSE).
00794   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
00795   *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
00796   * @note   As the LSE is in the Backup domain and write access is denied to
00797   *         this domain after reset, you have to enable write access using
00798   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
00799   *         (to be done once after reset).
00800   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
00801   *         software should wait on LSERDY flag to be set indicating that LSE clock
00802   *         is stable and can be used to clock the RTC.
00803   * @param  __STATE__: specifies the new state of the LSE.
00804   *         This parameter can be one of the following values:
00805   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
00806   *                              6 LSE oscillator clock cycles.
00807   *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
00808   *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
00809   */
00810 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
00811                     do {                                       \
00812                       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
00813                       if((__STATE__) == RCC_LSE_ON)            \
00814                       {                                        \
00815                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
00816                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
00817                       }                                        \
00818                       else if((__STATE__) == RCC_LSE_BYPASS)   \
00819                       {                                        \
00820                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
00821                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
00822                       }                                        \
00823                       else                                     \
00824                       {                                        \
00825                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
00826                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
00827                       }                                        \
00828                     } while(0)
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
00834   * @{
00835   */
00836
00837 /** @brief  Macros to enable or disable the RTC clock.
00838   * @note   These macros must be used only after the RTC clock source was selected.
00839   */
00840 #define __HAL_RCC_RTC_ENABLE()  (RCC->BDCR |= (RCC_BDCR_RTCEN))
00841 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
00842
00843 /** @brief  Macros to configure the RTC clock (RTCCLK).
00844   * @note   As the RTC clock configuration bits are in the Backup domain and write
00845   *         access is denied to this domain after reset, you have to enable write
00846   *         access using the Power Backup Access macro before to configure
00847   *         the RTC clock source (to be done once after reset).
00848   * @note   Once the RTC clock is configured it can't be changed unless the
00849   *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
00850   *         a Power On Reset (POR).
00851   * @param  __RTCCLKSource__: specifies the RTC clock source.
00852   *         This parameter can be one of the following values:
00853   *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
00854   *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
00855   *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
00856   *                                            as RTC clock, where x:[2,31]
00857   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
00858   *         work in STOP and STANDBY modes, and can be used as wakeup source.
00859   *         However, when the HSE clock is used as RTC clock source, the RTC
00860   *         cannot be used in STOP and STANDBY modes.
00861   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
00862   *         RTC clock source).
00863   */
00864 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
00865                                                  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
00866
00867 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
00868                                                     RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
00869                                                    } while (0)
00870
00871 /** @brief  Macros to force or release the Backup domain reset.
00872   * @note   This function resets the RTC peripheral (including the backup registers)
00873   *         and the RTC clock source selection in RCC_CSR register.
00874   * @note   The BKPSRAM is not affected by this reset.
00875   */
00876 #define __HAL_RCC_BACKUPRESET_FORCE()   (RCC->BDCR |= (RCC_BDCR_BDRST))
00877 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup RCC_PLL_Configuration PLL Configuration
00883   * @{
00884   */
00885
00886 /** @brief  Macros to enable or disable the main PLL.
00887   * @note   After enabling the main PLL, the application software should wait on
00888   *         PLLRDY flag to be set indicating that PLL clock is stable and can
00889   *         be used as system clock source.
00890   * @note   The main PLL can not be disabled if it is used as system clock source
00891   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
00892   */
00893 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
00894 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
00895
00896
00897 /** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
00898   * @note   This function must be used only when the main PLL is disabled.
00899   * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
00900   *         This parameter can be one of the following values:
00901   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
00902   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
00903   * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
00904   * @param  __PLLM__: specifies the division factor for PLL VCO input clock
00905   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
00906   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
00907   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00908   *         of 2 MHz to limit PLL jitter.
00909   * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
00910   *         This parameter must be a number between Min_Data = 100 and Max_Data = 432.
00911   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
00912   *         output frequency is between 100 and 432 MHz.
00913   * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
00914   *         This parameter must be a number in the range {2, 4, 6, or 8}.
00915   * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on
00916   *         the System clock frequency.
00917   * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
00918   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00919   * @note   If the USB OTG FS is used in your application, you have to set the
00920   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
00921   *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
00922   *         correctly.
00923   */
00924 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
00925                             (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
00926                             ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
00927                             ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
00928
00929 /** @brief  Macro to configure the PLL clock source.
00930   * @note   This function must be used only when the main PLL is disabled.
00931   * @param  __PLLSOURCE__: specifies the PLL entry clock source.
00932   *         This parameter can be one of the following values:
00933   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
00934   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
00935   *
00936   */
00937 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
00938
00939 /** @brief  Macro to configure the PLL multiplication factor.
00940   * @note   This function must be used only when the main PLL is disabled.
00941   * @param  __PLLM__: specifies the division factor for PLL VCO input clock
00942   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
00943   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
00944   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00945   *         of 2 MHz to limit PLL jitter.
00946   *
00947   */
00948 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
00949 /**
00950   * @}
00951   */
00952
00953 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
00954   * @{
00955   */
00956
00957 /** @brief  Macro to configure the I2S clock source (I2SCLK).
00958   * @note   This function must be called before enabling the I2S APB clock.
00959   * @param  __SOURCE__: specifies the I2S clock source.
00960   *         This parameter can be one of the following values:
00961   *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
00962   *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
00963   *                                       used as I2S clock source.
00964   */
00965 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
00966                                              RCC->CFGR |= (__SOURCE__);       \
00967                                             }while(0)
00968
00969 /** @brief Macros to enable or disable the PLLI2S.
00970   * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
00971   */
00972 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
00973 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
00974 /**
00975   * @}
00976   */
00977
00978 /** @defgroup RCC_Get_Clock_source Get Clock source
00979   * @{
00980   */
00981 /**
00982   * @brief Macro to configure the system clock source.
00983   * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
00984   * This parameter can be one of the following values:
00985   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
00986   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
00987   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
00988   */
00989 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
00990
00991 /** @brief  Macro to get the clock source used as system clock.
00992   * @retval The clock source used as system clock. The returned value can be one
00993   *         of the following:
00994   *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
00995   *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
00996   *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
00997   */
00998 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
00999
01000 /**
01001   * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.
01002   * @note   As the LSE is in the Backup domain and write access is denied to
01003   *         this domain after reset, you have to enable write access using
01004   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
01005   *         (to be done once after reset).
01006   * @param  __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
01007   *          This parameter can be one of the following values:
01008   *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
01009   *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
01010   *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
01011   *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
01012   * @retval None
01013   */
01014 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
01015                   (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
01016
01017 /** @brief  Macro to get the oscillator used as PLL clock source.
01018   * @retval The oscillator used as PLL clock source. The returned value can be one
01019   *         of the following:
01020   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
01021   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
01022   */
01023 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
01024 /**
01025   * @}
01026   */
01027
01028 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
01029   * @{
01030   */
01031
01032 /** @brief  Macro to configure the MCO1 clock.
01033   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
01034   *          This parameter can be one of the following values:
01035   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
01036   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
01037   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
01038   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
01039   * @param  __MCODIV__ specifies the MCO clock prescaler.
01040   *          This parameter can be one of the following values:
01041   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
01042   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
01043   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
01044   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
01045   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
01046   */
01047
01048 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
01049         MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
01050
01051 /** @brief  Macro to configure the MCO2 clock.
01052   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
01053   *          This parameter can be one of the following values:
01054   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
01055   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
01056   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
01057   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
01058   * @param  __MCODIV__ specifies the MCO clock prescaler.
01059   *          This parameter can be one of the following values:
01060   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
01061   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
01062   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
01063   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
01064   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
01065   */
01066
01067 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
01068         MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
01074   * @brief macros to manage the specified RCC Flags and interrupts.
01075   * @{
01076   */
01077
01078 /** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
01079   *         the selected interrupts).
01080   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
01081   *         This parameter can be any combination of the following values:
01082   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01083   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01084   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01085   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01086   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01087   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01088   */
01089 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
01090
01091 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
01092   *        the selected interrupts).
01093   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
01094   *         This parameter can be any combination of the following values:
01095   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01096   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01097   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01098   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01099   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01100   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01101   */
01102 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
01103
01104 /** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
01105   *         bits to clear the selected interrupt pending bits.
01106   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
01107   *         This parameter can be any combination of the following values:
01108   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01109   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01110   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01111   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01112   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01113   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01114   *            @arg RCC_IT_CSS: Clock Security System interrupt
01115   */
01116 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
01117
01118 /** @brief  Check the RCC's interrupt has occurred or not.
01119   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
01120   *         This parameter can be one of the following values:
01121   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01122   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01123   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01124   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01125   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01126   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01127   *            @arg RCC_IT_CSS: Clock Security System interrupt
01128   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
01129   */
01130 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
01131
01132 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
01133   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
01134   */
01135 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
01136
01137 /** @brief  Check RCC flag is set or not.
01138   * @param  __FLAG__: specifies the flag to check.
01139   *         This parameter can be one of the following values:
01140   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
01141   *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
01142   *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
01143   *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
01144   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
01145   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
01146   *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
01147   *            @arg RCC_FLAG_PINRST: Pin reset.
01148   *            @arg RCC_FLAG_PORRST: POR/PDR reset.
01149   *            @arg RCC_FLAG_SFTRST: Software reset.
01150   *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
01151   *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
01152   *            @arg RCC_FLAG_LPWRRST: Low Power reset.
01153   * @retval The new state of __FLAG__ (TRUE or FALSE).
01154   */
01155 #define RCC_FLAG_MASK  ((uint8_t)0x1F)
01156 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
01157
01158 /**
01159   * @}
01160   */
01161
01162 /**
01163   * @}
01164   */
01165
01166 /* Include RCC HAL Extension module */
01167 #include "stm32f7xx_hal_rcc_ex.h"
01168
01169 /* Exported functions --------------------------------------------------------*/
01170  /** @addtogroup RCC_Exported_Functions
01171   * @{
01172   */
01173
01174 /** @addtogroup RCC_Exported_Functions_Group1
01175   * @{
01176   */
01177 /* Initialization and de-initialization functions  ******************************/
01178 void HAL_RCC_DeInit(void);
01179 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
01180 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
01181 /**
01182   * @}
01183   */
01184
01185 /** @addtogroup RCC_Exported_Functions_Group2
01186   * @{
01187   */
01188 /* Peripheral Control functions  ************************************************/
01189 void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
01190 void     HAL_RCC_EnableCSS(void);
01191 void     HAL_RCC_DisableCSS(void);
01192 uint32_t HAL_RCC_GetSysClockFreq(void);
01193 uint32_t HAL_RCC_GetHCLKFreq(void);
01194 uint32_t HAL_RCC_GetPCLK1Freq(void);
01195 uint32_t HAL_RCC_GetPCLK2Freq(void);
01196 void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
01197 void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
01198
01199 /* CSS NMI IRQ handler */
01200 void HAL_RCC_NMI_IRQHandler(void);
01201
01202 /* User Callbacks in non blocking mode (IT mode) */
01203 void HAL_RCC_CSSCallback(void);
01204 /**
01205   * @}
01206   */
01207
01208 /**
01209   * @}
01210   */
01211
01212 /* Private types -------------------------------------------------------------*/
01213 /* Private variables ---------------------------------------------------------*/
01214 /* Private constants ---------------------------------------------------------*/
01215 /** @defgroup RCC_Private_Constants RCC Private Constants
01216   * @{
01217   */
01218 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
01219 #define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
01220 #define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
01221 #define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
01222 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
01223
01224 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
01225   * @brief RCC registers bit address alias
01226   * @{
01227   */
01228 /* CIR register byte 2 (Bits[15:8]) base address */
01229 #define RCC_CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
01230
01231 /* CIR register byte 3 (Bits[23:16]) base address */
01232 #define RCC_CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
01233
01234 #define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)
01235 #define RCC_LSE_TIMEOUT_VALUE      ((uint32_t)5000)
01236 /**
01237   * @}
01238   */
01239 /**
01240   * @}
01241   */
01242
01243 /* Private macros ------------------------------------------------------------*/
01244 /** @addtogroup RCC_Private_Macros RCC Private Macros
01245   * @{
01246   */
01247
01248 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
01249   * @{
01250   */
01251 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
01252
01253 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
01254                          ((HSE) == RCC_HSE_BYPASS))
01255
01256 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
01257                          ((LSE) == RCC_LSE_BYPASS))
01258
01259 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
01260
01261 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
01262
01263 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
01264
01265 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
01266                                   ((SOURCE) == RCC_PLLSOURCE_HSE))
01267
01268 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
01269                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
01270                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
01271 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
01272
01273 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
01274
01275 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
01276                                   ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
01277 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
01278
01279 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
01280                            ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
01281                            ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
01282                            ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
01283                            ((HCLK) == RCC_SYSCLK_DIV512))
01284
01285 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
01286
01287 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
01288                            ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
01289                            ((PCLK) == RCC_HCLK_DIV16))
01290
01291 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
01292
01293
01294 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
01295                                    ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
01296
01297 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
01298                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
01299
01300 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
01301                              ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
01302                              ((DIV) == RCC_MCODIV_5))
01303 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
01304
01305 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
01306                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
01307                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
01308                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
01309                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
01310                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
01311                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
01312                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
01313                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
01314                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
01315                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
01316                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
01317                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
01318                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
01319                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
01320                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
01321
01322
01323 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW)        || \
01324                                  ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \
01325                                  ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
01326                                  ((DRIVE) == RCC_LSEDRIVE_HIGH))
01327 /**
01328   * @}
01329   */
01330
01331 /**
01332   * @}
01333   */
01334
01335 /**
01336   * @}
01337   */
01338
01339 /**
01340   * @}
01341   */
01342
01343 #ifdef __cplusplus
01344 }
01345 #endif
01346
01347 #endif /* __STM32F7xx_HAL_RCC_H */
01348
01349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc_ex.c Source File

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stm32f7xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Extension RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities RCC extension peripheral:
00010   *           + Extended Peripheral Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f7xx_hal.h"
00044
00045 /** @addtogroup STM32F7xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup RCCEx RCCEx
00050   * @brief RCCEx HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_RCC_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @defgroup RCCEx_Private_Defines RCCEx Private Defines
00059   * @{
00060   */
00061
00062 #define PLLI2S_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
00063 #define PLLSAI_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
00064
00065 /**
00066   * @}
00067   */
00068 /* Private macro -------------------------------------------------------------*/
00069 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
00070  * @{
00071  */
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
00077  * @{
00078  */
00079
00080 /**
00081   * @}
00082   */
00083
00084
00085 /* Private variables ---------------------------------------------------------*/
00086 /* Private function prototypes -----------------------------------------------*/
00087 /* Private functions ---------------------------------------------------------*/
00088
00089 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00090   * @{
00091   */
00092
00093 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00094  *  @brief  Extended Peripheral Control functions
00095  *
00096 @verbatim
00097  ===============================================================================
00098                 ##### Extended Peripheral Control functions  #####
00099  ===============================================================================
00100     [..]
00101     This subsection provides a set of functions allowing to control the RCC Clocks
00102     frequencies.
00103     [..]
00104     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00105         select the RTC clock source; in this case the Backup domain will be reset in
00106         order to modify the RTC Clock source, as consequence RTC registers (including
00107         the backup registers) and RCC_BDCR register will be set to their reset values.
00108
00109 @endverbatim
00110   * @{
00111   */
00112 /**
00113   * @brief  Initializes the RCC extended peripherals clocks according to the specified
00114   *         parameters in the RCC_PeriphCLKInitTypeDef.
00115   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
00116   *         contains the configuration information for the Extended Peripherals
00117   *         clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
00118   *
00119   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00120   *         the RTC clock source; in this case the Backup domain will be reset in
00121   *         order to modify the RTC Clock source, as consequence RTC registers (including
00122   *         the backup registers) and RCC_BDCR register are set to their reset values.
00123   *
00124   * @retval HAL status
00125   */
00126 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00127 {
00128   uint32_t tickstart = 0;
00129   uint32_t tmpreg0 = 0;
00130   uint32_t tmpreg1 = 0;
00131   uint32_t plli2sused = 0;
00132   uint32_t pllsaiused = 0;
00133
00134   /* Check the parameters */
00135   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00136
00137   /*----------------------------------- I2S configuration ----------------------------------*/
00138   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
00139   {
00140     /* Check the parameters */
00141     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
00142
00143     /* Configure I2S Clock source */
00144     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
00145
00146     /* Enable the PLLI2S when it's used as clock source for I2S */
00147     if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
00148     {
00149       plli2sused = 1;
00150     }
00151   }
00152
00153   /*------------------------------------ SAI1 configuration --------------------------------------*/
00154   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
00155   {
00156     /* Check the parameters */
00157     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
00158
00159     /* Configure SAI1 Clock source */
00160     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00161     /* Enable the PLLI2S when it's used as clock source for SAI */
00162     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
00163     {
00164       plli2sused = 1;
00165     }
00166     /* Enable the PLLSAI when it's used as clock source for SAI */
00167     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
00168     {
00169       pllsaiused = 1;
00170     }
00171   }
00172
00173   /*------------------------------------ SAI2 configuration --------------------------------------*/
00174   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
00175   {
00176     /* Check the parameters */
00177     assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
00178
00179     /* Configure SAI2 Clock source */
00180     __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
00181
00182     /* Enable the PLLI2S when it's used as clock source for SAI */
00183     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
00184     {
00185       plli2sused = 1;
00186     }
00187     /* Enable the PLLSAI when it's used as clock source for SAI */
00188     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
00189     {
00190       pllsaiused = 1;
00191     }
00192   }
00193
00194   /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
00195   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
00196   {
00197       plli2sused = 1;
00198   }
00199
00200   /*------------------------------------ RTC configuration --------------------------------------*/
00201   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
00202   {
00203     /* Enable Power Clock*/
00204     __HAL_RCC_PWR_CLK_ENABLE();
00205
00206     /* Enable write access to Backup domain */
00207     PWR->CR1 |= PWR_CR1_DBP;
00208
00209     /* Get Start Tick*/
00210     tickstart = HAL_GetTick();
00211
00212     /* Wait for Backup domain Write protection disable */
00213     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
00214     {
00215       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00216       {
00217         return HAL_TIMEOUT;
00218       }
00219     }
00220     /* Reset the Backup domain only if the RTC Clock source selection is modified */
00221     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
00222     {
00223       /* Store the content of BDCR register before the reset of Backup Domain */
00224       tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
00225
00226       /* RTC Clock selection can be changed only if the Backup Domain is reset */
00227       __HAL_RCC_BACKUPRESET_FORCE();
00228       __HAL_RCC_BACKUPRESET_RELEASE();
00229
00230       /* Restore the Content of BDCR register */
00231       RCC->BDCR = tmpreg0;
00232
00233       /* If LSE is selected as RTC clock source, wait for LSE reactivation */
00234       if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
00235       {
00236         /* Get Start Tick*/
00237         tickstart = HAL_GetTick();
00238
00239         /* Wait till LSE is ready */
00240         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00241         {
00242           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00243           {
00244             return HAL_TIMEOUT;
00245           }
00246         }
00247       }
00248       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00249     }
00250   }
00251
00252   /*------------------------------------ TIM configuration --------------------------------------*/
00253   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
00254   {
00255     /* Check the parameters */
00256     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
00257
00258     /* Configure Timer Prescaler */
00259     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
00260   }
00261
00262   /*-------------------------------------- I2C1 Configuration -----------------------------------*/
00263   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
00264   {
00265     /* Check the parameters */
00266     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
00267
00268     /* Configure the I2C1 clock source */
00269     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
00270   }
00271
00272   /*-------------------------------------- I2C2 Configuration -----------------------------------*/
00273   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
00274   {
00275     /* Check the parameters */
00276     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
00277
00278     /* Configure the I2C2 clock source */
00279     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
00280   }
00281
00282   /*-------------------------------------- I2C3 Configuration -----------------------------------*/
00283   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
00284   {
00285     /* Check the parameters */
00286     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
00287
00288     /* Configure the I2C3 clock source */
00289     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
00290   }
00291
00292   /*-------------------------------------- I2C4 Configuration -----------------------------------*/
00293   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
00294   {
00295     /* Check the parameters */
00296     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
00297
00298     /* Configure the I2C4 clock source */
00299     __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
00300   }
00301
00302   /*-------------------------------------- USART1 Configuration -----------------------------------*/
00303   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
00304   {
00305     /* Check the parameters */
00306     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
00307
00308     /* Configure the USART1 clock source */
00309     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
00310   }
00311
00312   /*-------------------------------------- USART2 Configuration -----------------------------------*/
00313   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
00314   {
00315     /* Check the parameters */
00316     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
00317
00318     /* Configure the USART2 clock source */
00319     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
00320   }
00321
00322   /*-------------------------------------- USART3 Configuration -----------------------------------*/
00323   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
00324   {
00325     /* Check the parameters */
00326     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
00327
00328     /* Configure the USART3 clock source */
00329     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
00330   }
00331
00332   /*-------------------------------------- UART4 Configuration -----------------------------------*/
00333   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
00334   {
00335     /* Check the parameters */
00336     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
00337
00338     /* Configure the UART4 clock source */
00339     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
00340   }
00341
00342   /*-------------------------------------- UART5 Configuration -----------------------------------*/
00343   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
00344   {
00345     /* Check the parameters */
00346     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
00347
00348     /* Configure the UART5 clock source */
00349     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
00350   }
00351
00352   /*-------------------------------------- USART6 Configuration -----------------------------------*/
00353   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
00354   {
00355     /* Check the parameters */
00356     assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
00357
00358     /* Configure the USART6 clock source */
00359     __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
00360   }
00361
00362   /*-------------------------------------- UART7 Configuration -----------------------------------*/
00363   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
00364   {
00365     /* Check the parameters */
00366     assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
00367
00368     /* Configure the UART7 clock source */
00369     __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
00370   }
00371
00372   /*-------------------------------------- UART8 Configuration -----------------------------------*/
00373   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
00374   {
00375     /* Check the parameters */
00376     assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
00377
00378     /* Configure the UART8 clock source */
00379     __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
00380   }
00381
00382   /*--------------------------------------- CEC Configuration -----------------------------------*/
00383   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
00384   {
00385     /* Check the parameters */
00386     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
00387
00388     /* Configure the CEC clock source */
00389     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
00390   }
00391
00392   /*-------------------------------------- CK48 Configuration -----------------------------------*/
00393   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
00394   {
00395     /* Check the parameters */
00396     assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
00397
00398     /* Configure the CLK48 source */
00399     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
00400
00401     /* Enable the PLLSAI when it's used as clock source for CK48 */
00402     if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
00403     {
00404       pllsaiused = 1;
00405     }
00406   }
00407
00408   /*-------------------------------------- LTDC Configuration -----------------------------------*/
00409 #if defined(STM32F756xx) || defined(STM32F746xx)
00410   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
00411   {
00412     pllsaiused = 1;
00413   }
00414 #endif /* STM32F756xx || STM32F746xx */
00415   /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
00416   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
00417   {
00418     /* Check the parameters */
00419     assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
00420
00421     /* Configure the LTPIM1 clock source */
00422     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
00423    }
00424
00425   /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
00426   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
00427   {
00428     /* Check the parameters */
00429     assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
00430
00431     /* Configure the SDMMC1 clock source */
00432     __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
00433   }
00434
00435   /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
00436   /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
00437   if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
00438   {
00439     /* Disable the PLLI2S */
00440     __HAL_RCC_PLLI2S_DISABLE();
00441
00442     /* Get Start Tick*/
00443     tickstart = HAL_GetTick();
00444
00445     /* Wait till PLLI2S is disabled */
00446     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
00447     {
00448       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
00449       {
00450         /* return in case of Timeout detected */
00451         return HAL_TIMEOUT;
00452       }
00453     }
00454
00455     /* check for common PLLI2S Parameters */
00456     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
00457
00458     /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
00459     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
00460     {
00461       /* check for Parameters */
00462       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
00463
00464       /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
00465       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
00466       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
00467       /* Configure the PLLI2S division factors */
00468       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
00469       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
00470       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
00471     }
00472
00473     /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
00474     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
00475        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
00476     {
00477       /* Check for PLLI2S Parameters */
00478       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
00479       /* Check for PLLI2S/DIVQ parameters */
00480       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
00481
00482       /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
00483       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
00484       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00485       /* Configure the PLLI2S division factors */
00486       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
00487       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00488       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00489       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
00490
00491       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00492       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
00493     }
00494
00495     /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
00496     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
00497     {
00498       /* check for Parameters */
00499       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
00500
00501      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
00502       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
00503       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00504       /* Configure the PLLI2S division factors */
00505       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
00506       /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
00507       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
00508     }
00509
00510     /*----------------- In Case of PLLI2S is just selected  -----------------*/
00511     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
00512     {
00513       /* Check for Parameters */
00514       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
00515       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
00516       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
00517
00518       /* Configure the PLLI2S division factors */
00519       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
00520       /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
00521       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
00522     }
00523
00524     /* Enable the PLLI2S */
00525     __HAL_RCC_PLLI2S_ENABLE();
00526
00527     /* Get Start Tick*/
00528     tickstart = HAL_GetTick();
00529
00530     /* Wait till PLLI2S is ready */
00531     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
00532     {
00533       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
00534       {
00535         /* return in case of Timeout detected */
00536         return HAL_TIMEOUT;
00537       }
00538     }
00539   }
00540
00541   /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
00542   /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
00543   if(pllsaiused == 1)
00544   {
00545     /* Disable PLLSAI Clock */
00546     __HAL_RCC_PLLSAI_DISABLE();
00547
00548     /* Get Start Tick*/
00549     tickstart = HAL_GetTick();
00550
00551     /* Wait till PLLSAI is disabled */
00552     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
00553     {
00554       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
00555       {
00556         /* return in case of Timeout detected */
00557         return HAL_TIMEOUT;
00558       }
00559     }
00560
00561     /* Check the PLLSAI division factors */
00562     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
00563
00564     /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
00565     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
00566        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
00567     {
00568       /* check for PLLSAIQ Parameter */
00569       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
00570       /* check for PLLSAI/DIVQ Parameter */
00571       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
00572
00573       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
00574       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
00575       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
00576       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00577       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00578       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00579       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
00580
00581       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00582       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
00583     }
00584
00585     /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
00586     /* In Case of PLLI2S is selected as source clock for CK48 */
00587     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
00588     {
00589       /* check for Parameters */
00590       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
00591       /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
00592       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00593       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
00594
00595       /* Configure the PLLSAI division factors */
00596       /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
00597       /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
00598       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
00599     }
00600
00601 #if defined(STM32F756xx) || defined(STM32F746xx)
00602     /*---------------------------- LTDC configuration -------------------------------*/
00603     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
00604     {
00605       assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
00606       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
00607
00608       /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
00609       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00610       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
00611
00612       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00613       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00614       /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
00615       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
00616
00617       /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
00618       __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
00619     }
00620 #endif /* STM32F756xx || STM32F746xx */
00621
00622     /* Enable PLLSAI Clock */
00623     __HAL_RCC_PLLSAI_ENABLE();
00624
00625     /* Get Start Tick*/
00626     tickstart = HAL_GetTick();
00627
00628     /* Wait till PLLSAI is ready */
00629     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
00630     {
00631       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
00632       {
00633         /* return in case of Timeout detected */
00634         return HAL_TIMEOUT;
00635       }
00636     }
00637   }
00638   return HAL_OK;
00639 }
00640
00641 /**
00642   * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
00643   *         RCC configuration registers.
00644   * @param  PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
00645   * @retval None
00646   */
00647 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00648 {
00649   uint32_t tempreg = 0;
00650
00651   /* Set all possible values for the extended clock type parameter------------*/
00652   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
00653                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
00654                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
00655                                         RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
00656                                         RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
00657                                         RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
00658                                         RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
00659                                         RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
00660                                         RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
00661                                         RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
00662                                         RCC_PERIPHCLK_CLK48;
00663
00664
00665   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
00666   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
00667   PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
00668   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
00669   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00670
00671   /* Get the PLLSAI Clock configuration -----------------------------------------------*/
00672   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
00673   PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
00674   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00675   PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
00676
00677   /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
00678   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
00679   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
00680   PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
00681
00682   /* Get the SAI1 clock configuration ----------------------------------------------*/
00683   PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
00684
00685   /* Get the SAI2 clock configuration ----------------------------------------------*/
00686   PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
00687
00688   /* Get the I2S clock configuration ------------------------------------------*/
00689   PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
00690
00691   /* Get the I2C1 clock configuration ------------------------------------------*/
00692   PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
00693
00694   /* Get the I2C2 clock configuration ------------------------------------------*/
00695   PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
00696
00697   /* Get the I2C3 clock configuration ------------------------------------------*/
00698   PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
00699
00700   /* Get the I2C4 clock configuration ------------------------------------------*/
00701   PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
00702
00703   /* Get the USART1 clock configuration ------------------------------------------*/
00704   PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
00705
00706   /* Get the USART2 clock configuration ------------------------------------------*/
00707   PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
00708
00709   /* Get the USART3 clock configuration ------------------------------------------*/
00710   PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
00711
00712   /* Get the UART4 clock configuration ------------------------------------------*/
00713   PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
00714
00715   /* Get the UART5 clock configuration ------------------------------------------*/
00716   PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
00717
00718   /* Get the USART6 clock configuration ------------------------------------------*/
00719   PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
00720
00721   /* Get the UART7 clock configuration ------------------------------------------*/
00722   PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
00723
00724   /* Get the UART8 clock configuration ------------------------------------------*/
00725   PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
00726
00727   /* Get the LPTIM1 clock configuration ------------------------------------------*/
00728   PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
00729
00730   /* Get the CEC clock configuration -----------------------------------------------*/
00731   PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
00732
00733   /* Get the CK48 clock configuration -----------------------------------------------*/
00734   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
00735
00736   /* Get the SDMMC clock configuration -----------------------------------------------*/
00737   PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
00738
00739   /* Get the RTC Clock configuration -----------------------------------------------*/
00740   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
00741   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
00742
00743   /* Get the TIM Prescaler configuration --------------------------------------------*/
00744   if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
00745   {
00746     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
00747   }
00748   else
00749   {
00750     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
00751   }
00752 }
00753
00754 /**
00755   * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
00756   * @note   Return 0 if peripheral clock identifier not managed by this API
00757   * @param  PeriphClk: Peripheral clock identifier
00758   *         This parameter can be one of the following values:
00759   *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
00760   *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
00761   * @retval Frequency in KHz
00762   */
00763 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00764 {
00765   uint32_t tmpreg = 0;
00766   /* This variable is used to store the SAI clock frequency (value in Hz) */
00767   uint32_t frequency = 0;
00768   /* This variable is used to store the VCO Input (value in Hz) */
00769   uint32_t vcoinput = 0;
00770   /* This variable is used to store the SAI clock source */
00771   uint32_t saiclocksource = 0;
00772
00773   if (PeriphClk == RCC_PERIPHCLK_SAI1)
00774   {
00775     saiclocksource = RCC->DCKCFGR1;
00776     saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
00777     switch (saiclocksource)
00778     {
00779     case 0: /* PLLSAI is the clock source for SAI1 */
00780       {
00781         /* Configure the PLLSAI division factor */
00782         /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00783         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00784         {
00785           /* In Case the PLL Source is HSI (Internal Clock) */
00786           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
00787         }
00788         else
00789         {
00790           /* In Case the PLL Source is HSE (External Clock) */
00791           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
00792         }
00793         /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00794         /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00795         tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
00796         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
00797
00798         /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00799         tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
00800         frequency = frequency/(tmpreg);
00801         break;
00802       }
00803     case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
00804       {
00805         /* Configure the PLLI2S division factor */
00806         /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
00807         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00808         {
00809           /* In Case the PLL Source is HSI (Internal Clock) */
00810           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
00811         }
00812         else
00813         {
00814           /* In Case the PLL Source is HSE (External Clock) */
00815           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
00816         }
00817
00818         /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00819         /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00820         tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
00821         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
00822
00823         /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00824         tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
00825         frequency = frequency/(tmpreg);
00826         break;
00827       }
00828     case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
00829       {
00830         frequency = EXTERNAL_CLOCK_VALUE;
00831         break;
00832       }
00833     default :
00834       {
00835         break;
00836       }
00837     }
00838   }
00839
00840   if (PeriphClk == RCC_PERIPHCLK_SAI2)
00841   {
00842     saiclocksource = RCC->DCKCFGR1;
00843     saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
00844     switch (saiclocksource)
00845     {
00846     case 0: /* PLLSAI is the clock source for SAI*/
00847       {
00848         /* Configure the PLLSAI division factor */
00849         /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00850         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00851         {
00852           /* In Case the PLL Source is HSI (Internal Clock) */
00853           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
00854         }
00855         else
00856         {
00857           /* In Case the PLL Source is HSE (External Clock) */
00858           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
00859         }
00860         /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00861         /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00862         tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
00863         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
00864
00865         /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00866         tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
00867         frequency = frequency/(tmpreg);
00868         break;
00869       }
00870     case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
00871       {
00872         /* Configure the PLLI2S division factor */
00873         /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
00874         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00875         {
00876           /* In Case the PLL Source is HSI (Internal Clock) */
00877           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
00878         }
00879         else
00880         {
00881           /* In Case the PLL Source is HSE (External Clock) */
00882           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
00883         }
00884
00885         /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00886         /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00887         tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
00888         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
00889
00890         /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00891         tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
00892         frequency = frequency/(tmpreg);
00893         break;
00894       }
00895     case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
00896       {
00897         frequency = EXTERNAL_CLOCK_VALUE;
00898         break;
00899       }
00900     default :
00901       {
00902         break;
00903       }
00904     }
00905   }
00906
00907   return frequency;
00908 }
00909 /**
00910   * @}
00911   */
00912
00913 /**
00914   * @}
00915   */
00916
00917 #endif /* HAL_RCC_MODULE_ENABLED */
00918 /**
00919   * @}
00920   */
00921
00922 /**
00923   * @}
00924   */
00925
00926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rcc_ex.h Source File

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stm32f7xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of RCC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_RCC_EX_H
00040 #define __STM32F7xx_HAL_RCC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  PLLI2S Clock structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00068                             This parameter must be a number between Min_Data = 50 and Max_Data = 432.
00069                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00070
00071   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
00072                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
00073                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00074
00075   uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
00076                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00077                             This parameter will be used only when PLLI2S is selected as Clock Source SAI */
00078
00079   uint32_t PLLI2SP;    /*!< Specifies the division factor for SPDIF-RX clock.
00080                             This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
00081                             This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
00082 }RCC_PLLI2SInitTypeDef;
00083
00084 /**
00085   * @brief  PLLSAI Clock structure definition
00086   */
00087 typedef struct
00088 {
00089   uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00090                             This parameter must be a number between Min_Data = 50 and Max_Data = 432.
00091                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
00092
00093   uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
00094                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00095                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
00096
00097   uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
00098                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
00099                             This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
00100
00101   uint32_t PLLSAIP;    /*!< Specifies the division factor for 48MHz clock.
00102                             This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
00103                             This parameter will be used only when PLLSAI is disabled */
00104 }RCC_PLLSAIInitTypeDef;
00105
00106 /**
00107   * @brief  RCC extended clocks structure definition
00108   */
00109 typedef struct
00110 {
00111   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00112                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00113
00114   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
00115                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00116
00117   RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.
00118                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
00119
00120   uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
00121                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
00122                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI */
00123
00124   uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
00125                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
00126                                       This parameter will be used only when PLLSAI is selected as Clock Source SAI */
00127
00128   uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
00129                                       This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
00130
00131   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock source Selection.
00132                                         This parameter can be a value of @ref RCC_RTC_Clock_Source */
00133
00134   uint32_t I2sClockSelection;      /*!< Specifies I2S Clock source Selection.
00135                                         This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00136
00137   uint32_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection.
00138                                        This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
00139
00140   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 Clock Prescalers Selection
00141                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
00142
00143   uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 Clock Prescalers Selection
00144                                         This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
00145
00146   uint32_t Usart1ClockSelection; /*!< USART1 clock source
00147                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00148
00149   uint32_t Usart2ClockSelection; /*!< USART2 clock source
00150                                       This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
00151
00152   uint32_t Usart3ClockSelection; /*!< USART3 clock source
00153                                       This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
00154
00155   uint32_t Uart4ClockSelection;  /*!< UART4 clock source
00156                                       This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00157
00158   uint32_t Uart5ClockSelection;  /*!< UART5 clock source
00159                                       This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00160
00161   uint32_t Usart6ClockSelection;  /*!< USART6 clock source
00162                                       This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
00163
00164   uint32_t Uart7ClockSelection;  /*!< UART7 clock source
00165                                       This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
00166
00167   uint32_t Uart8ClockSelection;  /*!< UART8 clock source
00168                                       This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
00169
00170   uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
00171                                       This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
00172
00173   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
00174                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00175
00176   uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
00177                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00178
00179   uint32_t I2c4ClockSelection;   /*!< I2C4 clock source
00180                                       This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
00181
00182   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
00183                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00184
00185   uint32_t CecClockSelection;      /*!< CEC clock source
00186                                         This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
00187
00188   uint32_t Clk48ClockSelection;    /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
00189                                         This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
00190
00191   uint32_t Sdmmc1ClockSelection;     /*!< SDMMC1 clock source
00192                                         This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
00193 }RCC_PeriphCLKInitTypeDef;
00194 /**
00195   * @}
00196   */
00197
00198 /* Exported constants --------------------------------------------------------*/
00199 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00200   * @{
00201   */
00202
00203 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
00204   * @{
00205   */
00206 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001)
00207 #if defined(STM32F746xx) || defined(STM32F756xx)
00208 #define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008)
00209 #endif /* STM32F746xx || STM32F756xx */
00210 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010)
00211 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020)
00212 #define RCC_PERIPHCLK_USART1          ((uint32_t)0x00000040)
00213 #define RCC_PERIPHCLK_USART2          ((uint32_t)0x00000080)
00214 #define RCC_PERIPHCLK_USART3          ((uint32_t)0x00000100)
00215 #define RCC_PERIPHCLK_UART4           ((uint32_t)0x00000200)
00216 #define RCC_PERIPHCLK_UART5           ((uint32_t)0x00000400)
00217 #define RCC_PERIPHCLK_USART6          ((uint32_t)0x00000800)
00218 #define RCC_PERIPHCLK_UART7           ((uint32_t)0x00001000)
00219 #define RCC_PERIPHCLK_UART8           ((uint32_t)0x00002000)
00220 #define RCC_PERIPHCLK_I2C1            ((uint32_t)0x00004000)
00221 #define RCC_PERIPHCLK_I2C2            ((uint32_t)0x00008000)
00222 #define RCC_PERIPHCLK_I2C3            ((uint32_t)0x00010000)
00223 #define RCC_PERIPHCLK_I2C4            ((uint32_t)0x00020000)
00224 #define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00040000)
00225 #define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00080000)
00226 #define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00100000)
00227 #define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00200000)
00228 #define RCC_PERIPHCLK_CEC             ((uint32_t)0x00400000)
00229 #define RCC_PERIPHCLK_SDMMC1          ((uint32_t)0x00800000)
00230 #define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x01000000)
00231 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x02000000)
00232
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
00238   * @{
00239   */
00240 #define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000000)
00241 #define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000001)
00242 #define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000002)
00243 #define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000003)
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
00249   * @{
00250   */
00251 #define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000000)
00252 #define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000001)
00253 #define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000002)
00254 #define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000003)
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
00260   * @{
00261   */
00262 #define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000)
00263 #define RCC_PLLSAIDIVR_4                RCC_DCKCFGR1_PLLSAIDIVR_0
00264 #define RCC_PLLSAIDIVR_8                RCC_DCKCFGR1_PLLSAIDIVR_1
00265 #define RCC_PLLSAIDIVR_16               RCC_DCKCFGR1_PLLSAIDIVR
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
00271   * @{
00272   */
00273 #define RCC_I2SCLKSOURCE_PLLI2S             ((uint32_t)0x00000000)
00274 #define RCC_I2SCLKSOURCE_EXT                RCC_CFGR_I2SSRC
00275
00276 /**
00277   * @}
00278   */
00279
00280
00281 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
00282   * @{
00283   */
00284 #define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
00285 #define RCC_SAI1CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI1SEL_0
00286 #define RCC_SAI1CLKSOURCE_PIN                RCC_DCKCFGR1_SAI1SEL_1
00287
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
00293   * @{
00294   */
00295 #define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
00296 #define RCC_SAI2CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI2SEL_0
00297 #define RCC_SAI2CLKSOURCE_PIN                RCC_DCKCFGR1_SAI2SEL_1
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
00303   * @{
00304   */
00305 #define RCC_CECCLKSOURCE_LSE             ((uint32_t)0x00000000)
00306 #define RCC_CECCLKSOURCE_HSI             RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
00312   * @{
00313   */
00314 #define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000)
00315 #define RCC_USART1CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART1SEL_0
00316 #define RCC_USART1CLKSOURCE_HSI        RCC_DCKCFGR2_USART1SEL_1
00317 #define RCC_USART1CLKSOURCE_LSE        RCC_DCKCFGR2_USART1SEL
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
00323   * @{
00324   */
00325 #define RCC_USART2CLKSOURCE_PCLK1       ((uint32_t)0x00000000)
00326 #define RCC_USART2CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART2SEL_0
00327 #define RCC_USART2CLKSOURCE_HSI        RCC_DCKCFGR2_USART2SEL_1
00328 #define RCC_USART2CLKSOURCE_LSE        RCC_DCKCFGR2_USART2SEL
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
00334   * @{
00335   */
00336 #define RCC_USART3CLKSOURCE_PCLK1       ((uint32_t)0x00000000)
00337 #define RCC_USART3CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART3SEL_0
00338 #define RCC_USART3CLKSOURCE_HSI        RCC_DCKCFGR2_USART3SEL_1
00339 #define RCC_USART3CLKSOURCE_LSE        RCC_DCKCFGR2_USART3SEL
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
00345   * @{
00346   */
00347 #define RCC_UART4CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00348 #define RCC_UART4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART4SEL_0
00349 #define RCC_UART4CLKSOURCE_HSI          RCC_DCKCFGR2_UART4SEL_1
00350 #define RCC_UART4CLKSOURCE_LSE          RCC_DCKCFGR2_UART4SEL
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
00356   * @{
00357   */
00358 #define RCC_UART5CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00359 #define RCC_UART5CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART5SEL_0
00360 #define RCC_UART5CLKSOURCE_HSI          RCC_DCKCFGR2_UART5SEL_1
00361 #define RCC_UART5CLKSOURCE_LSE          RCC_DCKCFGR2_UART5SEL
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
00367   * @{
00368   */
00369 #define RCC_USART6CLKSOURCE_PCLK2       ((uint32_t)0x00000000)
00370 #define RCC_USART6CLKSOURCE_SYSCLK      RCC_DCKCFGR2_USART6SEL_0
00371 #define RCC_USART6CLKSOURCE_HSI         RCC_DCKCFGR2_USART6SEL_1
00372 #define RCC_USART6CLKSOURCE_LSE         RCC_DCKCFGR2_USART6SEL
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
00378   * @{
00379   */
00380 #define RCC_UART7CLKSOURCE_PCLK1       ((uint32_t)0x00000000)
00381 #define RCC_UART7CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART7SEL_0
00382 #define RCC_UART7CLKSOURCE_HSI         RCC_DCKCFGR2_UART7SEL_1
00383 #define RCC_UART7CLKSOURCE_LSE         RCC_DCKCFGR2_UART7SEL
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
00389   * @{
00390   */
00391 #define RCC_UART8CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00392 #define RCC_UART8CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART8SEL_0
00393 #define RCC_UART8CLKSOURCE_HSI         RCC_DCKCFGR2_UART8SEL_1
00394 #define RCC_UART8CLKSOURCE_LSE         RCC_DCKCFGR2_UART8SEL
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
00400   * @{
00401   */
00402 #define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00403 #define RCC_I2C1CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C1SEL_0
00404 #define RCC_I2C1CLKSOURCE_HSI          RCC_DCKCFGR2_I2C1SEL_1
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
00410   * @{
00411   */
00412 #define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00413 #define RCC_I2C2CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C2SEL_0
00414 #define RCC_I2C2CLKSOURCE_HSI          RCC_DCKCFGR2_I2C2SEL_1
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
00421   * @{
00422   */
00423 #define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00424 #define RCC_I2C3CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C3SEL_0
00425 #define RCC_I2C3CLKSOURCE_HSI          RCC_DCKCFGR2_I2C3SEL_1
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
00431   * @{
00432   */
00433 #define RCC_I2C4CLKSOURCE_PCLK1        ((uint32_t)0x00000000)
00434 #define RCC_I2C4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C4SEL_0
00435 #define RCC_I2C4CLKSOURCE_HSI          RCC_DCKCFGR2_I2C4SEL_1
00436 /**
00437   * @}
00438   */
00439
00440 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
00441   * @{
00442   */
00443 #define RCC_LPTIM1CLKSOURCE_PCLK       ((uint32_t)0x00000000)
00444 #define RCC_LPTIM1CLKSOURCE_LSI        RCC_DCKCFGR2_LPTIM1SEL_0
00445 #define RCC_LPTIM1CLKSOURCE_HSI        RCC_DCKCFGR2_LPTIM1SEL_1
00446 #define RCC_LPTIM1CLKSOURCE_LSE        RCC_DCKCFGR2_LPTIM1SEL
00447
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
00453   * @{
00454   */
00455 #define RCC_CLK48SOURCE_PLL         ((uint32_t)0x00000000)
00456 #define RCC_CLK48SOURCE_PLLSAIP     RCC_DCKCFGR2_CK48MSEL
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
00462   * @{
00463   */
00464 #define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000)
00465 #define RCC_TIMPRES_ACTIVATED           RCC_DCKCFGR1_TIMPRE
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
00471   * @{
00472   */
00473 #define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000)
00474 #define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /* Exported macro ------------------------------------------------------------*/
00484 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00485   * @{
00486   */
00487 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
00488   * @brief  Enables or disables the AHB/APB peripheral clock.
00489   * @note   After reset, the peripheral clock (used for registers read/write access)
00490   *         is disabled and the application software has to enable this clock before
00491   *         using it.
00492   * @{
00493   */
00494
00495 /** @brief  Enables or disables the AHB1 peripheral clock.
00496   * @note   After reset, the peripheral clock (used for registers read/write access)
00497   *         is disabled and the application software has to enable this clock before
00498   *         using it.
00499   */
00500 #define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \
00501                                       __IO uint32_t tmpreg = 0x00; \
00502                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
00503                                         /* Delay after an RCC peripheral clock enabling */ \
00504                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
00505                                         UNUSED(tmpreg); \
00506                                       } while(0)
00507
00508 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()   do { \
00509                                       __IO uint32_t tmpreg = 0x00; \
00510                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
00511                                         /* Delay after an RCC peripheral clock enabling */ \
00512                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
00513                                         UNUSED(tmpreg); \
00514                                       } while(0)
00515
00516 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
00517                                       __IO uint32_t tmpreg = 0x00; \
00518                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00519                                         /* Delay after an RCC peripheral clock enabling */ \
00520                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00521                                         UNUSED(tmpreg); \
00522                                       } while(0)
00523
00524 #define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
00525                                       __IO uint32_t tmpreg = 0x00; \
00526                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
00527                                         /* Delay after an RCC peripheral clock enabling */ \
00528                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
00529                                         UNUSED(tmpreg); \
00530                                       } while(0)
00531
00532 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
00533                                       __IO uint32_t tmpreg = 0x00; \
00534                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
00535                                         /* Delay after an RCC peripheral clock enabling */ \
00536                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
00537                                         UNUSED(tmpreg); \
00538                                       } while(0)
00539
00540 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
00541                                       __IO uint32_t tmpreg = 0x00; \
00542                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
00543                                         /* Delay after an RCC peripheral clock enabling */ \
00544                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
00545                                         UNUSED(tmpreg); \
00546                                       } while(0)
00547
00548 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
00549                                       __IO uint32_t tmpreg = 0x00; \
00550                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
00551                                         /* Delay after an RCC peripheral clock enabling */ \
00552                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
00553                                         UNUSED(tmpreg); \
00554                                       } while(0)
00555
00556 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
00557                                       __IO uint32_t tmpreg = 0x00; \
00558                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
00559                                         /* Delay after an RCC peripheral clock enabling */ \
00560                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
00561                                         UNUSED(tmpreg); \
00562                                       } while(0)
00563
00564 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
00565                                       __IO uint32_t tmpreg = 0x00; \
00566                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
00567                                         /* Delay after an RCC peripheral clock enabling */ \
00568                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
00569                                         UNUSED(tmpreg); \
00570                                       } while(0)
00571
00572 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
00573                                       __IO uint32_t tmpreg = 0x00; \
00574                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
00575                                         /* Delay after an RCC peripheral clock enabling */ \
00576                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
00577                                         UNUSED(tmpreg); \
00578                                       } while(0)
00579
00580 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
00581                                       __IO uint32_t tmpreg = 0x00; \
00582                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
00583                                         /* Delay after an RCC peripheral clock enabling */ \
00584                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
00585                                         UNUSED(tmpreg); \
00586                                       } while(0)
00587
00588 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
00589                                       __IO uint32_t tmpreg = 0x00; \
00590                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
00591                                         /* Delay after an RCC peripheral clock enabling */ \
00592                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
00593                                         UNUSED(tmpreg); \
00594                                       } while(0)
00595
00596 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
00597                                       __IO uint32_t tmpreg = 0x00; \
00598                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
00599                                         /* Delay after an RCC peripheral clock enabling */ \
00600                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
00601                                         UNUSED(tmpreg); \
00602                                       } while(0)
00603
00604 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
00605                                       __IO uint32_t tmpreg = 0x00; \
00606                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
00607                                         /* Delay after an RCC peripheral clock enabling */ \
00608                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
00609                                         UNUSED(tmpreg); \
00610                                       } while(0)
00611
00612 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
00613                                       __IO uint32_t tmpreg = 0x00; \
00614                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
00615                                         /* Delay after an RCC peripheral clock enabling */ \
00616                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
00617                                         UNUSED(tmpreg); \
00618                                       } while(0)
00619
00620 #define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
00621                                       __IO uint32_t tmpreg = 0x00; \
00622                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
00623                                         /* Delay after an RCC peripheral clock enabling */ \
00624                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
00625                                         UNUSED(tmpreg); \
00626                                       } while(0)
00627
00628 #define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
00629                                       __IO uint32_t tmpreg = 0x00; \
00630                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
00631                                         /* Delay after an RCC peripheral clock enabling */ \
00632                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
00633                                         UNUSED(tmpreg); \
00634                                       } while(0)
00635
00636 #define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
00637 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
00638 #define __HAL_RCC_DMA2_CLK_DISABLE()            (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
00639 #define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
00640 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
00641 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
00642 #define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
00643 #define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
00644 #define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
00645 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
00646 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
00647 #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
00648 #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
00649 #define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
00650 #define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
00651 #define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
00652 #define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
00653 /**
00654   * @brief  Enable ETHERNET clock.
00655   */
00656 #define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
00657                                       __IO uint32_t tmpreg = 0x00; \
00658                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
00659                                         /* Delay after an RCC peripheral clock enabling */ \
00660                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
00661                                         UNUSED(tmpreg); \
00662                                       } while(0)
00663
00664 #define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
00665                                       __IO uint32_t tmpreg = 0x00; \
00666                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
00667                                         /* Delay after an RCC peripheral clock enabling */ \
00668                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
00669                                         UNUSED(tmpreg); \
00670                                       } while(0)
00671
00672 #define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
00673                                       __IO uint32_t tmpreg = 0x00; \
00674                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
00675                                         /* Delay after an RCC peripheral clock enabling */ \
00676                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
00677                                         UNUSED(tmpreg); \
00678                                       } while(0)
00679
00680 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \
00681                                       __IO uint32_t tmpreg = 0x00; \
00682                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
00683                                         /* Delay after an RCC peripheral clock enabling */ \
00684                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
00685                                         UNUSED(tmpreg); \
00686                                       } while(0)
00687
00688 #define __HAL_RCC_ETH_CLK_ENABLE()       do {                            \
00689                                      __HAL_RCC_ETHMAC_CLK_ENABLE();      \
00690                                      __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
00691                                      __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
00692                                     } while(0)
00693 /**
00694   * @brief  Disable ETHERNET clock.
00695   */
00696 #define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
00697 #define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
00698 #define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
00699 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
00700 #define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
00701                                       __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
00702                                       __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
00703                                       __HAL_RCC_ETHMAC_CLK_DISABLE();      \
00704                                      } while(0)
00705
00706 /** @brief  Enable or disable the AHB2 peripheral clock.
00707   * @note   After reset, the peripheral clock (used for registers read/write access)
00708   *         is disabled and the application software has to enable this clock before
00709   *         using it.
00710   */
00711 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
00712                                       __IO uint32_t tmpreg = 0x00; \
00713                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
00714                                         /* Delay after an RCC peripheral clock enabling */ \
00715                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
00716                                         UNUSED(tmpreg); \
00717                                       } while(0)
00718
00719 #define __HAL_RCC_RNG_CLK_ENABLE()   do { \
00720                                       __IO uint32_t tmpreg = 0x00; \
00721                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
00722                                         /* Delay after an RCC peripheral clock enabling */ \
00723                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
00724                                         UNUSED(tmpreg); \
00725                                       } while(0)
00726
00727 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \
00728                                       __IO uint32_t tmpreg = 0x00; \
00729                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
00730                                         /* Delay after an RCC peripheral clock enabling */ \
00731                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
00732                                         UNUSED(tmpreg); \
00733                                         __HAL_RCC_SYSCFG_CLK_ENABLE();\
00734                                       } while(0)
00735
00736 #define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
00737 #define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
00738
00739 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
00740 #if defined(STM32F756xx)
00741 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
00742                                       __IO uint32_t tmpreg = 0x00; \
00743                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
00744                                         /* Delay after an RCC peripheral clock enabling */ \
00745                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
00746                                         UNUSED(tmpreg); \
00747                                       } while(0)
00748
00749 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
00750                                       __IO uint32_t tmpreg = 0x00; \
00751                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
00752                                         /* Delay after an RCC peripheral clock enabling */ \
00753                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
00754                                         UNUSED(tmpreg); \
00755                                       } while(0)
00756
00757 #define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
00758 #define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
00759 #endif /* STM32F756x */
00760
00761 /** @brief  Enables or disables the AHB3 peripheral clock.
00762   * @note   After reset, the peripheral clock (used for registers read/write access)
00763   *         is disabled and the application software has to enable this clock before
00764   *         using it.
00765   */
00766 #define __HAL_RCC_FMC_CLK_ENABLE()   do { \
00767                                       __IO uint32_t tmpreg = 0x00; \
00768                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
00769                                         /* Delay after an RCC peripheral clock enabling */ \
00770                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
00771                                         UNUSED(tmpreg); \
00772                                       } while(0)
00773
00774 #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
00775                                       __IO uint32_t tmpreg = 0x00; \
00776                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
00777                                         /* Delay after an RCC peripheral clock enabling */ \
00778                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
00779                                         UNUSED(tmpreg); \
00780                                       } while(0)
00781
00782 #define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
00783 #define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
00784
00785 /** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
00786   * @note   After reset, the peripheral clock (used for registers read/write access)
00787   *         is disabled and the application software has to enable this clock before
00788   *         using it.
00789   */
00790 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
00791                                       __IO uint32_t tmpreg = 0x00; \
00792                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
00793                                         /* Delay after an RCC peripheral clock enabling */ \
00794                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
00795                                         UNUSED(tmpreg); \
00796                                       } while(0)
00797
00798 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
00799                                       __IO uint32_t tmpreg = 0x00; \
00800                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
00801                                         /* Delay after an RCC peripheral clock enabling */ \
00802                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
00803                                         UNUSED(tmpreg); \
00804                                       } while(0)
00805
00806 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
00807                                       __IO uint32_t tmpreg = 0x00; \
00808                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
00809                                         /* Delay after an RCC peripheral clock enabling */ \
00810                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
00811                                         UNUSED(tmpreg); \
00812                                       } while(0)
00813
00814 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
00815                                       __IO uint32_t tmpreg = 0x00; \
00816                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00817                                         /* Delay after an RCC peripheral clock enabling */ \
00818                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00819                                         UNUSED(tmpreg); \
00820                                       } while(0)
00821
00822 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
00823                                       __IO uint32_t tmpreg = 0x00; \
00824                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00825                                         /* Delay after an RCC peripheral clock enabling */ \
00826                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00827                                         UNUSED(tmpreg); \
00828                                       } while(0)
00829
00830 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
00831                                       __IO uint32_t tmpreg = 0x00; \
00832                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
00833                                         /* Delay after an RCC peripheral clock enabling */ \
00834                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
00835                                         UNUSED(tmpreg); \
00836                                       } while(0)
00837
00838 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
00839                                       __IO uint32_t tmpreg = 0x00; \
00840                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
00841                                         /* Delay after an RCC peripheral clock enabling */ \
00842                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
00843                                         UNUSED(tmpreg); \
00844                                       } while(0)
00845
00846 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
00847                                       __IO uint32_t tmpreg = 0x00; \
00848                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
00849                                         /* Delay after an RCC peripheral clock enabling */ \
00850                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
00851                                         UNUSED(tmpreg); \
00852                                       } while(0)
00853
00854 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
00855                                       __IO uint32_t tmpreg = 0x00; \
00856                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
00857                                         /* Delay after an RCC peripheral clock enabling */ \
00858                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
00859                                         UNUSED(tmpreg); \
00860                                       } while(0)
00861
00862 #define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
00863                                       __IO uint32_t tmpreg = 0x00; \
00864                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
00865                                         /* Delay after an RCC peripheral clock enabling */ \
00866                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
00867                                         UNUSED(tmpreg); \
00868                                       } while(0)
00869
00870 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
00871                                       __IO uint32_t tmpreg = 0x00; \
00872                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
00873                                         /* Delay after an RCC peripheral clock enabling */ \
00874                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
00875                                         UNUSED(tmpreg); \
00876                                       } while(0)
00877
00878 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
00879                                       __IO uint32_t tmpreg = 0x00; \
00880                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
00881                                         /* Delay after an RCC peripheral clock enabling */ \
00882                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
00883                                         UNUSED(tmpreg); \
00884                                       } while(0)
00885
00886 #define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
00887                                       __IO uint32_t tmpreg = 0x00; \
00888                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
00889                                         /* Delay after an RCC peripheral clock enabling */ \
00890                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
00891                                         UNUSED(tmpreg); \
00892                                       } while(0)
00893
00894 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
00895                                       __IO uint32_t tmpreg = 0x00; \
00896                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00897                                         /* Delay after an RCC peripheral clock enabling */ \
00898                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00899                                         UNUSED(tmpreg); \
00900                                       } while(0)
00901
00902 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
00903                                       __IO uint32_t tmpreg = 0x00; \
00904                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
00905                                         /* Delay after an RCC peripheral clock enabling */ \
00906                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
00907                                         UNUSED(tmpreg); \
00908                                       } while(0)
00909
00910 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
00911                                       __IO uint32_t tmpreg = 0x00; \
00912                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
00913                                         /* Delay after an RCC peripheral clock enabling */ \
00914                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
00915                                         UNUSED(tmpreg); \
00916                                       } while(0)
00917
00918 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
00919                                       __IO uint32_t tmpreg = 0x00; \
00920                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
00921                                         /* Delay after an RCC peripheral clock enabling */ \
00922                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
00923                                         UNUSED(tmpreg); \
00924                                       } while(0)
00925
00926 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
00927                                       __IO uint32_t tmpreg = 0x00; \
00928                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00929                                         /* Delay after an RCC peripheral clock enabling */ \
00930                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00931                                         UNUSED(tmpreg); \
00932                                       } while(0)
00933
00934 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
00935                                       __IO uint32_t tmpreg = 0x00; \
00936                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
00937                                         /* Delay after an RCC peripheral clock enabling */ \
00938                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
00939                                         UNUSED(tmpreg); \
00940                                       } while(0)
00941
00942 #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
00943                                       __IO uint32_t tmpreg = 0x00; \
00944                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
00945                                         /* Delay after an RCC peripheral clock enabling */ \
00946                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
00947                                         UNUSED(tmpreg); \
00948                                       } while(0)
00949
00950 #define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
00951                                       __IO uint32_t tmpreg = 0x00; \
00952                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
00953                                         /* Delay after an RCC peripheral clock enabling */ \
00954                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
00955                                         UNUSED(tmpreg); \
00956                                       } while(0)
00957
00958 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
00959                                       __IO uint32_t tmpreg = 0x00; \
00960                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
00961                                         /* Delay after an RCC peripheral clock enabling */ \
00962                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
00963                                         UNUSED(tmpreg); \
00964                                       } while(0)
00965
00966 #define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
00967                                       __IO uint32_t tmpreg = 0x00; \
00968                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
00969                                         /* Delay after an RCC peripheral clock enabling */ \
00970                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
00971                                         UNUSED(tmpreg); \
00972                                       } while(0)
00973
00974 #define __HAL_RCC_CEC_CLK_ENABLE()   do { \
00975                                       __IO uint32_t tmpreg = 0x00; \
00976                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
00977                                         /* Delay after an RCC peripheral clock enabling */ \
00978                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
00979                                         UNUSED(tmpreg); \
00980                                       } while(0)
00981
00982 #define __HAL_RCC_DAC_CLK_ENABLE()   do { \
00983                                       __IO uint32_t tmpreg = 0x00; \
00984                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
00985                                         /* Delay after an RCC peripheral clock enabling */ \
00986                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
00987                                         UNUSED(tmpreg); \
00988                                       } while(0)
00989
00990 #define __HAL_RCC_UART7_CLK_ENABLE()   do { \
00991                                       __IO uint32_t tmpreg = 0x00; \
00992                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
00993                                         /* Delay after an RCC peripheral clock enabling */ \
00994                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
00995                                         UNUSED(tmpreg); \
00996                                       } while(0)
00997
00998 #define __HAL_RCC_UART8_CLK_ENABLE()   do { \
00999                                       __IO uint32_t tmpreg = 0x00; \
01000                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
01001                                         /* Delay after an RCC peripheral clock enabling */ \
01002                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
01003                                         UNUSED(tmpreg); \
01004                                       } while(0)
01005
01006 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
01007 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
01008 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
01009 #define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
01010 #define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
01011 #define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
01012 #define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
01013 #define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
01014 #define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
01015 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
01016 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
01017 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
01018 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
01019 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
01020 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
01021 #define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
01022 #define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
01023 #define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
01024 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
01025 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
01026 #define __HAL_RCC_I2C4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
01027 #define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
01028 #define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
01029 #define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
01030 #define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
01031 #define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
01032 #define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
01033
01034 /** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
01035   * @note   After reset, the peripheral clock (used for registers read/write access)
01036   *         is disabled and the application software has to enable this clock before
01037   *         using it.
01038   */
01039 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
01040                                       __IO uint32_t tmpreg = 0x00; \
01041                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
01042                                         /* Delay after an RCC peripheral clock enabling */ \
01043                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
01044                                         UNUSED(tmpreg); \
01045                                       } while(0)
01046
01047 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
01048                                       __IO uint32_t tmpreg = 0x00; \
01049                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01050                                         /* Delay after an RCC peripheral clock enabling */ \
01051                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01052                                         UNUSED(tmpreg); \
01053                                       } while(0)
01054
01055 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
01056                                       __IO uint32_t tmpreg = 0x00; \
01057                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
01058                                         /* Delay after an RCC peripheral clock enabling */ \
01059                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
01060                                         UNUSED(tmpreg); \
01061                                       } while(0)
01062
01063 #define __HAL_RCC_USART6_CLK_ENABLE()   do { \
01064                                       __IO uint32_t tmpreg = 0x00; \
01065                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
01066                                         /* Delay after an RCC peripheral clock enabling */ \
01067                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
01068                                         UNUSED(tmpreg); \
01069                                       } while(0)
01070
01071 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
01072                                       __IO uint32_t tmpreg = 0x00; \
01073                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
01074                                         /* Delay after an RCC peripheral clock enabling */ \
01075                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
01076                                         UNUSED(tmpreg); \
01077                                       } while(0)
01078
01079 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
01080                                       __IO uint32_t tmpreg = 0x00; \
01081                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
01082                                         /* Delay after an RCC peripheral clock enabling */ \
01083                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
01084                                         UNUSED(tmpreg); \
01085                                       } while(0)
01086
01087 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
01088                                       __IO uint32_t tmpreg = 0x00; \
01089                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
01090                                         /* Delay after an RCC peripheral clock enabling */ \
01091                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
01092                                         UNUSED(tmpreg); \
01093                                       } while(0)
01094
01095 #define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
01096                                       __IO uint32_t tmpreg = 0x00; \
01097                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
01098                                         /* Delay after an RCC peripheral clock enabling */ \
01099                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
01100                                         UNUSED(tmpreg); \
01101                                       } while(0)
01102
01103 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
01104                                       __IO uint32_t tmpreg = 0x00; \
01105                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
01106                                         /* Delay after an RCC peripheral clock enabling */ \
01107                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
01108                                         UNUSED(tmpreg); \
01109                                       } while(0)
01110
01111 #define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
01112                                       __IO uint32_t tmpreg = 0x00; \
01113                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
01114                                         /* Delay after an RCC peripheral clock enabling */ \
01115                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
01116                                         UNUSED(tmpreg); \
01117                                       } while(0)
01118
01119 #define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
01120                                       __IO uint32_t tmpreg = 0x00; \
01121                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
01122                                         /* Delay after an RCC peripheral clock enabling */ \
01123                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
01124                                         UNUSED(tmpreg); \
01125                                       } while(0)
01126
01127 #define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
01128                                       __IO uint32_t tmpreg = 0x00; \
01129                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
01130                                         /* Delay after an RCC peripheral clock enabling */ \
01131                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
01132                                         UNUSED(tmpreg); \
01133                                       } while(0)
01134
01135 #define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
01136                                       __IO uint32_t tmpreg = 0x00; \
01137                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
01138                                         /* Delay after an RCC peripheral clock enabling */ \
01139                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
01140                                         UNUSED(tmpreg); \
01141                                       } while(0)
01142
01143 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
01144                                       __IO uint32_t tmpreg = 0x00; \
01145                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
01146                                         /* Delay after an RCC peripheral clock enabling */ \
01147                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
01148                                         UNUSED(tmpreg); \
01149                                       } while(0)
01150
01151 #define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
01152                                       __IO uint32_t tmpreg = 0x00; \
01153                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
01154                                         /* Delay after an RCC peripheral clock enabling */ \
01155                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
01156                                         UNUSED(tmpreg); \
01157                                       } while(0)
01158
01159 #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
01160                                       __IO uint32_t tmpreg = 0x00; \
01161                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
01162                                         /* Delay after an RCC peripheral clock enabling */ \
01163                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
01164                                         UNUSED(tmpreg); \
01165                                       } while(0)
01166
01167 #define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
01168                                       __IO uint32_t tmpreg = 0x00; \
01169                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
01170                                         /* Delay after an RCC peripheral clock enabling */ \
01171                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
01172                                         UNUSED(tmpreg); \
01173                                       } while(0)
01174
01175 #if defined (STM32F746xx) || defined (STM32F756xx)
01176 #define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
01177                                       __IO uint32_t tmpreg = 0x00; \
01178                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
01179                                         /* Delay after an RCC peripheral clock enabling */ \
01180                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
01181                                         UNUSED(tmpreg); \
01182                                       } while(0)
01183 #endif /* STM32F746xx || STM32F756xx */
01184
01185 #define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
01186 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
01187 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
01188 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
01189 #define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
01190 #define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
01191 #define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
01192 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
01193 #define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
01194 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
01195 #define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
01196 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
01197 #define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
01198 #define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
01199 #define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
01200 #define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
01201 #define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
01202 #if defined (STM32F746xx) || defined (STM32F756xx)
01203 #define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
01204 #endif /* STM32F746xx || STM32F756xx */
01205 /**
01206   * @}
01207   */
01208
01209
01210 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
01211   * @brief  Get the enable or disable status of the AHB/APB peripheral clock.
01212   * @note   After reset, the peripheral clock (used for registers read/write access)
01213   *         is disabled and the application software has to enable this clock before
01214   *         using it.
01215   * @{
01216   */
01217
01218 /** @brief  Get the enable or disable status of the AHB1 peripheral clock.
01219   * @note   After reset, the peripheral clock (used for registers read/write access)
01220   *         is disabled and the application software has to enable this clock before
01221   *         using it.
01222   */
01223 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
01224 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
01225 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
01226 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
01227 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
01228 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
01229 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
01230 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
01231 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
01232 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
01233 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
01234 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
01235 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
01236 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
01237 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
01238 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
01239 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
01240
01241 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
01242 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
01243 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
01244 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
01245 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
01246 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
01247 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
01248 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
01249 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
01250 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
01251 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
01252 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
01253 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
01254 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
01255 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
01256 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
01257 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
01258 /**
01259   * @brief  Enable ETHERNET clock.
01260   */
01261 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
01262 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
01263 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
01264 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
01265 #define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
01266                                                __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
01267                                                                                            __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
01268
01269 /**
01270   * @brief  Disable ETHERNET clock.
01271   */
01272 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
01273 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
01274 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
01275 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
01276 #define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
01277                                                 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
01278                                                                                             __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
01279
01280 /** @brief  Get the enable or disable status of the AHB2 peripheral clock.
01281   * @note   After reset, the peripheral clock (used for registers read/write access)
01282   *         is disabled and the application software has to enable this clock before
01283   *         using it.
01284   */
01285 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
01286 #define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
01287 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
01288
01289 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
01290 #define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
01291 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
01292
01293 #if defined(STM32F756xx)
01294 #define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
01295 #define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
01296 #define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
01297 #define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
01298 #endif /* STM32F756xx */
01299
01300 /** @brief  Get the enable or disable status of the AHB3 peripheral clock.
01301   * @note   After reset, the peripheral clock (used for registers read/write access)
01302   *         is disabled and the application software has to enable this clock before
01303   *         using it.
01304   */
01305 #define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
01306 #define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
01307
01308 #define __HAL_RCC_FMC_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
01309 #define __HAL_RCC_QSPI_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
01310
01311 /** @brief  Get the enable or disable status of the APB1 peripheral clock.
01312   * @note   After reset, the peripheral clock (used for registers read/write access)
01313   *         is disabled and the application software has to enable this clock before
01314   *         using it.
01315   */
01316 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
01317 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
01318 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
01319 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
01320 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
01321 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
01322 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
01323 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
01324 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
01325 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
01326 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
01327 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
01328 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
01329 #define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
01330 #define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
01331 #define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
01332 #define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
01333 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
01334 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
01335 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
01336 #define __HAL_RCC_I2C4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
01337 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
01338 #define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
01339 #define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
01340 #define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
01341 #define __HAL_RCC_UART7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
01342 #define __HAL_RCC_UART8_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
01343
01344 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
01345 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
01346 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
01347 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
01348 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
01349 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
01350 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
01351 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
01352 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
01353 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
01354 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
01355 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
01356 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
01357 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
01358 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
01359 #define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
01360 #define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
01361 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
01362 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
01363 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
01364 #define __HAL_RCC_I2C4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
01365 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
01366 #define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
01367 #define __HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
01368 #define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
01369 #define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
01370 #define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
01371
01372 /** @brief  Get the enable or disable status of the APB2 peripheral clock.
01373   * @note   After reset, the peripheral clock (used for registers read/write access)
01374   *         is disabled and the application software has to enable this clock before
01375   *         using it.
01376   */
01377 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
01378 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
01379 #define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
01380 #define __HAL_RCC_USART6_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
01381 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
01382 #define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
01383 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
01384 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
01385 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
01386 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
01387 #define __HAL_RCC_TIM9_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
01388 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
01389 #define __HAL_RCC_TIM11_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
01390 #define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
01391 #define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
01392 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
01393 #define __HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
01394 #if defined (STM32F746xx) || defined (STM32F756xx)
01395 #define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
01396 #endif /* STM32F746xx || STM32F756xx */
01397 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
01398 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
01399 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
01400 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
01401 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
01402 #define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
01403 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
01404 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
01405 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
01406 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
01407 #define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
01408 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
01409 #define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
01410 #define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
01411 #define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
01412 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
01413 #define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
01414 #if defined (STM32F746xx) || defined (STM32F756xx)
01415 #define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
01416 #endif /* STM32F746xx || STM32F756xx */
01417 /**
01418   * @}
01419   */
01420
01421 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
01422   * @brief  Forces or releases AHB/APB peripheral reset.
01423   * @{
01424   */
01425
01426 /** @brief  Force or release AHB1 peripheral reset.
01427   */
01428 #define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
01429 #define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
01430 #define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
01431 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
01432 #define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
01433 #define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
01434 #define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
01435 #define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
01436 #define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
01437 #define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
01438 #define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
01439 #define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
01440 #define __HAL_RCC_GPIOI_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
01441 #define __HAL_RCC_GPIOJ_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
01442 #define __HAL_RCC_GPIOK_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
01443
01444 #define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
01445 #define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
01446 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
01447 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
01448 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
01449 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
01450 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
01451 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
01452 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
01453 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
01454 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
01455 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
01456 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
01457 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
01458 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
01459
01460 /** @brief  Force or release AHB2 peripheral reset.
01461   */
01462 #define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFF)
01463 #define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
01464 #define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
01465 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
01466
01467 #define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00)
01468 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
01469 #define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
01470 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
01471
01472 #if defined(STM32F756xx)
01473 #define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
01474 #define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
01475 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
01476 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
01477 #endif /* STM32F756xx */
01478
01479 /** @brief  Force or release AHB3 peripheral reset
01480   */
01481 #define __HAL_RCC_AHB3_FORCE_RESET()   (RCC->AHB3RSTR = 0xFFFFFFFF)
01482 #define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
01483 #define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
01484
01485 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
01486 #define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
01487 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
01488
01489 /** @brief  Force or release APB1 peripheral reset.
01490   */
01491 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
01492 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
01493 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
01494 #define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
01495 #define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
01496 #define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
01497 #define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
01498 #define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
01499 #define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
01500 #define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
01501 #define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
01502 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
01503 #define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
01504 #define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
01505 #define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
01506 #define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
01507 #define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
01508 #define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
01509 #define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
01510 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
01511 #define __HAL_RCC_I2C4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
01512 #define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
01513 #define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
01514 #define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
01515 #define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
01516 #define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
01517 #define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
01518
01519 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
01520 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
01521 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
01522 #define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
01523 #define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
01524 #define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
01525 #define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
01526 #define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
01527 #define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
01528 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
01529 #define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
01530 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
01531 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
01532 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
01533 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
01534 #define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
01535 #define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
01536 #define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
01537 #define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
01538 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
01539 #define __HAL_RCC_I2C4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
01540 #define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
01541 #define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
01542 #define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
01543 #define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
01544 #define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
01545 #define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
01546
01547 /** @brief  Force or release APB2 peripheral reset.
01548   */
01549 #define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
01550 #define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
01551 #define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
01552 #define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
01553 #define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
01554 #define __HAL_RCC_SDMMC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
01555 #define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
01556 #define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
01557 #define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
01558 #define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
01559 #define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
01560 #define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
01561 #define __HAL_RCC_SPI6_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
01562 #define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
01563 #define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
01564 #if defined (STM32F746xx) || defined (STM32F756xx)
01565 #define __HAL_RCC_LTDC_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
01566 #endif /* STM32F746xx || STM32F756xx */
01567
01568 #define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
01569 #define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
01570 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
01571 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
01572 #define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
01573 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
01574 #define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
01575 #define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
01576 #define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
01577 #define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
01578 #define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
01579 #define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
01580 #define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
01581 #define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
01582 #define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
01583 #if defined (STM32F746xx) || defined (STM32F756xx)
01584 #define __HAL_RCC_LTDC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
01585 #endif /* STM32F746xx || STM32F756xx */
01586
01587 /**
01588   * @}
01589   */
01590
01591 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
01592   * @brief  Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
01593   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01594   *         power consumption.
01595   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01596   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01597   * @{
01598   */
01599
01600 /** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
01601   */
01602 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
01603 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
01604 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
01605 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
01606 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
01607 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
01608 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
01609 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
01610 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
01611 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
01612 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
01613 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
01614 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
01615 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
01616 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
01617 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
01618 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
01619 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
01620 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
01621 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
01622 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
01623 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
01624 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
01625 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
01626 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
01627
01628 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
01629 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
01630 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
01631 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
01632 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
01633 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
01634 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
01635 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
01636 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
01637 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
01638 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
01639 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
01640 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
01641 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
01642 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
01643 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
01644 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
01645 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
01646 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
01647 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
01648 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
01649 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
01650 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
01651 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
01652 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
01653
01654 /** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
01655   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01656   *         power consumption.
01657   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01658   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01659   */
01660 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
01661 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
01662
01663 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
01664 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
01665
01666 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
01667 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
01668
01669 #if defined(STM32F756xx)
01670 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
01671 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
01672
01673 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
01674 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
01675 #endif /* STM32F756xx */
01676
01677 /** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
01678   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01679   *         power consumption.
01680   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01681   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01682   */
01683 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
01684 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
01685
01686 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
01687 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
01688
01689 /** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
01690   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01691   *         power consumption.
01692   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01693   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01694   */
01695 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
01696 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
01697 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
01698 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
01699 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
01700 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
01701 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
01702 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
01703 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
01704 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
01705 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
01706 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
01707 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
01708 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
01709 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
01710 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
01711 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
01712 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
01713 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
01714 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
01715 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
01716 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
01717 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
01718 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
01719 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
01720 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
01721 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
01722
01723 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
01724 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
01725 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
01726 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
01727 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
01728 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
01729 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
01730 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
01731 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
01732 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
01733 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
01734 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
01735 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
01736 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
01737 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
01738 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
01739 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
01740 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
01741 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
01742 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
01743 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
01744 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
01745 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
01746 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
01747 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
01748 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
01749 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
01750
01751 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
01752   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01753   *         power consumption.
01754   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01755   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01756   */
01757 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
01758 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
01759 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
01760 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
01761 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
01762 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
01763 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
01764 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
01765 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
01766 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
01767 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
01768 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
01769 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
01770 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
01771 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
01772 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
01773 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
01774 #if defined (STM32F746xx) || defined (STM32F756xx)
01775 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
01776 #endif /* STM32F746xx || STM32F756xx */
01777
01778 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
01779 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
01780 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
01781 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
01782 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
01783 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
01784 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
01785 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
01786 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
01787 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
01788 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
01789 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
01790 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
01791 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
01792 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
01793 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
01794 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
01795 #if defined (STM32F746xx) || defined (STM32F756xx)
01796 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
01797 #endif /* STM32F746xx || STM32F756xx */
01798
01799 /**
01800   * @}
01801   */
01802
01803 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
01804   * @brief  Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
01805   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01806   *         power consumption.
01807   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01808   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01809   * @{
01810   */
01811
01812 /** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
01813   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01814   *         power consumption.
01815   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01816   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01817   */
01818 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
01819 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
01820 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
01821 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
01822 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
01823 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
01824 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
01825 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
01826 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
01827 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
01828 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
01829 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
01830 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
01831 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
01832 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
01833 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
01834 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
01835 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
01836 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
01837 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
01838 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
01839 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
01840 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
01841 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
01842 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
01843
01844 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
01845 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
01846 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
01847 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
01848 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
01849 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
01850 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
01851 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
01852 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
01853 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
01854 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
01855 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
01856 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
01857 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
01858 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
01859 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
01860 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
01861 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
01862 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
01863 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
01864 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
01865 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
01866 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
01867 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
01868 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
01869
01870 /** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
01871   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01872   *         power consumption.
01873   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01874   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01875   */
01876 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
01877 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
01878
01879 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
01880 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
01881
01882 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
01883 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
01884
01885 #if defined(STM32F756xx)
01886 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
01887 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
01888
01889 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
01890 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
01891 #endif /* STM32F756xx */
01892
01893 /** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
01894   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01895   *         power consumption.
01896   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01897   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01898   */
01899 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
01900 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
01901
01902 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
01903 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
01904
01905 /** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
01906   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01907   *         power consumption.
01908   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01909   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01910   */
01911 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
01912 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
01913 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
01914 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
01915 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
01916 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
01917 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
01918 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
01919 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
01920 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
01921 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
01922 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
01923 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
01924 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
01925 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
01926 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
01927 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
01928 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
01929 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
01930 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
01931 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
01932 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
01933 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
01934 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
01935 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
01936 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
01937 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
01938
01939 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
01940 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
01941 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
01942 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
01943 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
01944 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
01945 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
01946 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
01947 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
01948 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
01949 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
01950 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
01951 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
01952 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
01953 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
01954 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
01955 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
01956 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
01957 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
01958 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
01959 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
01960 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
01961 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
01962 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
01963 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
01964 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
01965 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
01966
01967 /** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
01968   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01969   *         power consumption.
01970   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01971   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01972   */
01973 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
01974 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
01975 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
01976 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
01977 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
01978 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
01979 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
01980 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
01981 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
01982 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
01983 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
01984 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
01985 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
01986 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
01987 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
01988 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
01989 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
01990 #if defined (STM32F746xx) || defined (STM32F756xx)
01991 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
01992 #endif /* STM32F746xx || STM32F756xx */
01993
01994 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
01995 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
01996 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
01997 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
01998 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
01999 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
02000 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
02001 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
02002 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
02003 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
02004 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
02005 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
02006 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
02007 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
02008 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
02009 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
02010 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
02011 #if defined (STM32F746xx) || defined (STM32F756xx)
02012 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
02013 #endif /* STM32F746xx || STM32F756xx */
02014
02015 /**
02016   * @}
02017   */
02018
02019 /*---------------------------------------------------------------------------------------------*/
02020
02021 /** @brief  Macro to configure the Timers clocks prescalers
02022   * @param  __PRESC__ : specifies the Timers clocks prescalers selection
02023   *         This parameter can be one of the following values:
02024   *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
02025   *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,
02026   *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
02027   *                 division by 4 or more.
02028   *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
02029   *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
02030   *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
02031   *                 to division by 8 or more.
02032   */
02033 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
02034                                                  RCC->DCKCFGR1 |= (__PRESC__);           \
02035                                                 }while(0)
02036
02037 /** @brief Macros to Enable or Disable the PLLISAI.
02038   * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
02039   */
02040 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
02041 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
02042
02043 /** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
02044   * @note   This function must be used only when the PLLSAI is disabled.
02045   * @note   PLLSAI clock source is common with the main PLL (configured in
02046   *         RCC_PLLConfig function )
02047   * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
02048   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
02049   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
02050   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
02051   * @param  __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
02052   *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
02053   * @param  __PLLSAIQ__: specifies the division factor for SAI clock
02054   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
02055   * @param  __PLLSAIR__: specifies the division factor for LTDC clock
02056   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
02057   */
02058 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)                        \
02059                                (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
02060                                ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP))                    |\
02061                                ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                    |\
02062                                ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
02063
02064 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors.
02065   * @note   This macro must be used only when the PLLI2S is disabled.
02066   * @note   PLLI2S clock source is common with the main PLL (configured in
02067   *         HAL_RCC_ClockConfig() API)
02068   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
02069   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
02070   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
02071   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
02072   * @param  __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
02073   *         This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
02074   * @param  __PLLI2SQ__: specifies the division factor for SAI clock.
02075   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
02076   * @param  __PLLI2SR__: specifies the division factor for I2S clock
02077   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
02078   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
02079   *         on the I2S clock frequency.
02080   */
02081 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)                        \
02082                                (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
02083                                ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP))                    |\
02084                                ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))                    |\
02085                                ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
02086
02087 /** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
02088   * @note   This function must be called before enabling the PLLI2S.
02089   * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
02090   *          This parameter must be a number between 1 and 32.
02091   *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
02092   */
02093 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
02094
02095 /** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
02096   * @note   This function must be called before enabling the PLLSAI.
02097   * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
02098   *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
02099   *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
02100   */
02101 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
02102
02103 /** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
02104   *
02105   * @note   This function must be called before enabling the PLLSAI.
02106   * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
02107   *          This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
02108   *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
02109   */
02110 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
02111                             MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
02112
02113 /** @brief  Macro to configure SAI1 clock source selection.
02114   * @note   This function must be called before enabling PLLSAI, PLLI2S and
02115   *         the SAI clock.
02116   * @param  __SOURCE__: specifies the SAI1 clock source.
02117   *         This parameter can be one of the following values:
02118   *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
02119   *                                           as SAI1 clock.
02120   *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
02121   *                                           as SAI1 clock.
02122   *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
02123   *                                        used as SAI1 clock.
02124   */
02125 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
02126                              MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
02127
02128 /** @brief  Macro to get the SAI1 clock source.
02129   * @retval The clock source can be one of the following values:
02130   *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
02131   *                                           as SAI1 clock.
02132   *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
02133   *                                           as SAI1 clock.
02134   *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
02135   *                                        used as SAI1 clock.
02136   */
02137 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
02138
02139
02140 /** @brief  Macro to configure SAI2 clock source selection.
02141   * @note   This function must be called before enabling PLLSAI, PLLI2S and
02142   *         the SAI clock.
02143   * @param  __SOURCE__: specifies the SAI2 clock source.
02144   *         This parameter can be one of the following values:
02145   *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
02146   *                                           as SAI2 clock.
02147   *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
02148   *                                           as SAI2 clock.
02149   *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
02150   *                                        used as SAI2 clock.
02151   */
02152 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
02153                             MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
02154
02155
02156 /** @brief  Macro to get the SAI2 clock source.
02157   * @retval The clock source can be one of the following values:
02158   *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
02159   *                                           as SAI2 clock.
02160   *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
02161   *                                           as SAI2 clock.
02162   *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
02163   *                                        used as SAI2 clock.
02164   */
02165 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
02166
02167
02168 /** @brief Enable PLLSAI_RDY interrupt.
02169   */
02170 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
02171
02172 /** @brief Disable PLLSAI_RDY interrupt.
02173   */
02174 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
02175
02176 /** @brief Clear the PLLSAI RDY interrupt pending bits.
02177   */
02178 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
02179
02180 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
02181   * @retval The new state (TRUE or FALSE).
02182   */
02183 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
02184
02185 /** @brief  Check PLLSAI RDY flag is set or not.
02186   * @retval The new state (TRUE or FALSE).
02187   */
02188 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
02189
02190 /** @brief  Macro to Get I2S clock source selection.
02191   * @retval The clock source can be one of the following values:
02192   *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
02193   *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
02194   */
02195 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
02196
02197 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
02198   *
02199   * @param  __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
02200   *          This parameter can be one of the following values:
02201   *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
02202   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
02203   *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
02204   */
02205 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
02206                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
02207
02208 /** @brief  Macro to get the I2C1 clock source.
02209   * @retval The clock source can be one of the following values:
02210   *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
02211   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
02212   *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
02213   */
02214 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
02215
02216 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
02217   *
02218   * @param  __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
02219   *          This parameter can be one of the following values:
02220   *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
02221   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
02222   *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
02223   */
02224 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
02225                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
02226
02227 /** @brief  Macro to get the I2C2 clock source.
02228   * @retval The clock source can be one of the following values:
02229   *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
02230   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
02231   *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
02232   */
02233 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
02234
02235 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
02236   *
02237   * @param  __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
02238   *          This parameter can be one of the following values:
02239   *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
02240   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
02241   *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
02242   */
02243 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
02244                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
02245
02246 /** @brief  macro to get the I2C3 clock source.
02247   * @retval The clock source can be one of the following values:
02248   *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
02249   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
02250   *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
02251   */
02252 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
02253
02254 /** @brief  Macro to configure the I2C4 clock (I2C4CLK).
02255   *
02256   * @param  __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
02257   *          This parameter can be one of the following values:
02258   *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
02259   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
02260   *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
02261   */
02262 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
02263                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
02264
02265 /** @brief  macro to get the I2C4 clock source.
02266   * @retval The clock source can be one of the following values:
02267   *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
02268   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
02269   *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
02270   */
02271 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
02272
02273 /** @brief  Macro to configure the USART1 clock (USART1CLK).
02274   *
02275   * @param  __USART1_CLKSOURCE__: specifies the USART1 clock source.
02276   *          This parameter can be one of the following values:
02277   *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
02278   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
02279   *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
02280   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
02281   */
02282 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
02283                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
02284
02285 /** @brief  macro to get the USART1 clock source.
02286   * @retval The clock source can be one of the following values:
02287   *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
02288   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
02289   *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
02290   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
02291   */
02292 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
02293
02294 /** @brief  Macro to configure the USART2 clock (USART2CLK).
02295   *
02296   * @param  __USART2_CLKSOURCE__: specifies the USART2 clock source.
02297   *          This parameter can be one of the following values:
02298   *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
02299   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
02300   *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
02301   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
02302   */
02303 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
02304                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
02305
02306 /** @brief  macro to get the USART2 clock source.
02307   * @retval The clock source can be one of the following values:
02308   *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
02309   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
02310   *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
02311   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
02312   */
02313 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
02314
02315 /** @brief  Macro to configure the USART3 clock (USART3CLK).
02316   *
02317   * @param  __USART3_CLKSOURCE__: specifies the USART3 clock source.
02318   *          This parameter can be one of the following values:
02319   *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
02320   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
02321   *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
02322   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
02323   */
02324 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
02325                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
02326
02327 /** @brief  macro to get the USART3 clock source.
02328   * @retval The clock source can be one of the following values:
02329   *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
02330   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
02331   *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
02332   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
02333   */
02334 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
02335
02336  /** @brief  Macro to configure the UART4 clock (UART4CLK).
02337   *
02338   * @param  __UART4_CLKSOURCE__: specifies the UART4 clock source.
02339   *          This parameter can be one of the following values:
02340   *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
02341   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
02342   *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
02343   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
02344   */
02345 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
02346                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
02347
02348 /** @brief  macro to get the UART4 clock source.
02349   * @retval The clock source can be one of the following values:
02350   *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
02351   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
02352   *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
02353   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
02354   */
02355 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
02356
02357  /** @brief  Macro to configure the UART5 clock (UART5CLK).
02358   *
02359   * @param  __UART5_CLKSOURCE__: specifies the UART5 clock source.
02360   *          This parameter can be one of the following values:
02361   *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
02362   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
02363   *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
02364   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
02365   */
02366 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
02367                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
02368
02369 /** @brief  macro to get the UART5 clock source.
02370   * @retval The clock source can be one of the following values:
02371   *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
02372   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
02373   *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
02374   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
02375   */
02376 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
02377
02378  /** @brief  Macro to configure the USART6 clock (USART6CLK).
02379   *
02380   * @param  __USART6_CLKSOURCE__: specifies the USART6 clock source.
02381   *          This parameter can be one of the following values:
02382   *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
02383   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
02384   *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
02385   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
02386   */
02387 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
02388                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
02389
02390 /** @brief  macro to get the USART6 clock source.
02391   * @retval The clock source can be one of the following values:
02392   *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
02393   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
02394   *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
02395   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
02396   */
02397 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
02398
02399  /** @brief  Macro to configure the UART7 clock (UART7CLK).
02400   *
02401   * @param  __UART7_CLKSOURCE__: specifies the UART7 clock source.
02402   *          This parameter can be one of the following values:
02403   *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
02404   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
02405   *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
02406   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
02407   */
02408 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
02409                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
02410
02411 /** @brief  macro to get the UART7 clock source.
02412   * @retval The clock source can be one of the following values:
02413   *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
02414   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
02415   *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
02416   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
02417   */
02418 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
02419
02420 /** @brief  Macro to configure the UART8 clock (UART8CLK).
02421   *
02422   * @param  __UART8_CLKSOURCE__: specifies the UART8 clock source.
02423   *          This parameter can be one of the following values:
02424   *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
02425   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
02426   *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
02427   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
02428   */
02429 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
02430                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
02431
02432 /** @brief  macro to get the UART8 clock source.
02433   * @retval The clock source can be one of the following values:
02434   *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
02435   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
02436   *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
02437   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
02438   */
02439 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
02440
02441 /** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
02442   *
02443   * @param  __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
02444   *          This parameter can be one of the following values:
02445   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
02446   *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
02447   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
02448   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
02449   */
02450 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
02451                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
02452
02453 /** @brief  macro to get the LPTIM1 clock source.
02454   * @retval The clock source can be one of the following values:
02455   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
02456   *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
02457   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
02458   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
02459   */
02460 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
02461
02462 /** @brief  Macro to configure the CEC clock (CECCLK).
02463   *
02464   * @param  __CEC_CLKSOURCE__: specifies the CEC clock source.
02465   *          This parameter can be one of the following values:
02466   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
02467   *            @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
02468   */
02469 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
02470                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
02471
02472 /** @brief  macro to get the CEC clock source.
02473   * @retval The clock source can be one of the following values:
02474   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
02475   *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
02476   */
02477 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
02478
02479 /** @brief  Macro to configure the CLK48 source (CLK48CLK).
02480   *
02481   * @param  __CLK48_SOURCE__: specifies the CLK48 clock source.
02482   *          This parameter can be one of the following values:
02483   *            @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
02484   *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
02485   */
02486 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
02487                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
02488
02489 /** @brief  macro to get the CLK48 source.
02490   * @retval The clock source can be one of the following values:
02491   *            @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
02492   *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
02493   */
02494 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
02495
02496 /** @brief  Macro to configure the SDMMC1 clock (SDMMC1CLK).
02497   *
02498   * @param  __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
02499   *          This parameter can be one of the following values:
02500   *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
02501   *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
02502   */
02503 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
02504                   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
02505
02506 /** @brief  macro to get the SDMMC1 clock source.
02507   * @retval The clock source can be one of the following values:
02508   *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
02509   *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
02510   */
02511 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
02512
02513 /**
02514   * @}
02515   */
02516
02517 /* Exported functions --------------------------------------------------------*/
02518 /** @addtogroup RCCEx_Exported_Functions_Group1
02519   * @{
02520   */
02521 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
02522 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
02523 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
02524
02525 /**
02526   * @}
02527   */
02528 /* Private macros ------------------------------------------------------------*/
02529 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
02530   * @{
02531   */
02532 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
02533   * @{
02534   */
02535 #if defined(STM32F756xx) || defined(STM32F746xx)
02536 #define IS_RCC_PERIPHCLOCK(SELECTION)  \
02537                ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
02538                 (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \
02539                 (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
02540                 (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
02541                 (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
02542                 (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
02543                 (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
02544                 (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
02545                 (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
02546                 (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
02547                 (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
02548                 (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
02549                 (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
02550                 (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
02551                 (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
02552                 (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
02553                 (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
02554                 (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
02555                 (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
02556                 (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
02557                 (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
02558                 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
02559                 (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
02560 #elif defined(STM32F745xx)
02561 #define IS_RCC_PERIPHCLOCK(SELECTION)  \
02562                ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
02563                 (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
02564                 (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
02565                 (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
02566                 (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
02567                 (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
02568                 (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
02569                 (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
02570                 (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
02571                 (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
02572                 (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
02573                 (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
02574                 (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
02575                 (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
02576                 (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
02577                 (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
02578                 (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
02579                 (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
02580                 (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
02581                 (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
02582                 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
02583                 (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
02584 #endif /* STM32F746xx || STM32F756xx */
02585 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
02586 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
02587                                      ((VALUE) == RCC_PLLI2SP_DIV4) ||\
02588                                      ((VALUE) == RCC_PLLI2SP_DIV6) ||\
02589                                      ((VALUE) == RCC_PLLI2SP_DIV8))
02590 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
02591 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
02592
02593 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
02594 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
02595                                      ((VALUE) == RCC_PLLSAIP_DIV4) ||\
02596                                      ((VALUE) == RCC_PLLSAIP_DIV6) ||\
02597                                      ((VALUE) == RCC_PLLSAIP_DIV8))
02598 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
02599 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
02600
02601 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
02602
02603 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
02604
02605 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
02606                                          ((VALUE) == RCC_PLLSAIDIVR_4) ||\
02607                                          ((VALUE) == RCC_PLLSAIDIVR_8) ||\
02608                                          ((VALUE) == RCC_PLLSAIDIVR_16))
02609 #define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
02610                                       ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
02611
02612 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
02613                                         ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
02614
02615 #define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
02616                                       ((SOURCE) == RCC_CECCLKSOURCE_LSE))
02617 #define IS_RCC_USART1CLKSOURCE(SOURCE)  \
02618                (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
02619                 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
02620                 ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
02621                 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
02622
02623 #define IS_RCC_USART2CLKSOURCE(SOURCE)  \
02624                (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1)  || \
02625                 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
02626                 ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
02627                 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
02628 #define IS_RCC_USART3CLKSOURCE(SOURCE)  \
02629                (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1)  || \
02630                 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
02631                 ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
02632                 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
02633
02634 #define IS_RCC_UART4CLKSOURCE(SOURCE)  \
02635                (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \
02636                 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
02637                 ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
02638                 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
02639
02640 #define IS_RCC_UART5CLKSOURCE(SOURCE)  \
02641                (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \
02642                 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
02643                 ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
02644                 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
02645
02646 #define IS_RCC_USART6CLKSOURCE(SOURCE)  \
02647                (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2)  || \
02648                 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
02649                 ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
02650                 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
02651
02652 #define IS_RCC_UART7CLKSOURCE(SOURCE)  \
02653                (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1)  || \
02654                 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
02655                 ((SOURCE) == RCC_UART7CLKSOURCE_LSE)    || \
02656                 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
02657
02658 #define IS_RCC_UART8CLKSOURCE(SOURCE)  \
02659                (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1)  || \
02660                 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
02661                 ((SOURCE) == RCC_UART8CLKSOURCE_LSE)    || \
02662                 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
02663 #define IS_RCC_I2C1CLKSOURCE(SOURCE)   \
02664                (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
02665                 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
02666                 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
02667 #define IS_RCC_I2C2CLKSOURCE(SOURCE)   \
02668                (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
02669                 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
02670                 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
02671
02672 #define IS_RCC_I2C3CLKSOURCE(SOURCE)   \
02673                (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
02674                 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
02675                 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
02676 #define IS_RCC_I2C4CLKSOURCE(SOURCE)   \
02677                (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
02678                 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
02679                 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
02680 #define IS_RCC_LPTIM1CLK(SOURCE)  \
02681                (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
02682                 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  || \
02683                 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  || \
02684                 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
02685 #define IS_RCC_CLK48SOURCE(SOURCE)  \
02686                (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
02687                 ((SOURCE) == RCC_CLK48SOURCE_PLL))
02688 #define IS_RCC_TIMPRES(VALUE)  \
02689                (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
02690                 ((VALUE) == RCC_TIMPRES_ACTIVATED))
02691
02692 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)
02693 #define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
02694                                        ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
02695                                        ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
02696 #define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
02697                                        ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
02698                                        ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
02699 #endif /* STM32F745xx || STM32F746xx || STM32F756xx */
02700
02701 /**
02702   * @}
02703   */
02704
02705 /**
02706   * @}
02707   */
02708
02709 /**
02710   * @}
02711   */
02712
02713 /**
02714   * @}
02715   */
02716
02717 #ifdef __cplusplus
02718 }
02719 #endif
02720
02721 #endif /* __STM32F7xx_HAL_RCC_EX_H */
02722
02723 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rng.c Source File

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stm32f7xx_hal_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   RNG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Random Number Generator (RNG) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019       The RNG HAL driver can be used as follows:
00020
00021       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00022           in HAL_RNG_MspInit().
00023       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00024       (#) Wait until the 32 bit Random Number Generator contains a valid
00025           random data using (polling/interrupt) mode.
00026       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00033   *
00034   * Redistribution and use in source and binary forms, with or without modification,
00035   * are permitted provided that the following conditions are met:
00036   *   1. Redistributions of source code must retain the above copyright notice,
00037   *      this list of conditions and the following disclaimer.
00038   *   2. Redistributions in binary form must reproduce the above copyright notice,
00039   *      this list of conditions and the following disclaimer in the documentation
00040   *      and/or other materials provided with the distribution.
00041   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00042   *      may be used to endorse or promote products derived from this software
00043   *      without specific prior written permission.
00044   *
00045   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00046   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00047   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00048   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00049   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00050   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00051   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00052   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00053   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00054   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00055   *
00056   ******************************************************************************
00057   */
00058
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32f7xx_hal.h"
00061
00062 /** @addtogroup STM32F7xx_HAL_Driver
00063   * @{
00064   */
00065
00066 /** @addtogroup RNG
00067   * @{
00068   */
00069
00070 #ifdef HAL_RNG_MODULE_ENABLED
00071
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private defines -----------------------------------------------------------*/
00074 /* Private variables ---------------------------------------------------------*/
00075 /* Private constants ---------------------------------------------------------*/
00076 /** @addtogroup RNG_Private_Constants
00077   * @{
00078   */
00079 #define RNG_TIMEOUT_VALUE     2
00080 /**
00081   * @}
00082   */
00083 /* Private macros ------------------------------------------------------------*/
00084 /* Private functions prototypes ----------------------------------------------*/
00085 /* Private functions ---------------------------------------------------------*/
00086 /* Exported functions --------------------------------------------------------*/
00087
00088 /** @addtogroup RNG_Exported_Functions
00089   * @{
00090   */
00091
00092 /** @addtogroup RNG_Exported_Functions_Group1
00093  *  @brief   Initialization and de-initialization functions
00094  *
00095 @verbatim
00096  ===============================================================================
00097           ##### Initialization and de-initialization functions #####
00098  ===============================================================================
00099     [..]  This section provides functions allowing to:
00100       (+) Initialize the RNG according to the specified parameters
00101           in the RNG_InitTypeDef and create the associated handle
00102       (+) DeInitialize the RNG peripheral
00103       (+) Initialize the RNG MSP
00104       (+) DeInitialize RNG MSP
00105
00106 @endverbatim
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  Initializes the RNG peripheral and creates the associated handle.
00112   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00113   *                the configuration information for RNG.
00114   * @retval HAL status
00115   */
00116 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00117 {
00118   /* Check the RNG handle allocation */
00119   if(hrng == NULL)
00120   {
00121     return HAL_ERROR;
00122   }
00123
00124   __HAL_LOCK(hrng);
00125
00126   if(hrng->State == HAL_RNG_STATE_RESET)
00127   {
00128     /* Allocate lock resource and initialize it */
00129     hrng->Lock = HAL_UNLOCKED;
00130
00131     /* Init the low level hardware */
00132     HAL_RNG_MspInit(hrng);
00133   }
00134
00135   /* Change RNG peripheral state */
00136   hrng->State = HAL_RNG_STATE_BUSY;
00137
00138   /* Enable the RNG Peripheral */
00139   __HAL_RNG_ENABLE(hrng);
00140
00141   /* Initialize the RNG state */
00142   hrng->State = HAL_RNG_STATE_READY;
00143
00144   __HAL_UNLOCK(hrng);
00145
00146   /* Return function status */
00147   return HAL_OK;
00148 }
00149
00150 /**
00151   * @brief  DeInitializes the RNG peripheral.
00152   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00153   *                the configuration information for RNG.
00154   * @retval HAL status
00155   */
00156 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00157 {
00158   /* Check the RNG handle allocation */
00159   if(hrng == NULL)
00160   {
00161     return HAL_ERROR;
00162   }
00163   /* Disable the RNG Peripheral */
00164   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00165
00166   /* Clear RNG interrupt status flags */
00167   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00168
00169   /* DeInit the low level hardware */
00170   HAL_RNG_MspDeInit(hrng);
00171
00172   /* Update the RNG state */
00173   hrng->State = HAL_RNG_STATE_RESET;
00174
00175   /* Release Lock */
00176   __HAL_UNLOCK(hrng);
00177
00178   /* Return the function status */
00179   return HAL_OK;
00180 }
00181
00182 /**
00183   * @brief  Initializes the RNG MSP.
00184   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00185   *                the configuration information for RNG.
00186   * @retval None
00187   */
00188 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00189 {
00190   /* Prevent unused argument(s) compilation warning */
00191   UNUSED(hrng);
00192
00193   /* NOTE : This function should not be modified. When the callback is needed,
00194             function HAL_RNG_MspInit must be implemented in the user file.
00195    */
00196 }
00197
00198 /**
00199   * @brief  DeInitializes the RNG MSP.
00200   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00201   *                the configuration information for RNG.
00202   * @retval None
00203   */
00204 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00205 {
00206   /* Prevent unused argument(s) compilation warning */
00207   UNUSED(hrng);
00208
00209   /* NOTE : This function should not be modified. When the callback is needed,
00210             function HAL_RNG_MspDeInit must be implemented in the user file.
00211    */
00212 }
00213
00214 /**
00215   * @}
00216   */
00217
00218 /** @addtogroup RNG_Exported_Functions_Group2
00219  *  @brief   Peripheral Control functions
00220  *
00221 @verbatim
00222  ===============================================================================
00223                       ##### Peripheral Control functions #####
00224  ===============================================================================
00225     [..]  This section provides functions allowing to:
00226       (+) Get the 32 bit Random number
00227       (+) Get the 32 bit Random number with interrupt enabled
00228       (+) Handle RNG interrupt request
00229
00230 @endverbatim
00231   * @{
00232   */
00233
00234 /**
00235   * @brief  Generates a 32-bit random number.
00236   * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
00237   *         is automatically cleared.
00238   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00239   *                the configuration information for RNG.
00240   * @param  random32bit: pointer to generated random number variable if successful.
00241   * @retval HAL status
00242   */
00243
00244 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00245 {
00246   uint32_t tickstart = 0;
00247   HAL_StatusTypeDef status = HAL_OK;
00248
00249   /* Process Locked */
00250   __HAL_LOCK(hrng);
00251
00252   /* Check RNG peripheral state */
00253   if(hrng->State == HAL_RNG_STATE_READY)
00254   {
00255     /* Change RNG peripheral state */
00256     hrng->State = HAL_RNG_STATE_BUSY;
00257
00258     /* Get tick */
00259     tickstart = HAL_GetTick();
00260
00261     /* Check if data register contains valid random data */
00262     while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00263     {
00264       if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
00265       {
00266         hrng->State = HAL_RNG_STATE_ERROR;
00267
00268         /* Process Unlocked */
00269         __HAL_UNLOCK(hrng);
00270
00271         return HAL_TIMEOUT;
00272       }
00273     }
00274
00275     /* Get a 32bit Random number */
00276     hrng->RandomNumber = hrng->Instance->DR;
00277     *random32bit = hrng->RandomNumber;
00278
00279     hrng->State = HAL_RNG_STATE_READY;
00280   }
00281   else
00282   {
00283     status = HAL_ERROR;
00284   }
00285
00286   /* Process Unlocked */
00287   __HAL_UNLOCK(hrng);
00288
00289   return status;
00290 }
00291
00292 /**
00293   * @brief  Generates a 32-bit random number in interrupt mode.
00294   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00295   *                the configuration information for RNG.
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00299 {
00300   HAL_StatusTypeDef status = HAL_OK;
00301
00302   /* Process Locked */
00303   __HAL_LOCK(hrng);
00304
00305   /* Check RNG peripheral state */
00306   if(hrng->State == HAL_RNG_STATE_READY)
00307   {
00308     /* Change RNG peripheral state */
00309     hrng->State = HAL_RNG_STATE_BUSY;
00310
00311     /* Process Unlocked */
00312     __HAL_UNLOCK(hrng);
00313
00314     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00315     __HAL_RNG_ENABLE_IT(hrng);
00316   }
00317   else
00318   {
00319     /* Process Unlocked */
00320     __HAL_UNLOCK(hrng);
00321
00322     status = HAL_ERROR;
00323   }
00324
00325   return status;
00326 }
00327
00328 /**
00329   * @brief  Handles RNG interrupt request.
00330   * @note   In the case of a clock error, the RNG is no more able to generate
00331   *         random numbers because the PLL48CLK clock is not correct. User has
00332   *         to check that the clock controller is correctly configured to provide
00333   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00334   *         The clock error has no impact on the previously generated
00335   *         random numbers, and the RNG_DR register contents can be used.
00336   * @note   In the case of a seed error, the generation of random numbers is
00337   *         interrupted as long as the SECS bit is '1'. If a number is
00338   *         available in the RNG_DR register, it must not be used because it may
00339   *         not have enough entropy. In this case, it is recommended to clear the
00340   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00341   *         the RNG peripheral to reinitialize and restart the RNG.
00342   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00343   *         or CEIS are set.
00344   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00345   *                the configuration information for RNG.
00346   * @retval None
00347
00348   */
00349 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00350 {
00351   /* RNG clock error interrupt occurred */
00352   if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
00353   {
00354     /* Change RNG peripheral state */
00355     hrng->State = HAL_RNG_STATE_ERROR;
00356
00357     HAL_RNG_ErrorCallback(hrng);
00358
00359     /* Clear the clock error flag */
00360     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
00361
00362   }
00363
00364   /* Check RNG data ready interrupt occurred */
00365   if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00366   {
00367     /* Generate random number once, so disable the IT */
00368     __HAL_RNG_DISABLE_IT(hrng);
00369
00370     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00371     hrng->RandomNumber = hrng->Instance->DR;
00372
00373     if(hrng->State != HAL_RNG_STATE_ERROR)
00374     {
00375       /* Change RNG peripheral state */
00376       hrng->State = HAL_RNG_STATE_READY;
00377
00378       /* Data Ready callback */
00379       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00380     }
00381   }
00382 }
00383
00384 /**
00385   * @brief  Returns generated random number in polling mode (Obsolete)
00386   *         Use HAL_RNG_GenerateRandomNumber() API instead.
00387   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00388   *                the configuration information for RNG.
00389   * @retval Random value
00390   */
00391 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
00392 {
00393   if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
00394   {
00395     return hrng->RandomNumber;
00396   }
00397   else
00398   {
00399     return 0;
00400   }
00401 }
00402
00403 /**
00404   * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
00405   *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
00406   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00407   *                the configuration information for RNG.
00408   * @retval 32-bit random number
00409   */
00410 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
00411 {
00412   uint32_t random32bit = 0;
00413
00414   /* Process locked */
00415   __HAL_LOCK(hrng);
00416
00417   /* Change RNG peripheral state */
00418   hrng->State = HAL_RNG_STATE_BUSY;
00419
00420   /* Get a 32bit Random number */
00421   random32bit = hrng->Instance->DR;
00422
00423   /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00424   __HAL_RNG_ENABLE_IT(hrng);
00425
00426   /* Return the 32 bit random number */
00427   return random32bit;
00428 }
00429
00430 /**
00431   * @brief  Read latest generated random number.
00432   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00433   *                the configuration information for RNG.
00434   * @retval random value
00435   */
00436 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00437 {
00438   return(hrng->RandomNumber);
00439 }
00440
00441 /**
00442   * @brief  Data Ready callback in non-blocking mode.
00443   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00444   *                the configuration information for RNG.
00445   * @param  random32bit: generated random number.
00446   * @retval None
00447   */
00448 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00449 {
00450   /* Prevent unused argument(s) compilation warning */
00451   UNUSED(hrng);
00452
00453   /* NOTE : This function should not be modified. When the callback is needed,
00454             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00455    */
00456 }
00457
00458 /**
00459   * @brief  RNG error callbacks.
00460   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00461   *                the configuration information for RNG.
00462   * @retval None
00463   */
00464 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00465 {
00466   /* Prevent unused argument(s) compilation warning */
00467   UNUSED(hrng);
00468
00469   /* NOTE : This function should not be modified. When the callback is needed,
00470             function HAL_RNG_ErrorCallback must be implemented in the user file.
00471    */
00472 }
00473 /**
00474   * @}
00475   */
00476
00477
00478 /** @addtogroup RNG_Exported_Functions_Group3
00479  *  @brief   Peripheral State functions
00480  *
00481 @verbatim
00482  ===============================================================================
00483                       ##### Peripheral State functions #####
00484  ===============================================================================
00485     [..]
00486     This subsection permits to get in run-time the status of the peripheral
00487     and the data flow.
00488
00489 @endverbatim
00490   * @{
00491   */
00492
00493 /**
00494   * @brief  Returns the RNG state.
00495   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00496   *                the configuration information for RNG.
00497   * @retval HAL state
00498   */
00499 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00500 {
00501   return hrng->State;
00502 }
00503
00504 /**
00505   * @}
00506   */
00507
00508 /**
00509   * @}
00510   */
00511
00512 #endif /* HAL_RNG_MODULE_ENABLED */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rng.h Source File

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stm32f7xx_hal_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of RNG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_RNG_H
00040 #define __STM32F7xx_HAL_RNG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup RNG RNG
00054   * @brief RNG HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup RNG_Exported_Types RNG Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
00065   * @{
00066   */
00067 typedef enum
00068 {
00069   HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
00070   HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
00071   HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */
00072   HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
00073   HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
00074
00075 }HAL_RNG_StateTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
00082   * @{
00083   */
00084 typedef struct
00085 {
00086   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00087
00088   uint32_t                    RandomNumber; /*!< Last Generated random number */
00089
00090   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00091
00092   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00093
00094 }RNG_HandleTypeDef;
00095
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105
00106 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00107   * @{
00108   */
00109
00110 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00111   * @{
00112   */
00113 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00114 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00115 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00121   * @{
00122   */
00123 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00124 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00125 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /* Exported macros -----------------------------------------------------------*/
00136
00137 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00138   * @{
00139   */
00140
00141 /** @brief Reset RNG handle state
00142   * @param  __HANDLE__: RNG Handle
00143   * @retval None
00144   */
00145 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00146
00147 /**
00148   * @brief  Enables the RNG peripheral.
00149   * @param  __HANDLE__: RNG Handle
00150   * @retval None
00151   */
00152 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00153
00154 /**
00155   * @brief  Disables the RNG peripheral.
00156   * @param  __HANDLE__: RNG Handle
00157   * @retval None
00158   */
00159 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00160
00161 /**
00162   * @brief  Check the selected RNG flag status.
00163   * @param  __HANDLE__: RNG Handle
00164   * @param  __FLAG__: RNG flag
00165   *          This parameter can be one of the following values:
00166   *            @arg RNG_FLAG_DRDY: Data ready
00167   *            @arg RNG_FLAG_CECS: Clock error current status
00168   *            @arg RNG_FLAG_SECS: Seed error current status
00169   * @retval The new state of __FLAG__ (SET or RESET).
00170   */
00171 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00172
00173 /**
00174   * @brief  Clears the selected RNG flag status.
00175   * @param  __HANDLE__: RNG handle
00176   * @param  __FLAG__: RNG flag to clear
00177   * @note   WARNING: This is a dummy macro for HAL code alignment,
00178   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00179   * @retval None
00180   */
00181 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00182
00183
00184
00185 /**
00186   * @brief  Enables the RNG interrupts.
00187   * @param  __HANDLE__: RNG Handle
00188   * @retval None
00189   */
00190 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00191
00192 /**
00193   * @brief  Disables the RNG interrupts.
00194   * @param  __HANDLE__: RNG Handle
00195   * @retval None
00196   */
00197 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00198
00199 /**
00200   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00201   * @param  __HANDLE__: RNG Handle
00202   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
00203   *         This parameter can be one of the following values:
00204   *            @arg RNG_IT_DRDY: Data ready interrupt
00205   *            @arg RNG_IT_CEI: Clock error interrupt
00206   *            @arg RNG_IT_SEI: Seed error interrupt
00207   * @retval The new state of __INTERRUPT__ (SET or RESET).
00208   */
00209 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00210
00211 /**
00212   * @brief  Clear the RNG interrupt status flags.
00213   * @param  __HANDLE__: RNG Handle
00214   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
00215   *          This parameter can be one of the following values:
00216   *            @arg RNG_IT_CEI: Clock error interrupt
00217   *            @arg RNG_IT_SEI: Seed error interrupt
00218   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00219   * @retval None
00220   */
00221 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00222
00223 /**
00224   * @}
00225   */
00226
00227 /* Exported functions --------------------------------------------------------*/
00228 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00229   * @{
00230   */
00231
00232 /** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
00233   * @{
00234   */
00235 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00236 HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
00237 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00238 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00239
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00245   * @{
00246   */
00247 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
00248 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
00249
00250 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00251 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00252 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00253
00254 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00255 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00256 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
00257
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00263   * @{
00264   */
00265 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /* Private types -------------------------------------------------------------*/
00276 /** @defgroup RNG_Private_Types RNG Private Types
00277   * @{
00278   */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /* Private defines -----------------------------------------------------------*/
00285 /** @defgroup RNG_Private_Defines RNG Private Defines
00286   * @{
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /* Private variables ---------------------------------------------------------*/
00294 /** @defgroup RNG_Private_Variables RNG Private Variables
00295   * @{
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /* Private constants ---------------------------------------------------------*/
00303 /** @defgroup RNG_Private_Constants RNG Private Constants
00304   * @{
00305   */
00306
00307 /**
00308   * @}
00309   */
00310
00311 /* Private macros ------------------------------------------------------------*/
00312 /** @defgroup RNG_Private_Macros RNG Private Macros
00313   * @{
00314   */
00315 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00316                        ((IT) == RNG_IT_SEI))
00317
00318 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00319                            ((FLAG) == RNG_FLAG_CECS) || \
00320                            ((FLAG) == RNG_FLAG_SECS))
00321
00322 /**
00323   * @}
00324   */
00325
00326 /* Private functions prototypes ----------------------------------------------*/
00327 /** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
00328   * @{
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /* Private functions ---------------------------------------------------------*/
00336 /** @defgroup RNG_Private_Functions RNG Private Functions
00337   * @{
00338   */
00339
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 #ifdef __cplusplus
00353 }
00354 #endif
00355
00356 #endif /* __STM32F7xx_HAL_RNG_H */
00357
00358 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc.c Source File

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stm32f7xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + RTC Time and Date functions
00012   *           + RTC Alarm functions
00013   *           + Peripheral Control functions
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018               ##### Backup Domain Operating Condition #####
00019   ==============================================================================
00020   [..] The real-time clock (RTC), the RTC backup registers, and the backup
00021        SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
00022        VDD supply is powered off.
00023        To retain the content of the RTC backup registers, backup SRAM, and supply
00024        the RTC when VDD is turned off, VBAT pin can be connected to an optional
00025        standby voltage supplied by a battery or by another source.
00026
00027   [..] To allow the RTC operating even when the main digital supply (VDD) is turned
00028        off, the VBAT pin powers the following blocks:
00029     (#) The RTC
00030     (#) The LSE oscillator
00031     (#) The backup SRAM when the low power backup regulator is enabled
00032     (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
00033
00034   [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
00035        the following pins are available:
00036     (#) PC14 and PC15 can be used as either GPIO or LSE pins
00037     (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
00038     (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
00039
00040   [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
00041        because VDD is not present), the following pins are available:
00042     (#) PC14 and PC15 can be used as LSE pins only
00043     (#) PC13 can be used as the RTC_AF1 pin
00044     (#) PI8 can be used as the RTC_AF2 pin
00045     (#) PC1 can be used as the RTC_AF3 pin
00046
00047                    ##### Backup Domain Reset #####
00048   ==================================================================
00049   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00050        to their reset values. The BKPSRAM is not affected by this reset. The only
00051        way to reset the BKPSRAM is through the Flash interface by requesting
00052        a protection level change from 1 to 0.
00053   [..] A backup domain reset is generated when one of the following events occurs:
00054     (#) Software reset, triggered by setting the BDRST bit in the
00055         RCC Backup domain control register (RCC_BDCR).
00056     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00057
00058                    ##### Backup Domain Access #####
00059   ==================================================================
00060   [..] After reset, the backup domain (RTC registers, RTC backup data
00061        registers and backup SRAM) is protected against possible unwanted write
00062        accesses.
00063   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00064     (+) Enable the Power Controller (PWR) APB1 interface clock using the
00065         __HAL_RCC_PWR_CLK_ENABLE() function.
00066     (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00067     (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
00068     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
00069
00070
00071                   ##### How to use this driver #####
00072   ==================================================================
00073   [..]
00074     (+) Enable the RTC domain access (see description in the section above).
00075     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00076         format using the HAL_RTC_Init() function.
00077
00078   *** Time and Date configuration ***
00079   ===================================
00080   [..]
00081     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00082         and HAL_RTC_SetDate() functions.
00083     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00084
00085   *** Alarm configuration ***
00086   ===========================
00087   [..]
00088     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00089         You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
00090     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00091
00092                   ##### RTC and low power modes #####
00093   ==================================================================
00094   [..] The MCU can be woken up from a low power mode by an RTC alternate
00095        function.
00096   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00097        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00098        These RTC alternate functions can wake up the system from the Stop and
00099        Standby low power modes.
00100   [..] The system can also wake up from low power modes without depending
00101        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00102        or the RTC wakeup events.
00103   [..] The RTC provides a programmable time base for waking up from the
00104        Stop or Standby mode at regular intervals.
00105        Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
00106        is LSE or LSI.
00107
00108    @endverbatim
00109   ******************************************************************************
00110   * @attention
00111   *
00112   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00113   *
00114   * Redistribution and use in source and binary forms, with or without modification,
00115   * are permitted provided that the following conditions are met:
00116   *   1. Redistributions of source code must retain the above copyright notice,
00117   *      this list of conditions and the following disclaimer.
00118   *   2. Redistributions in binary form must reproduce the above copyright notice,
00119   *      this list of conditions and the following disclaimer in the documentation
00120   *      and/or other materials provided with the distribution.
00121   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00122   *      may be used to endorse or promote products derived from this software
00123   *      without specific prior written permission.
00124   *
00125   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00126   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00127   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00128   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00129   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00130   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00131   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00132   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00133   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00134   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00135   *
00136   ******************************************************************************
00137   */
00138
00139 /* Includes ------------------------------------------------------------------*/
00140 #include "stm32f7xx_hal.h"
00141
00142 /** @addtogroup STM32F7xx_HAL_Driver
00143   * @{
00144   */
00145
00146 /** @defgroup RTC RTC
00147   * @brief RTC HAL module driver
00148   * @{
00149   */
00150
00151 #ifdef HAL_RTC_MODULE_ENABLED
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /* Private macro -------------------------------------------------------------*/
00156 /* Private variables ---------------------------------------------------------*/
00157 /* Private function prototypes -----------------------------------------------*/
00158 /* Private functions ---------------------------------------------------------*/
00159
00160 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00161   * @{
00162   */
00163
00164 /** @defgroup RTC_Group1 Initialization and de-initialization functions
00165  *  @brief    Initialization and Configuration functions
00166  *
00167 @verbatim
00168  ===============================================================================
00169               ##### Initialization and de-initialization functions #####
00170  ===============================================================================
00171    [..] This section provides functions allowing to initialize and configure the
00172          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00173          RTC registers Write protection, enter and exit the RTC initialization mode,
00174          RTC registers synchronization check and reference clock detection enable.
00175          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00176              It is split into 2 programmable prescalers to minimize power consumption.
00177              (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
00178              (++) When both prescalers are used, it is recommended to configure the
00179                  asynchronous prescaler to a high value to minimize power consumption.
00180          (#) All RTC registers are Write protected. Writing to the RTC registers
00181              is enabled by writing a key into the Write Protection register, RTC_WPR.
00182          (#) To configure the RTC Calendar, user application should enter
00183              initialization mode. In this mode, the calendar counter is stopped
00184              and its value can be updated. When the initialization sequence is
00185              complete, the calendar restarts counting after 4 RTCCLK cycles.
00186          (#) To read the calendar through the shadow registers after Calendar
00187              initialization, calendar update or after wakeup from low power modes
00188              the software must first clear the RSF flag. The software must then
00189              wait until it is set again before reading the calendar, which means
00190              that the calendar registers have been correctly copied into the
00191              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00192              implements the above software sequence (RSF clear and RSF check).
00193
00194 @endverbatim
00195   * @{
00196   */
00197
00198 /**
00199   * @brief  Initializes the RTC peripheral
00200   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00201   *                the configuration information for RTC.
00202   * @retval HAL status
00203   */
00204 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00205 {
00206   /* Check the RTC peripheral state */
00207   if(hrtc == NULL)
00208   {
00209      return HAL_ERROR;
00210   }
00211
00212   /* Check the parameters */
00213   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00214   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00215   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00216   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00217   assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
00218   assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00219   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00220
00221   if(hrtc->State == HAL_RTC_STATE_RESET)
00222   {
00223     /* Allocate lock resource and initialize it */
00224     hrtc->Lock = HAL_UNLOCKED;
00225     /* Initialize RTC MSP */
00226     HAL_RTC_MspInit(hrtc);
00227   }
00228
00229   /* Set RTC state */
00230   hrtc->State = HAL_RTC_STATE_BUSY;
00231
00232   /* Disable the write protection for RTC registers */
00233   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00234
00235   /* Set Initialization mode */
00236   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00237   {
00238     /* Enable the write protection for RTC registers */
00239     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00240
00241     /* Set RTC state */
00242     hrtc->State = HAL_RTC_STATE_ERROR;
00243
00244     return HAL_ERROR;
00245   }
00246   else
00247   {
00248     /* Clear RTC_CR FMT, OSEL and POL Bits */
00249     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
00250     /* Set RTC_CR register */
00251     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00252
00253     /* Configure the RTC PRER */
00254     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
00255     hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
00256
00257     /* Exit Initialization mode */
00258     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00259
00260     hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;
00261     hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
00262
00263     /* Enable the write protection for RTC registers */
00264     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00265
00266     /* Set RTC state */
00267     hrtc->State = HAL_RTC_STATE_READY;
00268
00269     return HAL_OK;
00270   }
00271 }
00272
00273 /**
00274   * @brief  DeInitializes the RTC peripheral
00275   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00276   *                the configuration information for RTC.
00277   * @note   This function doesn't reset the RTC Backup Data registers.
00278   * @retval HAL status
00279   */
00280 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00281 {
00282   uint32_t tickstart = 0;
00283
00284   /* Check the parameters */
00285   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00286
00287   /* Set RTC state */
00288   hrtc->State = HAL_RTC_STATE_BUSY;
00289
00290   /* Disable the write protection for RTC registers */
00291   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00292
00293   /* Set Initialization mode */
00294   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00295   {
00296     /* Enable the write protection for RTC registers */
00297     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00298
00299     /* Set RTC state */
00300     hrtc->State = HAL_RTC_STATE_ERROR;
00301
00302     return HAL_ERROR;
00303   }
00304   else
00305   {
00306     /* Reset TR, DR and CR registers */
00307     hrtc->Instance->TR = (uint32_t)0x00000000;
00308     hrtc->Instance->DR = (uint32_t)0x00002101;
00309     /* Reset All CR bits except CR[2:0] */
00310     hrtc->Instance->CR &= (uint32_t)0x00000007;
00311
00312     /* Get tick */
00313     tickstart = HAL_GetTick();
00314
00315     /* Wait till WUTWF flag is set and if Time out is reached exit */
00316     while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
00317     {
00318       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00319       {
00320         /* Enable the write protection for RTC registers */
00321         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00322
00323         /* Set RTC state */
00324         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00325
00326         return HAL_TIMEOUT;
00327       }
00328     }
00329
00330     /* Reset all RTC CR register bits */
00331     hrtc->Instance->CR &= (uint32_t)0x00000000;
00332     hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
00333     hrtc->Instance->PRER = (uint32_t)0x007F00FF;
00334     hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
00335     hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
00336     hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
00337     hrtc->Instance->CALR = (uint32_t)0x00000000;
00338     hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
00339     hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
00340
00341     /* Reset ISR register and exit initialization mode */
00342     hrtc->Instance->ISR = (uint32_t)0x00000000;
00343
00344     /* Reset Tamper and alternate functions configuration register */
00345     hrtc->Instance->TAMPCR = 0x00000000;
00346
00347     /* Reset Option register */
00348     hrtc->Instance->OR = 0x00000000;
00349
00350     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00351     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00352     {
00353       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00354       {
00355         /* Enable the write protection for RTC registers */
00356         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00357
00358         hrtc->State = HAL_RTC_STATE_ERROR;
00359
00360         return HAL_ERROR;
00361       }
00362     }
00363   }
00364
00365   /* Enable the write protection for RTC registers */
00366   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00367
00368   /* De-Initialize RTC MSP */
00369   HAL_RTC_MspDeInit(hrtc);
00370
00371   hrtc->State = HAL_RTC_STATE_RESET;
00372
00373   /* Release Lock */
00374   __HAL_UNLOCK(hrtc);
00375
00376   return HAL_OK;
00377 }
00378
00379 /**
00380   * @brief  Initializes the RTC MSP.
00381   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00382   *                the configuration information for RTC.
00383   * @retval None
00384   */
00385 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00386 {
00387   /* Prevent unused argument(s) compilation warning */
00388   UNUSED(hrtc);
00389
00390   /* NOTE : This function Should not be modified, when the callback is needed,
00391             the HAL_RTC_MspInit could be implemented in the user file
00392    */
00393 }
00394
00395 /**
00396   * @brief  DeInitializes the RTC MSP.
00397   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00398   *                the configuration information for RTC.
00399   * @retval None
00400   */
00401 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00402 {
00403   /* Prevent unused argument(s) compilation warning */
00404   UNUSED(hrtc);
00405
00406   /* NOTE : This function Should not be modified, when the callback is needed,
00407             the HAL_RTC_MspDeInit could be implemented in the user file
00408    */
00409 }
00410
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup RTC_Group2 RTC Time and Date functions
00416  *  @brief   RTC Time and Date functions
00417  *
00418 @verbatim
00419  ===============================================================================
00420                  ##### RTC Time and Date functions #####
00421  ===============================================================================
00422
00423  [..] This section provides functions allowing to configure Time and Date features
00424
00425 @endverbatim
00426   * @{
00427   */
00428
00429 /**
00430   * @brief  Sets RTC current time.
00431   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00432   *                the configuration information for RTC.
00433   * @param  sTime: Pointer to Time structure
00434   * @param  Format: Specifies the format of the entered parameters.
00435   *          This parameter can be one of the following values:
00436   *            @arg FORMAT_BIN: Binary data format
00437   *            @arg FORMAT_BCD: BCD data format
00438   * @retval HAL status
00439   */
00440 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00441 {
00442   uint32_t tmpreg = 0;
00443
00444  /* Check the parameters */
00445   assert_param(IS_RTC_FORMAT(Format));
00446   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00447   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00448
00449   /* Process Locked */
00450   __HAL_LOCK(hrtc);
00451
00452   hrtc->State = HAL_RTC_STATE_BUSY;
00453
00454   if(Format == RTC_FORMAT_BIN)
00455   {
00456     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00457     {
00458       assert_param(IS_RTC_HOUR12(sTime->Hours));
00459       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00460     }
00461     else
00462     {
00463       sTime->TimeFormat = 0x00;
00464       assert_param(IS_RTC_HOUR24(sTime->Hours));
00465     }
00466     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00467     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00468
00469     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
00470                         ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
00471                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
00472                         (((uint32_t)sTime->TimeFormat) << 16));
00473   }
00474   else
00475   {
00476     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00477     {
00478       tmpreg = RTC_Bcd2ToByte(sTime->Hours);
00479       assert_param(IS_RTC_HOUR12(tmpreg));
00480       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00481     }
00482     else
00483     {
00484       sTime->TimeFormat = 0x00;
00485       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00486     }
00487     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00488     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00489     tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
00490               ((uint32_t)(sTime->Minutes) << 8) | \
00491               ((uint32_t)sTime->Seconds) | \
00492               ((uint32_t)(sTime->TimeFormat) << 16));
00493   }
00494
00495   /* Disable the write protection for RTC registers */
00496   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00497
00498   /* Set Initialization mode */
00499   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00500   {
00501     /* Enable the write protection for RTC registers */
00502     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00503
00504     /* Set RTC state */
00505     hrtc->State = HAL_RTC_STATE_ERROR;
00506
00507     /* Process Unlocked */
00508     __HAL_UNLOCK(hrtc);
00509
00510     return HAL_ERROR;
00511   }
00512   else
00513   {
00514     /* Set the RTC_TR register */
00515     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00516
00517     /* Clear the bits to be configured */
00518     hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
00519
00520     /* Configure the RTC_CR register */
00521     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00522
00523     /* Exit Initialization mode */
00524     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00525
00526     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00527     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00528     {
00529       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00530       {
00531         /* Enable the write protection for RTC registers */
00532         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00533
00534         hrtc->State = HAL_RTC_STATE_ERROR;
00535
00536         /* Process Unlocked */
00537         __HAL_UNLOCK(hrtc);
00538
00539         return HAL_ERROR;
00540       }
00541     }
00542
00543     /* Enable the write protection for RTC registers */
00544     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00545
00546    hrtc->State = HAL_RTC_STATE_READY;
00547
00548    __HAL_UNLOCK(hrtc);
00549
00550    return HAL_OK;
00551   }
00552 }
00553
00554 /**
00555   * @brief  Gets RTC current time.
00556   * @param  hrtc: RTC handle
00557   * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
00558   *                with input format (BIN or BCD), also SubSeconds field returning the
00559   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
00560   *                factor to be used for second fraction ratio computation.
00561   * @param  Format: Specifies the format of the entered parameters.
00562   *          This parameter can be one of the following values:
00563   *            @arg RTC_FORMAT_BIN: Binary data format
00564   *            @arg RTC_FORMAT_BCD: BCD data format
00565   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00566   *        value in second fraction ratio with time unit following generic formula:
00567   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00568   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00569   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00570   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00571   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
00572   *        to ensure consistency between the time and date values.
00573   * @retval HAL status
00574   */
00575 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00576 {
00577   uint32_t tmpreg = 0;
00578
00579   /* Check the parameters */
00580   assert_param(IS_RTC_FORMAT(Format));
00581
00582   /* Get subseconds values from the correspondent registers*/
00583   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00584
00585   /* Get the TR register */
00586   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00587
00588   /* Fill the structure fields with the read parameters */
00589   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00590   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
00591   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00592   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
00593
00594   /* Check the input parameters format */
00595   if(Format == RTC_FORMAT_BIN)
00596   {
00597     /* Convert the time structure parameters to Binary format */
00598     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00599     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00600     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00601   }
00602
00603   return HAL_OK;
00604 }
00605
00606 /**
00607   * @brief  Sets RTC current date.
00608   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00609   *                the configuration information for RTC.
00610   * @param  sDate: Pointer to date structure
00611   * @param  Format: specifies the format of the entered parameters.
00612   *          This parameter can be one of the following values:
00613   *            @arg RTC_FORMAT_BIN: Binary data format
00614   *            @arg RTC_FORMAT_BCD: BCD data format
00615   * @retval HAL status
00616   */
00617 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00618 {
00619   uint32_t datetmpreg = 0;
00620
00621  /* Check the parameters */
00622   assert_param(IS_RTC_FORMAT(Format));
00623
00624  /* Process Locked */
00625  __HAL_LOCK(hrtc);
00626
00627   hrtc->State = HAL_RTC_STATE_BUSY;
00628
00629   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
00630   {
00631     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
00632   }
00633
00634   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00635
00636   if(Format == RTC_FORMAT_BIN)
00637   {
00638     assert_param(IS_RTC_YEAR(sDate->Year));
00639     assert_param(IS_RTC_MONTH(sDate->Month));
00640     assert_param(IS_RTC_DATE(sDate->Date));
00641
00642    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
00643                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
00644                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
00645                  ((uint32_t)sDate->WeekDay << 13));
00646   }
00647   else
00648   {
00649     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00650     datetmpreg = RTC_Bcd2ToByte(sDate->Month);
00651     assert_param(IS_RTC_MONTH(datetmpreg));
00652     datetmpreg = RTC_Bcd2ToByte(sDate->Date);
00653     assert_param(IS_RTC_DATE(datetmpreg));
00654
00655     datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
00656                   (((uint32_t)sDate->Month) << 8) | \
00657                   ((uint32_t)sDate->Date) | \
00658                   (((uint32_t)sDate->WeekDay) << 13));
00659   }
00660
00661   /* Disable the write protection for RTC registers */
00662   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00663
00664   /* Set Initialization mode */
00665   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00666   {
00667     /* Enable the write protection for RTC registers */
00668     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00669
00670     /* Set RTC state*/
00671     hrtc->State = HAL_RTC_STATE_ERROR;
00672
00673     /* Process Unlocked */
00674     __HAL_UNLOCK(hrtc);
00675
00676     return HAL_ERROR;
00677   }
00678   else
00679   {
00680     /* Set the RTC_DR register */
00681     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00682
00683     /* Exit Initialization mode */
00684     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00685
00686     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00687     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00688     {
00689       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00690       {
00691         /* Enable the write protection for RTC registers */
00692         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00693
00694         hrtc->State = HAL_RTC_STATE_ERROR;
00695
00696         /* Process Unlocked */
00697         __HAL_UNLOCK(hrtc);
00698
00699         return HAL_ERROR;
00700       }
00701     }
00702
00703     /* Enable the write protection for RTC registers */
00704     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00705
00706     hrtc->State = HAL_RTC_STATE_READY ;
00707
00708     /* Process Unlocked */
00709     __HAL_UNLOCK(hrtc);
00710
00711     return HAL_OK;
00712   }
00713 }
00714
00715 /**
00716   * @brief  Gets RTC current date.
00717   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00718   *                the configuration information for RTC.
00719   * @param  sDate: Pointer to Date structure
00720   * @param  Format: Specifies the format of the entered parameters.
00721   *          This parameter can be one of the following values:
00722   *            @arg RTC_FORMAT_BIN:  Binary data format
00723   *            @arg RTC_FORMAT_BCD:  BCD data format
00724   * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00725   * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00726   * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
00727   * @retval HAL status
00728   */
00729 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00730 {
00731   uint32_t datetmpreg = 0;
00732
00733   /* Check the parameters */
00734   assert_param(IS_RTC_FORMAT(Format));
00735
00736   /* Get the DR register */
00737   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
00738
00739   /* Fill the structure fields with the read parameters */
00740   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
00741   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
00742   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
00743   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
00744
00745   /* Check the input parameters format */
00746   if(Format == RTC_FORMAT_BIN)
00747   {
00748     /* Convert the date structure parameters to Binary format */
00749     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
00750     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
00751     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
00752   }
00753   return HAL_OK;
00754 }
00755
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup RTC_Group3 RTC Alarm functions
00761  *  @brief   RTC Alarm functions
00762  *
00763 @verbatim
00764  ===============================================================================
00765                  ##### RTC Alarm functions #####
00766  ===============================================================================
00767
00768  [..] This section provides functions allowing to configure Alarm feature
00769
00770 @endverbatim
00771   * @{
00772   */
00773 /**
00774   * @brief  Sets the specified RTC Alarm.
00775   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00776   *                the configuration information for RTC.
00777   * @param  sAlarm: Pointer to Alarm structure
00778   * @param  Format: Specifies the format of the entered parameters.
00779   *          This parameter can be one of the following values:
00780   *             @arg FORMAT_BIN: Binary data format
00781   *             @arg FORMAT_BCD: BCD data format
00782   * @retval HAL status
00783   */
00784 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00785 {
00786   uint32_t tickstart = 0;
00787   uint32_t tmpreg = 0, subsecondtmpreg = 0;
00788
00789   /* Check the parameters */
00790   assert_param(IS_RTC_FORMAT(Format));
00791   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00792   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00793   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00794   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00795   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00796
00797   /* Process Locked */
00798   __HAL_LOCK(hrtc);
00799
00800   hrtc->State = HAL_RTC_STATE_BUSY;
00801
00802   if(Format == RTC_FORMAT_BIN)
00803   {
00804     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00805     {
00806       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00807       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00808     }
00809     else
00810     {
00811       sAlarm->AlarmTime.TimeFormat = 0x00;
00812       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00813     }
00814     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00815     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00816
00817     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00818     {
00819       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00820     }
00821     else
00822     {
00823       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00824     }
00825
00826     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
00827               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
00828               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00829               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00830               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
00831               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00832               ((uint32_t)sAlarm->AlarmMask));
00833   }
00834   else
00835   {
00836     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00837     {
00838       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
00839       assert_param(IS_RTC_HOUR12(tmpreg));
00840       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00841     }
00842     else
00843     {
00844       sAlarm->AlarmTime.TimeFormat = 0x00;
00845       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
00846     }
00847
00848     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
00849     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00850
00851     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00852     {
00853       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00854       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
00855     }
00856     else
00857     {
00858       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00859       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
00860     }
00861
00862     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
00863               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
00864               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
00865               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00866               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
00867               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00868               ((uint32_t)sAlarm->AlarmMask));
00869   }
00870
00871   /* Configure the Alarm A or Alarm B Sub Second registers */
00872   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
00873
00874   /* Disable the write protection for RTC registers */
00875   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00876
00877   /* Configure the Alarm register */
00878   if(sAlarm->Alarm == RTC_ALARM_A)
00879   {
00880     /* Disable the Alarm A interrupt */
00881     __HAL_RTC_ALARMA_DISABLE(hrtc);
00882
00883     /* In case of interrupt mode is used, the interrupt source must disabled */
00884     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
00885
00886     /* Get tick */
00887     tickstart = HAL_GetTick();
00888
00889     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
00890     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
00891     {
00892       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00893       {
00894         /* Enable the write protection for RTC registers */
00895         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00896
00897         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00898
00899         /* Process Unlocked */
00900         __HAL_UNLOCK(hrtc);
00901
00902         return HAL_TIMEOUT;
00903       }
00904     }
00905
00906     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
00907     /* Configure the Alarm A Sub Second register */
00908     hrtc->Instance->ALRMASSR = subsecondtmpreg;
00909     /* Configure the Alarm state: Enable Alarm */
00910     __HAL_RTC_ALARMA_ENABLE(hrtc);
00911   }
00912   else
00913   {
00914     /* Disable the Alarm B interrupt */
00915     __HAL_RTC_ALARMB_DISABLE(hrtc);
00916
00917     /* In case of interrupt mode is used, the interrupt source must disabled */
00918     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
00919
00920     /* Get tick */
00921     tickstart = HAL_GetTick();
00922
00923     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
00924     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
00925     {
00926       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00927       {
00928         /* Enable the write protection for RTC registers */
00929         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00930
00931         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00932
00933         /* Process Unlocked */
00934         __HAL_UNLOCK(hrtc);
00935
00936         return HAL_TIMEOUT;
00937       }
00938     }
00939
00940     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
00941     /* Configure the Alarm B Sub Second register */
00942     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
00943     /* Configure the Alarm state: Enable Alarm */
00944     __HAL_RTC_ALARMB_ENABLE(hrtc);
00945   }
00946
00947   /* Enable the write protection for RTC registers */
00948   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00949
00950   /* Change RTC state */
00951   hrtc->State = HAL_RTC_STATE_READY;
00952
00953   /* Process Unlocked */
00954   __HAL_UNLOCK(hrtc);
00955
00956   return HAL_OK;
00957 }
00958
00959 /**
00960   * @brief  Sets the specified RTC Alarm with Interrupt
00961   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00962   *                the configuration information for RTC.
00963   * @param  sAlarm: Pointer to Alarm structure
00964   * @param  Format: Specifies the format of the entered parameters.
00965   *          This parameter can be one of the following values:
00966   *             @arg FORMAT_BIN: Binary data format
00967   *             @arg FORMAT_BCD: BCD data format
00968   * @note   The Alarm register can only be written when the corresponding Alarm
00969   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
00970   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
00971   * @retval HAL status
00972   */
00973 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00974 {
00975   uint32_t tickstart = 0;
00976   uint32_t tmpreg = 0, subsecondtmpreg = 0;
00977
00978   /* Check the parameters */
00979   assert_param(IS_RTC_FORMAT(Format));
00980   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00981   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00982   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00983   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00984   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00985
00986   /* Process Locked */
00987   __HAL_LOCK(hrtc);
00988
00989   hrtc->State = HAL_RTC_STATE_BUSY;
00990
00991   if(Format == RTC_FORMAT_BIN)
00992   {
00993     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00994     {
00995       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00996       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00997     }
00998     else
00999     {
01000       sAlarm->AlarmTime.TimeFormat = 0x00;
01001       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01002     }
01003     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01004     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01005
01006     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01007     {
01008       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01009     }
01010     else
01011     {
01012       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01013     }
01014     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
01015               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
01016               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
01017               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
01018               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
01019               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01020               ((uint32_t)sAlarm->AlarmMask));
01021   }
01022   else
01023   {
01024     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
01025     {
01026       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01027       assert_param(IS_RTC_HOUR12(tmpreg));
01028       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01029     }
01030     else
01031     {
01032       sAlarm->AlarmTime.TimeFormat = 0x00;
01033       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01034     }
01035
01036     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01037     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01038
01039     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01040     {
01041       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01042       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
01043     }
01044     else
01045     {
01046       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01047       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
01048     }
01049     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
01050               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
01051               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01052               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
01053               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
01054               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01055               ((uint32_t)sAlarm->AlarmMask));
01056   }
01057   /* Configure the Alarm A or Alarm B Sub Second registers */
01058   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01059
01060   /* Disable the write protection for RTC registers */
01061   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01062
01063   /* Configure the Alarm register */
01064   if(sAlarm->Alarm == RTC_ALARM_A)
01065   {
01066     /* Disable the Alarm A interrupt */
01067     __HAL_RTC_ALARMA_DISABLE(hrtc);
01068
01069     /* Clear flag alarm A */
01070     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01071
01072     /* Get tick */
01073     tickstart = HAL_GetTick();
01074
01075     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01076     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01077     {
01078       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01079       {
01080         /* Enable the write protection for RTC registers */
01081         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01082
01083         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01084
01085         /* Process Unlocked */
01086         __HAL_UNLOCK(hrtc);
01087
01088         return HAL_TIMEOUT;
01089       }
01090     }
01091
01092     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01093     /* Configure the Alarm A Sub Second register */
01094     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01095     /* Configure the Alarm state: Enable Alarm */
01096     __HAL_RTC_ALARMA_ENABLE(hrtc);
01097     /* Configure the Alarm interrupt */
01098     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01099   }
01100   else
01101   {
01102     /* Disable the Alarm B interrupt */
01103     __HAL_RTC_ALARMB_DISABLE(hrtc);
01104
01105     /* Clear flag alarm B */
01106     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01107
01108     /* Get tick */
01109     tickstart = HAL_GetTick();
01110
01111     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01112     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01113     {
01114       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01115       {
01116         /* Enable the write protection for RTC registers */
01117         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01118
01119         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01120
01121         /* Process Unlocked */
01122         __HAL_UNLOCK(hrtc);
01123
01124         return HAL_TIMEOUT;
01125       }
01126     }
01127
01128     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01129     /* Configure the Alarm B Sub Second register */
01130     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01131     /* Configure the Alarm state: Enable Alarm */
01132     __HAL_RTC_ALARMB_ENABLE(hrtc);
01133     /* Configure the Alarm interrupt */
01134     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01135   }
01136
01137   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01138   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01139
01140   EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
01141
01142   /* Enable the write protection for RTC registers */
01143   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01144
01145   hrtc->State = HAL_RTC_STATE_READY;
01146
01147   /* Process Unlocked */
01148   __HAL_UNLOCK(hrtc);
01149
01150   return HAL_OK;
01151 }
01152
01153 /**
01154   * @brief  Deactive the specified RTC Alarm
01155   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01156   *                the configuration information for RTC.
01157   * @param  Alarm: Specifies the Alarm.
01158   *          This parameter can be one of the following values:
01159   *            @arg RTC_ALARM_A:  AlarmA
01160   *            @arg RTC_ALARM_B:  AlarmB
01161   * @retval HAL status
01162   */
01163 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01164 {
01165   uint32_t tickstart = 0;
01166
01167   /* Check the parameters */
01168   assert_param(IS_RTC_ALARM(Alarm));
01169
01170   /* Process Locked */
01171   __HAL_LOCK(hrtc);
01172
01173   hrtc->State = HAL_RTC_STATE_BUSY;
01174
01175   /* Disable the write protection for RTC registers */
01176   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01177
01178   if(Alarm == RTC_ALARM_A)
01179   {
01180     /* AlarmA */
01181     __HAL_RTC_ALARMA_DISABLE(hrtc);
01182
01183     /* In case of interrupt mode is used, the interrupt source must disabled */
01184     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01185
01186     /* Get tick */
01187     tickstart = HAL_GetTick();
01188
01189     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01190     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01191     {
01192       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01193       {
01194         /* Enable the write protection for RTC registers */
01195         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01196
01197         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01198
01199         /* Process Unlocked */
01200         __HAL_UNLOCK(hrtc);
01201
01202         return HAL_TIMEOUT;
01203       }
01204     }
01205   }
01206   else
01207   {
01208     /* AlarmB */
01209     __HAL_RTC_ALARMB_DISABLE(hrtc);
01210
01211     /* In case of interrupt mode is used, the interrupt source must disabled */
01212     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01213
01214     /* Get tick */
01215     tickstart = HAL_GetTick();
01216
01217     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01218     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01219     {
01220       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01221       {
01222         /* Enable the write protection for RTC registers */
01223         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01224
01225         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01226
01227         /* Process Unlocked */
01228         __HAL_UNLOCK(hrtc);
01229
01230         return HAL_TIMEOUT;
01231       }
01232     }
01233   }
01234   /* Enable the write protection for RTC registers */
01235   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01236
01237   hrtc->State = HAL_RTC_STATE_READY;
01238
01239   /* Process Unlocked */
01240   __HAL_UNLOCK(hrtc);
01241
01242   return HAL_OK;
01243 }
01244
01245 /**
01246   * @brief  Gets the RTC Alarm value and masks.
01247   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01248   *                the configuration information for RTC.
01249   * @param  sAlarm: Pointer to Date structure
01250   * @param  Alarm: Specifies the Alarm.
01251   *          This parameter can be one of the following values:
01252   *             @arg RTC_ALARM_A: AlarmA
01253   *             @arg RTC_ALARM_B: AlarmB
01254   * @param  Format: Specifies the format of the entered parameters.
01255   *          This parameter can be one of the following values:
01256   *             @arg RTC_FORMAT_BIN: Binary data format
01257   *             @arg RTC_FORMAT_BCD: BCD data format
01258   * @retval HAL status
01259   */
01260 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01261 {
01262   uint32_t tmpreg = 0, subsecondtmpreg = 0;
01263
01264   /* Check the parameters */
01265   assert_param(IS_RTC_FORMAT(Format));
01266   assert_param(IS_RTC_ALARM(Alarm));
01267
01268   if(Alarm == RTC_ALARM_A)
01269   {
01270     /* AlarmA */
01271     sAlarm->Alarm = RTC_ALARM_A;
01272
01273     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01274     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01275   }
01276   else
01277   {
01278     sAlarm->Alarm = RTC_ALARM_B;
01279
01280     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01281     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01282   }
01283
01284   /* Fill the structure with the read parameters */
01285   sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
01286   sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
01287   sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01288   sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
01289   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01290   sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
01291   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01292   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01293
01294   if(Format == RTC_FORMAT_BIN)
01295   {
01296     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01297     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01298     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01299     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01300   }
01301
01302   return HAL_OK;
01303 }
01304
01305 /**
01306   * @brief  This function handles Alarm interrupt request.
01307   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01308   *                the configuration information for RTC.
01309   * @retval None
01310   */
01311 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01312 {
01313   if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
01314   {
01315     /* Get the status of the Interrupt */
01316     if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
01317     {
01318       /* AlarmA callback */
01319       HAL_RTC_AlarmAEventCallback(hrtc);
01320
01321       /* Clear the Alarm interrupt pending bit */
01322       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
01323     }
01324   }
01325
01326   if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
01327   {
01328     /* Get the status of the Interrupt */
01329     if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
01330     {
01331       /* AlarmB callback */
01332       HAL_RTCEx_AlarmBEventCallback(hrtc);
01333
01334       /* Clear the Alarm interrupt pending bit */
01335       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
01336     }
01337   }
01338
01339   /* Clear the EXTI's line Flag for RTC Alarm */
01340   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01341
01342   /* Change RTC state */
01343   hrtc->State = HAL_RTC_STATE_READY;
01344 }
01345
01346 /**
01347   * @brief  Alarm A callback.
01348   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01349   *                the configuration information for RTC.
01350   * @retval None
01351   */
01352 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01353 {
01354   /* Prevent unused argument(s) compilation warning */
01355   UNUSED(hrtc);
01356
01357   /* NOTE : This function Should not be modified, when the callback is needed,
01358             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01359    */
01360 }
01361
01362 /**
01363   * @brief  This function handles AlarmA Polling request.
01364   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01365   *                the configuration information for RTC.
01366   * @param  Timeout: Timeout duration
01367   * @retval HAL status
01368   */
01369 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01370 {
01371   uint32_t tickstart = 0;
01372
01373     /* Get tick */
01374     tickstart = HAL_GetTick();
01375
01376   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
01377   {
01378     if(Timeout != HAL_MAX_DELAY)
01379     {
01380       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01381       {
01382         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01383         return HAL_TIMEOUT;
01384       }
01385     }
01386   }
01387
01388   /* Clear the Alarm interrupt pending bit */
01389   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01390
01391   /* Change RTC state */
01392   hrtc->State = HAL_RTC_STATE_READY;
01393
01394   return HAL_OK;
01395 }
01396
01397 /**
01398   * @}
01399   */
01400
01401 /** @defgroup RTC_Group4 Peripheral Control functions
01402  *  @brief   Peripheral Control functions
01403  *
01404 @verbatim
01405  ===============================================================================
01406                      ##### Peripheral Control functions #####
01407  ===============================================================================
01408     [..]
01409     This subsection provides functions allowing to
01410       (+) Wait for RTC Time and Date Synchronization
01411
01412 @endverbatim
01413   * @{
01414   */
01415
01416 /**
01417   * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01418   *         synchronized with RTC APB clock.
01419   * @note   The RTC Resynchronization mode is write protected, use the
01420   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01421   * @note   To read the calendar through the shadow registers after Calendar
01422   *         initialization, calendar update or after wakeup from low power modes
01423   *         the software must first clear the RSF flag.
01424   *         The software must then wait until it is set again before reading
01425   *         the calendar, which means that the calendar registers have been
01426   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01427   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01428   *                the configuration information for RTC.
01429   * @retval HAL status
01430   */
01431 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01432 {
01433   uint32_t tickstart = 0;
01434
01435   /* Clear RSF flag */
01436   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01437
01438     /* Get tick */
01439     tickstart = HAL_GetTick();
01440
01441   /* Wait the registers to be synchronised */
01442   while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
01443   {
01444     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01445     {
01446       return HAL_TIMEOUT;
01447     }
01448   }
01449
01450   return HAL_OK;
01451 }
01452
01453 /**
01454   * @}
01455   */
01456
01457 /** @defgroup RTC_Group5 Peripheral State functions
01458  *  @brief   Peripheral State functions
01459  *
01460 @verbatim
01461  ===============================================================================
01462                      ##### Peripheral State functions #####
01463  ===============================================================================
01464     [..]
01465     This subsection provides functions allowing to
01466       (+) Get RTC state
01467
01468 @endverbatim
01469   * @{
01470   */
01471 /**
01472   * @brief  Returns the RTC state.
01473   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01474   *                the configuration information for RTC.
01475   * @retval HAL state
01476   */
01477 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01478 {
01479   return hrtc->State;
01480 }
01481
01482 /**
01483   * @}
01484   */
01485
01486 /**
01487   * @brief  Enters the RTC Initialization mode.
01488   * @note   The RTC Initialization mode is write protected, use the
01489   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01490   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01491   *                the configuration information for RTC.
01492   * @retval HAL status
01493   */
01494 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01495 {
01496   uint32_t tickstart = 0;
01497
01498   /* Check if the Initialization mode is set */
01499   if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01500   {
01501     /* Set the Initialization mode */
01502     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
01503
01504     /* Get tick */
01505     tickstart = HAL_GetTick();
01506
01507     /* Wait till RTC is in INIT state and if Time out is reached exit */
01508     while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01509     {
01510       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01511       {
01512         return HAL_TIMEOUT;
01513       }
01514     }
01515   }
01516
01517   return HAL_OK;
01518 }
01519
01520
01521 /**
01522   * @brief  Converts a 2 digit decimal to BCD format.
01523   * @param  Value: Byte to be converted
01524   * @retval Converted byte
01525   */
01526 uint8_t RTC_ByteToBcd2(uint8_t Value)
01527 {
01528   uint32_t bcdhigh = 0;
01529
01530   while(Value >= 10)
01531   {
01532     bcdhigh++;
01533     Value -= 10;
01534   }
01535
01536   return  ((uint8_t)(bcdhigh << 4) | Value);
01537 }
01538
01539 /**
01540   * @brief  Converts from 2 digit BCD to Binary.
01541   * @param  Value: BCD value to be converted
01542   * @retval Converted word
01543   */
01544 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01545 {
01546   uint32_t tmp = 0;
01547   tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
01548   return (tmp + (Value & (uint8_t)0x0F));
01549 }
01550
01551 /**
01552   * @}
01553   */
01554
01555 #endif /* HAL_RTC_MODULE_ENABLED */
01556 /**
01557   * @}
01558   */
01559
01560 /**
01561   * @}
01562   */
01563
01564 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc.h Source File

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stm32f7xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of RTC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_RTC_H
00040 #define __STM32F7xx_HAL_RTC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTC_Exported_Types RTC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
00068   HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
00069   HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */
00070   HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */
00071   HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */
00072
00073 }HAL_RTCStateTypeDef;
00074
00075 /**
00076   * @brief  RTC Configuration Structure definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00081                                  This parameter can be a value of @ref RTC_Hour_Formats */
00082
00083   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00084                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00085
00086   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00087                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00088
00089   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00090                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00091
00092   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00093                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00094
00095   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00096                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00097 }RTC_InitTypeDef;
00098
00099 /**
00100   * @brief  RTC Time structure definition
00101   */
00102 typedef struct
00103 {
00104   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00105                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00106                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
00107
00108   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00109                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00110
00111   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00112                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00113
00114   uint32_t SubSeconds;      /*!< Specifies the RTC Time SubSeconds.
00115                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00116
00117   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00118                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00119
00120   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
00121                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00122
00123   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
00124                                  in CR register to store the operation.
00125                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00126 }RTC_TimeTypeDef;
00127
00128 /**
00129   * @brief  RTC Date structure definition
00130   */
00131 typedef struct
00132 {
00133   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00134                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00135
00136   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00137                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00138
00139   uint8_t Date;     /*!< Specifies the RTC Date.
00140                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00141
00142   uint8_t Year;     /*!< Specifies the RTC Date Year.
00143                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00144
00145 }RTC_DateTypeDef;
00146
00147 /**
00148   * @brief  RTC Alarm structure definition
00149   */
00150 typedef struct
00151 {
00152   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00153
00154   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00155                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00156
00157   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00158                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00159
00160   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00161                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00162
00163   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00164                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00165                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00166
00167   uint32_t Alarm;                /*!< Specifies the alarm .
00168                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00169 }RTC_AlarmTypeDef;
00170
00171 /**
00172   * @brief  RTC Handle Structure definition
00173   */
00174 typedef struct
00175 {
00176   RTC_TypeDef                 *Instance;  /*!< Register base address    */
00177
00178   RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
00179
00180   HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
00181
00182   __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
00183
00184 }RTC_HandleTypeDef;
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported constants --------------------------------------------------------*/
00191 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00192   * @{
00193   */
00194
00195 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00196   * @{
00197   */
00198 #define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
00199 #define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
00200 /**
00201   * @}
00202   */
00203
00204
00205 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00206   * @{
00207   */
00208 #define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
00209 #define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00215   * @{
00216   */
00217 #define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
00218 #define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMTYPE)  /* 0x00000008 */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00224   * @{
00225   */
00226 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
00227 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
00233   * @{
00234   */
00235 #define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
00236 #define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
00237 #define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
00243   * @{
00244   */
00245 #define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
00246 #define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00252   * @{
00253   */
00254 #define RTC_FORMAT_BIN                      ((uint32_t)0x000000000)
00255 #define RTC_FORMAT_BCD                      ((uint32_t)0x000000001)
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00261   * @{
00262   */
00263 /* Coded in BCD format */
00264 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
00265 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
00266 #define RTC_MONTH_MARCH                ((uint8_t)0x03)
00267 #define RTC_MONTH_APRIL                ((uint8_t)0x04)
00268 #define RTC_MONTH_MAY                  ((uint8_t)0x05)
00269 #define RTC_MONTH_JUNE                 ((uint8_t)0x06)
00270 #define RTC_MONTH_JULY                 ((uint8_t)0x07)
00271 #define RTC_MONTH_AUGUST               ((uint8_t)0x08)
00272 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
00273 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
00274 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
00275 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00281   * @{
00282   */
00283 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
00284 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
00285 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
00286 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
00287 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
00288 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
00289 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
00295   * @{
00296   */
00297 #define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
00298 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
00304   * @{
00305   */
00306 #define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
00307 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
00308 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
00309 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
00310 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
00311 #define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00317   * @{
00318   */
00319 #define RTC_ALARM_A                       RTC_CR_ALRAE
00320 #define RTC_ALARM_B                       RTC_CR_ALRBE
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00326   * @{
00327   */
00328 #define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked.
00329                                                                         There is no comparison on sub seconds
00330                                                                         for Alarm */
00331 #define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm
00332                                                                         comparison. Only SS[0] is compared.    */
00333 #define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm
00334                                                                         comparison. Only SS[1:0] are compared  */
00335 #define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm
00336                                                                         comparison. Only SS[2:0] are compared  */
00337 #define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm
00338                                                                         comparison. Only SS[3:0] are compared  */
00339 #define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm
00340                                                                         comparison. Only SS[4:0] are compared  */
00341 #define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm
00342                                                                         comparison. Only SS[5:0] are compared  */
00343 #define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm
00344                                                                         comparison. Only SS[6:0] are compared  */
00345 #define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm
00346                                                                         comparison. Only SS[7:0] are compared  */
00347 #define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm
00348                                                                         comparison. Only SS[8:0] are compared  */
00349 #define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm
00350                                                                         comparison. Only SS[9:0] are compared  */
00351 #define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm
00352                                                                         comparison. Only SS[10:0] are compared */
00353 #define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm
00354                                                                         comparison.Only SS[11:0] are compared  */
00355 #define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm
00356                                                                         comparison. Only SS[12:0] are compared */
00357 #define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm
00358                                                                         comparison.Only SS[13:0] are compared  */
00359 #define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match
00360                                                                         to activate alarm. */
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00366   * @{
00367   */
00368 #define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)
00369 #define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)
00370 #define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)
00371 #define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)
00372 #define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
00373 #define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE)
00374 #define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE)
00375 #define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE)
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00381   * @{
00382   */
00383 #define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
00384 #define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
00385 #define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
00386 #define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
00387 #define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
00388 #define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
00389 #define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
00390 #define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
00391 #define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
00392 #define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
00393 #define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
00394 #define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
00395 #define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
00396 #define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
00397 #define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
00398 #define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
00399 #define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
00400 /**
00401   * @}
00402   */
00403
00404 /**
00405   * @}
00406   */
00407
00408 /* Exported macro ------------------------------------------------------------*/
00409 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00410   * @{
00411   */
00412
00413 /** @brief Reset RTC handle state
00414   * @param  __HANDLE__: specifies the RTC handle.
00415   * @retval None
00416   */
00417 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00418
00419 /**
00420   * @brief  Disable the write protection for RTC registers.
00421   * @param  __HANDLE__: specifies the RTC handle.
00422   * @retval None
00423   */
00424 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00425                         do{                                       \
00426                             (__HANDLE__)->Instance->WPR = 0xCA;   \
00427                             (__HANDLE__)->Instance->WPR = 0x53;   \
00428                           } while(0)
00429
00430 /**
00431   * @brief  Enable the write protection for RTC registers.
00432   * @param  __HANDLE__: specifies the RTC handle.
00433   * @retval None
00434   */
00435 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00436                         do{                                       \
00437                             (__HANDLE__)->Instance->WPR = 0xFF;   \
00438                           } while(0)
00439
00440 /**
00441   * @brief  Enable the RTC ALARMA peripheral.
00442   * @param  __HANDLE__: specifies the RTC handle.
00443   * @retval None
00444   */
00445 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00446
00447 /**
00448   * @brief  Disable the RTC ALARMA peripheral.
00449   * @param  __HANDLE__: specifies the RTC handle.
00450   * @retval None
00451   */
00452 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00453
00454 /**
00455   * @brief  Enable the RTC ALARMB peripheral.
00456   * @param  __HANDLE__: specifies the RTC handle.
00457   * @retval None
00458   */
00459 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00460
00461 /**
00462   * @brief  Disable the RTC ALARMB peripheral.
00463   * @param  __HANDLE__: specifies the RTC handle.
00464   * @retval None
00465   */
00466 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00467
00468 /**
00469   * @brief  Enable the RTC Alarm interrupt.
00470   * @param  __HANDLE__: specifies the RTC handle.
00471   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00472   *          This parameter can be any combination of the following values:
00473   *             @arg RTC_IT_ALRA: Alarm A interrupt
00474   *             @arg RTC_IT_ALRB: Alarm B interrupt
00475   * @retval None
00476   */
00477 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00478
00479 /**
00480   * @brief  Disable the RTC Alarm interrupt.
00481   * @param  __HANDLE__: specifies the RTC handle.
00482   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00483   *         This parameter can be any combination of the following values:
00484   *            @arg RTC_IT_ALRA: Alarm A interrupt
00485   *            @arg RTC_IT_ALRB: Alarm B interrupt
00486   * @retval None
00487   */
00488 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00489
00490 /**
00491   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00492   * @param  __HANDLE__: specifies the RTC handle.
00493   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
00494   *         This parameter can be:
00495   *            @arg RTC_IT_ALRA: Alarm A interrupt
00496   *            @arg RTC_IT_ALRB: Alarm B interrupt
00497   * @retval None
00498   */
00499 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)                  ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
00500
00501 /**
00502   * @brief  Get the selected RTC Alarm's flag status.
00503   * @param  __HANDLE__: specifies the RTC handle.
00504   * @param  __FLAG__: specifies the RTC Alarm Flag to check.
00505   *         This parameter can be:
00506   *            @arg RTC_FLAG_ALRAF
00507   *            @arg RTC_FLAG_ALRBF
00508   *            @arg RTC_FLAG_ALRAWF
00509   *            @arg RTC_FLAG_ALRBWF
00510   * @retval None
00511   */
00512 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00513
00514 /**
00515   * @brief  Clear the RTC Alarm's pending flags.
00516   * @param  __HANDLE__: specifies the RTC handle.
00517   * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
00518   *          This parameter can be:
00519   *             @arg RTC_FLAG_ALRAF
00520   *             @arg RTC_FLAG_ALRBF
00521   * @retval None
00522   */
00523 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00524
00525 /**
00526   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00527   * @param  __HANDLE__: specifies the RTC handle.
00528   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00529   *         This parameter can be:
00530   *            @arg RTC_IT_ALRA: Alarm A interrupt
00531   *            @arg RTC_IT_ALRB: Alarm B interrupt
00532   * @retval None
00533   */
00534 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00535
00536 /**
00537   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00538   * @retval None
00539   */
00540 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
00541
00542 /**
00543   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00544   * @retval None
00545   */
00546 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00547
00548 /**
00549   * @brief  Enable event on the RTC Alarm associated Exti line.
00550   * @retval None.
00551   */
00552 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
00553
00554 /**
00555   * @brief  Disable event on the RTC Alarm associated Exti line.
00556   * @retval None.
00557   */
00558 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00559
00560 /**
00561   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00562   * @retval None.
00563   */
00564 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
00565
00566 /**
00567   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00568   * @retval None.
00569   */
00570 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00571
00572 /**
00573   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00574   * @retval None.
00575   */
00576 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
00577
00578 /**
00579   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00580   * @retval None.
00581   */
00582 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00583
00584 /**
00585   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00586   * @retval None.
00587   */
00588 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
00589
00590 /**
00591   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00592   * @retval None.
00593   */
00594 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
00595
00596 /**
00597   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
00598   * @retval Line Status.
00599   */
00600 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
00601
00602 /**
00603   * @brief Clear the RTC Alarm associated Exti line flag.
00604   * @retval None.
00605   */
00606 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
00607
00608 /**
00609   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00610   * @retval None.
00611   */
00612 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
00613 /**
00614   * @}
00615   */
00616
00617 /* Include RTC HAL Extension module */
00618 #include "stm32f7xx_hal_rtc_ex.h"
00619
00620 /* Exported functions --------------------------------------------------------*/
00621 /** @addtogroup RTC_Exported_Functions
00622   * @{
00623   */
00624
00625 /** @addtogroup RTC_Exported_Functions_Group1
00626   * @{
00627   */
00628 /* Initialization and de-initialization functions  ****************************/
00629 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00630 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00631 void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00632 void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00633 /**
00634   * @}
00635   */
00636
00637 /** @addtogroup RTC_Exported_Functions_Group2
00638   * @{
00639   */
00640 /* RTC Time and Date functions ************************************************/
00641 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00642 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00643 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00644 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00645 /**
00646   * @}
00647   */
00648
00649 /** @addtogroup RTC_Exported_Functions_Group3
00650   * @{
00651   */
00652 /* RTC Alarm functions ********************************************************/
00653 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00654 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00655 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00656 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00657 void                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00658 HAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00659 void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00660 /**
00661   * @}
00662   */
00663
00664 /** @addtogroup RTC_Exported_Functions_Group4
00665   * @{
00666   */
00667 /* Peripheral Control functions ***********************************************/
00668 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00669 /**
00670   * @}
00671   */
00672
00673 /** @addtogroup RTC_Exported_Functions_Group5
00674   * @{
00675   */
00676 /* Peripheral State functions *************************************************/
00677 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /* Private types -------------------------------------------------------------*/
00687 /* Private variables ---------------------------------------------------------*/
00688 /* Private constants ---------------------------------------------------------*/
00689 /** @defgroup RTC_Private_Constants RTC Private Constants
00690   * @{
00691   */
00692 /* Masks Definition */
00693 #define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
00694 #define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F)
00695 #define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)
00696 #define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
00697
00698 #define RTC_TIMEOUT_VALUE       1000
00699
00700 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
00701 /**
00702   * @}
00703   */
00704
00705 /* Private macros ------------------------------------------------------------*/
00706 /** @defgroup RTC_Private_Macros RTC Private Macros
00707   * @{
00708   */
00709
00710 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00711   * @{
00712   */
00713 #define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \
00714                                         ((__FORMAT__) == RTC_HOURFORMAT_24))
00715 #define IS_RTC_OUTPUT_POL(__POL__)     (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \
00716                                         ((__POL__) == RTC_OUTPUT_POLARITY_LOW))
00717 #define IS_RTC_OUTPUT_TYPE(__TYPE__)   (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00718                                         ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))
00719 #define IS_RTC_ASYNCH_PREDIV(__PREDIV__)   ((__PREDIV__) <= (uint32_t)0x7F)
00720 #define IS_RTC_SYNCH_PREDIV(__PREDIV__)    ((__PREDIV__) <= (uint32_t)0x7FFF)
00721 #define IS_RTC_HOUR12(__HOUR__)            (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))
00722 #define IS_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= (uint32_t)23)
00723 #define IS_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= (uint32_t)59)
00724 #define IS_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= (uint32_t)59)
00725 #define IS_RTC_HOURFORMAT12(__PM__)  (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
00726 #define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
00727                                           ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
00728                                           ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))
00729 #define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
00730                                                ((__OPERATION__) == RTC_STOREOPERATION_SET))
00731 #define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
00732 #define IS_RTC_YEAR(__YEAR__)              ((__YEAR__) <= (uint32_t)99)
00733 #define IS_RTC_MONTH(__MONTH__)            (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))
00734 #define IS_RTC_DATE(__DATE__)              (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))
00735 #define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
00736                                      ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
00737                                      ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
00738                                      ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
00739                                      ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
00740                                      ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
00741                                      ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
00742
00743 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))
00744 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
00745                                                         ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
00746                                                         ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
00747                                                         ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
00748                                                         ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
00749                                                         ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
00750                                                         ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
00751 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00752                                                 ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00753 #define IS_RTC_ALARM_MASK(__MASK__)  (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)
00754 #define IS_RTC_ALARM(__ALARM__)      (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
00755 #define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)
00756 #define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__)   (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
00757                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00758                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00759                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00760                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00761                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00762                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00763                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00764                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00765                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00766                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00767                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00768                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00769                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00770                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \
00771                                                   ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))
00772
00773 /**
00774   * @}
00775   */
00776
00777 /**
00778   * @}
00779   */
00780
00781 /* Private functions ---------------------------------------------------------*/
00782 /** @defgroup RTC_Private_Functions RTC Private Functions
00783   * @{
00784   */
00785 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00786 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00787 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00788 /**
00789   * @}
00790   */
00791
00792 /**
00793   * @}
00794   */
00795
00796 /**
00797   * @}
00798   */
00799
00800 #ifdef __cplusplus
00801 }
00802 #endif
00803
00804 #endif /* __STM32F7xx_HAL_RTC_H */
00805
00806 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc_ex.c Source File

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stm32f7xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
00010   *           + RTC Time Stamp functions
00011   *           + RTC Tamper functions
00012   *           + RTC Wake-up functions
00013   *           + Extension Control functions
00014   *           + Extension RTC features functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                   ##### How to use this driver #####
00019   ==============================================================================
00020   [..]
00021     (+) Enable the RTC domain access.
00022     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00023         format using the HAL_RTC_Init() function.
00024
00025   *** RTC Wakeup configuration ***
00026   ================================
00027   [..]
00028     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
00029         function. You can also configure the RTC Wakeup timer in interrupt mode
00030         using the HAL_RTC_SetWakeUpTimer_IT() function.
00031     (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
00032         function.
00033
00034   *** TimeStamp configuration ***
00035   ===============================
00036   [..]
00037     (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.
00038         You can also configure the RTC TimeStamp with interrupt mode using the
00039         HAL_RTC_SetTimeStamp_IT() function.
00040     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
00041         function.
00042
00043   *** Internal TimeStamp configuration ***
00044   ===============================
00045   [..]
00046     (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.
00047     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
00048         function.
00049
00050   *** Tamper configuration ***
00051   ============================
00052   [..]
00053     (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
00054         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00055         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00056         Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper
00057         with interrupt mode using HAL_RTC_SetTamper_IT() function.
00058     (+) The default configuration of the Tamper erases the backup registers. To avoid
00059         erase, enable the NoErase field on the RTC_TAMPCR register.
00060
00061   *** Backup Data Registers configuration ***
00062   ===========================================
00063   [..]
00064     (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
00065         function.
00066     (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
00067         function.
00068
00069    @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f7xx_hal.h"
00102
00103 /** @addtogroup STM32F7xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup RTCEx RTCEx
00108   * @brief RTC Extended HAL module driver
00109   * @{
00110   */
00111
00112 #ifdef HAL_RTC_MODULE_ENABLED
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Private functions ---------------------------------------------------------*/
00120
00121 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00122   * @{
00123   */
00124
00125
00126 /** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
00127  *  @brief   RTC TimeStamp and Tamper functions
00128  *
00129 @verbatim
00130  ===============================================================================
00131                  ##### RTC TimeStamp and Tamper functions #####
00132  ===============================================================================
00133
00134  [..] This section provides functions allowing to configure TimeStamp feature
00135
00136 @endverbatim
00137   * @{
00138   */
00139
00140 /**
00141   * @brief  Sets TimeStamp.
00142   * @note   This API must be called before enabling the TimeStamp feature.
00143   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00144   *                the configuration information for RTC.
00145   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00146   *         activated.
00147   *          This parameter can be one of the following values:
00148   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00149   *                                        rising edge of the related pin.
00150   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00151   *                                         falling edge of the related pin.
00152   * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
00153   *          This parameter can be one of the following values:
00154   *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
00155   *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
00156   *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00160 {
00161   uint32_t tmpreg = 0;
00162
00163   /* Check the parameters */
00164   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00165   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00166
00167   /* Process Locked */
00168   __HAL_LOCK(hrtc);
00169
00170   hrtc->State = HAL_RTC_STATE_BUSY;
00171
00172   /* Get the RTC_CR register and clear the bits to be configured */
00173   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00174
00175   tmpreg|= TimeStampEdge;
00176
00177   /* Disable the write protection for RTC registers */
00178   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00179
00180   hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
00181   hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
00182
00183   /* Configure the Time Stamp TSEDGE and Enable bits */
00184   hrtc->Instance->CR = (uint32_t)tmpreg;
00185
00186   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00187
00188   /* Enable the write protection for RTC registers */
00189   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00190
00191   /* Change RTC state */
00192   hrtc->State = HAL_RTC_STATE_READY;
00193
00194   /* Process Unlocked */
00195   __HAL_UNLOCK(hrtc);
00196
00197   return HAL_OK;
00198 }
00199
00200 /**
00201   * @brief  Sets TimeStamp with Interrupt.
00202   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00203   *                the configuration information for RTC.
00204   * @note   This API must be called before enabling the TimeStamp feature.
00205   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00206   *         activated.
00207   *          This parameter can be one of the following values:
00208   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00209   *                                        rising edge of the related pin.
00210   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00211   *                                         falling edge of the related pin.
00212   * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
00213   *          This parameter can be one of the following values:
00214   *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
00215   *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
00216   *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00220 {
00221   uint32_t tmpreg = 0;
00222
00223   /* Check the parameters */
00224   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00225   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00226
00227   /* Process Locked */
00228   __HAL_LOCK(hrtc);
00229
00230   hrtc->State = HAL_RTC_STATE_BUSY;
00231
00232   /* Get the RTC_CR register and clear the bits to be configured */
00233   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00234
00235   tmpreg |= TimeStampEdge;
00236
00237   /* Disable the write protection for RTC registers */
00238   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00239
00240   /* Configure the Time Stamp TSEDGE and Enable bits */
00241   hrtc->Instance->CR = (uint32_t)tmpreg;
00242
00243   hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
00244   hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
00245
00246   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00247
00248   /* Enable IT timestamp */
00249   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00250
00251   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00252   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00253
00254   EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
00255
00256   /* Enable the write protection for RTC registers */
00257   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00258
00259   hrtc->State = HAL_RTC_STATE_READY;
00260
00261   /* Process Unlocked */
00262   __HAL_UNLOCK(hrtc);
00263
00264   return HAL_OK;
00265 }
00266
00267 /**
00268   * @brief  Deactivates TimeStamp.
00269   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00270   *                the configuration information for RTC.
00271   * @retval HAL status
00272   */
00273 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00274 {
00275   uint32_t tmpreg = 0;
00276
00277   /* Process Locked */
00278   __HAL_LOCK(hrtc);
00279
00280   hrtc->State = HAL_RTC_STATE_BUSY;
00281
00282   /* Disable the write protection for RTC registers */
00283   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00284
00285   /* In case of interrupt mode is used, the interrupt source must disabled */
00286   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00287
00288   /* Get the RTC_CR register and clear the bits to be configured */
00289   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00290
00291   /* Configure the Time Stamp TSEDGE and Enable bits */
00292   hrtc->Instance->CR = (uint32_t)tmpreg;
00293
00294   /* Enable the write protection for RTC registers */
00295   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00296
00297   hrtc->State = HAL_RTC_STATE_READY;
00298
00299   /* Process Unlocked */
00300   __HAL_UNLOCK(hrtc);
00301
00302   return HAL_OK;
00303 }
00304
00305 /**
00306   * @brief  Sets Internal TimeStamp.
00307   * @note   This API must be called before enabling the internal TimeStamp feature.
00308   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00309   *                the configuration information for RTC.
00310   * @retval HAL status
00311   */
00312 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00313 {
00314   /* Process Locked */
00315   __HAL_LOCK(hrtc);
00316
00317   hrtc->State = HAL_RTC_STATE_BUSY;
00318
00319   /* Disable the write protection for RTC registers */
00320   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00321
00322   /* Configure the internal Time Stamp Enable bits */
00323   __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
00324
00325   /* Enable the write protection for RTC registers */
00326   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00327
00328   /* Change RTC state */
00329   hrtc->State = HAL_RTC_STATE_READY;
00330
00331   /* Process Unlocked */
00332   __HAL_UNLOCK(hrtc);
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  Deactivates internal TimeStamp.
00339   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00340   *                the configuration information for RTC.
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00344 {
00345   /* Process Locked */
00346   __HAL_LOCK(hrtc);
00347
00348   hrtc->State = HAL_RTC_STATE_BUSY;
00349
00350   /* Disable the write protection for RTC registers */
00351   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00352
00353   /* Configure the internal Time Stamp Enable bits */
00354   __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
00355
00356   /* Enable the write protection for RTC registers */
00357   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00358
00359   hrtc->State = HAL_RTC_STATE_READY;
00360
00361   /* Process Unlocked */
00362   __HAL_UNLOCK(hrtc);
00363
00364   return HAL_OK;
00365 }
00366
00367 /**
00368   * @brief  Gets the RTC TimeStamp value.
00369   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00370   *                the configuration information for RTC.
00371   * @param  sTimeStamp: Pointer to Time structure
00372   * @param  sTimeStampDate: Pointer to Date structure
00373   * @param  Format: specifies the format of the entered parameters.
00374   *          This parameter can be one of the following values:
00375   *             FORMAT_BIN: Binary data format
00376   *             FORMAT_BCD: BCD data format
00377   * @retval HAL status
00378   */
00379 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00380 {
00381   uint32_t tmptime = 0, tmpdate = 0;
00382
00383   /* Check the parameters */
00384   assert_param(IS_RTC_FORMAT(Format));
00385
00386   /* Get the TimeStamp time and date registers values */
00387   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00388   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00389
00390   /* Fill the Time structure fields with the read parameters */
00391   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00392   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
00393   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
00394   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
00395   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00396
00397   /* Fill the Date structure fields with the read parameters */
00398   sTimeStampDate->Year = 0;
00399   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
00400   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00401   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
00402
00403   /* Check the input parameters format */
00404   if(Format == RTC_FORMAT_BIN)
00405   {
00406     /* Convert the TimeStamp structure parameters to Binary format */
00407     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00408     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00409     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00410
00411     /* Convert the DateTimeStamp structure parameters to Binary format */
00412     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00413     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00414     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00415   }
00416
00417   /* Clear the TIMESTAMP Flag */
00418   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00419
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief  Sets Tamper
00425   * @note   By calling this API we disable the tamper interrupt for all tampers.
00426   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00427   *                the configuration information for RTC.
00428   * @param  sTamper: Pointer to Tamper Structure.
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00432 {
00433   uint32_t tmpreg = 0;
00434
00435   /* Check the parameters */
00436   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00437   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00438   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00439   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00440   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00441   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00442   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00443   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00444   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00445
00446   /* Process Locked */
00447   __HAL_LOCK(hrtc);
00448
00449   hrtc->State = HAL_RTC_STATE_BUSY;
00450
00451   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00452   {
00453     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
00454   }
00455
00456   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00457   {
00458     sTamper->NoErase = 0;
00459     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00460     {
00461       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00462     }
00463     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00464     {
00465       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00466     }
00467     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00468     {
00469       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00470     }
00471   }
00472
00473   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00474   {
00475     sTamper->MaskFlag = 0;
00476     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00477     {
00478       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00479     }
00480     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00481     {
00482       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00483     }
00484     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00485     {
00486       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00487     }
00488   }
00489
00490   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00491             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00492             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00493
00494   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
00495                                        (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00496                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
00497                                        (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
00498                                        (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
00499                                        (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
00500
00501   hrtc->Instance->TAMPCR |= tmpreg;
00502
00503   hrtc->State = HAL_RTC_STATE_READY;
00504
00505   /* Process Unlocked */
00506   __HAL_UNLOCK(hrtc);
00507
00508   return HAL_OK;
00509 }
00510
00511 /**
00512   * @brief  Sets Tamper with interrupt.
00513   * @note   By calling this API we force the tamper interrupt for all tampers.
00514   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00515   *                the configuration information for RTC.
00516   * @param  sTamper: Pointer to RTC Tamper.
00517   * @retval HAL status
00518   */
00519 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00520 {
00521   uint32_t tmpreg = 0;
00522
00523   /* Check the parameters */
00524   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00525   assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
00526   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00527   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00528   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00529   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00530   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00531   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00532   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00533   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00534
00535   /* Process Locked */
00536   __HAL_LOCK(hrtc);
00537
00538   hrtc->State = HAL_RTC_STATE_BUSY;
00539
00540   /* Configure the tamper trigger */
00541   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00542   {
00543     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
00544   }
00545
00546   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00547   {
00548     sTamper->NoErase = 0;
00549     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00550     {
00551       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00552     }
00553     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00554     {
00555       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00556     }
00557     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00558     {
00559       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00560     }
00561   }
00562
00563   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00564   {
00565     sTamper->MaskFlag = 0;
00566     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00567     {
00568       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00569     }
00570     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00571     {
00572       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00573     }
00574     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00575     {
00576       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00577     }
00578   }
00579
00580   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00581             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00582             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00583
00584   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
00585                                        (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00586                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
00587                                        (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
00588                                        (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
00589                                        (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
00590
00591   hrtc->Instance->TAMPCR |= tmpreg;
00592
00593   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00594   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00595
00596   EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
00597
00598   hrtc->State = HAL_RTC_STATE_READY;
00599
00600   /* Process Unlocked */
00601   __HAL_UNLOCK(hrtc);
00602
00603   return HAL_OK;
00604 }
00605
00606 /**
00607   * @brief  Deactivates Tamper.
00608   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00609   *                the configuration information for RTC.
00610   * @param  Tamper: Selected tamper pin.
00611   *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
00612   * @retval HAL status
00613   */
00614 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00615 {
00616   assert_param(IS_RTC_TAMPER(Tamper));
00617
00618   /* Process Locked */
00619   __HAL_LOCK(hrtc);
00620
00621   hrtc->State = HAL_RTC_STATE_BUSY;
00622
00623 /* Disable the selected Tamper pin */
00624   hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;
00625
00626   if ((Tamper & RTC_TAMPER_1) != 0)
00627   {
00628     /* Disable the Tamper1 interrupt */
00629     hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);
00630   }
00631   if ((Tamper & RTC_TAMPER_2) != 0)
00632   {
00633     /* Disable the Tamper2 interrupt */
00634     hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);
00635   }
00636   if ((Tamper & RTC_TAMPER_3) != 0)
00637   {
00638     /* Disable the Tamper2 interrupt */
00639     hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3);
00640   }
00641
00642   hrtc->State = HAL_RTC_STATE_READY;
00643
00644   /* Process Unlocked */
00645   __HAL_UNLOCK(hrtc);
00646
00647   return HAL_OK;
00648 }
00649
00650 /**
00651   * @brief  This function handles TimeStamp interrupt request.
00652   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00653   *                the configuration information for RTC.
00654   * @retval None
00655   */
00656 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00657 {
00658   if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
00659   {
00660     /* Get the status of the Interrupt */
00661     if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
00662     {
00663        /* TIMESTAMP callback */
00664         HAL_RTCEx_TimeStampEventCallback(hrtc);
00665
00666       /* Clear the TIMESTAMP interrupt pending bit */
00667       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
00668     }
00669   }
00670
00671   /* Get the status of the Interrupt */
00672   if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)
00673   {
00674     /* Get the TAMPER Interrupt enable bit and pending bit */
00675     if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
00676        (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))
00677     {
00678       /* Tamper callback */
00679       HAL_RTCEx_Tamper1EventCallback(hrtc);
00680
00681       /* Clear the Tamper interrupt pending bit */
00682       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00683     }
00684   }
00685
00686   /* Get the status of the Interrupt */
00687   if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)
00688   {
00689     /* Get the TAMPER Interrupt enable bit and pending bit */
00690     if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
00691        (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))
00692     {
00693       /* Tamper callback */
00694       HAL_RTCEx_Tamper2EventCallback(hrtc);
00695
00696       /* Clear the Tamper interrupt pending bit */
00697       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00698     }
00699   }
00700
00701   /* Get the status of the Interrupt */
00702   if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)
00703   {
00704     /* Get the TAMPER Interrupt enable bit and pending bit */
00705     if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
00706        (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))
00707     {
00708       /* Tamper callback */
00709       HAL_RTCEx_Tamper3EventCallback(hrtc);
00710
00711       /* Clear the Tamper interrupt pending bit */
00712       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00713     }
00714   }
00715
00716   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
00717   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
00718
00719   /* Change RTC state */
00720   hrtc->State = HAL_RTC_STATE_READY;
00721 }
00722
00723 /**
00724   * @brief  TimeStamp callback.
00725   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00726   *                the configuration information for RTC.
00727   * @retval None
00728   */
00729 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00730 {
00731   /* Prevent unused argument(s) compilation warning */
00732   UNUSED(hrtc);
00733
00734   /* NOTE : This function Should not be modified, when the callback is needed,
00735             the HAL_RTC_TimeStampEventCallback could be implemented in the user file
00736   */
00737 }
00738
00739 /**
00740   * @brief  Tamper 1 callback.
00741   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00742   *                the configuration information for RTC.
00743   * @retval None
00744   */
00745 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00746 {
00747   /* Prevent unused argument(s) compilation warning */
00748   UNUSED(hrtc);
00749
00750   /* NOTE : This function Should not be modified, when the callback is needed,
00751             the HAL_RTC_Tamper1EventCallback could be implemented in the user file
00752    */
00753 }
00754
00755 /**
00756   * @brief  Tamper 2 callback.
00757   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00758   *                the configuration information for RTC.
00759   * @retval None
00760   */
00761 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
00762 {
00763   /* Prevent unused argument(s) compilation warning */
00764   UNUSED(hrtc);
00765
00766   /* NOTE : This function Should not be modified, when the callback is needed,
00767             the HAL_RTC_Tamper2EventCallback could be implemented in the user file
00768    */
00769 }
00770
00771 /**
00772   * @brief  Tamper 3 callback.
00773   * @param  hrtc: RTC handle
00774   * @retval None
00775   */
00776 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
00777 {
00778   /* Prevent unused argument(s) compilation warning */
00779   UNUSED(hrtc);
00780
00781   /* NOTE : This function Should not be modified, when the callback is needed,
00782             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
00783    */
00784 }
00785
00786 /**
00787   * @brief  This function handles TimeStamp polling request.
00788   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00789   *                the configuration information for RTC.
00790   * @param  Timeout: Timeout duration
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00794 {
00795   uint32_t tickstart = 0;
00796
00797   /* Get tick */
00798   tickstart = HAL_GetTick();
00799
00800   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
00801   {
00802     if(Timeout != HAL_MAX_DELAY)
00803     {
00804       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00805       {
00806         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00807         return HAL_TIMEOUT;
00808       }
00809     }
00810   }
00811
00812   if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
00813   {
00814     /* Clear the TIMESTAMP OverRun Flag */
00815     __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00816
00817     /* Change TIMESTAMP state */
00818     hrtc->State = HAL_RTC_STATE_ERROR;
00819
00820     return HAL_ERROR;
00821    }
00822
00823   /* Change RTC state */
00824   hrtc->State = HAL_RTC_STATE_READY;
00825
00826   return HAL_OK;
00827 }
00828
00829 /**
00830   * @brief  This function handles Tamper1 Polling.
00831   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00832   *                the configuration information for RTC.
00833   * @param  Timeout: Timeout duration
00834   * @retval HAL status
00835   */
00836 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00837 {
00838   uint32_t tickstart = 0;
00839
00840   /* Get tick */
00841   tickstart = HAL_GetTick();
00842
00843   /* Get the status of the Interrupt */
00844   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
00845   {
00846     if(Timeout != HAL_MAX_DELAY)
00847     {
00848       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00849       {
00850         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00851         return HAL_TIMEOUT;
00852       }
00853     }
00854   }
00855
00856   /* Clear the Tamper Flag */
00857   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00858
00859   /* Change RTC state */
00860   hrtc->State = HAL_RTC_STATE_READY;
00861
00862   return HAL_OK;
00863 }
00864
00865 /**
00866   * @brief  This function handles Tamper2 Polling.
00867   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00868   *                the configuration information for RTC.
00869   * @param  Timeout: Timeout duration
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00873 {
00874   uint32_t tickstart = 0;
00875
00876   /* Get tick */
00877   tickstart = HAL_GetTick();
00878
00879   /* Get the status of the Interrupt */
00880   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
00881   {
00882     if(Timeout != HAL_MAX_DELAY)
00883     {
00884       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00885       {
00886         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00887         return HAL_TIMEOUT;
00888       }
00889     }
00890   }
00891
00892   /* Clear the Tamper Flag */
00893   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
00894
00895   /* Change RTC state */
00896   hrtc->State = HAL_RTC_STATE_READY;
00897
00898   return HAL_OK;
00899 }
00900
00901 /**
00902   * @brief  This function handles Tamper3 Polling.
00903   * @param  hrtc: RTC handle
00904   * @param  Timeout: Timeout duration
00905   * @retval HAL status
00906   */
00907 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00908 {
00909   uint32_t tickstart = HAL_GetTick();
00910
00911   /* Get the status of the Interrupt */
00912   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
00913   {
00914     if(Timeout != HAL_MAX_DELAY)
00915     {
00916       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00917       {
00918         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00919         return HAL_TIMEOUT;
00920       }
00921     }
00922   }
00923
00924   /* Clear the Tamper Flag */
00925   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
00926
00927   /* Change RTC state */
00928   hrtc->State = HAL_RTC_STATE_READY;
00929
00930   return HAL_OK;
00931 }
00932
00933 /**
00934   * @}
00935   */
00936
00937 /** @defgroup RTCEx_Group2 RTC Wake-up functions
00938  *  @brief   RTC Wake-up functions
00939  *
00940 @verbatim
00941  ===============================================================================
00942                         ##### RTC Wake-up functions #####
00943  ===============================================================================
00944
00945  [..] This section provides functions allowing to configure Wake-up feature
00946
00947 @endverbatim
00948   * @{
00949   */
00950
00951 /**
00952   * @brief  Sets wake up timer.
00953   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00954   *                the configuration information for RTC.
00955   * @param  WakeUpCounter: Wake up counter
00956   * @param  WakeUpClock: Wake up clock
00957   * @retval HAL status
00958   */
00959 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00960 {
00961   uint32_t tickstart = 0;
00962
00963   /* Check the parameters */
00964   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00965   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00966
00967   /* Process Locked */
00968   __HAL_LOCK(hrtc);
00969
00970   hrtc->State = HAL_RTC_STATE_BUSY;
00971
00972   /* Disable the write protection for RTC registers */
00973   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00974
00975   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00976
00977   /* Get tick */
00978   tickstart = HAL_GetTick();
00979
00980   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
00981   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
00982   {
00983     /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00984     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00985     {
00986       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00987       {
00988         /* Enable the write protection for RTC registers */
00989         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00990
00991         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00992
00993         /* Process Unlocked */
00994         __HAL_UNLOCK(hrtc);
00995
00996         return HAL_TIMEOUT;
00997       }
00998     }
00999   }
01000
01001   /* Clear the Wakeup Timer clock source bits in CR register */
01002   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01003
01004   /* Configure the clock source */
01005   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01006
01007   /* Configure the Wakeup Timer counter */
01008   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01009
01010    /* Enable the Wakeup Timer */
01011   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01012
01013   /* Enable the write protection for RTC registers */
01014   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01015
01016   hrtc->State = HAL_RTC_STATE_READY;
01017
01018   /* Process Unlocked */
01019   __HAL_UNLOCK(hrtc);
01020
01021   return HAL_OK;
01022 }
01023
01024 /**
01025   * @brief  Sets wake up timer with interrupt
01026   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01027   *                the configuration information for RTC.
01028   * @param  WakeUpCounter: Wake up counter
01029   * @param  WakeUpClock: Wake up clock
01030   * @retval HAL status
01031   */
01032 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
01033 {
01034   uint32_t tickstart = 0;
01035
01036   /* Check the parameters */
01037   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01038   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01039
01040   /* Process Locked */
01041   __HAL_LOCK(hrtc);
01042
01043   hrtc->State = HAL_RTC_STATE_BUSY;
01044
01045   /* Disable the write protection for RTC registers */
01046   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01047
01048   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01049
01050   /* Get tick */
01051   tickstart = HAL_GetTick();
01052
01053     /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
01054   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
01055   {
01056     /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01057     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01058     {
01059       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01060       {
01061         /* Enable the write protection for RTC registers */
01062         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01063
01064         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01065
01066         /* Process Unlocked */
01067         __HAL_UNLOCK(hrtc);
01068
01069         return HAL_TIMEOUT;
01070       }
01071     }
01072   }
01073
01074   /* Configure the Wakeup Timer counter */
01075   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01076
01077   /* Clear the Wakeup Timer clock source bits in CR register */
01078   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01079
01080   /* Configure the clock source */
01081   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01082
01083   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
01084   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
01085
01086   EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
01087
01088   /* Configure the Interrupt in the RTC_CR register */
01089   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
01090
01091   /* Enable the Wakeup Timer */
01092   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01093
01094   /* Enable the write protection for RTC registers */
01095   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01096
01097   hrtc->State = HAL_RTC_STATE_READY;
01098
01099   /* Process Unlocked */
01100   __HAL_UNLOCK(hrtc);
01101
01102   return HAL_OK;
01103 }
01104
01105 /**
01106   * @brief  Deactivates wake up timer counter.
01107   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01108   *                the configuration information for RTC.
01109   * @retval HAL status
01110   */
01111 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
01112 {
01113   uint32_t tickstart = 0;
01114
01115   /* Process Locked */
01116   __HAL_LOCK(hrtc);
01117
01118   hrtc->State = HAL_RTC_STATE_BUSY;
01119
01120   /* Disable the write protection for RTC registers */
01121   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01122
01123   /* Disable the Wakeup Timer */
01124   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01125
01126   /* In case of interrupt mode is used, the interrupt source must disabled */
01127   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
01128
01129   /* Get tick */
01130   tickstart = HAL_GetTick();
01131
01132   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01133   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01134   {
01135     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01136     {
01137       /* Enable the write protection for RTC registers */
01138       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01139
01140       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01141
01142       /* Process Unlocked */
01143       __HAL_UNLOCK(hrtc);
01144
01145       return HAL_TIMEOUT;
01146     }
01147   }
01148
01149   /* Enable the write protection for RTC registers */
01150   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01151
01152   hrtc->State = HAL_RTC_STATE_READY;
01153
01154   /* Process Unlocked */
01155   __HAL_UNLOCK(hrtc);
01156
01157   return HAL_OK;
01158 }
01159
01160 /**
01161   * @brief  Gets wake up timer counter.
01162   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01163   *                the configuration information for RTC.
01164   * @retval Counter value
01165   */
01166 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
01167 {
01168   /* Get the counter value */
01169   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
01170 }
01171
01172 /**
01173   * @brief  This function handles Wake Up Timer interrupt request.
01174   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01175   *                the configuration information for RTC.
01176   * @retval None
01177   */
01178 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
01179 {
01180   if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
01181   {
01182     /* Get the status of the Interrupt */
01183     if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
01184     {
01185       /* WAKEUPTIMER callback */
01186       HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
01187
01188       /* Clear the WAKEUPTIMER interrupt pending bit */
01189       __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01190     }
01191   }
01192
01193   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
01194   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01195
01196   /* Change RTC state */
01197   hrtc->State = HAL_RTC_STATE_READY;
01198 }
01199
01200 /**
01201   * @brief  Wake Up Timer callback.
01202   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01203   *                the configuration information for RTC.
01204   * @retval None
01205   */
01206 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
01207 {
01208   /* Prevent unused argument(s) compilation warning */
01209   UNUSED(hrtc);
01210
01211   /* NOTE : This function Should not be modified, when the callback is needed,
01212             the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
01213    */
01214 }
01215
01216 /**
01217   * @brief  This function handles Wake Up Timer Polling.
01218   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01219   *                the configuration information for RTC.
01220   * @param  Timeout: Timeout duration
01221   * @retval HAL status
01222   */
01223 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01224 {
01225   uint32_t tickstart = 0;
01226
01227   /* Get tick */
01228   tickstart = HAL_GetTick();
01229
01230   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
01231   {
01232     if(Timeout != HAL_MAX_DELAY)
01233     {
01234       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01235       {
01236         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01237
01238         return HAL_TIMEOUT;
01239       }
01240     }
01241   }
01242
01243   /* Clear the WAKEUPTIMER Flag */
01244   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01245
01246   /* Change RTC state */
01247   hrtc->State = HAL_RTC_STATE_READY;
01248
01249   return HAL_OK;
01250 }
01251
01252 /**
01253   * @}
01254   */
01255
01256
01257 /** @defgroup RTCEx_Group3 Extension Peripheral Control functions
01258  *  @brief   Extension Peripheral Control functions
01259  *
01260 @verbatim
01261  ===============================================================================
01262               ##### Extension Peripheral Control functions #####
01263  ===============================================================================
01264     [..]
01265     This subsection provides functions allowing to
01266       (+) Write a data in a specified RTC Backup data register
01267       (+) Read a data in a specified RTC Backup data register
01268       (+) Set the Coarse calibration parameters.
01269       (+) Deactivate the Coarse calibration parameters
01270       (+) Set the Smooth calibration parameters.
01271       (+) Configure the Synchronization Shift Control Settings.
01272       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01273       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01274       (+) Enable the RTC reference clock detection.
01275       (+) Disable the RTC reference clock detection.
01276       (+) Enable the Bypass Shadow feature.
01277       (+) Disable the Bypass Shadow feature.
01278
01279 @endverbatim
01280   * @{
01281   */
01282
01283 /**
01284   * @brief  Writes a data in a specified RTC Backup data register.
01285   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01286   *                the configuration information for RTC.
01287   * @param  BackupRegister: RTC Backup data Register number.
01288   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01289   *                                 specify the register.
01290   * @param  Data: Data to be written in the specified RTC Backup data register.
01291   * @retval None
01292   */
01293 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01294 {
01295   uint32_t tmp = 0;
01296
01297   /* Check the parameters */
01298   assert_param(IS_RTC_BKP(BackupRegister));
01299
01300   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01301   tmp += (BackupRegister * 4);
01302
01303   /* Write the specified register */
01304   *(__IO uint32_t *)tmp = (uint32_t)Data;
01305 }
01306
01307 /**
01308   * @brief  Reads data from the specified RTC Backup data Register.
01309   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01310   *                the configuration information for RTC.
01311   * @param  BackupRegister: RTC Backup data Register number.
01312   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01313   *                                 specify the register.
01314   * @retval Read value
01315   */
01316 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01317 {
01318   uint32_t tmp = 0;
01319
01320   /* Check the parameters */
01321   assert_param(IS_RTC_BKP(BackupRegister));
01322
01323   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01324   tmp += (BackupRegister * 4);
01325
01326   /* Read the specified register */
01327   return (*(__IO uint32_t *)tmp);
01328 }
01329
01330 /**
01331   * @brief  Sets the Smooth calibration parameters.
01332   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01333   *                the configuration information for RTC.
01334   * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
01335   *          This parameter can be can be one of the following values :
01336   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
01337   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
01338   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
01339   * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
01340   *          This parameter can be one of the following values:
01341   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.
01342   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
01343   * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
01344   *          This parameter can be one any value from 0 to 0x000001FF.
01345   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
01346   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
01347   *         SmouthCalibMinusPulsesValue must be equal to 0.
01348   * @retval HAL status
01349   */
01350 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
01351 {
01352   uint32_t tickstart = 0;
01353
01354   /* Check the parameters */
01355   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
01356   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
01357   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
01358
01359   /* Process Locked */
01360   __HAL_LOCK(hrtc);
01361
01362   hrtc->State = HAL_RTC_STATE_BUSY;
01363
01364   /* Disable the write protection for RTC registers */
01365   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01366
01367   /* check if a calibration is pending*/
01368   if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01369   {
01370   /* Get tick */
01371   tickstart = HAL_GetTick();
01372
01373     /* check if a calibration is pending*/
01374     while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01375     {
01376       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01377       {
01378         /* Enable the write protection for RTC registers */
01379         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01380
01381         /* Change RTC state */
01382         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01383
01384         /* Process Unlocked */
01385         __HAL_UNLOCK(hrtc);
01386
01387         return HAL_TIMEOUT;
01388       }
01389     }
01390   }
01391
01392   /* Configure the Smooth calibration settings */
01393   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
01394
01395   /* Enable the write protection for RTC registers */
01396   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01397
01398   /* Change RTC state */
01399   hrtc->State = HAL_RTC_STATE_READY;
01400
01401   /* Process Unlocked */
01402   __HAL_UNLOCK(hrtc);
01403
01404   return HAL_OK;
01405 }
01406
01407 /**
01408   * @brief  Configures the Synchronization Shift Control Settings.
01409   * @note   When REFCKON is set, firmware must not write to Shift control register.
01410   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01411   *                the configuration information for RTC.
01412   * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
01413   *          This parameter can be one of the following values :
01414   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
01415   *             @arg RTC_SHIFTADD1S_RESET: No effect.
01416   * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
01417   *          This parameter can be one any value from 0 to 0x7FFF.
01418   * @retval HAL status
01419   */
01420 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
01421 {
01422   uint32_t tickstart = 0;
01423
01424   /* Check the parameters */
01425   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
01426   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
01427
01428   /* Process Locked */
01429   __HAL_LOCK(hrtc);
01430
01431   hrtc->State = HAL_RTC_STATE_BUSY;
01432
01433   /* Disable the write protection for RTC registers */
01434   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01435
01436   /* Get tick */
01437   tickstart = HAL_GetTick();
01438
01439     /* Wait until the shift is completed*/
01440     while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
01441     {
01442       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01443       {
01444         /* Enable the write protection for RTC registers */
01445         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01446
01447         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01448
01449         /* Process Unlocked */
01450         __HAL_UNLOCK(hrtc);
01451
01452         return HAL_TIMEOUT;
01453       }
01454     }
01455
01456     /* Check if the reference clock detection is disabled */
01457     if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
01458     {
01459       /* Configure the Shift settings */
01460       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
01461
01462       /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
01463       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
01464       {
01465         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01466         {
01467           /* Enable the write protection for RTC registers */
01468           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01469
01470           hrtc->State = HAL_RTC_STATE_ERROR;
01471
01472           /* Process Unlocked */
01473           __HAL_UNLOCK(hrtc);
01474
01475           return HAL_ERROR;
01476         }
01477       }
01478     }
01479     else
01480     {
01481       /* Enable the write protection for RTC registers */
01482       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01483
01484       /* Change RTC state */
01485       hrtc->State = HAL_RTC_STATE_ERROR;
01486
01487       /* Process Unlocked */
01488       __HAL_UNLOCK(hrtc);
01489
01490       return HAL_ERROR;
01491     }
01492
01493   /* Enable the write protection for RTC registers */
01494   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01495
01496   /* Change RTC state */
01497   hrtc->State = HAL_RTC_STATE_READY;
01498
01499   /* Process Unlocked */
01500   __HAL_UNLOCK(hrtc);
01501
01502   return HAL_OK;
01503 }
01504
01505 /**
01506   * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01507   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01508   *                the configuration information for RTC.
01509   * @param  CalibOutput: Select the Calibration output Selection .
01510   *          This parameter can be one of the following values:
01511   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01512   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01513   * @retval HAL status
01514   */
01515 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01516 {
01517   /* Check the parameters */
01518   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01519
01520   /* Process Locked */
01521   __HAL_LOCK(hrtc);
01522
01523   hrtc->State = HAL_RTC_STATE_BUSY;
01524
01525   /* Disable the write protection for RTC registers */
01526   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01527
01528   /* Clear flags before config */
01529   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01530
01531   /* Configure the RTC_CR register */
01532   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01533
01534   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01535
01536   /* Enable the write protection for RTC registers */
01537   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01538
01539   /* Change RTC state */
01540   hrtc->State = HAL_RTC_STATE_READY;
01541
01542   /* Process Unlocked */
01543   __HAL_UNLOCK(hrtc);
01544
01545   return HAL_OK;
01546 }
01547
01548 /**
01549   * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01550   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01551   *                the configuration information for RTC.
01552   * @retval HAL status
01553   */
01554 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01555 {
01556   /* Process Locked */
01557   __HAL_LOCK(hrtc);
01558
01559   hrtc->State = HAL_RTC_STATE_BUSY;
01560
01561   /* Disable the write protection for RTC registers */
01562   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01563
01564   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01565
01566   /* Enable the write protection for RTC registers */
01567   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01568
01569   /* Change RTC state */
01570   hrtc->State = HAL_RTC_STATE_READY;
01571
01572   /* Process Unlocked */
01573   __HAL_UNLOCK(hrtc);
01574
01575   return HAL_OK;
01576 }
01577
01578 /**
01579   * @brief  Enables the RTC reference clock detection.
01580   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01581   *                the configuration information for RTC.
01582   * @retval HAL status
01583   */
01584 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01585 {
01586   /* Process Locked */
01587   __HAL_LOCK(hrtc);
01588
01589   hrtc->State = HAL_RTC_STATE_BUSY;
01590
01591   /* Disable the write protection for RTC registers */
01592   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01593
01594   /* Set Initialization mode */
01595   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01596   {
01597     /* Enable the write protection for RTC registers */
01598     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01599
01600     /* Set RTC state*/
01601     hrtc->State = HAL_RTC_STATE_ERROR;
01602
01603     /* Process Unlocked */
01604     __HAL_UNLOCK(hrtc);
01605
01606     return HAL_ERROR;
01607   }
01608   else
01609   {
01610     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01611
01612     /* Exit Initialization mode */
01613     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01614   }
01615
01616   /* Enable the write protection for RTC registers */
01617   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01618
01619    /* Change RTC state */
01620   hrtc->State = HAL_RTC_STATE_READY;
01621
01622   /* Process Unlocked */
01623   __HAL_UNLOCK(hrtc);
01624
01625   return HAL_OK;
01626 }
01627
01628 /**
01629   * @brief  Disable the RTC reference clock detection.
01630   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01631   *                the configuration information for RTC.
01632   * @retval HAL status
01633   */
01634 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01635 {
01636   /* Process Locked */
01637   __HAL_LOCK(hrtc);
01638
01639   hrtc->State = HAL_RTC_STATE_BUSY;
01640
01641   /* Disable the write protection for RTC registers */
01642   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01643
01644   /* Set Initialization mode */
01645   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01646   {
01647     /* Enable the write protection for RTC registers */
01648     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01649
01650     /* Set RTC state*/
01651     hrtc->State = HAL_RTC_STATE_ERROR;
01652
01653     /* Process Unlocked */
01654     __HAL_UNLOCK(hrtc);
01655
01656     return HAL_ERROR;
01657   }
01658   else
01659   {
01660     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01661
01662     /* Exit Initialization mode */
01663     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01664   }
01665
01666   /* Enable the write protection for RTC registers */
01667   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01668
01669   /* Change RTC state */
01670   hrtc->State = HAL_RTC_STATE_READY;
01671
01672   /* Process Unlocked */
01673   __HAL_UNLOCK(hrtc);
01674
01675   return HAL_OK;
01676 }
01677
01678 /**
01679   * @brief  Enables the Bypass Shadow feature.
01680   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01681   *                the configuration information for RTC.
01682   * @note   When the Bypass Shadow is enabled the calendar value are taken
01683   *         directly from the Calendar counter.
01684   * @retval HAL status
01685   */
01686 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01687 {
01688   /* Process Locked */
01689   __HAL_LOCK(hrtc);
01690
01691   hrtc->State = HAL_RTC_STATE_BUSY;
01692
01693   /* Disable the write protection for RTC registers */
01694   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01695
01696   /* Set the BYPSHAD bit */
01697   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01698
01699   /* Enable the write protection for RTC registers */
01700   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01701
01702   /* Change RTC state */
01703   hrtc->State = HAL_RTC_STATE_READY;
01704
01705   /* Process Unlocked */
01706   __HAL_UNLOCK(hrtc);
01707
01708   return HAL_OK;
01709 }
01710
01711 /**
01712   * @brief  Disables the Bypass Shadow feature.
01713   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01714   *                the configuration information for RTC.
01715   * @note   When the Bypass Shadow is enabled the calendar value are taken
01716   *         directly from the Calendar counter.
01717   * @retval HAL status
01718   */
01719 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01720 {
01721   /* Process Locked */
01722   __HAL_LOCK(hrtc);
01723
01724   hrtc->State = HAL_RTC_STATE_BUSY;
01725
01726   /* Disable the write protection for RTC registers */
01727   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01728
01729   /* Reset the BYPSHAD bit */
01730   hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
01731
01732   /* Enable the write protection for RTC registers */
01733   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01734
01735   /* Change RTC state */
01736   hrtc->State = HAL_RTC_STATE_READY;
01737
01738   /* Process Unlocked */
01739   __HAL_UNLOCK(hrtc);
01740
01741   return HAL_OK;
01742 }
01743
01744 /**
01745   * @}
01746   */
01747
01748   /** @defgroup RTCEx_Group4 Extended features functions
01749  *  @brief    Extended features functions
01750  *
01751 @verbatim
01752  ===============================================================================
01753                  ##### Extended features functions #####
01754  ===============================================================================
01755     [..]  This section provides functions allowing to:
01756       (+) RTC Alram B callback
01757       (+) RTC Poll for Alarm B request
01758
01759 @endverbatim
01760   * @{
01761   */
01762
01763 /**
01764   * @brief  Alarm B callback.
01765   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01766   *                the configuration information for RTC.
01767   * @retval None
01768   */
01769 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01770 {
01771   /* Prevent unused argument(s) compilation warning */
01772   UNUSED(hrtc);
01773
01774   /* NOTE : This function Should not be modified, when the callback is needed,
01775             the HAL_RTC_AlarmBEventCallback could be implemented in the user file
01776    */
01777 }
01778
01779 /**
01780   * @brief  This function handles AlarmB Polling request.
01781   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01782   *                the configuration information for RTC.
01783   * @param  Timeout: Timeout duration
01784   * @retval HAL status
01785   */
01786 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01787 {
01788   uint32_t tickstart = 0;
01789
01790   /* Get tick */
01791   tickstart = HAL_GetTick();
01792
01793   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
01794   {
01795     if(Timeout != HAL_MAX_DELAY)
01796     {
01797       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01798       {
01799         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01800         return HAL_TIMEOUT;
01801       }
01802     }
01803   }
01804
01805   /* Clear the Alarm Flag */
01806   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01807
01808   /* Change RTC state */
01809   hrtc->State = HAL_RTC_STATE_READY;
01810
01811   return HAL_OK;
01812 }
01813
01814 /**
01815   * @}
01816   */
01817
01818 /**
01819   * @}
01820   */
01821
01822 #endif /* HAL_RTC_MODULE_ENABLED */
01823 /**
01824   * @}
01825   */
01826
01827 /**
01828   * @}
01829   */
01830
01831 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_rtc_ex.h Source File

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stm32f7xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of RTC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_RTC_EX_H
00040 #define __STM32F7xx_HAL_RTC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  RTC Tamper structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00068                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00069
00070   uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
00071                                              This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
00072
00073   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00074                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00075
00076   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00077                                              This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
00078
00079   uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
00080                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
00081
00082   uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
00083                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00084
00085   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00086                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00087
00088   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00089                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00090
00091   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00092                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00093
00094   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00095                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00096 }RTC_TamperTypeDef;
00097 /**
00098   * @}
00099   */
00100
00101 /* Exported constants --------------------------------------------------------*/
00102 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00103   * @{
00104   */
00105
00106 /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions
00107   * @{
00108   */
00109 #define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
00110 #define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
00111 #define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
00112 #define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
00118   * @{
00119   */
00120 #define RTC_BKP_DR0                       ((uint32_t)0x00000000)
00121 #define RTC_BKP_DR1                       ((uint32_t)0x00000001)
00122 #define RTC_BKP_DR2                       ((uint32_t)0x00000002)
00123 #define RTC_BKP_DR3                       ((uint32_t)0x00000003)
00124 #define RTC_BKP_DR4                       ((uint32_t)0x00000004)
00125 #define RTC_BKP_DR5                       ((uint32_t)0x00000005)
00126 #define RTC_BKP_DR6                       ((uint32_t)0x00000006)
00127 #define RTC_BKP_DR7                       ((uint32_t)0x00000007)
00128 #define RTC_BKP_DR8                       ((uint32_t)0x00000008)
00129 #define RTC_BKP_DR9                       ((uint32_t)0x00000009)
00130 #define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
00131 #define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
00132 #define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
00133 #define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
00134 #define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
00135 #define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
00136 #define RTC_BKP_DR16                      ((uint32_t)0x00000010)
00137 #define RTC_BKP_DR17                      ((uint32_t)0x00000011)
00138 #define RTC_BKP_DR18                      ((uint32_t)0x00000012)
00139 #define RTC_BKP_DR19                      ((uint32_t)0x00000013)
00140 #define RTC_BKP_DR20                      ((uint32_t)0x00000014)
00141 #define RTC_BKP_DR21                      ((uint32_t)0x00000015)
00142 #define RTC_BKP_DR22                      ((uint32_t)0x00000016)
00143 #define RTC_BKP_DR23                      ((uint32_t)0x00000017)
00144 #define RTC_BKP_DR24                      ((uint32_t)0x00000018)
00145 #define RTC_BKP_DR25                      ((uint32_t)0x00000019)
00146 #define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
00147 #define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
00148 #define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
00149 #define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
00150 #define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
00151 #define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions
00157   * @{
00158   */
00159 #define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
00160 #define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions
00166   * @{
00167   */
00168 #define RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E
00169 #define RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E
00170 #define RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
00176   * @{
00177   */
00178 #define RTC_TAMPER1_INTERRUPT                RTC_TAMPCR_TAMP1IE
00179 #define RTC_TAMPER2_INTERRUPT                RTC_TAMPCR_TAMP2IE
00180 #define RTC_TAMPER3_INTERRUPT                RTC_TAMPCR_TAMP3IE
00181 #define RTC_ALL_TAMPER_INTERRUPT             RTC_TAMPCR_TAMPIE
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection
00187   * @{
00188   */
00189 #define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000)
00190 #define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00000002)
00191 #define RTC_TIMESTAMPPIN_POS2               ((uint32_t)0x00000004)
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions
00197   * @{
00198   */
00199 #define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
00200 #define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
00201 #define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
00202 #define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
00203 /**
00204   * @}
00205   */
00206
00207   /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions
00208 * @{
00209 */
00210 #define RTC_TAMPER_ERASE_BACKUP_ENABLE               ((uint32_t)0x00000000)
00211 #define RTC_TAMPER_ERASE_BACKUP_DISABLE              ((uint32_t)0x00020000)
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions
00217   * @{
00218   */
00219 #define RTC_TAMPERMASK_FLAG_DISABLE                ((uint32_t)0x00000000)
00220 #define RTC_TAMPERMASK_FLAG_ENABLE                 ((uint32_t)0x00040000)
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
00226   * @{
00227   */
00228 #define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
00229
00230 #define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2
00231                                                                 consecutive samples at the active level */
00232 #define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4
00233                                                                 consecutive samples at the active level */
00234 #define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8
00235                                                                 consecutive samples at the active leve. */
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
00241   * @{
00242   */
00243 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
00244                                                                              with a frequency =  RTCCLK / 32768 */
00245 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
00246                                                                              with a frequency =  RTCCLK / 16384 */
00247 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
00248                                                                              with a frequency =  RTCCLK / 8192  */
00249 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
00250                                                                              with a frequency =  RTCCLK / 4096  */
00251 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
00252                                                                              with a frequency =  RTCCLK / 2048  */
00253 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
00254                                                                              with a frequency =  RTCCLK / 1024  */
00255 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
00256                                                                              with a frequency =  RTCCLK / 512   */
00257 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
00258                                                                              with a frequency =  RTCCLK / 256   */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
00264   * @{
00265   */
00266 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
00267                                                                          sampling during 1 RTCCLK cycle */
00268 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
00269                                                                          sampling during 2 RTCCLK cycles */
00270 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
00271                                                                          sampling during 4 RTCCLK cycles */
00272 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
00273                                                                          sampling during 8 RTCCLK cycles */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions
00279   * @{
00280   */
00281 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
00282 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)        /*!< TimeStamp on Tamper Detection event is not saved */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup  RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
00288   * @{
00289   */
00290 #define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)            /*!< TimeStamp on Tamper Detection event saved        */
00291 #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
00297   * @{
00298   */
00299 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
00300 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
00301 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
00302 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
00303 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
00304 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
00310   * @{
00311   */
00312 #define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00313                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
00314 #define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00315                                                                     period is 16s, else 2exp19 RTCCLK seconds */
00316 #define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00317                                                                     period is 8s, else 2exp18 RTCCLK seconds */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
00323   * @{
00324   */
00325 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000)  /*!< The number of RTCCLK pulses added
00326                                                                        during a X -second window = Y - CALM[8:0]
00327                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
00328 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000)  /*!< The number of RTCCLK pulses subbstited
00329                                                                        during a 32-second window = CALM[8:0] */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions
00335   * @{
00336   */
00337 #define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
00338 #define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
00339 /**
00340   * @}
00341   */
00342
00343  /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
00344   * @{
00345   */
00346 #define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000)
00347 #define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Exported macros -----------------------------------------------------------*/
00357 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00358   * @{
00359   */
00360
00361 /**
00362   * @brief  Enable the RTC WakeUp Timer peripheral.
00363   * @param  __HANDLE__: specifies the RTC handle.
00364   * @retval None
00365   */
00366 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00367
00368 /**
00369   * @brief  Disable the RTC WakeUp Timer peripheral.
00370   * @param  __HANDLE__: specifies the RTC handle.
00371   * @retval None
00372   */
00373 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00374
00375 /**
00376   * @brief  Enable the RTC WakeUpTimer interrupt.
00377   * @param  __HANDLE__: specifies the RTC handle.
00378   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
00379   *         This parameter can be:
00380   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00381   * @retval None
00382   */
00383 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00384
00385 /**
00386   * @brief  Disable the RTC WakeUpTimer interrupt.
00387   * @param  __HANDLE__: specifies the RTC handle.
00388   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
00389   *         This parameter can be:
00390   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00391   * @retval None
00392   */
00393 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00394
00395 /**
00396   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00397   * @param  __HANDLE__: specifies the RTC handle.
00398   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
00399   *         This parameter can be:
00400   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00401   * @retval None
00402   */
00403 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00404
00405 /**
00406   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00407   * @param  __HANDLE__: specifies the RTC handle.
00408   * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
00409   *         This parameter can be:
00410   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00411   * @retval None
00412   */
00413 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00414
00415 /**
00416   * @brief  Get the selected RTC WakeUpTimer's flag status.
00417   * @param  __HANDLE__: specifies the RTC handle.
00418   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
00419   *          This parameter can be:
00420   *             @arg RTC_FLAG_WUTF
00421   *             @arg RTC_FLAG_WUTWF
00422   * @retval None
00423   */
00424 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00425
00426 /**
00427   * @brief  Clear the RTC Wake Up timer's pending flags.
00428   * @param  __HANDLE__: specifies the RTC handle.
00429   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
00430   *         This parameter can be:
00431   *            @arg RTC_FLAG_WUTF
00432   * @retval None
00433   */
00434 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00435
00436 /**
00437   * @brief  Enable the RTC Tamper1 input detection.
00438   * @param  __HANDLE__: specifies the RTC handle.
00439   * @retval None
00440   */
00441 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
00442
00443 /**
00444   * @brief  Disable the RTC Tamper1 input detection.
00445   * @param  __HANDLE__: specifies the RTC handle.
00446   * @retval None
00447   */
00448 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
00449
00450 /**
00451   * @brief  Enable the RTC Tamper2 input detection.
00452   * @param  __HANDLE__: specifies the RTC handle.
00453   * @retval None
00454   */
00455 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
00456
00457 /**
00458   * @brief  Disable the RTC Tamper2 input detection.
00459   * @param  __HANDLE__: specifies the RTC handle.
00460   * @retval None
00461   */
00462 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
00463
00464 /**
00465   * @brief  Enable the RTC Tamper3 input detection.
00466   * @param  __HANDLE__: specifies the RTC handle.
00467   * @retval None
00468   */
00469 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
00470
00471 /**
00472   * @brief  Disable the RTC Tamper3 input detection.
00473   * @param  __HANDLE__: specifies the RTC handle.
00474   * @retval None
00475   */
00476 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
00477
00478 /**
00479   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
00480   * @param  __HANDLE__: specifies the RTC handle.
00481   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
00482   *         This parameter can be:
00483   *            @arg  RTC_IT_TAMP: All tampers interrupts
00484   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00485   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00486   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00487   * @retval None
00488   */
00489 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
00490                                                                       ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
00491                                                                                                           (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
00492
00493 /**
00494   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
00495   * @param  __HANDLE__: specifies the RTC handle.
00496   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
00497   *         This parameter can be:
00498   *            @arg  RTC_IT_TAMP: All tampers interrupts
00499   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00500   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00501   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00502   * @retval None
00503   */
00504 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00505
00506 /**
00507   * @brief  Get the selected RTC Tamper's flag status.
00508   * @param  __HANDLE__: specifies the RTC handle.
00509   * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
00510   *          This parameter can be:
00511   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
00512   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00513   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
00514   * @retval None
00515   */
00516 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00517
00518 /**
00519   * @brief  Clear the RTC Tamper's pending flags.
00520   * @param  __HANDLE__: specifies the RTC handle.
00521   * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.
00522   *          This parameter can be:
00523   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
00524   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00525   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
00526   * @retval None
00527   */
00528 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00529
00530 /**
00531   * @brief  Enable the RTC TimeStamp peripheral.
00532   * @param  __HANDLE__: specifies the RTC handle.
00533   * @retval None
00534   */
00535 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00536
00537 /**
00538   * @brief  Disable the RTC TimeStamp peripheral.
00539   * @param  __HANDLE__: specifies the RTC handle.
00540   * @retval None
00541   */
00542 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00543
00544 /**
00545   * @brief  Enable the RTC TimeStamp interrupt.
00546   * @param  __HANDLE__: specifies the RTC handle.
00547   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
00548   *         This parameter can be:
00549   *            @arg RTC_IT_TS: TimeStamp interrupt
00550   * @retval None
00551   */
00552 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00553
00554 /**
00555   * @brief  Disable the RTC TimeStamp interrupt.
00556   * @param  __HANDLE__: specifies the RTC handle.
00557   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
00558   *         This parameter can be:
00559   *            @arg RTC_IT_TS: TimeStamp interrupt
00560   * @retval None
00561   */
00562 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00563
00564 /**
00565   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00566   * @param  __HANDLE__: specifies the RTC handle.
00567   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to check.
00568   *         This parameter can be:
00569   *            @arg RTC_IT_TS: TimeStamp interrupt
00570   * @retval None
00571   */
00572 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00573
00574 /**
00575   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
00576   * @param  __HANDLE__: specifies the RTC handle.
00577   * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
00578   *         This parameter can be:
00579   *            @arg RTC_IT_TS: TimeStamp interrupt
00580   * @retval None
00581   */
00582 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00583
00584 /**
00585   * @brief  Get the selected RTC TimeStamp's flag status.
00586   * @param  __HANDLE__: specifies the RTC handle.
00587   * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
00588   *         This parameter can be:
00589   *            @arg RTC_FLAG_TSF
00590   *            @arg RTC_FLAG_TSOVF
00591   * @retval None
00592   */
00593 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00594
00595 /**
00596   * @brief  Clear the RTC Time Stamp's pending flags.
00597   * @param  __HANDLE__: specifies the RTC handle.
00598   * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
00599   *          This parameter can be:
00600   *             @arg RTC_FLAG_TSF
00601   *             @arg RTC_FLAG_TSOVF
00602   * @retval None
00603   */
00604 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00605
00606 /**
00607   * @brief  Enable the RTC internal TimeStamp peripheral.
00608   * @param  __HANDLE__: specifies the RTC handle.
00609   * @retval None
00610   */
00611 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
00612
00613 /**
00614   * @brief  Disable the RTC internal TimeStamp peripheral.
00615   * @param  __HANDLE__: specifies the RTC handle.
00616   * @retval None
00617   */
00618 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
00619
00620 /**
00621   * @brief  Get the selected RTC Internal Time Stamp's flag status.
00622   * @param  __HANDLE__: specifies the RTC handle.
00623   * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
00624   *         This parameter can be:
00625   *            @arg RTC_FLAG_ITSF
00626   * @retval None
00627   */
00628 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00629
00630 /**
00631   * @brief  Clear the RTC Internal Time Stamp's pending flags.
00632   * @param  __HANDLE__: specifies the RTC handle.
00633   * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
00634   *          This parameter can be:
00635   *             @arg RTC_FLAG_ITSF
00636   * @retval None
00637   */
00638 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00639
00640 /**
00641   * @brief  Enable the RTC calibration output.
00642   * @param  __HANDLE__: specifies the RTC handle.
00643   * @retval None
00644   */
00645 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00646
00647 /**
00648   * @brief  Disable the calibration output.
00649   * @param  __HANDLE__: specifies the RTC handle.
00650   * @retval None
00651   */
00652 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00653
00654 /**
00655   * @brief  Enable the clock reference detection.
00656   * @param  __HANDLE__: specifies the RTC handle.
00657   * @retval None
00658   */
00659 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00660
00661 /**
00662   * @brief  Disable the clock reference detection.
00663   * @param  __HANDLE__: specifies the RTC handle.
00664   * @retval None
00665   */
00666 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00667
00668 /**
00669   * @brief  Get the selected RTC shift operation's flag status.
00670   * @param  __HANDLE__: specifies the RTC handle.
00671   * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
00672   *          This parameter can be:
00673   *             @arg RTC_FLAG_SHPF
00674   * @retval None
00675   */
00676 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00677
00678 /**
00679   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
00680   * @retval None
00681   */
00682 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00683
00684 /**
00685   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
00686   * @retval None
00687   */
00688 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00689
00690 /**
00691   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
00692   * @retval None.
00693   */
00694 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00695
00696 /**
00697   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
00698   * @retval None.
00699   */
00700 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00701
00702 /**
00703   * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00704   * @retval None.
00705   */
00706 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00707
00708 /**
00709   * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00710   * @retval None.
00711   */
00712 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00713
00714 /**
00715   * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00716   * @retval None.
00717   */
00718 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00719
00720 /**
00721   * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00722   * @retval None.
00723   */
00724 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00725
00726 /**
00727   * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00728   * @retval None.
00729   */
00730 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
00731
00732 /**
00733   * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00734   * This parameter can be:
00735   * @retval None.
00736   */
00737 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
00738
00739 /**
00740   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
00741   * @retval Line Status.
00742   */
00743 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00744
00745 /**
00746   * @brief Clear the RTC WakeUp Timer associated Exti line flag.
00747   * @retval None.
00748   */
00749 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00750
00751 /**
00752   * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
00753   * @retval None.
00754   */
00755 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00756
00757 /**
00758   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
00759   * @retval None
00760   */
00761 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00762
00763 /**
00764   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
00765   * @retval None
00766   */
00767 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00768
00769 /**
00770   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
00771   * @retval None.
00772   */
00773 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00774
00775 /**
00776   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
00777   * @retval None.
00778   */
00779 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00780
00781 /**
00782   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00783   * @retval None.
00784   */
00785 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00786
00787 /**
00788   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00789   * @retval None.
00790   */
00791 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00792
00793 /**
00794   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00795   * @retval None.
00796   */
00797 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00798
00799 /**
00800   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00801   * @retval None.
00802   */
00803 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00804
00805 /**
00806   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00807   * @retval None.
00808   */
00809 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
00810
00811 /**
00812   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00813   * This parameter can be:
00814   * @retval None.
00815   */
00816 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
00817
00818 /**
00819   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
00820   * @retval Line Status.
00821   */
00822 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00823
00824 /**
00825   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
00826   * @retval None.
00827   */
00828 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00829
00830 /**
00831   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
00832   * @retval None.
00833   */
00834 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00835
00836 /**
00837   * @}
00838   */
00839
00840 /* Exported functions --------------------------------------------------------*/
00841 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00842   * @{
00843   */
00844
00845 /** @addtogroup RTCEx_Exported_Functions_Group1
00846   * @{
00847   */
00848
00849 /* RTC TimeStamp and Tamper functions *****************************************/
00850 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00851 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00852 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
00853 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00854 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00855 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
00856
00857 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00858 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00859 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00860 void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
00861
00862 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00863 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
00864 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
00865 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
00866 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00867 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00868 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00869 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00870 /**
00871   * @}
00872   */
00873
00874 /** @addtogroup RTCEx_Exported_Functions_Group2
00875   * @{
00876   */
00877 /* RTC Wake-up functions ******************************************************/
00878 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00879 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00880 uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
00881 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
00882 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
00883 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
00884 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00885 /**
00886   * @}
00887   */
00888
00889 /** @addtogroup RTCEx_Exported_Functions_Group3
00890   * @{
00891   */
00892 /* Extension Control functions ************************************************/
00893 void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
00894 uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
00895
00896 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
00897 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
00898 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
00899 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
00900 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
00901 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
00902 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
00903 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
00904 /**
00905   * @}
00906   */
00907
00908 /** @addtogroup RTCEx_Exported_Functions_Group4
00909   * @{
00910   */
00911 /* Extension RTC features functions *******************************************/
00912 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
00913 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00914 /**
00915   * @}
00916   */
00917
00918 /**
00919   * @}
00920   */
00921 /* Private types -------------------------------------------------------------*/
00922 /* Private variables ---------------------------------------------------------*/
00923 /* Private constants ---------------------------------------------------------*/
00924 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
00925   * @{
00926   */
00927 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
00928 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */
00929 /**
00930   * @}
00931   */
00932
00933 /* Private constants ---------------------------------------------------------*/
00934 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
00935   * @{
00936   */
00937 /* Masks Definition */
00938 #define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
00939 #define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT))
00940 /**
00941   * @}
00942   */
00943
00944 /* Private macros ------------------------------------------------------------*/
00945 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
00946   * @{
00947   */
00948
00949 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
00950   * @{
00951   */
00952 #define IS_RTC_OUTPUT(__OUTPUT__)      (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \
00953                                         ((__OUTPUT__) == RTC_OUTPUT_ALARMA)  || \
00954                                         ((__OUTPUT__) == RTC_OUTPUT_ALARMB)  || \
00955                                         ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))
00956 #define IS_RTC_BKP(__BKP__)               ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)
00957 #define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \
00958                                      ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))
00959 #define IS_RTC_TAMPER(__TAMPER__)   ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
00960
00961 #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)  ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
00962
00963 #define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \
00964                                        ((__PIN__) == RTC_TIMESTAMPPIN_POS1)  || \
00965                                        ((__PIN__) == RTC_TIMESTAMPPIN_POS2))
00966 #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
00967                                         ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
00968                                         ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
00969                                         ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
00970 #define IS_RTC_TAMPER_ERASE_MODE(__MODE__)             (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
00971                                                         ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
00972 #define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)     (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
00973                                                      ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
00974 #define IS_RTC_TAMPER_FILTER(__FILTER__)  (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
00975                                        ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
00976                                        ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
00977                                        ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
00978 #define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
00979                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
00980                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
00981                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
00982                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
00983                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
00984                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
00985                                            ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
00986 #define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
00987                                                     ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
00988                                                     ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
00989                                                     ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
00990 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
00991                                                               ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
00992 #define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
00993                                        ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
00994 #define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
00995                                     ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
00996                                     ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
00997                                     ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
00998                                     ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
00999                                     ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01000
01001 #define IS_RTC_WAKEUP_COUNTER(__COUNTER__)  ((__COUNTER__) <= 0xFFFF)
01002 #define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01003                                                 ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01004                                                 ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01005 #define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01006                                             ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01007 #define  IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)
01008 #define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \
01009                                      ((__SEL__) == RTC_SHIFTADD1S_SET))
01010 #define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)
01011 #define IS_RTC_CALIB_OUTPUT(__OUTPUT__)  (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \
01012                                           ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))
01013 /**
01014   * @}
01015   */
01016
01017 /**
01018   * @}
01019   */
01020
01021 /**
01022   * @}
01023   */
01024
01025 /**
01026   * @}
01027   */
01028
01029 #ifdef __cplusplus
01030 }
01031 #endif
01032
01033 #endif /* __STM32F7xx_HAL_RTC_EX_H */
01034
01035 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai.c Source File

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stm32f7xx_hal_sai.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SAI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + I/O operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016  ==============================================================================
00017                   ##### How to use this driver #####
00018   ==============================================================================
00019
00020   [..]
00021     The SAI HAL driver can be used as follows:
00022
00023     (#) Declare a SAI_HandleTypeDef handle structure.
00024     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00025         (##) Enable the SAI interface clock.
00026         (##) SAI pins configuration:
00027             (+++) Enable the clock for the SAI GPIOs.
00028             (+++) Configure these SAI pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00030              and HAL_SAI_Receive_IT() APIs):
00031             (+++) Configure the SAI interrupt priority.
00032             (+++) Enable the NVIC SAI IRQ handle.
00033
00034         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00035              and HAL_SAI_Receive_DMA() APIs):
00036             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00037             (+++) Enable the DMAx interface clock.
00038             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx Stream.
00040             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00042                 DMA Tx/Rx Stream.
00043
00044    (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00045        using HAL_SAI_Init() function.
00046
00047    -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00048        will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
00049        inside the transmit and receive process.
00050
00051   [..]
00052    (@) SAI Clock Source, the configuration is managed through RCCEx_PeriphCLKConfig()
00053             function in the HAL RCC drivers
00054   [..]
00055    (@) Make sure that either:
00056        (+@) I2S PLL is configured or
00057        (+@) SAI PLL is configured or
00058        (+@) External clock source is configured after setting correctly
00059             the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file.
00060
00061   [..]
00062     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00063         for the external slaves even if there is no data in the FIFO, However FS signal
00064         generation is conditioned by the presence of data in the FIFO.
00065
00066   [..]
00067     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00068         and FS signal for the external slaves.
00069
00070   [..]
00071     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00072         (+@)  First bit Offset <= (SLOT size - Data size)
00073         (+@)  Data size <= SLOT size
00074         (+@)  Number of SLOT x SLOT size = Frame length
00075         (+@)  The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00076
00077   [..]
00078      Three operation modes are available within this driver :
00079
00080    *** Polling mode IO operation ***
00081    =================================
00082    [..]
00083      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00084      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00085
00086    *** Interrupt mode IO operation ***
00087    ===================================
00088    [..]
00089      (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT()
00090      (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
00091          add his own code by customization of function pointer HAL_SAI_TxCpltCallback
00092      (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT()
00093      (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
00094          add his own code by customization of function pointer HAL_SAI_RxCpltCallback
00095      (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
00096          add his own code by customization of function pointer HAL_SAI_ErrorCallback
00097
00098    *** DMA mode IO operation ***
00099    ==============================
00100    [..]
00101      (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00102      (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
00103          add his own code by customization of function pointer HAL_SAI_TxCpltCallback
00104      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA()
00105      (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
00106          add his own code by customization of function pointer HAL_SAI_RxCpltCallback
00107      (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
00108          add his own code by customization of function pointer HAL_SAI_ErrorCallback
00109      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00110      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00111      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00112
00113    *** SAI HAL driver macros list ***
00114    =============================================
00115    [..]
00116      Below the list of most used macros in USART HAL driver :
00117
00118       (+) __HAL_SAI_ENABLE: Enable the SAI peripheral
00119       (+) __HAL_SAI_DISABLE: Disable the SAI peripheral
00120       (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts
00121       (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts
00122       (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is
00123           enabled or disabled
00124       (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not
00125
00126   @endverbatim
00127   ******************************************************************************
00128   * @attention
00129   *
00130   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00131   *
00132   * Redistribution and use in source and binary forms, with or without modification,
00133   * are permitted provided that the following conditions are met:
00134   *   1. Redistributions of source code must retain the above copyright notice,
00135   *      this list of conditions and the following disclaimer.
00136   *   2. Redistributions in binary form must reproduce the above copyright notice,
00137   *      this list of conditions and the following disclaimer in the documentation
00138   *      and/or other materials provided with the distribution.
00139   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00140   *      may be used to endorse or promote products derived from this software
00141   *      without specific prior written permission.
00142   *
00143   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00144   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00145   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00146   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00147   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00148   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00149   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00150   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00151   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00152   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00153   *
00154   ******************************************************************************
00155   */
00156
00157 /* Includes ------------------------------------------------------------------*/
00158 #include "stm32f7xx_hal.h"
00159
00160 /** @addtogroup STM32F7xx_HAL_Driver
00161   * @{
00162   */
00163
00164 /** @defgroup SAI SAI
00165   * @brief SAI HAL module driver
00166   * @{
00167   */
00168
00169 #ifdef HAL_SAI_MODULE_ENABLED
00170
00171 /* Private typedef -----------------------------------------------------------*/
00172 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00173   * @{
00174   */
00175 typedef enum {
00176   SAI_MODE_DMA,
00177   SAI_MODE_IT
00178 }SAI_ModeTypedef;
00179 /**
00180   * @}
00181   */
00182 /* Private define ------------------------------------------------------------*/
00183 /** @defgroup SAI_Private_Constants  SAI Private Constants
00184   * @{
00185   */
00186 #define SAI_FIFO_SIZE       8
00187 #define SAI_DEFAULT_TIMEOUT 4
00188 #define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
00189 /**
00190   * @}
00191   */
00192
00193 /* SAI registers Masks */
00194 #define CR1_CLEAR_MASK            ((uint32_t)0xFF04C010)
00195 #define FRCR_CLEAR_MASK           ((uint32_t)0xFFF88000)
00196 #define SLOTR_CLEAR_MASK          ((uint32_t)0x0000F020)
00197
00198 #define SAI_TIMEOUT_VALUE         10
00199 /* Private macro -------------------------------------------------------------*/
00200 /* Private variables ---------------------------------------------------------*/
00201 /* Private function prototypes -----------------------------------------------*/
00202 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00203 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
00204 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00205 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00206
00207 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00208 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00209 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00210 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00211 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00212 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00213 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00214
00215 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00216 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00217 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00218 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00219 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00220
00221 /* Exported functions ---------------------------------------------------------*/
00222
00223 /** @defgroup SAI_Exported_Functions  SAI Exported Functions
00224   * @{
00225   */
00226
00227 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00228  *  @brief    Initialization and Configuration functions
00229  *
00230 @verbatim
00231  ===============================================================================
00232               ##### Initialization and de-initialization functions #####
00233  ===============================================================================
00234     [..]  This subsection provides a set of functions allowing to initialize and
00235           de-initialize the SAIx peripheral:
00236
00237       (+) User must implement HAL_SAI_MspInit() function in which he configures
00238           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00239
00240       (+) Call the function HAL_SAI_Init() to configure the selected device with
00241           the selected configuration:
00242         (++) Mode (Master/slave TX/RX)
00243         (++) Protocol
00244         (++) Data Size
00245         (++) MCLK Output
00246         (++) Audio frequency
00247         (++) FIFO Threshold
00248         (++) Frame Config
00249         (++) Slot Config
00250
00251       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00252           of the selected SAI peripheral.
00253
00254 @endverbatim
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Initializes the structure FrameInit, SlotInit and the low part of
00260   *         Init according to the specified parameters and call the function
00261   *         HAL_SAI_Init to initialize the SAI block.
00262   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
00263   *               the configuration information for SAI module.
00264   * @param  protocol : one of the supported protocol @ref SAI_Protocol
00265   * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
00266   *                the configuration information for SAI module.
00267   * @param  nbslot   : Number of slot.
00268   * @retval HAL status
00269   */
00270 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00271 {
00272   HAL_StatusTypeDef status = HAL_OK;
00273
00274   /* Check the parameters */
00275   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00276   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00277
00278   switch(protocol)
00279   {
00280   case SAI_I2S_STANDARD :
00281   case SAI_I2S_MSBJUSTIFIED :
00282   case SAI_I2S_LSBJUSTIFIED :
00283     status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00284     break;
00285   case SAI_PCM_LONG :
00286   case SAI_PCM_SHORT :
00287     status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00288     break;
00289   default :
00290     status = HAL_ERROR;
00291     break;
00292   }
00293
00294   if(status == HAL_OK)
00295   {
00296     status = HAL_SAI_Init(hsai);
00297   }
00298
00299   return status;
00300 }
00301
00302 /**
00303   * @brief  Initializes the SAI according to the specified parameters
00304   *         in the SAI_InitTypeDef and create the associated handle.
00305   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00306   *                the configuration information for SAI module.
00307   * @retval HAL status
00308   */
00309 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00310 {
00311   uint32_t tmpclock = 0;
00312
00313   /* This variable used to store the SAI_CK_x (value in Hz) */
00314   uint32_t freq = 0;
00315
00316   /* This variable is used to compute CKSTR bits of SAI CR1 according to
00317      ClockStrobing and AudioMode fields */
00318   uint32_t ckstr_bits = 0;
00319
00320   uint32_t syncen_bits = 0;
00321
00322   /* Check the SAI handle allocation */
00323   if(hsai == NULL)
00324   {
00325     return HAL_ERROR;
00326   }
00327
00328   /* Check the SAI Block parameters */
00329   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00330   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00331   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00332   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00333   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00334   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00335   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00336   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00337   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00338   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00339   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00340   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00341   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00342   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00343
00344   /* Check the SAI Block Frame parameters */
00345   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00346   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00347   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00348   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00349   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00350
00351   /* Check the SAI Block Slot parameters */
00352   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00353   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00354   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00355   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00356
00357   if(hsai->State == HAL_SAI_STATE_RESET)
00358   {
00359     /* Allocate lock resource and initialize it */
00360     hsai->Lock = HAL_UNLOCKED;
00361
00362     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00363     HAL_SAI_MspInit(hsai);
00364   }
00365
00366   hsai->State = HAL_SAI_STATE_BUSY;
00367
00368   /* Disable the selected SAI peripheral */
00369   SAI_Disable(hsai);
00370
00371   /* SAI Block Synchro Configuration -----------------------------------------*/
00372   SAI_BlockSynchroConfig(hsai);
00373
00374   /* Configure Master Clock using the following formula :
00375      MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
00376      FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
00377      MCKDIV[3:0] = SAI_CK_x / FS * 512 */
00378   if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00379   {
00380   /* Get SAI clock source based on Source clock selection from RCC */
00381   freq = SAI_GetInputClock(hsai);
00382
00383     /* (saiclocksource x 10) to keep Significant digits */
00384     tmpclock = (((freq * 10) / ((hsai->Init.AudioFrequency) * 512)));
00385
00386     hsai->Init.Mckdiv = tmpclock / 10;
00387
00388         /* Round result to the nearest integer */
00389     if((tmpclock % 10) > 8)
00390     {
00391       hsai->Init.Mckdiv+= 1;
00392     }
00393   }
00394
00395   /* Compute CKSTR bits of SAI CR1 according to ClockStrobing and AudioMode */
00396   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00397   {
00398     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0: SAI_xCR1_CKSTR;
00399   }
00400   else
00401   {
00402     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR: 0;
00403   }
00404
00405   /* SAI Block Configuration ------------------------------------------------------------*/
00406   switch(hsai->Init.Synchro)
00407   {
00408     case SAI_ASYNCHRONOUS :
00409       {
00410         syncen_bits = 0;
00411       }
00412       break;
00413     case SAI_SYNCHRONOUS :
00414       {
00415         syncen_bits = SAI_xCR1_SYNCEN_0;
00416       }
00417       break;
00418     case SAI_SYNCHRONOUS_EXT_SAI1 :
00419     case SAI_SYNCHRONOUS_EXT_SAI2 :
00420       {
00421         syncen_bits = SAI_xCR1_SYNCEN_1;
00422       }
00423       break;
00424   }
00425   /* SAI CR1 Configuration */
00426   hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00427                          SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
00428                          SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00429                          SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
00430
00431   hsai->Instance->CR1|= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00432                         hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00433                         ckstr_bits | syncen_bits |        \
00434                         hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00435                         hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20));
00436
00437   /* SAI CR2 Configuration */
00438   hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00439   hsai->Instance->CR2|=  (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00440
00441   /* SAI Frame Configuration -----------------------------------------*/
00442   hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00443                            SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF));
00444   hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1)  |
00445                             hsai->FrameInit.FSOffset |
00446                             hsai->FrameInit.FSDefinition |
00447                             hsai->FrameInit.FSPolarity   |
00448                             ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
00449
00450   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00451   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00452   hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |            \
00453                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
00454
00455   hsai->Instance->SLOTR|=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize
00456                           | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) <<  8);
00457
00458   /* Initialize the error code */
00459   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00460
00461   /* Initialize the SAI state */
00462   hsai->State= HAL_SAI_STATE_READY;
00463
00464   /* Release Lock */
00465   __HAL_UNLOCK(hsai);
00466
00467   return HAL_OK;
00468 }
00469
00470 /**
00471   * @brief  DeInitializes the SAI peripheral.
00472   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00473   *                the configuration information for SAI module.
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00477 {
00478   /* Check the SAI handle allocation */
00479   if(hsai == NULL)
00480   {
00481     return HAL_ERROR;
00482   }
00483
00484   hsai->State = HAL_SAI_STATE_BUSY;
00485
00486   /* Disabled All interrupt and clear all the flag */
00487   hsai->Instance->IMR = 0;
00488   hsai->Instance->CLRFR = 0xFFFFFFFF;
00489
00490   /* Disable the SAI */
00491   SAI_Disable(hsai);
00492
00493   /* Flush the fifo */
00494   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00495
00496   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00497   HAL_SAI_MspDeInit(hsai);
00498
00499   /* Initialize the error code */
00500   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00501
00502   /* Initialize the SAI state */
00503   hsai->State = HAL_SAI_STATE_RESET;
00504
00505   /* Release Lock */
00506   __HAL_UNLOCK(hsai);
00507
00508   return HAL_OK;
00509 }
00510
00511 /**
00512   * @brief SAI MSP Init.
00513   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00514   *                the configuration information for SAI module.
00515   * @retval None
00516   */
00517 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00518 {
00519   /* Prevent unused argument(s) compilation warning */
00520   UNUSED(hsai);
00521
00522   /* NOTE : This function should not be modified, when the callback is needed,
00523             the HAL_SAI_MspInit could be implemented in the user file
00524    */
00525 }
00526
00527 /**
00528   * @brief SAI MSP DeInit.
00529   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00530   *                the configuration information for SAI module.
00531   * @retval None
00532   */
00533 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00534 {
00535   /* Prevent unused argument(s) compilation warning */
00536   UNUSED(hsai);
00537
00538   /* NOTE : This function should not be modified, when the callback is needed,
00539             the HAL_SAI_MspDeInit could be implemented in the user file
00540    */
00541 }
00542
00543 /**
00544   * @}
00545   */
00546
00547 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
00548  *  @brief   Data transfers functions
00549  *
00550 @verbatim
00551   ===============================================================================
00552                       ##### IO operation functions #####
00553  ===============================================================================
00554     [..]
00555     This subsection provides a set of functions allowing to manage the SAI data
00556     transfers.
00557
00558     (+) There are two modes of transfer:
00559        (++) Blocking mode : The communication is performed in the polling mode.
00560             The status of all data processing is returned by the same function
00561             after finishing transfer.
00562        (++) No-Blocking mode : The communication is performed using Interrupts
00563             or DMA. These functions return the status of the transfer startup.
00564             The end of the data processing will be indicated through the
00565             dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
00566             using DMA mode.
00567
00568     (+) Blocking mode functions are :
00569         (++) HAL_SAI_Transmit()
00570         (++) HAL_SAI_Receive()
00571         (++) HAL_SAI_TransmitReceive()
00572
00573     (+) Non Blocking mode functions with Interrupt are :
00574         (++) HAL_SAI_Transmit_IT()
00575         (++) HAL_SAI_Receive_IT()
00576         (++) HAL_SAI_TransmitReceive_IT()
00577
00578     (+) Non Blocking mode functions with DMA are :
00579         (++) HAL_SAI_Transmit_DMA()
00580         (++) HAL_SAI_Receive_DMA()
00581         (++) HAL_SAI_TransmitReceive_DMA()
00582
00583     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00584         (++) HAL_SAI_TxCpltCallback()
00585         (++) HAL_SAI_RxCpltCallback()
00586         (++) HAL_SAI_ErrorCallback()
00587
00588 @endverbatim
00589   * @{
00590   */
00591
00592 /**
00593   * @brief  Transmits an amount of data in blocking mode.
00594   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00595   *                the configuration information for SAI module.
00596   * @param  pData: Pointer to data buffer
00597   * @param  Size: Amount of data to be sent
00598   * @param  Timeout: Timeout duration
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
00602 {
00603   uint32_t tickstart = HAL_GetTick();
00604
00605   if((pData == NULL ) || (Size == 0))
00606   {
00607     return  HAL_ERROR;
00608   }
00609
00610   if(hsai->State == HAL_SAI_STATE_READY)
00611   {
00612     /* Process Locked */
00613     __HAL_LOCK(hsai);
00614
00615     hsai->XferSize = Size;
00616     hsai->XferCount = Size;
00617     hsai->pBuffPtr = pData;
00618     hsai->State = HAL_SAI_STATE_BUSY_TX;
00619     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00620
00621     /* Check if the SAI is already enabled */
00622     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00623     {
00624       /* fill the fifo with data before to enabled the SAI */
00625       SAI_FillFifo(hsai);
00626       /* Enable SAI peripheral */
00627       __HAL_SAI_ENABLE(hsai);
00628     }
00629
00630     while(hsai->XferCount > 0)
00631     {
00632       /* Write data if the FIFO is not full */
00633       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
00634       {
00635         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00636         {
00637           hsai->Instance->DR = (*hsai->pBuffPtr++);
00638         }
00639         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00640         {
00641           hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
00642           hsai->pBuffPtr+= 2;
00643         }
00644         else
00645         {
00646           hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
00647           hsai->pBuffPtr+= 4;
00648         }
00649         hsai->XferCount--;
00650       }
00651       else
00652       {
00653         /* Check for the Timeout */
00654         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
00655         {
00656           /* Update error code */
00657           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00658           /* Change the SAI state */
00659           hsai->State = HAL_SAI_STATE_TIMEOUT;
00660
00661           return HAL_TIMEOUT;
00662         }
00663       }
00664     }
00665
00666     hsai->State = HAL_SAI_STATE_READY;
00667
00668     /* Process Unlocked */
00669     __HAL_UNLOCK(hsai);
00670
00671     return HAL_OK;
00672   }
00673   else
00674   {
00675     return HAL_BUSY;
00676   }
00677 }
00678
00679 /**
00680   * @brief  Receives an amount of data in blocking mode.
00681   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00682   *                the configuration information for SAI module.
00683   * @param  pData: Pointer to data buffer
00684   * @param  Size: Amount of data to be received
00685   * @param  Timeout: Timeout duration
00686   * @retval HAL status
00687   */
00688 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00689 {
00690   uint32_t tickstart = HAL_GetTick();
00691
00692   if((pData == NULL ) || (Size == 0))
00693   {
00694     return  HAL_ERROR;
00695   }
00696
00697   if(hsai->State == HAL_SAI_STATE_READY)
00698   {
00699     /* Process Locked */
00700     __HAL_LOCK(hsai);
00701
00702     hsai->pBuffPtr = pData;
00703     hsai->XferSize = Size;
00704     hsai->XferCount = Size;
00705     hsai->State = HAL_SAI_STATE_BUSY_RX;
00706     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00707
00708     /* Check if the SAI is already enabled */
00709     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00710     {
00711       /* Enable SAI peripheral */
00712       __HAL_SAI_ENABLE(hsai);
00713     }
00714
00715     /* Receive data */
00716     while(hsai->XferCount > 0)
00717     {
00718       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
00719       {
00720         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00721         {
00722           (*hsai->pBuffPtr++) = hsai->Instance->DR;
00723         }
00724         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00725         {
00726           *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00727           hsai->pBuffPtr+= 2;
00728         }
00729         else
00730         {
00731           *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00732           hsai->pBuffPtr+= 4;
00733         }
00734         hsai->XferCount--;
00735       }
00736       else
00737       {
00738         /* Check for the Timeout */
00739         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
00740         {
00741           /* Update error code */
00742           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00743           /* Change the SAI state */
00744           hsai->State = HAL_SAI_STATE_TIMEOUT;
00745
00746           return HAL_TIMEOUT;
00747         }
00748       }
00749     }
00750
00751     hsai->State = HAL_SAI_STATE_READY;
00752
00753     /* Process Unlocked */
00754     __HAL_UNLOCK(hsai);
00755
00756     return HAL_OK;
00757   }
00758   else
00759   {
00760     return HAL_BUSY;
00761   }
00762 }
00763
00764 /**
00765   * @brief  Transmits an amount of data in no-blocking mode with Interrupt.
00766   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00767   *                the configuration information for SAI module.
00768   * @param  pData: Pointer to data buffer
00769   * @param  Size: Amount of data to be sent
00770   * @retval HAL status
00771   */
00772 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00773 {
00774     if((pData == NULL) || (Size == 0))
00775     {
00776       return  HAL_ERROR;
00777     }
00778
00779   if(hsai->State == HAL_SAI_STATE_READY)
00780   {
00781     /* Process Locked */
00782     __HAL_LOCK(hsai);
00783
00784     hsai->pBuffPtr = pData;
00785     hsai->XferSize = Size;
00786     hsai->XferCount = Size;
00787     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00788     hsai->State = HAL_SAI_STATE_BUSY_TX;
00789
00790     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00791     {
00792       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
00793     }
00794     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00795     {
00796       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
00797     }
00798     else
00799     {
00800       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
00801     }
00802
00803     /* Fill the fifo before starting the communication */
00804     SAI_FillFifo(hsai);
00805
00806     /* Enable FRQ and OVRUDR interrupts */
00807     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00808
00809     /* Check if the SAI is already enabled */
00810     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00811     {
00812       /* Enable SAI peripheral */
00813       __HAL_SAI_ENABLE(hsai);
00814     }
00815     /* Process Unlocked */
00816     __HAL_UNLOCK(hsai);
00817
00818     return HAL_OK;
00819   }
00820   else
00821   {
00822     return HAL_BUSY;
00823   }
00824 }
00825
00826 /**
00827   * @brief  Receives an amount of data in no-blocking mode with Interrupt.
00828   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00829   *                the configuration information for SAI module.
00830   * @param  pData: Pointer to data buffer
00831   * @param  Size: Amount of data to be received
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00835 {
00836     if((pData == NULL) || (Size == 0))
00837     {
00838       return  HAL_ERROR;
00839     }
00840
00841   if(hsai->State == HAL_SAI_STATE_READY)
00842   {
00843     /* Process Locked */
00844     __HAL_LOCK(hsai);
00845
00846     hsai->pBuffPtr = pData;
00847     hsai->XferSize = Size;
00848     hsai->XferCount = Size;
00849     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00850     hsai->State = HAL_SAI_STATE_BUSY_RX;
00851
00852     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00853     {
00854       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
00855     }
00856     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00857     {
00858       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
00859     }
00860     else
00861     {
00862       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
00863     }
00864
00865     /* Enable TXE and OVRUDR interrupts */
00866     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00867
00868     /* Check if the SAI is already enabled */
00869     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00870     {
00871       /* Enable SAI peripheral */
00872       __HAL_SAI_ENABLE(hsai);
00873     }
00874
00875     /* Process Unlocked */
00876     __HAL_UNLOCK(hsai);
00877
00878     return HAL_OK;
00879   }
00880   else
00881   {
00882     return HAL_BUSY;
00883   }
00884 }
00885
00886 /**
00887   * @brief Pauses the audio stream playing from the Media.
00888   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00889   *                the configuration information for SAI module.
00890   * @retval HAL status
00891   */
00892 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
00893 {
00894   /* Process Locked */
00895   __HAL_LOCK(hsai);
00896
00897   /* Pause the audio file playing by disabling the SAI DMA requests */
00898   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00899
00900   /* Process Unlocked */
00901   __HAL_UNLOCK(hsai);
00902
00903   return HAL_OK;
00904 }
00905
00906 /**
00907   * @brief Resumes the audio stream playing from the Media.
00908   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00909   *                the configuration information for SAI module.
00910   * @retval HAL status
00911   */
00912 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
00913 {
00914   /* Process Locked */
00915   __HAL_LOCK(hsai);
00916
00917   /* Enable the SAI DMA requests */
00918   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
00919
00920   /* If the SAI peripheral is still not enabled, enable it */
00921   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00922   {
00923     /* Enable SAI peripheral */
00924     __HAL_SAI_ENABLE(hsai);
00925   }
00926
00927   /* Process Unlocked */
00928   __HAL_UNLOCK(hsai);
00929
00930   return HAL_OK;
00931 }
00932
00933 /**
00934   * @brief Stops the audio stream playing from the Media.
00935   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
00936   *                the configuration information for SAI module.
00937   * @retval HAL status
00938   */
00939 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
00940 {
00941   /* Process Locked */
00942   __HAL_LOCK(hsai);
00943
00944   /* Disable the SAI DMA request */
00945   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00946
00947   /* Abort the SAI DMA Tx Stream */
00948   if(hsai->hdmatx != NULL)
00949   {
00950     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
00951     {
00952       return HAL_ERROR;
00953     }
00954   }
00955   /* Abort the SAI DMA Rx Stream */
00956   if(hsai->hdmarx != NULL)
00957   {
00958     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
00959     {
00960       return HAL_ERROR;
00961     }
00962   }
00963
00964   /* Disable SAI peripheral */
00965   SAI_Disable(hsai);
00966
00967   hsai->State = HAL_SAI_STATE_READY;
00968
00969   /* Process Unlocked */
00970   __HAL_UNLOCK(hsai);
00971
00972   return HAL_OK;
00973 }
00974
00975 /**
00976   * @brief Abort the current transfer and disbaled the SAI.
00977   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
00978   *                the configuration information for SAI module.
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
00982 {
00983   /* Disable the SAI DMA request */
00984   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00985
00986   /* Abort the SAI DMA Tx Stream */
00987   if(hsai->hdmatx != NULL)
00988   {
00989     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
00990     {
00991       return HAL_ERROR;
00992     }
00993   }
00994   /* Abort the SAI DMA Rx Stream */
00995   if(hsai->hdmarx != NULL)
00996   {
00997     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
00998     {
00999       return HAL_ERROR;
01000     }
01001   }
01002
01003   /* Disabled All interrupt and clear all the flag */
01004   hsai->Instance->IMR = 0;
01005   hsai->Instance->CLRFR = 0xFFFFFFFF;
01006
01007   /* Disable SAI peripheral */
01008   SAI_Disable(hsai);
01009
01010   /* Flush the fifo */
01011   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01012
01013   hsai->State = HAL_SAI_STATE_READY;
01014
01015   /* Process Unlocked */
01016   __HAL_UNLOCK(hsai);
01017
01018   return HAL_OK;
01019 }
01020
01021 /**
01022   * @brief  Transmits an amount of data in no-blocking mode with DMA.
01023   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01024   *                the configuration information for SAI module.
01025   * @param  pData: Pointer to data buffer
01026   * @param  Size: Amount of data to be sent
01027   * @retval HAL status
01028   */
01029 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01030 {
01031   uint32_t *tmp;
01032
01033   if((pData == NULL) || (Size == 0))
01034   {
01035     return  HAL_ERROR;
01036   }
01037
01038   if(hsai->State == HAL_SAI_STATE_READY)
01039   {
01040     /* Process Locked */
01041     __HAL_LOCK(hsai);
01042
01043     hsai->pBuffPtr = pData;
01044     hsai->XferSize = Size;
01045     hsai->XferCount = Size;
01046     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01047     hsai->State = HAL_SAI_STATE_BUSY_TX;
01048
01049     /* Set the SAI Tx DMA Half transfer complete callback */
01050     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01051
01052     /* Set the SAI TxDMA transfer complete callback */
01053     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01054
01055     /* Set the DMA error callback */
01056     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01057
01058     /* Enable the Tx DMA Stream */
01059     tmp = (uint32_t*)&pData;
01060     HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);
01061
01062     /* Check if the SAI is already enabled */
01063     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01064     {
01065       /* Enable SAI peripheral */
01066       __HAL_SAI_ENABLE(hsai);
01067     }
01068
01069     /* Enable the interrupts for error handling */
01070     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01071
01072     /* Enable SAI Tx DMA Request */
01073     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01074
01075     /* Process Unlocked */
01076     __HAL_UNLOCK(hsai);
01077
01078     return HAL_OK;
01079   }
01080   else
01081   {
01082     return HAL_BUSY;
01083   }
01084 }
01085
01086 /**
01087   * @brief  Receives an amount of data in no-blocking mode with DMA.
01088   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01089   *                the configuration information for SAI module.
01090   * @param  pData: Pointer to data buffer
01091   * @param  Size: Amount of data to be received
01092   * @retval HAL status
01093   */
01094 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01095 {
01096   uint32_t *tmp;
01097
01098   if((pData == NULL) || (Size == 0))
01099   {
01100     return  HAL_ERROR;
01101   }
01102
01103   if(hsai->State == HAL_SAI_STATE_READY)
01104   {
01105     /* Process Locked */
01106     __HAL_LOCK(hsai);
01107
01108     hsai->pBuffPtr = pData;
01109     hsai->XferSize = Size;
01110     hsai->XferCount = Size;
01111     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01112     hsai->State = HAL_SAI_STATE_BUSY_RX;
01113
01114     /* Set the SAI Rx DMA Half transfer complete callback */
01115     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01116
01117     /* Set the SAI Rx DMA transfer complete callback */
01118     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01119
01120     /* Set the DMA error callback */
01121     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01122
01123     /* Enable the Rx DMA Stream */
01124     tmp = (uint32_t*)&pData;
01125     HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);
01126
01127     /* Check if the SAI is already enabled */
01128     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01129     {
01130       /* Enable SAI peripheral */
01131       __HAL_SAI_ENABLE(hsai);
01132     }
01133
01134     /* Enable the interrupts for error handling */
01135     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01136
01137     /* Enable SAI Rx DMA Request */
01138     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01139
01140     /* Process Unlocked */
01141     __HAL_UNLOCK(hsai);
01142
01143     return HAL_OK;
01144   }
01145   else
01146   {
01147     return HAL_BUSY;
01148   }
01149 }
01150
01151 /**
01152   * @brief  Enable the tx mute mode.
01153   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01154   *                the configuration information for SAI module.
01155   * @param  val :  value sent during the mute @ref SAI_Block_Mute_Value
01156   * @retval HAL status
01157   */
01158 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01159 {
01160   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01161
01162   if(hsai->State != HAL_SAI_STATE_RESET)
01163   {
01164     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01165     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
01166     return HAL_OK;
01167   }
01168   return HAL_ERROR;
01169 }
01170
01171 /**
01172   * @brief  Disable the tx mute mode.
01173   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01174   *                the configuration information for SAI module.
01175   * @retval HAL status
01176   */
01177 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01178 {
01179   if(hsai->State != HAL_SAI_STATE_RESET)
01180   {
01181     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01182     return HAL_OK;
01183   }
01184   return HAL_ERROR;
01185 }
01186
01187 /**
01188   * @brief  Enable the rx mute detection.
01189   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01190   *                the configuration information for SAI module.
01191   * @param  callback : function called when the mute is detected
01192   * @param  counter : number a data before mute detection max 63.
01193   * @retval HAL status
01194   */
01195 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01196 {
01197   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01198
01199   if(hsai->State != HAL_SAI_STATE_RESET)
01200   {
01201     /* set the mute counter */
01202     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01203     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
01204     hsai->mutecallback = callback;
01205     /* enable the IT interrupt */
01206     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01207     return HAL_OK;
01208   }
01209   return HAL_ERROR;
01210 }
01211
01212 /**
01213   * @brief  Disable the rx mute detection.
01214   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01215   *                the configuration information for SAI module.
01216   * @retval HAL status
01217   */
01218 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01219 {
01220   if(hsai->State != HAL_SAI_STATE_RESET)
01221   {
01222     /* set the mutecallback to NULL */
01223     hsai->mutecallback = (SAIcallback)NULL;
01224     /* enable the IT interrupt */
01225     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01226     return HAL_OK;
01227   }
01228   return HAL_ERROR;
01229 }
01230
01231 /**
01232   * @brief  This function handles SAI interrupt request.
01233   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01234   *                the configuration information for SAI module.
01235   * @retval HAL status
01236   */
01237 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01238 {
01239   if(hsai->State != HAL_SAI_STATE_RESET)
01240   {
01241     uint32_t tmpFlag = hsai->Instance->SR;
01242     uint32_t tmpItSource = hsai->Instance->IMR;
01243
01244     if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ))
01245     {
01246       hsai->InterruptServiceRoutine(hsai);
01247     }
01248
01249     /* check the flag only if one of them is set */
01250     if(tmpFlag != 0x00000000)
01251     {
01252       /* SAI Overrun error interrupt occurred ----------------------------------*/
01253       if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01254       {
01255         /* Clear the SAI Overrun flag */
01256         __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01257         /* Change the SAI error code */
01258         hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01259         /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01260         HAL_SAI_ErrorCallback(hsai);
01261       }
01262
01263       /* SAI mutedet interrupt occurred ----------------------------------*/
01264       if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01265       {
01266         /* Clear the SAI mutedet flag */
01267         __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01268         /* call the call back function */
01269         if(hsai->mutecallback != (SAIcallback)NULL)
01270         {
01271           /* inform the user that an RX mute event has been detected */
01272           hsai->mutecallback();
01273         }
01274       }
01275
01276       /* SAI AFSDET interrupt occurred ----------------------------------*/
01277       if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01278       {
01279         /* Change the SAI error code */
01280         hsai->ErrorCode = HAL_SAI_ERROR_AFSDET;
01281         HAL_SAI_Abort(hsai);
01282         HAL_SAI_ErrorCallback(hsai);
01283       }
01284
01285       /* SAI LFSDET interrupt occurred ----------------------------------*/
01286       if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01287       {
01288         /* Change the SAI error code */
01289         hsai->ErrorCode = HAL_SAI_ERROR_LFSDET;
01290         HAL_SAI_Abort(hsai);
01291         HAL_SAI_ErrorCallback(hsai);
01292       }
01293
01294       /* SAI WCKCFG interrupt occurred ----------------------------------*/
01295       if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
01296       {
01297         /* Change the SAI error code */
01298         hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG;
01299         HAL_SAI_Abort(hsai);
01300         HAL_SAI_ErrorCallback(hsai);
01301       }
01302       /* SAI CNRDY interrupt occurred ----------------------------------*/
01303       if(((tmpFlag & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((tmpItSource & SAI_IT_CNRDY) == SAI_IT_CNRDY))
01304       {
01305         /* Clear the SAI CNRDY flag */
01306         __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
01307         /* Change the SAI error code */
01308         hsai->ErrorCode = HAL_SAI_ERROR_CNREADY;
01309         /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01310         HAL_SAI_ErrorCallback(hsai);
01311       }
01312     }
01313   }
01314 }
01315
01316 /**
01317   * @brief Tx Transfer completed callbacks.
01318   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01319   *                the configuration information for SAI module.
01320   * @retval None
01321   */
01322  __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
01323 {
01324   /* Prevent unused argument(s) compilation warning */
01325   UNUSED(hsai);
01326
01327   /* NOTE : This function Should not be modified, when the callback is needed,
01328             the HAL_SAI_TxCpltCallback could be implemented in the user file
01329    */
01330 }
01331
01332 /**
01333   * @brief Tx Transfer Half completed callbacks
01334   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01335   *                the configuration information for SAI module.
01336   * @retval None
01337   */
01338  __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01339 {
01340   /* Prevent unused argument(s) compilation warning */
01341   UNUSED(hsai);
01342
01343   /* NOTE : This function Should not be modified, when the callback is needed,
01344             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
01345    */
01346 }
01347
01348 /**
01349   * @brief Rx Transfer completed callbacks.
01350   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01351   *                the configuration information for SAI module.
01352   * @retval None
01353   */
01354 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
01355 {
01356   /* Prevent unused argument(s) compilation warning */
01357   UNUSED(hsai);
01358
01359   /* NOTE : This function Should not be modified, when the callback is needed,
01360             the HAL_SAI_RxCpltCallback could be implemented in the user file
01361    */
01362 }
01363
01364 /**
01365   * @brief Rx Transfer half completed callbacks
01366   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01367   *                the configuration information for SAI module.
01368   * @retval None
01369   */
01370 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01371 {
01372   /* Prevent unused argument(s) compilation warning */
01373   UNUSED(hsai);
01374
01375   /* NOTE : This function Should not be modified, when the callback is needed,
01376             the HAL_SAI_RxCpltCallback could be implemented in the user file
01377    */
01378 }
01379
01380 /**
01381   * @brief SAI error callbacks.
01382   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01383   *                the configuration information for SAI module.
01384   * @retval None
01385   */
01386 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
01387 {
01388   /* Prevent unused argument(s) compilation warning */
01389   UNUSED(hsai);
01390
01391   /* NOTE : This function Should not be modified, when the callback is needed,
01392             the HAL_SAI_ErrorCallback could be implemented in the user file
01393    */
01394 }
01395
01396 /**
01397   * @}
01398   */
01399
01400
01401 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
01402  *  @brief   Peripheral State functions
01403  *
01404 @verbatim
01405  ===============================================================================
01406                 ##### Peripheral State and Errors functions #####
01407  ===============================================================================
01408     [..]
01409     This subsection permits to get in run-time the status of the peripheral
01410     and the data flow.
01411
01412 @endverbatim
01413   * @{
01414   */
01415
01416 /**
01417   * @brief  Returns the SAI state.
01418   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01419   *                the configuration information for SAI module.
01420   * @retval HAL state
01421   */
01422 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
01423 {
01424   return hsai->State;
01425 }
01426
01427 /**
01428 * @brief  Return the SAI error code
01429 * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01430   *              the configuration information for the specified SAI Block.
01431 * @retval SAI Error Code
01432 */
01433 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
01434 {
01435   return hsai->ErrorCode;
01436 }
01437 /**
01438   * @}
01439   */
01440
01441 /**
01442   * @brief  Initializes the SAI I2S protocol according to the specified parameters
01443   *         in the SAI_InitTypeDef and create the associated handle.
01444   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01445   *                the configuration information for SAI module.
01446   * @param  protocol : one of the supported protocol
01447   * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
01448   *                the configuration information for SAI module.
01449   * @param  nbslot : number of slot minimum value is 2 and max is 16.
01450   *                    the value must be a multiple of 2.
01451   * @retval HAL status
01452   */
01453 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01454 {
01455   /* Check the parameters */
01456   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
01457   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
01458
01459   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01460   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01461   /* Compute ClockStrobing according AudioMode */
01462   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01463   { /* Transmit */
01464     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01465   }
01466   else
01467   { /* Receive */
01468     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01469   }
01470   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
01471   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01472   hsai->SlotInit.FirstBitOffset  = 0;
01473   hsai->SlotInit.SlotNumber      = nbslot;
01474
01475   /* in IS2 the number of slot must be even */
01476   if((nbslot & 0x1) != 0 )
01477   {
01478     return HAL_ERROR;
01479   }
01480
01481   switch(protocol)
01482   {
01483   case SAI_I2S_STANDARD :
01484     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
01485     hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
01486     break;
01487   case SAI_I2S_MSBJUSTIFIED :
01488   case SAI_I2S_LSBJUSTIFIED :
01489     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
01490     hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
01491     break;
01492   default :
01493     return HAL_ERROR;
01494   }
01495
01496   /* Frame definition */
01497   switch(datasize)
01498   {
01499   case SAI_PROTOCOL_DATASIZE_16BIT:
01500     hsai->Init.DataSize = SAI_DATASIZE_16;
01501     hsai->FrameInit.FrameLength = 32*(nbslot/2);
01502     hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
01503     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01504     break;
01505   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01506     hsai->Init.DataSize = SAI_DATASIZE_16;
01507     hsai->FrameInit.FrameLength = 64*(nbslot/2);
01508     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01509     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01510     break;
01511   case SAI_PROTOCOL_DATASIZE_24BIT:
01512     hsai->Init.DataSize = SAI_DATASIZE_24;
01513     hsai->FrameInit.FrameLength = 64*(nbslot/2);
01514     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01515     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01516     break;
01517   case SAI_PROTOCOL_DATASIZE_32BIT:
01518     hsai->Init.DataSize = SAI_DATASIZE_32;
01519     hsai->FrameInit.FrameLength = 64*(nbslot/2);
01520     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01521     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01522     break;
01523   default :
01524     return HAL_ERROR;
01525   }
01526   if(protocol == SAI_I2S_LSBJUSTIFIED)
01527   {
01528     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
01529     {
01530       hsai->SlotInit.FirstBitOffset = 16;
01531     }
01532     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
01533     {
01534       hsai->SlotInit.FirstBitOffset = 8;
01535     }
01536   }
01537   return HAL_OK;
01538 }
01539
01540 /**
01541   * @brief  Initializes the SAI PCM protocol according to the specified parameters
01542   *         in the SAI_InitTypeDef and create the associated handle.
01543   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01544   *                the configuration information for SAI module.
01545   * @param  protocol : one of the supported protocol
01546   * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
01547   * @param  nbslot : number of slot minimum value is 1 and the max is 16.
01548   * @retval HAL status
01549   */
01550 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01551 {
01552   /* Check the parameters */
01553   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
01554   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
01555
01556   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01557   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01558   /* Compute ClockStrobing according AudioMode */
01559   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01560   { /* Transmit */
01561     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01562   }
01563   else
01564   { /* Receive */
01565     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01566   }
01567   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
01568   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
01569   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
01570   hsai->SlotInit.FirstBitOffset  = 0;
01571   hsai->SlotInit.SlotNumber      = nbslot;
01572   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01573
01574   switch(protocol)
01575   {
01576   case SAI_PCM_SHORT :
01577     hsai->FrameInit.ActiveFrameLength = 1;
01578     break;
01579   case SAI_PCM_LONG :
01580     hsai->FrameInit.ActiveFrameLength = 13;
01581     break;
01582   default :
01583     return HAL_ERROR;
01584   }
01585
01586   switch(datasize)
01587   {
01588   case SAI_PROTOCOL_DATASIZE_16BIT:
01589     hsai->Init.DataSize = SAI_DATASIZE_16;
01590     hsai->FrameInit.FrameLength = 16 * nbslot;
01591     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01592     break;
01593   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01594     hsai->Init.DataSize = SAI_DATASIZE_16;
01595     hsai->FrameInit.FrameLength = 32 * nbslot;
01596     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01597     break;
01598   case SAI_PROTOCOL_DATASIZE_24BIT :
01599     hsai->Init.DataSize = SAI_DATASIZE_24;
01600     hsai->FrameInit.FrameLength = 32 * nbslot;
01601     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01602     break;
01603   case SAI_PROTOCOL_DATASIZE_32BIT:
01604     hsai->Init.DataSize = SAI_DATASIZE_32;
01605     hsai->FrameInit.FrameLength = 32 * nbslot;
01606     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01607     break;
01608   default :
01609     return HAL_ERROR;
01610   }
01611
01612   return HAL_OK;
01613 }
01614
01615 /**
01616   * @brief  Fill the fifo
01617   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01618   *                the configuration information for SAI module.
01619   * @retval None.
01620   */
01621 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
01622 {
01623   /* fill the fifo with data before to enabled the SAI */
01624   while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))
01625   {
01626     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01627     {
01628       hsai->Instance->DR = (*hsai->pBuffPtr++);
01629     }
01630     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
01631     {
01632       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01633       hsai->pBuffPtr+= 2;
01634     }
01635     else
01636     {
01637       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01638       hsai->pBuffPtr+= 4;
01639     }
01640     hsai->XferCount--;
01641   }
01642 }
01643
01644 /**
01645   * @brief  return the interrupt flag to set according the SAI setup
01646   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01647   *                the configuration information for SAI module.
01648   * @param  mode : SAI_MODE_DMA or SAI_MODE_IT
01649   * @retval the list of the IT flag to enable
01650  */
01651 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
01652 {
01653   uint32_t tmpIT = SAI_IT_OVRUDR;
01654
01655   if(mode == SAI_MODE_IT)
01656   {
01657     tmpIT|= SAI_IT_FREQ;
01658   }
01659
01660   if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
01661     ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
01662   {
01663     tmpIT|= SAI_IT_CNRDY;
01664   }
01665
01666   if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01667   {
01668     tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
01669   }
01670   else
01671   {
01672     /* hsai has been configured in master mode */
01673     tmpIT|= SAI_IT_WCKCFG;
01674   }
01675   return tmpIT;
01676 }
01677
01678 /**
01679   * @brief  disable the SAI and wait the disabling
01680   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01681   *                the configuration information for SAI module.
01682   * @retval None.
01683   */
01684 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
01685 {
01686   uint32_t tickstart = HAL_GetTick();
01687   HAL_StatusTypeDef status = HAL_OK;
01688
01689   __HAL_SAI_DISABLE(hsai);
01690   while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
01691   {
01692     /* Check for the Timeout */
01693     if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)
01694     {
01695       /* Update error code */
01696       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01697
01698       return HAL_TIMEOUT;
01699     }
01700   }
01701   return status;
01702 }
01703
01704 /**
01705   * @brief  Tx Handler for Transmit in Interrupt mode 8Bit transfer
01706   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01707   *                the configuration information for SAI module.
01708   * @retval None.
01709   */
01710 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
01711 {
01712   if(hsai->XferCount == 0)
01713   {
01714     /* Handle the end of the transmission */
01715     /* Disable FREQ and OVRUDR interrupts */
01716     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01717     hsai->State = HAL_SAI_STATE_READY;
01718     HAL_SAI_TxCpltCallback(hsai);
01719   }
01720   else
01721   {
01722     /* Write data on DR register */
01723     hsai->Instance->DR = (*hsai->pBuffPtr++);
01724     hsai->XferCount--;
01725   }
01726 }
01727
01728 /**
01729   * @brief  Tx Handler for Transmit in Interrupt mode for 16Bit transfer
01730   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01731   *                the configuration information for SAI module.
01732   * @retval None.
01733   */
01734 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
01735 {
01736   if(hsai->XferCount == 0)
01737   {
01738     /* Handle the end of the transmission */
01739     /* Disable FREQ and OVRUDR interrupts */
01740     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01741     hsai->State = HAL_SAI_STATE_READY;
01742     HAL_SAI_TxCpltCallback(hsai);
01743   }
01744   else
01745   {
01746     /* Write data on DR register */
01747     hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
01748     hsai->pBuffPtr+=2;
01749     hsai->XferCount--;
01750   }
01751 }
01752
01753 /**
01754   * @brief  Tx Handler for Transmit in Interrupt mode for 32Bit transfer
01755   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01756   *                the configuration information for SAI module.
01757   * @retval None.
01758   */
01759 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
01760 {
01761   if(hsai->XferCount == 0)
01762   {
01763     /* Handle the end of the transmission */
01764     /* Disable FREQ and OVRUDR interrupts */
01765     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01766     hsai->State = HAL_SAI_STATE_READY;
01767     HAL_SAI_TxCpltCallback(hsai);
01768   }
01769   else
01770   {
01771     /* Write data on DR register */
01772     hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
01773     hsai->pBuffPtr+=4;
01774     hsai->XferCount--;
01775   }
01776 }
01777
01778 /**
01779   * @brief  Rx Handler for Receive in Interrupt mode 8Bit transfer
01780   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01781   *                the configuration information for SAI module.
01782   * @retval None.
01783   */
01784 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
01785 {
01786   /* Receive data */
01787   (*hsai->pBuffPtr++) = hsai->Instance->DR;
01788   hsai->XferCount--;
01789
01790   /* Check end of the transfer */
01791   if(hsai->XferCount == 0)
01792   {
01793     /* Disable TXE and OVRUDR interrupts */
01794     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01795
01796     /* Clear the SAI Overrun flag */
01797     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01798
01799     hsai->State = HAL_SAI_STATE_READY;
01800     HAL_SAI_RxCpltCallback(hsai);
01801   }
01802 }
01803
01804 /**
01805   * @brief  Rx Handler for Receive in Interrupt mode for 16Bit transfer
01806   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01807   *                the configuration information for SAI module.
01808   * @retval None.
01809   */
01810 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
01811 {
01812   /* Receive data */
01813   *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
01814   hsai->pBuffPtr+=2;
01815   hsai->XferCount--;
01816
01817   /* Check end of the transfer */
01818   if(hsai->XferCount == 0)
01819   {
01820     /* Disable TXE and OVRUDR interrupts */
01821     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01822
01823     /* Clear the SAI Overrun flag */
01824     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01825
01826     hsai->State = HAL_SAI_STATE_READY;
01827     HAL_SAI_RxCpltCallback(hsai);
01828   }
01829 }
01830 /**
01831   * @brief  Rx Handler for Receive in Interrupt mode for 32Bit transfer
01832   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01833   *                the configuration information for SAI module.
01834   * @retval None.
01835   */
01836 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
01837 {
01838   /* Receive data */
01839   *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
01840   hsai->pBuffPtr+=4;
01841   hsai->XferCount--;
01842
01843   /* Check end of the transfer */
01844   if(hsai->XferCount == 0)
01845   {
01846     /* Disable TXE and OVRUDR interrupts */
01847     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01848
01849     /* Clear the SAI Overrun flag */
01850     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01851
01852     hsai->State = HAL_SAI_STATE_READY;
01853     HAL_SAI_RxCpltCallback(hsai);
01854   }
01855 }
01856
01857 /**
01858   * @brief DMA SAI transmit process complete callback.
01859   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01860   *                the configuration information for the specified DMA module.
01861   * @retval None
01862   */
01863 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
01864 {
01865   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
01866
01867   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01868   {
01869     hsai->XferCount = 0;
01870
01871     /* Disable SAI Tx DMA Request */
01872     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
01873
01874     /* Stop the interrupts error handling */
01875     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01876
01877     hsai->State= HAL_SAI_STATE_READY;
01878   }
01879   HAL_SAI_TxCpltCallback(hsai);
01880 }
01881
01882 /**
01883   * @brief DMA SAI transmit process half complete callback
01884   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01885   *                the configuration information for the specified DMA module.
01886   * @retval None
01887   */
01888 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01889 {
01890   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01891
01892   HAL_SAI_TxHalfCpltCallback(hsai);
01893 }
01894
01895 /**
01896   * @brief DMA SAI receive process complete callback.
01897   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01898   *                the configuration information for the specified DMA module.
01899   * @retval None
01900   */
01901 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
01902 {
01903   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01904   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01905   {
01906     /* Disable Rx DMA Request */
01907     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
01908     hsai->XferCount = 0;
01909
01910     /* Stop the interrupts error handling */
01911     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01912
01913     hsai->State = HAL_SAI_STATE_READY;
01914   }
01915   HAL_SAI_RxCpltCallback(hsai);
01916 }
01917
01918 /**
01919   * @brief DMA SAI receive process half complete callback
01920   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01921   *                the configuration information for the specified DMA module.
01922   * @retval None
01923   */
01924 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01925 {
01926   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01927
01928   HAL_SAI_RxHalfCpltCallback(hsai);
01929 }
01930 /**
01931   * @brief DMA SAI communication error callback.
01932   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01933   *                the configuration information for the specified DMA module.
01934   * @retval None
01935   */
01936 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
01937 {
01938   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01939
01940   /* Stop the DMA transfer */
01941   HAL_SAI_DMAStop(hsai);
01942
01943   /* Set the SAI state ready to be able to start again the process */
01944   hsai->State= HAL_SAI_STATE_READY;
01945   HAL_SAI_ErrorCallback(hsai);
01946
01947   hsai->XferCount = 0;
01948 }
01949
01950 /**
01951   * @}
01952   */
01953
01954 #endif /* HAL_SAI_MODULE_ENABLED */
01955 /**
01956   * @}
01957   */
01958
01959 /**
01960   * @}
01961   */
01962
01963 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai.h Source File

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stm32f7xx_hal_sai.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SAI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SAI_H
00040 #define __STM32F7xx_HAL_SAI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f7xx_hal_def.h"
00049
00050 /** @addtogroup STM32F7xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup SAI
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup SAI_Exported_Types SAI Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL State structures definition
00065   */
00066 typedef enum
00067 {
00068   HAL_SAI_STATE_RESET      = 0x00,  /*!< SAI not yet initialized or disabled                */
00069   HAL_SAI_STATE_READY      = 0x01,  /*!< SAI initialized and ready for use                  */
00070   HAL_SAI_STATE_BUSY       = 0x02,  /*!< SAI internal process is ongoing                    */
00071   HAL_SAI_STATE_BUSY_TX    = 0x12,  /*!< Data transmission process is ongoing               */
00072   HAL_SAI_STATE_BUSY_RX    = 0x22,  /*!< Data reception process is ongoing                  */
00073   HAL_SAI_STATE_TIMEOUT    = 0x03,  /*!< SAI timeout state                                  */
00074   HAL_SAI_STATE_ERROR      = 0x04   /*!< SAI error state                                    */
00075 }HAL_SAI_StateTypeDef;
00076
00077 /**
00078   * @brief  SAI Callback prototype
00079   */
00080 typedef void (*SAIcallback)(void);
00081
00082 /**
00083   * @brief  SAI Init Structure definition
00084   */
00085 typedef struct
00086 {
00087   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00088                                      This parameter can be a value of @ref SAI_Block_Mode                 */
00089
00090   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00091                                      This parameter can be a value of @ref SAI_Block_Synchronization           */
00092
00093   uint32_t SynchroExt;          /*!< Specifies SAI Block synchronization, this setup is common
00094                                      for BLOCKA and BLOCKB
00095                                      This parameter can be a value of @ref SAI_Block_SyncExt                   */
00096
00097   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00098                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00099                                      @note this value has to be set before enabling the audio block
00100                                      but after the audio block configuration.                                  */
00101
00102   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00103                                      This parameter can be a value of @ref SAI_Block_NoDivider
00104                                      @note  If bit NODIV in the SAI_xCR1 register is cleared, the frame length
00105                                             should be aligned to a number equal to a power of 2, from 8 to 256.
00106                                             If bit NODIV in the SAI_xCR1 register is set, the frame length can
00107                                             take any of the values without constraint since the input clock of
00108                                             the audio block should be equal to the bit clock.
00109                                              There is no MCLK_x clock which can be output.                     */
00110
00111   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00112                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold            */
00113
00114   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00115                                      This parameter can be a value of @ref SAI_Audio_Frequency                 */
00116
00117   uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
00118                                      AudioFrequency the user choice
00119                                      This parameter must be a number between Min_Data = 0 and Max_Data = 15    */
00120
00121   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00122                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode                */
00123
00124   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00125                                      This parameter can be a value of @ref SAI_Block_Companding_Mode           */
00126
00127   uint32_t TriState;            /*!< Specifies the companding mode type.
00128                                      This parameter can be a value of @ref SAI_TRIState_Management             */
00129
00130   /* This part of the structure is automatically filled if your are using the high level initialisation
00131      function HAL_SAI_InitProtocol                                                                             */
00132
00133   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00134                                  This parameter can be a value of @ref SAI_Block_Protocol                      */
00135
00136   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00137                                  This parameter can be a value of @ref SAI_Block_Data_Size                     */
00138
00139   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00140                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission          */
00141
00142   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00143                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing                */
00144 }SAI_InitTypeDef;
00145
00146 /**
00147   * @brief  SAI Block Frame Init structure definition
00148   */
00149
00150 typedef struct
00151 {
00152
00153   uint32_t FrameLength;         /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00154                                      This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00155                                      @note  If master clock MCLK_x pin is declared as an output, the frame length
00156                                             should be aligned to a number equal to power of 2 in order to keep
00157                                             in an audio frame, an integer number of MCLK pulses by bit Clock. */
00158
00159   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00160                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00161                                     of the active level of FS signal in audio frame.
00162                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00163
00164   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00165                                     This parameter can be a value of @ref SAI_Block_FS_Definition             */
00166
00167   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00168                                     This parameter can be a value of @ref SAI_Block_FS_Polarity               */
00169
00170   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00171                                     This parameter can be a value of @ref SAI_Block_FS_Offset                 */
00172
00173 }SAI_FrameInitTypeDef;
00174
00175 /**
00176   * @brief   SAI Block Slot Init Structure definition
00177   */
00178
00179 typedef struct
00180 {
00181   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00182                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00183
00184   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00185                                  This parameter can be a value of @ref SAI_Block_Slot_Size              */
00186
00187   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00188                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00189
00190   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00191                                  This parameter can be a value of @ref SAI_Block_Slot_Active            */
00192 }SAI_SlotInitTypeDef;
00193
00194 /**
00195   * @brief  SAI handle Structure definition
00196   */
00197 typedef struct __SAI_HandleTypeDef
00198 {
00199   SAI_Block_TypeDef         *Instance;  /*!< SAI Blockx registers base address        */
00200
00201   SAI_InitTypeDef           Init;       /*!< SAI communication parameters             */
00202
00203   SAI_FrameInitTypeDef      FrameInit;  /*!< SAI Frame configuration parameters       */
00204
00205   SAI_SlotInitTypeDef       SlotInit;   /*!< SAI Slot configuration parameters        */
00206
00207   uint8_t                  *pBuffPtr;  /*!< Pointer to SAI transfer Buffer            */
00208
00209   uint16_t                  XferSize;  /*!< SAI transfer size                         */
00210
00211   uint16_t                  XferCount; /*!< SAI transfer counter                      */
00212
00213   DMA_HandleTypeDef         *hdmatx;     /*!< SAI Tx DMA handle parameters            */
00214
00215   DMA_HandleTypeDef         *hdmarx;     /*!< SAI Rx DMA handle parameters            */
00216
00217   SAIcallback               mutecallback;/*!< SAI mute callback                */
00218
00219   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler   */
00220
00221   HAL_LockTypeDef           Lock;        /*!< SAI locking object                      */
00222
00223   __IO HAL_SAI_StateTypeDef State;       /*!< SAI communication state                 */
00224
00225   __IO uint32_t             ErrorCode;   /*!< SAI Error code                          */
00226 }SAI_HandleTypeDef;
00227
00228 /**
00229   * @}
00230   */
00231
00232 /* Exported constants --------------------------------------------------------*/
00233
00234 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00235   * @{
00236   */
00237
00238 /** @defgroup SAI_Error_Code SAI Error Code
00239   * @{
00240   */
00241 #define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000)  /*!< No error                                    */
00242 #define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001)  /*!< Overrun Error                               */
00243 #define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002)  /*!< Underrun error                              */
00244 #define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004)  /*!< Anticipated Frame synchronisation detection */
00245 #define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008)  /*!< Late Frame synchronisation detection        */
00246 #define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010)  /*!< codec not ready                             */
00247 #define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020)  /*!< Wrong clock configuration                   */
00248 #define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040)  /*!< Timeout error                               */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00254   * @{
00255   */
00256 #define SAI_SYNCEXT_DISABLE           ((uint32_t)0x00000000)
00257 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE  ((uint32_t)0x00000001)
00258 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE  ((uint32_t)0x00000002)
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup SAI_Protocol SAI Supported protocol
00264   * @{
00265   */
00266 #define SAI_I2S_STANDARD      ((uint32_t)0x00000000)
00267 #define SAI_I2S_MSBJUSTIFIED  ((uint32_t)0x00000001)
00268 #define SAI_I2S_LSBJUSTIFIED  ((uint32_t)0x00000002)
00269 #define SAI_PCM_LONG          ((uint32_t)0x00000004)
00270 #define SAI_PCM_SHORT         ((uint32_t)0x00000008)
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00276   * @{
00277   */
00278 #define SAI_PROTOCOL_DATASIZE_16BIT          ((uint32_t)0x00000000)
00279 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED  ((uint32_t)0x00000001)
00280 #define SAI_PROTOCOL_DATASIZE_24BIT          ((uint32_t)0x00000002)
00281 #define SAI_PROTOCOL_DATASIZE_32BIT          ((uint32_t)0x00000004)
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SAI_Clock_Source  SAI Clock Source
00287   * @{
00288   */
00289 #define SAI_CLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
00290 #define SAI_CLKSOURCE_PLLI2S             ((uint32_t)0x00100000)
00291 #define SAI_CLKSOURCE_EXT                ((uint32_t)0x00200000)
00292 #define SAI_CLKSOURCE_NA                 ((uint32_t)0x00400000)
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00298   * @{
00299   */
00300 #define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000)
00301 #define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000)
00302 #define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000)
00303 #define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100)
00304 #define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000)
00305 #define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050)
00306 #define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000)
00307 #define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025)
00308 #define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000)
00309 #define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0)
00310
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup SAI_Block_Mode SAI Block Mode
00316   * @{
00317   */
00318 #define SAI_MODEMASTER_TX         ((uint32_t)0x00000000)
00319 #define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
00320 #define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
00321 #define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
00322
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00328   * @{
00329   */
00330 #define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000)
00331 #define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
00332 #define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
00333
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00339   * @{
00340   */
00341 #define SAI_DATASIZE_8                   ((uint32_t)SAI_xCR1_DS_1)
00342 #define SAI_DATASIZE_10                  ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00343 #define SAI_DATASIZE_16                  ((uint32_t)SAI_xCR1_DS_2)
00344 #define SAI_DATASIZE_20                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
00345 #define SAI_DATASIZE_24                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
00346 #define SAI_DATASIZE_32                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00347
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00353   * @{
00354   */
00355 #define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000)
00356 #define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
00357
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00363   * @{
00364   */
00365 #define SAI_CLOCKSTROBING_FALLINGEDGE     ((uint32_t)0x00000000)
00366 #define SAI_CLOCKSTROBING_RISINGEDGE      ((uint32_t)0x00000001)
00367
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00373   * @{
00374   */
00375 #define SAI_ASYNCHRONOUS                  ((uint32_t)0x00000000) /*!< Asynchronous */
00376 #define SAI_SYNCHRONOUS                   ((uint32_t)0x00000001) /*!< Synchronous with other block of same SAI */
00377 #define SAI_SYNCHRONOUS_EXT_SAI1          ((uint32_t)0x00000002) /*!< Synchronous with other SAI, SAI1 */
00378 #define SAI_SYNCHRONOUS_EXT_SAI2          ((uint32_t)0x00000003) /*!< Synchronous with other SAI, SAI2 */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00384   * @{
00385   */
00386 #define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000)
00387 #define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
00388
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00394   * @{
00395   */
00396 #define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000)
00397 #define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
00398
00399 /**
00400   * @}
00401   */
00402
00403
00404 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00405   * @{
00406   */
00407 #define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000)
00408 #define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
00409
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00415   * @{
00416   */
00417 #define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000)
00418 #define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPO)
00419
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00425   * @{
00426   */
00427 #define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000)
00428 #define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
00429
00430 /**
00431   * @}
00432   */
00433
00434
00435   /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00436   * @{
00437   */
00438 #define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000)
00439 #define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
00440 #define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00446   * @{
00447   */
00448 #define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000)
00449 #define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001)
00450 #define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002)
00451 #define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004)
00452 #define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008)
00453 #define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010)
00454 #define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020)
00455 #define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040)
00456 #define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080)
00457 #define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100)
00458 #define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200)
00459 #define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400)
00460 #define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800)
00461 #define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000)
00462 #define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000)
00463 #define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000)
00464 #define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000)
00465 #define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFF)
00466
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00472   * @{
00473   */
00474 #define SAI_STEREOMODE                    ((uint32_t)0x00000000)
00475 #define SAI_MONOMODE                      ((uint32_t)SAI_xCR1_MONO)
00476
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00482   * @{
00483   */
00484 #define SAI_OUTPUT_NOTRELEASED              ((uint32_t)0x00000000)
00485 #define SAI_OUTPUT_RELEASED                 ((uint32_t)SAI_xCR2_TRIS)
00486
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00492   * @{
00493   */
00494 #define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000)
00495 #define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)SAI_xCR2_FTH_0)
00496 #define SAI_FIFOTHRESHOLD_HF     ((uint32_t)SAI_xCR2_FTH_1)
00497 #define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
00498 #define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)SAI_xCR2_FTH_2)
00499
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00505   * @{
00506   */
00507 #define SAI_NOCOMPANDING                  ((uint32_t)0x00000000)
00508 #define SAI_ULAW_1CPL_COMPANDING          ((uint32_t)SAI_xCR2_COMP_1)
00509 #define SAI_ALAW_1CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
00510 #define SAI_ULAW_2CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
00511 #define SAI_ALAW_2CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
00512
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00518   * @{
00519   */
00520 #define SAI_ZERO_VALUE                     ((uint32_t)0x00000000)
00521 #define SAI_LAST_SENT_VALUE                 ((uint32_t)SAI_xCR2_MUTEVAL)
00522
00523 /**
00524   * @}
00525   */
00526
00527
00528 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00529   * @{
00530   */
00531 #define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
00532 #define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
00533 #define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
00534 #define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
00535 #define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
00536 #define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
00537 #define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
00538
00539 /**
00540   * @}
00541   */
00542
00543 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00544   * @{
00545   */
00546 #define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
00547 #define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
00548 #define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
00549 #define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
00550 #define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
00551 #define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
00552 #define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
00553
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00559   * @{
00560   */
00561 #define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000)
00562 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000)
00563 #define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000)
00564 #define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000)
00565 #define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000)
00566 #define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000)
00567
00568 /**
00569   * @}
00570   */
00571
00572 /**
00573   * @}
00574   */
00575
00576 /* Exported macro ------------------------------------------------------------*/
00577
00578 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00579  *  @brief macros to handle interrupts and specific configurations
00580  * @{
00581  */
00582
00583 /** @brief Reset SAI handle state
00584   * @param  __HANDLE__: specifies the SAI Handle.
00585   * @retval None
00586   */
00587 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00588
00589 /** @brief  Enable or disable the specified SAI interrupts.
00590   * @param  __HANDLE__: specifies the SAI Handle.
00591   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00592   *         This parameter can be one of the following values:
00593   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00594   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00595   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00596   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00597   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00598   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00599   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
00600   * @retval None
00601   */
00602
00603 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00604 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00605
00606 /** @brief  Check if the specified SAI interrupt source is enabled or disabled.
00607   * @param  __HANDLE__: specifies the SAI Handle.
00608   *         This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
00609   * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
00610   *         This parameter can be one of the following values:
00611   *            @arg SAI_IT_TXE: Tx buffer empty interrupt enable.
00612   *            @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.
00613   *            @arg SAI_IT_ERR: Error interrupt enable.
00614   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00615   */
00616 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00617
00618 /** @brief  Check whether the specified SAI flag is set or not.
00619   * @param  __HANDLE__: specifies the SAI Handle.
00620   * @param  __FLAG__: specifies the flag to check.
00621   *         This parameter can be one of the following values:
00622   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00623   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00624   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00625   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00626   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00627   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00628   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00629   * @retval The new state of __FLAG__ (TRUE or FALSE).
00630   */
00631 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00632
00633 /** @brief  Clears the specified SAI pending flag.
00634   * @param  __HANDLE__: specifies the SAI Handle.
00635   * @param  __FLAG__: specifies the flag to check.
00636   *          This parameter can be any combination of the following values:
00637   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00638   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00639   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00640   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00641   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00642   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00643   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00644   *
00645   * @retval None
00646   */
00647 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00648
00649 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00650 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00651
00652  /**
00653   * @}
00654   */
00655
00656 /* Include RCC SAI Extension module */
00657 #include "stm32f7xx_hal_sai_ex.h"
00658
00659 /* Exported functions --------------------------------------------------------*/
00660
00661 /** @addtogroup SAI_Exported_Functions
00662   * @{
00663   */
00664
00665 /* Initialization/de-initialization functions  **********************************/
00666 /** @addtogroup SAI_Exported_Functions_Group1
00667   * @{
00668   */
00669 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00670 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00671 HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
00672 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00673 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00674
00675 /**
00676   * @}
00677   */
00678
00679 /* I/O operation functions  *****************************************************/
00680 /** @addtogroup SAI_Exported_Functions_Group2
00681   * @{
00682   */
00683 /* Blocking mode: Polling */
00684 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00685 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00686
00687 /* Non-Blocking mode: Interrupt */
00688 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00689 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00690
00691 /* Non-Blocking mode: DMA */
00692 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00693 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00694 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00695 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00696 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00697
00698 /* Abort function */
00699 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00700
00701 /* Mute management */
00702 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00703 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00704 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00705 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00706
00707 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00708 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00709 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00710 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00711 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00712 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00713 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00714 /**
00715   * @}
00716   */
00717
00718 /** @addtogroup SAI_Exported_Functions_Group3
00719   * @{
00720   */
00721 /* Peripheral State functions  **************************************************/
00722 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
00723 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
00724 /**
00725   * @}
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /* Private types -------------------------------------------------------------*/
00733 /** @defgroup SAI_Private_Types SAI Private Types
00734   * @{
00735   */
00736
00737 /**
00738   * @}
00739   */
00740
00741 /* Private variables ---------------------------------------------------------*/
00742 /** @defgroup SAI_Private_Variables SAI Private Variables
00743   * @{
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /* Private constants ---------------------------------------------------------*/
00751 /** @defgroup SAI_Private_Constants SAI Private Constants
00752   * @{
00753   */
00754
00755 /**
00756   * @}
00757   */
00758
00759 /* Private macros ------------------------------------------------------------*/
00760 /** @addtogroup SAI_Private_Macros
00761   * @{
00762   */
00763 #define IS_SAI_BLOCK_SYNCEXT(STATE)   (((STATE) == SAI_SYNCEXT_DISABLE)           ||\
00764                                        ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE)  ||\
00765                                        ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
00766
00767 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00768                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00769                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00770                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00771                                                ((PROTOCOL) == SAI_PCM_SHORT))
00772
00773 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00774                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00775                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00776                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00777
00778 #define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
00779                                    ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
00780                                    ((SOURCE) == SAI_CLKSOURCE_EXT))
00781
00782 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00783                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00784                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00785                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00786                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00787
00788 #define IS_SAI_BLOCK_MODE(MODE)    (((MODE) == SAI_MODEMASTER_TX) || \
00789                                     ((MODE) == SAI_MODEMASTER_RX) || \
00790                                     ((MODE) == SAI_MODESLAVE_TX)  || \
00791                                     ((MODE) == SAI_MODESLAVE_RX))
00792
00793 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00794                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00795                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00796
00797 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00798                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00799                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00800                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00801                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00802                                          ((DATASIZE) == SAI_DATASIZE_32))
00803
00804 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00805                                      ((BIT) == SAI_FIRSTBIT_LSB))
00806
00807 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00808                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00809
00810 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
00811                                        ((SYNCHRO) == SAI_SYNCHRONOUS)  || \
00812                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
00813                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
00814
00815 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00816                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00817
00818 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00819                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00820
00821 #define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \
00822                                           ((STATUS) == SAI_FIFOSTATUS_HALFFULL)          || \
00823                                           ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL)      || \
00824                                           ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL)     || \
00825                                           ((STATUS) == SAI_FIFOSTATUS_FULL)              || \
00826                                           ((STATUS) == SAI_FIFOSTATUS_EMPTY))
00827
00828 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
00829
00830 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00831                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00832
00833 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00834                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00835                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00836                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00837                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00838
00839 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00840                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00841                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00842                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00843                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00844
00845 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00846                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00847
00848 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00849                                        ((MODE) == SAI_STEREOMODE))
00850
00851 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00852
00853 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
00854
00855 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00856                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00857                                       ((SIZE) == SAI_SLOTSIZE_32B))
00858
00859 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
00860
00861 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00862                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00863
00864 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00865                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00866
00867 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00868                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00869
00870 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
00871
00872 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
00873
00874 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
00875
00876 /**
00877   * @}
00878   */
00879
00880 /* Private functions ---------------------------------------------------------*/
00881 /** @defgroup SAI_Private_Functions SAI Private Functions
00882   * @{
00883   */
00884
00885 /**
00886   * @}
00887   */
00888
00889 /**
00890   * @}
00891   */
00892
00893 /**
00894   * @}
00895   */
00896
00897 #ifdef __cplusplus
00898 }
00899 #endif
00900
00901 #endif /* __STM32F7xx_HAL_SAI_H */
00902
00903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai_ex.c Source File

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stm32f7xx_hal_sai_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sai_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SAI Extension HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of SAI extension peripheral:
00010   *           + Extension features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### SAI peripheral extension features  #####
00015   ==============================================================================
00016
00017                      ##### How to use this driver #####
00018   ==============================================================================
00019   [..] This driver provides functions to manage several sources to clock SAI
00020
00021   @endverbatim
00022   ******************************************************************************
00023   * @attention
00024   *
00025   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00026   *
00027   * Redistribution and use in source and binary forms, with or without modification,
00028   * are permitted provided that the following conditions are met:
00029   *   1. Redistributions of source code must retain the above copyright notice,
00030   *      this list of conditions and the following disclaimer.
00031   *   2. Redistributions in binary form must reproduce the above copyright notice,
00032   *      this list of conditions and the following disclaimer in the documentation
00033   *      and/or other materials provided with the distribution.
00034   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00035   *      may be used to endorse or promote products derived from this software
00036   *      without specific prior written permission.
00037   *
00038   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00039   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00040   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00041   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00042   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00043   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00044   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00045   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00046   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00047   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00048   *
00049   ******************************************************************************
00050   */
00051
00052 /* Includes ------------------------------------------------------------------*/
00053 #include "stm32f7xx_hal.h"
00054
00055 /** @addtogroup STM32F7xx_HAL_Driver
00056   * @{
00057   */
00058
00059 /** @defgroup SAIEx SAIEx
00060   * @brief SAI Extension HAL module driver
00061   * @{
00062   */
00063
00064 #ifdef HAL_SAI_MODULE_ENABLED
00065
00066 /* Private typedef -----------------------------------------------------------*/
00067 /* Private define ------------------------------------------------------------*/
00068 /* SAI registers Masks */
00069 /* Private macro -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073
00074 /** @defgroup SAI_Private_Functions  SAI Private Functions
00075   * @{
00076   */
00077  /**
00078   * @}
00079   */
00080
00081 /* Exported functions --------------------------------------------------------*/
00082 /** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
00083   * @{
00084   */
00085
00086 /** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
00087   *  @brief   Extension features functions
00088   *
00089 @verbatim
00090  ===============================================================================
00091                        ##### Extension features Functions #####
00092  ===============================================================================
00093     [..]
00094     This subsection provides a set of functions allowing to manage the possible
00095     SAI clock sources.
00096
00097 @endverbatim
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  Configure SAI Block synchronization mode
00103   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00104   *               the configuration information for SAI module.
00105   * @retval SAI Clock Input
00106   */
00107 void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
00108 {
00109   uint32_t tmpregisterGCR = 0;
00110
00111   /* This setting must be done with both audio block (A & B) disabled     */
00112   switch(hsai->Init.SynchroExt)
00113   {
00114     case SAI_SYNCEXT_DISABLE :
00115       tmpregisterGCR = 0;
00116       break;
00117     case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
00118       tmpregisterGCR = SAI_GCR_SYNCOUT_0;
00119       break;
00120     case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
00121       tmpregisterGCR = SAI_GCR_SYNCOUT_1;
00122       break;
00123   default:
00124     tmpregisterGCR = 0;
00125     break;
00126   }
00127
00128   if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
00129   {
00130         tmpregisterGCR |= SAI_GCR_SYNCIN_0;
00131   }
00132
00133   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00134   {
00135     SAI1->GCR = tmpregisterGCR;
00136   }
00137   else
00138   {
00139     SAI2->GCR = tmpregisterGCR;
00140   }
00141 }
00142   /**
00143   * @brief  Get SAI Input Clock based on SAI source clock selection
00144   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00145   *               the configuration information for SAI module.
00146   * @retval SAI Clock Input
00147   */
00148 uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
00149 {
00150   /* This variable used to store the SAI_CK_x (value in Hz) */
00151   uint32_t saiclocksource = 0;
00152
00153   if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00154   {
00155     saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00156   }
00157   else /* SAI2_Block_A || SAI2_Block_B*/
00158   {
00159     saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
00160   }
00161   /* the return result is the value of SAI clock */
00162   return saiclocksource;
00163 }
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 #endif /* HAL_SAI_MODULE_ENABLED */
00174 /**
00175   * @}
00176   */
00177
00178 /**
00179   * @}
00180   */
00181
00182 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sai_ex.h Source File

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  • Inc
stm32f7xx_hal_sai_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sai_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SAI Extension HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SAI_EX_H
00040 #define __STM32F7xx_HAL_SAI_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SAIEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup SAIEx_Exported_Functions SAI Extended Exported Functions
00061   * @{
00062   */
00063
00064 /** @addtogroup SAIEx_Exported_Functions_Group1 Extension features functions
00065   * @{
00066   */
00067
00068 /* Extended features functions ************************************************/
00069 void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
00070 uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078 /* Private types -------------------------------------------------------------*/
00079 /* Private variables ---------------------------------------------------------*/
00080 /* Private constants ---------------------------------------------------------*/
00081 /* Private macros ------------------------------------------------------------*/
00082 /* Private functions ---------------------------------------------------------*/
00083
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 #ifdef __cplusplus
00093 }
00094 #endif
00095
00096 #endif /* __STM32F7xx_HAL_SAI_EX_H */
00097
00098 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sd.c Source File

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stm32f7xx_hal_sd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SD card HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (SD) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     This driver implements a high level communication layer for read and write from/to
00021     this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
00022     the user in HAL_SD_MspInit() function (MSP layer).
00023     Basically, the MSP layer configuration should be the same as we provide in the
00024     examples.
00025     You can easily tailor this configuration according to hardware resources.
00026
00027   [..]
00028     This driver is a generic layered driver for SDMMC memories which uses the HAL
00029     SDMMC driver functions to interface with SD and uSD cards devices.
00030     It is used as follows:
00031
00032     (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
00033         (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
00034         (##) SDMMC pins configuration for SD card
00035             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00036             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
00037                   and according to your pin assignment;
00038         (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
00039              and HAL_SD_WriteBlocks_DMA() APIs).
00040             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
00041             (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
00042         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
00043             (+++) Configure the SDMMC and DMA interrupt priorities using functions
00044                   HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
00045             (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
00046             (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT()
00047                   and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.
00048             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()
00049                   and __HAL_SD_SDMMC_CLEAR_IT()
00050     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
00051
00052
00053   *** SD Card Initialization and configuration ***
00054   ================================================
00055   [..]
00056     To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
00057     the SD Card and put it into StandBy State (Ready for data transfer).
00058     This function provide the following operations:
00059
00060     (#) Apply the SD Card initialization process at 400KHz and check the SD Card
00061         type (Standard Capacity or High Capacity). You can change or adapt this
00062         frequency by adjusting the "ClockDiv" field.
00063         The SD Card frequency (SDMMC_CK) is computed as follows:
00064
00065            SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
00066
00067         In initialization mode and according to the SD Card standard,
00068         make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
00069
00070     (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
00071         structure. This structure provide also ready computed SD Card capacity
00072         and Block size.
00073
00074         -@- These information are stored in SD handle structure in case of future use.
00075
00076     (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
00077         frequency is set to 24MHz. You can change or adapt this frequency by adjusting
00078         the "ClockDiv" field.
00079         In transfer mode and according to the SD Card standard, make sure that the
00080         SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
00081         To be able to use a frequency higher than 24MHz, you should use the SDMMC
00082         peripheral in bypass mode. Refer to the corresponding reference manual
00083         for more details.
00084
00085     (#) Select the corresponding SD Card according to the address read with the step 2.
00086
00087     (#) Configure the SD Card in wide bus mode: 4-bits data.
00088
00089   *** SD Card Read operation ***
00090   ==============================
00091   [..]
00092     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
00093         This function support only 512-bytes block length (the block size should be
00094         chosen as 512 bytes).
00095         You can choose either one block read operation or multiple block read operation
00096         by adjusting the "NumberOfBlocks" parameter.
00097
00098     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
00099         This function support only 512-bytes block length (the block size should be
00100         chosen as 512 bytes).
00101         You can choose either one block read operation or multiple block read operation
00102         by adjusting the "NumberOfBlocks" parameter.
00103         After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
00104         that the read transfer is done correctly in both DMA and SD sides.
00105
00106   *** SD Card Write operation ***
00107   ===============================
00108   [..]
00109     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
00110         This function support only 512-bytes block length (the block size should be
00111         chosen as 512 bytes).
00112         You can choose either one block read operation or multiple block read operation
00113         by adjusting the "NumberOfBlocks" parameter.
00114
00115     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
00116         This function support only 512-bytes block length (the block size should be
00117         chosen as 512 byte).
00118         You can choose either one block read operation or multiple block read operation
00119         by adjusting the "NumberOfBlocks" parameter.
00120         After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
00121         that the write transfer is done correctly in both DMA and SD sides.
00122
00123   *** SD card status ***
00124   ======================
00125   [..]
00126     (+) At any time, you can check the SD Card status and get the SD card state
00127         by using the HAL_SD_GetStatus() function. This function checks first if the
00128         SD card is still connected and then get the internal SD Card transfer state.
00129     (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
00130         function.
00131
00132   *** SD HAL driver macros list ***
00133   ==================================
00134   [..]
00135     Below the list of most used macros in SD HAL driver.
00136
00137     (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device
00138     (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device
00139     (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer
00140     (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer
00141     (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt
00142     (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt
00143     (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not
00144     (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags
00145
00146     (@) You can refer to the SD HAL driver header file for more useful macros
00147
00148   @endverbatim
00149   ******************************************************************************
00150   * @attention
00151   *
00152   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00153   *
00154   * Redistribution and use in source and binary forms, with or without modification,
00155   * are permitted provided that the following conditions are met:
00156   *   1. Redistributions of source code must retain the above copyright notice,
00157   *      this list of conditions and the following disclaimer.
00158   *   2. Redistributions in binary form must reproduce the above copyright notice,
00159   *      this list of conditions and the following disclaimer in the documentation
00160   *      and/or other materials provided with the distribution.
00161   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00162   *      may be used to endorse or promote products derived from this software
00163   *      without specific prior written permission.
00164   *
00165   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00166   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00167   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00168   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00169   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00170   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00171   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00172   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00173   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00174   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00175   *
00176   ******************************************************************************
00177   */
00178
00179 /* Includes ------------------------------------------------------------------*/
00180 #include "stm32f7xx_hal.h"
00181
00182 /** @addtogroup STM32F7xx_HAL_Driver
00183   * @{
00184   */
00185
00186 /** @addtogroup SD
00187   * @{
00188   */
00189
00190 #ifdef HAL_SD_MODULE_ENABLED
00191
00192 /* Private typedef -----------------------------------------------------------*/
00193 /* Private define ------------------------------------------------------------*/
00194 /** @addtogroup SD_Private_Defines
00195   * @{
00196   */
00197 /**
00198   * @brief  SDMMC Data block size
00199   */
00200 #define DATA_BLOCK_SIZE                  ((uint32_t)(9 << 4))
00201 /**
00202   * @brief  SDMMC Static flags, Timeout, FIFO Address
00203   */
00204 #define SDMMC_STATIC_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
00205                                                     SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
00206                                                     SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
00207                                                     SDMMC_FLAG_DBCKEND))
00208
00209 #define SDMMC_CMD0TIMEOUT                ((uint32_t)0x00010000)
00210
00211 /**
00212   * @brief  Mask for errors Card Status R1 (OCR Register)
00213   */
00214 #define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
00215 #define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
00216 #define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
00217 #define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
00218 #define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
00219 #define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
00220 #define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
00221 #define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
00222 #define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
00223 #define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
00224 #define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
00225 #define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
00226 #define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
00227 #define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
00228 #define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000)
00229 #define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
00230 #define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
00231 #define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
00232 #define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
00233 #define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
00234
00235 /**
00236   * @brief  Masks for R6 Response
00237   */
00238 #define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
00239 #define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
00240 #define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
00241
00242 #define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
00243 #define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
00244 #define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
00245 #define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
00246
00247 #define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
00248 #define SD_ALLZERO                      ((uint32_t)0x00000000)
00249
00250 #define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
00251 #define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
00252 #define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
00253
00254 #define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
00255 #define SD_0TO7BITS                     ((uint32_t)0x000000FF)
00256 #define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
00257 #define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
00258 #define SD_24TO31BITS                   ((uint32_t)0xFF000000)
00259 #define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
00260
00261 #define SD_HALFFIFO                     ((uint32_t)0x00000008)
00262 #define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
00263
00264 /**
00265   * @brief  Command Class Supported
00266   */
00267 #define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
00268 #define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
00269 #define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
00270
00271 /**
00272   * @brief  Following commands are SD Card Specific commands.
00273   *         SDMMC_APP_CMD should be sent before sending these commands.
00274   */
00275 #define SD_SDMMC_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
00276 /**
00277   * @}
00278   */
00279
00280 /* Private macro -------------------------------------------------------------*/
00281 /* Private variables ---------------------------------------------------------*/
00282 /* Private function prototypes -----------------------------------------------*/
00283 /* Private functions ---------------------------------------------------------*/
00284 /** @defgroup SD_Private_Functions SD Private Functions
00285   * @{
00286   */
00287 static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
00288 static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
00289 static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
00290 static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
00291 static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
00292 static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
00293 static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
00294 static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
00295 static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
00296 static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
00297 static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
00298 static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
00299 static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
00300 static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
00301 static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
00302 static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
00303 static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
00304 static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
00305 static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
00306 static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
00307 /**
00308   * @}
00309   */
00310 /* Exported functions --------------------------------------------------------*/
00311 /** @addtogroup SD_Exported_Functions
00312   * @{
00313   */
00314
00315 /** @addtogroup SD_Exported_Functions_Group1
00316  *  @brief   Initialization and de-initialization functions
00317  *
00318 @verbatim
00319   ==============================================================================
00320           ##### Initialization and de-initialization functions #####
00321   ==============================================================================
00322   [..]
00323     This section provides functions allowing to initialize/de-initialize the SD
00324     card device to be ready for use.
00325
00326
00327 @endverbatim
00328   * @{
00329   */
00330
00331 /**
00332   * @brief  Initializes the SD card according to the specified parameters in the
00333             SD_HandleTypeDef and create the associated handle.
00334   * @param  hsd: SD handle
00335   * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information
00336   * @retval HAL SD error state
00337   */
00338 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
00339 {
00340   __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
00341   SD_InitTypeDef tmpinit;
00342
00343   /* Allocate lock resource and initialize it */
00344   hsd->Lock = HAL_UNLOCKED;
00345
00346   /* Initialize the low level hardware (MSP) */
00347   HAL_SD_MspInit(hsd);
00348
00349   /* Default SDMMC peripheral configuration for SD card initialization */
00350   tmpinit.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
00351   tmpinit.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
00352   tmpinit.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
00353   tmpinit.BusWide             = SDMMC_BUS_WIDE_1B;
00354   tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
00355   tmpinit.ClockDiv            = SDMMC_INIT_CLK_DIV;
00356
00357   /* Initialize SDMMC peripheral interface with default configuration */
00358   SDMMC_Init(hsd->Instance, tmpinit);
00359
00360   /* Identify card operating voltage */
00361   errorstate = SD_PowerON(hsd);
00362
00363   if(errorstate != SD_OK)
00364   {
00365     return errorstate;
00366   }
00367
00368   /* Initialize the present SDMMC card(s) and put them in idle state */
00369   errorstate = SD_Initialize_Cards(hsd);
00370
00371   if (errorstate != SD_OK)
00372   {
00373     return errorstate;
00374   }
00375
00376   /* Read CSD/CID MSD registers */
00377   errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
00378
00379   if (errorstate == SD_OK)
00380   {
00381     /* Select the Card */
00382     errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
00383   }
00384
00385   /* Configure SDMMC peripheral interface */
00386   SDMMC_Init(hsd->Instance, hsd->Init);
00387
00388   return errorstate;
00389 }
00390
00391 /**
00392   * @brief  De-Initializes the SD card.
00393   * @param  hsd: SD handle
00394   * @retval HAL status
00395   */
00396 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
00397 {
00398
00399   /* Set SD power state to off */
00400   SD_PowerOFF(hsd);
00401
00402   /* De-Initialize the MSP layer */
00403   HAL_SD_MspDeInit(hsd);
00404
00405   return HAL_OK;
00406 }
00407
00408
00409 /**
00410   * @brief  Initializes the SD MSP.
00411   * @param  hsd: SD handle
00412   * @retval None
00413   */
00414 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
00415 {
00416   /* Prevent unused argument(s) compilation warning */
00417   UNUSED(hsd);
00418
00419   /* NOTE : This function Should not be modified, when the callback is needed,
00420             the HAL_SD_MspInit could be implemented in the user file
00421    */
00422 }
00423
00424 /**
00425   * @brief  De-Initialize SD MSP.
00426   * @param  hsd: SD handle
00427   * @retval None
00428   */
00429 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
00430 {
00431   /* Prevent unused argument(s) compilation warning */
00432   UNUSED(hsd);
00433
00434   /* NOTE : This function Should not be modified, when the callback is needed,
00435             the HAL_SD_MspDeInit could be implemented in the user file
00436    */
00437 }
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @addtogroup SD_Exported_Functions_Group2
00444  *  @brief   Data transfer functions
00445  *
00446 @verbatim
00447   ==============================================================================
00448                         ##### IO operation functions #####
00449   ==============================================================================
00450   [..]
00451     This subsection provides a set of functions allowing to manage the data
00452     transfer from/to SD card.
00453
00454 @endverbatim
00455   * @{
00456   */
00457
00458 /**
00459   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00460   *         is managed by polling mode.
00461   * @param  hsd: SD handle
00462   * @param  pReadBuffer: pointer to the buffer that will contain the received data
00463   * @param  ReadAddr: Address from where data is to be read
00464   * @param  BlockSize: SD card Data block size
00465   *   @note BlockSize must be 512 bytes.
00466   * @param  NumberOfBlocks: Number of SD blocks to read
00467   * @retval SD Card error state
00468   */
00469 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00470 {
00471   SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
00472   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00473   HAL_SD_ErrorTypedef errorstate = SD_OK;
00474   uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
00475
00476   /* Initialize data control register */
00477   hsd->Instance->DCTRL = 0;
00478
00479   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00480   {
00481     BlockSize = 512;
00482     ReadAddr /= 512;
00483   }
00484
00485   /* Set Block Size for Card */
00486   sdmmc_cmdinitstructure.Argument         = (uint32_t) BlockSize;
00487   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00488   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
00489   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
00490   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
00491   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00492
00493   /* Check for error conditions */
00494   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00495
00496   if (errorstate != SD_OK)
00497   {
00498     return errorstate;
00499   }
00500
00501   /* Configure the SD DPSM (Data Path State Machine) */
00502   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00503   sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
00504   sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
00505   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00506   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00507   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
00508   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
00509
00510   if(NumberOfBlocks > 1)
00511   {
00512     /* Send CMD18 READ_MULT_BLOCK with argument data address */
00513     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
00514   }
00515   else
00516   {
00517     /* Send CMD17 READ_SINGLE_BLOCK */
00518     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
00519   }
00520
00521   sdmmc_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
00522   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00523
00524   /* Read block(s) in polling mode */
00525   if(NumberOfBlocks > 1)
00526   {
00527     /* Check for error conditions */
00528     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
00529
00530     if (errorstate != SD_OK)
00531     {
00532       return errorstate;
00533     }
00534
00535     /* Poll on SDMMC flags */
00536     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00537     {
00538       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
00539       {
00540         /* Read data from SDMMC Rx FIFO */
00541         for (count = 0; count < 8; count++)
00542         {
00543           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
00544         }
00545
00546         tempbuff += 8;
00547       }
00548     }
00549   }
00550   else
00551   {
00552     /* Check for error conditions */
00553     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
00554
00555     if (errorstate != SD_OK)
00556     {
00557       return errorstate;
00558     }
00559
00560     /* In case of single block transfer, no need of stop transfer at all */
00561     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
00562     {
00563       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
00564       {
00565         /* Read data from SDMMC Rx FIFO */
00566         for (count = 0; count < 8; count++)
00567         {
00568           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
00569         }
00570
00571         tempbuff += 8;
00572       }
00573     }
00574   }
00575
00576   /* Send stop transmission command in case of multiblock read */
00577   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
00578   {
00579     if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
00580       (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
00581         (hsd->CardType == HIGH_CAPACITY_SD_CARD))
00582     {
00583       /* Send stop transmission command */
00584       errorstate = HAL_SD_StopTransfer(hsd);
00585     }
00586   }
00587
00588   /* Get error state */
00589   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00590   {
00591     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
00592
00593     errorstate = SD_DATA_TIMEOUT;
00594
00595     return errorstate;
00596   }
00597   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00598   {
00599     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
00600
00601     errorstate = SD_DATA_CRC_FAIL;
00602
00603     return errorstate;
00604   }
00605   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
00606   {
00607     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
00608
00609     errorstate = SD_RX_OVERRUN;
00610
00611     return errorstate;
00612   }
00613   else
00614   {
00615     /* No error flag set */
00616   }
00617
00618   count = SD_DATATIMEOUT;
00619
00620   /* Empty FIFO if there is still any data */
00621   while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
00622   {
00623     *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
00624     tempbuff++;
00625     count--;
00626   }
00627
00628   /* Clear all the static flags */
00629   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00630
00631   return errorstate;
00632 }
00633
00634 /**
00635   * @brief  Allows to write block(s) to a specified address in a card. The Data
00636   *         transfer is managed by polling mode.
00637   * @param  hsd: SD handle
00638   * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
00639   * @param  WriteAddr: Address from where data is to be written
00640   * @param  BlockSize: SD card Data block size
00641   * @note   BlockSize must be 512 bytes.
00642   * @param  NumberOfBlocks: Number of SD blocks to write
00643   * @retval SD Card error state
00644   */
00645 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00646 {
00647   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
00648   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00649   HAL_SD_ErrorTypedef errorstate = SD_OK;
00650   uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
00651   uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
00652   uint8_t cardstate  = 0;
00653
00654   /* Initialize data control register */
00655   hsd->Instance->DCTRL = 0;
00656
00657   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00658   {
00659     BlockSize = 512;
00660     WriteAddr /= 512;
00661   }
00662
00663   /* Set Block Size for Card */
00664   sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
00665   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00666   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
00667   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
00668   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
00669   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00670
00671   /* Check for error conditions */
00672   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00673
00674   if (errorstate != SD_OK)
00675   {
00676     return errorstate;
00677   }
00678
00679   if(NumberOfBlocks > 1)
00680   {
00681     /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
00682     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
00683   }
00684   else
00685   {
00686     /* Send CMD24 WRITE_SINGLE_BLOCK */
00687     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
00688   }
00689
00690   sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
00691   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00692
00693   /* Check for error conditions */
00694   if(NumberOfBlocks > 1)
00695   {
00696     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
00697   }
00698   else
00699   {
00700     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
00701   }
00702
00703   if (errorstate != SD_OK)
00704   {
00705     return errorstate;
00706   }
00707
00708   /* Set total number of bytes to write */
00709   totalnumberofbytes = NumberOfBlocks * BlockSize;
00710
00711   /* Configure the SD DPSM (Data Path State Machine) */
00712   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00713   sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
00714   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00715   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00716   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00717   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
00718   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
00719
00720   /* Write block(s) in polling mode */
00721   if(NumberOfBlocks > 1)
00722   {
00723     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00724     {
00725       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
00726       {
00727         if ((totalnumberofbytes - bytestransferred) < 32)
00728         {
00729           restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
00730
00731           /* Write data to SDMMC Tx FIFO */
00732           for (count = 0; count < restwords; count++)
00733           {
00734             SDMMC_WriteFIFO(hsd->Instance, tempbuff);
00735             tempbuff++;
00736             bytestransferred += 4;
00737           }
00738         }
00739         else
00740         {
00741           /* Write data to SDMMC Tx FIFO */
00742           for (count = 0; count < 8; count++)
00743           {
00744             SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
00745           }
00746
00747           tempbuff += 8;
00748           bytestransferred += 32;
00749         }
00750       }
00751     }
00752   }
00753   else
00754   {
00755     /* In case of single data block transfer no need of stop command at all */
00756     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
00757     {
00758       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
00759       {
00760         if ((totalnumberofbytes - bytestransferred) < 32)
00761         {
00762           restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
00763
00764           /* Write data to SDMMC Tx FIFO */
00765           for (count = 0; count < restwords; count++)
00766           {
00767             SDMMC_WriteFIFO(hsd->Instance, tempbuff);
00768             tempbuff++;
00769             bytestransferred += 4;
00770           }
00771         }
00772         else
00773         {
00774           /* Write data to SDMMC Tx FIFO */
00775           for (count = 0; count < 8; count++)
00776           {
00777             SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
00778           }
00779
00780           tempbuff += 8;
00781           bytestransferred += 32;
00782         }
00783       }
00784     }
00785   }
00786
00787   /* Send stop transmission command in case of multiblock write */
00788   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
00789   {
00790     if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
00791       (hsd->CardType == HIGH_CAPACITY_SD_CARD))
00792     {
00793       /* Send stop transmission command */
00794       errorstate = HAL_SD_StopTransfer(hsd);
00795     }
00796   }
00797
00798   /* Get error state */
00799   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00800   {
00801     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
00802
00803     errorstate = SD_DATA_TIMEOUT;
00804
00805     return errorstate;
00806   }
00807   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00808   {
00809     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
00810
00811     errorstate = SD_DATA_CRC_FAIL;
00812
00813     return errorstate;
00814   }
00815   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
00816   {
00817     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
00818
00819     errorstate = SD_TX_UNDERRUN;
00820
00821     return errorstate;
00822   }
00823   else
00824   {
00825     /* No error flag set */
00826   }
00827
00828   /* Clear all the static flags */
00829   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00830
00831   /* Wait till the card is in programming state */
00832   errorstate = SD_IsCardProgramming(hsd, &cardstate);
00833
00834   while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
00835   {
00836     errorstate = SD_IsCardProgramming(hsd, &cardstate);
00837   }
00838
00839   return errorstate;
00840 }
00841
00842 /**
00843   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00844   *         is managed by DMA mode.
00845   * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
00846   *         to check the completion of the read process
00847   * @param  hsd: SD handle
00848   * @param  pReadBuffer: Pointer to the buffer that will contain the received data
00849   * @param  ReadAddr: Address from where data is to be read
00850   * @param  BlockSize: SD card Data block size
00851   * @note   BlockSize must be 512 bytes.
00852   * @param  NumberOfBlocks: Number of blocks to read.
00853   * @retval SD Card error state
00854   */
00855 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00856 {
00857   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
00858   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00859   HAL_SD_ErrorTypedef errorstate = SD_OK;
00860
00861   /* Initialize data control register */
00862   hsd->Instance->DCTRL = 0;
00863
00864   /* Initialize handle flags */
00865   hsd->SdTransferCplt  = 0;
00866   hsd->DmaTransferCplt = 0;
00867   hsd->SdTransferErr   = SD_OK;
00868
00869   /* Initialize SD Read operation */
00870   if(NumberOfBlocks > 1)
00871   {
00872     hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
00873   }
00874   else
00875   {
00876     hsd->SdOperation = SD_READ_SINGLE_BLOCK;
00877   }
00878
00879   /* Enable transfer interrupts */
00880   __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
00881                                  SDMMC_IT_DTIMEOUT |\
00882                                  SDMMC_IT_DATAEND  |\
00883                                  SDMMC_IT_RXOVERR));
00884
00885   /* Enable SDMMC DMA transfer */
00886   __HAL_SD_SDMMC_DMA_ENABLE(hsd);
00887
00888   /* Configure DMA user callbacks */
00889   hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
00890   hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
00891
00892   /* Enable the DMA Channel */
00893   HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
00894
00895   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00896   {
00897     BlockSize = 512;
00898     ReadAddr /= 512;
00899   }
00900
00901   /* Set Block Size for Card */
00902   sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
00903   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00904   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
00905   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
00906   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
00907   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00908
00909   /* Check for error conditions */
00910   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00911
00912   if (errorstate != SD_OK)
00913   {
00914     return errorstate;
00915   }
00916
00917   /* Configure the SD DPSM (Data Path State Machine) */
00918   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00919   sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
00920   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00921   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00922   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00923   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
00924   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
00925
00926   /* Check number of blocks command */
00927   if(NumberOfBlocks > 1)
00928   {
00929     /* Send CMD18 READ_MULT_BLOCK with argument data address */
00930     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
00931   }
00932   else
00933   {
00934     /* Send CMD17 READ_SINGLE_BLOCK */
00935     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
00936   }
00937
00938   sdmmc_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
00939   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00940
00941   /* Check for error conditions */
00942   if(NumberOfBlocks > 1)
00943   {
00944     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
00945   }
00946   else
00947   {
00948     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
00949   }
00950
00951   /* Update the SD transfer error in SD handle */
00952   hsd->SdTransferErr = errorstate;
00953
00954   return errorstate;
00955 }
00956
00957
00958 /**
00959   * @brief  Writes block(s) to a specified address in a card. The Data transfer
00960   *         is managed by DMA mode.
00961   * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
00962   *         to check the completion of the write process (by SD current status polling).
00963   * @param  hsd: SD handle
00964   * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
00965   * @param  WriteAddr: Address from where data is to be read
00966   * @param  BlockSize: the SD card Data block size
00967   * @note   BlockSize must be 512 bytes.
00968   * @param  NumberOfBlocks: Number of blocks to write
00969   * @retval SD Card error state
00970   */
00971 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00972 {
00973   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
00974   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00975   HAL_SD_ErrorTypedef errorstate = SD_OK;
00976
00977   /* Initialize data control register */
00978   hsd->Instance->DCTRL = 0;
00979
00980   /* Initialize handle flags */
00981   hsd->SdTransferCplt  = 0;
00982   hsd->DmaTransferCplt = 0;
00983   hsd->SdTransferErr   = SD_OK;
00984
00985   /* Initialize SD Write operation */
00986   if(NumberOfBlocks > 1)
00987   {
00988     hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
00989   }
00990   else
00991   {
00992     hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
00993   }
00994
00995   /* Enable transfer interrupts */
00996   __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
00997                                  SDMMC_IT_DTIMEOUT |\
00998                                  SDMMC_IT_DATAEND  |\
00999                                  SDMMC_IT_TXUNDERR));
01000
01001   /* Configure DMA user callbacks */
01002   hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
01003   hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
01004
01005   /* Enable the DMA Channel */
01006   HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
01007
01008   /* Enable SDMMC DMA transfer */
01009   __HAL_SD_SDMMC_DMA_ENABLE(hsd);
01010
01011   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01012   {
01013     BlockSize = 512;
01014     WriteAddr /= 512;
01015   }
01016
01017   /* Set Block Size for Card */
01018   sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
01019   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01020   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01021   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01022   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01023   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01024
01025   /* Check for error conditions */
01026   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01027
01028   if (errorstate != SD_OK)
01029   {
01030     return errorstate;
01031   }
01032
01033   /* Check number of blocks command */
01034   if(NumberOfBlocks <= 1)
01035   {
01036     /* Send CMD24 WRITE_SINGLE_BLOCK */
01037     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
01038   }
01039   else
01040   {
01041     /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
01042     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
01043   }
01044
01045   sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
01046   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01047
01048   /* Check for error conditions */
01049   if(NumberOfBlocks > 1)
01050   {
01051     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
01052   }
01053   else
01054   {
01055     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
01056   }
01057
01058   if (errorstate != SD_OK)
01059   {
01060     return errorstate;
01061   }
01062
01063   /* Configure the SD DPSM (Data Path State Machine) */
01064   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01065   sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
01066   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01067   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01068   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01069   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
01070   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
01071
01072   hsd->SdTransferErr = errorstate;
01073
01074   return errorstate;
01075 }
01076
01077 /**
01078   * @brief  This function waits until the SD DMA data read transfer is finished.
01079   *         This API should be called after HAL_SD_ReadBlocks_DMA() function
01080   *         to insure that all data sent by the card is already transferred by the
01081   *         DMA controller.
01082   * @param  hsd: SD handle
01083   * @param  Timeout: Timeout duration
01084   * @retval SD Card error state
01085   */
01086 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
01087 {
01088   HAL_SD_ErrorTypedef errorstate = SD_OK;
01089   uint32_t timeout = Timeout;
01090   uint32_t tmp1, tmp2;
01091   HAL_SD_ErrorTypedef tmp3;
01092
01093   /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
01094   tmp1 = hsd->DmaTransferCplt;
01095   tmp2 = hsd->SdTransferCplt;
01096   tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01097
01098   while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
01099   {
01100     tmp1 = hsd->DmaTransferCplt;
01101     tmp2 = hsd->SdTransferCplt;
01102     tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01103     timeout--;
01104   }
01105
01106   timeout = Timeout;
01107
01108   /* Wait until the Rx transfer is no longer active */
01109   while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))
01110   {
01111     timeout--;
01112   }
01113
01114   /* Send stop command in multiblock read */
01115   if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
01116   {
01117     errorstate = HAL_SD_StopTransfer(hsd);
01118   }
01119
01120   if ((timeout == 0) && (errorstate == SD_OK))
01121   {
01122     errorstate = SD_DATA_TIMEOUT;
01123   }
01124
01125   /* Clear all the static flags */
01126   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01127
01128   /* Return error state */
01129   if (hsd->SdTransferErr != SD_OK)
01130   {
01131     return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
01132   }
01133
01134   return errorstate;
01135 }
01136
01137 /**
01138   * @brief  This function waits until the SD DMA data write transfer is finished.
01139   *         This API should be called after HAL_SD_WriteBlocks_DMA() function
01140   *         to insure that all data sent by the card is already transferred by the
01141   *         DMA controller.
01142   * @param  hsd: SD handle
01143   * @param  Timeout: Timeout duration
01144   * @retval SD Card error state
01145   */
01146 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
01147 {
01148   HAL_SD_ErrorTypedef errorstate = SD_OK;
01149   uint32_t timeout = Timeout;
01150   uint32_t tmp1, tmp2;
01151   HAL_SD_ErrorTypedef tmp3;
01152
01153   /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
01154   tmp1 = hsd->DmaTransferCplt;
01155   tmp2 = hsd->SdTransferCplt;
01156   tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01157
01158   while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
01159   {
01160     tmp1 = hsd->DmaTransferCplt;
01161     tmp2 = hsd->SdTransferCplt;
01162     tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01163     timeout--;
01164   }
01165
01166   timeout = Timeout;
01167
01168   /* Wait until the Tx transfer is no longer active */
01169   while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT))  && (timeout > 0))
01170   {
01171     timeout--;
01172   }
01173
01174   /* Send stop command in multiblock write */
01175   if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
01176   {
01177     errorstate = HAL_SD_StopTransfer(hsd);
01178   }
01179
01180   if ((timeout == 0) && (errorstate == SD_OK))
01181   {
01182     errorstate = SD_DATA_TIMEOUT;
01183   }
01184
01185   /* Clear all the static flags */
01186   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01187
01188   /* Return error state */
01189   if (hsd->SdTransferErr != SD_OK)
01190   {
01191     return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
01192   }
01193
01194   /* Wait until write is complete */
01195   while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
01196   {
01197   }
01198
01199   return errorstate;
01200 }
01201
01202 /**
01203   * @brief  Erases the specified memory area of the given SD card.
01204   * @param  hsd: SD handle
01205   * @param  startaddr: Start byte address
01206   * @param  endaddr: End byte address
01207   * @retval SD Card error state
01208   */
01209 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
01210 {
01211   HAL_SD_ErrorTypedef errorstate = SD_OK;
01212   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
01213
01214   uint32_t delay         = 0;
01215   __IO uint32_t maxdelay = 0;
01216   uint8_t cardstate      = 0;
01217
01218   /* Check if the card command class supports erase command */
01219   if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
01220   {
01221     errorstate = SD_REQUEST_NOT_APPLICABLE;
01222
01223     return errorstate;
01224   }
01225
01226   /* Get max delay value */
01227   maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
01228
01229   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
01230   {
01231     errorstate = SD_LOCK_UNLOCK_FAILED;
01232
01233     return errorstate;
01234   }
01235
01236   /* Get start and end block for high capacity cards */
01237   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01238   {
01239     startaddr /= 512;
01240     endaddr   /= 512;
01241   }
01242
01243   /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01244   if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
01245     (hsd->CardType == HIGH_CAPACITY_SD_CARD))
01246   {
01247     /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01248     sdmmc_cmdinitstructure.Argument         =(uint32_t)startaddr;
01249     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
01250     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01251     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01252     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01253     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01254
01255     /* Check for error conditions */
01256     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
01257
01258     if (errorstate != SD_OK)
01259     {
01260       return errorstate;
01261     }
01262
01263     /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01264     sdmmc_cmdinitstructure.Argument         = (uint32_t)endaddr;
01265     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
01266     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01267
01268     /* Check for error conditions */
01269     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
01270
01271     if (errorstate != SD_OK)
01272     {
01273       return errorstate;
01274     }
01275   }
01276
01277   /* Send CMD38 ERASE */
01278   sdmmc_cmdinitstructure.Argument         = 0;
01279   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
01280   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01281
01282   /* Check for error conditions */
01283   errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
01284
01285   if (errorstate != SD_OK)
01286   {
01287     return errorstate;
01288   }
01289
01290   for (; delay < maxdelay; delay++)
01291   {
01292   }
01293
01294   /* Wait until the card is in programming state */
01295   errorstate = SD_IsCardProgramming(hsd, &cardstate);
01296
01297   delay = SD_DATATIMEOUT;
01298
01299   while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
01300   {
01301     errorstate = SD_IsCardProgramming(hsd, &cardstate);
01302     delay--;
01303   }
01304
01305   return errorstate;
01306 }
01307
01308 /**
01309   * @brief  This function handles SD card interrupt request.
01310   * @param  hsd: SD handle
01311   * @retval None
01312   */
01313 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
01314 {
01315   /* Check for SDMMC interrupt flags */
01316   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))
01317   {
01318     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND);
01319
01320     /* SD transfer is complete */
01321     hsd->SdTransferCplt = 1;
01322
01323     /* No transfer error */
01324     hsd->SdTransferErr  = SD_OK;
01325
01326     HAL_SD_XferCpltCallback(hsd);
01327   }
01328   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))
01329   {
01330     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
01331
01332     hsd->SdTransferErr = SD_DATA_CRC_FAIL;
01333
01334     HAL_SD_XferErrorCallback(hsd);
01335
01336   }
01337   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))
01338   {
01339     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
01340
01341     hsd->SdTransferErr = SD_DATA_TIMEOUT;
01342
01343     HAL_SD_XferErrorCallback(hsd);
01344   }
01345   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))
01346   {
01347     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
01348
01349     hsd->SdTransferErr = SD_RX_OVERRUN;
01350
01351     HAL_SD_XferErrorCallback(hsd);
01352   }
01353   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))
01354   {
01355     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
01356
01357     hsd->SdTransferErr = SD_TX_UNDERRUN;
01358
01359     HAL_SD_XferErrorCallback(hsd);
01360   }
01361   else
01362   {
01363     /* No error flag set */
01364   }
01365
01366   /* Disable all SDMMC peripheral interrupt sources */
01367   __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND  |\
01368                                  SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\
01369                                  SDMMC_IT_RXOVERR);
01370 }
01371
01372
01373 /**
01374   * @brief  SD end of transfer callback.
01375   * @param  hsd: SD handle
01376   * @retval None
01377   */
01378 __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
01379 {
01380   /* Prevent unused argument(s) compilation warning */
01381   UNUSED(hsd);
01382
01383   /* NOTE : This function Should not be modified, when the callback is needed,
01384             the HAL_SD_XferCpltCallback could be implemented in the user file
01385    */
01386 }
01387
01388 /**
01389   * @brief  SD Transfer Error callback.
01390   * @param  hsd: SD handle
01391   * @retval None
01392   */
01393 __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
01394 {
01395   /* Prevent unused argument(s) compilation warning */
01396   UNUSED(hsd);
01397
01398   /* NOTE : This function Should not be modified, when the callback is needed,
01399             the HAL_SD_XferErrorCallback could be implemented in the user file
01400    */
01401 }
01402
01403 /**
01404   * @brief  SD Transfer complete Rx callback in non blocking mode.
01405   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01406   *                the configuration information for the specified DMA module.
01407   * @retval None
01408   */
01409 __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
01410 {
01411   /* Prevent unused argument(s) compilation warning */
01412   UNUSED(hdma);
01413
01414   /* NOTE : This function Should not be modified, when the callback is needed,
01415             the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
01416    */
01417 }
01418
01419 /**
01420   * @brief  SD DMA transfer complete Rx error callback.
01421   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01422   *                the configuration information for the specified DMA module.
01423   * @retval None
01424   */
01425 __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
01426 {
01427   /* Prevent unused argument(s) compilation warning */
01428   UNUSED(hdma);
01429
01430   /* NOTE : This function Should not be modified, when the callback is needed,
01431             the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
01432    */
01433 }
01434
01435 /**
01436   * @brief  SD Transfer complete Tx callback in non blocking mode.
01437   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01438   *                the configuration information for the specified DMA module.
01439   * @retval None
01440   */
01441 __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
01442 {
01443   /* Prevent unused argument(s) compilation warning */
01444   UNUSED(hdma);
01445
01446   /* NOTE : This function Should not be modified, when the callback is needed,
01447             the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
01448    */
01449 }
01450
01451 /**
01452   * @brief  SD DMA transfer complete error Tx callback.
01453   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01454   *                the configuration information for the specified DMA module.
01455   * @retval None
01456   */
01457 __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
01458 {
01459   /* Prevent unused argument(s) compilation warning */
01460   UNUSED(hdma);
01461
01462   /* NOTE : This function Should not be modified, when the callback is needed,
01463             the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
01464    */
01465 }
01466
01467 /**
01468   * @}
01469   */
01470
01471 /** @addtogroup SD_Exported_Functions_Group3
01472  *  @brief   management functions
01473  *
01474 @verbatim
01475   ==============================================================================
01476                       ##### Peripheral Control functions #####
01477   ==============================================================================
01478   [..]
01479     This subsection provides a set of functions allowing to control the SD card
01480     operations.
01481
01482 @endverbatim
01483   * @{
01484   */
01485
01486 /**
01487   * @brief  Returns information about specific card.
01488   * @param  hsd: SD handle
01489   * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that
01490   *         contains all SD cardinformation
01491   * @retval SD Card error state
01492   */
01493 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
01494 {
01495   HAL_SD_ErrorTypedef errorstate = SD_OK;
01496   uint32_t tmp = 0;
01497
01498   pCardInfo->CardType = (uint8_t)(hsd->CardType);
01499   pCardInfo->RCA      = (uint16_t)(hsd->RCA);
01500
01501   /* Byte 0 */
01502   tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
01503   pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
01504   pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
01505   pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
01506
01507   /* Byte 1 */
01508   tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
01509   pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
01510
01511   /* Byte 2 */
01512   tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
01513   pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
01514
01515   /* Byte 3 */
01516   tmp = hsd->CSD[0] & 0x000000FF;
01517   pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
01518
01519   /* Byte 4 */
01520   tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
01521   pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
01522
01523   /* Byte 5 */
01524   tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
01525   pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
01526   pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
01527
01528   /* Byte 6 */
01529   tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
01530   pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
01531   pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
01532   pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
01533   pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
01534   pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
01535
01536   if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
01537   {
01538     pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
01539
01540     /* Byte 7 */
01541     tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
01542     pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
01543
01544     /* Byte 8 */
01545     tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
01546     pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
01547
01548     pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
01549     pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
01550
01551     /* Byte 9 */
01552     tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
01553     pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
01554     pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
01555     pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
01556     /* Byte 10 */
01557     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
01558     pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
01559
01560     pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
01561     pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
01562     pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
01563     pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
01564   }
01565   else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01566   {
01567     /* Byte 7 */
01568     tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
01569     pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
01570
01571     /* Byte 8 */
01572     tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
01573
01574     pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
01575
01576     /* Byte 9 */
01577     tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
01578
01579     pCardInfo->SD_csd.DeviceSize |= (tmp);
01580
01581     /* Byte 10 */
01582     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
01583
01584     pCardInfo->CardCapacity  = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
01585     pCardInfo->CardBlockSize = 512;
01586   }
01587   else
01588   {
01589     /* Not supported card type */
01590     errorstate = SD_ERROR;
01591   }
01592
01593   pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
01594   pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
01595
01596   /* Byte 11 */
01597   tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
01598   pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
01599   pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
01600
01601   /* Byte 12 */
01602   tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
01603   pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
01604   pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
01605   pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
01606   pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
01607
01608   /* Byte 13 */
01609   tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
01610   pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
01611   pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
01612   pCardInfo->SD_csd.Reserved3           = 0;
01613   pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
01614
01615   /* Byte 14 */
01616   tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
01617   pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
01618   pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
01619   pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
01620   pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
01621   pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
01622   pCardInfo->SD_csd.ECC              = (tmp & 0x03);
01623
01624   /* Byte 15 */
01625   tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
01626   pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
01627   pCardInfo->SD_csd.Reserved4 = 1;
01628
01629   /* Byte 0 */
01630   tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
01631   pCardInfo->SD_cid.ManufacturerID = tmp;
01632
01633   /* Byte 1 */
01634   tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
01635   pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
01636
01637   /* Byte 2 */
01638   tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
01639   pCardInfo->SD_cid.OEM_AppliID |= tmp;
01640
01641   /* Byte 3 */
01642   tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
01643   pCardInfo->SD_cid.ProdName1 = tmp << 24;
01644
01645   /* Byte 4 */
01646   tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
01647   pCardInfo->SD_cid.ProdName1 |= tmp << 16;
01648
01649   /* Byte 5 */
01650   tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
01651   pCardInfo->SD_cid.ProdName1 |= tmp << 8;
01652
01653   /* Byte 6 */
01654   tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
01655   pCardInfo->SD_cid.ProdName1 |= tmp;
01656
01657   /* Byte 7 */
01658   tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
01659   pCardInfo->SD_cid.ProdName2 = tmp;
01660
01661   /* Byte 8 */
01662   tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
01663   pCardInfo->SD_cid.ProdRev = tmp;
01664
01665   /* Byte 9 */
01666   tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
01667   pCardInfo->SD_cid.ProdSN = tmp << 24;
01668
01669   /* Byte 10 */
01670   tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
01671   pCardInfo->SD_cid.ProdSN |= tmp << 16;
01672
01673   /* Byte 11 */
01674   tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
01675   pCardInfo->SD_cid.ProdSN |= tmp << 8;
01676
01677   /* Byte 12 */
01678   tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
01679   pCardInfo->SD_cid.ProdSN |= tmp;
01680
01681   /* Byte 13 */
01682   tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
01683   pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
01684   pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
01685
01686   /* Byte 14 */
01687   tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
01688   pCardInfo->SD_cid.ManufactDate |= tmp;
01689
01690   /* Byte 15 */
01691   tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
01692   pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
01693   pCardInfo->SD_cid.Reserved2 = 1;
01694
01695   return errorstate;
01696 }
01697
01698 /**
01699   * @brief  Enables wide bus operation for the requested card if supported by
01700   *         card.
01701   * @param  hsd: SD handle
01702   * @param  WideMode: Specifies the SD card wide bus mode
01703   *          This parameter can be one of the following values:
01704   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
01705   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
01706   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
01707   * @retval SD Card error state
01708   */
01709 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
01710 {
01711   HAL_SD_ErrorTypedef errorstate = SD_OK;
01712   SDMMC_InitTypeDef tmpinit;
01713
01714   /* MMC Card does not support this feature */
01715   if (hsd->CardType == MULTIMEDIA_CARD)
01716   {
01717     errorstate = SD_UNSUPPORTED_FEATURE;
01718
01719     return errorstate;
01720   }
01721   else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
01722     (hsd->CardType == HIGH_CAPACITY_SD_CARD))
01723   {
01724     if (WideMode == SDMMC_BUS_WIDE_8B)
01725     {
01726       errorstate = SD_UNSUPPORTED_FEATURE;
01727     }
01728     else if (WideMode == SDMMC_BUS_WIDE_4B)
01729     {
01730       errorstate = SD_WideBus_Enable(hsd);
01731     }
01732     else if (WideMode == SDMMC_BUS_WIDE_1B)
01733     {
01734       errorstate = SD_WideBus_Disable(hsd);
01735     }
01736     else
01737     {
01738       /* WideMode is not a valid argument*/
01739       errorstate = SD_INVALID_PARAMETER;
01740     }
01741
01742     if (errorstate == SD_OK)
01743     {
01744       /* Configure the SDMMC peripheral */
01745       tmpinit.ClockEdge           = hsd->Init.ClockEdge;
01746       tmpinit.ClockBypass         = hsd->Init.ClockBypass;
01747       tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
01748       tmpinit.BusWide             = WideMode;
01749       tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
01750       tmpinit.ClockDiv            = hsd->Init.ClockDiv;
01751       SDMMC_Init(hsd->Instance, tmpinit);
01752     }
01753   }
01754
01755   return errorstate;
01756 }
01757
01758 /**
01759   * @brief  Aborts an ongoing data transfer.
01760   * @param  hsd: SD handle
01761   * @retval SD Card error state
01762   */
01763 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
01764 {
01765   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
01766   HAL_SD_ErrorTypedef errorstate = SD_OK;
01767
01768   /* Send CMD12 STOP_TRANSMISSION  */
01769   sdmmc_cmdinitstructure.Argument         = 0;
01770   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
01771   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01772   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01773   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01774   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01775
01776   /* Check for error conditions */
01777   errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
01778
01779   return errorstate;
01780 }
01781
01782 /**
01783   * @brief  Switches the SD card to High Speed mode.
01784   *         This API must be used after "Transfer State"
01785   * @note   This operation should be followed by the configuration
01786   *         of PLL to have SDMMCCK clock between 67 and 75 MHz
01787   * @param  hsd: SD handle
01788   * @retval SD Card error state
01789   */
01790 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
01791 {
01792   HAL_SD_ErrorTypedef errorstate = SD_OK;
01793   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
01794   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
01795
01796   uint8_t SD_hs[64]  = {0};
01797   uint32_t SD_scr[2] = {0, 0};
01798   uint32_t SD_SPEC   = 0 ;
01799   uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
01800
01801   /* Initialize the Data control register */
01802   hsd->Instance->DCTRL = 0;
01803
01804   /* Get SCR Register */
01805   errorstate = SD_FindSCR(hsd, SD_scr);
01806
01807   if (errorstate != SD_OK)
01808   {
01809     return errorstate;
01810   }
01811
01812   /* Test the Version supported by the card*/
01813   SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
01814
01815   if (SD_SPEC != SD_ALLZERO)
01816   {
01817     /* Set Block Size for Card */
01818     sdmmc_cmdinitstructure.Argument         = (uint32_t)64;
01819     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01820     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01821     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01822     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01823     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01824
01825     /* Check for error conditions */
01826     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01827
01828     if (errorstate != SD_OK)
01829     {
01830       return errorstate;
01831     }
01832
01833     /* Configure the SD DPSM (Data Path State Machine) */
01834     sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01835     sdmmc_datainitstructure.DataLength    = 64;
01836     sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
01837     sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01838     sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01839     sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
01840     SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
01841
01842     /* Send CMD6 switch mode */
01843     sdmmc_cmdinitstructure.Argument         = 0x80FFFF01;
01844     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
01845     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01846
01847     /* Check for error conditions */
01848     errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
01849
01850     if (errorstate != SD_OK)
01851     {
01852       return errorstate;
01853     }
01854
01855     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
01856     {
01857       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
01858       {
01859         for (count = 0; count < 8; count++)
01860         {
01861           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
01862         }
01863
01864         tempbuff += 8;
01865       }
01866     }
01867
01868     if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
01869     {
01870       __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
01871
01872       errorstate = SD_DATA_TIMEOUT;
01873
01874       return errorstate;
01875     }
01876     else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
01877     {
01878       __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
01879
01880       errorstate = SD_DATA_CRC_FAIL;
01881
01882       return errorstate;
01883     }
01884     else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
01885     {
01886       __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
01887
01888       errorstate = SD_RX_OVERRUN;
01889
01890       return errorstate;
01891     }
01892     else
01893     {
01894       /* No error flag set */
01895     }
01896
01897     count = SD_DATATIMEOUT;
01898
01899     while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
01900     {
01901       *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
01902       tempbuff++;
01903       count--;
01904     }
01905
01906     /* Clear all the static flags */
01907     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01908
01909     /* Test if the switch mode HS is ok */
01910     if ((SD_hs[13]& 2) != 2)
01911     {
01912       errorstate = SD_UNSUPPORTED_FEATURE;
01913     }
01914   }
01915
01916   return errorstate;
01917 }
01918
01919 /**
01920   * @}
01921   */
01922
01923 /** @addtogroup SD_Exported_Functions_Group4
01924  *  @brief   Peripheral State functions
01925  *
01926 @verbatim
01927   ==============================================================================
01928                       ##### Peripheral State functions #####
01929   ==============================================================================
01930   [..]
01931     This subsection permits to get in runtime the status of the peripheral
01932     and the data flow.
01933
01934 @endverbatim
01935   * @{
01936   */
01937
01938 /**
01939   * @brief  Returns the current SD card's status.
01940   * @param  hsd: SD handle
01941   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
01942   *         SD Status register)
01943   * @retval SD Card error state
01944   */
01945 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
01946 {
01947   SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
01948   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
01949   HAL_SD_ErrorTypedef errorstate = SD_OK;
01950   uint32_t count = 0;
01951
01952   /* Check SD response */
01953   if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
01954   {
01955     errorstate = SD_LOCK_UNLOCK_FAILED;
01956
01957     return errorstate;
01958   }
01959
01960   /* Set block size for card if it is not equal to current block size for card */
01961   sdmmc_cmdinitstructure.Argument         = 64;
01962   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01963   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01964   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01965   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01966   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01967
01968   /* Check for error conditions */
01969   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01970
01971   if (errorstate != SD_OK)
01972   {
01973     return errorstate;
01974   }
01975
01976   /* Send CMD55 */
01977   sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
01978   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
01979   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01980
01981   /* Check for error conditions */
01982   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
01983
01984   if (errorstate != SD_OK)
01985   {
01986     return errorstate;
01987   }
01988
01989   /* Configure the SD DPSM (Data Path State Machine) */
01990   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01991   sdmmc_datainitstructure.DataLength    = 64;
01992   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
01993   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01994   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01995   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
01996   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
01997
01998   /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
01999   sdmmc_cmdinitstructure.Argument         = 0;
02000   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
02001   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02002
02003   /* Check for error conditions */
02004   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
02005
02006   if (errorstate != SD_OK)
02007   {
02008     return errorstate;
02009   }
02010
02011   /* Get status data */
02012   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
02013   {
02014     if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
02015     {
02016       for (count = 0; count < 8; count++)
02017       {
02018         *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
02019       }
02020
02021       pSDstatus += 8;
02022     }
02023   }
02024
02025   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
02026   {
02027     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
02028
02029     errorstate = SD_DATA_TIMEOUT;
02030
02031     return errorstate;
02032   }
02033   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
02034   {
02035     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
02036
02037     errorstate = SD_DATA_CRC_FAIL;
02038
02039     return errorstate;
02040   }
02041   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
02042   {
02043     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
02044
02045     errorstate = SD_RX_OVERRUN;
02046
02047     return errorstate;
02048   }
02049   else
02050   {
02051     /* No error flag set */
02052   }
02053
02054   count = SD_DATATIMEOUT;
02055   while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
02056   {
02057     *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
02058     pSDstatus++;
02059     count--;
02060   }
02061
02062   /* Clear all the static status flags*/
02063   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02064
02065   return errorstate;
02066 }
02067
02068 /**
02069   * @brief  Gets the current sd card data status.
02070   * @param  hsd: SD handle
02071   * @retval Data Transfer state
02072   */
02073 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
02074 {
02075   HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
02076
02077   /* Get SD card state */
02078   cardstate = SD_GetState(hsd);
02079
02080   /* Find SD status according to card state*/
02081   if (cardstate == SD_CARD_TRANSFER)
02082   {
02083     return SD_TRANSFER_OK;
02084   }
02085   else if(cardstate == SD_CARD_ERROR)
02086   {
02087     return SD_TRANSFER_ERROR;
02088   }
02089   else
02090   {
02091     return SD_TRANSFER_BUSY;
02092   }
02093 }
02094
02095 /**
02096   * @brief  Gets the SD card status.
02097   * @param  hsd: SD handle
02098   * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
02099   *         will contain the SD card status information
02100   * @retval SD Card error state
02101   */
02102 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
02103 {
02104   HAL_SD_ErrorTypedef errorstate = SD_OK;
02105   uint32_t tmp = 0;
02106   uint32_t sd_status[16];
02107
02108   errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
02109
02110   if (errorstate  != SD_OK)
02111   {
02112     return errorstate;
02113   }
02114
02115   /* Byte 0 */
02116   tmp = (sd_status[0] & 0xC0) >> 6;
02117   pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
02118
02119   /* Byte 0 */
02120   tmp = (sd_status[0] & 0x20) >> 5;
02121   pCardStatus->SECURED_MODE = (uint8_t)tmp;
02122
02123   /* Byte 2 */
02124   tmp = (sd_status[2] & 0xFF);
02125   pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
02126
02127   /* Byte 3 */
02128   tmp = (sd_status[3] & 0xFF);
02129   pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
02130
02131   /* Byte 4 */
02132   tmp = (sd_status[4] & 0xFF);
02133   pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
02134
02135   /* Byte 5 */
02136   tmp = (sd_status[5] & 0xFF);
02137   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
02138
02139   /* Byte 6 */
02140   tmp = (sd_status[6] & 0xFF);
02141   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
02142
02143   /* Byte 7 */
02144   tmp = (sd_status[7] & 0xFF);
02145   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
02146
02147   /* Byte 8 */
02148   tmp = (sd_status[8] & 0xFF);
02149   pCardStatus->SPEED_CLASS = (uint8_t)tmp;
02150
02151   /* Byte 9 */
02152   tmp = (sd_status[9] & 0xFF);
02153   pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
02154
02155   /* Byte 10 */
02156   tmp = (sd_status[10] & 0xF0) >> 4;
02157   pCardStatus->AU_SIZE = (uint8_t)tmp;
02158
02159   /* Byte 11 */
02160   tmp = (sd_status[11] & 0xFF);
02161   pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
02162
02163   /* Byte 12 */
02164   tmp = (sd_status[12] & 0xFF);
02165   pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
02166
02167   /* Byte 13 */
02168   tmp = (sd_status[13] & 0xFC) >> 2;
02169   pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
02170
02171   /* Byte 13 */
02172   tmp = (sd_status[13] & 0x3);
02173   pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
02174
02175   return errorstate;
02176 }
02177
02178 /**
02179   * @}
02180   */
02181
02182 /**
02183   * @}
02184   */
02185
02186 /* Private function ----------------------------------------------------------*/
02187 /** @addtogroup SD_Private_Functions
02188   * @{
02189   */
02190
02191 /**
02192   * @brief  SD DMA transfer complete Rx callback.
02193   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02194   *                the configuration information for the specified DMA module.
02195   * @retval None
02196   */
02197 static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
02198 {
02199   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02200
02201   /* DMA transfer is complete */
02202   hsd->DmaTransferCplt = 1;
02203
02204   /* Wait until SD transfer is complete */
02205   while(hsd->SdTransferCplt == 0)
02206   {
02207   }
02208
02209   /* Disable the DMA channel */
02210   HAL_DMA_Abort(hdma);
02211
02212   /* Transfer complete user callback */
02213   HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
02214 }
02215
02216 /**
02217   * @brief  SD DMA transfer Error Rx callback.
02218   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02219   *                the configuration information for the specified DMA module.
02220   * @retval None
02221   */
02222 static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
02223 {
02224   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02225
02226   /* Transfer complete user callback */
02227   HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
02228 }
02229
02230 /**
02231   * @brief  SD DMA transfer complete Tx callback.
02232   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02233   *                the configuration information for the specified DMA module.
02234   * @retval None
02235   */
02236 static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
02237 {
02238   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02239
02240   /* DMA transfer is complete */
02241   hsd->DmaTransferCplt = 1;
02242
02243   /* Wait until SD transfer is complete */
02244   while(hsd->SdTransferCplt == 0)
02245   {
02246   }
02247
02248   /* Disable the DMA channel */
02249   HAL_DMA_Abort(hdma);
02250
02251   /* Transfer complete user callback */
02252   HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
02253 }
02254
02255 /**
02256   * @brief  SD DMA transfer Error Tx callback.
02257   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02258   *                the configuration information for the specified DMA module.
02259   * @retval None
02260   */
02261 static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
02262 {
02263   SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02264
02265   /* Transfer complete user callback */
02266   HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
02267 }
02268
02269 /**
02270   * @brief  Returns the SD current state.
02271   * @param  hsd: SD handle
02272   * @retval SD card current state
02273   */
02274 static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
02275 {
02276   uint32_t resp1 = 0;
02277
02278   if (SD_SendStatus(hsd, &resp1) != SD_OK)
02279   {
02280     return SD_CARD_ERROR;
02281   }
02282   else
02283   {
02284     return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
02285   }
02286 }
02287
02288 /**
02289   * @brief  Initializes all cards or single card as the case may be Card(s) come
02290   *         into standby state.
02291   * @param  hsd: SD handle
02292   * @retval SD Card error state
02293   */
02294 static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
02295 {
02296   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02297   HAL_SD_ErrorTypedef errorstate = SD_OK;
02298   uint16_t sd_rca = 1;
02299
02300   if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */
02301   {
02302     errorstate = SD_REQUEST_NOT_APPLICABLE;
02303
02304     return errorstate;
02305   }
02306
02307   if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
02308   {
02309     /* Send CMD2 ALL_SEND_CID */
02310     sdmmc_cmdinitstructure.Argument         = 0;
02311     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
02312     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
02313     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02314     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02315     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02316
02317     /* Check for error conditions */
02318     errorstate = SD_CmdResp2Error(hsd);
02319
02320     if(errorstate != SD_OK)
02321     {
02322       return errorstate;
02323     }
02324
02325     /* Get Card identification number data */
02326     hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02327     hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02328     hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02329     hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02330   }
02331
02332   if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
02333      (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
02334   {
02335     /* Send CMD3 SET_REL_ADDR with argument 0 */
02336     /* SD Card publishes its RCA. */
02337     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
02338     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02339     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02340
02341     /* Check for error conditions */
02342     errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
02343
02344     if(errorstate != SD_OK)
02345     {
02346       return errorstate;
02347     }
02348   }
02349
02350   if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
02351   {
02352     /* Get the SD card RCA */
02353     hsd->RCA = sd_rca;
02354
02355     /* Send CMD9 SEND_CSD with argument as card's RCA */
02356     sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
02357     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
02358     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
02359     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02360
02361     /* Check for error conditions */
02362     errorstate = SD_CmdResp2Error(hsd);
02363
02364     if(errorstate != SD_OK)
02365     {
02366       return errorstate;
02367     }
02368
02369     /* Get Card Specific Data */
02370     hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02371     hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02372     hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02373     hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02374   }
02375
02376   /* All cards are initialized */
02377   return errorstate;
02378 }
02379
02380 /**
02381   * @brief  Selects od Deselects the corresponding card.
02382   * @param  hsd: SD handle
02383   * @param  addr: Address of the card to be selected
02384   * @retval SD Card error state
02385   */
02386 static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
02387 {
02388   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02389   HAL_SD_ErrorTypedef errorstate = SD_OK;
02390
02391   /* Send CMD7 SDMMC_SEL_DESEL_CARD */
02392   sdmmc_cmdinitstructure.Argument         = (uint32_t)addr;
02393   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
02394   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02395   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02396   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02397   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02398
02399   /* Check for error conditions */
02400   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
02401
02402   return errorstate;
02403 }
02404
02405 /**
02406   * @brief  Enquires cards about their operating voltage and configures clock
02407   *         controls and stores SD information that will be needed in future
02408   *         in the SD handle.
02409   * @param  hsd: SD handle
02410   * @retval SD Card error state
02411   */
02412 static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
02413 {
02414   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02415   __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
02416   uint32_t response = 0, count = 0, validvoltage = 0;
02417   uint32_t sdtype = SD_STD_CAPACITY;
02418
02419   /* Power ON Sequence -------------------------------------------------------*/
02420   /* Disable SDMMC Clock */
02421   __HAL_SD_SDMMC_DISABLE(hsd);
02422
02423   /* Set Power State to ON */
02424   SDMMC_PowerState_ON(hsd->Instance);
02425
02426   /* 1ms: required power up waiting time before starting the SD initialization
02427      sequence */
02428   HAL_Delay(1);
02429
02430   /* Enable SDMMC Clock */
02431   __HAL_SD_SDMMC_ENABLE(hsd);
02432
02433   /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
02434   /* No CMD response required */
02435   sdmmc_cmdinitstructure.Argument         = 0;
02436   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
02437   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_NO;
02438   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02439   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02440   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02441
02442   /* Check for error conditions */
02443   errorstate = SD_CmdError(hsd);
02444
02445   if(errorstate != SD_OK)
02446   {
02447     /* CMD Response Timeout (wait for CMDSENT flag) */
02448     return errorstate;
02449   }
02450
02451   /* CMD8: SEND_IF_COND ------------------------------------------------------*/
02452   /* Send CMD8 to verify SD card interface operating condition */
02453   /* Argument: - [31:12]: Reserved (shall be set to '0')
02454   - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
02455   - [7:0]: Check Pattern (recommended 0xAA) */
02456   /* CMD Response: R7 */
02457   sdmmc_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
02458   sdmmc_cmdinitstructure.CmdIndex         = SD_SDMMC_SEND_IF_COND;
02459   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02460   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02461
02462   /* Check for error conditions */
02463   errorstate = SD_CmdResp7Error(hsd);
02464
02465   if (errorstate == SD_OK)
02466   {
02467     /* SD Card 2.0 */
02468     hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
02469     sdtype        = SD_HIGH_CAPACITY;
02470   }
02471
02472   /* Send CMD55 */
02473   sdmmc_cmdinitstructure.Argument         = 0;
02474   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02475   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02476
02477   /* Check for error conditions */
02478   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02479
02480   /* If errorstate is Command Timeout, it is a MMC card */
02481   /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
02482      or SD card 1.x */
02483   if(errorstate == SD_OK)
02484   {
02485     /* SD CARD */
02486     /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
02487     while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
02488     {
02489
02490       /* SEND CMD55 APP_CMD with RCA as 0 */
02491       sdmmc_cmdinitstructure.Argument         = 0;
02492       sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02493       sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02494       sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02495       sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02496       SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02497
02498       /* Check for error conditions */
02499       errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02500
02501       if(errorstate != SD_OK)
02502       {
02503         return errorstate;
02504       }
02505
02506       /* Send CMD41 */
02507       sdmmc_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
02508       sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
02509       sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02510       sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02511       sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02512       SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02513
02514       /* Check for error conditions */
02515       errorstate = SD_CmdResp3Error(hsd);
02516
02517       if(errorstate != SD_OK)
02518       {
02519         return errorstate;
02520       }
02521
02522       /* Get command response */
02523       response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02524
02525       /* Get operating voltage*/
02526       validvoltage = (((response >> 31) == 1) ? 1 : 0);
02527
02528       count++;
02529     }
02530
02531     if(count >= SD_MAX_VOLT_TRIAL)
02532     {
02533       errorstate = SD_INVALID_VOLTRANGE;
02534
02535       return errorstate;
02536     }
02537
02538     if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
02539     {
02540       hsd->CardType = HIGH_CAPACITY_SD_CARD;
02541     }
02542
02543   } /* else MMC Card */
02544
02545   return errorstate;
02546 }
02547
02548 /**
02549   * @brief  Turns the SDMMC output signals off.
02550   * @param  hsd: SD handle
02551   * @retval SD Card error state
02552   */
02553 static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
02554 {
02555   HAL_SD_ErrorTypedef errorstate = SD_OK;
02556
02557   /* Set Power State to OFF */
02558   SDMMC_PowerState_OFF(hsd->Instance);
02559
02560   return errorstate;
02561 }
02562
02563 /**
02564   * @brief  Returns the current card's status.
02565   * @param  hsd: SD handle
02566   * @param  pCardStatus: pointer to the buffer that will contain the SD card
02567   *         status (Card Status register)
02568   * @retval SD Card error state
02569   */
02570 static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
02571 {
02572   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02573   HAL_SD_ErrorTypedef errorstate = SD_OK;
02574
02575   if(pCardStatus == NULL)
02576   {
02577     errorstate = SD_INVALID_PARAMETER;
02578
02579     return errorstate;
02580   }
02581
02582   /* Send Status command */
02583   sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
02584   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
02585   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02586   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02587   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02588   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02589
02590   /* Check for error conditions */
02591   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
02592
02593   if(errorstate != SD_OK)
02594   {
02595     return errorstate;
02596   }
02597
02598   /* Get SD card status */
02599   *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02600
02601   return errorstate;
02602 }
02603
02604 /**
02605   * @brief  Checks for error conditions for CMD0.
02606   * @param  hsd: SD handle
02607   * @retval SD Card error state
02608   */
02609 static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
02610 {
02611   HAL_SD_ErrorTypedef errorstate = SD_OK;
02612   uint32_t timeout, tmp;
02613
02614   timeout = SDMMC_CMD0TIMEOUT;
02615
02616   tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
02617
02618   while((timeout > 0) && (!tmp))
02619   {
02620     tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
02621     timeout--;
02622   }
02623
02624   if(timeout == 0)
02625   {
02626     errorstate = SD_CMD_RSP_TIMEOUT;
02627     return errorstate;
02628   }
02629
02630   /* Clear all the static flags */
02631   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02632
02633   return errorstate;
02634 }
02635
02636 /**
02637   * @brief  Checks for error conditions for R7 response.
02638   * @param  hsd: SD handle
02639   * @retval SD Card error state
02640   */
02641 static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
02642 {
02643   HAL_SD_ErrorTypedef errorstate = SD_ERROR;
02644   uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;
02645
02646   tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
02647
02648   while((!tmp) && (timeout > 0))
02649   {
02650     tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
02651     timeout--;
02652   }
02653
02654   tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02655
02656   if((timeout == 0) || tmp)
02657   {
02658     /* Card is not V2.0 compliant or card does not support the set voltage range */
02659     errorstate = SD_CMD_RSP_TIMEOUT;
02660
02661     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02662
02663     return errorstate;
02664   }
02665
02666   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))
02667   {
02668     /* Card is SD V2.0 compliant */
02669     errorstate = SD_OK;
02670
02671     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);
02672
02673     return errorstate;
02674   }
02675
02676   return errorstate;
02677 }
02678
02679 /**
02680   * @brief  Checks for error conditions for R1 response.
02681   * @param  hsd: SD handle
02682   * @param  SD_CMD: The sent command index
02683   * @retval SD Card error state
02684   */
02685 static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
02686 {
02687   HAL_SD_ErrorTypedef errorstate = SD_OK;
02688   uint32_t response_r1;
02689
02690   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02691   {
02692   }
02693
02694   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02695   {
02696     errorstate = SD_CMD_RSP_TIMEOUT;
02697
02698     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02699
02700     return errorstate;
02701   }
02702   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
02703   {
02704     errorstate = SD_CMD_CRC_FAIL;
02705
02706     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
02707
02708     return errorstate;
02709   }
02710
02711   /* Check response received is of desired command */
02712   if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
02713   {
02714     errorstate = SD_ILLEGAL_CMD;
02715
02716     return errorstate;
02717   }
02718
02719   /* Clear all the static flags */
02720   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02721
02722   /* We have received response, retrieve it for analysis  */
02723   response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02724
02725   if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
02726   {
02727     return errorstate;
02728   }
02729
02730   if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
02731   {
02732     return(SD_ADDR_OUT_OF_RANGE);
02733   }
02734
02735   if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
02736   {
02737     return(SD_ADDR_MISALIGNED);
02738   }
02739
02740   if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
02741   {
02742     return(SD_BLOCK_LEN_ERR);
02743   }
02744
02745   if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
02746   {
02747     return(SD_ERASE_SEQ_ERR);
02748   }
02749
02750   if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
02751   {
02752     return(SD_BAD_ERASE_PARAM);
02753   }
02754
02755   if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
02756   {
02757     return(SD_WRITE_PROT_VIOLATION);
02758   }
02759
02760   if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
02761   {
02762     return(SD_LOCK_UNLOCK_FAILED);
02763   }
02764
02765   if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
02766   {
02767     return(SD_COM_CRC_FAILED);
02768   }
02769
02770   if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
02771   {
02772     return(SD_ILLEGAL_CMD);
02773   }
02774
02775   if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
02776   {
02777     return(SD_CARD_ECC_FAILED);
02778   }
02779
02780   if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
02781   {
02782     return(SD_CC_ERROR);
02783   }
02784
02785   if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
02786   {
02787     return(SD_GENERAL_UNKNOWN_ERROR);
02788   }
02789
02790   if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
02791   {
02792     return(SD_STREAM_READ_UNDERRUN);
02793   }
02794
02795   if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
02796   {
02797     return(SD_STREAM_WRITE_OVERRUN);
02798   }
02799
02800   if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
02801   {
02802     return(SD_CID_CSD_OVERWRITE);
02803   }
02804
02805   if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
02806   {
02807     return(SD_WP_ERASE_SKIP);
02808   }
02809
02810   if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
02811   {
02812     return(SD_CARD_ECC_DISABLED);
02813   }
02814
02815   if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
02816   {
02817     return(SD_ERASE_RESET);
02818   }
02819
02820   if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
02821   {
02822     return(SD_AKE_SEQ_ERROR);
02823   }
02824
02825   return errorstate;
02826 }
02827
02828 /**
02829   * @brief  Checks for error conditions for R3 (OCR) response.
02830   * @param  hsd: SD handle
02831   * @retval SD Card error state
02832   */
02833 static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
02834 {
02835   HAL_SD_ErrorTypedef errorstate = SD_OK;
02836
02837   while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02838   {
02839   }
02840
02841   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02842   {
02843     errorstate = SD_CMD_RSP_TIMEOUT;
02844
02845     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02846
02847     return errorstate;
02848   }
02849
02850   /* Clear all the static flags */
02851   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02852
02853   return errorstate;
02854 }
02855
02856 /**
02857   * @brief  Checks for error conditions for R2 (CID or CSD) response.
02858   * @param  hsd: SD handle
02859   * @retval SD Card error state
02860   */
02861 static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
02862 {
02863   HAL_SD_ErrorTypedef errorstate = SD_OK;
02864
02865   while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02866   {
02867   }
02868
02869   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02870   {
02871     errorstate = SD_CMD_RSP_TIMEOUT;
02872
02873     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02874
02875     return errorstate;
02876   }
02877   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
02878   {
02879     errorstate = SD_CMD_CRC_FAIL;
02880
02881     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
02882
02883     return errorstate;
02884   }
02885   else
02886   {
02887     /* No error flag set */
02888   }
02889
02890   /* Clear all the static flags */
02891   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02892
02893   return errorstate;
02894 }
02895
02896 /**
02897   * @brief  Checks for error conditions for R6 (RCA) response.
02898   * @param  hsd: SD handle
02899   * @param  SD_CMD: The sent command index
02900   * @param  pRCA: Pointer to the variable that will contain the SD card relative
02901   *         address RCA
02902   * @retval SD Card error state
02903   */
02904 static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
02905 {
02906   HAL_SD_ErrorTypedef errorstate = SD_OK;
02907   uint32_t response_r1;
02908
02909   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02910   {
02911   }
02912
02913   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02914   {
02915     errorstate = SD_CMD_RSP_TIMEOUT;
02916
02917     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02918
02919     return errorstate;
02920   }
02921   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
02922   {
02923     errorstate = SD_CMD_CRC_FAIL;
02924
02925     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
02926
02927     return errorstate;
02928   }
02929   else
02930   {
02931     /* No error flag set */
02932   }
02933
02934   /* Check response received is of desired command */
02935   if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
02936   {
02937     errorstate = SD_ILLEGAL_CMD;
02938
02939     return errorstate;
02940   }
02941
02942   /* Clear all the static flags */
02943   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02944
02945   /* We have received response, retrieve it.  */
02946   response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02947
02948   if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
02949   {
02950     *pRCA = (uint16_t) (response_r1 >> 16);
02951
02952     return errorstate;
02953   }
02954
02955   if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
02956   {
02957     return(SD_GENERAL_UNKNOWN_ERROR);
02958   }
02959
02960   if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
02961   {
02962     return(SD_ILLEGAL_CMD);
02963   }
02964
02965   if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
02966   {
02967     return(SD_COM_CRC_FAILED);
02968   }
02969
02970   return errorstate;
02971 }
02972
02973 /**
02974   * @brief  Enables the SDMMC wide bus mode.
02975   * @param  hsd: SD handle
02976   * @retval SD Card error state
02977   */
02978 static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
02979 {
02980   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02981   HAL_SD_ErrorTypedef errorstate = SD_OK;
02982
02983   uint32_t scr[2] = {0, 0};
02984
02985   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
02986   {
02987     errorstate = SD_LOCK_UNLOCK_FAILED;
02988
02989     return errorstate;
02990   }
02991
02992   /* Get SCR Register */
02993   errorstate = SD_FindSCR(hsd, scr);
02994
02995   if(errorstate != SD_OK)
02996   {
02997     return errorstate;
02998   }
02999
03000   /* If requested card supports wide bus operation */
03001   if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
03002   {
03003     /* Send CMD55 APP_CMD with argument as card's RCA.*/
03004     sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
03005     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03006     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03007     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03008     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03009     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03010
03011     /* Check for error conditions */
03012     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03013
03014     if(errorstate != SD_OK)
03015     {
03016       return errorstate;
03017     }
03018
03019     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
03020     sdmmc_cmdinitstructure.Argument         = 2;
03021     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
03022     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03023
03024     /* Check for error conditions */
03025     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
03026
03027     if(errorstate != SD_OK)
03028     {
03029       return errorstate;
03030     }
03031
03032     return errorstate;
03033   }
03034   else
03035   {
03036     errorstate = SD_REQUEST_NOT_APPLICABLE;
03037
03038     return errorstate;
03039   }
03040 }
03041
03042 /**
03043   * @brief  Disables the SDMMC wide bus mode.
03044   * @param  hsd: SD handle
03045   * @retval SD Card error state
03046   */
03047 static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
03048 {
03049   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
03050   HAL_SD_ErrorTypedef errorstate = SD_OK;
03051
03052   uint32_t scr[2] = {0, 0};
03053
03054   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
03055   {
03056     errorstate = SD_LOCK_UNLOCK_FAILED;
03057
03058     return errorstate;
03059   }
03060
03061   /* Get SCR Register */
03062   errorstate = SD_FindSCR(hsd, scr);
03063
03064   if(errorstate != SD_OK)
03065   {
03066     return errorstate;
03067   }
03068
03069   /* If requested card supports 1 bit mode operation */
03070   if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
03071   {
03072     /* Send CMD55 APP_CMD with argument as card's RCA */
03073     sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
03074     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03075     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03076     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03077     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03078     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03079
03080     /* Check for error conditions */
03081     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03082
03083     if(errorstate != SD_OK)
03084     {
03085       return errorstate;
03086     }
03087
03088     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
03089     sdmmc_cmdinitstructure.Argument         = 0;
03090     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
03091     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03092
03093     /* Check for error conditions */
03094     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
03095
03096     if(errorstate != SD_OK)
03097     {
03098       return errorstate;
03099     }
03100
03101     return errorstate;
03102   }
03103   else
03104   {
03105     errorstate = SD_REQUEST_NOT_APPLICABLE;
03106
03107     return errorstate;
03108   }
03109 }
03110
03111
03112 /**
03113   * @brief  Finds the SD card SCR register value.
03114   * @param  hsd: SD handle
03115   * @param  pSCR: pointer to the buffer that will contain the SCR value
03116   * @retval SD Card error state
03117   */
03118 static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
03119 {
03120   SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
03121   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
03122   HAL_SD_ErrorTypedef errorstate = SD_OK;
03123   uint32_t index = 0;
03124   uint32_t tempscr[2] = {0, 0};
03125
03126   /* Set Block Size To 8 Bytes */
03127   /* Send CMD55 APP_CMD with argument as card's RCA */
03128   sdmmc_cmdinitstructure.Argument         = (uint32_t)8;
03129   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
03130   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03131   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03132   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03133   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03134
03135   /* Check for error conditions */
03136   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
03137
03138   if(errorstate != SD_OK)
03139   {
03140     return errorstate;
03141   }
03142
03143   /* Send CMD55 APP_CMD with argument as card's RCA */
03144   sdmmc_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);
03145   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03146   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03147
03148   /* Check for error conditions */
03149   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03150
03151   if(errorstate != SD_OK)
03152   {
03153     return errorstate;
03154   }
03155   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
03156   sdmmc_datainitstructure.DataLength    = 8;
03157   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
03158   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03159   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03160   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
03161   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
03162
03163   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
03164   sdmmc_cmdinitstructure.Argument         = 0;
03165   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
03166   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03167
03168   /* Check for error conditions */
03169   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
03170
03171   if(errorstate != SD_OK)
03172   {
03173     return errorstate;
03174   }
03175
03176   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
03177   {
03178     if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
03179     {
03180       *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
03181       index++;
03182     }
03183   }
03184
03185   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03186   {
03187     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
03188
03189     errorstate = SD_DATA_TIMEOUT;
03190
03191     return errorstate;
03192   }
03193   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03194   {
03195     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
03196
03197     errorstate = SD_DATA_CRC_FAIL;
03198
03199     return errorstate;
03200   }
03201   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03202   {
03203     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
03204
03205     errorstate = SD_RX_OVERRUN;
03206
03207     return errorstate;
03208   }
03209   else
03210   {
03211     /* No error flag set */
03212   }
03213
03214   /* Clear all the static flags */
03215   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
03216
03217   *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
03218     ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
03219
03220   *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
03221     ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
03222
03223   return errorstate;
03224 }
03225
03226 /**
03227   * @brief  Checks if the SD card is in programming state.
03228   * @param  hsd: SD handle
03229   * @param  pStatus: pointer to the variable that will contain the SD card state
03230   * @retval SD Card error state
03231   */
03232 static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
03233 {
03234   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
03235   HAL_SD_ErrorTypedef errorstate = SD_OK;
03236   __IO uint32_t responseR1 = 0;
03237
03238   sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
03239   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
03240   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03241   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03242   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03243   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03244
03245   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
03246   {
03247   }
03248
03249   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
03250   {
03251     errorstate = SD_CMD_RSP_TIMEOUT;
03252
03253     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
03254
03255     return errorstate;
03256   }
03257   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
03258   {
03259     errorstate = SD_CMD_CRC_FAIL;
03260
03261     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
03262
03263     return errorstate;
03264   }
03265   else
03266   {
03267     /* No error flag set */
03268   }
03269
03270   /* Check response received is of desired command */
03271   if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
03272   {
03273     errorstate = SD_ILLEGAL_CMD;
03274
03275     return errorstate;
03276   }
03277
03278   /* Clear all the static flags */
03279   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
03280
03281
03282   /* We have received response, retrieve it for analysis */
03283   responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
03284
03285   /* Find out card status */
03286   *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
03287
03288   if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
03289   {
03290     return errorstate;
03291   }
03292
03293   if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
03294   {
03295     return(SD_ADDR_OUT_OF_RANGE);
03296   }
03297
03298   if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
03299   {
03300     return(SD_ADDR_MISALIGNED);
03301   }
03302
03303   if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
03304   {
03305     return(SD_BLOCK_LEN_ERR);
03306   }
03307
03308   if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
03309   {
03310     return(SD_ERASE_SEQ_ERR);
03311   }
03312
03313   if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
03314   {
03315     return(SD_BAD_ERASE_PARAM);
03316   }
03317
03318   if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
03319   {
03320     return(SD_WRITE_PROT_VIOLATION);
03321   }
03322
03323   if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
03324   {
03325     return(SD_LOCK_UNLOCK_FAILED);
03326   }
03327
03328   if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
03329   {
03330     return(SD_COM_CRC_FAILED);
03331   }
03332
03333   if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
03334   {
03335     return(SD_ILLEGAL_CMD);
03336   }
03337
03338   if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
03339   {
03340     return(SD_CARD_ECC_FAILED);
03341   }
03342
03343   if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
03344   {
03345     return(SD_CC_ERROR);
03346   }
03347
03348   if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
03349   {
03350     return(SD_GENERAL_UNKNOWN_ERROR);
03351   }
03352
03353   if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
03354   {
03355     return(SD_STREAM_READ_UNDERRUN);
03356   }
03357
03358   if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
03359   {
03360     return(SD_STREAM_WRITE_OVERRUN);
03361   }
03362
03363   if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
03364   {
03365     return(SD_CID_CSD_OVERWRITE);
03366   }
03367
03368   if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
03369   {
03370     return(SD_WP_ERASE_SKIP);
03371   }
03372
03373   if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
03374   {
03375     return(SD_CARD_ECC_DISABLED);
03376   }
03377
03378   if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
03379   {
03380     return(SD_ERASE_RESET);
03381   }
03382
03383   if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
03384   {
03385     return(SD_AKE_SEQ_ERROR);
03386   }
03387
03388   return errorstate;
03389 }
03390
03391 /**
03392   * @}
03393   */
03394
03395 #endif /* HAL_SD_MODULE_ENABLED */
03396
03397 /**
03398   * @}
03399   */
03400
03401 /**
03402   * @}
03403   */
03404
03405 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sd.h Source File

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stm32f7xx_hal_sd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SD_H
00040 #define __STM32F7xx_HAL_SD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_sdmmc.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup SD SD
00054   * @brief SD HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup SD_Exported_Types SD Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
00064   * @{
00065   */
00066 #define SD_InitTypeDef      SDMMC_InitTypeDef
00067 #define SD_TypeDef          SDMMC_TypeDef
00068
00069 typedef struct
00070 {
00071   SD_TypeDef                   *Instance;        /*!< SDMMC register base address                     */
00072
00073   SD_InitTypeDef               Init;             /*!< SD required parameters                         */
00074
00075   HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
00076
00077   uint32_t                     CardType;         /*!< SD card type                                   */
00078
00079   uint32_t                     RCA;              /*!< SD relative card address                       */
00080
00081   uint32_t                     CSD[4];           /*!< SD card specific data table                    */
00082
00083   uint32_t                     CID[4];           /*!< SD card identification number table            */
00084
00085   __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
00086
00087   __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
00088
00089   __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
00090
00091   __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
00092
00093   DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
00094
00095   DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
00096
00097 }SD_HandleTypeDef;
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
00103   * @{
00104   */
00105 typedef struct
00106 {
00107   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00108   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00109   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00110   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00111   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00112   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00113   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00114   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00115   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00116   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00117   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00118   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00119   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00120   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00121   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00122   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00123   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00124   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00125   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00126   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00127   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00128   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00129   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00130   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00131   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00132   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00133   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00134   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00135   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00136   __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
00137   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00138   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00139   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00140   __IO uint8_t  FileFormat;           /*!< File format                           */
00141   __IO uint8_t  ECC;                  /*!< ECC code                              */
00142   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00143   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00144
00145 }HAL_SD_CSDTypedef;
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
00151   * @{
00152   */
00153 typedef struct
00154 {
00155   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00156   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00157   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00158   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00159   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00160   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00161   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00162   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00163   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00164   __IO uint8_t  Reserved2;       /*!< Always 1              */
00165
00166 }HAL_SD_CIDTypedef;
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
00172   * @{
00173   */
00174 typedef struct
00175 {
00176   __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
00177   __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
00178   __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
00179   __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
00180   __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
00181   __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
00182   __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
00183   __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
00184   __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
00185   __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
00186
00187 }HAL_SD_CardStatusTypedef;
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup SD_Exported_Types_Group5 SD Card information structure
00193   * @{
00194   */
00195 typedef struct
00196 {
00197   HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
00198   HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
00199   uint64_t            CardCapacity;   /*!< Card capacity                          */
00200   uint32_t            CardBlockSize;  /*!< Card block size                        */
00201   uint16_t            RCA;            /*!< SD relative card address               */
00202   uint8_t             CardType;       /*!< SD card type                           */
00203
00204 }HAL_SD_CardInfoTypedef;
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
00210   * @{
00211   */
00212 typedef enum
00213 {
00214 /**
00215   * @brief  SD specific error defines
00216   */
00217   SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
00218   SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
00219   SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
00220   SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
00221   SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
00222   SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
00223   SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
00224   SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
00225   SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
00226   SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
00227   SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
00228   SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
00229   SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
00230   SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
00231   SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
00232   SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
00233   SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
00234   SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
00235   SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
00236   SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
00237   SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
00238   SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
00239   SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
00240   SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
00241   SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
00242   SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
00243   SD_INVALID_VOLTRANGE               = (27),
00244   SD_ADDR_OUT_OF_RANGE               = (28),
00245   SD_SWITCH_ERROR                    = (29),
00246   SD_SDMMC_DISABLED                  = (30),
00247   SD_SDMMC_FUNCTION_BUSY             = (31),
00248   SD_SDMMC_FUNCTION_FAILED           = (32),
00249   SD_SDMMC_UNKNOWN_FUNCTION          = (33),
00250
00251 /**
00252   * @brief  Standard error defines
00253   */
00254   SD_INTERNAL_ERROR                  = (34),
00255   SD_NOT_CONFIGURED                  = (35),
00256   SD_REQUEST_PENDING                 = (36),
00257   SD_REQUEST_NOT_APPLICABLE          = (37),
00258   SD_INVALID_PARAMETER               = (38),
00259   SD_UNSUPPORTED_FEATURE             = (39),
00260   SD_UNSUPPORTED_HW                  = (40),
00261   SD_ERROR                           = (41),
00262   SD_OK                              = (0)
00263
00264 }HAL_SD_ErrorTypedef;
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
00270   * @{
00271   */
00272 typedef enum
00273 {
00274   SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
00275   SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
00276   SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
00277
00278 }HAL_SD_TransferStateTypedef;
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
00284   * @{
00285   */
00286 typedef enum
00287 {
00288   SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
00289   SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
00290   SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
00291   SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */
00292   SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
00293   SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
00294   SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
00295   SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
00296   SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
00297
00298 }HAL_SD_CardStateTypedef;
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
00304   * @{
00305   */
00306 typedef enum
00307 {
00308   SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
00309   SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
00310   SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
00311   SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
00312
00313 }HAL_SD_OperationTypedef;
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321
00322 /* Exported constants --------------------------------------------------------*/
00323 /** @defgroup SD_Exported_Constants SD Exported Constants
00324   * @{
00325   */
00326
00327 /**
00328   * @brief SD Commands Index
00329   */
00330 #define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
00331 #define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
00332 #define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
00333 #define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
00334 #define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
00335 #define SD_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
00336                                                                        operating condition register (OCR) content in the response on the CMD line.              */
00337 #define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
00338 #define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
00339 #define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
00340                                                                        and asks the card whether card supports voltage.                                         */
00341 #define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
00342 #define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
00343 #define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
00344 #define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
00345 #define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
00346 #define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
00347 #define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
00348 #define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands
00349                                                                        (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
00350                                                                        for SDHS and SDXC.                                                                       */
00351 #define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
00352                                                                        fixed 512 bytes in case of SDHC and SDXC.                                                */
00353 #define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by
00354                                                                        STOP_TRANSMISSION command.                                                               */
00355 #define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
00356 #define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
00357 #define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
00358 #define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
00359                                                                        fixed 512 bytes in case of SDHC and SDXC.                                                */
00360 #define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
00361 #define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
00362 #define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
00363 #define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
00364 #define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
00365 #define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
00366 #define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
00367 #define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
00368 #define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command
00369                                                                        system set by switch function command (CMD6).                                            */
00370 #define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased.
00371                                                                        Reserved for each command system set by switch function command (CMD6).                  */
00372 #define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
00373 #define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
00374 #define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
00375 #define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
00376                                                                        the SET_BLOCK_LEN command.                                                               */
00377 #define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather
00378                                                                        than a standard command.                                                                 */
00379 #define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card
00380                                                                        for general purpose/application specific commands.                                       */
00381 #define SD_CMD_NO_CMD                              ((uint8_t)64)
00382
00383 /**
00384   * @brief Following commands are SD Card Specific commands.
00385   *        SDMMC_APP_CMD should be sent before sending these commands.
00386   */
00387 #define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
00388                                                                        widths are given in SCR register.                                                          */
00389 #define SD_CMD_SD_APP_STATUS                       ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
00390 #define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
00391                                                                        32bit+CRC data block.                                                                      */
00392 #define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
00393                                                                        send its operating condition register (OCR) content in the response on the CMD line.       */
00394 #define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
00395 #define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
00396 #define SD_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
00397 #define SD_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
00398
00399 /**
00400   * @brief Following commands are SD Card Specific security commands.
00401   *        SD_CMD_APP_CMD should be sent before sending these commands.
00402   */
00403 #define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
00404 #define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
00405 #define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
00406 #define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
00407 #define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
00408 #define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
00409 #define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
00410 #define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
00411 #define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
00412 #define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
00413 #define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
00414
00415 /**
00416   * @brief Supported SD Memory Cards
00417   */
00418 #define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
00419 #define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
00420 #define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
00421 #define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
00422 #define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
00423 #define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
00424 #define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
00425 #define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
00426 /**
00427   * @}
00428   */
00429
00430 /* Exported macro ------------------------------------------------------------*/
00431 /** @defgroup SD_Exported_macros SD Exported Macros
00432  *  @brief macros to handle interrupts and specific clock configurations
00433  * @{
00434  */
00435
00436 /**
00437   * @brief  Enable the SD device.
00438   * @retval None
00439   */
00440 #define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
00441
00442 /**
00443   * @brief  Disable the SD device.
00444   * @retval None
00445   */
00446 #define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
00447
00448 /**
00449   * @brief  Enable the SDMMC DMA transfer.
00450   * @retval None
00451   */
00452 #define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
00453
00454 /**
00455   * @brief  Disable the SDMMC DMA transfer.
00456   * @retval None
00457   */
00458 #define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
00459
00460 /**
00461   * @brief  Enable the SD device interrupt.
00462   * @param  __HANDLE__: SD Handle
00463   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00464   *         This parameter can be one or a combination of the following values:
00465   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00466   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00467   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00468   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00469   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00470   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00471   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00472   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00473   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00474   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00475   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00476   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00477   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00478   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00479   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00480   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00481   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00482   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00483   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00484   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00485   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00486   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00487   * @retval None
00488   */
00489 #define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00490
00491 /**
00492   * @brief  Disable the SD device interrupt.
00493   * @param  __HANDLE__: SD Handle
00494   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00495   *          This parameter can be one or a combination of the following values:
00496   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00497   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00498   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00499   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00500   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00501   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00502   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00503   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00504   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00505   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00506   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00507   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00508   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00509   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00510   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00511   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00512   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00513   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00514   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00515   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00516   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00517   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00518   * @retval None
00519   */
00520 #define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00521
00522 /**
00523   * @brief  Check whether the specified SD flag is set or not.
00524   * @param  __HANDLE__: SD Handle
00525   * @param  __FLAG__: specifies the flag to check.
00526   *          This parameter can be one of the following values:
00527   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
00528   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00529   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
00530   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
00531   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
00532   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
00533   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
00534   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
00535   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00536   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00537   *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
00538   *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
00539   *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
00540   *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00541   *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
00542   *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
00543   *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
00544   *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
00545   *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
00546   *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
00547   *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
00548   *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
00549   * @retval The new state of SD FLAG (SET or RESET).
00550   */
00551 #define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00552
00553 /**
00554   * @brief  Clear the SD's pending flags.
00555   * @param  __HANDLE__: SD Handle
00556   * @param  __FLAG__: specifies the flag to clear.
00557   *          This parameter can be one or a combination of the following values:
00558   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
00559   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00560   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
00561   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
00562   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
00563   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
00564   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
00565   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
00566   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00567   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00568   *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
00569   * @retval None
00570   */
00571 #define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00572
00573 /**
00574   * @brief  Check whether the specified SD interrupt has occurred or not.
00575   * @param  __HANDLE__: SD Handle
00576   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00577   *          This parameter can be one of the following values:
00578   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00579   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00580   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00581   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00582   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00583   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00584   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00585   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00586   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00587   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00588   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00589   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00590   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00591   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00592   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00593   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00594   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00595   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00596   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00597   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00598   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00599   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00600   * @retval The new state of SD IT (SET or RESET).
00601   */
00602 #define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00603
00604 /**
00605   * @brief  Clear the SD's interrupt pending bits.
00606   * @param  __HANDLE__: SD Handle
00607   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00608   *          This parameter can be one or a combination of the following values:
00609   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00610   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00611   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00612   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00613   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00614   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00615   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00616   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00617   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
00618   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00619   * @retval None
00620   */
00621 #define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00622 /**
00623   * @}
00624   */
00625
00626 /* Exported functions --------------------------------------------------------*/
00627 /** @defgroup SD_Exported_Functions SD Exported Functions
00628   * @{
00629   */
00630
00631 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
00632   * @{
00633   */
00634 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
00635 HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
00636 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
00637 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
00643   * @{
00644   */
00645 /* Blocking mode: Polling */
00646 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00647 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00648 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
00649
00650 /* Non-Blocking mode: Interrupt */
00651 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
00652
00653 /* Callback in non blocking modes (DMA) */
00654 void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
00655 void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
00656 void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
00657 void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
00658 void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
00659 void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
00660
00661 /* Non-Blocking mode: DMA */
00662 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00663 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00664 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
00665 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
00671   * @{
00672   */
00673 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
00674 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
00675 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
00676 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
00677 /**
00678   * @}
00679   */
00680
00681 /* Peripheral State functions  ************************************************/
00682 /** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
00683   * @{
00684   */
00685 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00686 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
00687 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
00688 /**
00689   * @}
00690   */
00691
00692 /**
00693   * @}
00694   */
00695
00696 /* Private types -------------------------------------------------------------*/
00697 /** @defgroup SD_Private_Types SD Private Types
00698   * @{
00699   */
00700
00701 /**
00702   * @}
00703   */
00704
00705 /* Private defines -----------------------------------------------------------*/
00706 /** @defgroup SD_Private_Defines SD Private Defines
00707   * @{
00708   */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /* Private variables ---------------------------------------------------------*/
00715 /** @defgroup SD_Private_Variables SD Private Variables
00716   * @{
00717   */
00718
00719 /**
00720   * @}
00721   */
00722
00723 /* Private constants ---------------------------------------------------------*/
00724 /** @defgroup SD_Private_Constants SD Private Constants
00725   * @{
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /* Private macros ------------------------------------------------------------*/
00733 /** @defgroup SD_Private_Macros SD Private Macros
00734   * @{
00735   */
00736
00737 /**
00738   * @}
00739   */
00740
00741 /* Private functions prototypes ----------------------------------------------*/
00742 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
00743   * @{
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /* Private functions ---------------------------------------------------------*/
00751 /** @defgroup SD_Private_Functions SD Private Functions
00752   * @{
00753   */
00754
00755 /**
00756   * @}
00757   */
00758
00759 /**
00760   * @}
00761   */
00762
00763 /**
00764   * @}
00765   */
00766
00767 #ifdef __cplusplus
00768 }
00769 #endif
00770
00771
00772 #endif /* __STM32F7xx_HAL_SD_H */
00773
00774 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sdram.c Source File

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stm32f7xx_hal_sdram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sdram.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SDRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SDRAM memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                        ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SDRAM memories. It uses the FMC layer functions to interface
00018     with SDRAM devices.
00019     The following sequence should be followed to configure the FMC to interface
00020     with SDRAM memories:
00021
00022    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
00023           SDRAM_HandleTypeDef  hdsram
00024
00025        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SDRAM device
00030
00031    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
00032           FMC_SDRAM_TimingTypeDef  Timing;
00033       and fill its fields with the allowed values of the structure member.
00034
00035    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
00036        performs the following sequence:
00037
00038        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
00039        (##) Control register configuration using the FMC SDRAM interface function
00040             FMC_SDRAM_Init()
00041        (##) Timing register configuration using the FMC SDRAM interface function
00042             FMC_SDRAM_Timing_Init()
00043        (##) Program the SDRAM external device by applying its initialization sequence
00044             according to the device plugged in your hardware. This step is mandatory
00045             for accessing the SDRAM device.
00046
00047    (#) At this stage you can perform read/write accesses from/to the memory connected
00048        to the SDRAM Bank. You can perform either polling or DMA transfer using the
00049        following APIs:
00050        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
00051        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
00052
00053    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
00054        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
00055        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
00056        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
00057        structure.
00058
00059    (#) You can continuously monitor the SDRAM device HAL state by calling the function
00060        HAL_SDRAM_GetState()
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32f7xx_hal.h"
00095
00096 /** @addtogroup STM32F7xx_HAL_Driver
00097   * @{
00098   */
00099
00100 /** @defgroup SDRAM SDRAM
00101   * @brief SDRAM driver modules
00102   * @{
00103   */
00104 #ifdef HAL_SDRAM_MODULE_ENABLED
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 /* Private macro -------------------------------------------------------------*/
00109 /* Private variables ---------------------------------------------------------*/
00110 /* Private functions ---------------------------------------------------------*/
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
00113   * @{
00114   */
00115
00116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00117   * @brief    Initialization and Configuration functions
00118   *
00119   @verbatim
00120   ==============================================================================
00121            ##### SDRAM Initialization and de_initialization functions #####
00122   ==============================================================================
00123   [..]
00124     This section provides functions allowing to initialize/de-initialize
00125     the SDRAM memory
00126
00127 @endverbatim
00128   * @{
00129   */
00130
00131 /**
00132   * @brief  Performs the SDRAM device initialization sequence.
00133   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00134   *                the configuration information for SDRAM module.
00135   * @param  Timing: Pointer to SDRAM control timing structure
00136   * @retval HAL status
00137   */
00138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
00139 {
00140   /* Check the SDRAM handle parameter */
00141   if(hsdram == NULL)
00142   {
00143     return HAL_ERROR;
00144   }
00145
00146   if(hsdram->State == HAL_SDRAM_STATE_RESET)
00147   {
00148     /* Allocate lock resource and initialize it */
00149     hsdram->Lock = HAL_UNLOCKED;
00150     /* Initialize the low level hardware (MSP) */
00151     HAL_SDRAM_MspInit(hsdram);
00152   }
00153
00154   /* Initialize the SDRAM controller state */
00155   hsdram->State = HAL_SDRAM_STATE_BUSY;
00156
00157   /* Initialize SDRAM control Interface */
00158   FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
00159
00160   /* Initialize SDRAM timing Interface */
00161   FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
00162
00163   /* Update the SDRAM controller state */
00164   hsdram->State = HAL_SDRAM_STATE_READY;
00165
00166   return HAL_OK;
00167 }
00168
00169 /**
00170   * @brief  Perform the SDRAM device initialization sequence.
00171   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00172   *                the configuration information for SDRAM module.
00173   * @retval HAL status
00174   */
00175 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
00176 {
00177   /* Initialize the low level hardware (MSP) */
00178   HAL_SDRAM_MspDeInit(hsdram);
00179
00180   /* Configure the SDRAM registers with their reset values */
00181   FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
00182
00183   /* Reset the SDRAM controller state */
00184   hsdram->State = HAL_SDRAM_STATE_RESET;
00185
00186   /* Release Lock */
00187   __HAL_UNLOCK(hsdram);
00188
00189   return HAL_OK;
00190 }
00191
00192 /**
00193   * @brief  SDRAM MSP Init.
00194   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00195   *                the configuration information for SDRAM module.
00196   * @retval None
00197   */
00198 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
00199 {
00200   /* Prevent unused argument(s) compilation warning */
00201   UNUSED(hsdram);
00202
00203   /* NOTE: This function Should not be modified, when the callback is needed,
00204             the HAL_SDRAM_MspInit could be implemented in the user file
00205    */
00206 }
00207
00208 /**
00209   * @brief  SDRAM MSP DeInit.
00210   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00211   *                the configuration information for SDRAM module.
00212   * @retval None
00213   */
00214 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
00215 {
00216   /* Prevent unused argument(s) compilation warning */
00217   UNUSED(hsdram);
00218
00219   /* NOTE: This function Should not be modified, when the callback is needed,
00220             the HAL_SDRAM_MspDeInit could be implemented in the user file
00221    */
00222 }
00223
00224 /**
00225   * @brief  This function handles SDRAM refresh error interrupt request.
00226   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00227   *                the configuration information for SDRAM module.
00228   * @retval HAL status
00229 */
00230 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
00231 {
00232   /* Check SDRAM interrupt Rising edge flag */
00233   if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
00234   {
00235     /* SDRAM refresh error interrupt callback */
00236     HAL_SDRAM_RefreshErrorCallback(hsdram);
00237
00238     /* Clear SDRAM refresh error interrupt pending bit */
00239     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
00240   }
00241 }
00242
00243 /**
00244   * @brief  SDRAM Refresh error callback.
00245   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00246   *                the configuration information for SDRAM module.
00247   * @retval None
00248   */
00249 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
00250 {
00251   /* Prevent unused argument(s) compilation warning */
00252   UNUSED(hsdram);
00253
00254   /* NOTE: This function Should not be modified, when the callback is needed,
00255             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
00256    */
00257 }
00258
00259 /**
00260   * @brief  DMA transfer complete callback.
00261   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00262   *                the configuration information for the specified DMA module.
00263   * @retval None
00264   */
00265 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00266 {
00267   /* Prevent unused argument(s) compilation warning */
00268   UNUSED(hdma);
00269
00270   /* NOTE: This function Should not be modified, when the callback is needed,
00271             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
00272    */
00273 }
00274
00275 /**
00276   * @brief  DMA transfer complete error callback.
00277   * @param  hdma: DMA handle
00278   * @retval None
00279   */
00280 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00281 {
00282   /* Prevent unused argument(s) compilation warning */
00283   UNUSED(hdma);
00284
00285   /* NOTE: This function Should not be modified, when the callback is needed,
00286             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
00287    */
00288 }
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
00295   * @brief    Input Output and memory control functions
00296   *
00297   @verbatim
00298   ==============================================================================
00299                     ##### SDRAM Input and Output functions #####
00300   ==============================================================================
00301   [..]
00302     This section provides functions allowing to use and control the SDRAM memory
00303
00304 @endverbatim
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Reads 8-bit data buffer from the SDRAM memory.
00310   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00311   *                the configuration information for SDRAM module.
00312   * @param  pAddress: Pointer to read start address
00313   * @param  pDstBuffer: Pointer to destination buffer
00314   * @param  BufferSize: Size of the buffer to read from memory
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00318 {
00319   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00320
00321   /* Process Locked */
00322   __HAL_LOCK(hsdram);
00323
00324   /* Check the SDRAM controller state */
00325   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00326   {
00327     return HAL_BUSY;
00328   }
00329   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00330   {
00331     return  HAL_ERROR;
00332   }
00333
00334   /* Read data from source */
00335   for(; BufferSize != 0; BufferSize--)
00336   {
00337     *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
00338     pDstBuffer++;
00339     pSdramAddress++;
00340   }
00341
00342   /* Process Unlocked */
00343   __HAL_UNLOCK(hsdram);
00344
00345   return HAL_OK;
00346 }
00347
00348
00349 /**
00350   * @brief  Writes 8-bit data buffer to SDRAM memory.
00351   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00352   *                the configuration information for SDRAM module.
00353   * @param  pAddress: Pointer to write start address
00354   * @param  pSrcBuffer: Pointer to source buffer to write
00355   * @param  BufferSize: Size of the buffer to write to memory
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00359 {
00360   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00361   uint32_t tmp = 0;
00362
00363   /* Process Locked */
00364   __HAL_LOCK(hsdram);
00365
00366   /* Check the SDRAM controller state */
00367   tmp = hsdram->State;
00368
00369   if(tmp == HAL_SDRAM_STATE_BUSY)
00370   {
00371     return HAL_BUSY;
00372   }
00373   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00374   {
00375     return  HAL_ERROR;
00376   }
00377
00378   /* Write data to memory */
00379   for(; BufferSize != 0; BufferSize--)
00380   {
00381     *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
00382     pSrcBuffer++;
00383     pSdramAddress++;
00384   }
00385
00386   /* Process Unlocked */
00387   __HAL_UNLOCK(hsdram);
00388
00389   return HAL_OK;
00390 }
00391
00392
00393 /**
00394   * @brief  Reads 16-bit data buffer from the SDRAM memory.
00395   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00396   *                the configuration information for SDRAM module.
00397   * @param  pAddress: Pointer to read start address
00398   * @param  pDstBuffer: Pointer to destination buffer
00399   * @param  BufferSize: Size of the buffer to read from memory
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00403 {
00404   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
00405
00406   /* Process Locked */
00407   __HAL_LOCK(hsdram);
00408
00409   /* Check the SDRAM controller state */
00410   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00411   {
00412     return HAL_BUSY;
00413   }
00414   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00415   {
00416     return  HAL_ERROR;
00417   }
00418
00419   /* Read data from source */
00420   for(; BufferSize != 0; BufferSize--)
00421   {
00422     *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
00423     pDstBuffer++;
00424     pSdramAddress++;
00425   }
00426
00427   /* Process Unlocked */
00428   __HAL_UNLOCK(hsdram);
00429
00430   return HAL_OK;
00431 }
00432
00433 /**
00434   * @brief  Writes 16-bit data buffer to SDRAM memory.
00435   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00436   *                the configuration information for SDRAM module.
00437   * @param  pAddress: Pointer to write start address
00438   * @param  pSrcBuffer: Pointer to source buffer to write
00439   * @param  BufferSize: Size of the buffer to write to memory
00440   * @retval HAL status
00441   */
00442 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00443 {
00444   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
00445   uint32_t tmp = 0;
00446
00447   /* Process Locked */
00448   __HAL_LOCK(hsdram);
00449
00450   /* Check the SDRAM controller state */
00451   tmp = hsdram->State;
00452
00453   if(tmp == HAL_SDRAM_STATE_BUSY)
00454   {
00455     return HAL_BUSY;
00456   }
00457   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00458   {
00459     return  HAL_ERROR;
00460   }
00461
00462   /* Write data to memory */
00463   for(; BufferSize != 0; BufferSize--)
00464   {
00465     *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
00466     pSrcBuffer++;
00467     pSdramAddress++;
00468   }
00469
00470   /* Process Unlocked */
00471   __HAL_UNLOCK(hsdram);
00472
00473   return HAL_OK;
00474 }
00475
00476 /**
00477   * @brief  Reads 32-bit data buffer from the SDRAM memory.
00478   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00479   *                the configuration information for SDRAM module.
00480   * @param  pAddress: Pointer to read start address
00481   * @param  pDstBuffer: Pointer to destination buffer
00482   * @param  BufferSize: Size of the buffer to read from memory
00483   * @retval HAL status
00484   */
00485 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00486 {
00487   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00488
00489   /* Process Locked */
00490   __HAL_LOCK(hsdram);
00491
00492   /* Check the SDRAM controller state */
00493   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00494   {
00495     return HAL_BUSY;
00496   }
00497   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00498   {
00499     return  HAL_ERROR;
00500   }
00501
00502   /* Read data from source */
00503   for(; BufferSize != 0; BufferSize--)
00504   {
00505     *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
00506     pDstBuffer++;
00507     pSdramAddress++;
00508   }
00509
00510   /* Process Unlocked */
00511   __HAL_UNLOCK(hsdram);
00512
00513   return HAL_OK;
00514 }
00515
00516 /**
00517   * @brief  Writes 32-bit data buffer to SDRAM memory.
00518   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00519   *                the configuration information for SDRAM module.
00520   * @param  pAddress: Pointer to write start address
00521   * @param  pSrcBuffer: Pointer to source buffer to write
00522   * @param  BufferSize: Size of the buffer to write to memory
00523   * @retval HAL status
00524   */
00525 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00526 {
00527   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00528   uint32_t tmp = 0;
00529
00530   /* Process Locked */
00531   __HAL_LOCK(hsdram);
00532
00533   /* Check the SDRAM controller state */
00534   tmp = hsdram->State;
00535
00536   if(tmp == HAL_SDRAM_STATE_BUSY)
00537   {
00538     return HAL_BUSY;
00539   }
00540   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00541   {
00542     return  HAL_ERROR;
00543   }
00544
00545   /* Write data to memory */
00546   for(; BufferSize != 0; BufferSize--)
00547   {
00548     *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
00549     pSrcBuffer++;
00550     pSdramAddress++;
00551   }
00552
00553   /* Process Unlocked */
00554   __HAL_UNLOCK(hsdram);
00555
00556   return HAL_OK;
00557 }
00558
00559 /**
00560   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
00561   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00562   *                the configuration information for SDRAM module.
00563   * @param  pAddress: Pointer to read start address
00564   * @param  pDstBuffer: Pointer to destination buffer
00565   * @param  BufferSize: Size of the buffer to read from memory
00566   * @retval HAL status
00567   */
00568 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00569 {
00570   uint32_t tmp = 0;
00571
00572   /* Process Locked */
00573   __HAL_LOCK(hsdram);
00574
00575   /* Check the SDRAM controller state */
00576   tmp = hsdram->State;
00577
00578   if(tmp == HAL_SDRAM_STATE_BUSY)
00579   {
00580     return HAL_BUSY;
00581   }
00582   else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
00583   {
00584     return  HAL_ERROR;
00585   }
00586
00587   /* Configure DMA user callbacks */
00588   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
00589   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00590
00591   /* Enable the DMA Stream */
00592   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00593
00594   /* Process Unlocked */
00595   __HAL_UNLOCK(hsdram);
00596
00597   return HAL_OK;
00598 }
00599
00600 /**
00601   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
00602   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00603   *                the configuration information for SDRAM module.
00604   * @param  pAddress: Pointer to write start address
00605   * @param  pSrcBuffer: Pointer to source buffer to write
00606   * @param  BufferSize: Size of the buffer to write to memory
00607   * @retval HAL status
00608   */
00609 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00610 {
00611   uint32_t tmp = 0;
00612
00613   /* Process Locked */
00614   __HAL_LOCK(hsdram);
00615
00616   /* Check the SDRAM controller state */
00617   tmp = hsdram->State;
00618
00619   if(tmp == HAL_SDRAM_STATE_BUSY)
00620   {
00621     return HAL_BUSY;
00622   }
00623   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00624   {
00625     return  HAL_ERROR;
00626   }
00627
00628   /* Configure DMA user callbacks */
00629   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
00630   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00631
00632   /* Enable the DMA Stream */
00633   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00634
00635   /* Process Unlocked */
00636   __HAL_UNLOCK(hsdram);
00637
00638   return HAL_OK;
00639 }
00640
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
00646  *  @brief   management functions
00647  *
00648 @verbatim
00649   ==============================================================================
00650                          ##### SDRAM Control functions #####
00651   ==============================================================================
00652   [..]
00653     This subsection provides a set of functions allowing to control dynamically
00654     the SDRAM interface.
00655
00656 @endverbatim
00657   * @{
00658   */
00659
00660 /**
00661   * @brief  Enables dynamically SDRAM write protection.
00662   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00663   *                the configuration information for SDRAM module.
00664   * @retval HAL status
00665   */
00666 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
00667 {
00668   /* Check the SDRAM controller state */
00669   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00670   {
00671     return HAL_BUSY;
00672   }
00673
00674   /* Update the SDRAM state */
00675   hsdram->State = HAL_SDRAM_STATE_BUSY;
00676
00677   /* Enable write protection */
00678   FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
00679
00680   /* Update the SDRAM state */
00681   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
00682
00683   return HAL_OK;
00684 }
00685
00686 /**
00687   * @brief  Disables dynamically SDRAM write protection.
00688   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00689   *                the configuration information for SDRAM module.
00690   * @retval HAL status
00691   */
00692 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
00693 {
00694   /* Check the SDRAM controller state */
00695   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00696   {
00697     return HAL_BUSY;
00698   }
00699
00700   /* Update the SDRAM state */
00701   hsdram->State = HAL_SDRAM_STATE_BUSY;
00702
00703   /* Disable write protection */
00704   FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
00705
00706   /* Update the SDRAM state */
00707   hsdram->State = HAL_SDRAM_STATE_READY;
00708
00709   return HAL_OK;
00710 }
00711
00712 /**
00713   * @brief  Sends Command to the SDRAM bank.
00714   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00715   *                the configuration information for SDRAM module.
00716   * @param  Command: SDRAM command structure
00717   * @param  Timeout: Timeout duration
00718   * @retval HAL status
00719   */
00720 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
00721 {
00722   /* Check the SDRAM controller state */
00723   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00724   {
00725     return HAL_BUSY;
00726   }
00727
00728   /* Update the SDRAM state */
00729   hsdram->State = HAL_SDRAM_STATE_BUSY;
00730
00731   /* Send SDRAM command */
00732   FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
00733
00734   /* Update the SDRAM controller state state */
00735   if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
00736   {
00737     hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
00738   }
00739   else
00740   {
00741     hsdram->State = HAL_SDRAM_STATE_READY;
00742   }
00743
00744   return HAL_OK;
00745 }
00746
00747 /**
00748   * @brief  Programs the SDRAM Memory Refresh rate.
00749   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00750   *                the configuration information for SDRAM module.
00751   * @param  RefreshRate: The SDRAM refresh rate value
00752   * @retval HAL status
00753   */
00754 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
00755 {
00756   /* Check the SDRAM controller state */
00757   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00758   {
00759     return HAL_BUSY;
00760   }
00761
00762   /* Update the SDRAM state */
00763   hsdram->State = HAL_SDRAM_STATE_BUSY;
00764
00765   /* Program the refresh rate */
00766   FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
00767
00768   /* Update the SDRAM state */
00769   hsdram->State = HAL_SDRAM_STATE_READY;
00770
00771   return HAL_OK;
00772 }
00773
00774 /**
00775   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
00776   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00777   *                the configuration information for SDRAM module.
00778   * @param  AutoRefreshNumber: The SDRAM auto Refresh number
00779   * @retval HAL status
00780   */
00781 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
00782 {
00783   /* Check the SDRAM controller state */
00784   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00785   {
00786     return HAL_BUSY;
00787   }
00788
00789   /* Update the SDRAM state */
00790   hsdram->State = HAL_SDRAM_STATE_BUSY;
00791
00792   /* Set the Auto-Refresh number */
00793   FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
00794
00795   /* Update the SDRAM state */
00796   hsdram->State = HAL_SDRAM_STATE_READY;
00797
00798   return HAL_OK;
00799 }
00800
00801 /**
00802   * @brief  Returns the SDRAM memory current mode.
00803   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00804   *                the configuration information for SDRAM module.
00805   * @retval The SDRAM memory mode.
00806   */
00807 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
00808 {
00809   /* Return the SDRAM memory current mode */
00810   return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
00811 }
00812
00813 /**
00814   * @}
00815   */
00816
00817 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
00818  *  @brief   Peripheral State functions
00819  *
00820 @verbatim
00821   ==============================================================================
00822                       ##### SDRAM State functions #####
00823   ==============================================================================
00824   [..]
00825     This subsection permits to get in run-time the status of the SDRAM controller
00826     and the data flow.
00827
00828 @endverbatim
00829   * @{
00830   */
00831
00832 /**
00833   * @brief  Returns the SDRAM state.
00834   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00835   *                the configuration information for SDRAM module.
00836   * @retval HAL state
00837   */
00838 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
00839 {
00840   return hsdram->State;
00841 }
00842
00843 /**
00844   * @}
00845   */
00846
00847 /**
00848   * @}
00849   */
00850 #endif /* HAL_SDRAM_MODULE_ENABLED */
00851 /**
00852   * @}
00853   */
00854
00855 /**
00856   * @}
00857   */
00858
00859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sdram.h Source File

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stm32f7xx_hal_sdram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sdram.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SDRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SDRAM_H
00040 #define __STM32F7xx_HAL_SDRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_fmc.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SDRAM
00054   * @{
00055   */
00056
00057 /* Exported typedef ----------------------------------------------------------*/
00058
00059 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL SDRAM State structure definition
00065   */
00066 typedef enum
00067 {
00068   HAL_SDRAM_STATE_RESET             = 0x00,  /*!< SDRAM not yet initialized or disabled */
00069   HAL_SDRAM_STATE_READY             = 0x01,  /*!< SDRAM initialized and ready for use   */
00070   HAL_SDRAM_STATE_BUSY              = 0x02,  /*!< SDRAM internal process is ongoing     */
00071   HAL_SDRAM_STATE_ERROR             = 0x03,  /*!< SDRAM error state                     */
00072   HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04,  /*!< SDRAM device write protected          */
00073   HAL_SDRAM_STATE_PRECHARGED        = 0x05   /*!< SDRAM device precharged               */
00074
00075 }HAL_SDRAM_StateTypeDef;
00076
00077 /**
00078   * @brief  SDRAM handle Structure definition
00079   */
00080 typedef struct
00081 {
00082   FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
00083
00084   FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
00085
00086   __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
00087
00088   HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */
00089
00090   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */
00091
00092 }SDRAM_HandleTypeDef;
00093 /**
00094   * @}
00095   */
00096
00097 /* Exported constants --------------------------------------------------------*/
00098 /* Exported macro ------------------------------------------------------------*/
00099
00100 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
00101   * @{
00102   */
00103
00104 /** @brief Reset SDRAM handle state
00105   * @param  __HANDLE__: specifies the SDRAM handle.
00106   * @retval None
00107   */
00108 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported functions --------------------------------------------------------*/
00115
00116 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
00117   * @{
00118   */
00119
00120 /** @addtogroup SDRAM_Exported_Functions_Group1
00121   * @{
00122   */
00123
00124 /* Initialization/de-initialization functions *********************************/
00125 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
00126 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
00127 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
00128 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
00129
00130 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
00131 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
00132 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00133 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00134
00135 /**
00136   * @}
00137   */
00138
00139 /** @addtogroup SDRAM_Exported_Functions_Group2
00140   * @{
00141   */
00142 /* I/O operation functions ****************************************************/
00143 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00144 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00147 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00148 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00149
00150 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00151 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @addtogroup SDRAM_Exported_Functions_Group3
00158   * @{
00159   */
00160 /* SDRAM Control functions  *****************************************************/
00161 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
00162 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
00163 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
00164 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
00165 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
00166 uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
00167
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup SDRAM_Exported_Functions_Group4
00173   * @{
00174   */
00175 /* SDRAM State functions ********************************************************/
00176 HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 #ifdef __cplusplus
00194 }
00195 #endif
00196
00197 #endif /* __STM32F7xx_HAL_SDRAM_H */
00198
00199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard.c Source File

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stm32f7xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the SMARTCARD peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The SMARTCARD HAL driver can be used as follow:
00020
00021     (#) Declare a SMARTCARD_HandleTypeDef handle structure.
00022     (#) Associate a USART to the SMARTCARD handle hsc.
00023     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00024         (##) Enable the USARTx interface clock.
00025         (##) SMARTCARD pins configuration:
00026             (+++) Enable the clock for the SMARTCARD GPIOs.
00027             (+++) Configure these SMARTCARD pins as alternate function pull-up.
00028         (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00029              and HAL_SMARTCARD_Receive_IT() APIs):
00030             (+++) Configure the USARTx interrupt priority.
00031             (+++) Enable the NVIC USART IRQ handle.
00032             (+++) The specific USART interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00035         (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00036              and HAL_SMARTCARD_Receive_DMA() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx Stream.
00041             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
00043
00044     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00045         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00046         error enabling or disabling in the hsc Init structure.
00047
00048     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00049         in the hsc AdvancedInit structure.
00050
00051     (#) Initialize the SMARTCARD associated USART registers by calling
00052         the HAL_SMARTCARD_Init() API.
00053
00054   [..]
00055     (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00056         calling the customized HAL_SMARTCARD_MspInit() API.
00057
00058   @endverbatim
00059   ******************************************************************************
00060   * @attention
00061   *
00062   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00063   *
00064   * Redistribution and use in source and binary forms, with or without modification,
00065   * are permitted provided that the following conditions are met:
00066   *   1. Redistributions of source code must retain the above copyright notice,
00067   *      this list of conditions and the following disclaimer.
00068   *   2. Redistributions in binary form must reproduce the above copyright notice,
00069   *      this list of conditions and the following disclaimer in the documentation
00070   *      and/or other materials provided with the distribution.
00071   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00072   *      may be used to endorse or promote products derived from this software
00073   *      without specific prior written permission.
00074   *
00075   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00076   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00077   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00078   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00079   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00080   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00081   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00082   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00083   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00084   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00085   *
00086   ******************************************************************************
00087   */
00088
00089 /* Includes ------------------------------------------------------------------*/
00090 #include "stm32f7xx_hal.h"
00091
00092 /** @addtogroup STM32F7xx_HAL_Driver
00093   * @{
00094   */
00095
00096 /** @defgroup SMARTCARD SMARTCARD
00097   * @brief HAL USART SMARTCARD module driver
00098   * @{
00099   */
00100 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00101 /* Private typedef -----------------------------------------------------------*/
00102 /* Private define ------------------------------------------------------------*/
00103 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00104  * @{
00105  */
00106 #define TEACK_REACK_TIMEOUT               1000
00107 #define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE  22000
00108 #define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00109                                           USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
00110 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
00111 #define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
00112 #define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))
00113 /**
00114   * @}
00115   */
00116 /* Private macros -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /** @addtogroup SMARTCARD_Private_Functions
00120   * @{
00121   */
00122 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00123 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00124 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00125 static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc);
00126 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00127 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc);
00128 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
00129 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
00130 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
00131 /**
00132   * @}
00133   */
00134 /* Exported functions --------------------------------------------------------*/
00135 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00136   * @{
00137   */
00138
00139 /** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
00140   *  @brief    Initialization and Configuration functions
00141   *
00142 @verbatim
00143 ===============================================================================
00144             ##### Initialization and Configuration functions #####
00145  ===============================================================================
00146   [..]
00147   This subsection provides a set of functions allowing to initialize the USART
00148   associated to the SmartCard.
00149       (+) These parameters can be configured:
00150         (++) Baud Rate
00151         (++) Parity: parity should be enabled,
00152              Frame Length is fixed to 8 bits plus parity:
00153              the USART frame format is given in the following table:
00154
00155         (+++) +---------------------------------------------------------------+
00156         (+++) | M1M0 bits |  PCE bit  |            USART frame                |
00157         (+++) |-----------------------|---------------------------------------|
00158         (+++) |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00159         (+++) +---------------------------------------------------------------+
00160
00161         (++) Receiver/transmitter modes
00162         (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00163         (++) Prescaler value
00164         (++) Guard bit time
00165         (++) NACK enabling or disabling on transmission error
00166
00167       (+) The following advanced features can be configured as well:
00168         (++) TX and/or RX pin level inversion
00169         (++) data logical level inversion
00170         (++) RX and TX pins swap
00171         (++) RX overrun detection disabling
00172         (++) DMA disabling on RX error
00173         (++) MSB first on communication line
00174         (++) Time out enabling (and if activated, timeout value)
00175         (++) Block length
00176         (++) Auto-retry counter
00177
00178     [..]
00179     The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures
00180     (details for the procedures are available in reference manual).
00181
00182 @endverbatim
00183   * @{
00184   */
00185
00186 /**
00187   * @brief Initializes the SMARTCARD mode according to the specified
00188   *         parameters in the SMARTCARD_InitTypeDef and create the associated handle .
00189   * @param hsc: SMARTCARD handle
00190   * @retval HAL status
00191   */
00192 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
00193 {
00194   /* Check the SMARTCARD handle allocation */
00195   if(hsc == NULL)
00196   {
00197     return HAL_ERROR;
00198   }
00199
00200   /* Check the parameters */
00201   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00202
00203   if(hsc->State == HAL_SMARTCARD_STATE_RESET)
00204   {
00205     /* Allocate lock resource and initialize it */
00206     hsc->Lock = HAL_UNLOCKED;
00207     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00208     HAL_SMARTCARD_MspInit(hsc);
00209   }
00210
00211   hsc->State = HAL_SMARTCARD_STATE_BUSY;
00212
00213   /* Disable the Peripheral */
00214   __HAL_SMARTCARD_DISABLE(hsc);
00215
00216   /* Set the SMARTCARD Communication parameters */
00217   SMARTCARD_SetConfig(hsc);
00218
00219   if(hsc->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00220   {
00221     SMARTCARD_AdvFeatureConfig(hsc);
00222   }
00223
00224   /* In SmartCard mode, the following bits must be kept cleared:
00225   - LINEN in the USART_CR2 register,
00226   - HDSEL and IREN  bits in the USART_CR3 register.*/
00227   hsc->Instance->CR2 &= ~(USART_CR2_LINEN);
00228   hsc->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
00229
00230   /* set the USART in SMARTCARD mode */
00231   hsc->Instance->CR3 |= USART_CR3_SCEN;
00232
00233   /* Enable the Peripheral */
00234   __HAL_SMARTCARD_ENABLE(hsc);
00235
00236   /* TEACK and/or REACK to check before moving hsc->State to Ready */
00237   return (SMARTCARD_CheckIdleState(hsc));
00238 }
00239
00240 /**
00241   * @brief DeInitializes the SMARTCARD peripheral
00242   * @param hsc: SMARTCARD handle
00243   * @retval HAL status
00244   */
00245 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
00246 {
00247   /* Check the SMARTCARD handle allocation */
00248   if(hsc == NULL)
00249   {
00250     return HAL_ERROR;
00251   }
00252
00253   /* Check the parameters */
00254   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00255
00256   hsc->State = HAL_SMARTCARD_STATE_BUSY;
00257
00258   /* DeInit the low level hardware */
00259   HAL_SMARTCARD_MspDeInit(hsc);
00260
00261   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00262   hsc->State = HAL_SMARTCARD_STATE_RESET;
00263
00264   /* Release Lock */
00265   __HAL_UNLOCK(hsc);
00266
00267   return HAL_OK;
00268 }
00269
00270 /**
00271   * @brief SMARTCARD MSP Init
00272   * @param hsc: SMARTCARD handle
00273   * @retval None
00274   */
00275  __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
00276 {
00277   /* Prevent unused argument(s) compilation warning */
00278   UNUSED(hsc);
00279
00280   /* NOTE : This function Should not be modified, when the callback is needed,
00281             the HAL_SMARTCARD_MspInit could be implemented in the user file
00282    */
00283 }
00284
00285 /**
00286   * @brief SMARTCARD MSP DeInit
00287   * @param hsc: SMARTCARD handle
00288   * @retval None
00289   */
00290  __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
00291 {
00292   /* Prevent unused argument(s) compilation warning */
00293   UNUSED(hsc);
00294
00295   /* NOTE : This function Should not be modified, when the callback is needed,
00296             the HAL_SMARTCARD_MspDeInit could be implemented in the user file
00297    */
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00305   *  @brief   SMARTCARD Transmit and Receive functions
00306   *
00307 @verbatim
00308  ===============================================================================
00309                       ##### IO operation functions #####
00310  ===============================================================================
00311     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00312
00313     (#) There are two modes of transfer:
00314        (+) Blocking mode: The communication is performed in polling mode.
00315             The HAL status of all data processing is returned by the same function
00316             after finishing transfer.
00317        (+) No-Blocking mode: The communication is performed using Interrupts
00318            or DMA, These API's return the HAL status.
00319            The end of the data processing will be indicated through the
00320            dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00321            using DMA mode.
00322            The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00323            will be executed respectively at the end of the Transmit or Receive process
00324            The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected
00325
00326     (#) Blocking mode API's are :
00327         (+) HAL_SMARTCARD_Transmit()
00328         (+) HAL_SMARTCARD_Receive()
00329
00330     (#) Non-Blocking mode API's with Interrupt are :
00331         (+) HAL_SMARTCARD_Transmit_IT()
00332         (+) HAL_SMARTCARD_Receive_IT()
00333         (+) HAL_SMARTCARD_IRQHandler()
00334         (+) SMARTCARD_Transmit_IT()
00335         (+) SMARTCARD_Receive_IT()
00336
00337     (#) No-Blocking mode functions with DMA are :
00338         (+) HAL_SMARTCARD_Transmit_DMA()
00339         (+) HAL_SMARTCARD_Receive_DMA()
00340
00341     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00342         (+) HAL_SMARTCARD_TxCpltCallback()
00343         (+) HAL_SMARTCARD_RxCpltCallback()
00344         (+) HAL_SMARTCARD_ErrorCallback()
00345
00346 @endverbatim
00347   * @{
00348   */
00349
00350 /**
00351   * @brief Send an amount of data in blocking mode
00352   * @param hsc: SMARTCARD handle
00353   * @param pData: pointer to data buffer
00354   * @param Size: amount of data to be sent
00355   * @param Timeout: Timeout duration
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00359 {
00360   if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))
00361   {
00362     if((pData == NULL) || (Size == 0))
00363     {
00364       return  HAL_ERROR;
00365     }
00366
00367     /* Process Locked */
00368     __HAL_LOCK(hsc);
00369     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00370     /* Check if a non-blocking receive process is ongoing or not */
00371     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
00372     {
00373       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
00374     }
00375     else
00376     {
00377       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
00378     }
00379
00380     hsc->TxXferSize = Size;
00381     hsc->TxXferCount = Size;
00382     while(hsc->TxXferCount > 0)
00383     {
00384       hsc->TxXferCount--;
00385       if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
00386       {
00387         return HAL_TIMEOUT;
00388       }
00389       hsc->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00390     }
00391     if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
00392     {
00393       return HAL_TIMEOUT;
00394     }
00395     /* Check if a non-blocking receive Process is ongoing or not */
00396     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
00397     {
00398       hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
00399     }
00400     else
00401     {
00402       hsc->State = HAL_SMARTCARD_STATE_READY;
00403     }
00404     /* Process Unlocked */
00405     __HAL_UNLOCK(hsc);
00406
00407     return HAL_OK;
00408   }
00409   else
00410   {
00411     return HAL_BUSY;
00412   }
00413 }
00414
00415 /**
00416   * @brief Receive an amount of data in blocking mode
00417   * @param hsc: SMARTCARD handle
00418   * @param pData: pointer to data buffer
00419   * @param Size: amount of data to be received
00420   * @param Timeout: Timeout duration
00421   * @retval HAL status
00422   */
00423 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00424 {
00425   if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))
00426   {
00427     if((pData == NULL) || (Size == 0))
00428     {
00429       return  HAL_ERROR;
00430     }
00431
00432     /* Process Locked */
00433     __HAL_LOCK(hsc);
00434
00435     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00436     /* Check if a non-blocking transmit process is ongoing or not */
00437     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
00438     {
00439       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
00440     }
00441     else
00442     {
00443       hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
00444     }
00445
00446     hsc->RxXferSize = Size;
00447     hsc->RxXferCount = Size;
00448     /* Check the remain data to be received */
00449     while(hsc->RxXferCount > 0)
00450     {
00451       hsc->RxXferCount--;
00452       if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00453       {
00454         return HAL_TIMEOUT;
00455       }
00456       *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FF);
00457     }
00458
00459     /* Check if a non-blocking transmit process is ongoing or not */
00460     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
00461     {
00462       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
00463     }
00464     else
00465     {
00466       hsc->State = HAL_SMARTCARD_STATE_READY;
00467     }
00468
00469     /* Process Unlocked */
00470     __HAL_UNLOCK(hsc);
00471
00472     return HAL_OK;
00473   }
00474   else
00475   {
00476     return HAL_BUSY;
00477   }
00478 }
00479
00480 /**
00481   * @brief Send an amount of data in interrupt mode
00482   * @param hsc: SMARTCARD handle
00483   * @param pData: pointer to data buffer
00484   * @param Size: amount of data to be sent
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00488 {
00489   if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))
00490   {
00491     if((pData == NULL) || (Size == 0))
00492     {
00493       return HAL_ERROR;
00494     }
00495
00496     /* Process Locked */
00497     __HAL_LOCK(hsc);
00498
00499     hsc->pTxBuffPtr = pData;
00500     hsc->TxXferSize = Size;
00501     hsc->TxXferCount = Size;
00502
00503     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00504     /* Check if a receive process is ongoing or not */
00505     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
00506     {
00507       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
00508     }
00509     else
00510     {
00511       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
00512     }
00513
00514     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00515     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
00516
00517     /* Process Unlocked */
00518     __HAL_UNLOCK(hsc);
00519
00520     /* Enable the SMARTCARD Transmit Complete Interrupt */
00521     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
00522
00523     return HAL_OK;
00524   }
00525   else
00526   {
00527     return HAL_BUSY;
00528   }
00529 }
00530
00531 /**
00532   * @brief Receive an amount of data in interrupt mode
00533   * @param hsc: SMARTCARD handle
00534   * @param pData: pointer to data buffer
00535   * @param Size: amount of data to be received
00536   * @retval HAL status
00537   */
00538 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00539 {
00540   if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))
00541   {
00542     if((pData == NULL) || (Size == 0))
00543     {
00544       return HAL_ERROR;
00545     }
00546
00547     /* Process Locked */
00548     __HAL_LOCK(hsc);
00549
00550     hsc->pRxBuffPtr = pData;
00551     hsc->RxXferSize = Size;
00552     hsc->RxXferCount = Size;
00553
00554     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00555     /* Check if a transmit process is ongoing or not */
00556     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
00557     {
00558       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
00559     }
00560     else
00561     {
00562       hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
00563     }
00564
00565     /* Enable the SMARTCARD Parity Error Interrupt */
00566     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
00567
00568     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00569     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
00570
00571     /* Process Unlocked */
00572     __HAL_UNLOCK(hsc);
00573
00574     /* Enable the SMARTCARD Data Register not empty Interrupt */
00575     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
00576
00577     return HAL_OK;
00578   }
00579   else
00580   {
00581     return HAL_BUSY;
00582   }
00583 }
00584
00585 /**
00586   * @brief Send an amount of data in DMA mode
00587   * @param hsc: SMARTCARD handle
00588   * @param pData: pointer to data buffer
00589   * @param Size: amount of data to be sent
00590   * @retval HAL status
00591   */
00592 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00593 {
00594   uint32_t *tmp;
00595
00596   if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))
00597   {
00598     if((pData == NULL) || (Size == 0))
00599     {
00600       return HAL_ERROR;
00601     }
00602
00603     /* Process Locked */
00604     __HAL_LOCK(hsc);
00605
00606     hsc->pTxBuffPtr = pData;
00607     hsc->TxXferSize = Size;
00608     hsc->TxXferCount = Size;
00609
00610     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00611     /* Check if a receive process is ongoing or not */
00612     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
00613     {
00614       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
00615     }
00616     else
00617     {
00618       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
00619     }
00620
00621     /* Set the SMARTCARD DMA transfer complete callback */
00622     hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
00623
00624     /* Set the SMARTCARD error callback */
00625     hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
00626
00627     /* Enable the SMARTCARD transmit DMA Stream */
00628     tmp = (uint32_t*)&pData;
00629     HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size);
00630
00631         /* Clear the TC flag in the SR register by writing 0 to it */
00632     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC);
00633
00634     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00635        in the SMARTCARD associated USART CR3 register */
00636     hsc->Instance->CR3 |= USART_CR3_DMAT;
00637
00638     /* Process Unlocked */
00639     __HAL_UNLOCK(hsc);
00640
00641     return HAL_OK;
00642   }
00643   else
00644   {
00645     return HAL_BUSY;
00646   }
00647 }
00648
00649 /**
00650   * @brief Receive an amount of data in DMA mode
00651   * @param hsc: SMARTCARD handle
00652   * @param pData: pointer to data buffer
00653   * @param Size: amount of data to be received
00654   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
00655   *         the received data contain the parity bit (MSB position)
00656   * @retval HAL status
00657   */
00658 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00659 {
00660   uint32_t *tmp;
00661
00662   if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))
00663   {
00664     if((pData == NULL) || (Size == 0))
00665     {
00666       return HAL_ERROR;
00667     }
00668
00669     /* Process Locked */
00670     __HAL_LOCK(hsc);
00671
00672     hsc->pRxBuffPtr = pData;
00673     hsc->RxXferSize = Size;
00674
00675     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00676     /* Check if a transmit process is ongoing or not */
00677     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
00678     {
00679       hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
00680     }
00681     else
00682     {
00683       hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
00684     }
00685
00686     /* Set the SMARTCARD DMA transfer complete callback */
00687     hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
00688
00689     /* Set the SMARTCARD DMA error callback */
00690     hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
00691
00692     /* Enable the DMA Stream */
00693     tmp = (uint32_t*)&pData;
00694     HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size);
00695
00696     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00697     in the SMARTCARD associated USART CR3 register */
00698     hsc->Instance->CR3 |= USART_CR3_DMAR;
00699
00700     /* Process Unlocked */
00701     __HAL_UNLOCK(hsc);
00702
00703     return HAL_OK;
00704   }
00705   else
00706   {
00707     return HAL_BUSY;
00708   }
00709 }
00710
00711 /**
00712   * @brief SMARTCARD interrupt requests handling.
00713   * @param hsc: SMARTCARD handle
00714   * @retval None
00715   */
00716 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
00717 {
00718   /* SMARTCARD parity error interrupt occurred -------------------------------*/
00719   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE) != RESET))
00720   {
00721     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_PEF);
00722     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
00723     /* Set the SMARTCARD state ready to be able to start again the process */
00724     hsc->State = HAL_SMARTCARD_STATE_READY;
00725   }
00726
00727   /* SMARTCARD frame error interrupt occurred ---------------------------------*/
00728   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET))
00729   {
00730     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_FEF);
00731     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
00732     /* Set the SMARTCARD state ready to be able to start again the process */
00733     hsc->State = HAL_SMARTCARD_STATE_READY;
00734   }
00735
00736   /* SMARTCARD noise error interrupt occurred ---------------------------------*/
00737   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET))
00738   {
00739     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_NEF);
00740     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
00741     /* Set the SMARTCARD state ready to be able to start again the process */
00742     hsc->State = HAL_SMARTCARD_STATE_READY;
00743   }
00744
00745   /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
00746   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET))
00747   {
00748     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_OREF);
00749     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
00750     /* Set the SMARTCARD state ready to be able to start again the process */
00751     hsc->State = HAL_SMARTCARD_STATE_READY;
00752   }
00753
00754   /* SMARTCARD receiver timeout interrupt occurred ----------------------------*/
00755   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RTO) != RESET))
00756   {
00757     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_RTOF);
00758     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
00759     /* Set the SMARTCARD state ready to be able to start again the process */
00760     hsc->State = HAL_SMARTCARD_STATE_READY;
00761   }
00762
00763   /* Call SMARTCARD Error Call back function if need be ----------------------*/
00764   if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
00765   {
00766     HAL_SMARTCARD_ErrorCallback(hsc);
00767   }
00768
00769   /* SMARTCARD in mode Receiver ----------------------------------------------*/
00770   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE) != RESET))
00771   {
00772     SMARTCARD_Receive_IT(hsc);
00773     /* Clear RXNE interrupt flag */
00774     __HAL_SMARTCARD_SEND_REQ(hsc, SMARTCARD_RXDATA_FLUSH_REQUEST);
00775   }
00776
00777   /* SMARTCARD in mode Receiver, end of block interruption -------------------*/
00778   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_EOB) != RESET))
00779   {
00780     hsc->State = HAL_SMARTCARD_STATE_READY;
00781     HAL_SMARTCARD_RxCpltCallback(hsc);
00782     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
00783     * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
00784     __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_EOBF);
00785   }
00786
00787   /* SMARTCARD in mode Transmitter -------------------------------------------*/
00788   if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_TC) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC) != RESET))
00789   {
00790     SMARTCARD_Transmit_IT(hsc);
00791   }
00792 }
00793
00794 /**
00795   * @brief Tx Transfer completed callbacks
00796   * @param hsc: SMARTCARD handle
00797   * @retval None
00798   */
00799  __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
00800 {
00801   /* Prevent unused argument(s) compilation warning */
00802   UNUSED(hsc);
00803
00804   /* NOTE : This function Should not be modified, when the callback is needed,
00805             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
00806    */
00807 }
00808
00809 /**
00810   * @brief Rx Transfer completed callbacks
00811   * @param hsc: SMARTCARD handle
00812   * @retval None
00813   */
00814 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
00815 {
00816   /* Prevent unused argument(s) compilation warning */
00817   UNUSED(hsc);
00818
00819   /* NOTE : This function Should not be modified, when the callback is needed,
00820             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
00821    */
00822 }
00823
00824 /**
00825   * @brief SMARTCARD error callbacks
00826   * @param hsc: SMARTCARD handle
00827   * @retval None
00828   */
00829  __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
00830 {
00831   /* Prevent unused argument(s) compilation warning */
00832   UNUSED(hsc);
00833
00834   /* NOTE : This function Should not be modified, when the callback is needed,
00835             the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
00836    */
00837 }
00838
00839 /**
00840   * @}
00841   */
00842
00843 /** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions
00844   *  @brief   SMARTCARD State functions
00845   *
00846 @verbatim
00847  ===============================================================================
00848                 ##### Peripheral State and Errors functions #####
00849  ===============================================================================
00850     [..]
00851     This subsection provides a set of functions allowing to initialize the SMARTCARD.
00852      (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral
00853      (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral
00854      (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
00855
00856 @endverbatim
00857   * @{
00858   */
00859
00860
00861 /**
00862   * @brief return the SMARTCARD state
00863   * @param hsc: SMARTCARD handle
00864   * @retval HAL state
00865   */
00866 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
00867 {
00868   return hsc->State;
00869 }
00870
00871 /**
00872   * @brief  Return the SMARTCARD error code
00873   * @param  hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
00874   *              the configuration information for the specified SMARTCARD.
00875   * @retval SMARTCARD Error Code
00876   */
00877 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
00878 {
00879   return hsc->ErrorCode;
00880 }
00881
00882 /**
00883   * @}
00884   */
00885
00886 /**
00887   * @brief Send an amount of data in non blocking mode
00888   * @param hsc: SMARTCARD handle.
00889   *         Function called under interruption only, once
00890   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
00891   * @retval HAL status
00892   */
00893 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
00894 {
00895   if((hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
00896   {
00897     if(hsc->TxXferCount == 0)
00898     {
00899       /* Disable the SMARTCARD Transmit Complete Interrupt */
00900       __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC);
00901
00902       /* Check if a receive Process is ongoing or not */
00903       if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
00904       {
00905         hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
00906       }
00907       else
00908       {
00909         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00910         __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
00911
00912         hsc->State = HAL_SMARTCARD_STATE_READY;
00913       }
00914
00915       HAL_SMARTCARD_TxCpltCallback(hsc);
00916
00917       return HAL_OK;
00918     }
00919     else
00920     {
00921       hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFF);
00922       hsc->TxXferCount--;
00923
00924       return HAL_OK;
00925     }
00926   }
00927   else
00928   {
00929     return HAL_BUSY;
00930   }
00931 }
00932
00933 /**
00934   * @brief Receive an amount of data in non blocking mode
00935   * @param hsc: SMARTCARD handle.
00936   *         Function called under interruption only, once
00937   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
00938   * @retval HAL status
00939   */
00940 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
00941 {
00942   if((hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
00943   {
00944     *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFF);
00945
00946     if(--hsc->RxXferCount == 0)
00947     {
00948       while(HAL_IS_BIT_SET(hsc->Instance->ISR, SMARTCARD_FLAG_RXNE))
00949       {
00950       }
00951       __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
00952
00953       /* Check if a transmit Process is ongoing or not */
00954       if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
00955       {
00956         hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
00957       }
00958       else
00959       {
00960         /* Disable the SMARTCARD Parity Error Interrupt */
00961         __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
00962
00963         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00964         __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
00965
00966         hsc->State = HAL_SMARTCARD_STATE_READY;
00967       }
00968
00969       HAL_SMARTCARD_RxCpltCallback(hsc);
00970
00971       return HAL_OK;
00972     }
00973     return HAL_OK;
00974   }
00975   else
00976   {
00977     return HAL_BUSY;
00978   }
00979 }
00980
00981 /**
00982   * @brief Configure the SMARTCARD associated USART peripheral
00983   * @param hsc: SMARTCARD handle
00984   * @retval None
00985   */
00986 static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
00987 {
00988   uint32_t tmpreg = 0x00000000;
00989   uint32_t clocksource = 0x00000000;
00990
00991   /* Check the parameters */
00992   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00993   assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
00994   assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
00995   assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
00996   assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
00997   assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
00998   assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
00999   assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
01000   assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
01001   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling));
01002   assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState));
01003   assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable));
01004   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount));
01005
01006   /*-------------------------- USART CR1 Configuration -----------------------*/
01007   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
01008    * Oversampling is forced to 16 (OVER8 = 0).
01009    * Configure the Parity and Mode:
01010    *  set PS bit according to hsc->Init.Parity value
01011    *  set TE and RE bits according to hsc->Init.Mode value */
01012   tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode;
01013   /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
01014      the bidirectional line to detect a NACK signal in case of parity error.
01015      Therefore, the receiver block must be enabled as well (RE bit must be set). */
01016   if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE))
01017   {
01018     tmpreg |= USART_CR1_RE;
01019   }
01020   tmpreg |= (uint32_t) hsc->Init.WordLength;
01021   MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);
01022
01023   /*-------------------------- USART CR2 Configuration -----------------------*/
01024   /* Stop bits are forced to 1.5 (STOP = 11) */
01025   tmpreg = hsc->Init.StopBits;
01026   /* Synchronous mode is activated by default */
01027   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity;
01028   tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit;
01029   tmpreg |= (uint32_t) hsc->Init.TimeOutEnable;
01030   MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg);
01031
01032   /*-------------------------- USART CR3 Configuration -----------------------*/
01033   /* Configure
01034    * - one-bit sampling method versus three samples' majority rule
01035    *   according to hsc->Init.OneBitSampling
01036    * - NACK transmission in case of parity error according
01037    *   to hsc->Init.NACKEnable
01038    * - autoretry counter according to hsc->Init.AutoRetryCount     */
01039   tmpreg =  (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState;
01040   tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
01041   MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
01042
01043   /*-------------------------- USART GTPR Configuration ----------------------*/
01044   tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
01045   MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
01046
01047   /*-------------------------- USART RTOR Configuration ----------------------*/
01048   tmpreg =   (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
01049   if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
01050   {
01051     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));
01052     tmpreg |=  (uint32_t) hsc->Init.TimeOutValue;
01053   }
01054   MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
01055
01056   /*-------------------------- USART BRR Configuration -----------------------*/
01057   SMARTCARD_GETCLOCKSOURCE(hsc, clocksource);
01058   switch (clocksource)
01059   {
01060   case SMARTCARD_CLOCKSOURCE_PCLK1:
01061     hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsc->Init.BaudRate);
01062     break;
01063   case SMARTCARD_CLOCKSOURCE_PCLK2:
01064     hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsc->Init.BaudRate);
01065     break;
01066   case SMARTCARD_CLOCKSOURCE_HSI:
01067     hsc->Instance->BRR = (uint16_t)(HSI_VALUE / hsc->Init.BaudRate);
01068     break;
01069   case SMARTCARD_CLOCKSOURCE_SYSCLK:
01070     hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsc->Init.BaudRate);
01071     break;
01072   case SMARTCARD_CLOCKSOURCE_LSE:
01073     hsc->Instance->BRR = (uint16_t)(LSE_VALUE / hsc->Init.BaudRate);
01074     break;
01075   default:
01076     break;
01077   }
01078 }
01079
01080 /**
01081   * @brief Check the SMARTCARD Idle State
01082   * @param hsc: SMARTCARD handle
01083   * @retval HAL status
01084   */
01085 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc)
01086 {
01087
01088   /* Initialize the SMARTCARD ErrorCode */
01089   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01090
01091   /* Check if the Transmitter is enabled */
01092   if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01093   {
01094     /* Wait until TEACK flag is set */
01095     if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
01096     {
01097       return HAL_TIMEOUT;
01098     }
01099   }
01100   /* Check if the Receiver is enabled */
01101   if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01102   {
01103     /* Wait until REACK flag is set */
01104     if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
01105     {
01106       return HAL_TIMEOUT;
01107     }
01108   }
01109
01110   /* Process Unlocked */
01111   __HAL_UNLOCK(hsc);
01112
01113   /* Initialize the SMARTCARD state*/
01114   hsc->State= HAL_SMARTCARD_STATE_READY;
01115
01116   return HAL_OK;
01117 }
01118
01119 /**
01120   * @brief Configure the SMARTCARD associated USART peripheral advanced features
01121   * @param hsc: SMARTCARD handle
01122   * @retval None
01123   */
01124 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc)
01125 {
01126   /* Check whether the set of advanced features to configure is properly set */
01127   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsc->AdvancedInit.AdvFeatureInit));
01128
01129   /* if required, configure TX pin active level inversion */
01130   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
01131   {
01132     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsc->AdvancedInit.TxPinLevelInvert));
01133     MODIFY_REG(hsc->Instance->CR2, USART_CR2_TXINV, hsc->AdvancedInit.TxPinLevelInvert);
01134   }
01135
01136   /* if required, configure RX pin active level inversion */
01137   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
01138   {
01139     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsc->AdvancedInit.RxPinLevelInvert));
01140     MODIFY_REG(hsc->Instance->CR2, USART_CR2_RXINV, hsc->AdvancedInit.RxPinLevelInvert);
01141   }
01142
01143   /* if required, configure data inversion */
01144   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
01145   {
01146     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsc->AdvancedInit.DataInvert));
01147     MODIFY_REG(hsc->Instance->CR2, USART_CR2_DATAINV, hsc->AdvancedInit.DataInvert);
01148   }
01149
01150   /* if required, configure RX/TX pins swap */
01151   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
01152   {
01153     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsc->AdvancedInit.Swap));
01154     MODIFY_REG(hsc->Instance->CR2, USART_CR2_SWAP, hsc->AdvancedInit.Swap);
01155   }
01156
01157   /* if required, configure RX overrun detection disabling */
01158   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
01159   {
01160     assert_param(IS_SMARTCARD_OVERRUN(hsc->AdvancedInit.OverrunDisable));
01161     MODIFY_REG(hsc->Instance->CR3, USART_CR3_OVRDIS, hsc->AdvancedInit.OverrunDisable);
01162   }
01163
01164   /* if required, configure DMA disabling on reception error */
01165   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
01166   {
01167     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsc->AdvancedInit.DMADisableonRxError));
01168     MODIFY_REG(hsc->Instance->CR3, USART_CR3_DDRE, hsc->AdvancedInit.DMADisableonRxError);
01169   }
01170
01171   /* if required, configure MSB first on communication line */
01172   if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
01173   {
01174     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsc->AdvancedInit.MSBFirst));
01175     MODIFY_REG(hsc->Instance->CR2, USART_CR2_MSBFIRST, hsc->AdvancedInit.MSBFirst);
01176   }
01177 }
01178
01179 /**
01180   * @brief  This function handles SMARTCARD Communication Timeout.
01181   * @param  hsc: SMARTCARD handle
01182   * @param  Flag: specifies the SMARTCARD flag to check.
01183   * @param  Status: The new Flag status (SET or RESET).
01184   * @param  Timeout: Timeout duration
01185   * @retval HAL status
01186   */
01187 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01188 {
01189   uint32_t tickstart = 0x00;
01190
01191   /* Get tick */
01192   tickstart = HAL_GetTick();
01193
01194   /* Wait until flag is set */
01195   if(Status == RESET)
01196   {
01197     while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
01198     {
01199       /* Check for the Timeout */
01200       if(Timeout != HAL_MAX_DELAY)
01201       {
01202         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01203         {
01204           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01205           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
01206           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
01207           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
01208           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
01209
01210           hsc->State= HAL_SMARTCARD_STATE_READY;
01211
01212           /* Process Unlocked */
01213           __HAL_UNLOCK(hsc);
01214
01215           return HAL_TIMEOUT;
01216         }
01217       }
01218     }
01219   }
01220   else
01221   {
01222     while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
01223     {
01224       /* Check for the Timeout */
01225       if(Timeout != HAL_MAX_DELAY)
01226       {
01227         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01228         {
01229           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01230           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
01231           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
01232           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
01233           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
01234
01235           hsc->State= HAL_SMARTCARD_STATE_READY;
01236
01237           /* Process Unlocked */
01238           __HAL_UNLOCK(hsc);
01239
01240           return HAL_TIMEOUT;
01241         }
01242       }
01243     }
01244   }
01245   return HAL_OK;
01246 }
01247
01248 /**
01249   * @brief DMA SMARTCARD transmit process complete callback
01250   * @param hdma: DMA handle
01251   * @retval None
01252   */
01253 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01254 {
01255   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01256   hsc->TxXferCount = 0;
01257
01258   /* Disable the DMA transfer for transmit request by setting the DMAT bit
01259   in the SMARTCARD associated USART CR3 register */
01260   hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
01261
01262   /* Wait for SMARTCARD TC Flag */
01263   if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, HAL_SMARTCARD_TXDMA_TIMEOUTVALUE) != HAL_OK)
01264   {
01265     /* Timeout Occurred */
01266     hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
01267     HAL_SMARTCARD_ErrorCallback(hsc);
01268   }
01269   else
01270   {
01271     /* No Timeout */
01272     /* Check if a receive Process is ongoing or not */
01273     if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
01274     {
01275       hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
01276     }
01277     else
01278     {
01279       hsc->State = HAL_SMARTCARD_STATE_READY;
01280     }
01281     HAL_SMARTCARD_TxCpltCallback(hsc);
01282   }
01283 }
01284
01285 /**
01286   * @brief DMA SMARTCARD receive process complete callback
01287   * @param hdma: DMA handle
01288   * @retval None
01289   */
01290 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01291 {
01292   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01293   hsc->RxXferCount = 0;
01294
01295   /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01296      in the SMARTCARD associated USART CR3 register */
01297   hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
01298
01299   /* Check if a transmit Process is ongoing or not */
01300   if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
01301   {
01302     hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
01303   }
01304   else
01305   {
01306     hsc->State = HAL_SMARTCARD_STATE_READY;
01307   }
01308
01309   HAL_SMARTCARD_RxCpltCallback(hsc);
01310 }
01311
01312 /**
01313   * @brief DMA SMARTCARD communication error callback
01314   * @param hdma: DMA handle
01315   * @retval None
01316   */
01317 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
01318 {
01319   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01320   hsc->RxXferCount = 0;
01321   hsc->TxXferCount = 0;
01322   hsc->State= HAL_SMARTCARD_STATE_READY;
01323   hsc->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
01324   HAL_SMARTCARD_ErrorCallback(hsc);
01325 }
01326 /**
01327   * @}
01328   */
01329
01330 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
01331 /**
01332   * @}
01333   */
01334
01335 /**
01336   * @}
01337   */
01338
01339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard.h Source File

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stm32f7xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SMARTCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SMARTCARD_H
00040 #define __STM32F7xx_HAL_SMARTCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SMARTCARD Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((hsc->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
00073
00074   uint32_t StopBits;                  /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
00075                                            Only 1.5 stop bits are authorized in SmartCard mode. */
00076
00077   uint32_t Parity;                    /*!< Specifies the parity mode.
00078                                            This parameter can be a value of @ref SMARTCARD_Parity
00079                                            @note The parity is enabled by default (PCE is forced to 1).
00080                                                  Since the WordLength is forced to 8 bits + parity, M is
00081                                                  forced to 1 and the parity bit is the 9th bit. */
00082
00083   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00084                                            This parameter can be a value of @ref SMARTCARD_Mode */
00085
00086   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00087                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00088
00089   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00090                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00091
00092   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00093                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00094                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00095
00096   uint32_t OneBitSampling;            /*!< Specifies  whether a single sample or three samples' majority vote is selected.
00097                                            Selecting the single sample method increases the receiver tolerance to clock
00098                                            deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling */
00099
00100   uint32_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler */
00101
00102   uint32_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time */
00103
00104   uint32_t NACKState;                  /*!< Specifies whether the SmartCard NACK transmission is enabled
00105                                             in case of parity error.
00106                                             This parameter can be a value of @ref SMARTCARD_NACK_State */
00107
00108   uint32_t TimeOutEnable;              /*!< Specifies whether the receiver timeout is enabled.
00109                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00110
00111   uint32_t TimeOutValue;               /*!< Specifies the receiver time out value in number of baud blocks:
00112                                             it is used to implement the Character Wait Time (CWT) and
00113                                             Block Wait Time (BWT). It is coded over 24 bits. */
00114
00115   uint32_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00116                                             This parameter can be any value from 0x0 to 0xFF */
00117
00118   uint32_t AutoRetryCount;              /*!< Specifies the SmartCard auto-retry count (number of retries in
00119                                              receive and transmit mode). When set to 0, retransmission is
00120                                              disabled. Otherwise, its maximum value is 7 (before signalling
00121                                              an error) */
00122
00123 }SMARTCARD_InitTypeDef;
00124
00125 /**
00126   * @brief  SMARTCARD advanced features initalization structure definition
00127   */
00128 typedef struct
00129 {
00130   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00131                                            advanced features may be initialized at the same time. This parameter
00132                                            can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
00133
00134   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00135                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00136
00137   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00138                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00139
00140   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00141                                            vs negative/inverted logic).
00142                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00143
00144   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00145                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00146
00147   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00148                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00149
00150   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00151                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00152
00153   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00154                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00155 }SMARTCARD_AdvFeatureInitTypeDef;
00156
00157 /**
00158   * @brief HAL State structures definition
00159   */
00160 typedef enum
00161 {
00162   HAL_SMARTCARD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
00163   HAL_SMARTCARD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
00164   HAL_SMARTCARD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
00165   HAL_SMARTCARD_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
00166   HAL_SMARTCARD_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
00167   HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00168   HAL_SMARTCARD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
00169   HAL_SMARTCARD_STATE_ERROR             = 0x04     /*!< Error */
00170 }HAL_SMARTCARD_StateTypeDef;
00171
00172
00173 /**
00174   * @brief  SMARTCARD clock sources definition
00175   */
00176 typedef enum
00177 {
00178   SMARTCARD_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source  */
00179   SMARTCARD_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source  */
00180   SMARTCARD_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source    */
00181   SMARTCARD_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source */
00182   SMARTCARD_CLOCKSOURCE_LSE        = 0x08     /*!< LSE clock source    */
00183 }SMARTCARD_ClockSourceTypeDef;
00184
00185 /**
00186   * @brief  SMARTCARD handle Structure definition
00187   */
00188 typedef struct
00189 {
00190   USART_TypeDef                       *Instance;        /* USART registers base address                          */
00191
00192   SMARTCARD_InitTypeDef               Init;             /* SmartCard communication parameters                    */
00193
00194   SMARTCARD_AdvFeatureInitTypeDef     AdvancedInit;     /* SmartCard advanced features initialization parameters */
00195
00196   uint8_t                             *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer            */
00197
00198   uint16_t                            TxXferSize;       /* SmartCard Tx Transfer size                         */
00199
00200   uint16_t                            TxXferCount;      /* SmartCard Tx Transfer Counter                      */
00201
00202   uint8_t                             *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer        */
00203
00204   uint16_t                            RxXferSize;       /* SmartCard Rx Transfer size                     */
00205
00206   uint16_t                            RxXferCount;      /* SmartCard Rx Transfer Counter                  */
00207
00208   DMA_HandleTypeDef                   *hdmatx;          /* SmartCard Tx DMA Handle parameters             */
00209
00210   DMA_HandleTypeDef                   *hdmarx;          /* SmartCard Rx DMA Handle parameters             */
00211
00212   HAL_LockTypeDef                     Lock;             /* Locking object                                 */
00213
00214   __IO HAL_SMARTCARD_StateTypeDef     State;            /* SmartCard communication state                  */
00215
00216   __IO uint32_t                       ErrorCode;        /* SmartCard Error code                           */
00217
00218 }SMARTCARD_HandleTypeDef;
00219
00220 /**
00221   * @}
00222   */
00223 /* Exported constants --------------------------------------------------------*/
00224 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
00225   * @{
00226   */
00227 /** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
00228   * @brief    SMARTCARD Error Code
00229   * @{
00230   */
00231 #define HAL_SMARTCARD_ERROR_NONE      ((uint32_t)0x00)    /*!< No error                */
00232 #define HAL_SMARTCARD_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error            */
00233 #define HAL_SMARTCARD_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error             */
00234 #define HAL_SMARTCARD_ERROR_FE        ((uint32_t)0x04)    /*!< frame error             */
00235 #define HAL_SMARTCARD_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error           */
00236 #define HAL_SMARTCARD_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error      */
00237 #define HAL_SMARTCARD_ERROR_RTO       ((uint32_t)0x20)    /*!< Receiver TimeOut error  */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00243   * @{
00244   */
00245 #define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00251   * @{
00252   */
00253 #define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP))
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00259   * @{
00260   */
00261 #define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00262 #define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup SMARTCARD_Mode SMARTCARD Mode
00268   * @{
00269   */
00270 #define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
00271 #define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
00272 #define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00278   * @{
00279   */
00280 #define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x0000)
00281 #define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase
00287   * @{
00288   */
00289 #define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x0000)
00290 #define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
00296   * @{
00297   */
00298 #define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x0000)
00299 #define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling
00305   * @{
00306   */
00307 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE   ((uint32_t)0x0000)
00308 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE    ((uint32_t)USART_CR3_ONEBIT)
00309 /**
00310   * @}
00311   */
00312
00313
00314 /** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State
00315   * @{
00316   */
00317 #define SMARTCARD_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)
00318 #define SMARTCARD_NACK_DISABLE          ((uint32_t)0x0000)
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00324   * @{
00325   */
00326 #define SMARTCARD_TIMEOUT_DISABLE      ((uint32_t)0x00000000)
00327 #define SMARTCARD_TIMEOUT_ENABLE       ((uint32_t)USART_CR2_RTOEN)
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests
00333   * @{
00334   */
00335
00336 #define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
00337 #define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type
00344   * @{
00345   */
00346 #define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)
00347 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)
00348 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)
00349 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)
00350 #define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)
00351 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)
00352 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)
00353 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv
00359   * @{
00360   */
00361 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE   ((uint32_t)0x00000000)
00362 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE    ((uint32_t)USART_CR2_TXINV)
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv
00368   * @{
00369   */
00370 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE   ((uint32_t)0x00000000)
00371 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE    ((uint32_t)USART_CR2_RXINV)
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv
00377   * @{
00378   */
00379 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000)
00380 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap
00386   * @{
00387   */
00388 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000)
00389 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable
00395   * @{
00396   */
00397 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000)
00398 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error
00404   * @{
00405   */
00406 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR       ((uint32_t)0x00000000)
00407 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR      ((uint32_t)USART_CR3_DDRE)
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First
00413   * @{
00414   */
00415 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000)
00416 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup SmartCard_Flags SMARTCARD Flags
00422   *        Elements values convention: 0xXXXX
00423   *           - 0xXXXX  : Flag mask in the ISR register
00424   * @{
00425   */
00426 #define SMARTCARD_FLAG_REACK                     ((uint32_t)0x00400000)
00427 #define SMARTCARD_FLAG_TEACK                     ((uint32_t)0x00200000)
00428 #define SMARTCARD_FLAG_BUSY                      ((uint32_t)0x00010000)
00429 #define SMARTCARD_FLAG_EOBF                      ((uint32_t)0x00001000)
00430 #define SMARTCARD_FLAG_RTOF                      ((uint32_t)0x00000800)
00431 #define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080)
00432 #define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040)
00433 #define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020)
00434 #define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010)
00435 #define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008)
00436 #define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004)
00437 #define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002)
00438 #define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001)
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition
00444   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00445   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00446   *           - XX  : Interrupt source register (2bits)
00447   *                 - 01: CR1 register
00448   *                 - 10: CR2 register
00449   *                 - 11: CR3 register
00450   *           - ZZZZ  : Flag position in the ISR register(4bits)
00451   * @{
00452   */
00453
00454 #define SMARTCARD_IT_PE                          ((uint16_t)0x0028)
00455 #define SMARTCARD_IT_TXE                         ((uint16_t)0x0727)
00456 #define SMARTCARD_IT_TC                          ((uint16_t)0x0626)
00457 #define SMARTCARD_IT_RXNE                        ((uint16_t)0x0525)
00458 #define SMARTCARD_IT_IDLE                        ((uint16_t)0x0424)
00459 #define SMARTCARD_IT_ERR                         ((uint16_t)0x0060)
00460 #define SMARTCARD_IT_ORE                         ((uint16_t)0x0300)
00461 #define SMARTCARD_IT_NE                          ((uint16_t)0x0200)
00462 #define SMARTCARD_IT_FE                          ((uint16_t)0x0100)
00463
00464 #define SMARTCARD_IT_EOB                         ((uint16_t)0x0C3B)
00465 #define SMARTCARD_IT_RTO                         ((uint16_t)0x0B3A)
00466 /**
00467   * @}
00468   */
00469
00470
00471 /** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags
00472   * @{
00473   */
00474 #define SMARTCARD_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */
00475 #define SMARTCARD_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */
00476 #define SMARTCARD_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */
00477 #define SMARTCARD_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */
00478 #define SMARTCARD_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< Idle line detected clear Flag */
00479 #define SMARTCARD_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00480 #define SMARTCARD_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */
00481 #define SMARTCARD_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */
00482 /**
00483   * @}
00484   */
00485
00486 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00487   * @{
00488   */
00489 #define SMARTCARD_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */
00490 #define SMARTCARD_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00491 /**
00492   * @}
00493   */
00494
00495
00496 /** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS
00497   * @{
00498   */
00499 #define SMARTCARD_CR3_SCARCNT_LSB_POS            ((uint32_t) 17)
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS
00505   * @{
00506   */
00507 #define SMARTCARD_GTPR_GT_LSB_POS            ((uint32_t) 8)
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS
00513   * @{
00514   */
00515 #define SMARTCARD_RTOR_BLEN_LSB_POS          ((uint32_t) 24)
00516 /**
00517   * @}
00518   */
00519
00520 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask
00521   * @{
00522   */
00523 #define SMARTCARD_IT_MASK  ((uint16_t)0x001F)
00524 /**
00525   * @}
00526   */
00527
00528 /**
00529   * @}
00530   */
00531
00532 /* Exported macro ------------------------------------------------------------*/
00533 /** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
00534   * @{
00535   */
00536
00537 /** @brief Reset SMARTCARD handle state
00538   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00539   *         The Handle Instance which can be USART1 or USART2
00540   * @retval None
00541   */
00542 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
00543
00544 /** @brief  Flush the Smartcard DR register
00545   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00546   *         The Handle Instance which can be USART1 or USART2.
00547   * @retval None
00548   */
00549 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))
00550
00551 /** @brief  Checks whether the specified Smartcard flag is set or not.
00552   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00553   *         The Handle Instance which can be USART1 or USART2.
00554   * @param  __FLAG__: specifies the flag to check.
00555   *        This parameter can be one of the following values:
00556   *            @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
00557   *            @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
00558   *            @arg SMARTCARD_FLAG_BUSY:  Busy flag
00559   *            @arg SMARTCARD_FLAG_EOBF:  End of block flag
00560   *            @arg SMARTCARD_FLAG_RTOF:  Receiver timeout flag
00561   *            @arg SMARTCARD_FLAG_TXE:   Transmit data register empty flag
00562   *            @arg SMARTCARD_FLAG_TC:    Transmission Complete flag
00563   *            @arg SMARTCARD_FLAG_RXNE:  Receive data register not empty flag
00564   *            @arg SMARTCARD_FLAG_ORE:   OverRun Error flag
00565   *            @arg SMARTCARD_FLAG_NE:    Noise Error flag
00566   *            @arg SMARTCARD_FLAG_FE:    Framing Error flag
00567   *            @arg SMARTCARD_FLAG_PE:    Parity Error flag
00568   * @retval The new state of __FLAG__ (TRUE or FALSE).
00569   */
00570 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00571
00572 /** @brief  Enables the specified SmartCard interrupt.
00573   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00574   *         The Handle Instance which can be USART1 or USART2.
00575   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
00576   *          This parameter can be one of the following values:
00577   *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt
00578   *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
00579   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00580   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00581   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00582   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00583   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00584   * @retval None
00585   */
00586 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00587                                                         ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00588                                                         ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00589 /** @brief  Disables the specified SmartCard interrupt.
00590   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00591   *         The Handle Instance which can be USART1 or USART2.
00592   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
00593   *          This parameter can be one of the following values:
00594   *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt
00595   *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
00596   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00597   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00598   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00599   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00600   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00601   * @retval None
00602   */
00603 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00604                                                         ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00605                                                         ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00606
00607 /** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
00608   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00609   *         The Handle Instance which can be USART1 or USART2.
00610   * @param  __IT__: specifies the SMARTCARD interrupt to check.
00611   *          This parameter can be one of the following values:
00612   *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt
00613   *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
00614   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00615   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00616   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00617   *            @arg SMARTCARD_IT_ORE:  OverRun Error interrupt
00618   *            @arg SMARTCARD_IT_NE:   Noise Error interrupt
00619   *            @arg SMARTCARD_IT_FE:   Framing Error interrupt
00620   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00621   * @retval The new state of __IT__ (TRUE or FALSE).
00622   */
00623 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00624
00625 /** @brief  Checks whether the specified SmartCard interrupt interrupt source is enabled.
00626   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00627   *         The Handle Instance which can be USART1 or USART2.
00628   * @param  __IT__: specifies the SMARTCARD interrupt source to check.
00629   *          This parameter can be one of the following values:
00630   *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt
00631   *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
00632   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00633   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00634   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00635   *            @arg SMARTCARD_IT_ORE:  OverRun Error interrupt
00636   *            @arg SMARTCARD_IT_NE:   Noise Error interrupt
00637   *            @arg SMARTCARD_IT_FE:   Framing Error interrupt
00638   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00639   * @retval The new state of __IT__ (TRUE or FALSE).
00640   */
00641 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
00642                                                                (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
00643                                                                (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
00644
00645
00646 /** @brief  Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00647   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00648   *         The Handle Instance which can be USART1 or USART2.
00649   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00650   *                       to clear the corresponding interrupt
00651   *          This parameter can be one of the following values:
00652   *            @arg USART_CLEAR_PEF: Parity Error Clear Flag
00653   *            @arg USART_CLEAR_FEF: Framing Error Clear Flag
00654   *            @arg USART_CLEAR_NEF: Noise detected Clear Flag
00655   *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag
00656   *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
00657   *            @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
00658   *            @arg USART_CLEAR_EOBF: End Of Block Clear Flag
00659   * @retval None
00660   */
00661 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00662
00663 /** @brief  Set a specific SMARTCARD request flag.
00664   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00665   *         The Handle Instance which can be USART1 or USART2.
00666   * @param  __REQ__: specifies the request flag to set
00667   *          This parameter can be one of the following values:
00668   *            @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
00669   *            @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
00670   *
00671   * @retval None
00672   */
00673 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
00674
00675 /** @brief  Enable the USART associated to the SMARTCARD Handle
00676   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00677   *         The Handle Instance which can be USART1 or USART2.
00678   * @retval None
00679   */
00680 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00681
00682 /** @brief  Disable the USART associated to the SMARTCARD Handle
00683   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00684   *         The Handle Instance which can be USART1 or USART2.
00685   * @retval None
00686   */
00687 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00688
00689 /** @brief  Macros to enable or disable the SmartCard DMA request.
00690   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00691   *         The Handle Instance which can be USART1 or USART2.
00692   * @param  __REQUEST__: specifies the SmartCard DMA request.
00693   *          This parameter can be one of the following values:
00694   *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
00695   *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
00696   */
00697 #define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
00698 #define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
00699 /**
00700   * @}
00701   */
00702
00703 /* Include SMARTCARD HAL Extension module */
00704 #include "stm32f7xx_hal_smartcard_ex.h"
00705 /* Exported functions --------------------------------------------------------*/
00706 /** @addtogroup SMARTCARD_Exported_Functions
00707   * @{
00708   */
00709
00710 /** @addtogroup SMARTCARD_Exported_Functions_Group1
00711   * @{
00712   */
00713 /* Initialization/de-initialization functions  **********************************/
00714 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
00715 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
00716 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
00717 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
00718 /**
00719   * @}
00720   */
00721
00722 /** @addtogroup SMARTCARD_Exported_Functions_Group2
00723   * @{
00724   */
00725 /* IO operation functions *******************************************************/
00726 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00727 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00728 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00729 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00730 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00731 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00732 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
00733 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00734 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00735 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
00736 /**
00737   * @}
00738   */
00739
00740 /** @addtogroup SMARTCARD_Exported_Functions_Group3
00741   * @{
00742   */
00743 /* Peripheral State functions  **************************************************/
00744 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
00745 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
00746
00747 /**
00748   * @}
00749   */
00750
00751 /**
00752   * @}
00753   */
00754 /* Private types -------------------------------------------------------------*/
00755 /* Private variables ---------------------------------------------------------*/
00756 /* Private constants ---------------------------------------------------------*/
00757 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00758   * @{
00759   */
00760
00761 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00762 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
00763 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00764                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00765 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
00766 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00767 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
00768 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
00769                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
00770 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
00771                                                   ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
00772 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
00773                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
00774 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
00775                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
00776 #define IS_SMARTCARD_ADVFEATURE_INIT(INIT)           ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
00777                                                             SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
00778                                                             SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
00779                                                             SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
00780                                                             SMARTCARD_ADVFEATURE_SWAP_INIT | \
00781                                                             SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
00782                                                             SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT   | \
00783                                                             SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
00784 #define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
00785                                          ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
00786 #define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
00787                                          ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
00788 #define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
00789                                              ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
00790 #define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
00791                                        ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
00792 #define IS_SMARTCARD_OVERRUN(OVERRUN)         (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
00793                                           ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
00794 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
00795                                                    ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
00796 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
00797 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
00798 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)
00799 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)
00800 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
00801                                                ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
00802 #define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
00803                                                ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))
00804
00805
00806 /**
00807   * @}
00808   */
00809
00810 /* Private functions ---------------------------------------------------------*/
00811 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
00812   * @{
00813   */
00814
00815 /**
00816   * @}
00817   */
00818
00819 /**
00820   * @}
00821   */
00822
00823 /**
00824   * @}
00825   */
00826
00827 #ifdef __cplusplus
00828 }
00829 #endif
00830
00831 #endif /* __STM32F7xx_HAL_SMARTCARD_H */
00832
00833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard_ex.c Source File

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stm32f7xx_hal_smartcard_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SMARTCARD HAL module driver.
00008   *
00009   *          This file provides extended firmware functions to manage the following
00010   *          functionalities of the SmartCard.
00011   *           + Initialization and de-initialization functions
00012   *           + Peripheral Control functions
00013   @verbatim
00014  ===============================================================================
00015                         ##### How to use this driver #####
00016  ===============================================================================
00017     [..]
00018     The Extended SMARTCARD HAL driver can be used as follow:
00019
00020     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00021         then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
00022         auto-retry counter,...) in the hsc AdvancedInit structure.
00023
00024   @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054
00055 /* Includes ------------------------------------------------------------------*/
00056 #include "stm32f7xx_hal.h"
00057
00058 /** @addtogroup STM32F7xx_HAL_Driver
00059   * @{
00060   */
00061
00062 /** @defgroup SMARTCARDEx SMARTCARDEx
00063   * @brief SMARTCARD Extended HAL module driver
00064   * @{
00065   */
00066 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macro -------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /* Private functions ---------------------------------------------------------*/
00074
00075 /** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions
00080   * @brief    Extended control functions
00081   *
00082 @verbatim
00083  ===============================================================================
00084                       ##### Peripheral Control functions #####
00085  ===============================================================================
00086     [..]
00087     This subsection provides a set of functions allowing to initialize the SMARTCARD.
00088      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00089      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00090      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00091      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief Update on the fly the SMARTCARD block length in RTOR register
00099   * @param hsc: SMARTCARD handle
00100   * @param BlockLength: SMARTCARD block length (8-bit long at most)
00101   * @retval None
00102   */
00103 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
00104 {
00105   MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
00106 }
00107
00108 /**
00109   * @brief Update on the fly the receiver timeout value in RTOR register
00110   * @param hsc: SMARTCARD handle
00111   * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
00112   *                     value must be less or equal to 0x0FFFFFFFF.
00113   * @retval None
00114   */
00115 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
00116 {
00117   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));
00118   MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00119 }
00120
00121 /**
00122   * @brief Enable the SMARTCARD receiver timeout feature
00123   * @param hsc: SMARTCARD handle
00124   * @retval HAL status
00125   */
00126 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
00127 {
00128   /* Process Locked */
00129   __HAL_LOCK(hsc);
00130
00131   hsc->State = HAL_SMARTCARD_STATE_BUSY;
00132
00133   /* Set the USART RTOEN bit */
00134   hsc->Instance->CR2 |= USART_CR2_RTOEN;
00135
00136   hsc->State = HAL_SMARTCARD_STATE_READY;
00137
00138   /* Process Unlocked */
00139   __HAL_UNLOCK(hsc);
00140
00141   return HAL_OK;
00142 }
00143
00144 /**
00145   * @brief Disable the SMARTCARD receiver timeout feature
00146   * @param hsc: SMARTCARD handle
00147   * @retval HAL status
00148   */
00149 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
00150 {
00151   /* Process Locked */
00152   __HAL_LOCK(hsc);
00153
00154   hsc->State = HAL_SMARTCARD_STATE_BUSY;
00155
00156   /* Clear the USART RTOEN bit */
00157   hsc->Instance->CR2 &= ~(USART_CR2_RTOEN);
00158
00159   hsc->State = HAL_SMARTCARD_STATE_READY;
00160
00161   /* Process Unlocked */
00162   __HAL_UNLOCK(hsc);
00163
00164   return HAL_OK;
00165 }
00166
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32F745xx HAL User Manual: stm32f7xx_hal_smartcard_ex.h Source File

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stm32f7xx_hal_smartcard_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SMARTCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SMARTCARD_EX_H
00040 #define __STM32F7xx_HAL_SMARTCARD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARDEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported macro ------------------------------------------------------------*/
00060
00061 /** @brief  Reports the SMARTCARD clock source.
00062   * @param  __HANDLE__: specifies the USART Handle
00063   * @param  __CLOCKSOURCE__ : output variable
00064   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00065   */
00066 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
00067   do {                                                             \
00068     if((__HANDLE__)->Instance == USART1)                           \
00069     {                                                              \
00070        switch(__HAL_RCC_GET_USART1_SOURCE())                       \
00071        {                                                           \
00072         case RCC_USART1CLKSOURCE_PCLK2:                            \
00073           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;         \
00074           break;                                                   \
00075         case RCC_USART1CLKSOURCE_HSI:                              \
00076           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00077           break;                                                   \
00078         case RCC_USART1CLKSOURCE_SYSCLK:                           \
00079           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \
00080           break;                                                   \
00081         case RCC_USART1CLKSOURCE_LSE:                              \
00082           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00083           break;                                                   \
00084         default:                                                   \
00085           break;                                                   \
00086        }                                                           \
00087     }                                                              \
00088     else if((__HANDLE__)->Instance == USART2)                      \
00089     {                                                              \
00090        switch(__HAL_RCC_GET_USART2_SOURCE())                       \
00091        {                                                           \
00092         case RCC_USART2CLKSOURCE_PCLK1:                            \
00093           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \
00094           break;                                                   \
00095         case RCC_USART2CLKSOURCE_HSI:                              \
00096           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00097           break;                                                   \
00098         case RCC_USART2CLKSOURCE_SYSCLK:                           \
00099           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \
00100           break;                                                   \
00101         case RCC_USART2CLKSOURCE_LSE:                              \
00102           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00103           break;                                                   \
00104         default:                                                   \
00105           break;                                                   \
00106        }                                                           \
00107     }                                                              \
00108     else if((__HANDLE__)->Instance == USART3)                      \
00109     {                                                              \
00110        switch(__HAL_RCC_GET_USART3_SOURCE())                       \
00111        {                                                           \
00112         case RCC_USART3CLKSOURCE_PCLK1:                            \
00113           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \
00114           break;                                                   \
00115         case RCC_USART3CLKSOURCE_HSI:                              \
00116           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00117           break;                                                   \
00118         case RCC_USART3CLKSOURCE_SYSCLK:                           \
00119           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \
00120           break;                                                   \
00121         case RCC_USART3CLKSOURCE_LSE:                              \
00122           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00123           break;                                                   \
00124         default:                                                   \
00125           break;                                                   \
00126        }                                                           \
00127     }                                                              \
00128     else if((__HANDLE__)->Instance == USART6)                      \
00129     {                                                              \
00130        switch(__HAL_RCC_GET_USART6_SOURCE())                       \
00131        {                                                           \
00132         case RCC_USART6CLKSOURCE_PCLK2:                            \
00133           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;         \
00134           break;                                                   \
00135         case RCC_USART6CLKSOURCE_HSI:                              \
00136           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
00137           break;                                                   \
00138         case RCC_USART6CLKSOURCE_SYSCLK:                           \
00139           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \
00140           break;                                                   \
00141         case RCC_USART6CLKSOURCE_LSE:                              \
00142           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \
00143           break;                                                   \
00144         default:                                                   \
00145           break;                                                   \
00146        }                                                           \
00147     }                                                              \
00148     } while(0)
00149
00150 /* Exported functions --------------------------------------------------------*/
00151 /* Initialization and de-initialization functions  ****************************/
00152 /* IO operation functions *****************************************************/
00153 /* Peripheral Control functions ***********************************************/
00154 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength);
00155 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue);
00156 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);
00157 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);
00158
00159 /* Peripheral State and Error functions ***************************************/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 #ifdef __cplusplus
00170 }
00171 #endif
00172
00173 #endif /* __STM32F7xx_HAL_SMARTCARD_EX_H */
00174
00175 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32F745xx HAL User Manual: stm32f7xx_hal_spdifrx.c Source File

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stm32f7xx_hal_spdifrx.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_spdifrx.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the SPDIFRX audio interface:
00009   *           + Initialization and Configuration
00010   *           + Data transfers functions
00011   *           + DMA transfers management
00012   *           + Interrupts and flags management
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The SPDIFRX HAL driver can be used as follow:
00019
00020     (#) Declare SPDIFRX_HandleTypeDef handle structure.
00021     (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
00022         (##) Enable the SPDIFRX interface clock.
00023         (##) SPDIFRX pins configuration:
00024             (+++) Enable the clock for the SPDIFRX GPIOs.
00025             (+++) Configure these SPDIFRX pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
00027             (+++) Configure the SPDIFRX interrupt priority.
00028             (+++) Enable the NVIC SPDIFRX IRQ handle.
00029         (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
00030             (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
00031             (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
00032             (+++) Enable the DMAx interface clock.
00033             (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
00034             (+++) Configure the DMA Channel.
00035             (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00037                 DMA CtrlRx/DataRx channel.
00038
00039    (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
00040        using HAL_SPDIFRX_Init() function.
00041
00042    -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
00043        __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
00044    -@- Make sure that ck_spdif clock is configured.
00045
00046    (#) Three operation modes are available within this driver :
00047
00048    *** Polling mode for reception operation (for debug purpose) ***
00049    ================================================================
00050    [..]
00051      (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
00052          (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
00053
00054    *** Interrupt mode for reception operation ***
00055    =========================================
00056    [..]
00057      (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
00058          (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
00059      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00060          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00061      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00062          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00063      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00064          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00065
00066    *** DMA mode for reception operation ***
00067    ========================================
00068    [..]
00069      (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
00070          (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
00071      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00072          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00073      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00074          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00075      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00076          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00077      (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
00078
00079    *** SPDIFRX HAL driver macros list ***
00080    =============================================
00081    [..]
00082      Below the list of most used macros in USART HAL driver.
00083       (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
00084       (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
00085       (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
00086       (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
00087       (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
00088       (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
00089
00090     [..]
00091       (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
00092
00093   @endverbatim
00094   ******************************************************************************
00095   * @attention
00096   *
00097   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00098   *
00099   * Redistribution and use in source and binary forms, with or without modification,
00100   * are permitted provided that the following conditions are met:
00101   *   1. Redistributions of source code must retain the above copyright notice,
00102   *      this list of conditions and the following disclaimer.
00103   *   2. Redistributions in binary form must reproduce the above copyright notice,
00104   *      this list of conditions and the following disclaimer in the documentation
00105   *      and/or other materials provided with the distribution.
00106   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00107   *      may be used to endorse or promote products derived from this software
00108   *      without specific prior written permission.
00109   *
00110   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00111   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00112   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00113   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00114   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00115   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00116   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00117   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00118   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00119   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00120   *
00121   ******************************************************************************
00122   */
00123
00124 /* Includes ------------------------------------------------------------------*/
00125 #include "stm32f7xx_hal.h"
00126
00127 /** @addtogroup STM32F7xx_HAL_Driver
00128   * @{
00129   */
00130 /** @defgroup SPDIFRX SPDIFRX
00131 * @brief SPDIFRX HAL module driver
00132 * @{
00133 */
00134
00135 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00136
00137 /* Private typedef -----------------------------------------------------------*/
00138 /* Private define ------------------------------------------------------------*/
00139 #define SPDIFRX_TIMEOUT_VALUE  0xFFFF
00140
00141 /* Private macro -------------------------------------------------------------*/
00142 /* Private variables ---------------------------------------------------------*/
00143 /* Private function prototypes -----------------------------------------------*/
00144 /** @addtogroup SPDIFRX_Private_Functions
00145   * @{
00146   */
00147 static void  SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
00148 static void  SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00149 static void  SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
00150 static void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
00151 static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
00152 static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00153 static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00154 static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00155 /**
00156   * @}
00157   */
00158 /* Exported functions ---------------------------------------------------------*/
00159
00160 /** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
00161   * @{
00162   */
00163
00164 /** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
00165   *  @brief    Initialization and Configuration functions
00166   *
00167   @verbatim
00168   ===============================================================================
00169   ##### Initialization and de-initialization functions #####
00170   ===============================================================================
00171   [..]  This subsection provides a set of functions allowing to initialize and
00172   de-initialize the SPDIFRX peripheral:
00173
00174   (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
00175   all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00176
00177   (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
00178   the selected configuration:
00179   (++) Input Selection (IN0, IN1,...)
00180   (++) Maximum allowed re-tries during synchronization phase
00181   (++) Wait for activity on SPDIF selected input
00182   (++) Channel status selection (from channel A or B)
00183   (++) Data format (LSB, MSB, ...)
00184   (++) Stereo mode
00185   (++) User bits masking (PT,C,U,V,...)
00186
00187   (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
00188   of the selected SPDIFRXx peripheral.
00189   @endverbatim
00190   * @{
00191   */
00192
00193 /**
00194   * @brief Initializes the SPDIFRX according to the specified parameters
00195   *        in the SPDIFRX_InitTypeDef and create the associated handle.
00196   * @param hspdif: SPDIFRX handle
00197   * @retval HAL status
00198   */
00199 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
00200 {
00201   uint32_t tmpreg = 0;
00202
00203   /* Check the SPDIFRX handle allocation */
00204   if(hspdif == NULL)
00205   {
00206     return HAL_ERROR;
00207   }
00208
00209   /* Check the SPDIFRX parameters */
00210   assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
00211   assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
00212   assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
00213   assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
00214   assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
00215   assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
00216   assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
00217   assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
00218   assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
00219   assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
00220
00221   if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
00222   {
00223     /* Allocate lock resource and initialize it */
00224     hspdif->Lock = HAL_UNLOCKED;
00225     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00226     HAL_SPDIFRX_MspInit(hspdif);
00227   }
00228
00229      /* SPDIFRX peripheral state is BUSY*/
00230    hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00231
00232   /* Disable SPDIFRX interface (IDLE State) */
00233   __HAL_SPDIFRX_IDLE(hspdif);
00234
00235   /* Reset the old SPDIFRX CR configuration */
00236   tmpreg = hspdif->Instance->CR;
00237
00238   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00239                          SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |
00240                          SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
00241                          SPDIFRX_CR_INSEL);
00242
00243   /* Sets the new configuration of the SPDIFRX peripheral */
00244   tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
00245                         hspdif->Init.InputSelection |
00246                         hspdif->Init.Retries |
00247                         hspdif->Init.WaitForActivity |
00248                         hspdif->Init.ChannelSelection |
00249                         hspdif->Init.DataFormat |
00250                         hspdif->Init.PreambleTypeMask |
00251                         hspdif->Init.ChannelStatusMask |
00252                         hspdif->Init.ValidityBitMask |
00253                         hspdif->Init.ParityErrorMask);
00254
00255   hspdif->Instance->CR = tmpreg;
00256
00257   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00258
00259     /* SPDIFRX peripheral state is READY*/
00260   hspdif->State = HAL_SPDIFRX_STATE_READY;
00261
00262   return HAL_OK;
00263 }
00264
00265 /**
00266   * @brief DeInitializes the SPDIFRX peripheral
00267   * @param hspdif: SPDIFRX handle
00268   * @retval HAL status
00269   */
00270 HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
00271 {
00272   /* Check the SPDIFRX handle allocation */
00273   if(hspdif == NULL)
00274   {
00275     return HAL_ERROR;
00276   }
00277
00278   /* Check the parameters */
00279   assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
00280
00281   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00282
00283   /* Disable SPDIFRX interface (IDLE state) */
00284   __HAL_SPDIFRX_IDLE(hspdif);
00285
00286   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00287   HAL_SPDIFRX_MspDeInit(hspdif);
00288
00289   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00290
00291     /* SPDIFRX peripheral state is RESET*/
00292   hspdif->State = HAL_SPDIFRX_STATE_RESET;
00293
00294   /* Release Lock */
00295   __HAL_UNLOCK(hspdif);
00296
00297   return HAL_OK;
00298 }
00299
00300 /**
00301   * @brief SPDIFRX MSP Init
00302   * @param hspdif: SPDIFRX handle
00303   * @retval None
00304   */
00305 __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
00306 {
00307    /* Prevent unused argument(s) compilation warning */
00308   UNUSED(hspdif);
00309
00310   /* NOTE : This function Should not be modified, when the callback is needed,
00311   the HAL_SPDIFRX_MspInit could be implemented in the user file
00312   */
00313 }
00314
00315 /**
00316   * @brief SPDIFRX MSP DeInit
00317   * @param hspdif: SPDIFRX handle
00318   * @retval None
00319   */
00320 __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
00321 {
00322   /* Prevent unused argument(s) compilation warning */
00323   UNUSED(hspdif);
00324
00325   /* NOTE : This function Should not be modified, when the callback is needed,
00326   the HAL_SPDIFRX_MspDeInit could be implemented in the user file
00327   */
00328 }
00329
00330 /**
00331   * @brief Sets the SPDIFRX  dtat format according to the specified parameters
00332   *        in the SPDIFRX_InitTypeDef.
00333   * @param hspdif: SPDIFRX handle
00334   * @param sDataFormat: SPDIFRX data format
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat)
00338 {
00339   uint32_t tmpreg = 0;
00340
00341   /* Check the SPDIFRX handle allocation */
00342   if(hspdif == NULL)
00343   {
00344     return HAL_ERROR;
00345   }
00346
00347   /* Check the SPDIFRX parameters */
00348   assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
00349   assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
00350   assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
00351   assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
00352   assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
00353   assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
00354
00355   /* Reset the old SPDIFRX CR configuration */
00356   tmpreg = hspdif->Instance->CR;
00357
00358   if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
00359     (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
00360     ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
00361   {
00362       return HAL_ERROR;
00363   }
00364
00365   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00366                          SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
00367
00368   /* Sets the new configuration of the SPDIFRX peripheral */
00369   tmpreg |= ((uint16_t) sDataFormat.StereoMode |
00370                         sDataFormat.DataFormat |
00371                         sDataFormat.PreambleTypeMask |
00372                         sDataFormat.ChannelStatusMask |
00373                         sDataFormat.ValidityBitMask |
00374                         sDataFormat.ParityErrorMask);
00375
00376   hspdif->Instance->CR = tmpreg;
00377
00378   return HAL_OK;
00379 }
00380
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
00386   *  @brief Data transfers functions
00387   *
00388 @verbatim
00389 ===============================================================================
00390                      ##### IO operation functions #####
00391 ===============================================================================
00392     [..]
00393     This subsection provides a set of functions allowing to manage the SPDIFRX data
00394     transfers.
00395
00396     (#) There is two mode of transfer:
00397         (++) Blocking mode : The communication is performed in the polling mode.
00398              The status of all data processing is returned by the same function
00399              after finishing transfer.
00400         (++) No-Blocking mode : The communication is performed using Interrupts
00401              or DMA. These functions return the status of the transfer start-up.
00402              The end of the data processing will be indicated through the
00403              dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
00404              using DMA mode.
00405
00406     (#) Blocking mode functions are :
00407         (++) HAL_SPDIFRX_ReceiveDataFlow()
00408         (++) HAL_SPDIFRX_ReceiveControlFlow()
00409                 (+@) Do not use blocking mode to receive both control and data flow at the same time.
00410
00411     (#) No-Blocking mode functions with Interrupt are :
00412         (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
00413         (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
00414
00415     (#) No-Blocking mode functions with DMA are :
00416         (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
00417         (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
00418
00419     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00420         (++) HAL_SPDIFRX_RxCpltCallback()
00421         (++) HAL_SPDIFRX_ErrorCallback()
00422
00423 @endverbatim
00424 * @{
00425 */
00426
00427
00428 /**
00429   * @brief  Receives an amount of data (Data Flow) in blocking mode.
00430   * @param  hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
00431   *                 the configuration information for SPDIFRX module.
00432   * @param  pData: Pointer to data buffer
00433   * @param  Size: Amount of data to be received
00434   * @param  Timeout: Timeout duration
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00438 {
00439
00440   if((pData == NULL ) || (Size == 0))
00441   {
00442     return  HAL_ERROR;
00443   }
00444
00445   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00446   {
00447     /* Process Locked */
00448     __HAL_LOCK(hspdif);
00449
00450      hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00451
00452         /* Start synchronisation */
00453         __HAL_SPDIFRX_SYNC(hspdif);
00454
00455             /* Wait until SYNCD flag is set */
00456       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
00457       {
00458         return HAL_TIMEOUT;
00459       }
00460
00461             /* Start reception */
00462       __HAL_SPDIFRX_RCV(hspdif);
00463
00464     /* Receive data flow */
00465     while(Size > 0)
00466     {
00467       /* Wait until RXNE flag is set */
00468       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00469       {
00470         return HAL_TIMEOUT;
00471       }
00472
00473       (*pData++) = hspdif->Instance->DR;
00474       Size--;
00475     }
00476
00477     /* SPDIFRX ready */
00478     hspdif->State = HAL_SPDIFRX_STATE_READY;
00479
00480     /* Process Unlocked */
00481     __HAL_UNLOCK(hspdif);
00482
00483     return HAL_OK;
00484   }
00485   else
00486   {
00487     return HAL_BUSY;
00488   }
00489 }
00490
00491 /**
00492   * @brief  Receives an amount of data (Control Flow) in blocking mode.
00493   * @param  hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
00494   *                 the configuration information for SPDIFRX module.
00495   * @param  pData: Pointer to data buffer
00496   * @param  Size: Amount of data to be received
00497   * @param  Timeout: Timeout duration
00498   * @retval HAL status
00499   */
00500 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00501 {
00502
00503   if((pData == NULL ) || (Size == 0))
00504   {
00505     return  HAL_ERROR;
00506   }
00507
00508   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00509   {
00510     /* Process Locked */
00511     __HAL_LOCK(hspdif);
00512
00513      hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00514
00515         /* Start synchronization */
00516         __HAL_SPDIFRX_SYNC(hspdif);
00517
00518         /* Wait until SYNCD flag is set */
00519       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
00520       {
00521         return HAL_TIMEOUT;
00522       }
00523
00524         /* Start reception */
00525       __HAL_SPDIFRX_RCV(hspdif);
00526
00527         /* Receive control flow */
00528     while(Size > 0)
00529     {
00530       /* Wait until CSRNE flag is set */
00531       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
00532       {
00533         return HAL_TIMEOUT;
00534       }
00535
00536       (*pData++) = hspdif->Instance->CSR;
00537       Size--;
00538     }
00539
00540     /* SPDIFRX ready */
00541     hspdif->State = HAL_SPDIFRX_STATE_READY;
00542
00543     /* Process Unlocked */
00544     __HAL_UNLOCK(hspdif);
00545
00546     return HAL_OK;
00547   }
00548   else
00549   {
00550     return HAL_BUSY;
00551   }
00552 }
00553 /**
00554   * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
00555   * @param hspdif: SPDIFRX handle
00556   * @param pData: a 32-bit pointer to the Receive data buffer.
00557   * @param Size: number of data sample to be received .
00558   * @retval HAL status
00559   */
00560 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00561 {
00562  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
00563   {
00564     if((pData == NULL) || (Size == 0))
00565     {
00566       return HAL_ERROR;
00567     }
00568
00569     /* Process Locked */
00570     __HAL_LOCK(hspdif);
00571
00572     hspdif->pRxBuffPtr = pData;
00573     hspdif->RxXferSize = Size;
00574     hspdif->RxXferCount = Size;
00575
00576     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00577
00578     /* Check if a receive process is ongoing or not */
00579      hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00580
00581
00582     /* Enable the SPDIFRX  PE Error Interrupt */
00583     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00584
00585     /* Enable the SPDIFRX  OVR Error Interrupt */
00586     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00587
00588     /* Process Unlocked */
00589     __HAL_UNLOCK(hspdif);
00590
00591     /* Enable the SPDIFRX RXNE interrupt */
00592     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
00593
00594         if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00))
00595         {
00596         /* Start synchronization */
00597         __HAL_SPDIFRX_SYNC(hspdif);
00598
00599         /* Wait until SYNCD flag is set */
00600       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00601       {
00602         return HAL_TIMEOUT;
00603       }
00604
00605         /* Start reception */
00606       __HAL_SPDIFRX_RCV(hspdif);
00607         }
00608
00609     return HAL_OK;
00610   }
00611   else
00612   {
00613     return HAL_BUSY;
00614   }
00615 }
00616
00617 /**
00618   * @brief Receive an amount of data (Control Flow) with Interrupt
00619   * @param hspdif: SPDIFRX handle
00620   * @param pData: a 32-bit pointer to the Receive data buffer.
00621   * @param Size: number of data sample (Control Flow) to be received :
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00625 {
00626  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
00627   {
00628     if((pData == NULL ) || (Size == 0))
00629     {
00630       return HAL_ERROR;
00631     }
00632
00633     /* Process Locked */
00634     __HAL_LOCK(hspdif);
00635
00636     hspdif->pCsBuffPtr = pData;
00637     hspdif->CsXferSize = Size;
00638     hspdif->CsXferCount = Size;
00639
00640     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00641
00642     /* Check if a receive process is ongoing or not */
00643      hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00644
00645
00646     /* Enable the SPDIFRX PE Error Interrupt */
00647      __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00648
00649     /* Enable the SPDIFRX OVR Error Interrupt */
00650      __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00651
00652     /* Process Unlocked */
00653     __HAL_UNLOCK(hspdif);
00654
00655     /* Enable the SPDIFRX CSRNE interrupt */
00656     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
00657
00658         if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00))
00659         {
00660         /* Start synchronization */
00661         __HAL_SPDIFRX_SYNC(hspdif);
00662
00663         /* Wait until SYNCD flag is set */
00664       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00665       {
00666         return HAL_TIMEOUT;
00667       }
00668
00669         /* Start reception */
00670       __HAL_SPDIFRX_RCV(hspdif);
00671       }
00672
00673     return HAL_OK;
00674   }
00675   else
00676   {
00677     return HAL_BUSY;
00678   }
00679 }
00680
00681 /**
00682   * @brief Receive an amount of data (Data Flow) mode with DMA
00683   * @param hspdif: SPDIFRX handle
00684   * @param pData: a 32-bit pointer to the Receive data buffer.
00685   * @param Size: number of data sample to be received :
00686   * @retval HAL status
00687   */
00688 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00689 {
00690
00691   if((pData == NULL) || (Size == 0))
00692   {
00693     return  HAL_ERROR;
00694   }
00695
00696   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
00697   {
00698     hspdif->pRxBuffPtr = pData;
00699     hspdif->RxXferSize = Size;
00700     hspdif->RxXferCount = Size;
00701
00702     /* Process Locked */
00703     __HAL_LOCK(hspdif);
00704
00705     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00706     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00707
00708     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
00709     hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
00710
00711     /* Set the SPDIFRX Rx DMA transfer complete callback */
00712     hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
00713
00714     /* Set the DMA error callback */
00715     hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
00716
00717     /* Enable the DMA request */
00718     HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
00719
00720     /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
00721      hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
00722
00723         if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00))
00724         {
00725         /* Start synchronization */
00726         __HAL_SPDIFRX_SYNC(hspdif);
00727
00728         /* Wait until SYNCD flag is set */
00729       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00730       {
00731         return HAL_TIMEOUT;
00732       }
00733
00734         /* Start reception */
00735       __HAL_SPDIFRX_RCV(hspdif);
00736         }
00737
00738     /* Process Unlocked */
00739     __HAL_UNLOCK(hspdif);
00740
00741     return HAL_OK;
00742   }
00743   else
00744   {
00745     return HAL_BUSY;
00746   }
00747 }
00748
00749 /**
00750   * @brief Receive an amount of data (Control Flow) with DMA
00751   * @param hspdif: SPDIFRX handle
00752   * @param pData: a 32-bit pointer to the Receive data buffer.
00753   * @param Size: number of data (Control Flow) sample to be received :
00754   * @retval HAL status
00755   */
00756 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00757 {
00758
00759   if((pData == NULL) || (Size == 0))
00760   {
00761     return  HAL_ERROR;
00762   }
00763
00764  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
00765   {
00766     hspdif->pCsBuffPtr = pData;
00767     hspdif->CsXferSize = Size;
00768     hspdif->CsXferCount = Size;
00769
00770     /* Process Locked */
00771     __HAL_LOCK(hspdif);
00772
00773     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00774     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00775
00776     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
00777     hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
00778
00779     /* Set the SPDIFRX Rx DMA transfer complete callback */
00780     hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
00781
00782     /* Set the DMA error callback */
00783     hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
00784
00785     /* Enable the DMA request */
00786     HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
00787
00788     /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
00789     hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
00790
00791         if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00))
00792         {
00793         /* Start synchronization */
00794         __HAL_SPDIFRX_SYNC(hspdif);
00795
00796         /* Wait until SYNCD flag is set */
00797       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00798       {
00799         return HAL_TIMEOUT;
00800       }
00801
00802         /* Start reception */
00803       __HAL_SPDIFRX_RCV(hspdif);
00804         }
00805
00806     /* Process Unlocked */
00807     __HAL_UNLOCK(hspdif);
00808
00809     return HAL_OK;
00810   }
00811   else
00812   {
00813     return HAL_BUSY;
00814   }
00815 }
00816
00817 /**
00818   * @brief stop the audio stream receive from the Media.
00819   * @param hspdif: SPDIFRX handle
00820   * @retval None
00821   */
00822 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
00823 {
00824   /* Process Locked */
00825   __HAL_LOCK(hspdif);
00826
00827   /* Disable the SPDIFRX DMA requests */
00828   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
00829   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
00830
00831   /* Disable the SPDIFRX DMA channel */
00832   __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
00833   __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
00834
00835   /* Disable SPDIFRX peripheral */
00836   __HAL_SPDIFRX_IDLE(hspdif);
00837
00838   hspdif->State = HAL_SPDIFRX_STATE_READY;
00839
00840   /* Process Unlocked */
00841   __HAL_UNLOCK(hspdif);
00842
00843   return HAL_OK;
00844 }
00845
00846 /**
00847   * @brief  This function handles SPDIFRX interrupt request.
00848   * @param  hspdif: SPDIFRX handle
00849   * @retval HAL status
00850   */
00851 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
00852 {
00853   /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
00854   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
00855   {
00856       __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
00857     SPDIFRX_ReceiveDataFlow_IT(hspdif);
00858   }
00859
00860    /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
00861   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
00862   {
00863         __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
00864     SPDIFRX_ReceiveControlFlow_IT(hspdif);
00865   }
00866
00867   /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
00868   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
00869   {
00870     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
00871
00872         /* Change the SPDIFRX error code */
00873     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
00874
00875         /* the transfer is not stopped */
00876     HAL_SPDIFRX_ErrorCallback(hspdif);
00877   }
00878
00879       /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
00880   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
00881   {
00882     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
00883
00884         /* Change the SPDIFRX error code */
00885     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
00886
00887         /* the transfer is not stopped */
00888     HAL_SPDIFRX_ErrorCallback(hspdif);
00889   }
00890
00891 }
00892
00893 /**
00894   * @brief Rx Transfer (Data flow) half completed callbacks
00895   * @param hspdif: SPDIFRX handle
00896   * @retval None
00897   */
00898 __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00899 {
00900   /* Prevent unused argument(s) compilation warning */
00901   UNUSED(hspdif);
00902
00903   /* NOTE : This function Should not be modified, when the callback is needed,
00904   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00905   */
00906 }
00907
00908 /**
00909   * @brief Rx Transfer (Data flow) completed callbacks
00910   * @param hspdif: SPDIFRX handle
00911   * @retval None
00912   */
00913 __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00914 {
00915   /* Prevent unused argument(s) compilation warning */
00916   UNUSED(hspdif);
00917
00918   /* NOTE : This function Should not be modified, when the callback is needed,
00919   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00920   */
00921 }
00922
00923 /**
00924   * @brief Rx (Control flow) Transfer half completed callbacks
00925   * @param hspdif: SPDIFRX handle
00926   * @retval None
00927   */
00928 __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00929 {
00930   /* Prevent unused argument(s) compilation warning */
00931   UNUSED(hspdif);
00932
00933   /* NOTE : This function Should not be modified, when the callback is needed,
00934   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00935   */
00936 }
00937
00938 /**
00939   * @brief Rx Transfer (Control flow) completed callbacks
00940   * @param hspdif: SPDIFRX handle
00941   * @retval None
00942   */
00943 __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00944 {
00945   /* Prevent unused argument(s) compilation warning */
00946   UNUSED(hspdif);
00947
00948   /* NOTE : This function Should not be modified, when the callback is needed,
00949   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00950   */
00951 }
00952
00953 /**
00954   * @brief SPDIFRX error callbacks
00955   * @param hspdif: SPDIFRX handle
00956   * @retval None
00957   */
00958 __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
00959 {
00960   /* Prevent unused argument(s) compilation warning */
00961   UNUSED(hspdif);
00962
00963   /* NOTE : This function Should not be modified, when the callback is needed,
00964   the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
00965   */
00966 }
00967
00968 /**
00969   * @}
00970   */
00971
00972 /** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
00973   *  @brief   Peripheral State functions
00974   *
00975 @verbatim
00976 ===============================================================================
00977 ##### Peripheral State and Errors functions #####
00978 ===============================================================================
00979 [..]
00980 This subsection permit to get in run-time the status of the peripheral
00981 and the data flow.
00982
00983 @endverbatim
00984   * @{
00985   */
00986
00987 /**
00988   * @brief  Return the SPDIFRX state
00989   * @param  hspdif : SPDIFRX handle
00990   * @retval HAL state
00991   */
00992 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
00993 {
00994   return hspdif->State;
00995 }
00996
00997 /**
00998   * @brief  Return the SPDIFRX error code
00999   * @param  hspdif : SPDIFRX handle
01000   * @retval SPDIFRX Error Code
01001   */
01002 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
01003 {
01004   return hspdif->ErrorCode;
01005 }
01006
01007 /**
01008   * @}
01009   */
01010
01011 /**
01012   * @brief DMA SPDIFRX receive process (Data flow) complete callback
01013   * @param hdma : DMA handle
01014   * @retval None
01015   */
01016 static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
01017 {
01018   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01019
01020   /* Disable Rx DMA Request */
01021   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01022   {
01023     hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
01024     hspdif->RxXferCount = 0;
01025     hspdif->State = HAL_SPDIFRX_STATE_READY;
01026   }
01027   HAL_SPDIFRX_RxCpltCallback(hspdif);
01028 }
01029
01030 /**
01031   * @brief DMA SPDIFRX receive process (Data flow) half complete callback
01032   * @param hdma : DMA handle
01033   * @retval None
01034   */
01035 static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01036 {
01037   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01038
01039   HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
01040 }
01041
01042
01043 /**
01044   * @brief DMA SPDIFRX receive process (Control flow) complete callback
01045   * @param hdma : DMA handle
01046   * @retval None
01047   */
01048 static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
01049 {
01050   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01051
01052   /* Disable Cb DMA Request */
01053   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
01054   hspdif->CsXferCount = 0;
01055
01056   hspdif->State = HAL_SPDIFRX_STATE_READY;
01057   HAL_SPDIFRX_CxCpltCallback(hspdif);
01058 }
01059
01060 /**
01061   * @brief DMA SPDIFRX receive process (Control flow) half complete callback
01062   * @param hdma : DMA handle
01063   * @retval None
01064   */
01065 static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
01066 {
01067   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01068
01069   HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
01070 }
01071
01072 /**
01073   * @brief DMA SPDIFRX communication error callback
01074   * @param hdma : DMA handle
01075   * @retval None
01076   */
01077 static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
01078 {
01079   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01080
01081   /* Disable Rx and Cb DMA Request */
01082   hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
01083   hspdif->RxXferCount = 0;
01084
01085   hspdif->State= HAL_SPDIFRX_STATE_READY;
01086
01087   /* Set the error code and execute error callback*/
01088   hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
01089   HAL_SPDIFRX_ErrorCallback(hspdif);
01090 }
01091
01092
01093 /**
01094   * @brief Receive an amount of data (Data Flow) with Interrupt
01095   * @param hspdif: SPDIFRX handle
01096   * @retval None
01097   */
01098 static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01099 {
01100     /* Receive data */
01101     (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
01102     hspdif->RxXferCount--;
01103
01104     if(hspdif->RxXferCount == 0)
01105     {
01106       /* Disable RXNE/PE and OVR interrupts */
01107       __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
01108
01109       hspdif->State = HAL_SPDIFRX_STATE_READY;
01110
01111       /* Process Unlocked */
01112       __HAL_UNLOCK(hspdif);
01113
01114       HAL_SPDIFRX_RxCpltCallback(hspdif);
01115     }
01116 }
01117
01118 /**
01119   * @brief Receive an amount of data (Control Flow) with Interrupt
01120   * @param hspdif: SPDIFRX handle
01121   * @retval None
01122   */
01123 static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01124 {
01125     /* Receive data */
01126     (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
01127     hspdif->CsXferCount--;
01128
01129     if(hspdif->CsXferCount == 0)
01130     {
01131       /* Disable CSRNE interrupt */
01132       __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01133
01134        hspdif->State = HAL_SPDIFRX_STATE_READY;
01135
01136       /* Process Unlocked */
01137       __HAL_UNLOCK(hspdif);
01138
01139       HAL_SPDIFRX_CxCpltCallback(hspdif);
01140     }
01141 }
01142
01143 /**
01144   * @brief This function handles SPDIFRX Communication Timeout.
01145   * @param hspdif: SPDIFRX handle
01146   * @param Flag: Flag checked
01147   * @param Status: Value of the flag expected
01148   * @param Timeout: Duration of the timeout
01149   * @retval HAL status
01150   */
01151 static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01152 {
01153   uint32_t tickstart = 0;
01154
01155   /* Get tick */
01156   tickstart = HAL_GetTick();
01157
01158   /* Wait until flag is set */
01159   if(Status == RESET)
01160   {
01161     while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
01162     {
01163       /* Check for the Timeout */
01164       if(Timeout != HAL_MAX_DELAY)
01165       {
01166         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01167         {
01168           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01169           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01170           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01171           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01172           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01173           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01174           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01175           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01176
01177           hspdif->State= HAL_SPDIFRX_STATE_READY;
01178
01179           /* Process Unlocked */
01180           __HAL_UNLOCK(hspdif);
01181
01182           return HAL_TIMEOUT;
01183         }
01184       }
01185     }
01186   }
01187   else
01188   {
01189     while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
01190     {
01191       /* Check for the Timeout */
01192       if(Timeout != HAL_MAX_DELAY)
01193       {
01194         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01195         {
01196           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01197           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01198           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01199           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01200           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01201                     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01202           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01203           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01204
01205           hspdif->State= HAL_SPDIFRX_STATE_READY;
01206
01207           /* Process Unlocked */
01208           __HAL_UNLOCK(hspdif);
01209
01210           return HAL_TIMEOUT;
01211         }
01212       }
01213     }
01214   }
01215   return HAL_OK;
01216 }
01217
01218 /**
01219 * @}
01220 */
01221
01222 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
01223 /**
01224   * @}
01225   */
01226
01227 /**
01228   * @}
01229   */
01230
01231 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spdifrx.h Source File

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stm32f7xx_hal_spdifrx.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_spdifrx.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SPDIFRX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SPDIFRX_H
00040 #define __STM32F7xx_HAL_SPDIFRX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPDIFRX
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SPDIFRX Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.
00068                                           This parameter can be a value of @ref SPDIFRX_Input_Selection */
00069
00070   uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.
00071                                           This parameter can be a value of @ref SPDIFRX_Max_Retries */
00072
00073   uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.
00074                                           This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
00075
00076   uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.
00077                                           This parameter can be a value of @ref SPDIFRX_Channel_Selection */
00078
00079   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00080                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00081
00082   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00083                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00084
00085     uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00086                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00087
00088     uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00089                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00090
00091     uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00092                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00093
00094     uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00095                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00096
00097 }SPDIFRX_InitTypeDef;
00098
00099 /**
00100   * @brief SPDIFRX SetDataFormat structure definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00105                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00106
00107   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00108                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00109
00110   uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00111                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00112
00113   uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00114                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00115
00116   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00117                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00118
00119   uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00120                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00121
00122 }SPDIFRX_SetDataFormatTypeDef;
00123
00124 /**
00125   * @brief  HAL State structures definition
00126   */
00127 typedef enum
00128 {
00129   HAL_SPDIFRX_STATE_RESET      = 0x00,  /*!< SPDIFRX not yet initialized or disabled                */
00130   HAL_SPDIFRX_STATE_READY      = 0x01,  /*!< SPDIFRX initialized and ready for use                  */
00131   HAL_SPDIFRX_STATE_BUSY       = 0x02,  /*!< SPDIFRX internal process is ongoing                    */
00132   HAL_SPDIFRX_STATE_BUSY_RX    = 0x03,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */
00133   HAL_SPDIFRX_STATE_BUSY_CX    = 0x04,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */
00134   HAL_SPDIFRX_STATE_ERROR      = 0x07   /*!< SPDIFRX error state                                    */
00135 }HAL_SPDIFRX_StateTypeDef;
00136
00137 /**
00138   * @brief SPDIFRX handle Structure definition
00139   */
00140 typedef struct
00141 {
00142   SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */
00143
00144   SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */
00145
00146   uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */
00147
00148     uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */
00149
00150   __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */
00151
00152   __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter
00153                                               (This field is initialized at the
00154                                                same value as transfer size at the
00155                                                beginning of the transfer and
00156                                                decremented when a sample is received.
00157                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00158
00159   __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */
00160
00161   __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter
00162                                               (This field is initialized at the
00163                                                same value as transfer size at the
00164                                                beginning of the transfer and
00165                                                decremented when a sample is received.
00166                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00167
00168   DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
00169
00170   DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */
00171
00172   __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */
00173
00174   __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */
00175
00176   __IO uint32_t  ErrorCode;                /* SPDIFRX Error code                 */
00177
00178 }SPDIFRX_HandleTypeDef;
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported constants --------------------------------------------------------*/
00184 /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
00185   * @{
00186   */
00187 /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
00188   * @{
00189   */
00190 #define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error           */
00191 #define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001)  /*!< Timeout error      */
00192 #define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002)  /*!< OVR error          */
00193 #define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004)  /*!< Parity error       */
00194 #define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008)  /*!< DMA transfer error */
00195 #define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010)  /*!< Unknown Error error */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
00201   * @{
00202   */
00203 #define SPDIFRX_INPUT_IN0               ((uint32_t)0x00000000)
00204 #define SPDIFRX_INPUT_IN1               ((uint32_t)0x00010000)
00205 #define SPDIFRX_INPUT_IN2               ((uint32_t)0x00020000)
00206 #define SPDIFRX_INPUT_IN3               ((uint32_t)0x00030000)
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
00212   * @{
00213   */
00214 #define SPDIFRX_MAXRETRIES_NONE            ((uint32_t)0x00000000)
00215 #define SPDIFRX_MAXRETRIES_3               ((uint32_t)0x00001000)
00216 #define SPDIFRX_MAXRETRIES_15              ((uint32_t)0x00002000)
00217 #define SPDIFRX_MAXRETRIES_63              ((uint32_t)0x00003000)
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
00223   * @{
00224   */
00225 #define SPDIFRX_WAITFORACTIVITY_OFF                   ((uint32_t)0x00000000)
00226 #define SPDIFRX_WAITFORACTIVITY_ON                    ((uint32_t)SPDIFRX_CR_WFA)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
00232 * @{
00233 */
00234 #define SPDIFRX_PREAMBLETYPEMASK_OFF                   ((uint32_t)0x00000000)
00235 #define SPDIFRX_PREAMBLETYPEMASK_ON                    ((uint32_t)SPDIFRX_CR_PTMSK)
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask
00241 * @{
00242 */
00243 #define SPDIFRX_CHANNELSTATUS_OFF                 ((uint32_t)0x00000000)        /* The channel status and user bits are copied into the SPDIF_DR */
00244 #define SPDIFRX_CHANNELSTATUS_ON                  ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
00250 * @{
00251 */
00252 #define SPDIFRX_VALIDITYMASK_OFF                   ((uint32_t)0x00000000)
00253 #define SPDIFRX_VALIDITYMASK_ON                    ((uint32_t)SPDIFRX_CR_VMSK)
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask
00259 * @{
00260 */
00261 #define SPDIFRX_PARITYERRORMASK_OFF                   ((uint32_t)0x00000000)
00262 #define SPDIFRX_PARITYERRORMASK_ON                    ((uint32_t)SPDIFRX_CR_PMSK)
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection
00268   * @{
00269   */
00270 #define SPDIFRX_CHANNEL_A      ((uint32_t)0x00000000)
00271 #define SPDIFRX_CHANNEL_B      ((uint32_t)SPDIFRX_CR_CHSEL)
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
00277   * @{
00278   */
00279 #define SPDIFRX_DATAFORMAT_LSB                   ((uint32_t)0x00000000)
00280 #define SPDIFRX_DATAFORMAT_MSB                   ((uint32_t)0x00000010)
00281 #define SPDIFRX_DATAFORMAT_32BITS                ((uint32_t)0x00000020)
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
00287   * @{
00288   */
00289 #define SPDIFRX_STEREOMODE_DISABLE           ((uint32_t)0x00000000)
00290 #define SPDIFRX_STEREOMODE_ENABLE           ((uint32_t)SPDIFRX_CR_RXSTEO)
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SPDIFRX_State SPDIFRX State
00296   * @{
00297   */
00298
00299 #define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFC)
00300 #define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001)
00301 #define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
00307   * @{
00308   */
00309 #define SPDIFRX_IT_RXNE                       ((uint32_t)SPDIFRX_IMR_RXNEIE)
00310 #define SPDIFRX_IT_CSRNE                      ((uint32_t)SPDIFRX_IMR_CSRNEIE)
00311 #define SPDIFRX_IT_PERRIE                     ((uint32_t)SPDIFRX_IMR_PERRIE)
00312 #define SPDIFRX_IT_OVRIE                      ((uint32_t)SPDIFRX_IMR_OVRIE)
00313 #define SPDIFRX_IT_SBLKIE                     ((uint32_t)SPDIFRX_IMR_SBLKIE)
00314 #define SPDIFRX_IT_SYNCDIE                    ((uint32_t)SPDIFRX_IMR_SYNCDIE)
00315 #define SPDIFRX_IT_IFEIE                      ((uint32_t)SPDIFRX_IMR_IFEIE )
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
00321   * @{
00322   */
00323 #define SPDIFRX_FLAG_RXNE                   ((uint32_t)SPDIFRX_SR_RXNE)
00324 #define SPDIFRX_FLAG_CSRNE                  ((uint32_t)SPDIFRX_SR_CSRNE)
00325 #define SPDIFRX_FLAG_PERR                   ((uint32_t)SPDIFRX_SR_PERR)
00326 #define SPDIFRX_FLAG_OVR                    ((uint32_t)SPDIFRX_SR_OVR)
00327 #define SPDIFRX_FLAG_SBD                    ((uint32_t)SPDIFRX_SR_SBD)
00328 #define SPDIFRX_FLAG_SYNCD                  ((uint32_t)SPDIFRX_SR_SYNCD)
00329 #define SPDIFRX_FLAG_FERR                   ((uint32_t)SPDIFRX_SR_FERR)
00330 #define SPDIFRX_FLAG_SERR                   ((uint32_t)SPDIFRX_SR_SERR)
00331 #define SPDIFRX_FLAG_TERR                   ((uint32_t)SPDIFRX_SR_TERR)
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 /* Exported macros -----------------------------------------------------------*/
00341 /** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
00342   * @{
00343   */
00344
00345 /** @brief  Reset SPDIFRX handle state
00346   * @param  __HANDLE__: SPDIFRX handle.
00347   * @retval None
00348   */
00349 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
00350
00351 /** @brief  Disable the specified SPDIFRX peripheral (IDLE State).
00352   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00353   * @retval None
00354   */
00355 #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
00356
00357 /** @brief  Enable the specified SPDIFRX peripheral (SYNC State).
00358   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00359   * @retval None
00360   */
00361 #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
00362
00363
00364 /** @brief  Enable the specified SPDIFRX peripheral (RCV State).
00365   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00366   * @retval None
00367   */
00368 #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
00369
00370
00371 /** @brief  Enable or disable the specified SPDIFRX interrupts.
00372   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00373   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00374   *        This parameter can be one of the following values:
00375   *            @arg SPDIFRX_IT_RXNE
00376   *            @arg SPDIFRX_IT_CSRNE
00377   *            @arg SPDIFRX_IT_PERRIE
00378   *            @arg SPDIFRX_IT_OVRIE
00379   *            @arg SPDIFRX_IT_SBLKIE
00380   *            @arg SPDIFRX_IT_SYNCDIE
00381   *            @arg SPDIFRX_IT_IFEIE
00382   * @retval None
00383   */
00384 #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00385 #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
00386
00387 /** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.
00388   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00389   * @param  __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
00390   *          This parameter can be one of the following values:
00391   *            @arg SPDIFRX_IT_RXNE
00392   *            @arg SPDIFRX_IT_CSRNE
00393   *            @arg SPDIFRX_IT_PERRIE
00394   *            @arg SPDIFRX_IT_OVRIE
00395   *            @arg SPDIFRX_IT_SBLKIE
00396   *            @arg SPDIFRX_IT_SYNCDIE
00397   *            @arg SPDIFRX_IT_IFEIE
00398   * @retval The new state of __IT__ (TRUE or FALSE).
00399   */
00400 #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00401
00402 /** @brief  Checks whether the specified SPDIFRX flag is set or not.
00403   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00404   * @param  __FLAG__: specifies the flag to check.
00405   *        This parameter can be one of the following values:
00406   *            @arg SPDIFRX_FLAG_RXNE
00407   *            @arg SPDIFRX_FLAG_CSRNE
00408   *            @arg SPDIFRX_FLAG_PERR
00409   *            @arg SPDIFRX_FLAG_OVR
00410   *            @arg SPDIFRX_FLAG_SBD
00411   *            @arg SPDIFRX_FLAG_SYNCD
00412   *            @arg SPDIFRX_FLAG_FERR
00413   *            @arg SPDIFRX_FLAG_SERR
00414   *            @arg SPDIFRX_FLAG_TERR
00415   * @retval The new state of __FLAG__ (TRUE or FALSE).
00416   */
00417 #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00418
00419 /** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
00420   * @param  __HANDLE__: specifies the USART Handle.
00421   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00422   *                       to clear the corresponding interrupt
00423   *          This parameter can be one of the following values:
00424   *            @arg SPDIFRX_FLAG_PERR
00425   *            @arg SPDIFRX_FLAG_OVR
00426   *            @arg SPDIFRX_SR_SBD
00427   *            @arg SPDIFRX_SR_SYNCD
00428   * @retval None
00429   */
00430 #define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
00431
00432 /**
00433   * @}
00434   */
00435
00436 /* Exported functions --------------------------------------------------------*/
00437 /** @addtogroup SPDIFRX_Exported_Functions
00438   * @{
00439   */
00440
00441 /** @addtogroup SPDIFRX_Exported_Functions_Group1
00442   * @{
00443   */
00444 /* Initialization/de-initialization functions  **********************************/
00445 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
00446 HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
00447 void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
00448 void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
00449 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);
00450 /**
00451   * @}
00452   */
00453
00454 /** @addtogroup SPDIFRX_Exported_Functions_Group2
00455   * @{
00456   */
00457 /* I/O operation functions  ***************************************************/
00458  /* Blocking mode: Polling */
00459 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00460 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00461
00462  /* Non-Blocking mode: Interrupt */
00463 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00464 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00465 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
00466
00467 /* Non-Blocking mode: DMA */
00468 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00469 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00470
00471 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
00472
00473 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00474 void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00475 void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00476 void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
00477 void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00478 void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00479 /**
00480   * @}
00481   */
00482
00483 /** @addtogroup SPDIFRX_Exported_Functions_Group3
00484   * @{
00485   */
00486 /* Peripheral Control and State functions  ************************************/
00487 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
00488 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
00489 /**
00490   * @}
00491   */
00492
00493 /**
00494   * @}
00495   */
00496 /* Private types -------------------------------------------------------------*/
00497 /* Private variables ---------------------------------------------------------*/
00498 /* Private constants ---------------------------------------------------------*/
00499 /* Private macros ------------------------------------------------------------*/
00500 /** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
00501   * @{
00502   */
00503 #define IS_SPDIFRX_INPUT_SELECT(INPUT)  (((INPUT) == SPDIFRX_INPUT_IN1) || \
00504                                          ((INPUT) == SPDIFRX_INPUT_IN2) || \
00505                                          ((INPUT) == SPDIFRX_INPUT_IN3)  || \
00506                                          ((INPUT) == SPDIFRX_INPUT_IN0))
00507 #define IS_SPDIFRX_MAX_RETRIES(RET)   (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
00508                                       ((RET) == SPDIFRX_MAXRETRIES_3)  || \
00509                                       ((RET) == SPDIFRX_MAXRETRIES_15) || \
00510                                       ((RET) == SPDIFRX_MAXRETRIES_63))
00511 #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)    (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
00512                                                ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
00513 #define IS_PREAMBLE_TYPE_MASK(VAL)           (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
00514                                              ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
00515 #define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
00516                                              ((VAL) == SPDIFRX_VALIDITYMASK_ON))
00517 #define IS_PARITY_ERROR_MASK(VAL)            (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
00518                                              ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
00519 #define IS_SPDIFRX_CHANNEL(CHANNEL)   (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
00520                                        ((CHANNEL) == SPDIFRX_CHANNEL_B))
00521 #define IS_SPDIFRX_DATA_FORMAT(FORMAT)           (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
00522                                                  ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
00523                                                  ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
00524 #define IS_STEREO_MODE(MODE)                 (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
00525                                              ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
00526
00527 #define IS_CHANNEL_STATUS_MASK(VAL)          (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
00528                                               ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
00529 /**
00530   * @}
00531   */
00532
00533 /* Private functions ---------------------------------------------------------*/
00534 /** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
00535   * @{
00536   */
00537 /**
00538   * @}
00539   */
00540
00541 /**
00542   * @}
00543   */
00544
00545 /**
00546   * @}
00547   */
00548
00549 #ifdef __cplusplus
00550 }
00551 #endif
00552
00553
00554 #endif /* __STM32F7xx_HAL_SPDIFRX_H */
00555
00556 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:26 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spi.c Source File

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stm32f7xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The SPI HAL driver can be used as follows:
00020
00021       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00022           SPI_HandleTypeDef  hspi;
00023
00024       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
00025           (##) Enable the SPIx interface clock
00026           (##) SPI pins configuration
00027               (+++) Enable the clock for the SPI GPIOs
00028               (+++) Configure these SPI pins as alternate function push-pull
00029           (##) NVIC configuration if you need to use interrupt process
00030               (+++) Configure the SPIx interrupt priority
00031               (+++) Enable the NVIC SPI IRQ handle
00032           (##) DMA Configuration if you need to use DMA process
00033               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00034               (+++) Enable the DMAx clock
00035               (+++) Configure the DMA handle parameters
00036               (+++) Configure the DMA Tx or Rx channel
00037               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
00038               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
00039
00040       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00041           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00042
00043       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00044           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00045               by calling the customised HAL_SPI_MspInit() API.
00046      [..]
00047        Circular mode restriction:
00048       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00049           (##) Master 2Lines RxOnly
00050           (##) Master 1Line Rx
00051       (#) The CRC feature is not managed when the DMA circular mode is enabled
00052       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00053           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00054
00055   @endverbatim
00056   ******************************************************************************
00057   * @attention
00058   *
00059   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00060   *
00061   * Redistribution and use in source and binary forms, with or without modification,
00062   * are permitted provided that the following conditions are met:
00063   *   1. Redistributions of source code must retain the above copyright notice,
00064   *      this list of conditions and the following disclaimer.
00065   *   2. Redistributions in binary form must reproduce the above copyright notice,
00066   *      this list of conditions and the following disclaimer in the documentation
00067   *      and/or other materials provided with the distribution.
00068   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00069   *      may be used to endorse or promote products derived from this software
00070   *      without specific prior written permission.
00071   *
00072   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00073   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00074   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00075   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00076   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00077   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00078   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00079   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00080   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00081   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32f7xx_hal.h"
00088
00089 /** @addtogroup STM32F7xx_HAL_Driver
00090   * @{
00091   */
00092
00093 /** @defgroup SPI SPI
00094   * @brief SPI HAL module driver
00095   * @{
00096   */
00097 #ifdef HAL_SPI_MODULE_ENABLED
00098
00099 /* Private typedef -----------------------------------------------------------*/
00100 /* Private defines -----------------------------------------------------------*/
00101 /** @defgroup SPI_Private_Constants SPI Private Constants
00102   * @{
00103   */
00104 #define SPI_DEFAULT_TIMEOUT 50
00105 /**
00106   * @}
00107   */
00108
00109 /* Private macro -------------------------------------------------------------*/
00110 /* Private variables ---------------------------------------------------------*/
00111 /* Private function prototypes -----------------------------------------------*/
00112 /** @addtogroup SPI_Private_Functions
00113   * @{
00114   */
00115 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00116 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00117 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00118 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00119 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00120 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00121 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00122 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
00123 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
00124 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00125 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00126 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00127 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00128 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00129 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00130 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00131 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00132 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00133 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00134 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00135 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00136 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00137 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00138 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00139 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
00140 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions ---------------------------------------------------------*/
00146
00147 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00152  *  @brief    Initialization and Configuration functions
00153  *
00154 @verbatim
00155  ===============================================================================
00156               ##### Initialization and de-initialization functions #####
00157  ===============================================================================
00158     [..]  This subsection provides a set of functions allowing to initialize and
00159           de-initialize the SPIx peripheral:
00160
00161       (+) User must implement HAL_SPI_MspInit() function in which he configures
00162           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00163
00164       (+) Call the function HAL_SPI_Init() to configure the selected device with
00165           the selected configuration:
00166         (++) Mode
00167         (++) Direction
00168         (++) Data Size
00169         (++) Clock Polarity and Phase
00170         (++) NSS Management
00171         (++) BaudRate Prescaler
00172         (++) FirstBit
00173         (++) TIMode
00174         (++) CRC Calculation
00175         (++) CRC Polynomial if CRC enabled
00176         (++) CRC Length, used only with Data8 and Data16
00177         (++) FIFO reception threshold
00178
00179       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00180           of the selected SPIx peripheral.
00181
00182 @endverbatim
00183   * @{
00184   */
00185
00186 /**
00187   * @brief  Initializes the SPI according to the specified parameters
00188   *         in the SPI_InitTypeDef and create the associated handle.
00189   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00190   *               the configuration information for SPI module.
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00194 {
00195   uint32_t frxth;
00196
00197   /* Check the SPI handle allocation */
00198   if(hspi == NULL)
00199   {
00200     return HAL_ERROR;
00201   }
00202
00203   /* Check the parameters */
00204   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00205   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00206   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00207   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00208   assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00209   assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00210   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00211   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00212   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00213   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00214   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00215   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00216   assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00217   assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00218
00219   if(hspi->State == HAL_SPI_STATE_RESET)
00220   {
00221     /* Allocate lock resource and initialize it */
00222     hspi->Lock = HAL_UNLOCKED;
00223
00224     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00225     HAL_SPI_MspInit(hspi);
00226   }
00227
00228   hspi->State = HAL_SPI_STATE_BUSY;
00229
00230   /* Disable the selected SPI peripheral */
00231   __HAL_SPI_DISABLE(hspi);
00232
00233   /* Align by default the rs fifo threshold on the data size */
00234   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00235   {
00236     frxth = SPI_RXFIFO_THRESHOLD_HF;
00237   }
00238   else
00239   {
00240     frxth = SPI_RXFIFO_THRESHOLD_QF;
00241   }
00242
00243   /* CRC calculation is valid only for 16Bit and 8 Bit */
00244   if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
00245   {
00246     /* CRC must be disabled */
00247     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00248   }
00249
00250   /* Align the CRC Length on the data size */
00251   if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00252   {
00253     /* CRC Length aligned on the data size : value set by default */
00254     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00255     {
00256       hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00257     }
00258     else
00259     {
00260       hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
00261     }
00262   }
00263
00264   /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
00265   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00266   Communication speed, First bit, CRC calculation state, CRC Length */
00267   hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
00268                          hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00269                          hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
00270
00271   if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00272   {
00273     hspi->Instance->CR1|= SPI_CR1_CRCL;
00274   }
00275
00276   /* Configure : NSS management */
00277   /* Configure : Rx Fifo Threshold */
00278   hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
00279                          hspi->Init.DataSize ) | frxth;
00280
00281   /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
00282   /* Configure : CRC Polynomial */
00283   hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
00284
00285   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00286   hspi->State= HAL_SPI_STATE_READY;
00287
00288   return HAL_OK;
00289 }
00290
00291 /**
00292   * @brief  DeInitializes the SPI peripheral
00293   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00294   *               the configuration information for SPI module.
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00298 {
00299   /* Check the SPI handle allocation */
00300   if(hspi == NULL)
00301   {
00302     return HAL_ERROR;
00303   }
00304
00305   /* Check the parameters */
00306   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00307
00308   hspi->State = HAL_SPI_STATE_BUSY;
00309
00310   /* check flag before the SPI disable */
00311   SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
00312   SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
00313   SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
00314
00315   /* Disable the SPI Peripheral Clock */
00316   __HAL_SPI_DISABLE(hspi);
00317
00318   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00319   HAL_SPI_MspDeInit(hspi);
00320
00321   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00322   hspi->State = HAL_SPI_STATE_RESET;
00323
00324   __HAL_UNLOCK(hspi);
00325
00326   return HAL_OK;
00327 }
00328
00329 /**
00330   * @brief SPI MSP Init
00331   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00332   *               the configuration information for SPI module.
00333   * @retval None
00334   */
00335  __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00336  {
00337   /* Prevent unused argument(s) compilation warning */
00338   UNUSED(hspi);
00339
00340    /* NOTE : This function should not be modified, when the callback is needed,
00341             the HAL_SPI_MspInit should be implemented in the user file
00342    */
00343 }
00344
00345 /**
00346   * @brief SPI MSP DeInit
00347   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00348   *               the configuration information for SPI module.
00349   * @retval None
00350   */
00351  __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00352 {
00353   /* Prevent unused argument(s) compilation warning */
00354   UNUSED(hspi);
00355
00356   /* NOTE : This function should not be modified, when the callback is needed,
00357             the HAL_SPI_MspDeInit should be implemented in the user file
00358    */
00359 }
00360
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00366  *  @brief   Data transfers functions
00367  *
00368 @verbatim
00369   ==============================================================================
00370                       ##### IO operation functions #####
00371  ===============================================================================
00372     This subsection provides a set of functions allowing to manage the SPI
00373     data transfers.
00374
00375     [..] The SPI supports master and slave mode :
00376
00377     (#) There are two modes of transfer:
00378        (++) Blocking mode: The communication is performed in polling mode.
00379             The HAL status of all data processing is returned by the same function
00380             after finishing transfer.
00381        (++) No-Blocking mode: The communication is performed using Interrupts
00382            or DMA, These APIs return the HAL status.
00383            The end of the data processing will be indicated through the
00384            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00385            using DMA mode.
00386            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00387            will be executed respectively at the end of the transmit or Receive process
00388            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00389
00390     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00391         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00392
00393 @endverbatim
00394   * @{
00395   */
00396
00397 /**
00398   * @brief  Transmit an amount of data in blocking mode
00399   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00400   *               the configuration information for SPI module.
00401   * @param  pData: pointer to data buffer
00402   * @param  Size: amount of data to be sent
00403   * @param  Timeout: Timeout duration
00404   * @retval HAL status
00405   */
00406 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00407 {
00408   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00409
00410   /* Process Locked */
00411   __HAL_LOCK(hspi);
00412
00413   if(hspi->State != HAL_SPI_STATE_READY)
00414   {
00415     hspi->State = HAL_SPI_STATE_READY;
00416    /* Process Unlocked */
00417    __HAL_UNLOCK(hspi);
00418    return HAL_BUSY;
00419   }
00420
00421   if((pData == NULL ) || (Size == 0))
00422   {
00423     hspi->State = HAL_SPI_STATE_READY;
00424    /* Process Unlocked */
00425    __HAL_UNLOCK(hspi);
00426     return HAL_ERROR;
00427   }
00428
00429   /* Set the transaction information */
00430   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00431   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00432   hspi->pTxBuffPtr  = pData;
00433   hspi->TxXferSize  = Size;
00434   hspi->TxXferCount = Size;
00435   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00436   hspi->RxXferSize  = 0;
00437   hspi->RxXferCount = 0;
00438
00439   /* Configure communication direction : 1Line */
00440   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00441   {
00442     SPI_1LINE_TX(hspi);
00443   }
00444
00445   /* Reset CRC Calculation */
00446   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00447   {
00448     SPI_RESET_CRC(hspi);
00449   }
00450
00451   /* Check if the SPI is already enabled */
00452   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00453   {
00454     /* Enable SPI peripheral */
00455     __HAL_SPI_ENABLE(hspi);
00456   }
00457
00458   /* Transmit data in 16 Bit mode */
00459   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00460   {
00461     /* Transmit data in 16 Bit mode */
00462     while (hspi->TxXferCount > 0)
00463     {
00464       /* Wait until TXE flag is set to send data */
00465       if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
00466       {
00467         hspi->State = HAL_SPI_STATE_READY;
00468         /* Process Unlocked */
00469        __HAL_UNLOCK(hspi);
00470         return HAL_TIMEOUT;
00471       }
00472       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00473       hspi->pTxBuffPtr += sizeof(uint16_t);
00474       hspi->TxXferCount--;
00475     }
00476   }
00477   /* Transmit data in 8 Bit mode */
00478   else
00479   {
00480     while (hspi->TxXferCount > 0)
00481     {
00482       if(hspi->TxXferCount != 0x1)
00483       {
00484         /* Wait until TXE flag is set to send data */
00485         if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
00486         {
00487           hspi->State = HAL_SPI_STATE_READY;
00488           /* Process Unlocked */
00489           __HAL_UNLOCK(hspi);
00490           return HAL_TIMEOUT;
00491         }
00492         hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
00493         hspi->pTxBuffPtr += sizeof(uint16_t);
00494         hspi->TxXferCount -= 2;
00495       }
00496       else
00497       {
00498         /* Wait until TXE flag is set to send data */
00499         if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
00500         {
00501           return HAL_TIMEOUT;
00502         }
00503         *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
00504         hspi->TxXferCount--;
00505       }
00506     }
00507   }
00508
00509   /* Enable CRC Transmission */
00510   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00511   {
00512      hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
00513   }
00514
00515   /* Check the end of the transaction */
00516   if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
00517   {
00518     return HAL_TIMEOUT;
00519   }
00520
00521   /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
00522   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
00523   {
00524     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00525   }
00526
00527   hspi->State = HAL_SPI_STATE_READY;
00528
00529   /* Process Unlocked */
00530   __HAL_UNLOCK(hspi);
00531
00532   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00533   {
00534     return HAL_ERROR;
00535   }
00536   else
00537   {
00538     return HAL_OK;
00539   }
00540 }
00541
00542 /**
00543   * @brief  Receive an amount of data in blocking mode
00544   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00545   *               the configuration information for SPI module.
00546   * @param  pData: pointer to data buffer
00547   * @param  Size: amount of data to be received
00548   * @param  Timeout: Timeout duration
00549   * @retval HAL status
00550   */
00551 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00552 {
00553   __IO uint16_t tmpreg;
00554
00555   if(hspi->State != HAL_SPI_STATE_READY)
00556   {
00557     return HAL_BUSY;
00558   }
00559
00560   if((pData == NULL ) || (Size == 0))
00561   {
00562     return HAL_ERROR;
00563   }
00564
00565   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00566   {
00567     /* the receive process is not supported in 2Lines direction master mode */
00568     /* in this case we call the transmitReceive process                     */
00569     return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
00570   }
00571
00572   /* Process Locked */
00573   __HAL_LOCK(hspi);
00574
00575   hspi->State       = HAL_SPI_STATE_BUSY_RX;
00576   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00577   hspi->pRxBuffPtr  = pData;
00578   hspi->RxXferSize  = Size;
00579   hspi->RxXferCount = Size;
00580   hspi->pTxBuffPtr  = (uint8_t *)NULL;
00581   hspi->TxXferSize  = 0;
00582   hspi->TxXferCount = 0;
00583
00584   /* Reset CRC Calculation */
00585   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00586   {
00587     SPI_RESET_CRC(hspi);
00588     /* this is done to handle the CRCNEXT before the latest data */
00589     hspi->RxXferCount--;
00590   }
00591
00592   /* Set the Rx Fido threshold */
00593   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00594   {
00595     /* set fiforxthreshold according the reception data length: 16bit */
00596     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00597   }
00598   else
00599   {
00600     /* set fiforxthreshold according the reception data length: 8bit */
00601     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00602   }
00603
00604   /* Configure communication direction 1Line and enabled SPI if needed */
00605   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00606   {
00607     SPI_1LINE_RX(hspi);
00608   }
00609
00610   /* Check if the SPI is already enabled */
00611   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00612   {
00613     /* Enable SPI peripheral */
00614     __HAL_SPI_ENABLE(hspi);
00615   }
00616
00617   /* Receive data in 8 Bit mode */
00618   if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
00619   {
00620     while(hspi->RxXferCount > 1)
00621     {
00622       /* Wait until the RXNE flag */
00623       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00624       {
00625         return HAL_TIMEOUT;
00626       }
00627       (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
00628       hspi->RxXferCount--;
00629     }
00630   }
00631   else /* Receive data in 16 Bit mode */
00632   {
00633     while(hspi->RxXferCount > 1 )
00634     {
00635       /* Wait until RXNE flag is reset to read data */
00636       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00637       {
00638         return HAL_TIMEOUT;
00639       }
00640       *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
00641       hspi->pRxBuffPtr += sizeof(uint16_t);
00642       hspi->RxXferCount--;
00643     }
00644   }
00645
00646   /* Enable CRC Transmission */
00647   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00648   {
00649     hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
00650   }
00651
00652   /* Wait until RXNE flag is set */
00653   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00654   {
00655     return HAL_TIMEOUT;
00656   }
00657
00658   /* Receive last data in 16 Bit mode */
00659   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00660   {
00661     *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
00662     hspi->pRxBuffPtr += sizeof(uint16_t);
00663   }
00664   /* Receive last data in 8 Bit mode */
00665   else
00666   {
00667     (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
00668   }
00669   hspi->RxXferCount--;
00670
00671   /* Read CRC from DR to close CRC calculation process */
00672   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00673   {
00674     /* Wait until TXE flag */
00675     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00676     {
00677       /* Error on the CRC reception */
00678       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00679     }
00680     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00681     {
00682       tmpreg = hspi->Instance->DR;
00683       UNUSED(tmpreg); /* To avoid GCC warning */
00684     }
00685     else
00686     {
00687       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00688       UNUSED(tmpreg); /* To avoid GCC warning */
00689
00690       if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
00691       {
00692         if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00693         {
00694           /* Error on the CRC reception */
00695           hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
00696         }
00697         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00698         UNUSED(tmpreg); /* To avoid GCC warning */
00699       }
00700     }
00701   }
00702
00703   /* Check the end of the transaction */
00704   if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
00705   {
00706     return HAL_TIMEOUT;
00707   }
00708
00709   hspi->State = HAL_SPI_STATE_READY;
00710
00711   /* Check if CRC error occurred */
00712   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
00713   {
00714     hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00715     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00716
00717     /* Process Unlocked */
00718     __HAL_UNLOCK(hspi);
00719     return HAL_ERROR;
00720   }
00721
00722   /* Process Unlocked */
00723   __HAL_UNLOCK(hspi);
00724
00725   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00726   {
00727     return HAL_ERROR;
00728   }
00729   else
00730   {
00731     return HAL_OK;
00732   }
00733 }
00734
00735 /**
00736   * @brief  Transmit and Receive an amount of data in blocking mode
00737   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00738   *               the configuration information for SPI module.
00739   * @param  pTxData: pointer to transmission data buffer
00740   * @param  pRxData: pointer to reception data buffer
00741   * @param  Size: amount of data to be sent and received
00742   * @param  Timeout: Timeout duration
00743   * @retval HAL status
00744   */
00745 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00746 {
00747   __IO uint16_t tmpreg = 0;
00748   uint32_t tickstart = HAL_GetTick();
00749
00750   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
00751
00752   if(hspi->State != HAL_SPI_STATE_READY)
00753   {
00754     return HAL_BUSY;
00755   }
00756
00757   if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00758   {
00759     return HAL_ERROR;
00760   }
00761
00762
00763   /* Process Locked */
00764   __HAL_LOCK(hspi);
00765
00766   hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
00767   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00768   hspi->pRxBuffPtr  = pRxData;
00769   hspi->RxXferCount = Size;
00770   hspi->RxXferSize  = Size;
00771   hspi->pTxBuffPtr  = pTxData;
00772   hspi->TxXferCount = Size;
00773   hspi->TxXferSize  = Size;
00774
00775   /* Reset CRC Calculation */
00776   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00777   {
00778     SPI_RESET_CRC(hspi);
00779   }
00780
00781   /* Set the Rx Fido threshold */
00782   if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
00783   {
00784     /* set fiforxthreshold according the reception data length: 16bit */
00785     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00786   }
00787   else
00788   {
00789     /* set fiforxthreshold according the reception data length: 8bit */
00790     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00791   }
00792
00793   /* Check if the SPI is already enabled */
00794   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
00795   {
00796     /* Enable SPI peripheral */
00797     __HAL_SPI_ENABLE(hspi);
00798   }
00799
00800   /* Transmit and Receive data in 16 Bit mode */
00801   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00802   {
00803     while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
00804     {
00805       /* Check TXE flag */
00806       if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
00807       {
00808         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00809         hspi->pTxBuffPtr += sizeof(uint16_t);
00810         hspi->TxXferCount--;
00811
00812         /* Enable CRC Transmission */
00813         if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00814         {
00815           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00816         }
00817       }
00818
00819       /* Check RXNE flag */
00820       if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
00821       {
00822         *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
00823         hspi->pRxBuffPtr += sizeof(uint16_t);
00824         hspi->RxXferCount--;
00825       }
00826       if(Timeout != HAL_MAX_DELAY)
00827       {
00828         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00829         {
00830           hspi->State = HAL_SPI_STATE_READY;
00831           __HAL_UNLOCK(hspi);
00832           return HAL_TIMEOUT;
00833         }
00834       }
00835     }
00836   }
00837   /* Transmit and Receive data in 8 Bit mode */
00838   else
00839   {
00840     while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
00841     {
00842       /* check TXE flag */
00843       if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
00844       {
00845         if(hspi->TxXferCount > 1)
00846         {
00847           hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
00848           hspi->pTxBuffPtr += sizeof(uint16_t);
00849           hspi->TxXferCount -= 2;
00850         }
00851         else
00852         {
00853           *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
00854           hspi->TxXferCount--;
00855         }
00856
00857         /* Enable CRC Transmission */
00858         if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00859         {
00860           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00861         }
00862       }
00863
00864       /* Wait until RXNE flag is reset */
00865       if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
00866       {
00867         if(hspi->RxXferCount > 1)
00868         {
00869           *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
00870           hspi->pRxBuffPtr += sizeof(uint16_t);
00871           hspi->RxXferCount -= 2;
00872           if(hspi->RxXferCount <= 1)
00873           {
00874             /* set fiforxthreshold before to switch on 8 bit data size */
00875             SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00876           }
00877         }
00878         else
00879         {
00880           (*hspi->pRxBuffPtr++) =  *(__IO uint8_t *)&hspi->Instance->DR;
00881           hspi->RxXferCount--;
00882         }
00883       }
00884       if(Timeout != HAL_MAX_DELAY)
00885       {
00886         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00887         {
00888           hspi->State = HAL_SPI_STATE_READY;
00889           __HAL_UNLOCK(hspi);
00890           return HAL_TIMEOUT;
00891         }
00892       }
00893     }
00894   }
00895
00896   /* Read CRC from DR to close CRC calculation process */
00897   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00898   {
00899     /* Wait until TXE flag */
00900     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00901     {
00902       /* Error on the CRC reception */
00903       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00904     }
00905
00906     if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00907     {
00908       tmpreg = hspi->Instance->DR;
00909       UNUSED(tmpreg); /* To avoid GCC warning */
00910     }
00911     else
00912     {
00913       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00914       UNUSED(tmpreg); /* To avoid GCC warning */
00915
00916       if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00917       {
00918         if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00919         {
00920           /* Error on the CRC reception */
00921           hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00922         }
00923         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00924         UNUSED(tmpreg); /* To avoid GCC warning */
00925       }
00926     }
00927   }
00928
00929   /* Check the end of the transaction */
00930   if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
00931   {
00932     return HAL_TIMEOUT;
00933   }
00934
00935   hspi->State = HAL_SPI_STATE_READY;
00936
00937   /* Check if CRC error occurred */
00938   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
00939   {
00940     hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00941     /* Clear CRC Flag */
00942     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00943
00944     /* Process Unlocked */
00945     __HAL_UNLOCK(hspi);
00946
00947     return HAL_ERROR;
00948   }
00949
00950   /* Process Unlocked */
00951   __HAL_UNLOCK(hspi);
00952
00953   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00954   {
00955     return HAL_ERROR;
00956   }
00957   else
00958   {
00959     return HAL_OK;
00960   }
00961 }
00962
00963 /**
00964   * @brief  Transmit an amount of data in no-blocking mode with Interrupt
00965   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00966   *               the configuration information for SPI module.
00967   * @param  pData: pointer to data buffer
00968   * @param  Size: amount of data to be sent
00969   * @retval HAL status
00970   */
00971 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
00972 {
00973   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00974
00975   if(hspi->State == HAL_SPI_STATE_READY)
00976   {
00977     if((pData == NULL) || (Size == 0))
00978     {
00979       return  HAL_ERROR;
00980     }
00981
00982     /* Process Locked */
00983     __HAL_LOCK(hspi);
00984
00985     hspi->State       = HAL_SPI_STATE_BUSY_TX;
00986     hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00987     hspi->pTxBuffPtr  = pData;
00988     hspi->TxXferSize  = Size;
00989     hspi->TxXferCount = Size;
00990     hspi->pRxBuffPtr  = NULL;
00991     hspi->RxXferSize  = 0;
00992     hspi->RxXferCount = 0;
00993
00994     /* Set the function for IT treatement */
00995     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
00996     {
00997       hspi->RxISR = NULL;
00998       hspi->TxISR = SPI_TxISR_16BIT;
00999     }
01000     else
01001     {
01002       hspi->RxISR = NULL;
01003       hspi->TxISR = SPI_TxISR_8BIT;
01004     }
01005
01006     /* Configure communication direction : 1Line */
01007     if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01008     {
01009       SPI_1LINE_TX(hspi);
01010     }
01011
01012     /* Reset CRC Calculation */
01013     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01014     {
01015       SPI_RESET_CRC(hspi);
01016     }
01017
01018     /* Enable TXE and ERR interrupt */
01019     __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
01020
01021     /* Process Unlocked */
01022     __HAL_UNLOCK(hspi);
01023
01024     /* Note : The SPI must be enabled after unlocking current process
01025               to avoid the risk of SPI interrupt handle execution before current
01026               process unlock */
01027
01028     /* Check if the SPI is already enabled */
01029     if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01030     {
01031       /* Enable SPI peripheral */
01032       __HAL_SPI_ENABLE(hspi);
01033     }
01034
01035     return HAL_OK;
01036   }
01037   else
01038   {
01039     return HAL_BUSY;
01040   }
01041 }
01042
01043 /**
01044   * @brief  Receive an amount of data in no-blocking mode with Interrupt
01045   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01046   *               the configuration information for SPI module.
01047   * @param  pData: pointer to data buffer
01048   * @param  Size: amount of data to be sent
01049   * @retval HAL status
01050   */
01051 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01052 {
01053   if(hspi->State == HAL_SPI_STATE_READY)
01054   {
01055     if((pData == NULL) || (Size == 0))
01056     {
01057       return  HAL_ERROR;
01058     }
01059
01060     /* Process Locked */
01061     __HAL_LOCK(hspi);
01062
01063     /* Configure communication */
01064     hspi->State       = HAL_SPI_STATE_BUSY_RX;
01065     hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01066     hspi->pRxBuffPtr  = pData;
01067     hspi->RxXferSize  = Size;
01068     hspi->RxXferCount = Size;
01069     hspi->pTxBuffPtr  = NULL;
01070     hspi->TxXferSize  = 0;
01071     hspi->TxXferCount = 0;
01072
01073     if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
01074     {
01075       /* Process Unlocked */
01076       __HAL_UNLOCK(hspi);
01077       /* the receive process is not supported in 2Lines direction master mode */
01078       /* in this we call the transmitReceive process          */
01079       return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
01080     }
01081
01082     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01083     {
01084       hspi->CRCSize = 1;
01085       if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01086       {
01087         hspi->CRCSize = 2;
01088       }
01089     }
01090     else
01091     {
01092       hspi->CRCSize = 0;
01093     }
01094
01095     /* check the data size to adapt Rx threshold and the set the function for IT treatment */
01096     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01097     {
01098       /* set fiforxthreshold according the reception data length: 16 bit */
01099       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01100       hspi->RxISR = SPI_RxISR_16BIT;
01101       hspi->TxISR = NULL;
01102     }
01103     else
01104     {
01105       /* set fiforxthreshold according the reception data length: 8 bit */
01106       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01107       hspi->RxISR = SPI_RxISR_8BIT;
01108       hspi->TxISR = NULL;
01109     }
01110
01111     /* Configure communication direction : 1Line */
01112     if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01113     {
01114       SPI_1LINE_RX(hspi);
01115     }
01116
01117     /* Reset CRC Calculation */
01118     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01119     {
01120       SPI_RESET_CRC(hspi);
01121     }
01122
01123     /* Enable TXE and ERR interrupt */
01124     __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01125
01126     /* Process Unlocked */
01127     __HAL_UNLOCK(hspi);
01128
01129     /* Note : The SPI must be enabled after unlocking current process
01130     to avoid the risk of SPI interrupt handle execution before current
01131     process unlock */
01132
01133     /* Check if the SPI is already enabled */
01134     if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01135     {
01136       /* Enable SPI peripheral */
01137       __HAL_SPI_ENABLE(hspi);
01138     }
01139
01140     return HAL_OK;
01141   }
01142   else
01143   {
01144     return HAL_BUSY;
01145   }
01146 }
01147
01148 /**
01149   * @brief  Transmit and Receive an amount of data in no-blocking mode with Interrupt
01150   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01151   *               the configuration information for SPI module.
01152   * @param  pTxData: pointer to transmission data buffer
01153   * @param  pRxData: pointer to reception data buffer
01154   * @param  Size: amount of data to be sent and received
01155   * @retval HAL status
01156   */
01157 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01158 {
01159   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01160
01161   if((hspi->State == HAL_SPI_STATE_READY) || \
01162      ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
01163   {
01164     if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
01165     {
01166       return  HAL_ERROR;
01167     }
01168
01169     /* Process locked */
01170     __HAL_LOCK(hspi);
01171
01172     hspi->CRCSize = 0;
01173     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01174     {
01175       hspi->CRCSize = 1;
01176       if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01177       {
01178         hspi->CRCSize = 2;
01179       }
01180     }
01181
01182     if(hspi->State != HAL_SPI_STATE_BUSY_RX)
01183     {
01184       hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01185     }
01186
01187     hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01188     hspi->pTxBuffPtr  = pTxData;
01189     hspi->TxXferSize  = Size;
01190     hspi->TxXferCount = Size;
01191     hspi->pRxBuffPtr  = pRxData;
01192     hspi->RxXferSize  = Size;
01193     hspi->RxXferCount = Size;
01194
01195     /* Set the function for IT treatement */
01196     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01197     {
01198       hspi->RxISR = SPI_2linesRxISR_16BIT;
01199       hspi->TxISR = SPI_2linesTxISR_16BIT;
01200     }
01201     else
01202     {
01203       hspi->RxISR = SPI_2linesRxISR_8BIT;
01204       hspi->TxISR = SPI_2linesTxISR_8BIT;
01205     }
01206
01207     /* Reset CRC Calculation */
01208     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01209     {
01210       SPI_RESET_CRC(hspi);
01211     }
01212
01213     /* check if packing mode is enabled and if there is more than 2 data to receive */
01214     if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
01215     {
01216       /* set fiforxthreshold according the reception data length: 16 bit */
01217       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01218     }
01219     else
01220     {
01221       /* set fiforxthreshold according the reception data length: 8 bit */
01222       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01223     }
01224
01225     /* Enable TXE, RXNE and ERR interrupt */
01226     __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01227
01228     /* Process Unlocked */
01229     __HAL_UNLOCK(hspi);
01230
01231     /* Check if the SPI is already enabled */
01232     if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01233     {
01234       /* Enable SPI peripheral */
01235       __HAL_SPI_ENABLE(hspi);
01236     }
01237
01238     return HAL_OK;
01239   }
01240   else
01241   {
01242     return HAL_BUSY;
01243   }
01244 }
01245
01246 /**
01247   * @brief  Transmit an amount of data in no-blocking mode with DMA
01248   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01249   *               the configuration information for SPI module.
01250   * @param  pData: pointer to data buffer
01251   * @param  Size: amount of data to be sent
01252   * @retval HAL status
01253   */
01254 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01255 {
01256   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01257
01258   if(hspi->State != HAL_SPI_STATE_READY)
01259   {
01260     return HAL_BUSY;
01261   }
01262
01263   if((pData == NULL) || (Size == 0))
01264   {
01265     return HAL_ERROR;
01266   }
01267
01268   /* Process Locked */
01269   __HAL_LOCK(hspi);
01270
01271   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01272   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01273   hspi->pTxBuffPtr  = pData;
01274   hspi->TxXferSize  = Size;
01275   hspi->TxXferCount = Size;
01276   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01277   hspi->RxXferSize  = 0;
01278   hspi->RxXferCount = 0;
01279
01280   /* Configure communication direction : 1Line */
01281   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01282   {
01283     SPI_1LINE_TX(hspi);
01284   }
01285
01286   /* Reset CRC Calculation */
01287   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01288   {
01289     SPI_RESET_CRC(hspi);
01290   }
01291
01292   /* Set the SPI TxDMA Half transfer complete callback */
01293   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01294
01295   /* Set the SPI TxDMA transfer complete callback */
01296   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01297
01298   /* Set the DMA error callback */
01299   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01300
01301   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01302   /* packing mode is enabled only if the DMA setting is HALWORD */
01303   if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01304   {
01305     /* Check the even/odd of the data size + crc if enabled */
01306     if((hspi->TxXferCount & 0x1) == 0)
01307     {
01308       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01309       hspi->TxXferCount = (hspi->TxXferCount >> 1);
01310     }
01311     else
01312     {
01313       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01314       hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
01315     }
01316   }
01317
01318   /* Enable the Tx DMA channel */
01319   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01320
01321   /* Check if the SPI is already enabled */
01322   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01323   {
01324     /* Enable SPI peripheral */
01325     __HAL_SPI_ENABLE(hspi);
01326   }
01327
01328   /* Enable Tx DMA Request */
01329   hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
01330
01331   /* Process Unlocked */
01332   __HAL_UNLOCK(hspi);
01333
01334   return HAL_OK;
01335 }
01336
01337 /**
01338 * @brief  Receive an amount of data in no-blocking mode with DMA
01339 * @param  hspi: SPI handle
01340 * @param  pData: pointer to data buffer
01341 * @param  Size: amount of data to be sent
01342 * @retval HAL status
01343 */
01344 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01345 {
01346   if(hspi->State != HAL_SPI_STATE_READY)
01347   {
01348     return HAL_BUSY;
01349   }
01350
01351   if((pData == NULL) || (Size == 0))
01352   {
01353     return HAL_ERROR;
01354   }
01355
01356   /* Process Locked */
01357   __HAL_LOCK(hspi);
01358
01359   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01360   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01361   hspi->pRxBuffPtr  = pData;
01362   hspi->RxXferSize  = Size;
01363   hspi->RxXferCount = Size;
01364   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01365   hspi->TxXferSize  = 0;
01366   hspi->TxXferCount = 0;
01367
01368   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
01369   {
01370     /* Process Unlocked */
01371     __HAL_UNLOCK(hspi);
01372     /* the receive process is not supported in 2Lines direction master mode */
01373     /* in this case we call the transmitReceive process                     */
01374     return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
01375   }
01376
01377   /* Configure communication direction : 1Line */
01378   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01379   {
01380     SPI_1LINE_RX(hspi);
01381   }
01382
01383   /* Reset CRC Calculation */
01384   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01385   {
01386     SPI_RESET_CRC(hspi);
01387   }
01388
01389   /* packing mode management is enabled by the DMA settings */
01390   if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01391   {
01392     /* Process Locked */
01393     __HAL_UNLOCK(hspi);
01394     /* Restriction the DMA data received is not allowed in this mode */
01395     return HAL_ERROR;
01396   }
01397
01398   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01399   if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01400   {
01401     /* set fiforxthreshold according the reception data length: 16bit */
01402     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01403   }
01404   else
01405   {
01406     /* set fiforxthreshold according the reception data length: 8bit */
01407     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01408   }
01409
01410   /* Set the SPI RxDMA Half transfer complete callback */
01411   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01412
01413   /* Set the SPI Rx DMA transfer complete callback */
01414   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01415
01416   /* Set the DMA error callback */
01417   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01418
01419   /* Enable Rx DMA Request */
01420   hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
01421
01422   /* Enable the Rx DMA channel */
01423   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01424
01425   /* Process Unlocked */
01426   __HAL_UNLOCK(hspi);
01427
01428   /* Check if the SPI is already enabled */
01429   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01430   {
01431     /* Enable SPI peripheral */
01432     __HAL_SPI_ENABLE(hspi);
01433   }
01434
01435   return HAL_OK;
01436 }
01437
01438 /**
01439   * @brief  Transmit and Receive an amount of data in no-blocking mode with DMA
01440   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01441   *               the configuration information for SPI module.
01442   * @param  pTxData: pointer to transmission data buffer
01443   * @param  pRxData: pointer to reception data buffer
01444   * @note  When the CRC feature is enabled the pRxData Length must be Size + 1
01445   * @param  Size: amount of data to be sent
01446   * @retval HAL status
01447   */
01448 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01449 {
01450   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01451
01452   if((hspi->State == HAL_SPI_STATE_READY) ||
01453      ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
01454   {
01455     if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
01456     {
01457       return  HAL_ERROR;
01458     }
01459
01460     /* Process locked */
01461     __HAL_LOCK(hspi);
01462
01463     /* check if the transmit Receive function is not called by a receive master */
01464     if(hspi->State != HAL_SPI_STATE_BUSY_RX)
01465     {
01466       hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01467     }
01468
01469     hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01470     hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01471     hspi->TxXferSize  = Size;
01472     hspi->TxXferCount = Size;
01473     hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01474     hspi->RxXferSize  = Size;
01475     hspi->RxXferCount = Size;
01476
01477     /* Reset CRC Calculation + increase the rxsize */
01478     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01479     {
01480       SPI_RESET_CRC(hspi);
01481     }
01482
01483     /* Reset the threshold bit */
01484     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01485     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01486
01487     /* the packing mode management is enabled by the DMA settings according the spi data size */
01488     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01489     {
01490       /* set fiforxthreshold according the reception data length: 16bit */
01491       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01492     }
01493     else
01494     {
01495       /* set fiforxthreshold according the reception data length: 8bit */
01496       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01497
01498       if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01499       {
01500         if((hspi->TxXferSize & 0x1) == 0x0 )
01501         {
01502           CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01503           hspi->TxXferCount = hspi->TxXferCount >> 1;
01504         }
01505         else
01506         {
01507           SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01508           hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
01509         }
01510       }
01511
01512       if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01513       {
01514         /* set fiforxthreshold according the reception data length: 16bit */
01515         CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01516
01517         /* Size must include the CRC length */
01518         if((hspi->RxXferCount & 0x1) == 0x0 )
01519         {
01520           CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01521           hspi->RxXferCount = hspi->RxXferCount >> 1;
01522         }
01523         else
01524         {
01525           SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01526           hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
01527         }
01528       }
01529     }
01530
01531     /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
01532     the reception request (RXNE) */
01533     if(hspi->State == HAL_SPI_STATE_BUSY_RX)
01534     {
01535       hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01536       hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01537     }
01538     else
01539     {
01540        hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
01541       hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
01542     }
01543     /* Set the DMA error callback */
01544     hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01545
01546     /* Enable Rx DMA Request */
01547     hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
01548
01549     /* Enable the Rx DMA channel */
01550     HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
01551
01552     /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
01553     is performed in DMA reception complete callback  */
01554     hspi->hdmatx->XferHalfCpltCallback = NULL;
01555     hspi->hdmatx->XferCpltCallback = NULL;
01556
01557     if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
01558     {
01559       /* Set the DMA error callback */
01560       hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01561     }
01562     else
01563     {
01564       hspi->hdmatx->XferErrorCallback = NULL;
01565     }
01566
01567     /* Enable the Tx DMA channel */
01568     HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01569
01570     /* Process Unlocked */
01571     __HAL_UNLOCK(hspi);
01572
01573     /* Check if the SPI is already enabled */
01574     if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01575     {
01576       /* Enable SPI peripheral */
01577       __HAL_SPI_ENABLE(hspi);
01578     }
01579
01580     /* Enable Tx DMA Request */
01581     hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
01582
01583     return HAL_OK;
01584   }
01585   else
01586   {
01587     return HAL_BUSY;
01588   }
01589 }
01590
01591 /**
01592   * @brief Pauses the DMA Transfer.
01593   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01594   *               the configuration information for the specified SPI module.
01595   * @retval HAL status
01596   */
01597 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
01598 {
01599   /* Process Locked */
01600   __HAL_LOCK(hspi);
01601
01602   /* Disable the SPI DMA Tx & Rx requests */
01603   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01604
01605   /* Process Unlocked */
01606   __HAL_UNLOCK(hspi);
01607
01608   return HAL_OK;
01609 }
01610
01611 /**
01612   * @brief Resumes the DMA Transfer.
01613   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01614   *               the configuration information for the specified SPI module.
01615   * @retval HAL status
01616   */
01617 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
01618 {
01619   /* Process Locked */
01620   __HAL_LOCK(hspi);
01621
01622   /* Enable the SPI DMA Tx & Rx requests */
01623   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01624
01625   /* Process Unlocked */
01626   __HAL_UNLOCK(hspi);
01627
01628   return HAL_OK;
01629 }
01630
01631 /**
01632   * @brief Stops the DMA Transfer.
01633   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01634   *               the configuration information for the specified SPI module.
01635   * @retval HAL status
01636   */
01637 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
01638 {
01639   /* The Lock is not implemented on this API to allow the user application
01640      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
01641      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01642      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
01643      */
01644
01645   /* Abort the SPI DMA tx Stream */
01646   if(hspi->hdmatx != NULL)
01647   {
01648     HAL_DMA_Abort(hspi->hdmatx);
01649   }
01650   /* Abort the SPI DMA rx Stream */
01651   if(hspi->hdmarx != NULL)
01652   {
01653     HAL_DMA_Abort(hspi->hdmarx);
01654   }
01655
01656   /* Disable the SPI DMA Tx & Rx requests */
01657   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01658   hspi->State = HAL_SPI_STATE_READY;
01659   return HAL_OK;
01660 }
01661
01662 /**
01663   * @brief  This function handles SPI interrupt request.
01664   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01665   *               the configuration information for the specified SPI module.
01666   * @retval None
01667   */
01668 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
01669 {
01670   /* SPI in mode Receiver ----------------------------------------------------*/
01671   if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
01672      (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
01673   {
01674     hspi->RxISR(hspi);
01675     return;
01676   }
01677
01678   /* SPI in mode Transmitter ---------------------------------------------------*/
01679   if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
01680   {
01681     hspi->TxISR(hspi);
01682     return;
01683   }
01684
01685   /* SPI in ERROR Treatment ---------------------------------------------------*/
01686   if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
01687   {
01688     /* SPI Overrun error interrupt occurred -------------------------------------*/
01689     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
01690     {
01691       if(hspi->State != HAL_SPI_STATE_BUSY_TX)
01692       {
01693         hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
01694         __HAL_SPI_CLEAR_OVRFLAG(hspi);
01695       }
01696       else
01697       {
01698         return;
01699       }
01700     }
01701
01702     /* SPI Mode Fault error interrupt occurred -------------------------------------*/
01703     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
01704     {
01705       hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
01706       __HAL_SPI_CLEAR_MODFFLAG(hspi);
01707     }
01708
01709     /* SPI Frame error interrupt occurred ----------------------------------------*/
01710     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
01711     {
01712       hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
01713       __HAL_SPI_CLEAR_FREFLAG(hspi);
01714     }
01715
01716     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
01717     hspi->State = HAL_SPI_STATE_READY;
01718     HAL_SPI_ErrorCallback(hspi);
01719
01720     return;
01721   }
01722 }
01723
01724 /**
01725   * @brief Tx Transfer completed callback
01726   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01727   *               the configuration information for SPI module.
01728   * @retval None
01729   */
01730 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
01731 {
01732   /* Prevent unused argument(s) compilation warning */
01733   UNUSED(hspi);
01734
01735   /* NOTE : This function should not be modified, when the callback is needed,
01736             the HAL_SPI_TxCpltCallback should be implemented in the user file
01737    */
01738 }
01739
01740 /**
01741   * @brief Rx Transfer completed callbacks
01742   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01743   *               the configuration information for SPI module.
01744   * @retval None
01745   */
01746 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
01747 {
01748   /* Prevent unused argument(s) compilation warning */
01749   UNUSED(hspi);
01750
01751   /* NOTE : This function should not be modified, when the callback is needed,
01752             the HAL_SPI_RxCpltCallback should be implemented in the user file
01753    */
01754 }
01755
01756 /**
01757   * @brief Tx and Rx Transfer completed callback
01758   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01759   *               the configuration information for SPI module.
01760   * @retval None
01761   */
01762 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
01763 {
01764   /* Prevent unused argument(s) compilation warning */
01765   UNUSED(hspi);
01766
01767   /* NOTE : This function should not be modified, when the callback is needed,
01768             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
01769    */
01770 }
01771
01772 /**
01773   * @brief Tx Half Transfer completed callback
01774   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01775   *               the configuration information for SPI module.
01776   * @retval None
01777   */
01778 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01779 {
01780   /* Prevent unused argument(s) compilation warning */
01781   UNUSED(hspi);
01782
01783   /* NOTE : This function should not be modified, when the callback is needed,
01784             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
01785    */
01786 }
01787
01788 /**
01789   * @brief Rx Half Transfer completed callback
01790   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01791   *               the configuration information for SPI module.
01792   * @retval None
01793   */
01794 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01795 {
01796   /* Prevent unused argument(s) compilation warning */
01797   UNUSED(hspi);
01798
01799   /* NOTE : This function should not be modified, when the callback is needed,
01800             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
01801    */
01802 }
01803
01804 /**
01805   * @brief Tx and Rx Half Transfer callback
01806   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01807   *               the configuration information for SPI module.
01808   * @retval None
01809   */
01810 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01811 {
01812   /* Prevent unused argument(s) compilation warning */
01813   UNUSED(hspi);
01814
01815   /* NOTE : This function should not be modified, when the callback is needed,
01816             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
01817    */
01818 }
01819
01820 /**
01821   * @brief SPI error callback
01822   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01823   *               the configuration information for SPI module.
01824   * @retval None
01825   */
01826  __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
01827 {
01828   /* Prevent unused argument(s) compilation warning */
01829   UNUSED(hspi);
01830
01831   /* NOTE : This function should not be modified, when the callback is needed,
01832             the HAL_SPI_ErrorCallback should be implemented in the user file
01833    */
01834   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
01835             and user can use HAL_SPI_GetError() API to check the latest error occurred
01836    */
01837 }
01838
01839 /**
01840   * @}
01841   */
01842
01843 /**
01844   * @}
01845   */
01846
01847 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
01848   *  @brief   SPI control functions
01849   *
01850 @verbatim
01851  ===============================================================================
01852                       ##### Peripheral State and Errors functions #####
01853  ===============================================================================
01854     [..]
01855     This subsection provides a set of functions allowing to control the SPI.
01856      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
01857      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
01858 @endverbatim
01859   * @{
01860   */
01861
01862 /**
01863   * @brief  Return the SPI state
01864   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01865   *               the configuration information for SPI module.
01866   * @retval SPI state
01867   */
01868 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
01869 {
01870   return hspi->State;
01871 }
01872
01873 /**
01874   * @brief  Return the SPI error code
01875   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01876   *               the configuration information for SPI module.
01877   * @retval SPI error code in bitmap format
01878   */
01879 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
01880 {
01881   return hspi->ErrorCode;
01882 }
01883
01884 /**
01885   * @}
01886   */
01887
01888 /**
01889   * @}
01890   */
01891
01892 /** @defgroup SPI_Private_Functions SPI Private Functions
01893   * @{
01894   */
01895
01896 /**
01897   * @brief DMA SPI transmit process complete callback
01898   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01899   *               the configuration information for the specified DMA module.
01900   * @retval None
01901   */
01902 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01903 {
01904   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01905
01906   /* DMA Normal Mode */
01907   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01908   {
01909     /* Disable Tx DMA Request */
01910     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01911
01912     /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
01913     if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
01914     {
01915       __HAL_SPI_CLEAR_OVRFLAG(hspi);
01916     }
01917
01918     hspi->TxXferCount = 0;
01919     hspi->State = HAL_SPI_STATE_READY;
01920
01921     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01922     {
01923       HAL_SPI_ErrorCallback(hspi);
01924       return;
01925     }
01926   }
01927   HAL_SPI_TxCpltCallback(hspi);
01928 }
01929
01930 /**
01931   * @brief DMA SPI receive process complete callback
01932   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01933   *               the configuration information for the specified DMA module.
01934   * @retval None
01935   */
01936 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01937 {
01938   __IO uint16_t tmpreg;
01939   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01940
01941   /* DMA Normal mode */
01942   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01943   {
01944     /* CRC handling */
01945     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01946     {
01947       /* Wait until TXE flag */
01948       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
01949       {
01950         /* Error on the CRC reception */
01951         hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
01952       }
01953       if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01954       {
01955         tmpreg = hspi->Instance->DR;
01956         UNUSED(tmpreg); /* To avoid GCC warning */
01957       }
01958       else
01959       {
01960         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
01961         UNUSED(tmpreg); /* To avoid GCC warning */
01962
01963         if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
01964         {
01965           if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
01966           {
01967             /* Error on the CRC reception */
01968             hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
01969           }
01970           tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
01971           UNUSED(tmpreg); /* To avoid GCC warning */
01972         }
01973       }
01974     }
01975
01976     /* Disable Rx DMA Request */
01977     hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01978     /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
01979     hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01980
01981     /* Check the end of the transaction */
01982     SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
01983
01984     hspi->RxXferCount = 0;
01985     hspi->State = HAL_SPI_STATE_READY;
01986
01987     /* Check if CRC error occurred */
01988     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
01989     {
01990       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
01991       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01992       HAL_SPI_RxCpltCallback(hspi);
01993     }
01994     else
01995     {
01996       if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
01997       {
01998         HAL_SPI_RxCpltCallback(hspi);
01999       }
02000       else
02001       {
02002         HAL_SPI_ErrorCallback(hspi);
02003       }
02004     }
02005   }
02006   else
02007   {
02008     HAL_SPI_RxCpltCallback(hspi);
02009   }
02010 }
02011
02012 /**
02013   * @brief DMA SPI transmit receive process complete callback
02014   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02015   *               the configuration information for the specified DMA module.
02016   * @retval None
02017   */
02018 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02019 {
02020   __IO int16_t tmpreg;
02021   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02022
02023   /* CRC handling */
02024   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02025   {
02026     if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
02027     {
02028       if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
02029       {
02030         /* Error on the CRC reception */
02031         hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02032       }
02033       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
02034       UNUSED(tmpreg); /* To avoid GCC warning */
02035     }
02036     else
02037     {
02038       if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
02039       {
02040         /* Error on the CRC reception */
02041         hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02042       }
02043       tmpreg = hspi->Instance->DR;
02044       UNUSED(tmpreg); /* To avoid GCC warning */
02045     }
02046   }
02047
02048   /* Check the end of the transaction */
02049   SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
02050
02051   /* Disable Tx DMA Request */
02052   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02053
02054   /* Disable Rx DMA Request */
02055   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02056
02057   hspi->TxXferCount = 0;
02058   hspi->RxXferCount = 0;
02059   hspi->State = HAL_SPI_STATE_READY;
02060
02061   /* Check if CRC error occurred */
02062   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02063   {
02064     hspi->ErrorCode = HAL_SPI_ERROR_CRC;
02065     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02066     HAL_SPI_ErrorCallback(hspi);
02067   }
02068   else
02069   {
02070     if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02071     {
02072       HAL_SPI_TxRxCpltCallback(hspi);
02073     }
02074     else
02075     {
02076       HAL_SPI_ErrorCallback(hspi);
02077     }
02078   }
02079 }
02080
02081 /**
02082   * @brief DMA SPI half transmit process complete callback
02083   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02084   *               the configuration information for the specified DMA module.
02085   * @retval None
02086   */
02087 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
02088 {
02089   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02090
02091   HAL_SPI_TxHalfCpltCallback(hspi);
02092 }
02093
02094 /**
02095   * @brief DMA SPI half receive process complete callback
02096   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02097   *               the configuration information for the specified DMA module.
02098   * @retval None
02099   */
02100 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
02101 {
02102   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02103
02104   HAL_SPI_RxHalfCpltCallback(hspi);
02105 }
02106
02107 /**
02108   * @brief DMA SPI Half transmit receive process complete callback
02109   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02110   *               the configuration information for the specified DMA module.
02111   * @retval None
02112   */
02113 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02114 {
02115   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02116
02117   HAL_SPI_TxRxHalfCpltCallback(hspi);
02118 }
02119
02120 /**
02121   * @brief DMA SPI communication error callback
02122   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02123   *               the configuration information for the specified DMA module.
02124   * @retval None
02125   */
02126 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
02127 {
02128   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02129
02130   /* Stop the disable DMA transfer on SPI side */
02131   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02132
02133   hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
02134   hspi->State = HAL_SPI_STATE_READY;
02135   HAL_SPI_ErrorCallback(hspi);
02136 }
02137
02138 /**
02139   * @brief  Rx Handler for Transmit and Receive in Interrupt mode
02140   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02141   *               the configuration information for SPI module.
02142   * @retval None
02143   */
02144 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02145 {
02146   /* Receive data in packing mode */
02147   if(hspi->RxXferCount > 1)
02148   {
02149     *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
02150     hspi->pRxBuffPtr += sizeof(uint16_t);
02151     hspi->RxXferCount -= 2;
02152     if(hspi->RxXferCount == 1)
02153     {
02154       /* set fiforxthreshold according the reception data length: 8bit */
02155       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02156     }
02157   }
02158   /* Receive data in 8 Bit mode */
02159   else
02160   {
02161     *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
02162     hspi->RxXferCount--;
02163   }
02164
02165   /* check end of the reception */
02166   if(hspi->RxXferCount == 0)
02167   {
02168     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02169     {
02170       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02171       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
02172       return;
02173     }
02174
02175     /* Disable RXNE interrupt */
02176     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02177
02178     if(hspi->TxXferCount == 0)
02179     {
02180       SPI_CloseRxTx_ISR(hspi);
02181     }
02182   }
02183 }
02184
02185 /**
02186   * @brief  Rx Handler for Transmit and Receive in Interrupt mode
02187   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02188   *               the configuration information for SPI module.
02189   * @retval None
02190   */
02191 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02192 {
02193   __IO uint8_t tmpreg;
02194
02195   tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
02196   UNUSED(tmpreg); /* To avoid GCC warning */
02197
02198   hspi->CRCSize--;
02199
02200   /* check end of the reception */
02201   if(hspi->CRCSize == 0)
02202   {
02203     /* Disable RXNE interrupt */
02204     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02205
02206     if(hspi->TxXferCount == 0)
02207     {
02208       SPI_CloseRxTx_ISR(hspi);
02209     }
02210   }
02211 }
02212
02213 /**
02214   * @brief  Tx Handler for Transmit and Receive in Interrupt mode
02215   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02216   *               the configuration information for SPI module.
02217   * @retval None
02218   */
02219 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02220 {
02221   /* Transmit data in packing Bit mode */
02222   if(hspi->TxXferCount >= 2)
02223   {
02224     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02225     hspi->pTxBuffPtr += sizeof(uint16_t);
02226     hspi->TxXferCount -= 2;
02227   }
02228   /* Transmit data in 8 Bit mode */
02229   else
02230   {
02231     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02232     hspi->TxXferCount--;
02233   }
02234
02235   /* check the end of the transmission */
02236   if(hspi->TxXferCount == 0)
02237   {
02238     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02239     {
02240       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02241     }
02242     /* Disable TXE interrupt */
02243     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02244
02245     if(hspi->RxXferCount == 0)
02246     {
02247       SPI_CloseRxTx_ISR(hspi);
02248     }
02249   }
02250 }
02251
02252 /**
02253   * @brief  Rx 16Bit Handler for Transmit and Receive in Interrupt mode
02254   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02255   *               the configuration information for SPI module.
02256   * @retval None
02257   */
02258 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02259 {
02260   /* Receive data in 16 Bit mode */
02261   *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
02262   hspi->pRxBuffPtr += sizeof(uint16_t);
02263   hspi->RxXferCount--;
02264
02265   if(hspi->RxXferCount == 0)
02266   {
02267     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02268     {
02269       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
02270       return;
02271     }
02272
02273     /* Disable RXNE interrupt */
02274     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02275
02276     if(hspi->TxXferCount == 0)
02277     {
02278       SPI_CloseRxTx_ISR(hspi);
02279     }
02280   }
02281 }
02282
02283 /**
02284   * @brief  Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
02285   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02286   *               the configuration information for SPI module.
02287   * @retval None
02288   */
02289 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02290 {
02291   /* Receive data in 16 Bit mode */
02292   __IO uint16_t tmpreg = hspi->Instance->DR;
02293   UNUSED(tmpreg); /* To avoid GCC warning */
02294
02295   /* Disable RXNE interrupt */
02296   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02297
02298   SPI_CloseRxTx_ISR(hspi);
02299 }
02300
02301 /**
02302   * @brief  Tx Handler for Transmit and Receive in Interrupt mode
02303   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02304   *               the configuration information for SPI module.
02305   * @retval None
02306   */
02307 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02308 {
02309   /* Transmit data in 16 Bit mode */
02310   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02311   hspi->pTxBuffPtr += sizeof(uint16_t);
02312   hspi->TxXferCount--;
02313
02314   /* Enable CRC Transmission */
02315   if(hspi->TxXferCount == 0)
02316   {
02317     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02318     {
02319       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02320     }
02321     /* Disable TXE interrupt */
02322     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02323
02324     if(hspi->RxXferCount == 0)
02325     {
02326       SPI_CloseRxTx_ISR(hspi);
02327     }
02328   }
02329 }
02330
02331 /**
02332   * @brief  Manage the CRC receive in Interrupt context
02333   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02334   *               the configuration information for SPI module.
02335   * @retval None
02336   */
02337 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02338 {
02339   __IO uint8_t tmpreg;
02340   tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
02341   UNUSED(tmpreg); /* To avoid GCC warning */
02342
02343   hspi->CRCSize--;
02344
02345   if(hspi->CRCSize == 0)
02346   {
02347     SPI_CloseRx_ISR(hspi);
02348   }
02349 }
02350
02351 /**
02352   * @brief  Manage the receive in Interrupt context
02353   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02354   *               the configuration information for SPI module.
02355   * @retval None
02356   */
02357 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02358 {
02359   *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
02360   hspi->RxXferCount--;
02361
02362   /* Enable CRC Transmission */
02363   if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02364   {
02365     hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02366   }
02367
02368   if(hspi->RxXferCount == 0)
02369   {
02370     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02371     {
02372       hspi->RxISR =  SPI_RxISR_8BITCRC;
02373       return;
02374     }
02375     SPI_CloseRx_ISR(hspi);
02376   }
02377 }
02378
02379 /**
02380   * @brief  Manage the CRC 16bit receive in Interrupt context
02381   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02382   *               the configuration information for SPI module.
02383   * @retval None
02384   */
02385 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02386 {
02387   __IO uint16_t tmpreg;
02388
02389   tmpreg = hspi->Instance->DR;
02390   UNUSED(tmpreg); /* To avoid GCC warning */
02391
02392   /* Disable RXNE and ERR interrupt */
02393   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02394
02395   SPI_CloseRx_ISR(hspi);
02396 }
02397
02398 /**
02399   * @brief  Manage the 16Bit receive in Interrupt context
02400   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02401   *               the configuration information for SPI module.
02402   * @retval None
02403   */
02404 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02405 {
02406   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
02407   hspi->pRxBuffPtr += sizeof(uint16_t);
02408   hspi->RxXferCount--;
02409
02410   /* Enable CRC Transmission */
02411   if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02412   {
02413     hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02414   }
02415
02416   if(hspi->RxXferCount == 0)
02417   {
02418     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02419     {
02420       hspi->RxISR = SPI_RxISR_16BITCRC;
02421       return;
02422     }
02423     SPI_CloseRx_ISR(hspi);
02424   }
02425 }
02426
02427 /**
02428   * @brief  Handle the data 8Bit transmit in Interrupt mode
02429   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02430   *               the configuration information for SPI module.
02431   * @retval None
02432   */
02433 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02434 {
02435   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02436   hspi->TxXferCount--;
02437
02438   if(hspi->TxXferCount == 0)
02439   {
02440     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02441     {
02442       /* Enable CRC Transmission */
02443       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02444     }
02445     SPI_CloseTx_ISR(hspi);
02446   }
02447 }
02448
02449 /**
02450   * @brief  Handle the data 16Bit transmit in Interrupt mode
02451   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02452   *               the configuration information for SPI module.
02453   * @retval None
02454   */
02455 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02456 {
02457   /* Transmit data in 16 Bit mode */
02458   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02459   hspi->pTxBuffPtr += sizeof(uint16_t);
02460   hspi->TxXferCount--;
02461
02462   if(hspi->TxXferCount == 0)
02463   {
02464     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02465     {
02466       /* Enable CRC Transmission */
02467       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02468     }
02469     SPI_CloseTx_ISR(hspi);
02470   }
02471 }
02472
02473 /**
02474   * @brief This function handles SPI Communication Timeout.
02475   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02476   *               the configuration information for SPI module.
02477   * @param Flag : SPI flag to check
02478   * @param State : flag state to check
02479   * @param Timeout : Timeout duration
02480   * @retval HAL status
02481   */
02482 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
02483 {
02484   uint32_t tickstart = HAL_GetTick();
02485
02486   while((hspi->Instance->SR & Flag) != State)
02487   {
02488     if(Timeout != HAL_MAX_DELAY)
02489     {
02490       if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
02491       {
02492         /* Disable the SPI and reset the CRC: the CRC value should be cleared
02493         on both master and slave sides in order to resynchronize the master
02494         and slave for their respective CRC calculation */
02495
02496         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
02497         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
02498
02499         if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02500         {
02501           /* Disable SPI peripheral */
02502           __HAL_SPI_DISABLE(hspi);
02503         }
02504
02505         /* Reset CRC Calculation */
02506         if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02507         {
02508           SPI_RESET_CRC(hspi);
02509         }
02510
02511         hspi->State= HAL_SPI_STATE_READY;
02512
02513         /* Process Unlocked */
02514         __HAL_UNLOCK(hspi);
02515
02516         return HAL_TIMEOUT;
02517       }
02518     }
02519   }
02520
02521   return HAL_OK;
02522 }
02523
02524 /**
02525   * @brief This function handles SPI Communication Timeout.
02526   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02527   *               the configuration information for SPI module.
02528   * @param Fifo : Fifo to check
02529   * @param State : Fifo state to check
02530   * @param Timeout : Timeout duration
02531   * @retval HAL status
02532   */
02533 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
02534 {
02535   __IO uint8_t tmpreg;
02536   uint32_t tickstart = HAL_GetTick();
02537
02538   while((hspi->Instance->SR & Fifo) != State)
02539   {
02540     if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
02541     {
02542       tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
02543       UNUSED(tmpreg); /* To avoid GCC warning */
02544     }
02545
02546     if(Timeout != HAL_MAX_DELAY)
02547     {
02548       if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
02549       {
02550         /* Disable the SPI and reset the CRC: the CRC value should be cleared
02551                   on both master and slave sides in order to resynchronize the master
02552                  and slave for their respective CRC calculation */
02553
02554         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
02555         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
02556
02557         if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02558         {
02559           /* Disable SPI peripheral */
02560           __HAL_SPI_DISABLE(hspi);
02561         }
02562
02563         /* Reset CRC Calculation */
02564         if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02565         {
02566           SPI_RESET_CRC(hspi);
02567         }
02568
02569         hspi->State = HAL_SPI_STATE_READY;
02570
02571         /* Process Unlocked */
02572         __HAL_UNLOCK(hspi);
02573
02574         return HAL_TIMEOUT;
02575       }
02576     }
02577   }
02578
02579   return HAL_OK;
02580 }
02581
02582 /**
02583   * @brief This function handles the check of the RX transaction complete.
02584   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02585   *               the configuration information for SPI module.
02586   * @param Timeout : Timeout duration
02587   * @retval None
02588   */
02589 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout)
02590 {
02591   if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02592   {
02593     /* Disable SPI peripheral */
02594     __HAL_SPI_DISABLE(hspi);
02595   }
02596   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
02597   {
02598     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02599     return HAL_TIMEOUT;
02600   }
02601   if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
02602   {
02603     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02604     return HAL_TIMEOUT;
02605   }
02606
02607   return HAL_OK;
02608 }
02609
02610 /**
02611   * @brief This function handles the check of the RXTX or TX transaction complete.
02612   * @param hspi: SPI handle
02613   * @param Timeout : Timeout duration
02614   */
02615 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
02616 {
02617   /* Procedure to check the transaction complete */
02618   if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
02619   {
02620     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02621     return HAL_TIMEOUT;
02622   }
02623   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
02624   {
02625     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02626     return HAL_TIMEOUT;
02627   }
02628   if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
02629   {
02630     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02631     return HAL_TIMEOUT;
02632   }
02633   return HAL_OK;
02634 }
02635
02636 /**
02637   * @brief This function handles the close of the RXTX transaction.
02638   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02639   *               the configuration information for SPI module.
02640   * @retval None
02641   */
02642 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
02643 {
02644   /* Disable ERR interrupt */
02645   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02646
02647   /* Check if CRC error occurred */
02648   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02649   {
02650     hspi->State = HAL_SPI_STATE_READY;
02651     hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02652     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02653     HAL_SPI_ErrorCallback(hspi);
02654   }
02655   else
02656   {
02657     if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02658     {
02659       if(hspi->State == HAL_SPI_STATE_BUSY_RX)
02660       {
02661         hspi->State = HAL_SPI_STATE_READY;
02662         HAL_SPI_RxCpltCallback(hspi);
02663       }
02664       else
02665       {
02666         hspi->State = HAL_SPI_STATE_READY;
02667         HAL_SPI_TxRxCpltCallback(hspi);
02668       }
02669     }
02670     else
02671     {
02672       hspi->State = HAL_SPI_STATE_READY;
02673       HAL_SPI_ErrorCallback(hspi);
02674     }
02675   }
02676 }
02677
02678 /**
02679   * @brief This function handles the close of the RX transaction.
02680   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02681   *               the configuration information for SPI module.
02682   * @retval None
02683   */
02684 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
02685 {
02686     /* Disable RXNE and ERR interrupt */
02687     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02688
02689     /* Check the end of the transaction */
02690     SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
02691
02692     hspi->State = HAL_SPI_STATE_READY;
02693
02694     /* Check if CRC error occurred */
02695     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02696     {
02697       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02698       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02699       HAL_SPI_ErrorCallback(hspi);
02700     }
02701     else
02702     {
02703       if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02704       {
02705         HAL_SPI_RxCpltCallback(hspi);
02706       }
02707       else
02708       {
02709         HAL_SPI_ErrorCallback(hspi);
02710       }
02711     }
02712 }
02713
02714 /**
02715   * @brief This function handles the close of the TX transaction.
02716   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02717   *               the configuration information for SPI module.
02718   * @retval None
02719   */
02720 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
02721 {
02722   /* Disable TXE and ERR interrupt */
02723   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
02724
02725   /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
02726   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
02727   {
02728     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02729   }
02730
02731   hspi->State = HAL_SPI_STATE_READY;
02732   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02733   {
02734     HAL_SPI_ErrorCallback(hspi);
02735   }
02736   else
02737   {
02738     HAL_SPI_TxCpltCallback(hspi);
02739   }
02740 }
02741
02742 /**
02743   * @}
02744   */
02745
02746 #endif /* HAL_SPI_MODULE_ENABLED */
02747 /**
02748   * @}
02749   */
02750
02751 /**
02752   * @}
02753   */
02754
02755 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_spi.h Source File

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stm32f7xx_hal_spi.h
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00001  /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SPI_H
00040 #define __STM32F7xx_HAL_SPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SPI_Exported_Types SPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  SPI Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;                /*!< Specifies the SPI operating mode.
00068                                      This parameter can be a value of @ref SPI_Mode */
00069
00070   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00071                                      This parameter can be a value of @ref SPI_Direction */
00072
00073   uint32_t DataSize;            /*!< Specifies the SPI data size.
00074                                      This parameter can be a value of @ref SPI_Data_Size */
00075
00076   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
00077                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00078
00079   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
00080                                      This parameter can be a value of @ref SPI_Clock_Phase */
00081
00082   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
00083                                      hardware (NSS pin) or by software using the SSI bit.
00084                                      This parameter can be a value of @ref SPI_Slave_Select_management */
00085
00086   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00087                                      used to configure the transmit and receive SCK clock.
00088                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00089                                      @note The communication clock is derived from the master
00090                                      clock. The slave clock does not need to be set. */
00091
00092   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00094
00095   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .
00096                                      This parameter can be a value of @ref SPI_TI_mode */
00097
00098   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
00099                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00100
00101   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
00102                                      This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
00103
00104   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
00105                                      CRC Length is only used with Data8 and Data16, not other data size
00106                                      This parameter can be a value of @ref SPI_CRC_length */
00107
00108   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
00109                                      This parameter can be a value of @ref SPI_NSSP_Mode
00110                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00111                                      it takes effect only if the SPI interface is configured as Motorola SPI
00112                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00113                                      CPOL setting is ignored).. */
00114 } SPI_InitTypeDef;
00115
00116 /**
00117   * @brief  HAL State structures definition
00118   */
00119 typedef enum
00120 {
00121   HAL_SPI_STATE_RESET      = 0x00,    /*!< Peripheral not Initialized                         */
00122   HAL_SPI_STATE_READY      = 0x01,    /*!< Peripheral Initialized and ready for use           */
00123   HAL_SPI_STATE_BUSY       = 0x02,    /*!< an internal process is ongoing                     */
00124   HAL_SPI_STATE_BUSY_TX    = 0x03,    /*!< Data Transmission process is ongoing               */
00125   HAL_SPI_STATE_BUSY_RX    = 0x04,    /*!< Data Reception process is ongoing                  */
00126   HAL_SPI_STATE_BUSY_TX_RX = 0x05,    /*!< Data Transmission and Reception process is ongoing*/
00127   HAL_SPI_STATE_ERROR      = 0x06     /*!< SPI error state                                   */
00128 }HAL_SPI_StateTypeDef;
00129
00130 /**
00131   * @brief  SPI handle Structure definition
00132   */
00133 typedef struct __SPI_HandleTypeDef
00134 {
00135   SPI_TypeDef             *Instance;      /* SPI registers base address     */
00136
00137   SPI_InitTypeDef         Init;           /* SPI communication parameters   */
00138
00139   uint8_t                 *pTxBuffPtr;    /* Pointer to SPI Tx transfer Buffer */
00140
00141   uint16_t                TxXferSize;     /* SPI Tx Transfer size */
00142
00143   uint16_t                TxXferCount;    /* SPI Tx Transfer Counter */
00144
00145   uint8_t                 *pRxBuffPtr;    /* Pointer to SPI Rx transfer Buffer */
00146
00147   uint16_t                RxXferSize;     /* SPI Rx Transfer size */
00148
00149   uint16_t                RxXferCount;    /* SPI Rx Transfer Counter */
00150
00151   uint32_t                CRCSize;        /* SPI CRC size used for the transfer */
00152
00153   void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler   */
00154
00155   void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler   */
00156
00157   DMA_HandleTypeDef       *hdmatx;        /* SPI Tx DMA Handle parameters   */
00158
00159   DMA_HandleTypeDef       *hdmarx;        /* SPI Rx DMA Handle parameters   */
00160
00161   HAL_LockTypeDef         Lock;           /* Locking object                 */
00162
00163   HAL_SPI_StateTypeDef    State;          /* SPI communication state        */
00164
00165   uint32_t                ErrorCode;      /* SPI Error code                 */
00166
00167 }SPI_HandleTypeDef;
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Exported constants --------------------------------------------------------*/
00174
00175 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup SPI_Error_Code SPI Error Code
00180   * @{
00181   */
00182 #define HAL_SPI_ERROR_NONE   (uint32_t)0x00000000  /*!< No error                          */
00183 #define HAL_SPI_ERROR_MODF   (uint32_t)0x00000001  /*!< MODF error                        */
00184 #define HAL_SPI_ERROR_CRC    (uint32_t)0x00000002  /*!< CRC error                         */
00185 #define HAL_SPI_ERROR_OVR    (uint32_t)0x00000004  /*!< OVR error                         */
00186 #define HAL_SPI_ERROR_FRE    (uint32_t)0x00000008  /*!< FRE error                         */
00187 #define HAL_SPI_ERROR_DMA    (uint32_t)0x00000010  /*!< DMA transfer error                */
00188 #define HAL_SPI_ERROR_FLAG   (uint32_t)0x00000020  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
00189 #define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040  /*!< Unknow Error error                */
00190 /**
00191   * @}
00192   */
00193
00194
00195 /** @defgroup SPI_Mode SPI Mode
00196   * @{
00197   */
00198 #define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
00199 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup SPI_Direction SPI Direction Mode
00205   * @{
00206   */
00207 #define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
00208 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00209 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup SPI_Data_Size SPI Data Size
00215   * @{
00216   */
00217 #define SPI_DATASIZE_4BIT               ((uint32_t)0x0300)
00218 #define SPI_DATASIZE_5BIT               ((uint32_t)0x0400)
00219 #define SPI_DATASIZE_6BIT               ((uint32_t)0x0500)
00220 #define SPI_DATASIZE_7BIT               ((uint32_t)0x0600)
00221 #define SPI_DATASIZE_8BIT               ((uint32_t)0x0700)
00222 #define SPI_DATASIZE_9BIT               ((uint32_t)0x0800)
00223 #define SPI_DATASIZE_10BIT              ((uint32_t)0x0900)
00224 #define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00)
00225 #define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00)
00226 #define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00)
00227 #define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00)
00228 #define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00)
00229 #define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00235   * @{
00236   */
00237 #define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
00238 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00244   * @{
00245   */
00246 #define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
00247 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
00253   * @{
00254   */
00255 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00256 #define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
00257 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00263   * @{
00264   */
00265 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
00266 #define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000)
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00272   * @{
00273   */
00274 #define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
00275 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
00276 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
00277 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
00278 #define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
00279 #define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
00280 #define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
00281 #define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
00287   * @{
00288   */
00289 #define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
00290 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SPI_TI_mode SPI TI mode
00296   * @{
00297   */
00298 #define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000)
00299 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00305   * @{
00306   */
00307 #define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
00308 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup SPI_CRC_length SPI CRC Length
00314   * @{
00315   * This parameter can be one of the following values:
00316   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
00317   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
00318   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
00319   */
00320 #define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000)
00321 #define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001)
00322 #define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002)
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
00328   * @{
00329   * This parameter can be one of the following values:
00330   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
00331   *          RXNE event is generated if the FIFO
00332   *          level is greater or equal to 1/2(16-bits).
00333   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
00334   *          level is greater or equal to 1/4(8 bits). */
00335 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
00336 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
00337 #define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000)
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
00344   * @brief SPI Interrupt definition
00345   *        Elements values convention: 0xXXXXXXXX
00346   *           - XXXXXXXX  : Interrupt control mask
00347   * @{
00348   */
00349 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00350 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00351 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00352 /**
00353   * @}
00354   */
00355
00356
00357 /** @defgroup SPI_Flag_definition SPI Flag definition
00358   * @brief Flag definition
00359   *        Elements values convention: 0xXXXXYYYY
00360   *           - XXXX  : Flag register Index
00361   *           - YYYY  : Flag mask
00362   * @{
00363   */
00364 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
00365 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
00366 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
00367 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
00368 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
00369 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
00370 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00371 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */
00372 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
00378   * @{
00379   */
00380 #define SPI_FTLVL_EMPTY           ((uint32_t)0x0000)
00381 #define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800)
00382 #define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000)
00383 #define SPI_FTLVL_FULL            ((uint32_t)0x1800)
00384
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00390   * @{
00391   */
00392 #define SPI_FRLVL_EMPTY           ((uint32_t)0x0000)
00393 #define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200)
00394 #define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400)
00395 #define SPI_FRLVL_FULL            ((uint32_t)0x0600)
00396 /**
00397   * @}
00398   */
00399
00400 /**
00401   * @}
00402   */
00403
00404 /* Exported macros ------------------------------------------------------------*/
00405 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00406   * @{
00407   */
00408
00409 /** @brief  Reset SPI handle state
00410   * @param  __HANDLE__: SPI handle.
00411   * @retval None
00412   */
00413 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00414
00415 /** @brief  Enables or disables the specified SPI interrupts.
00416   * @param  __HANDLE__ : specifies the SPI Handle.
00417   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00418   * @param  __INTERRUPT__ : specifies the interrupt source to enable or disable.
00419   *        This parameter can be one of the following values:
00420   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00421   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00422   *            @arg SPI_IT_ERR: Error interrupt enable
00423   * @retval None
00424   */
00425 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00426 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
00427
00428 /** @brief  Checks if the specified SPI interrupt source is enabled or disabled.
00429   * @param  __HANDLE__ : specifies the SPI Handle.
00430   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00431   * @param  __INTERRUPT__ : specifies the SPI interrupt source to check.
00432   *          This parameter can be one of the following values:
00433   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00434   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00435   *            @arg SPI_IT_ERR: Error interrupt enable
00436   * @retval The new state of __IT__ (TRUE or FALSE).
00437   */
00438 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00439
00440 /** @brief  Checks whether the specified SPI flag is set or not.
00441   * @param  __HANDLE__ : specifies the SPI Handle.
00442   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00443   * @param  __FLAG__ : specifies the flag to check.
00444   *        This parameter can be one of the following values:
00445   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00446   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00447   *            @arg SPI_FLAG_CRCERR: CRC error flag
00448   *            @arg SPI_FLAG_MODF: Mode fault flag
00449   *            @arg SPI_FLAG_OVR: Overrun flag
00450   *            @arg SPI_FLAG_BSY: Busy flag
00451   *            @arg SPI_FLAG_FRE: Frame format error flag
00452   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00453   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00454   * @retval The new state of __FLAG__ (TRUE or FALSE).
00455   */
00456 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00457
00458 /** @brief  Clears the SPI CRCERR pending flag.
00459   * @param  __HANDLE__ : specifies the SPI Handle.
00460   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00461   * @retval None
00462   */
00463 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00464
00465 /** @brief  Clears the SPI MODF pending flag.
00466   * @param  __HANDLE__ : specifies the SPI Handle.
00467   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00468   *
00469   * @retval None
00470   */
00471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
00472    do{                                              \
00473    __IO uint32_t tmpreg = 0x00;                          \
00474      tmpreg = (__HANDLE__)->Instance->SR;           \
00475      (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
00476      UNUSED(tmpreg);                                \
00477    } while(0)
00478
00479 /** @brief  Clears the SPI OVR pending flag.
00480   * @param  __HANDLE__ : specifies the SPI Handle.
00481   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00482   *
00483   * @retval None
00484   */
00485 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
00486    do{                                              \
00487    __IO uint32_t tmpreg = 0x00;                          \
00488      tmpreg = (__HANDLE__)->Instance->DR;           \
00489      tmpreg = (__HANDLE__)->Instance->SR;           \
00490      UNUSED(tmpreg);                                \
00491    } while(0)
00492
00493 /** @brief  Clears the SPI FRE pending flag.
00494   * @param  __HANDLE__ : specifies the SPI Handle.
00495   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00496   *
00497   * @retval None
00498   */
00499 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
00500    do{                                              \
00501    __IO uint32_t tmpreg = 0x00;                          \
00502      tmpreg = (__HANDLE__)->Instance->SR;           \
00503      UNUSED(tmpreg);                                \
00504    } while(0)
00505
00506 /** @brief  Enables the SPI.
00507   * @param  __HANDLE__ : specifies the SPI Handle.
00508   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00509   * @retval None
00510   */
00511 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
00512
00513 /** @brief  Disables the SPI.
00514   * @param  __HANDLE__ : specifies the SPI Handle.
00515   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00516   * @retval None
00517   */
00518 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
00519
00520 /**
00521   * @}
00522   */
00523
00524 /* Private macros --------------------------------------------------------*/
00525 /** @defgroup SPI_Private_Macros   SPI Private Macros
00526   * @{
00527   */
00528
00529 /** @brief  Sets the SPI transmit-only mode.
00530   * @param  __HANDLE__ : specifies the SPI Handle.
00531   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00532   * @retval None
00533   */
00534 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
00535
00536 /** @brief  Sets the SPI receive-only mode.
00537   * @param  __HANDLE__ : specifies the SPI Handle.
00538   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00539   * @retval None
00540   */
00541 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
00542
00543 /** @brief  Resets the CRC calculation of the SPI.
00544   * @param  __HANDLE__ : specifies the SPI Handle.
00545   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00546   * @retval None
00547   */
00548 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
00549                                      (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
00550
00551 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
00552                            ((MODE) == SPI_MODE_MASTER))
00553
00554 #define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \
00555                                   ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
00556                                   ((MODE) == SPI_DIRECTION_1LINE))
00557
00558 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00559
00560 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
00561                                                  ((MODE) == SPI_DIRECTION_1LINE))
00562
00563 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
00564                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
00565                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
00566                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
00567                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
00568                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
00569                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
00570                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
00571                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
00572                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
00573                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
00574                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
00575                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
00576
00577 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
00578                            ((CPOL) == SPI_POLARITY_HIGH))
00579
00580 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
00581                            ((CPHA) == SPI_PHASE_2EDGE))
00582
00583 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
00584                          ((NSS) == SPI_NSS_HARD_INPUT) || \
00585                          ((NSS) == SPI_NSS_HARD_OUTPUT))
00586
00587 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
00588                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
00589
00590 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
00591                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
00592                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
00593                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
00594                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
00595                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
00596                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00597                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00598
00599 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00600                                ((BIT) == SPI_FIRSTBIT_LSB))
00601
00602 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
00603                              ((MODE) == SPI_TIMODE_ENABLE))
00604
00605 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
00606                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
00607
00608 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
00609                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
00610                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
00611
00612 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
00613
00614
00615 /**
00616   * @}
00617   */
00618
00619 /* Exported functions --------------------------------------------------------*/
00620 /** @addtogroup SPI_Exported_Functions SPI Exported Functions
00621   * @{
00622   */
00623
00624 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00625   * @{
00626   */
00627
00628 /* Initialization and de-initialization functions  ****************************/
00629 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00630 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
00631 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00632 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00633 /**
00634   * @}
00635   */
00636
00637 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
00638   * @{
00639   */
00640
00641 /* IO operation functions *****************************************************/
00642 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00643 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00644 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00645 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00646 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00647 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00648 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00649 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00650 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00651 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00652 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00653 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00654
00655 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00656 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00657 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00658 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00659 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00660 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00661 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00662 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00663 /**
00664   * @}
00665   */
00666
00667 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
00668   * @{
00669   */
00670
00671 /* Peripheral State and Error functions ***************************************/
00672 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00673 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /**
00687   * @}
00688   */
00689
00690 #ifdef __cplusplus
00691 }
00692 #endif
00693
00694 #endif /* __STM32F7xx_HAL_SPI_H */
00695
00696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sram.c Source File

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stm32f7xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   SRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SRAM memories
00009   *          mounted as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                           ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SRAM memories. It uses the FMC layer functions to interface
00018     with SRAM devices.
00019     The following sequence should be followed to configure the FMC to interface
00020     with SRAM/PSRAM memories:
00021
00022    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00023           SRAM_HandleTypeDef  hsram; and:
00024
00025        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SRAM device
00030
00031        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00032             base register instance for NOR or SRAM extended mode
00033
00034    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00035        mode timings; for example:
00036           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00037       and fill its fields with the allowed values of the structure member.
00038
00039    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00040        performs the following sequence:
00041
00042        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00043        (##) Control register configuration using the FMC NORSRAM interface function
00044             FMC_NORSRAM_Init()
00045        (##) Timing register configuration using the FMC NORSRAM interface function
00046             FMC_NORSRAM_Timing_Init()
00047        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00048             FMC_NORSRAM_Extended_Timing_Init()
00049        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00050
00051    (#) At this stage you can perform read/write accesses from/to the memory connected
00052        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00053        following APIs:
00054        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00055        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00056
00057    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00058        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00059
00060    (#) You can continuously monitor the SRAM device HAL state by calling the function
00061        HAL_SRAM_GetState()
00062
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00068   *
00069   * Redistribution and use in source and binary forms, with or without modification,
00070   * are permitted provided that the following conditions are met:
00071   *   1. Redistributions of source code must retain the above copyright notice,
00072   *      this list of conditions and the following disclaimer.
00073   *   2. Redistributions in binary form must reproduce the above copyright notice,
00074   *      this list of conditions and the following disclaimer in the documentation
00075   *      and/or other materials provided with the distribution.
00076   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00077   *      may be used to endorse or promote products derived from this software
00078   *      without specific prior written permission.
00079   *
00080   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00081   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00082   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00083   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00084   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00085   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00086   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00087   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00088   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00089   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00090   *
00091   ******************************************************************************
00092   */
00093
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32f7xx_hal.h"
00096
00097 /** @addtogroup STM32F7xx_HAL_Driver
00098   * @{
00099   */
00100
00101 /** @defgroup SRAM SRAM
00102   * @brief SRAM driver modules
00103   * @{
00104   */
00105 #ifdef HAL_SRAM_MODULE_ENABLED
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 /* Private macro -------------------------------------------------------------*/
00109 /* Private variables ---------------------------------------------------------*/
00110 /* Private function prototypes -----------------------------------------------*/
00111 /* Exported functions --------------------------------------------------------*/
00112
00113 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00114   * @{
00115   */
00116
00117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00118   * @brief    Initialization and Configuration functions.
00119   *
00120   @verbatim
00121   ==============================================================================
00122            ##### SRAM Initialization and de_initialization functions #####
00123   ==============================================================================
00124     [..]  This section provides functions allowing to initialize/de-initialize
00125           the SRAM memory
00126
00127 @endverbatim
00128   * @{
00129   */
00130
00131 /**
00132   * @brief  Performs the SRAM device initialization sequence
00133   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00134   *                the configuration information for SRAM module.
00135   * @param  Timing: Pointer to SRAM control timing structure
00136   * @param  ExtTiming: Pointer to SRAM extended mode timing structure
00137   * @retval HAL status
00138   */
00139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00140 {
00141   /* Check the SRAM handle parameter */
00142   if(hsram == NULL)
00143   {
00144      return HAL_ERROR;
00145   }
00146
00147   if(hsram->State == HAL_SRAM_STATE_RESET)
00148   {
00149     /* Allocate lock resource and initialize it */
00150     hsram->Lock = HAL_UNLOCKED;
00151     /* Initialize the low level hardware (MSP) */
00152     HAL_SRAM_MspInit(hsram);
00153   }
00154
00155   /* Initialize SRAM control Interface */
00156   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00157
00158   /* Initialize SRAM timing Interface */
00159   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00160
00161   /* Initialize SRAM extended mode timing Interface */
00162   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00163
00164   /* Enable the NORSRAM device */
00165   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00166
00167   return HAL_OK;
00168 }
00169
00170 /**
00171   * @brief  Performs the SRAM device De-initialization sequence.
00172   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00173   *                the configuration information for SRAM module.
00174   * @retval HAL status
00175   */
00176 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00177 {
00178   /* De-Initialize the low level hardware (MSP) */
00179   HAL_SRAM_MspDeInit(hsram);
00180
00181   /* Configure the SRAM registers with their reset values */
00182   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00183
00184   hsram->State = HAL_SRAM_STATE_RESET;
00185
00186   /* Release Lock */
00187   __HAL_UNLOCK(hsram);
00188
00189   return HAL_OK;
00190 }
00191
00192 /**
00193   * @brief  SRAM MSP Init.
00194   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00195   *                the configuration information for SRAM module.
00196   * @retval None
00197   */
00198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00199 {
00200   /* Prevent unused argument(s) compilation warning */
00201   UNUSED(hsram);
00202
00203   /* NOTE : This function Should not be modified, when the callback is needed,
00204             the HAL_SRAM_MspInit could be implemented in the user file
00205    */
00206 }
00207
00208 /**
00209   * @brief  SRAM MSP DeInit.
00210   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00211   *                the configuration information for SRAM module.
00212   * @retval None
00213   */
00214 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00215 {
00216   /* Prevent unused argument(s) compilation warning */
00217   UNUSED(hsram);
00218
00219   /* NOTE : This function Should not be modified, when the callback is needed,
00220             the HAL_SRAM_MspDeInit could be implemented in the user file
00221    */
00222 }
00223
00224 /**
00225   * @brief  DMA transfer complete callback.
00226   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00227   *                the configuration information for SRAM module.
00228   * @retval None
00229   */
00230 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00231 {
00232   /* Prevent unused argument(s) compilation warning */
00233   UNUSED(hdma);
00234
00235   /* NOTE : This function Should not be modified, when the callback is needed,
00236             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00237    */
00238 }
00239
00240 /**
00241   * @brief  DMA transfer complete error callback.
00242   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00243   *                the configuration information for SRAM module.
00244   * @retval None
00245   */
00246 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00247 {
00248   /* Prevent unused argument(s) compilation warning */
00249   UNUSED(hdma);
00250
00251   /* NOTE : This function Should not be modified, when the callback is needed,
00252             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00253    */
00254 }
00255
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00261   * @brief    Input Output and memory control functions
00262   *
00263   @verbatim
00264   ==============================================================================
00265                   ##### SRAM Input and Output functions #####
00266   ==============================================================================
00267   [..]
00268     This section provides functions allowing to use and control the SRAM memory
00269
00270 @endverbatim
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  Reads 8-bit buffer from SRAM memory.
00276   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00277   *                the configuration information for SRAM module.
00278   * @param  pAddress: Pointer to read start address
00279   * @param  pDstBuffer: Pointer to destination buffer
00280   * @param  BufferSize: Size of the buffer to read from memory
00281   * @retval HAL status
00282   */
00283 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00284 {
00285   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00286
00287   /* Process Locked */
00288   __HAL_LOCK(hsram);
00289
00290   /* Update the SRAM controller state */
00291   hsram->State = HAL_SRAM_STATE_BUSY;
00292
00293   /* Read data from memory */
00294   for(; BufferSize != 0; BufferSize--)
00295   {
00296     *pDstBuffer = *(__IO uint8_t *)psramaddress;
00297     pDstBuffer++;
00298     psramaddress++;
00299   }
00300
00301   /* Update the SRAM controller state */
00302   hsram->State = HAL_SRAM_STATE_READY;
00303
00304   /* Process unlocked */
00305   __HAL_UNLOCK(hsram);
00306
00307   return HAL_OK;
00308 }
00309
00310 /**
00311   * @brief  Writes 8-bit buffer to SRAM memory.
00312   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00313   *                the configuration information for SRAM module.
00314   * @param  pAddress: Pointer to write start address
00315   * @param  pSrcBuffer: Pointer to source buffer to write
00316   * @param  BufferSize: Size of the buffer to write to memory
00317   * @retval HAL status
00318   */
00319 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00320 {
00321   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00322
00323   /* Check the SRAM controller state */
00324   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00325   {
00326     return  HAL_ERROR;
00327   }
00328
00329   /* Process Locked */
00330   __HAL_LOCK(hsram);
00331
00332   /* Update the SRAM controller state */
00333   hsram->State = HAL_SRAM_STATE_BUSY;
00334
00335   /* Write data to memory */
00336   for(; BufferSize != 0; BufferSize--)
00337   {
00338     *(__IO uint8_t *)psramaddress = *pSrcBuffer;
00339     pSrcBuffer++;
00340     psramaddress++;
00341   }
00342
00343   /* Update the SRAM controller state */
00344   hsram->State = HAL_SRAM_STATE_READY;
00345
00346   /* Process unlocked */
00347   __HAL_UNLOCK(hsram);
00348
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief  Reads 16-bit buffer from SRAM memory.
00354   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00355   *                the configuration information for SRAM module.
00356   * @param  pAddress: Pointer to read start address
00357   * @param  pDstBuffer: Pointer to destination buffer
00358   * @param  BufferSize: Size of the buffer to read from memory
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00362 {
00363   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00364
00365   /* Process Locked */
00366   __HAL_LOCK(hsram);
00367
00368   /* Update the SRAM controller state */
00369   hsram->State = HAL_SRAM_STATE_BUSY;
00370
00371   /* Read data from memory */
00372   for(; BufferSize != 0; BufferSize--)
00373   {
00374     *pDstBuffer = *(__IO uint16_t *)psramaddress;
00375     pDstBuffer++;
00376     psramaddress++;
00377   }
00378
00379   /* Update the SRAM controller state */
00380   hsram->State = HAL_SRAM_STATE_READY;
00381
00382   /* Process unlocked */
00383   __HAL_UNLOCK(hsram);
00384
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  Writes 16-bit buffer to SRAM memory.
00390   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00391   *                the configuration information for SRAM module.
00392   * @param  pAddress: Pointer to write start address
00393   * @param  pSrcBuffer: Pointer to source buffer to write
00394   * @param  BufferSize: Size of the buffer to write to memory
00395   * @retval HAL status
00396   */
00397 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00398 {
00399   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00400
00401   /* Check the SRAM controller state */
00402   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00403   {
00404     return  HAL_ERROR;
00405   }
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsram);
00409
00410   /* Update the SRAM controller state */
00411   hsram->State = HAL_SRAM_STATE_BUSY;
00412
00413   /* Write data to memory */
00414   for(; BufferSize != 0; BufferSize--)
00415   {
00416     *(__IO uint16_t *)psramaddress = *pSrcBuffer;
00417     pSrcBuffer++;
00418     psramaddress++;
00419   }
00420
00421   /* Update the SRAM controller state */
00422   hsram->State = HAL_SRAM_STATE_READY;
00423
00424   /* Process unlocked */
00425   __HAL_UNLOCK(hsram);
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  Reads 32-bit buffer from SRAM memory.
00432   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00433   *                the configuration information for SRAM module.
00434   * @param  pAddress: Pointer to read start address
00435   * @param  pDstBuffer: Pointer to destination buffer
00436   * @param  BufferSize: Size of the buffer to read from memory
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00440 {
00441   /* Process Locked */
00442   __HAL_LOCK(hsram);
00443
00444   /* Update the SRAM controller state */
00445   hsram->State = HAL_SRAM_STATE_BUSY;
00446
00447   /* Read data from memory */
00448   for(; BufferSize != 0; BufferSize--)
00449   {
00450     *pDstBuffer = *(__IO uint32_t *)pAddress;
00451     pDstBuffer++;
00452     pAddress++;
00453   }
00454
00455   /* Update the SRAM controller state */
00456   hsram->State = HAL_SRAM_STATE_READY;
00457
00458   /* Process unlocked */
00459   __HAL_UNLOCK(hsram);
00460
00461   return HAL_OK;
00462 }
00463
00464 /**
00465   * @brief  Writes 32-bit buffer to SRAM memory.
00466   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00467   *                the configuration information for SRAM module.
00468   * @param  pAddress: Pointer to write start address
00469   * @param  pSrcBuffer: Pointer to source buffer to write
00470   * @param  BufferSize: Size of the buffer to write to memory
00471   * @retval HAL status
00472   */
00473 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00474 {
00475   /* Check the SRAM controller state */
00476   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00477   {
00478     return  HAL_ERROR;
00479   }
00480
00481   /* Process Locked */
00482   __HAL_LOCK(hsram);
00483
00484   /* Update the SRAM controller state */
00485   hsram->State = HAL_SRAM_STATE_BUSY;
00486
00487   /* Write data to memory */
00488   for(; BufferSize != 0; BufferSize--)
00489   {
00490     *(__IO uint32_t *)pAddress = *pSrcBuffer;
00491     pSrcBuffer++;
00492     pAddress++;
00493   }
00494
00495   /* Update the SRAM controller state */
00496   hsram->State = HAL_SRAM_STATE_READY;
00497
00498   /* Process unlocked */
00499   __HAL_UNLOCK(hsram);
00500
00501   return HAL_OK;
00502 }
00503
00504 /**
00505   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00506   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00507   *                the configuration information for SRAM module.
00508   * @param  pAddress: Pointer to read start address
00509   * @param  pDstBuffer: Pointer to destination buffer
00510   * @param  BufferSize: Size of the buffer to read from memory
00511   * @retval HAL status
00512   */
00513 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00514 {
00515   /* Process Locked */
00516   __HAL_LOCK(hsram);
00517
00518   /* Update the SRAM controller state */
00519   hsram->State = HAL_SRAM_STATE_BUSY;
00520
00521   /* Configure DMA user callbacks */
00522   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00523   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00524
00525   /* Enable the DMA Stream */
00526   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00527
00528   /* Update the SRAM controller state */
00529   hsram->State = HAL_SRAM_STATE_READY;
00530
00531   /* Process unlocked */
00532   __HAL_UNLOCK(hsram);
00533
00534   return HAL_OK;
00535 }
00536
00537 /**
00538   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00539   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00540   *                the configuration information for SRAM module.
00541   * @param  pAddress: Pointer to write start address
00542   * @param  pSrcBuffer: Pointer to source buffer to write
00543   * @param  BufferSize: Size of the buffer to write to memory
00544   * @retval HAL status
00545   */
00546 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00547 {
00548   /* Check the SRAM controller state */
00549   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00550   {
00551     return  HAL_ERROR;
00552   }
00553
00554   /* Process Locked */
00555   __HAL_LOCK(hsram);
00556
00557   /* Update the SRAM controller state */
00558   hsram->State = HAL_SRAM_STATE_BUSY;
00559
00560   /* Configure DMA user callbacks */
00561   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00562   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00563
00564   /* Enable the DMA Stream */
00565   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00566
00567   /* Update the SRAM controller state */
00568   hsram->State = HAL_SRAM_STATE_READY;
00569
00570   /* Process unlocked */
00571   __HAL_UNLOCK(hsram);
00572
00573   return HAL_OK;
00574 }
00575
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00581  *  @brief   Control functions
00582  *
00583 @verbatim
00584   ==============================================================================
00585                         ##### SRAM Control functions #####
00586   ==============================================================================
00587   [..]
00588     This subsection provides a set of functions allowing to control dynamically
00589     the SRAM interface.
00590
00591 @endverbatim
00592   * @{
00593   */
00594
00595 /**
00596   * @brief  Enables dynamically SRAM write operation.
00597   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00598   *                the configuration information for SRAM module.
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00602 {
00603   /* Process Locked */
00604   __HAL_LOCK(hsram);
00605
00606   /* Enable write operation */
00607   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00608
00609   /* Update the SRAM controller state */
00610   hsram->State = HAL_SRAM_STATE_READY;
00611
00612   /* Process unlocked */
00613   __HAL_UNLOCK(hsram);
00614
00615   return HAL_OK;
00616 }
00617
00618 /**
00619   * @brief  Disables dynamically SRAM write operation.
00620   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00621   *                the configuration information for SRAM module.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00625 {
00626   /* Process Locked */
00627   __HAL_LOCK(hsram);
00628
00629   /* Update the SRAM controller state */
00630   hsram->State = HAL_SRAM_STATE_BUSY;
00631
00632   /* Disable write operation */
00633   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00634
00635   /* Update the SRAM controller state */
00636   hsram->State = HAL_SRAM_STATE_PROTECTED;
00637
00638   /* Process unlocked */
00639   __HAL_UNLOCK(hsram);
00640
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00649  *  @brief   Peripheral State functions
00650  *
00651 @verbatim
00652   ==============================================================================
00653                       ##### SRAM State functions #####
00654   ==============================================================================
00655   [..]
00656     This subsection permits to get in run-time the status of the SRAM controller
00657     and the data flow.
00658
00659 @endverbatim
00660   * @{
00661   */
00662
00663 /**
00664   * @brief  Returns the SRAM controller state
00665   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00666   *                the configuration information for SRAM module.
00667   * @retval HAL state
00668   */
00669 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00670 {
00671   return hsram->State;
00672 }
00673
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681 #endif /* HAL_SRAM_MODULE_ENABLED */
00682 /**
00683   * @}
00684   */
00685
00686 /**
00687   * @}
00688   */
00689
00690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_sram.h Source File

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stm32f7xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of SRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_SRAM_H
00040 #define __STM32F7xx_HAL_SRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_ll_fmc.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052 /** @addtogroup SRAM
00053   * @{
00054   */
00055
00056 /* Exported typedef ----------------------------------------------------------*/
00057
00058 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  HAL SRAM State structures definition
00063   */
00064 typedef enum
00065 {
00066   HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
00067   HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
00068   HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
00069   HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
00070   HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
00071
00072 }HAL_SRAM_StateTypeDef;
00073
00074 /**
00075   * @brief  SRAM handle Structure definition
00076   */
00077 typedef struct
00078 {
00079   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00080
00081   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00082
00083   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00084
00085   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00086
00087   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00088
00089   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
00090
00091 }SRAM_HandleTypeDef;
00092
00093 /**
00094   * @}
00095   */
00096
00097 /* Exported constants --------------------------------------------------------*/
00098 /* Exported macro ------------------------------------------------------------*/
00099
00100 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00101  * @{
00102  */
00103
00104 /** @brief Reset SRAM handle state
00105   * @param  __HANDLE__: SRAM handle
00106   * @retval None
00107   */
00108 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
00116   * @{
00117   */
00118
00119 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00120  * @{
00121  */
00122
00123 /* Initialization/de-initialization functions  ********************************/
00124 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00125 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00126 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00127 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00128
00129 /**
00130   * @}
00131   */
00132
00133 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00134  * @{
00135  */
00136
00137 /* I/O operation functions  ***************************************************/
00138 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00139 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00140 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00141 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00142 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00143 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00144 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00146
00147 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00148 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
00155  * @{
00156  */
00157
00158 /* SRAM Control functions  ****************************************************/
00159 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00160 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00161
00162 /**
00163   * @}
00164   */
00165
00166 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
00167  * @{
00168  */
00169
00170 /* SRAM  State functions ******************************************************/
00171 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 #ifdef __cplusplus
00190 }
00191 #endif
00192
00193 #endif /* __STM32F7xx_HAL_SRAM_H */
00194
00195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim.c Source File

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stm32f7xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer (TIM) peripheral:
00010   *           + Time Base Initialization
00011   *           + Time Base Start
00012   *           + Time Base Start Interruption
00013   *           + Time Base Start DMA
00014   *           + Time Output Compare/PWM Initialization
00015   *           + Time Output Compare/PWM Channel Configuration
00016   *           + Time Output Compare/PWM  Start
00017   *           + Time Output Compare/PWM  Start Interruption
00018   *           + Time Output Compare/PWM Start DMA
00019   *           + Time Input Capture Initialization
00020   *           + Time Input Capture Channel Configuration
00021   *           + Time Input Capture Start
00022   *           + Time Input Capture Start Interruption
00023   *           + Time Input Capture Start DMA
00024   *           + Time One Pulse Initialization
00025   *           + Time One Pulse Channel Configuration
00026   *           + Time One Pulse Start
00027   *           + Time Encoder Interface Initialization
00028   *           + Time Encoder Interface Start
00029   *           + Time Encoder Interface Start Interruption
00030   *           + Time Encoder Interface Start DMA
00031   *           + Commutation Event configuration with Interruption and DMA
00032   *           + Time OCRef clear configuration
00033   *           + Time External Clock configuration
00034   @verbatim
00035   ==============================================================================
00036                       ##### TIMER Generic features #####
00037   ==============================================================================
00038   [..] The Timer features include:
00039        (#) 16-bit up, down, up/down auto-reload counter.
00040        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00041            counter clock frequency either by any factor between 1 and 65536.
00042        (#) Up to 4 independent channels for:
00043            (++) Input Capture
00044            (++) Output Compare
00045            (++) PWM generation (Edge and Center-aligned Mode)
00046            (++) One-pulse mode output
00047
00048                         ##### How to use this driver #####
00049   ==============================================================================
00050     [..]
00051      (#) Initialize the TIM low level resources by implementing the following functions
00052          depending from feature used :
00053            (++) Time Base : HAL_TIM_Base_MspInit()
00054            (++) Input Capture : HAL_TIM_IC_MspInit()
00055            (++) Output Compare : HAL_TIM_OC_MspInit()
00056            (++) PWM generation : HAL_TIM_PWM_MspInit()
00057            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00058            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00059
00060      (#) Initialize the TIM low level resources :
00061         (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
00062         (##) TIM pins configuration
00063             (+++) Enable the clock for the TIM GPIOs using the following function:
00064                  __GPIOx_CLK_ENABLE();
00065             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00066
00067      (#) The external Clock can be configured, if needed (the default clock is the
00068          internal clock from the APBx), using the following function:
00069          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00070          any start function.
00071
00072      (#) Configure the TIM in the desired functioning mode using one of the
00073          initialization function of this driver:
00074          (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00075          (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00076               Output Compare signal.
00077          (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00078               PWM signal.
00079          (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00080               external signal.
00081          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00082               in One Pulse Mode.
00083          (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00084
00085      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00086            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00087            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00088            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00089            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00090            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00091            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00092
00093      (#) The DMA Burst is managed with the two following functions:
00094          HAL_TIM_DMABurst_WriteStart()
00095          HAL_TIM_DMABurst_ReadStart()
00096
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00102   *
00103   * Redistribution and use in source and binary forms, with or without modification,
00104   * are permitted provided that the following conditions are met:
00105   *   1. Redistributions of source code must retain the above copyright notice,
00106   *      this list of conditions and the following disclaimer.
00107   *   2. Redistributions in binary form must reproduce the above copyright notice,
00108   *      this list of conditions and the following disclaimer in the documentation
00109   *      and/or other materials provided with the distribution.
00110   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00111   *      may be used to endorse or promote products derived from this software
00112   *      without specific prior written permission.
00113   *
00114   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00115   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00116   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00117   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00118   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00119   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00120   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00121   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00122   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00123   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00124   *
00125   ******************************************************************************
00126   */
00127
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32f7xx_hal.h"
00130
00131 /** @addtogroup STM32F7xx_HAL_Driver
00132   * @{
00133   */
00134
00135 /** @defgroup TIM TIM
00136   * @brief TIM HAL module driver
00137   * @{
00138   */
00139
00140 #ifdef HAL_TIM_MODULE_ENABLED
00141
00142 /* Private typedef -----------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /* Private macro -------------------------------------------------------------*/
00145 /* Private variables ---------------------------------------------------------*/
00146 /** @addtogroup TIM_Private_Functions
00147   * @{
00148   */
00149 /* Private function prototypes -----------------------------------------------*/
00150 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00151 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00152                        uint32_t TIM_ICFilter);
00153 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00154 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00155                        uint32_t TIM_ICFilter);
00156 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00157                        uint32_t TIM_ICFilter);
00158
00159 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
00160 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00161 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00162 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00163                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00164 /**
00165   * @}
00166   */
00167
00168 /* Exported functions --------------------------------------------------------*/
00169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00170   * @{
00171   */
00172
00173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
00174  *  @brief    Time Base functions
00175  *
00176 @verbatim
00177   ==============================================================================
00178               ##### Time Base functions #####
00179   ==============================================================================
00180   [..]
00181     This section provides functions allowing to:
00182     (+) Initialize and configure the TIM base.
00183     (+) De-initialize the TIM base.
00184     (+) Start the Time Base.
00185     (+) Stop the Time Base.
00186     (+) Start the Time Base and enable interrupt.
00187     (+) Stop the Time Base and disable interrupt.
00188     (+) Start the Time Base and enable DMA transfer.
00189     (+) Stop the Time Base and disable DMA transfer.
00190
00191 @endverbatim
00192   * @{
00193   */
00194 /**
00195   * @brief  Initializes the TIM Time base Unit according to the specified
00196   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00197   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00198   *                the configuration information for TIM module.
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00202 {
00203   /* Check the TIM handle allocation */
00204   if(htim == NULL)
00205   {
00206     return HAL_ERROR;
00207   }
00208
00209   /* Check the parameters */
00210   assert_param(IS_TIM_INSTANCE(htim->Instance));
00211   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00212   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00213
00214   if(htim->State == HAL_TIM_STATE_RESET)
00215   {
00216     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00217     HAL_TIM_Base_MspInit(htim);
00218   }
00219
00220   /* Set the TIM state */
00221   htim->State= HAL_TIM_STATE_BUSY;
00222
00223   /* Set the Time Base configuration */
00224   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00225
00226   /* Initialize the TIM state*/
00227   htim->State= HAL_TIM_STATE_READY;
00228
00229   return HAL_OK;
00230 }
00231
00232 /**
00233   * @brief  DeInitializes the TIM Base peripheral
00234   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00235   *                the configuration information for TIM module.
00236   * @retval HAL status
00237   */
00238 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00239 {
00240   /* Check the parameters */
00241   assert_param(IS_TIM_INSTANCE(htim->Instance));
00242
00243   htim->State = HAL_TIM_STATE_BUSY;
00244
00245   /* Disable the TIM Peripheral Clock */
00246   __HAL_TIM_DISABLE(htim);
00247
00248   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00249   HAL_TIM_Base_MspDeInit(htim);
00250
00251   /* Change TIM state */
00252   htim->State = HAL_TIM_STATE_RESET;
00253
00254   /* Release Lock */
00255   __HAL_UNLOCK(htim);
00256
00257   return HAL_OK;
00258 }
00259
00260 /**
00261   * @brief  Initializes the TIM Base MSP.
00262   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00263   *                the configuration information for TIM module.
00264   * @retval None
00265   */
00266 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00267 {
00268   /* Prevent unused argument(s) compilation warning */
00269   UNUSED(htim);
00270
00271   /* NOTE : This function Should not be modified, when the callback is needed,
00272             the HAL_TIM_Base_MspInit could be implemented in the user file
00273    */
00274 }
00275
00276 /**
00277   * @brief  DeInitializes TIM Base MSP.
00278   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00279   *                the configuration information for TIM module.
00280   * @retval None
00281   */
00282 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00283 {
00284   /* Prevent unused argument(s) compilation warning */
00285   UNUSED(htim);
00286
00287   /* NOTE : This function Should not be modified, when the callback is needed,
00288             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00289    */
00290 }
00291
00292 /**
00293   * @brief  Starts the TIM Base generation.
00294   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00295   *                the configuration information for TIM module.
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00299 {
00300   /* Check the parameters */
00301   assert_param(IS_TIM_INSTANCE(htim->Instance));
00302
00303   /* Set the TIM state */
00304   htim->State= HAL_TIM_STATE_BUSY;
00305
00306   /* Enable the Peripheral */
00307   __HAL_TIM_ENABLE(htim);
00308
00309   /* Change the TIM state*/
00310   htim->State= HAL_TIM_STATE_READY;
00311
00312   /* Return function status */
00313   return HAL_OK;
00314 }
00315
00316 /**
00317   * @brief  Stops the TIM Base generation.
00318   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00319   *                the configuration information for TIM module.
00320   * @retval HAL status
00321   */
00322 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00323 {
00324   /* Check the parameters */
00325   assert_param(IS_TIM_INSTANCE(htim->Instance));
00326
00327   /* Set the TIM state */
00328   htim->State= HAL_TIM_STATE_BUSY;
00329
00330   /* Disable the Peripheral */
00331   __HAL_TIM_DISABLE(htim);
00332
00333   /* Change the TIM state*/
00334   htim->State= HAL_TIM_STATE_READY;
00335
00336   /* Return function status */
00337   return HAL_OK;
00338 }
00339
00340 /**
00341   * @brief  Starts the TIM Base generation in interrupt mode.
00342   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00343   *                the configuration information for TIM module.
00344   * @retval HAL status
00345   */
00346 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00347 {
00348   /* Check the parameters */
00349   assert_param(IS_TIM_INSTANCE(htim->Instance));
00350
00351   /* Enable the TIM Update interrupt */
00352   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00353
00354   /* Enable the Peripheral */
00355   __HAL_TIM_ENABLE(htim);
00356
00357   /* Return function status */
00358   return HAL_OK;
00359 }
00360
00361 /**
00362   * @brief  Stops the TIM Base generation in interrupt mode.
00363   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00364   *                the configuration information for TIM module.
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00368 {
00369   /* Check the parameters */
00370   assert_param(IS_TIM_INSTANCE(htim->Instance));
00371   /* Disable the TIM Update interrupt */
00372   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00373
00374   /* Disable the Peripheral */
00375   __HAL_TIM_DISABLE(htim);
00376
00377   /* Return function status */
00378   return HAL_OK;
00379 }
00380
00381 /**
00382   * @brief  Starts the TIM Base generation in DMA mode.
00383   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00384   *                the configuration information for TIM module.
00385   * @param  pData: The source Buffer address.
00386   * @param  Length: The length of data to be transferred from memory to peripheral.
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00390 {
00391   /* Check the parameters */
00392   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00393
00394   if((htim->State == HAL_TIM_STATE_BUSY))
00395   {
00396      return HAL_BUSY;
00397   }
00398   else if((htim->State == HAL_TIM_STATE_READY))
00399   {
00400     if((pData == 0 ) && (Length > 0))
00401     {
00402       return HAL_ERROR;
00403     }
00404     else
00405     {
00406       htim->State = HAL_TIM_STATE_BUSY;
00407     }
00408   }
00409   /* Set the DMA Period elapsed callback */
00410   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00411
00412   /* Set the DMA error callback */
00413   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
00414
00415   /* Enable the DMA Stream */
00416   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00417
00418   /* Enable the TIM Update DMA request */
00419   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00420
00421   /* Enable the Peripheral */
00422   __HAL_TIM_ENABLE(htim);
00423
00424   /* Return function status */
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @brief  Stops the TIM Base generation in DMA mode.
00430   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00431   *                the configuration information for TIM module.
00432   * @retval HAL status
00433   */
00434 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00435 {
00436   /* Check the parameters */
00437   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00438
00439   /* Disable the TIM Update DMA request */
00440   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00441
00442   /* Disable the Peripheral */
00443   __HAL_TIM_DISABLE(htim);
00444
00445   /* Change the htim state */
00446   htim->State = HAL_TIM_STATE_READY;
00447
00448   /* Return function status */
00449   return HAL_OK;
00450 }
00451
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
00457  *  @brief    Time Output Compare functions
00458  *
00459 @verbatim
00460   ==============================================================================
00461                   ##### Time Output Compare functions #####
00462   ==============================================================================
00463   [..]
00464     This section provides functions allowing to:
00465     (+) Initialize and configure the TIM Output Compare.
00466     (+) De-initialize the TIM Output Compare.
00467     (+) Start the Time Output Compare.
00468     (+) Stop the Time Output Compare.
00469     (+) Start the Time Output Compare and enable interrupt.
00470     (+) Stop the Time Output Compare and disable interrupt.
00471     (+) Start the Time Output Compare and enable DMA transfer.
00472     (+) Stop the Time Output Compare and disable DMA transfer.
00473
00474 @endverbatim
00475   * @{
00476   */
00477 /**
00478   * @brief  Initializes the TIM Output Compare according to the specified
00479   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00480   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00481   *                the configuration information for TIM module.
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00485 {
00486   /* Check the TIM handle allocation */
00487   if(htim == NULL)
00488   {
00489     return HAL_ERROR;
00490   }
00491
00492   /* Check the parameters */
00493   assert_param(IS_TIM_INSTANCE(htim->Instance));
00494   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00495   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00496
00497   if(htim->State == HAL_TIM_STATE_RESET)
00498   {
00499     /* Allocate lock resource and initialize it */
00500     htim->Lock = HAL_UNLOCKED;
00501     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00502     HAL_TIM_OC_MspInit(htim);
00503   }
00504
00505   /* Set the TIM state */
00506   htim->State= HAL_TIM_STATE_BUSY;
00507
00508   /* Init the base time for the Output Compare */
00509   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00510
00511   /* Initialize the TIM state*/
00512   htim->State= HAL_TIM_STATE_READY;
00513
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @brief  DeInitializes the TIM peripheral
00519   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00520   *                the configuration information for TIM module.
00521   * @retval HAL status
00522   */
00523 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00524 {
00525   /* Check the parameters */
00526   assert_param(IS_TIM_INSTANCE(htim->Instance));
00527
00528    htim->State = HAL_TIM_STATE_BUSY;
00529
00530   /* Disable the TIM Peripheral Clock */
00531   __HAL_TIM_DISABLE(htim);
00532
00533   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00534   HAL_TIM_OC_MspDeInit(htim);
00535
00536   /* Change TIM state */
00537   htim->State = HAL_TIM_STATE_RESET;
00538
00539   /* Release Lock */
00540   __HAL_UNLOCK(htim);
00541
00542   return HAL_OK;
00543 }
00544
00545 /**
00546   * @brief  Initializes the TIM Output Compare MSP.
00547   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00548   *                the configuration information for TIM module.
00549   * @retval None
00550   */
00551 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00552 {
00553   /* Prevent unused argument(s) compilation warning */
00554   UNUSED(htim);
00555
00556   /* NOTE : This function Should not be modified, when the callback is needed,
00557             the HAL_TIM_OC_MspInit could be implemented in the user file
00558    */
00559 }
00560
00561 /**
00562   * @brief  DeInitializes TIM Output Compare MSP.
00563   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00564   *                the configuration information for TIM module.
00565   * @retval None
00566   */
00567 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00568 {
00569   /* Prevent unused argument(s) compilation warning */
00570   UNUSED(htim);
00571
00572   /* NOTE : This function Should not be modified, when the callback is needed,
00573             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00574    */
00575 }
00576
00577 /**
00578   * @brief  Starts the TIM Output Compare signal generation.
00579   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00580   *                the configuration information for TIM module.
00581   * @param  Channel: TIM Channel to be enabled.
00582   *          This parameter can be one of the following values:
00583   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00584   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00585   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00586   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00587   * @retval HAL status
00588   */
00589 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00590 {
00591   /* Check the parameters */
00592   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00593
00594   /* Enable the Output compare channel */
00595   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00596
00597   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00598   {
00599     /* Enable the main output */
00600     __HAL_TIM_MOE_ENABLE(htim);
00601   }
00602
00603   /* Enable the Peripheral */
00604   __HAL_TIM_ENABLE(htim);
00605
00606   /* Return function status */
00607   return HAL_OK;
00608 }
00609
00610 /**
00611   * @brief  Stops the TIM Output Compare signal generation.
00612   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00613   *                the configuration information for TIM module.
00614   * @param  Channel: TIM Channel to be disabled.
00615   *          This parameter can be one of the following values:
00616   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00617   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00618   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00619   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00623 {
00624   /* Check the parameters */
00625   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00626
00627   /* Disable the Output compare channel */
00628   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00629
00630   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00631   {
00632     /* Disable the Main Output */
00633     __HAL_TIM_MOE_DISABLE(htim);
00634   }
00635
00636   /* Disable the Peripheral */
00637   __HAL_TIM_DISABLE(htim);
00638
00639   /* Return function status */
00640   return HAL_OK;
00641 }
00642
00643 /**
00644   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00645   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00646   *                the configuration information for TIM module.
00647   * @param  Channel: TIM Channel to be enabled.
00648   *          This parameter can be one of the following values:
00649   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00650   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00651   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00652   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00653   * @retval HAL status
00654   */
00655 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00656 {
00657   /* Check the parameters */
00658   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00659
00660   switch (Channel)
00661   {
00662     case TIM_CHANNEL_1:
00663     {
00664       /* Enable the TIM Capture/Compare 1 interrupt */
00665       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00666     }
00667     break;
00668
00669     case TIM_CHANNEL_2:
00670     {
00671       /* Enable the TIM Capture/Compare 2 interrupt */
00672       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00673     }
00674     break;
00675
00676     case TIM_CHANNEL_3:
00677     {
00678       /* Enable the TIM Capture/Compare 3 interrupt */
00679       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00680     }
00681     break;
00682
00683     case TIM_CHANNEL_4:
00684     {
00685       /* Enable the TIM Capture/Compare 4 interrupt */
00686       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00687     }
00688     break;
00689
00690     default:
00691     break;
00692   }
00693
00694   /* Enable the Output compare channel */
00695   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00696
00697   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00698   {
00699     /* Enable the main output */
00700     __HAL_TIM_MOE_ENABLE(htim);
00701   }
00702
00703   /* Enable the Peripheral */
00704   __HAL_TIM_ENABLE(htim);
00705
00706   /* Return function status */
00707   return HAL_OK;
00708 }
00709
00710 /**
00711   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00712   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00713   *                the configuration information for TIM module.
00714   * @param  Channel: TIM Channel to be disabled.
00715   *          This parameter can be one of the following values:
00716   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00717   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00718   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00719   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00720   * @retval HAL status
00721   */
00722 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00723 {
00724   /* Check the parameters */
00725   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00726
00727   switch (Channel)
00728   {
00729     case TIM_CHANNEL_1:
00730     {
00731       /* Disable the TIM Capture/Compare 1 interrupt */
00732       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00733     }
00734     break;
00735
00736     case TIM_CHANNEL_2:
00737     {
00738       /* Disable the TIM Capture/Compare 2 interrupt */
00739       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00740     }
00741     break;
00742
00743     case TIM_CHANNEL_3:
00744     {
00745       /* Disable the TIM Capture/Compare 3 interrupt */
00746       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00747     }
00748     break;
00749
00750     case TIM_CHANNEL_4:
00751     {
00752       /* Disable the TIM Capture/Compare 4 interrupt */
00753       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00754     }
00755     break;
00756
00757     default:
00758     break;
00759   }
00760
00761   /* Disable the Output compare channel */
00762   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00763
00764   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00765   {
00766     /* Disable the Main Output */
00767     __HAL_TIM_MOE_DISABLE(htim);
00768   }
00769
00770   /* Disable the Peripheral */
00771   __HAL_TIM_DISABLE(htim);
00772
00773   /* Return function status */
00774   return HAL_OK;
00775 }
00776
00777 /**
00778   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00779   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00780   *                the configuration information for TIM module.
00781   * @param  Channel: TIM Channel to be enabled.
00782   *          This parameter can be one of the following values:
00783   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00784   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00785   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00786   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00787   * @param  pData: The source Buffer address.
00788   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00789   * @retval HAL status
00790   */
00791 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00792 {
00793   /* Check the parameters */
00794   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00795
00796   if((htim->State == HAL_TIM_STATE_BUSY))
00797   {
00798      return HAL_BUSY;
00799   }
00800   else if((htim->State == HAL_TIM_STATE_READY))
00801   {
00802     if(((uint32_t)pData == 0 ) && (Length > 0))
00803     {
00804       return HAL_ERROR;
00805     }
00806     else
00807     {
00808       htim->State = HAL_TIM_STATE_BUSY;
00809     }
00810   }
00811   switch (Channel)
00812   {
00813     case TIM_CHANNEL_1:
00814     {
00815       /* Set the DMA Period elapsed callback */
00816       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00817
00818       /* Set the DMA error callback */
00819       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
00820
00821       /* Enable the DMA Stream */
00822       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00823
00824       /* Enable the TIM Capture/Compare 1 DMA request */
00825       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00826     }
00827     break;
00828
00829     case TIM_CHANNEL_2:
00830     {
00831       /* Set the DMA Period elapsed callback */
00832       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00833
00834       /* Set the DMA error callback */
00835       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
00836
00837       /* Enable the DMA Stream */
00838       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00839
00840       /* Enable the TIM Capture/Compare 2 DMA request */
00841       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00842     }
00843     break;
00844
00845     case TIM_CHANNEL_3:
00846     {
00847       /* Set the DMA Period elapsed callback */
00848       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00849
00850       /* Set the DMA error callback */
00851       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
00852
00853       /* Enable the DMA Stream */
00854       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00855
00856       /* Enable the TIM Capture/Compare 3 DMA request */
00857       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00858     }
00859     break;
00860
00861     case TIM_CHANNEL_4:
00862     {
00863      /* Set the DMA Period elapsed callback */
00864       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00865
00866       /* Set the DMA error callback */
00867       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
00868
00869       /* Enable the DMA Stream */
00870       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00871
00872       /* Enable the TIM Capture/Compare 4 DMA request */
00873       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00874     }
00875     break;
00876
00877     default:
00878     break;
00879   }
00880
00881   /* Enable the Output compare channel */
00882   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00883
00884   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00885   {
00886     /* Enable the main output */
00887     __HAL_TIM_MOE_ENABLE(htim);
00888   }
00889
00890   /* Enable the Peripheral */
00891   __HAL_TIM_ENABLE(htim);
00892
00893   /* Return function status */
00894   return HAL_OK;
00895 }
00896
00897 /**
00898   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00899   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00900   *                the configuration information for TIM module.
00901   * @param  Channel: TIM Channel to be disabled.
00902   *          This parameter can be one of the following values:
00903   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00904   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00905   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00906   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00907   * @retval HAL status
00908   */
00909 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00910 {
00911   /* Check the parameters */
00912   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00913
00914   switch (Channel)
00915   {
00916     case TIM_CHANNEL_1:
00917     {
00918       /* Disable the TIM Capture/Compare 1 DMA request */
00919       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00920     }
00921     break;
00922
00923     case TIM_CHANNEL_2:
00924     {
00925       /* Disable the TIM Capture/Compare 2 DMA request */
00926       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00927     }
00928     break;
00929
00930     case TIM_CHANNEL_3:
00931     {
00932       /* Disable the TIM Capture/Compare 3 DMA request */
00933       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00934     }
00935     break;
00936
00937     case TIM_CHANNEL_4:
00938     {
00939       /* Disable the TIM Capture/Compare 4 interrupt */
00940       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00941     }
00942     break;
00943
00944     default:
00945     break;
00946   }
00947
00948   /* Disable the Output compare channel */
00949   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00950
00951   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00952   {
00953     /* Disable the Main Output */
00954     __HAL_TIM_MOE_DISABLE(htim);
00955   }
00956
00957   /* Disable the Peripheral */
00958   __HAL_TIM_DISABLE(htim);
00959
00960   /* Change the htim state */
00961   htim->State = HAL_TIM_STATE_READY;
00962
00963   /* Return function status */
00964   return HAL_OK;
00965 }
00966
00967 /**
00968   * @}
00969   */
00970
00971 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
00972  *  @brief    Time PWM functions
00973  *
00974 @verbatim
00975   ==============================================================================
00976                           ##### Time PWM functions #####
00977   ==============================================================================
00978   [..]
00979     This section provides functions allowing to:
00980     (+) Initialize and configure the TIM OPWM.
00981     (+) De-initialize the TIM PWM.
00982     (+) Start the Time PWM.
00983     (+) Stop the Time PWM.
00984     (+) Start the Time PWM and enable interrupt.
00985     (+) Stop the Time PWM and disable interrupt.
00986     (+) Start the Time PWM and enable DMA transfer.
00987     (+) Stop the Time PWM and disable DMA transfer.
00988
00989 @endverbatim
00990   * @{
00991   */
00992 /**
00993   * @brief  Initializes the TIM PWM Time Base according to the specified
00994   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00995   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00996   *                the configuration information for TIM module.
00997   * @retval HAL status
00998   */
00999 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
01000 {
01001   /* Check the TIM handle allocation */
01002   if(htim == NULL)
01003   {
01004     return HAL_ERROR;
01005   }
01006
01007   /* Check the parameters */
01008   assert_param(IS_TIM_INSTANCE(htim->Instance));
01009   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01010   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01011
01012   if(htim->State == HAL_TIM_STATE_RESET)
01013   {
01014     /* Allocate lock resource and initialize it */
01015     htim->Lock = HAL_UNLOCKED;
01016     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01017     HAL_TIM_PWM_MspInit(htim);
01018   }
01019
01020   /* Set the TIM state */
01021   htim->State= HAL_TIM_STATE_BUSY;
01022
01023   /* Init the base time for the PWM */
01024   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01025
01026   /* Initialize the TIM state*/
01027   htim->State= HAL_TIM_STATE_READY;
01028
01029   return HAL_OK;
01030 }
01031
01032 /**
01033   * @brief  DeInitializes the TIM peripheral
01034   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01035   *                the configuration information for TIM module.
01036   * @retval HAL status
01037   */
01038 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01039 {
01040   /* Check the parameters */
01041   assert_param(IS_TIM_INSTANCE(htim->Instance));
01042
01043   htim->State = HAL_TIM_STATE_BUSY;
01044
01045   /* Disable the TIM Peripheral Clock */
01046   __HAL_TIM_DISABLE(htim);
01047
01048   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01049   HAL_TIM_PWM_MspDeInit(htim);
01050
01051   /* Change TIM state */
01052   htim->State = HAL_TIM_STATE_RESET;
01053
01054   /* Release Lock */
01055   __HAL_UNLOCK(htim);
01056
01057   return HAL_OK;
01058 }
01059
01060 /**
01061   * @brief  Initializes the TIM PWM MSP.
01062   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01063   *                the configuration information for TIM module.
01064   * @retval None
01065   */
01066 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01067 {
01068   /* Prevent unused argument(s) compilation warning */
01069   UNUSED(htim);
01070
01071   /* NOTE : This function Should not be modified, when the callback is needed,
01072             the HAL_TIM_PWM_MspInit could be implemented in the user file
01073    */
01074 }
01075
01076 /**
01077   * @brief  DeInitializes TIM PWM MSP.
01078   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01079   *                the configuration information for TIM module.
01080   * @retval None
01081   */
01082 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01083 {
01084   /* Prevent unused argument(s) compilation warning */
01085   UNUSED(htim);
01086
01087   /* NOTE : This function Should not be modified, when the callback is needed,
01088             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01089    */
01090 }
01091
01092 /**
01093   * @brief  Starts the PWM signal generation.
01094   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01095   *                the configuration information for TIM module.
01096   * @param  Channel: TIM Channels to be enabled.
01097   *          This parameter can be one of the following values:
01098   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01099   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01100   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01101   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01102   * @retval HAL status
01103   */
01104 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01105 {
01106   /* Check the parameters */
01107   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01108
01109   /* Enable the Capture compare channel */
01110   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01111
01112   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01113   {
01114     /* Enable the main output */
01115     __HAL_TIM_MOE_ENABLE(htim);
01116   }
01117
01118   /* Enable the Peripheral */
01119   __HAL_TIM_ENABLE(htim);
01120
01121   /* Return function status */
01122   return HAL_OK;
01123 }
01124
01125 /**
01126   * @brief  Stops the PWM signal generation.
01127   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01128   *                the configuration information for TIM module.
01129   * @param  Channel: TIM Channels to be disabled.
01130   *          This parameter can be one of the following values:
01131   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01132   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01133   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01134   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01135   * @retval HAL status
01136   */
01137 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01138 {
01139   /* Check the parameters */
01140   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01141
01142   /* Disable the Capture compare channel */
01143   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01144
01145   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01146   {
01147     /* Disable the Main Output */
01148     __HAL_TIM_MOE_DISABLE(htim);
01149   }
01150
01151   /* Disable the Peripheral */
01152   __HAL_TIM_DISABLE(htim);
01153
01154   /* Change the htim state */
01155   htim->State = HAL_TIM_STATE_READY;
01156
01157   /* Return function status */
01158   return HAL_OK;
01159 }
01160
01161 /**
01162   * @brief  Starts the PWM signal generation in interrupt mode.
01163   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01164   *                the configuration information for TIM module.
01165   * @param  Channel: TIM Channel to be disabled.
01166   *          This parameter can be one of the following values:
01167   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01168   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01169   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01170   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01171   * @retval HAL status
01172   */
01173 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01174 {
01175   /* Check the parameters */
01176   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01177
01178   switch (Channel)
01179   {
01180     case TIM_CHANNEL_1:
01181     {
01182       /* Enable the TIM Capture/Compare 1 interrupt */
01183       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01184     }
01185     break;
01186
01187     case TIM_CHANNEL_2:
01188     {
01189       /* Enable the TIM Capture/Compare 2 interrupt */
01190       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01191     }
01192     break;
01193
01194     case TIM_CHANNEL_3:
01195     {
01196       /* Enable the TIM Capture/Compare 3 interrupt */
01197       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01198     }
01199     break;
01200
01201     case TIM_CHANNEL_4:
01202     {
01203       /* Enable the TIM Capture/Compare 4 interrupt */
01204       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01205     }
01206     break;
01207
01208     default:
01209     break;
01210   }
01211
01212   /* Enable the Capture compare channel */
01213   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01214
01215   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01216   {
01217     /* Enable the main output */
01218     __HAL_TIM_MOE_ENABLE(htim);
01219   }
01220
01221   /* Enable the Peripheral */
01222   __HAL_TIM_ENABLE(htim);
01223
01224   /* Return function status */
01225   return HAL_OK;
01226 }
01227
01228 /**
01229   * @brief  Stops the PWM signal generation in interrupt mode.
01230   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01231   *                the configuration information for TIM module.
01232   * @param  Channel: TIM Channels to be disabled.
01233   *          This parameter can be one of the following values:
01234   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01235   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01236   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01237   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01238   * @retval HAL status
01239   */
01240 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01241 {
01242   /* Check the parameters */
01243   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01244
01245   switch (Channel)
01246   {
01247     case TIM_CHANNEL_1:
01248     {
01249       /* Disable the TIM Capture/Compare 1 interrupt */
01250       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01251     }
01252     break;
01253
01254     case TIM_CHANNEL_2:
01255     {
01256       /* Disable the TIM Capture/Compare 2 interrupt */
01257       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01258     }
01259     break;
01260
01261     case TIM_CHANNEL_3:
01262     {
01263       /* Disable the TIM Capture/Compare 3 interrupt */
01264       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01265     }
01266     break;
01267
01268     case TIM_CHANNEL_4:
01269     {
01270       /* Disable the TIM Capture/Compare 4 interrupt */
01271       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01272     }
01273     break;
01274
01275     default:
01276     break;
01277   }
01278
01279   /* Disable the Capture compare channel */
01280   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01281
01282   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01283   {
01284     /* Disable the Main Output */
01285     __HAL_TIM_MOE_DISABLE(htim);
01286   }
01287
01288   /* Disable the Peripheral */
01289   __HAL_TIM_DISABLE(htim);
01290
01291   /* Return function status */
01292   return HAL_OK;
01293 }
01294
01295 /**
01296   * @brief  Starts the TIM PWM signal generation in DMA mode.
01297   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01298   *                the configuration information for TIM module.
01299   * @param  Channel: TIM Channels to be enabled.
01300   *          This parameter can be one of the following values:
01301   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01302   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01303   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01304   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01305   * @param  pData: The source Buffer address.
01306   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01307   * @retval HAL status
01308   */
01309 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01310 {
01311   /* Check the parameters */
01312   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01313
01314   if((htim->State == HAL_TIM_STATE_BUSY))
01315   {
01316      return HAL_BUSY;
01317   }
01318   else if((htim->State == HAL_TIM_STATE_READY))
01319   {
01320     if(((uint32_t)pData == 0 ) && (Length > 0))
01321     {
01322       return HAL_ERROR;
01323     }
01324     else
01325     {
01326       htim->State = HAL_TIM_STATE_BUSY;
01327     }
01328   }
01329   switch (Channel)
01330   {
01331     case TIM_CHANNEL_1:
01332     {
01333       /* Set the DMA Period elapsed callback */
01334       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01335
01336       /* Set the DMA error callback */
01337       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
01338
01339       /* Enable the DMA Stream */
01340       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01341
01342       /* Enable the TIM Capture/Compare 1 DMA request */
01343       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01344     }
01345     break;
01346
01347     case TIM_CHANNEL_2:
01348     {
01349       /* Set the DMA Period elapsed callback */
01350       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01351
01352       /* Set the DMA error callback */
01353       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
01354
01355       /* Enable the DMA Stream */
01356       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01357
01358       /* Enable the TIM Capture/Compare 2 DMA request */
01359       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01360     }
01361     break;
01362
01363     case TIM_CHANNEL_3:
01364     {
01365       /* Set the DMA Period elapsed callback */
01366       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01367
01368       /* Set the DMA error callback */
01369       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
01370
01371       /* Enable the DMA Stream */
01372       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01373
01374       /* Enable the TIM Output Capture/Compare 3 request */
01375       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01376     }
01377     break;
01378
01379     case TIM_CHANNEL_4:
01380     {
01381      /* Set the DMA Period elapsed callback */
01382       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01383
01384       /* Set the DMA error callback */
01385       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
01386
01387       /* Enable the DMA Stream */
01388       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01389
01390       /* Enable the TIM Capture/Compare 4 DMA request */
01391       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01392     }
01393     break;
01394
01395     default:
01396     break;
01397   }
01398
01399   /* Enable the Capture compare channel */
01400   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01401
01402   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01403   {
01404     /* Enable the main output */
01405     __HAL_TIM_MOE_ENABLE(htim);
01406   }
01407
01408   /* Enable the Peripheral */
01409   __HAL_TIM_ENABLE(htim);
01410
01411   /* Return function status */
01412   return HAL_OK;
01413 }
01414
01415 /**
01416   * @brief  Stops the TIM PWM signal generation in DMA mode.
01417   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01418   *                the configuration information for TIM module.
01419   * @param  Channel: TIM Channels to be disabled.
01420   *          This parameter can be one of the following values:
01421   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01422   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01423   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01424   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01425   * @retval HAL status
01426   */
01427 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01428 {
01429   /* Check the parameters */
01430   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01431
01432   switch (Channel)
01433   {
01434     case TIM_CHANNEL_1:
01435     {
01436       /* Disable the TIM Capture/Compare 1 DMA request */
01437       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01438     }
01439     break;
01440
01441     case TIM_CHANNEL_2:
01442     {
01443       /* Disable the TIM Capture/Compare 2 DMA request */
01444       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01445     }
01446     break;
01447
01448     case TIM_CHANNEL_3:
01449     {
01450       /* Disable the TIM Capture/Compare 3 DMA request */
01451       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01452     }
01453     break;
01454
01455     case TIM_CHANNEL_4:
01456     {
01457       /* Disable the TIM Capture/Compare 4 interrupt */
01458       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01459     }
01460     break;
01461
01462     default:
01463     break;
01464   }
01465
01466   /* Disable the Capture compare channel */
01467   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01468
01469   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01470   {
01471     /* Disable the Main Output */
01472     __HAL_TIM_MOE_DISABLE(htim);
01473   }
01474
01475   /* Disable the Peripheral */
01476   __HAL_TIM_DISABLE(htim);
01477
01478   /* Change the htim state */
01479   htim->State = HAL_TIM_STATE_READY;
01480
01481   /* Return function status */
01482   return HAL_OK;
01483 }
01484
01485 /**
01486   * @}
01487   */
01488
01489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
01490  *  @brief    Time Input Capture functions
01491  *
01492 @verbatim
01493   ==============================================================================
01494               ##### Time Input Capture functions #####
01495   ==============================================================================
01496  [..]
01497    This section provides functions allowing to:
01498    (+) Initialize and configure the TIM Input Capture.
01499    (+) De-initialize the TIM Input Capture.
01500    (+) Start the Time Input Capture.
01501    (+) Stop the Time Input Capture.
01502    (+) Start the Time Input Capture and enable interrupt.
01503    (+) Stop the Time Input Capture and disable interrupt.
01504    (+) Start the Time Input Capture and enable DMA transfer.
01505    (+) Stop the Time Input Capture and disable DMA transfer.
01506
01507 @endverbatim
01508   * @{
01509   */
01510 /**
01511   * @brief  Initializes the TIM Input Capture Time base according to the specified
01512   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01513   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01514   *                the configuration information for TIM module.
01515   * @retval HAL status
01516   */
01517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01518 {
01519   /* Check the TIM handle allocation */
01520   if(htim == NULL)
01521   {
01522     return HAL_ERROR;
01523   }
01524
01525   /* Check the parameters */
01526   assert_param(IS_TIM_INSTANCE(htim->Instance));
01527   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01528   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01529
01530   if(htim->State == HAL_TIM_STATE_RESET)
01531   {
01532     /* Allocate lock resource and initialize it */
01533     htim->Lock = HAL_UNLOCKED;
01534     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01535     HAL_TIM_IC_MspInit(htim);
01536   }
01537
01538   /* Set the TIM state */
01539   htim->State= HAL_TIM_STATE_BUSY;
01540
01541   /* Init the base time for the input capture */
01542   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01543
01544   /* Initialize the TIM state*/
01545   htim->State= HAL_TIM_STATE_READY;
01546
01547   return HAL_OK;
01548 }
01549
01550 /**
01551   * @brief  DeInitializes the TIM peripheral
01552   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01553   *                the configuration information for TIM module.
01554   * @retval HAL status
01555   */
01556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01557 {
01558   /* Check the parameters */
01559   assert_param(IS_TIM_INSTANCE(htim->Instance));
01560
01561   htim->State = HAL_TIM_STATE_BUSY;
01562
01563   /* Disable the TIM Peripheral Clock */
01564   __HAL_TIM_DISABLE(htim);
01565
01566   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01567   HAL_TIM_IC_MspDeInit(htim);
01568
01569   /* Change TIM state */
01570   htim->State = HAL_TIM_STATE_RESET;
01571
01572   /* Release Lock */
01573   __HAL_UNLOCK(htim);
01574
01575   return HAL_OK;
01576 }
01577
01578 /**
01579   * @brief  Initializes the TIM INput Capture MSP.
01580   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01581   *                the configuration information for TIM module.
01582   * @retval None
01583   */
01584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01585 {
01586   /* Prevent unused argument(s) compilation warning */
01587   UNUSED(htim);
01588
01589   /* NOTE : This function Should not be modified, when the callback is needed,
01590             the HAL_TIM_IC_MspInit could be implemented in the user file
01591    */
01592 }
01593
01594 /**
01595   * @brief  DeInitializes TIM Input Capture MSP.
01596   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01597   *                the configuration information for TIM module.
01598   * @retval None
01599   */
01600 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01601 {
01602   /* Prevent unused argument(s) compilation warning */
01603   UNUSED(htim);
01604
01605   /* NOTE : This function Should not be modified, when the callback is needed,
01606             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01607    */
01608 }
01609
01610 /**
01611   * @brief  Starts the TIM Input Capture measurement.
01612   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01613   *                the configuration information for TIM module.
01614   * @param  Channel: TIM Channels to be enabled.
01615   *          This parameter can be one of the following values:
01616   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01617   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01618   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01619   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01620   * @retval HAL status
01621   */
01622 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01623 {
01624   /* Check the parameters */
01625   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01626
01627   /* Enable the Input Capture channel */
01628   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01629
01630   /* Enable the Peripheral */
01631   __HAL_TIM_ENABLE(htim);
01632
01633   /* Return function status */
01634   return HAL_OK;
01635 }
01636
01637 /**
01638   * @brief  Stops the TIM Input Capture measurement.
01639   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01640   *                the configuration information for TIM module.
01641   * @param  Channel: TIM Channels to be disabled.
01642   *          This parameter can be one of the following values:
01643   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01644   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01645   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01646   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01647   * @retval HAL status
01648   */
01649 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01650 {
01651   /* Check the parameters */
01652   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01653
01654   /* Disable the Input Capture channel */
01655   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01656
01657   /* Disable the Peripheral */
01658   __HAL_TIM_DISABLE(htim);
01659
01660   /* Return function status */
01661   return HAL_OK;
01662 }
01663
01664 /**
01665   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01666   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01667   *                the configuration information for TIM module.
01668   * @param  Channel: TIM Channels to be enabled.
01669   *          This parameter can be one of the following values:
01670   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01671   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01672   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01673   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01674   * @retval HAL status
01675   */
01676 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01677 {
01678   /* Check the parameters */
01679   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01680
01681   switch (Channel)
01682   {
01683     case TIM_CHANNEL_1:
01684     {
01685       /* Enable the TIM Capture/Compare 1 interrupt */
01686       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01687     }
01688     break;
01689
01690     case TIM_CHANNEL_2:
01691     {
01692       /* Enable the TIM Capture/Compare 2 interrupt */
01693       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01694     }
01695     break;
01696
01697     case TIM_CHANNEL_3:
01698     {
01699       /* Enable the TIM Capture/Compare 3 interrupt */
01700       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01701     }
01702     break;
01703
01704     case TIM_CHANNEL_4:
01705     {
01706       /* Enable the TIM Capture/Compare 4 interrupt */
01707       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01708     }
01709     break;
01710
01711     default:
01712     break;
01713   }
01714   /* Enable the Input Capture channel */
01715   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01716
01717   /* Enable the Peripheral */
01718   __HAL_TIM_ENABLE(htim);
01719
01720   /* Return function status */
01721   return HAL_OK;
01722 }
01723
01724 /**
01725   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01726   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01727   *                the configuration information for TIM module.
01728   * @param  Channel: TIM Channels to be disabled.
01729   *          This parameter can be one of the following values:
01730   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01731   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01732   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01733   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01734   * @retval HAL status
01735   */
01736 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01737 {
01738   /* Check the parameters */
01739   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01740
01741   switch (Channel)
01742   {
01743     case TIM_CHANNEL_1:
01744     {
01745       /* Disable the TIM Capture/Compare 1 interrupt */
01746       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01747     }
01748     break;
01749
01750     case TIM_CHANNEL_2:
01751     {
01752       /* Disable the TIM Capture/Compare 2 interrupt */
01753       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01754     }
01755     break;
01756
01757     case TIM_CHANNEL_3:
01758     {
01759       /* Disable the TIM Capture/Compare 3 interrupt */
01760       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01761     }
01762     break;
01763
01764     case TIM_CHANNEL_4:
01765     {
01766       /* Disable the TIM Capture/Compare 4 interrupt */
01767       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01768     }
01769     break;
01770
01771     default:
01772     break;
01773   }
01774
01775   /* Disable the Input Capture channel */
01776   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01777
01778   /* Disable the Peripheral */
01779   __HAL_TIM_DISABLE(htim);
01780
01781   /* Return function status */
01782   return HAL_OK;
01783 }
01784
01785 /**
01786   * @brief  Starts the TIM Input Capture measurement on in DMA mode.
01787   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01788   *                the configuration information for TIM module.
01789   * @param  Channel: TIM Channels to be enabled.
01790   *          This parameter can be one of the following values:
01791   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01792   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01793   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01794   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01795   * @param  pData: The destination Buffer address.
01796   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
01797   * @retval HAL status
01798   */
01799 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01800 {
01801   /* Check the parameters */
01802   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01803   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01804
01805   if((htim->State == HAL_TIM_STATE_BUSY))
01806   {
01807      return HAL_BUSY;
01808   }
01809   else if((htim->State == HAL_TIM_STATE_READY))
01810   {
01811     if((pData == 0 ) && (Length > 0))
01812     {
01813       return HAL_ERROR;
01814     }
01815     else
01816     {
01817       htim->State = HAL_TIM_STATE_BUSY;
01818     }
01819   }
01820
01821   switch (Channel)
01822   {
01823     case TIM_CHANNEL_1:
01824     {
01825       /* Set the DMA Period elapsed callback */
01826       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01827
01828       /* Set the DMA error callback */
01829       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
01830
01831       /* Enable the DMA Stream */
01832       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01833
01834       /* Enable the TIM Capture/Compare 1 DMA request */
01835       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01836     }
01837     break;
01838
01839     case TIM_CHANNEL_2:
01840     {
01841       /* Set the DMA Period elapsed callback */
01842       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01843
01844       /* Set the DMA error callback */
01845       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
01846
01847       /* Enable the DMA Stream */
01848       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01849
01850       /* Enable the TIM Capture/Compare 2  DMA request */
01851       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01852     }
01853     break;
01854
01855     case TIM_CHANNEL_3:
01856     {
01857       /* Set the DMA Period elapsed callback */
01858       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01859
01860       /* Set the DMA error callback */
01861       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
01862
01863       /* Enable the DMA Stream */
01864       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01865
01866       /* Enable the TIM Capture/Compare 3  DMA request */
01867       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01868     }
01869     break;
01870
01871     case TIM_CHANNEL_4:
01872     {
01873       /* Set the DMA Period elapsed callback */
01874       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
01875
01876       /* Set the DMA error callback */
01877       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
01878
01879       /* Enable the DMA Stream */
01880       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01881
01882       /* Enable the TIM Capture/Compare 4  DMA request */
01883       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01884     }
01885     break;
01886
01887     default:
01888     break;
01889   }
01890
01891   /* Enable the Input Capture channel */
01892   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01893
01894   /* Enable the Peripheral */
01895   __HAL_TIM_ENABLE(htim);
01896
01897   /* Return function status */
01898   return HAL_OK;
01899 }
01900
01901 /**
01902   * @brief  Stops the TIM Input Capture measurement on in DMA mode.
01903   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01904   *                the configuration information for TIM module.
01905   * @param  Channel: TIM Channels to be disabled.
01906   *          This parameter can be one of the following values:
01907   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01908   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01909   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01910   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01911   * @retval HAL status
01912   */
01913 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01914 {
01915   /* Check the parameters */
01916   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01917   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01918
01919   switch (Channel)
01920   {
01921     case TIM_CHANNEL_1:
01922     {
01923       /* Disable the TIM Capture/Compare 1 DMA request */
01924       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01925     }
01926     break;
01927
01928     case TIM_CHANNEL_2:
01929     {
01930       /* Disable the TIM Capture/Compare 2 DMA request */
01931       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01932     }
01933     break;
01934
01935     case TIM_CHANNEL_3:
01936     {
01937       /* Disable the TIM Capture/Compare 3  DMA request */
01938       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01939     }
01940     break;
01941
01942     case TIM_CHANNEL_4:
01943     {
01944       /* Disable the TIM Capture/Compare 4  DMA request */
01945       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01946     }
01947     break;
01948
01949     default:
01950     break;
01951   }
01952
01953   /* Disable the Input Capture channel */
01954   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01955
01956   /* Disable the Peripheral */
01957   __HAL_TIM_DISABLE(htim);
01958
01959   /* Change the htim state */
01960   htim->State = HAL_TIM_STATE_READY;
01961
01962   /* Return function status */
01963   return HAL_OK;
01964 }
01965 /**
01966   * @}
01967   */
01968
01969 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
01970  *  @brief    Time One Pulse functions
01971  *
01972 @verbatim
01973   ==============================================================================
01974                         ##### Time One Pulse functions #####
01975   ==============================================================================
01976   [..]
01977     This section provides functions allowing to:
01978     (+) Initialize and configure the TIM One Pulse.
01979     (+) De-initialize the TIM One Pulse.
01980     (+) Start the Time One Pulse.
01981     (+) Stop the Time One Pulse.
01982     (+) Start the Time One Pulse and enable interrupt.
01983     (+) Stop the Time One Pulse and disable interrupt.
01984     (+) Start the Time One Pulse and enable DMA transfer.
01985     (+) Stop the Time One Pulse and disable DMA transfer.
01986
01987 @endverbatim
01988   * @{
01989   */
01990 /**
01991   * @brief  Initializes the TIM One Pulse Time Base according to the specified
01992   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01993   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01994   *                the configuration information for TIM module.
01995   * @param  OnePulseMode: Select the One pulse mode.
01996   *         This parameter can be one of the following values:
01997   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01998   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
01999   * @retval HAL status
02000   */
02001 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
02002 {
02003   /* Check the TIM handle allocation */
02004   if(htim == NULL)
02005   {
02006     return HAL_ERROR;
02007   }
02008
02009   /* Check the parameters */
02010   assert_param(IS_TIM_INSTANCE(htim->Instance));
02011   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02012   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02013   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02014
02015   if(htim->State == HAL_TIM_STATE_RESET)
02016   {
02017     /* Allocate lock resource and initialize it */
02018     htim->Lock = HAL_UNLOCKED;
02019     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02020     HAL_TIM_OnePulse_MspInit(htim);
02021   }
02022
02023   /* Set the TIM state */
02024   htim->State= HAL_TIM_STATE_BUSY;
02025
02026   /* Configure the Time base in the One Pulse Mode */
02027   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02028
02029   /* Reset the OPM Bit */
02030   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02031
02032   /* Configure the OPM Mode */
02033   htim->Instance->CR1 |= OnePulseMode;
02034
02035   /* Initialize the TIM state*/
02036   htim->State= HAL_TIM_STATE_READY;
02037
02038   return HAL_OK;
02039 }
02040
02041 /**
02042   * @brief  DeInitializes the TIM One Pulse
02043   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02044   *                the configuration information for TIM module.
02045   * @retval HAL status
02046   */
02047 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02048 {
02049   /* Check the parameters */
02050   assert_param(IS_TIM_INSTANCE(htim->Instance));
02051
02052   htim->State = HAL_TIM_STATE_BUSY;
02053
02054   /* Disable the TIM Peripheral Clock */
02055   __HAL_TIM_DISABLE(htim);
02056
02057   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02058   HAL_TIM_OnePulse_MspDeInit(htim);
02059
02060   /* Change TIM state */
02061   htim->State = HAL_TIM_STATE_RESET;
02062
02063   /* Release Lock */
02064   __HAL_UNLOCK(htim);
02065
02066   return HAL_OK;
02067 }
02068
02069 /**
02070   * @brief  Initializes the TIM One Pulse MSP.
02071   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02072   *                the configuration information for TIM module.
02073   * @retval None
02074   */
02075 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02076 {
02077   /* Prevent unused argument(s) compilation warning */
02078   UNUSED(htim);
02079
02080   /* NOTE : This function Should not be modified, when the callback is needed,
02081             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02082    */
02083 }
02084
02085 /**
02086   * @brief  DeInitializes TIM One Pulse MSP.
02087   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02088   *                the configuration information for TIM module.
02089   * @retval None
02090   */
02091 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02092 {
02093   /* Prevent unused argument(s) compilation warning */
02094   UNUSED(htim);
02095
02096   /* NOTE : This function Should not be modified, when the callback is needed,
02097             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02098    */
02099 }
02100
02101 /**
02102   * @brief  Starts the TIM One Pulse signal generation.
02103   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02104   *                the configuration information for TIM module.
02105   * @param  OutputChannel : TIM Channels to be enabled.
02106   *          This parameter can be one of the following values:
02107   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02108   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02109   * @retval HAL status
02110   */
02111 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02112 {
02113   /* Enable the Capture compare and the Input Capture channels
02114     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02115     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02116     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02117     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02118
02119     No need to enable the counter, it's enabled automatically by hardware
02120     (the counter starts in response to a stimulus and generate a pulse */
02121
02122   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02123   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02124
02125   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02126   {
02127     /* Enable the main output */
02128     __HAL_TIM_MOE_ENABLE(htim);
02129   }
02130
02131   /* Return function status */
02132   return HAL_OK;
02133 }
02134
02135 /**
02136   * @brief  Stops the TIM One Pulse signal generation.
02137   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02138   *                the configuration information for TIM module.
02139   * @param  OutputChannel : TIM Channels to be disable.
02140   *          This parameter can be one of the following values:
02141   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02142   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02143   * @retval HAL status
02144   */
02145 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02146 {
02147   /* Disable the Capture compare and the Input Capture channels
02148   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02149   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02150   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02151   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02152
02153   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02154   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02155
02156   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02157   {
02158     /* Disable the Main Output */
02159     __HAL_TIM_MOE_DISABLE(htim);
02160   }
02161
02162   /* Disable the Peripheral */
02163   __HAL_TIM_DISABLE(htim);
02164
02165   /* Return function status */
02166   return HAL_OK;
02167 }
02168
02169 /**
02170   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02171   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02172   *                the configuration information for TIM module.
02173   * @param  OutputChannel : TIM Channels to be enabled.
02174   *          This parameter can be one of the following values:
02175   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02176   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02177   * @retval HAL status
02178   */
02179 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02180 {
02181   /* Enable the Capture compare and the Input Capture channels
02182     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02183     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02184     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02185     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02186
02187     No need to enable the counter, it's enabled automatically by hardware
02188     (the counter starts in response to a stimulus and generate a pulse */
02189
02190   /* Enable the TIM Capture/Compare 1 interrupt */
02191   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02192
02193   /* Enable the TIM Capture/Compare 2 interrupt */
02194   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02195
02196   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02197   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02198
02199   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02200   {
02201     /* Enable the main output */
02202     __HAL_TIM_MOE_ENABLE(htim);
02203   }
02204
02205   /* Return function status */
02206   return HAL_OK;
02207 }
02208
02209 /**
02210   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02211   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02212   *                the configuration information for TIM module.
02213   * @param  OutputChannel : TIM Channels to be enabled.
02214   *          This parameter can be one of the following values:
02215   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02216   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02217   * @retval HAL status
02218   */
02219 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02220 {
02221   /* Disable the TIM Capture/Compare 1 interrupt */
02222   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02223
02224   /* Disable the TIM Capture/Compare 2 interrupt */
02225   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02226
02227   /* Disable the Capture compare and the Input Capture channels
02228   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02229   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02230   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02231   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02232   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02233   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02234
02235   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02236   {
02237     /* Disable the Main Output */
02238     __HAL_TIM_MOE_DISABLE(htim);
02239   }
02240
02241   /* Disable the Peripheral */
02242    __HAL_TIM_DISABLE(htim);
02243
02244   /* Return function status */
02245   return HAL_OK;
02246 }
02247
02248 /**
02249   * @}
02250   */
02251
02252 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
02253  *  @brief    Time Encoder functions
02254  *
02255 @verbatim
02256   ==============================================================================
02257                           ##### Time Encoder functions #####
02258   ==============================================================================
02259   [..]
02260     This section provides functions allowing to:
02261     (+) Initialize and configure the TIM Encoder.
02262     (+) De-initialize the TIM Encoder.
02263     (+) Start the Time Encoder.
02264     (+) Stop the Time Encoder.
02265     (+) Start the Time Encoder and enable interrupt.
02266     (+) Stop the Time Encoder and disable interrupt.
02267     (+) Start the Time Encoder and enable DMA transfer.
02268     (+) Stop the Time Encoder and disable DMA transfer.
02269
02270 @endverbatim
02271   * @{
02272   */
02273 /**
02274   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
02275   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02276   *                the configuration information for TIM module.
02277   * @param  sConfig: TIM Encoder Interface configuration structure
02278   * @retval HAL status
02279   */
02280 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02281 {
02282   uint32_t tmpsmcr = 0;
02283   uint32_t tmpccmr1 = 0;
02284   uint32_t tmpccer = 0;
02285
02286   /* Check the TIM handle allocation */
02287   if(htim == NULL)
02288   {
02289     return HAL_ERROR;
02290   }
02291
02292   /* Check the parameters */
02293   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02294   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02295   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02296   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02297   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02298   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02299   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02300   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02301   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02302   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02303
02304   if(htim->State == HAL_TIM_STATE_RESET)
02305   {
02306     /* Allocate lock resource and initialize it */
02307     htim->Lock = HAL_UNLOCKED;
02308     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02309     HAL_TIM_Encoder_MspInit(htim);
02310   }
02311
02312   /* Set the TIM state */
02313   htim->State= HAL_TIM_STATE_BUSY;
02314
02315   /* Reset the SMS bits */
02316   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02317
02318   /* Configure the Time base in the Encoder Mode */
02319   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02320
02321   /* Get the TIMx SMCR register value */
02322   tmpsmcr = htim->Instance->SMCR;
02323
02324   /* Get the TIMx CCMR1 register value */
02325   tmpccmr1 = htim->Instance->CCMR1;
02326
02327   /* Get the TIMx CCER register value */
02328   tmpccer = htim->Instance->CCER;
02329
02330   /* Set the encoder Mode */
02331   tmpsmcr |= sConfig->EncoderMode;
02332
02333   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02334   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02335   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
02336
02337   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02338   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02339   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02340   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
02341   tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
02342
02343   /* Set the TI1 and the TI2 Polarities */
02344   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02345   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02346   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
02347
02348   /* Write to TIMx SMCR */
02349   htim->Instance->SMCR = tmpsmcr;
02350
02351   /* Write to TIMx CCMR1 */
02352   htim->Instance->CCMR1 = tmpccmr1;
02353
02354   /* Write to TIMx CCER */
02355   htim->Instance->CCER = tmpccer;
02356
02357   /* Initialize the TIM state*/
02358   htim->State= HAL_TIM_STATE_READY;
02359
02360   return HAL_OK;
02361 }
02362
02363 /**
02364   * @brief  DeInitializes the TIM Encoder interface
02365   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02366   *                the configuration information for TIM module.
02367   * @retval HAL status
02368   */
02369 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02370 {
02371   /* Check the parameters */
02372   assert_param(IS_TIM_INSTANCE(htim->Instance));
02373
02374   htim->State = HAL_TIM_STATE_BUSY;
02375
02376   /* Disable the TIM Peripheral Clock */
02377   __HAL_TIM_DISABLE(htim);
02378
02379   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02380   HAL_TIM_Encoder_MspDeInit(htim);
02381
02382   /* Change TIM state */
02383   htim->State = HAL_TIM_STATE_RESET;
02384
02385   /* Release Lock */
02386   __HAL_UNLOCK(htim);
02387
02388   return HAL_OK;
02389 }
02390
02391 /**
02392   * @brief  Initializes the TIM Encoder Interface MSP.
02393   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02394   *                the configuration information for TIM module.
02395   * @retval None
02396   */
02397 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02398 {
02399   /* Prevent unused argument(s) compilation warning */
02400   UNUSED(htim);
02401
02402   /* NOTE : This function Should not be modified, when the callback is needed,
02403             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02404    */
02405 }
02406
02407 /**
02408   * @brief  DeInitializes TIM Encoder Interface MSP.
02409   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02410   *                the configuration information for TIM module.
02411   * @retval None
02412   */
02413 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02414 {
02415   /* Prevent unused argument(s) compilation warning */
02416   UNUSED(htim);
02417
02418   /* NOTE : This function Should not be modified, when the callback is needed,
02419             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02420    */
02421 }
02422
02423 /**
02424   * @brief  Starts the TIM Encoder Interface.
02425   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02426   *                the configuration information for TIM module.
02427   * @param  Channel: TIM Channels to be enabled.
02428   *          This parameter can be one of the following values:
02429   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02430   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02431   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02432   * @retval HAL status
02433   */
02434 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02435 {
02436   /* Check the parameters */
02437   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02438
02439   /* Enable the encoder interface channels */
02440   switch (Channel)
02441   {
02442     case TIM_CHANNEL_1:
02443     {
02444       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02445       break;
02446     }
02447     case TIM_CHANNEL_2:
02448     {
02449       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02450       break;
02451     }
02452     default :
02453     {
02454      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02455      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02456      break;
02457     }
02458   }
02459   /* Enable the Peripheral */
02460   __HAL_TIM_ENABLE(htim);
02461
02462   /* Return function status */
02463   return HAL_OK;
02464 }
02465
02466 /**
02467   * @brief  Stops the TIM Encoder Interface.
02468   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02469   *                the configuration information for TIM module.
02470   * @param  Channel: TIM Channels to be disabled.
02471   *          This parameter can be one of the following values:
02472   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02473   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02474   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02475   * @retval HAL status
02476   */
02477 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02478 {
02479   /* Check the parameters */
02480     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02481
02482    /* Disable the Input Capture channels 1 and 2
02483     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02484   switch (Channel)
02485   {
02486     case TIM_CHANNEL_1:
02487     {
02488       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02489       break;
02490     }
02491     case TIM_CHANNEL_2:
02492     {
02493       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02494       break;
02495     }
02496     default :
02497     {
02498      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02499      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02500      break;
02501     }
02502   }
02503   /* Disable the Peripheral */
02504   __HAL_TIM_DISABLE(htim);
02505
02506   /* Return function status */
02507   return HAL_OK;
02508 }
02509
02510 /**
02511   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02512   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02513   *                the configuration information for TIM module.
02514   * @param  Channel: TIM Channels to be enabled.
02515   *          This parameter can be one of the following values:
02516   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02517   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02518   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02519   * @retval HAL status
02520   */
02521 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02522 {
02523   /* Check the parameters */
02524   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02525
02526   /* Enable the encoder interface channels */
02527   /* Enable the capture compare Interrupts 1 and/or 2 */
02528   switch (Channel)
02529   {
02530     case TIM_CHANNEL_1:
02531     {
02532       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02533       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02534       break;
02535     }
02536     case TIM_CHANNEL_2:
02537     {
02538       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02539       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02540       break;
02541     }
02542     default :
02543     {
02544      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02545      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02546      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02547      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02548      break;
02549     }
02550   }
02551
02552   /* Enable the Peripheral */
02553   __HAL_TIM_ENABLE(htim);
02554
02555   /* Return function status */
02556   return HAL_OK;
02557 }
02558
02559 /**
02560   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02561   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02562   *                the configuration information for TIM module.
02563   * @param  Channel: TIM Channels to be disabled.
02564   *          This parameter can be one of the following values:
02565   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02566   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02567   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02568   * @retval HAL status
02569   */
02570 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02571 {
02572   /* Check the parameters */
02573   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02574
02575   /* Disable the Input Capture channels 1 and 2
02576     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02577   if(Channel == TIM_CHANNEL_1)
02578   {
02579     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02580
02581     /* Disable the capture compare Interrupts 1 */
02582   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02583   }
02584   else if(Channel == TIM_CHANNEL_2)
02585   {
02586     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02587
02588     /* Disable the capture compare Interrupts 2 */
02589   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02590   }
02591   else
02592   {
02593     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02594     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02595
02596     /* Disable the capture compare Interrupts 1 and 2 */
02597     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02598     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02599   }
02600
02601   /* Disable the Peripheral */
02602   __HAL_TIM_DISABLE(htim);
02603
02604   /* Change the htim state */
02605   htim->State = HAL_TIM_STATE_READY;
02606
02607   /* Return function status */
02608   return HAL_OK;
02609 }
02610
02611 /**
02612   * @brief  Starts the TIM Encoder Interface in DMA mode.
02613   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02614   *                the configuration information for TIM module.
02615   * @param  Channel: TIM Channels to be enabled.
02616   *          This parameter can be one of the following values:
02617   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02618   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02619   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02620   * @param  pData1: The destination Buffer address for IC1.
02621   * @param  pData2: The destination Buffer address for IC2.
02622   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
02623   * @retval HAL status
02624   */
02625 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02626 {
02627   /* Check the parameters */
02628   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02629
02630   if((htim->State == HAL_TIM_STATE_BUSY))
02631   {
02632      return HAL_BUSY;
02633   }
02634   else if((htim->State == HAL_TIM_STATE_READY))
02635   {
02636     if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
02637     {
02638       return HAL_ERROR;
02639     }
02640     else
02641     {
02642       htim->State = HAL_TIM_STATE_BUSY;
02643     }
02644   }
02645
02646   switch (Channel)
02647   {
02648     case TIM_CHANNEL_1:
02649     {
02650       /* Set the DMA Period elapsed callback */
02651       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02652
02653       /* Set the DMA error callback */
02654       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
02655
02656       /* Enable the DMA Stream */
02657       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02658
02659       /* Enable the TIM Input Capture DMA request */
02660       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02661
02662       /* Enable the Peripheral */
02663       __HAL_TIM_ENABLE(htim);
02664
02665       /* Enable the Capture compare channel */
02666       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02667     }
02668     break;
02669
02670     case TIM_CHANNEL_2:
02671     {
02672       /* Set the DMA Period elapsed callback */
02673       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02674
02675       /* Set the DMA error callback */
02676       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
02677       /* Enable the DMA Stream */
02678       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02679
02680       /* Enable the TIM Input Capture  DMA request */
02681       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02682
02683       /* Enable the Peripheral */
02684       __HAL_TIM_ENABLE(htim);
02685
02686       /* Enable the Capture compare channel */
02687       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02688     }
02689     break;
02690
02691     case TIM_CHANNEL_ALL:
02692     {
02693       /* Set the DMA Period elapsed callback */
02694       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02695
02696       /* Set the DMA error callback */
02697       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
02698
02699       /* Enable the DMA Stream */
02700       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02701
02702       /* Set the DMA Period elapsed callback */
02703       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
02704
02705       /* Set the DMA error callback */
02706       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
02707
02708       /* Enable the DMA Stream */
02709       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02710
02711      /* Enable the Peripheral */
02712       __HAL_TIM_ENABLE(htim);
02713
02714       /* Enable the Capture compare channel */
02715       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02716       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02717
02718       /* Enable the TIM Input Capture  DMA request */
02719       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02720       /* Enable the TIM Input Capture  DMA request */
02721       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02722     }
02723     break;
02724
02725     default:
02726     break;
02727   }
02728   /* Return function status */
02729   return HAL_OK;
02730 }
02731
02732 /**
02733   * @brief  Stops the TIM Encoder Interface in DMA mode.
02734   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02735   *                the configuration information for TIM module.
02736   * @param  Channel: TIM Channels to be enabled.
02737   *          This parameter can be one of the following values:
02738   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02739   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02740   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02741   * @retval HAL status
02742   */
02743 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02744 {
02745   /* Check the parameters */
02746   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02747
02748   /* Disable the Input Capture channels 1 and 2
02749     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02750   if(Channel == TIM_CHANNEL_1)
02751   {
02752     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02753
02754     /* Disable the capture compare DMA Request 1 */
02755     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02756   }
02757   else if(Channel == TIM_CHANNEL_2)
02758   {
02759     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02760
02761     /* Disable the capture compare DMA Request 2 */
02762     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02763   }
02764   else
02765   {
02766     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02767     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02768
02769     /* Disable the capture compare DMA Request 1 and 2 */
02770     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02771     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02772   }
02773
02774   /* Disable the Peripheral */
02775   __HAL_TIM_DISABLE(htim);
02776
02777   /* Change the htim state */
02778   htim->State = HAL_TIM_STATE_READY;
02779
02780   /* Return function status */
02781   return HAL_OK;
02782 }
02783
02784 /**
02785   * @}
02786   */
02787 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02788  *  @brief    IRQ handler management
02789  *
02790 @verbatim
02791   ==============================================================================
02792                         ##### IRQ handler management #####
02793   ==============================================================================
02794   [..]
02795     This section provides Timer IRQ handler function.
02796
02797 @endverbatim
02798   * @{
02799   */
02800 /**
02801   * @brief  This function handles TIM interrupts requests.
02802   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02803   *                the configuration information for TIM module.
02804   * @retval None
02805   */
02806 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02807 {
02808   /* Capture compare 1 event */
02809   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02810   {
02811     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02812     {
02813       {
02814         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
02815         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02816
02817         /* Input capture event */
02818         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
02819         {
02820           HAL_TIM_IC_CaptureCallback(htim);
02821         }
02822         /* Output compare event */
02823         else
02824         {
02825           HAL_TIM_OC_DelayElapsedCallback(htim);
02826           HAL_TIM_PWM_PulseFinishedCallback(htim);
02827         }
02828         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02829       }
02830     }
02831   }
02832   /* Capture compare 2 event */
02833   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02834   {
02835     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02836     {
02837       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
02838       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02839       /* Input capture event */
02840       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
02841       {
02842         HAL_TIM_IC_CaptureCallback(htim);
02843       }
02844       /* Output compare event */
02845       else
02846       {
02847         HAL_TIM_OC_DelayElapsedCallback(htim);
02848         HAL_TIM_PWM_PulseFinishedCallback(htim);
02849       }
02850       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02851     }
02852   }
02853   /* Capture compare 3 event */
02854   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02855   {
02856     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02857     {
02858       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
02859       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02860       /* Input capture event */
02861       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
02862       {
02863         HAL_TIM_IC_CaptureCallback(htim);
02864       }
02865       /* Output compare event */
02866       else
02867       {
02868         HAL_TIM_OC_DelayElapsedCallback(htim);
02869         HAL_TIM_PWM_PulseFinishedCallback(htim);
02870       }
02871       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02872     }
02873   }
02874   /* Capture compare 4 event */
02875   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02876   {
02877     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02878     {
02879       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
02880       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02881       /* Input capture event */
02882       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
02883       {
02884         HAL_TIM_IC_CaptureCallback(htim);
02885       }
02886       /* Output compare event */
02887       else
02888       {
02889         HAL_TIM_OC_DelayElapsedCallback(htim);
02890         HAL_TIM_PWM_PulseFinishedCallback(htim);
02891       }
02892       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02893     }
02894   }
02895   /* TIM Update event */
02896   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02897   {
02898     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02899     {
02900       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
02901       HAL_TIM_PeriodElapsedCallback(htim);
02902     }
02903   }
02904   /* TIM Break input event */
02905   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02906   {
02907     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02908     {
02909       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02910       HAL_TIMEx_BreakCallback(htim);
02911     }
02912   }
02913
02914     /* TIM Break input event */
02915   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
02916   {
02917     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02918     {
02919       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02920       HAL_TIMEx_BreakCallback(htim);
02921     }
02922   }
02923
02924   /* TIM Trigger detection event */
02925   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02926   {
02927     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02928     {
02929       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
02930       HAL_TIM_TriggerCallback(htim);
02931     }
02932   }
02933   /* TIM commutation event */
02934   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02935   {
02936     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02937     {
02938       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
02939       HAL_TIMEx_CommutationCallback(htim);
02940     }
02941   }
02942 }
02943
02944 /**
02945   * @}
02946   */
02947
02948 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02949  *  @brief      Peripheral Control functions
02950  *
02951 @verbatim
02952   ==============================================================================
02953                    ##### Peripheral Control functions #####
02954   ==============================================================================
02955  [..]
02956    This section provides functions allowing to:
02957    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
02958    (+) Configure External Clock source.
02959    (+) Configure Complementary channels, break features and dead time.
02960    (+) Configure Master and the Slave synchronization.
02961    (+) Configure the DMA Burst Mode.
02962
02963 @endverbatim
02964   * @{
02965   */
02966
02967 /**
02968   * @brief  Initializes the TIM Output Compare Channels according to the specified
02969   *         parameters in the TIM_OC_InitTypeDef.
02970   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02971   *                the configuration information for TIM module.
02972   * @param  sConfig: TIM Output Compare configuration structure
02973   * @param  Channel: TIM Channels to be enabled.
02974   *          This parameter can be one of the following values:
02975   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02976   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02977   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02978   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02979   * @retval HAL status
02980   */
02981 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
02982 {
02983   /* Check the parameters */
02984   assert_param(IS_TIM_CHANNELS(Channel));
02985   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
02986   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
02987
02988   /* Check input state */
02989   __HAL_LOCK(htim);
02990
02991   htim->State = HAL_TIM_STATE_BUSY;
02992
02993   switch (Channel)
02994   {
02995     case TIM_CHANNEL_1:
02996     {
02997       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02998       /* Configure the TIM Channel 1 in Output Compare */
02999       TIM_OC1_SetConfig(htim->Instance, sConfig);
03000     }
03001     break;
03002
03003     case TIM_CHANNEL_2:
03004     {
03005       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03006       /* Configure the TIM Channel 2 in Output Compare */
03007       TIM_OC2_SetConfig(htim->Instance, sConfig);
03008     }
03009     break;
03010
03011     case TIM_CHANNEL_3:
03012     {
03013        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03014       /* Configure the TIM Channel 3 in Output Compare */
03015       TIM_OC3_SetConfig(htim->Instance, sConfig);
03016     }
03017     break;
03018
03019     case TIM_CHANNEL_4:
03020     {
03021       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03022       /* Configure the TIM Channel 4 in Output Compare */
03023       TIM_OC4_SetConfig(htim->Instance, sConfig);
03024     }
03025     break;
03026
03027     default:
03028     break;
03029   }
03030   htim->State = HAL_TIM_STATE_READY;
03031
03032   __HAL_UNLOCK(htim);
03033
03034   return HAL_OK;
03035 }
03036
03037 /**
03038   * @brief  Initializes the TIM Input Capture Channels according to the specified
03039   *         parameters in the TIM_IC_InitTypeDef.
03040   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03041   *                the configuration information for TIM module.
03042   * @param  sConfig: TIM Input Capture configuration structure
03043   * @param  Channel: TIM Channels to be enabled.
03044   *          This parameter can be one of the following values:
03045   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03046   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03047   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03048   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03049   * @retval HAL status
03050   */
03051 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
03052 {
03053   /* Check the parameters */
03054   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03055   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03056   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03057   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03058   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03059
03060   __HAL_LOCK(htim);
03061
03062   htim->State = HAL_TIM_STATE_BUSY;
03063
03064   if (Channel == TIM_CHANNEL_1)
03065   {
03066     /* TI1 Configuration */
03067     TIM_TI1_SetConfig(htim->Instance,
03068                sConfig->ICPolarity,
03069                sConfig->ICSelection,
03070                sConfig->ICFilter);
03071
03072     /* Reset the IC1PSC Bits */
03073     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03074
03075     /* Set the IC1PSC value */
03076     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03077   }
03078   else if (Channel == TIM_CHANNEL_2)
03079   {
03080     /* TI2 Configuration */
03081     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03082
03083     TIM_TI2_SetConfig(htim->Instance,
03084                       sConfig->ICPolarity,
03085                       sConfig->ICSelection,
03086                       sConfig->ICFilter);
03087
03088     /* Reset the IC2PSC Bits */
03089     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03090
03091     /* Set the IC2PSC value */
03092     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
03093   }
03094   else if (Channel == TIM_CHANNEL_3)
03095   {
03096     /* TI3 Configuration */
03097     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03098
03099     TIM_TI3_SetConfig(htim->Instance,
03100                sConfig->ICPolarity,
03101                sConfig->ICSelection,
03102                sConfig->ICFilter);
03103
03104     /* Reset the IC3PSC Bits */
03105     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03106
03107     /* Set the IC3PSC value */
03108     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03109   }
03110   else
03111   {
03112     /* TI4 Configuration */
03113     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03114
03115     TIM_TI4_SetConfig(htim->Instance,
03116                sConfig->ICPolarity,
03117                sConfig->ICSelection,
03118                sConfig->ICFilter);
03119
03120     /* Reset the IC4PSC Bits */
03121     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03122
03123     /* Set the IC4PSC value */
03124     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
03125   }
03126
03127   htim->State = HAL_TIM_STATE_READY;
03128
03129   __HAL_UNLOCK(htim);
03130
03131   return HAL_OK;
03132 }
03133
03134 /**
03135   * @brief  Initializes the TIM PWM  channels according to the specified
03136   *         parameters in the TIM_OC_InitTypeDef.
03137   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03138   *                the configuration information for TIM module.
03139   * @param  sConfig: TIM PWM configuration structure
03140   * @param  Channel: TIM Channels to be enabled.
03141   *          This parameter can be one of the following values:
03142   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03143   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03144   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03145   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03146   * @retval HAL status
03147   */
03148 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
03149 {
03150   __HAL_LOCK(htim);
03151
03152   /* Check the parameters */
03153   assert_param(IS_TIM_CHANNELS(Channel));
03154   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03155   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03156   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03157
03158   htim->State = HAL_TIM_STATE_BUSY;
03159
03160   switch (Channel)
03161   {
03162     case TIM_CHANNEL_1:
03163     {
03164       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03165       /* Configure the Channel 1 in PWM mode */
03166       TIM_OC1_SetConfig(htim->Instance, sConfig);
03167
03168       /* Set the Preload enable bit for channel1 */
03169       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03170
03171       /* Configure the Output Fast mode */
03172       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03173       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03174     }
03175     break;
03176
03177     case TIM_CHANNEL_2:
03178     {
03179       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03180       /* Configure the Channel 2 in PWM mode */
03181       TIM_OC2_SetConfig(htim->Instance, sConfig);
03182
03183       /* Set the Preload enable bit for channel2 */
03184       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03185
03186       /* Configure the Output Fast mode */
03187       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03188       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
03189     }
03190     break;
03191
03192     case TIM_CHANNEL_3:
03193     {
03194       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03195       /* Configure the Channel 3 in PWM mode */
03196       TIM_OC3_SetConfig(htim->Instance, sConfig);
03197
03198       /* Set the Preload enable bit for channel3 */
03199       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03200
03201      /* Configure the Output Fast mode */
03202       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03203       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03204     }
03205     break;
03206
03207     case TIM_CHANNEL_4:
03208     {
03209       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03210       /* Configure the Channel 4 in PWM mode */
03211       TIM_OC4_SetConfig(htim->Instance, sConfig);
03212
03213       /* Set the Preload enable bit for channel4 */
03214       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03215
03216      /* Configure the Output Fast mode */
03217       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03218       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
03219     }
03220     break;
03221
03222     default:
03223     break;
03224   }
03225
03226   htim->State = HAL_TIM_STATE_READY;
03227
03228   __HAL_UNLOCK(htim);
03229
03230   return HAL_OK;
03231 }
03232
03233 /**
03234   * @brief  Initializes the TIM One Pulse Channels according to the specified
03235   *         parameters in the TIM_OnePulse_InitTypeDef.
03236   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03237   *                the configuration information for TIM module.
03238   * @param  sConfig: TIM One Pulse configuration structure
03239   * @param  OutputChannel: TIM Channels to be enabled.
03240   *          This parameter can be one of the following values:
03241   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03242   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03243   * @param  InputChannel: TIM Channels to be enabled.
03244   *          This parameter can be one of the following values:
03245   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03246   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03247   * @retval HAL status
03248   */
03249 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03250 {
03251   TIM_OC_InitTypeDef temp1;
03252
03253   /* Check the parameters */
03254   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03255   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03256
03257   if(OutputChannel != InputChannel)
03258   {
03259     __HAL_LOCK(htim);
03260
03261     htim->State = HAL_TIM_STATE_BUSY;
03262
03263     /* Extract the Output compare configuration from sConfig structure */
03264     temp1.OCMode = sConfig->OCMode;
03265     temp1.Pulse = sConfig->Pulse;
03266     temp1.OCPolarity = sConfig->OCPolarity;
03267     temp1.OCNPolarity = sConfig->OCNPolarity;
03268     temp1.OCIdleState = sConfig->OCIdleState;
03269     temp1.OCNIdleState = sConfig->OCNIdleState;
03270
03271     switch (OutputChannel)
03272     {
03273       case TIM_CHANNEL_1:
03274       {
03275         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03276
03277         TIM_OC1_SetConfig(htim->Instance, &temp1);
03278       }
03279       break;
03280       case TIM_CHANNEL_2:
03281       {
03282         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03283
03284         TIM_OC2_SetConfig(htim->Instance, &temp1);
03285       }
03286       break;
03287       default:
03288       break;
03289     }
03290     switch (InputChannel)
03291     {
03292       case TIM_CHANNEL_1:
03293       {
03294         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03295
03296         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03297                         sConfig->ICSelection, sConfig->ICFilter);
03298
03299         /* Reset the IC1PSC Bits */
03300         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03301
03302         /* Select the Trigger source */
03303         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03304         htim->Instance->SMCR |= TIM_TS_TI1FP1;
03305
03306         /* Select the Slave Mode */
03307         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03308         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03309       }
03310       break;
03311       case TIM_CHANNEL_2:
03312       {
03313         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03314
03315         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03316                  sConfig->ICSelection, sConfig->ICFilter);
03317
03318         /* Reset the IC2PSC Bits */
03319         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03320
03321         /* Select the Trigger source */
03322         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03323         htim->Instance->SMCR |= TIM_TS_TI2FP2;
03324
03325         /* Select the Slave Mode */
03326         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03327         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03328       }
03329       break;
03330
03331       default:
03332       break;
03333     }
03334
03335     htim->State = HAL_TIM_STATE_READY;
03336
03337     __HAL_UNLOCK(htim);
03338
03339     return HAL_OK;
03340   }
03341   else
03342   {
03343     return HAL_ERROR;
03344   }
03345 }
03346
03347 /**
03348   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03349   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03350   *                the configuration information for TIM module.
03351   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
03352   *         This parameters can be on of the following values:
03353   *            @arg TIM_DMABASE_CR1
03354   *            @arg TIM_DMABASE_CR2
03355   *            @arg TIM_DMABASE_SMCR
03356   *            @arg TIM_DMABASE_DIER
03357   *            @arg TIM_DMABASE_SR
03358   *            @arg TIM_DMABASE_EGR
03359   *            @arg TIM_DMABASE_CCMR1
03360   *            @arg TIM_DMABASE_CCMR2
03361   *            @arg TIM_DMABASE_CCER
03362   *            @arg TIM_DMABASE_CNT
03363   *            @arg TIM_DMABASE_PSC
03364   *            @arg TIM_DMABASE_ARR
03365   *            @arg TIM_DMABASE_RCR
03366   *            @arg TIM_DMABASE_CCR1
03367   *            @arg TIM_DMABASE_CCR2
03368   *            @arg TIM_DMABASE_CCR3
03369   *            @arg TIM_DMABASE_CCR4
03370   *            @arg TIM_DMABASE_BDTR
03371   *            @arg TIM_DMABASE_DCR
03372   * @param  BurstRequestSrc: TIM DMA Request sources.
03373   *         This parameters can be on of the following values:
03374   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03375   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03376   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03377   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03378   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03379   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03380   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03381   * @param  BurstBuffer: The Buffer address.
03382   * @param  BurstLength: DMA Burst length. This parameter can be one value
03383   *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03384   * @retval HAL status
03385   */
03386 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03387                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
03388 {
03389   /* Check the parameters */
03390   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03391   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03392   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03393   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03394
03395   if((htim->State == HAL_TIM_STATE_BUSY))
03396   {
03397      return HAL_BUSY;
03398   }
03399   else if((htim->State == HAL_TIM_STATE_READY))
03400   {
03401     if((BurstBuffer == 0 ) && (BurstLength > 0))
03402     {
03403       return HAL_ERROR;
03404     }
03405     else
03406     {
03407       htim->State = HAL_TIM_STATE_BUSY;
03408     }
03409   }
03410   switch(BurstRequestSrc)
03411   {
03412     case TIM_DMA_UPDATE:
03413     {
03414       /* Set the DMA Period elapsed callback */
03415       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03416
03417       /* Set the DMA error callback */
03418       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
03419
03420       /* Enable the DMA Stream */
03421       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03422     }
03423     break;
03424     case TIM_DMA_CC1:
03425     {
03426       /* Set the DMA Period elapsed callback */
03427       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
03428
03429       /* Set the DMA error callback */
03430       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
03431
03432       /* Enable the DMA Stream */
03433       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03434     }
03435     break;
03436     case TIM_DMA_CC2:
03437     {
03438       /* Set the DMA Period elapsed callback */
03439       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
03440
03441       /* Set the DMA error callback */
03442       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
03443
03444       /* Enable the DMA Stream */
03445       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03446     }
03447     break;
03448     case TIM_DMA_CC3:
03449     {
03450       /* Set the DMA Period elapsed callback */
03451       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
03452
03453       /* Set the DMA error callback */
03454       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
03455
03456       /* Enable the DMA Stream */
03457       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03458     }
03459     break;
03460     case TIM_DMA_CC4:
03461     {
03462       /* Set the DMA Period elapsed callback */
03463       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
03464
03465       /* Set the DMA error callback */
03466       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
03467
03468       /* Enable the DMA Stream */
03469       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03470     }
03471     break;
03472     case TIM_DMA_COM:
03473     {
03474       /* Set the DMA Period elapsed callback */
03475       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
03476
03477       /* Set the DMA error callback */
03478       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
03479
03480       /* Enable the DMA Stream */
03481       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03482     }
03483     break;
03484     case TIM_DMA_TRIGGER:
03485     {
03486       /* Set the DMA Period elapsed callback */
03487       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03488
03489       /* Set the DMA error callback */
03490       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
03491
03492       /* Enable the DMA Stream */
03493       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03494     }
03495     break;
03496     default:
03497     break;
03498   }
03499    /* configure the DMA Burst Mode */
03500    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03501
03502    /* Enable the TIM DMA Request */
03503    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03504
03505    htim->State = HAL_TIM_STATE_READY;
03506
03507   /* Return function status */
03508   return HAL_OK;
03509 }
03510
03511 /**
03512   * @brief  Stops the TIM DMA Burst mode
03513   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03514   *                the configuration information for TIM module.
03515   * @param  BurstRequestSrc: TIM DMA Request sources to disable
03516   * @retval HAL status
03517   */
03518 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03519 {
03520   /* Check the parameters */
03521   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03522
03523   /* Abort the DMA transfer (at least disable the DMA channel) */
03524   switch(BurstRequestSrc)
03525   {
03526     case TIM_DMA_UPDATE:
03527     {
03528       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03529     }
03530     break;
03531     case TIM_DMA_CC1:
03532     {
03533       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03534     }
03535     break;
03536     case TIM_DMA_CC2:
03537     {
03538       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03539     }
03540     break;
03541     case TIM_DMA_CC3:
03542     {
03543       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03544     }
03545     break;
03546     case TIM_DMA_CC4:
03547     {
03548       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03549     }
03550     break;
03551     case TIM_DMA_COM:
03552     {
03553       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03554     }
03555     break;
03556     case TIM_DMA_TRIGGER:
03557     {
03558       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03559     }
03560     break;
03561     default:
03562     break;
03563   }
03564
03565   /* Disable the TIM Update DMA request */
03566   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03567
03568   /* Return function status */
03569   return HAL_OK;
03570 }
03571
03572 /**
03573   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
03574   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03575   *                the configuration information for TIM module.
03576   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
03577   *         This parameters can be on of the following values:
03578   *            @arg TIM_DMABASE_CR1
03579   *            @arg TIM_DMABASE_CR2
03580   *            @arg TIM_DMABASE_SMCR
03581   *            @arg TIM_DMABASE_DIER
03582   *            @arg TIM_DMABASE_SR
03583   *            @arg TIM_DMABASE_EGR
03584   *            @arg TIM_DMABASE_CCMR1
03585   *            @arg TIM_DMABASE_CCMR2
03586   *            @arg TIM_DMABASE_CCER
03587   *            @arg TIM_DMABASE_CNT
03588   *            @arg TIM_DMABASE_PSC
03589   *            @arg TIM_DMABASE_ARR
03590   *            @arg TIM_DMABASE_RCR
03591   *            @arg TIM_DMABASE_CCR1
03592   *            @arg TIM_DMABASE_CCR2
03593   *            @arg TIM_DMABASE_CCR3
03594   *            @arg TIM_DMABASE_CCR4
03595   *            @arg TIM_DMABASE_BDTR
03596   *            @arg TIM_DMABASE_DCR
03597   * @param  BurstRequestSrc: TIM DMA Request sources.
03598   *         This parameters can be on of the following values:
03599   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03600   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03601   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03602   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03603   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03604   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03605   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03606   * @param  BurstBuffer: The Buffer address.
03607   * @param  BurstLength: DMA Burst length. This parameter can be one value
03608   *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03609   * @retval HAL status
03610   */
03611 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03612                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03613 {
03614   /* Check the parameters */
03615   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03616   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03617   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03618   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03619
03620   if((htim->State == HAL_TIM_STATE_BUSY))
03621   {
03622      return HAL_BUSY;
03623   }
03624   else if((htim->State == HAL_TIM_STATE_READY))
03625   {
03626     if((BurstBuffer == 0 ) && (BurstLength > 0))
03627     {
03628       return HAL_ERROR;
03629     }
03630     else
03631     {
03632       htim->State = HAL_TIM_STATE_BUSY;
03633     }
03634   }
03635   switch(BurstRequestSrc)
03636   {
03637     case TIM_DMA_UPDATE:
03638     {
03639       /* Set the DMA Period elapsed callback */
03640       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03641
03642       /* Set the DMA error callback */
03643       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
03644
03645       /* Enable the DMA Stream */
03646        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03647     }
03648     break;
03649     case TIM_DMA_CC1:
03650     {
03651       /* Set the DMA Period elapsed callback */
03652       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
03653
03654       /* Set the DMA error callback */
03655       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
03656
03657       /* Enable the DMA Stream */
03658       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03659     }
03660     break;
03661     case TIM_DMA_CC2:
03662     {
03663       /* Set the DMA Period elapsed callback */
03664       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
03665
03666       /* Set the DMA error callback */
03667       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
03668
03669       /* Enable the DMA Stream */
03670       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03671     }
03672     break;
03673     case TIM_DMA_CC3:
03674     {
03675       /* Set the DMA Period elapsed callback */
03676       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
03677
03678       /* Set the DMA error callback */
03679       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
03680
03681       /* Enable the DMA Stream */
03682       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03683     }
03684     break;
03685     case TIM_DMA_CC4:
03686     {
03687       /* Set the DMA Period elapsed callback */
03688       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
03689
03690       /* Set the DMA error callback */
03691       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
03692
03693       /* Enable the DMA Stream */
03694       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03695     }
03696     break;
03697     case TIM_DMA_COM:
03698     {
03699       /* Set the DMA Period elapsed callback */
03700       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
03701
03702       /* Set the DMA error callback */
03703       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
03704
03705       /* Enable the DMA Stream */
03706       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03707     }
03708     break;
03709     case TIM_DMA_TRIGGER:
03710     {
03711       /* Set the DMA Period elapsed callback */
03712       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03713
03714       /* Set the DMA error callback */
03715       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
03716
03717       /* Enable the DMA Stream */
03718       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03719     }
03720     break;
03721     default:
03722     break;
03723   }
03724
03725   /* configure the DMA Burst Mode */
03726   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03727
03728   /* Enable the TIM DMA Request */
03729   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03730
03731   htim->State = HAL_TIM_STATE_READY;
03732
03733   /* Return function status */
03734   return HAL_OK;
03735 }
03736
03737 /**
03738   * @brief  Stop the DMA burst reading
03739   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03740   *                the configuration information for TIM module.
03741   * @param  BurstRequestSrc: TIM DMA Request sources to disable.
03742   * @retval HAL status
03743   */
03744 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03745 {
03746   /* Check the parameters */
03747   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03748
03749   /* Abort the DMA transfer (at least disable the DMA channel) */
03750   switch(BurstRequestSrc)
03751   {
03752     case TIM_DMA_UPDATE:
03753     {
03754       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03755     }
03756     break;
03757     case TIM_DMA_CC1:
03758     {
03759       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03760     }
03761     break;
03762     case TIM_DMA_CC2:
03763     {
03764       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03765     }
03766     break;
03767     case TIM_DMA_CC3:
03768     {
03769       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03770     }
03771     break;
03772     case TIM_DMA_CC4:
03773     {
03774       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03775     }
03776     break;
03777     case TIM_DMA_COM:
03778     {
03779       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03780     }
03781     break;
03782     case TIM_DMA_TRIGGER:
03783     {
03784       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03785     }
03786     break;
03787     default:
03788     break;
03789   }
03790
03791   /* Disable the TIM Update DMA request */
03792   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03793
03794   /* Return function status */
03795   return HAL_OK;
03796 }
03797
03798 /**
03799   * @brief  Generate a software event
03800   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03801   *                the configuration information for TIM module.
03802   * @param  EventSource: specifies the event source.
03803   *          This parameter can be one of the following values:
03804   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03805   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
03806   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
03807   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
03808   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
03809   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
03810   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
03811   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
03812   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
03813   * @note   TIM6 and TIM7 can only generate an update event.
03814   * @note   TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
03815   * @retval HAL status
03816   */
03817
03818 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03819 {
03820   /* Check the parameters */
03821   assert_param(IS_TIM_INSTANCE(htim->Instance));
03822   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03823
03824   /* Process Locked */
03825   __HAL_LOCK(htim);
03826
03827   /* Change the TIM state */
03828   htim->State = HAL_TIM_STATE_BUSY;
03829
03830   /* Set the event sources */
03831   htim->Instance->EGR = EventSource;
03832
03833   /* Change the TIM state */
03834   htim->State = HAL_TIM_STATE_READY;
03835
03836   __HAL_UNLOCK(htim);
03837
03838   /* Return function status */
03839   return HAL_OK;
03840 }
03841
03842 /**
03843   * @brief  Configures the OCRef clear feature
03844   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03845   *                the configuration information for TIM module.
03846   * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
03847   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03848   * @param  Channel: specifies the TIM Channel.
03849   *          This parameter can be one of the following values:
03850   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03851   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03852   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03853   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03854   * @retval HAL status
03855   */
03856 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
03857 {
03858   /* Check the parameters */
03859   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03860   assert_param(IS_TIM_CHANNELS(Channel));
03861   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03862
03863   /* Process Locked */
03864   __HAL_LOCK(htim);
03865
03866   htim->State = HAL_TIM_STATE_BUSY;
03867
03868   if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
03869   {
03870     assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03871     assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03872     assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03873
03874     TIM_ETR_SetConfig(htim->Instance,
03875                       sClearInputConfig->ClearInputPrescaler,
03876                       sClearInputConfig->ClearInputPolarity,
03877                       sClearInputConfig->ClearInputFilter);
03878   }
03879
03880   switch (Channel)
03881   {
03882     case TIM_CHANNEL_1:
03883     {
03884       if(sClearInputConfig->ClearInputState != RESET)
03885       {
03886         /* Enable the Ocref clear feature for Channel 1 */
03887         htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
03888       }
03889       else
03890       {
03891         /* Disable the Ocref clear feature for Channel 1 */
03892         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
03893       }
03894     }
03895     break;
03896     case TIM_CHANNEL_2:
03897     {
03898       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03899       if(sClearInputConfig->ClearInputState != RESET)
03900       {
03901         /* Enable the Ocref clear feature for Channel 2 */
03902         htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
03903       }
03904       else
03905       {
03906         /* Disable the Ocref clear feature for Channel 2 */
03907         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
03908       }
03909     }
03910     break;
03911     case TIM_CHANNEL_3:
03912     {
03913       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03914       if(sClearInputConfig->ClearInputState != RESET)
03915       {
03916         /* Enable the Ocref clear feature for Channel 3 */
03917         htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
03918       }
03919       else
03920       {
03921         /* Disable the Ocref clear feature for Channel 3 */
03922         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
03923       }
03924     }
03925     break;
03926     case TIM_CHANNEL_4:
03927     {
03928       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03929       if(sClearInputConfig->ClearInputState != RESET)
03930       {
03931         /* Enable the Ocref clear feature for Channel 4 */
03932         htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
03933       }
03934       else
03935       {
03936         /* Disable the Ocref clear feature for Channel 4 */
03937         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
03938       }
03939     }
03940     break;
03941     default:
03942     break;
03943   }
03944
03945   htim->State = HAL_TIM_STATE_READY;
03946
03947   __HAL_UNLOCK(htim);
03948
03949   return HAL_OK;
03950 }
03951
03952 /**
03953   * @brief   Configures the clock source to be used
03954   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03955   *                the configuration information for TIM module.
03956   * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
03957   *         contains the clock source information for the TIM peripheral.
03958   * @retval HAL status
03959   */
03960 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
03961 {
03962   uint32_t tmpsmcr = 0;
03963
03964   /* Process Locked */
03965   __HAL_LOCK(htim);
03966
03967   htim->State = HAL_TIM_STATE_BUSY;
03968
03969   /* Check the parameters */
03970   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
03971
03972   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
03973   tmpsmcr = htim->Instance->SMCR;
03974   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03975   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03976   htim->Instance->SMCR = tmpsmcr;
03977
03978   switch (sClockSourceConfig->ClockSource)
03979   {
03980     case TIM_CLOCKSOURCE_INTERNAL:
03981     {
03982       assert_param(IS_TIM_INSTANCE(htim->Instance));
03983       /* Disable slave mode to clock the prescaler directly with the internal clock */
03984       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03985     }
03986     break;
03987
03988     case TIM_CLOCKSOURCE_ETRMODE1:
03989     {
03990       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
03991       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03992       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03993       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03994       /* Configure the ETR Clock source */
03995       TIM_ETR_SetConfig(htim->Instance,
03996                         sClockSourceConfig->ClockPrescaler,
03997                         sClockSourceConfig->ClockPolarity,
03998                         sClockSourceConfig->ClockFilter);
03999       /* Get the TIMx SMCR register value */
04000       tmpsmcr = htim->Instance->SMCR;
04001       /* Reset the SMS and TS Bits */
04002       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04003       /* Select the External clock mode1 and the ETRF trigger */
04004       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
04005       /* Write to TIMx SMCR */
04006       htim->Instance->SMCR = tmpsmcr;
04007     }
04008     break;
04009
04010     case TIM_CLOCKSOURCE_ETRMODE2:
04011     {
04012       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
04013       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04014       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04015       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04016
04017       /* Configure the ETR Clock source */
04018       TIM_ETR_SetConfig(htim->Instance,
04019                         sClockSourceConfig->ClockPrescaler,
04020                         sClockSourceConfig->ClockPolarity,
04021                         sClockSourceConfig->ClockFilter);
04022       /* Enable the External clock mode2 */
04023       htim->Instance->SMCR |= TIM_SMCR_ECE;
04024     }
04025     break;
04026
04027     case TIM_CLOCKSOURCE_TI1:
04028     {
04029       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04030
04031       /* Check TI1 input conditioning related parameters */
04032       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04033       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04034
04035       TIM_TI1_ConfigInputStage(htim->Instance,
04036                         sClockSourceConfig->ClockPolarity,
04037                         sClockSourceConfig->ClockFilter);
04038       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04039     }
04040     break;
04041     case TIM_CLOCKSOURCE_TI2:
04042     {
04043       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04044
04045       /* Check TI1 input conditioning related parameters */
04046       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04047       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04048
04049       TIM_TI2_ConfigInputStage(htim->Instance,
04050                         sClockSourceConfig->ClockPolarity,
04051                         sClockSourceConfig->ClockFilter);
04052       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04053     }
04054     break;
04055     case TIM_CLOCKSOURCE_TI1ED:
04056     {
04057       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04058       /* Check TI1 input conditioning related parameters */
04059       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04060       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04061
04062       TIM_TI1_ConfigInputStage(htim->Instance,
04063                         sClockSourceConfig->ClockPolarity,
04064                         sClockSourceConfig->ClockFilter);
04065       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04066     }
04067     break;
04068     case TIM_CLOCKSOURCE_ITR0:
04069     {
04070       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04071       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04072     }
04073     break;
04074     case TIM_CLOCKSOURCE_ITR1:
04075     {
04076       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04077       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04078     }
04079     break;
04080     case TIM_CLOCKSOURCE_ITR2:
04081     {
04082       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04083       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04084     }
04085     break;
04086     case TIM_CLOCKSOURCE_ITR3:
04087     {
04088       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04089       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04090     }
04091     break;
04092
04093     default:
04094     break;
04095   }
04096   htim->State = HAL_TIM_STATE_READY;
04097
04098   __HAL_UNLOCK(htim);
04099
04100   return HAL_OK;
04101 }
04102
04103 /**
04104   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04105   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04106   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04107   *                the configuration information for TIM module.
04108   * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
04109   *         output of a XOR gate.
04110   *         This parameter can be one of the following values:
04111   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04112   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04113   *            pins are connected to the TI1 input (XOR combination)
04114   * @retval HAL status
04115   */
04116 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04117 {
04118   uint32_t tmpcr2 = 0;
04119
04120   /* Check the parameters */
04121   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04122   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04123
04124   /* Get the TIMx CR2 register value */
04125   tmpcr2 = htim->Instance->CR2;
04126
04127   /* Reset the TI1 selection */
04128   tmpcr2 &= ~TIM_CR2_TI1S;
04129
04130   /* Set the TI1 selection */
04131   tmpcr2 |= TI1_Selection;
04132
04133   /* Write to TIMxCR2 */
04134   htim->Instance->CR2 = tmpcr2;
04135
04136   return HAL_OK;
04137 }
04138
04139 /**
04140   * @brief  Configures the TIM in Slave mode
04141   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04142   *                the configuration information for TIM module.
04143   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04144   *         contains the selected trigger (internal trigger input, filtered
04145   *         timer input or external trigger input) and the ) and the Slave
04146   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04147   * @retval HAL status
04148   */
04149 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04150 {
04151   uint32_t tmpsmcr  = 0;
04152   uint32_t tmpccmr1 = 0;
04153   uint32_t tmpccer = 0;
04154
04155   /* Check the parameters */
04156   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04157   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04158   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04159
04160   __HAL_LOCK(htim);
04161
04162   htim->State = HAL_TIM_STATE_BUSY;
04163
04164   /* Get the TIMx SMCR register value */
04165   tmpsmcr = htim->Instance->SMCR;
04166
04167   /* Reset the Trigger Selection Bits */
04168   tmpsmcr &= ~TIM_SMCR_TS;
04169   /* Set the Input Trigger source */
04170   tmpsmcr |= sSlaveConfig->InputTrigger;
04171
04172   /* Reset the slave mode Bits */
04173   tmpsmcr &= ~TIM_SMCR_SMS;
04174   /* Set the slave mode */
04175   tmpsmcr |= sSlaveConfig->SlaveMode;
04176
04177   /* Write to TIMx SMCR */
04178   htim->Instance->SMCR = tmpsmcr;
04179
04180   /* Configure the trigger prescaler, filter, and polarity */
04181   switch (sSlaveConfig->InputTrigger)
04182   {
04183   case TIM_TS_ETRF:
04184     {
04185       /* Check the parameters */
04186       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
04187       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
04188       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04189       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04190       /* Configure the ETR Trigger source */
04191       TIM_ETR_SetConfig(htim->Instance,
04192                         sSlaveConfig->TriggerPrescaler,
04193                         sSlaveConfig->TriggerPolarity,
04194                         sSlaveConfig->TriggerFilter);
04195     }
04196     break;
04197
04198   case TIM_TS_TI1F_ED:
04199     {
04200       /* Check the parameters */
04201       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04202       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04203
04204       /* Disable the Channel 1: Reset the CC1E Bit */
04205       tmpccer = htim->Instance->CCER;
04206       htim->Instance->CCER &= ~TIM_CCER_CC1E;
04207       tmpccmr1 = htim->Instance->CCMR1;
04208
04209       /* Set the filter */
04210       tmpccmr1 &= ~TIM_CCMR1_IC1F;
04211       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
04212
04213       /* Write to TIMx CCMR1 and CCER registers */
04214       htim->Instance->CCMR1 = tmpccmr1;
04215       htim->Instance->CCER = tmpccer;
04216
04217     }
04218     break;
04219
04220   case TIM_TS_TI1FP1:
04221     {
04222       /* Check the parameters */
04223       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04224       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04225       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04226
04227       /* Configure TI1 Filter and Polarity */
04228       TIM_TI1_ConfigInputStage(htim->Instance,
04229                                sSlaveConfig->TriggerPolarity,
04230                                sSlaveConfig->TriggerFilter);
04231     }
04232     break;
04233
04234   case TIM_TS_TI2FP2:
04235     {
04236       /* Check the parameters */
04237       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04238       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04239       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04240
04241       /* Configure TI2 Filter and Polarity */
04242       TIM_TI2_ConfigInputStage(htim->Instance,
04243                                 sSlaveConfig->TriggerPolarity,
04244                                 sSlaveConfig->TriggerFilter);
04245     }
04246     break;
04247
04248   case TIM_TS_ITR0:
04249     {
04250       /* Check the parameter */
04251       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04252     }
04253     break;
04254
04255   case TIM_TS_ITR1:
04256     {
04257       /* Check the parameter */
04258       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04259     }
04260     break;
04261
04262   case TIM_TS_ITR2:
04263     {
04264       /* Check the parameter */
04265       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04266     }
04267     break;
04268
04269   case TIM_TS_ITR3:
04270     {
04271       /* Check the parameter */
04272       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04273     }
04274     break;
04275
04276   default:
04277     break;
04278   }
04279
04280   htim->State = HAL_TIM_STATE_READY;
04281
04282   __HAL_UNLOCK(htim);
04283
04284   return HAL_OK;
04285 }
04286
04287 /**
04288   * @brief  Configures the TIM in Slave mode in interrupt mode
04289   * @param  htim: TIM handle.
04290   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04291   *         contains the selected trigger (internal trigger input, filtered
04292   *         timer input or external trigger input) and the ) and the Slave
04293   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04294   * @retval HAL status
04295   */
04296 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04297                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04298 {
04299   /* Check the parameters */
04300   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04301   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04302   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04303
04304   __HAL_LOCK(htim);
04305
04306   htim->State = HAL_TIM_STATE_BUSY;
04307
04308   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04309
04310   /* Enable Trigger Interrupt */
04311   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04312
04313   /* Disable Trigger DMA request */
04314   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04315
04316   htim->State = HAL_TIM_STATE_READY;
04317
04318   __HAL_UNLOCK(htim);
04319
04320   return HAL_OK;
04321 }
04322
04323 /**
04324   * @brief  Read the captured value from Capture Compare unit
04325   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04326   *                the configuration information for TIM module.
04327   * @param  Channel: TIM Channels to be enabled.
04328   *          This parameter can be one of the following values:
04329   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04330   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04331   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04332   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04333   * @retval Captured value
04334   */
04335 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04336 {
04337   uint32_t tmpreg = 0;
04338
04339   __HAL_LOCK(htim);
04340
04341   switch (Channel)
04342   {
04343     case TIM_CHANNEL_1:
04344     {
04345       /* Check the parameters */
04346       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04347
04348       /* Return the capture 1 value */
04349       tmpreg = htim->Instance->CCR1;
04350
04351       break;
04352     }
04353     case TIM_CHANNEL_2:
04354     {
04355       /* Check the parameters */
04356       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04357
04358       /* Return the capture 2 value */
04359       tmpreg = htim->Instance->CCR2;
04360
04361       break;
04362     }
04363
04364     case TIM_CHANNEL_3:
04365     {
04366       /* Check the parameters */
04367       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04368
04369       /* Return the capture 3 value */
04370       tmpreg = htim->Instance->CCR3;
04371
04372       break;
04373     }
04374
04375     case TIM_CHANNEL_4:
04376     {
04377       /* Check the parameters */
04378       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04379
04380       /* Return the capture 4 value */
04381       tmpreg = htim->Instance->CCR4;
04382
04383       break;
04384     }
04385
04386     default:
04387     break;
04388   }
04389
04390   __HAL_UNLOCK(htim);
04391   return tmpreg;
04392 }
04393
04394 /**
04395   * @}
04396   */
04397
04398 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04399  *  @brief    TIM Callbacks functions
04400  *
04401 @verbatim
04402   ==============================================================================
04403                         ##### TIM Callbacks functions #####
04404   ==============================================================================
04405  [..]
04406    This section provides TIM callback functions:
04407    (+) Timer Period elapsed callback
04408    (+) Timer Output Compare callback
04409    (+) Timer Input capture callback
04410    (+) Timer Trigger callback
04411    (+) Timer Error callback
04412
04413 @endverbatim
04414   * @{
04415   */
04416
04417 /**
04418   * @brief  Period elapsed callback in non blocking mode
04419   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04420   *                the configuration information for TIM module.
04421   * @retval None
04422   */
04423 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04424 {
04425   /* Prevent unused argument(s) compilation warning */
04426   UNUSED(htim);
04427
04428   /* NOTE : This function Should not be modified, when the callback is needed,
04429             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04430    */
04431
04432 }
04433 /**
04434   * @brief  Output Compare callback in non blocking mode
04435   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04436   *                the configuration information for TIM module.
04437   * @retval None
04438   */
04439 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04440 {
04441   /* Prevent unused argument(s) compilation warning */
04442   UNUSED(htim);
04443
04444   /* NOTE : This function Should not be modified, when the callback is needed,
04445             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04446    */
04447 }
04448 /**
04449   * @brief  Input Capture callback in non blocking mode
04450   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04451   *                the configuration information for TIM module.
04452   * @retval None
04453   */
04454 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04455 {
04456   /* Prevent unused argument(s) compilation warning */
04457   UNUSED(htim);
04458
04459   /* NOTE : This function Should not be modified, when the callback is needed,
04460             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04461    */
04462 }
04463
04464 /**
04465   * @brief  PWM Pulse finished callback in non blocking mode
04466   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04467   *                the configuration information for TIM module.
04468   * @retval None
04469   */
04470 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04471 {
04472   /* Prevent unused argument(s) compilation warning */
04473   UNUSED(htim);
04474
04475   /* NOTE : This function Should not be modified, when the callback is needed,
04476             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04477    */
04478 }
04479
04480 /**
04481   * @brief  Hall Trigger detection callback in non blocking mode
04482   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04483   *                the configuration information for TIM module.
04484   * @retval None
04485   */
04486 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04487 {
04488   /* Prevent unused argument(s) compilation warning */
04489   UNUSED(htim);
04490
04491   /* NOTE : This function Should not be modified, when the callback is needed,
04492             the HAL_TIM_TriggerCallback could be implemented in the user file
04493    */
04494 }
04495
04496 /**
04497   * @brief  Timer error callback in non blocking mode
04498   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04499   *                the configuration information for TIM module.
04500   * @retval None
04501   */
04502 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04503 {
04504   /* Prevent unused argument(s) compilation warning */
04505   UNUSED(htim);
04506
04507   /* NOTE : This function Should not be modified, when the callback is needed,
04508             the HAL_TIM_ErrorCallback could be implemented in the user file
04509    */
04510 }
04511
04512 /**
04513   * @}
04514   */
04515
04516 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
04517  *  @brief   Peripheral State functions
04518  *
04519 @verbatim
04520   ==============================================================================
04521                         ##### Peripheral State functions #####
04522   ==============================================================================
04523   [..]
04524     This subsection permits to get in run-time the status of the peripheral
04525     and the data flow.
04526
04527 @endverbatim
04528   * @{
04529   */
04530
04531 /**
04532   * @brief  Return the TIM Base state
04533   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04534   *                the configuration information for TIM module.
04535   * @retval HAL state
04536   */
04537 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04538 {
04539   return htim->State;
04540 }
04541
04542 /**
04543   * @brief  Return the TIM OC state
04544   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04545   *                the configuration information for TIM module.
04546   * @retval HAL state
04547   */
04548 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04549 {
04550   return htim->State;
04551 }
04552
04553 /**
04554   * @brief  Return the TIM PWM state
04555   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04556   *                the configuration information for TIM module.
04557   * @retval HAL state
04558   */
04559 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04560 {
04561   return htim->State;
04562 }
04563
04564 /**
04565   * @brief  Return the TIM Input Capture state
04566   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04567   *                the configuration information for TIM module.
04568   * @retval HAL state
04569   */
04570 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04571 {
04572   return htim->State;
04573 }
04574
04575 /**
04576   * @brief  Return the TIM One Pulse Mode state
04577   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04578   *                the configuration information for TIM module.
04579   * @retval HAL state
04580   */
04581 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04582 {
04583   return htim->State;
04584 }
04585
04586 /**
04587   * @brief  Return the TIM Encoder Mode state
04588   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04589   *                the configuration information for TIM module.
04590   * @retval HAL state
04591   */
04592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04593 {
04594   return htim->State;
04595 }
04596
04597 /**
04598   * @}
04599   */
04600
04601 /**
04602   * @brief  TIM DMA error callback
04603   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04604   *                the configuration information for the specified DMA module.
04605   * @retval None
04606   */
04607 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
04608 {
04609   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04610
04611   htim->State= HAL_TIM_STATE_READY;
04612
04613   HAL_TIM_ErrorCallback(htim);
04614 }
04615
04616 /**
04617   * @brief  TIM DMA Delay Pulse complete callback.
04618   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04619   *                the configuration information for the specified DMA module.
04620   * @retval None
04621   */
04622 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04623 {
04624   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04625
04626   htim->State= HAL_TIM_STATE_READY;
04627
04628   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04629   {
04630     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04631   }
04632   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04633   {
04634     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04635   }
04636   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04637   {
04638     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04639   }
04640   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04641   {
04642     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04643   }
04644
04645   HAL_TIM_PWM_PulseFinishedCallback(htim);
04646
04647   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04648 }
04649 /**
04650   * @brief  TIM DMA Capture complete callback.
04651   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04652   *                the configuration information for the specified DMA module.
04653   * @retval None
04654   */
04655 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04656 {
04657   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04658
04659    htim->State= HAL_TIM_STATE_READY;
04660
04661   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04662   {
04663     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04664   }
04665   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04666   {
04667     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04668   }
04669   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04670   {
04671     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04672   }
04673   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04674   {
04675     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04676   }
04677
04678   HAL_TIM_IC_CaptureCallback(htim);
04679
04680   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04681
04682 }
04683
04684 /**
04685   * @brief  TIM DMA Period Elapse complete callback.
04686   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04687   *                the configuration information for the specified DMA module.
04688   * @retval None
04689   */
04690 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04691 {
04692   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04693
04694   htim->State= HAL_TIM_STATE_READY;
04695
04696   HAL_TIM_PeriodElapsedCallback(htim);
04697 }
04698
04699 /**
04700   * @brief  TIM DMA Trigger callback.
04701   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04702   *                the configuration information for the specified DMA module.
04703   * @retval None
04704   */
04705 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04706 {
04707   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04708
04709   htim->State= HAL_TIM_STATE_READY;
04710
04711   HAL_TIM_TriggerCallback(htim);
04712 }
04713
04714 /**
04715   * @brief  Time Base configuration
04716   * @param  TIMx: TIM peripheral
04717   * @param  Structure: pointer on TIM Time Base required parameters
04718   * @retval None
04719   */
04720 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04721 {
04722   uint32_t tmpcr1 = 0;
04723   tmpcr1 = TIMx->CR1;
04724
04725   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04726   if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
04727   {
04728     /* Select the Counter Mode */
04729     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04730     tmpcr1 |= Structure->CounterMode;
04731   }
04732
04733   if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
04734   {
04735     /* Set the clock division */
04736     tmpcr1 &= ~TIM_CR1_CKD;
04737     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04738   }
04739
04740   TIMx->CR1 = tmpcr1;
04741
04742   /* Set the Auto-reload value */
04743   TIMx->ARR = (uint32_t)Structure->Period ;
04744
04745   /* Set the Prescaler value */
04746   TIMx->PSC = (uint32_t)Structure->Prescaler;
04747
04748   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04749   {
04750     /* Set the Repetition Counter value */
04751     TIMx->RCR = Structure->RepetitionCounter;
04752   }
04753
04754   /* Generate an update event to reload the Prescaler
04755      and the repetition counter(only for TIM1 and TIM8) value immediately */
04756   TIMx->EGR = TIM_EGR_UG;
04757 }
04758
04759 /**
04760   * @brief  Time Output Compare 1 configuration
04761   * @param  TIMx to select the TIM peripheral
04762   * @param  OC_Config: The output configuration structure
04763   * @retval None
04764   */
04765 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04766 {
04767   uint32_t tmpccmrx = 0;
04768   uint32_t tmpccer = 0;
04769   uint32_t tmpcr2 = 0;
04770
04771   /* Disable the Channel 1: Reset the CC1E Bit */
04772   TIMx->CCER &= ~TIM_CCER_CC1E;
04773
04774   /* Get the TIMx CCER register value */
04775   tmpccer = TIMx->CCER;
04776   /* Get the TIMx CR2 register value */
04777   tmpcr2 = TIMx->CR2;
04778
04779   /* Get the TIMx CCMR1 register value */
04780   tmpccmrx = TIMx->CCMR1;
04781
04782   /* Reset the Output Compare Mode Bits */
04783   tmpccmrx &= ~TIM_CCMR1_OC1M;
04784   tmpccmrx &= ~TIM_CCMR1_CC1S;
04785   /* Select the Output Compare Mode */
04786   tmpccmrx |= OC_Config->OCMode;
04787
04788   /* Reset the Output Polarity level */
04789   tmpccer &= ~TIM_CCER_CC1P;
04790   /* Set the Output Compare Polarity */
04791   tmpccer |= OC_Config->OCPolarity;
04792
04793
04794   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04795   {
04796     /* Reset the Output N Polarity level */
04797     tmpccer &= ~TIM_CCER_CC1NP;
04798     /* Set the Output N Polarity */
04799     tmpccer |= OC_Config->OCNPolarity;
04800     /* Reset the Output N State */
04801     tmpccer &= ~TIM_CCER_CC1NE;
04802
04803     /* Reset the Output Compare and Output Compare N IDLE State */
04804     tmpcr2 &= ~TIM_CR2_OIS1;
04805     tmpcr2 &= ~TIM_CR2_OIS1N;
04806     /* Set the Output Idle state */
04807     tmpcr2 |= OC_Config->OCIdleState;
04808     /* Set the Output N Idle state */
04809     tmpcr2 |= OC_Config->OCNIdleState;
04810   }
04811   /* Write to TIMx CR2 */
04812   TIMx->CR2 = tmpcr2;
04813
04814   /* Write to TIMx CCMR1 */
04815   TIMx->CCMR1 = tmpccmrx;
04816
04817   /* Set the Capture Compare Register value */
04818   TIMx->CCR1 = OC_Config->Pulse;
04819
04820   /* Write to TIMx CCER */
04821   TIMx->CCER = tmpccer;
04822 }
04823
04824 /**
04825   * @brief  Time Output Compare 2 configuration
04826   * @param  TIMx to select the TIM peripheral
04827   * @param  OC_Config: The output configuration structure
04828   * @retval None
04829   */
04830 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04831 {
04832   uint32_t tmpccmrx = 0;
04833   uint32_t tmpccer = 0;
04834   uint32_t tmpcr2 = 0;
04835
04836   /* Disable the Channel 2: Reset the CC2E Bit */
04837   TIMx->CCER &= ~TIM_CCER_CC2E;
04838
04839   /* Get the TIMx CCER register value */
04840   tmpccer = TIMx->CCER;
04841   /* Get the TIMx CR2 register value */
04842   tmpcr2 = TIMx->CR2;
04843
04844   /* Get the TIMx CCMR1 register value */
04845   tmpccmrx = TIMx->CCMR1;
04846
04847   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04848   tmpccmrx &= ~TIM_CCMR1_OC2M;
04849   tmpccmrx &= ~TIM_CCMR1_CC2S;
04850
04851   /* Select the Output Compare Mode */
04852   tmpccmrx |= (OC_Config->OCMode << 8);
04853
04854   /* Reset the Output Polarity level */
04855   tmpccer &= ~TIM_CCER_CC2P;
04856   /* Set the Output Compare Polarity */
04857   tmpccer |= (OC_Config->OCPolarity << 4);
04858
04859   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04860   {
04861     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04862
04863     /* Reset the Output N Polarity level */
04864     tmpccer &= ~TIM_CCER_CC2NP;
04865     /* Set the Output N Polarity */
04866     tmpccer |= (OC_Config->OCNPolarity << 4);
04867     /* Reset the Output N State */
04868     tmpccer &= ~TIM_CCER_CC2NE;
04869
04870     /* Reset the Output Compare and Output Compare N IDLE State */
04871     tmpcr2 &= ~TIM_CR2_OIS2;
04872     tmpcr2 &= ~TIM_CR2_OIS2N;
04873     /* Set the Output Idle state */
04874     tmpcr2 |= (OC_Config->OCIdleState << 2);
04875     /* Set the Output N Idle state */
04876     tmpcr2 |= (OC_Config->OCNIdleState << 2);
04877   }
04878   /* Write to TIMx CR2 */
04879   TIMx->CR2 = tmpcr2;
04880
04881   /* Write to TIMx CCMR1 */
04882   TIMx->CCMR1 = tmpccmrx;
04883
04884   /* Set the Capture Compare Register value */
04885   TIMx->CCR2 = OC_Config->Pulse;
04886
04887   /* Write to TIMx CCER */
04888   TIMx->CCER = tmpccer;
04889 }
04890
04891 /**
04892   * @brief  Time Output Compare 3 configuration
04893   * @param  TIMx to select the TIM peripheral
04894   * @param  OC_Config: The output configuration structure
04895   * @retval None
04896   */
04897 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04898 {
04899   uint32_t tmpccmrx = 0;
04900   uint32_t tmpccer = 0;
04901   uint32_t tmpcr2 = 0;
04902
04903   /* Disable the Channel 3: Reset the CC2E Bit */
04904   TIMx->CCER &= ~TIM_CCER_CC3E;
04905
04906   /* Get the TIMx CCER register value */
04907   tmpccer = TIMx->CCER;
04908   /* Get the TIMx CR2 register value */
04909   tmpcr2 = TIMx->CR2;
04910
04911   /* Get the TIMx CCMR2 register value */
04912   tmpccmrx = TIMx->CCMR2;
04913
04914   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04915   tmpccmrx &= ~TIM_CCMR2_OC3M;
04916   tmpccmrx &= ~TIM_CCMR2_CC3S;
04917   /* Select the Output Compare Mode */
04918   tmpccmrx |= OC_Config->OCMode;
04919
04920   /* Reset the Output Polarity level */
04921   tmpccer &= ~TIM_CCER_CC3P;
04922   /* Set the Output Compare Polarity */
04923   tmpccer |= (OC_Config->OCPolarity << 8);
04924
04925   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04926   {
04927     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04928
04929     /* Reset the Output N Polarity level */
04930     tmpccer &= ~TIM_CCER_CC3NP;
04931     /* Set the Output N Polarity */
04932     tmpccer |= (OC_Config->OCNPolarity << 8);
04933     /* Reset the Output N State */
04934     tmpccer &= ~TIM_CCER_CC3NE;
04935
04936     /* Reset the Output Compare and Output Compare N IDLE State */
04937     tmpcr2 &= ~TIM_CR2_OIS3;
04938     tmpcr2 &= ~TIM_CR2_OIS3N;
04939     /* Set the Output Idle state */
04940     tmpcr2 |= (OC_Config->OCIdleState << 4);
04941     /* Set the Output N Idle state */
04942     tmpcr2 |= (OC_Config->OCNIdleState << 4);
04943   }
04944   /* Write to TIMx CR2 */
04945   TIMx->CR2 = tmpcr2;
04946
04947   /* Write to TIMx CCMR2 */
04948   TIMx->CCMR2 = tmpccmrx;
04949
04950   /* Set the Capture Compare Register value */
04951   TIMx->CCR3 = OC_Config->Pulse;
04952
04953   /* Write to TIMx CCER */
04954   TIMx->CCER = tmpccer;
04955 }
04956
04957 /**
04958   * @brief  Time Output Compare 4 configuration
04959   * @param  TIMx to select the TIM peripheral
04960   * @param  OC_Config: The output configuration structure
04961   * @retval None
04962   */
04963 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04964 {
04965   uint32_t tmpccmrx = 0;
04966   uint32_t tmpccer = 0;
04967   uint32_t tmpcr2 = 0;
04968
04969   /* Disable the Channel 4: Reset the CC4E Bit */
04970   TIMx->CCER &= ~TIM_CCER_CC4E;
04971
04972   /* Get the TIMx CCER register value */
04973   tmpccer = TIMx->CCER;
04974   /* Get the TIMx CR2 register value */
04975   tmpcr2 = TIMx->CR2;
04976
04977   /* Get the TIMx CCMR2 register value */
04978   tmpccmrx = TIMx->CCMR2;
04979
04980   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04981   tmpccmrx &= ~TIM_CCMR2_OC4M;
04982   tmpccmrx &= ~TIM_CCMR2_CC4S;
04983
04984   /* Select the Output Compare Mode */
04985   tmpccmrx |= (OC_Config->OCMode << 8);
04986
04987   /* Reset the Output Polarity level */
04988   tmpccer &= ~TIM_CCER_CC4P;
04989   /* Set the Output Compare Polarity */
04990   tmpccer |= (OC_Config->OCPolarity << 12);
04991
04992   /*if((TIMx == TIM1) || (TIMx == TIM8))*/
04993   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04994   {
04995     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04996     /* Reset the Output Compare IDLE State */
04997     tmpcr2 &= ~TIM_CR2_OIS4;
04998     /* Set the Output Idle state */
04999     tmpcr2 |= (OC_Config->OCIdleState << 6);
05000   }
05001   /* Write to TIMx CR2 */
05002   TIMx->CR2 = tmpcr2;
05003
05004   /* Write to TIMx CCMR2 */
05005   TIMx->CCMR2 = tmpccmrx;
05006
05007   /* Set the Capture Compare Register value */
05008   TIMx->CCR4 = OC_Config->Pulse;
05009
05010   /* Write to TIMx CCER */
05011   TIMx->CCER = tmpccer;
05012 }
05013
05014 /**
05015   * @brief  Time Output Compare 4 configuration
05016   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
05017   *                the configuration information for TIM module.
05018   * @param  sSlaveConfig: The slave configuration structure
05019   * @retval None
05020   */
05021 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
05022                               TIM_SlaveConfigTypeDef * sSlaveConfig)
05023 {
05024   uint32_t tmpsmcr = 0;
05025   uint32_t tmpccmr1 = 0;
05026   uint32_t tmpccer = 0;
05027
05028  /* Get the TIMx SMCR register value */
05029   tmpsmcr = htim->Instance->SMCR;
05030
05031   /* Reset the Trigger Selection Bits */
05032   tmpsmcr &= ~TIM_SMCR_TS;
05033   /* Set the Input Trigger source */
05034   tmpsmcr |= sSlaveConfig->InputTrigger;
05035
05036   /* Reset the slave mode Bits */
05037   tmpsmcr &= ~TIM_SMCR_SMS;
05038   /* Set the slave mode */
05039   tmpsmcr |= sSlaveConfig->SlaveMode;
05040
05041   /* Write to TIMx SMCR */
05042   htim->Instance->SMCR = tmpsmcr;
05043
05044   /* Configure the trigger prescaler, filter, and polarity */
05045   switch (sSlaveConfig->InputTrigger)
05046   {
05047   case TIM_TS_ETRF:
05048     {
05049       /* Check the parameters */
05050       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
05051       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
05052       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05053       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05054       /* Configure the ETR Trigger source */
05055       TIM_ETR_SetConfig(htim->Instance,
05056                         sSlaveConfig->TriggerPrescaler,
05057                         sSlaveConfig->TriggerPolarity,
05058                         sSlaveConfig->TriggerFilter);
05059     }
05060     break;
05061
05062   case TIM_TS_TI1F_ED:
05063     {
05064       /* Check the parameters */
05065       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05066       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05067       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05068
05069       /* Disable the Channel 1: Reset the CC1E Bit */
05070       tmpccer = htim->Instance->CCER;
05071       htim->Instance->CCER &= ~TIM_CCER_CC1E;
05072       tmpccmr1 = htim->Instance->CCMR1;
05073
05074       /* Set the filter */
05075       tmpccmr1 &= ~TIM_CCMR1_IC1F;
05076       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
05077
05078       /* Write to TIMx CCMR1 and CCER registers */
05079       htim->Instance->CCMR1 = tmpccmr1;
05080       htim->Instance->CCER = tmpccer;
05081
05082     }
05083     break;
05084
05085   case TIM_TS_TI1FP1:
05086     {
05087       /* Check the parameters */
05088       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05089       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05090       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05091
05092       /* Configure TI1 Filter and Polarity */
05093       TIM_TI1_ConfigInputStage(htim->Instance,
05094                                sSlaveConfig->TriggerPolarity,
05095                                sSlaveConfig->TriggerFilter);
05096     }
05097     break;
05098
05099   case TIM_TS_TI2FP2:
05100     {
05101       /* Check the parameters */
05102       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05103       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05104       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05105
05106       /* Configure TI2 Filter and Polarity */
05107       TIM_TI2_ConfigInputStage(htim->Instance,
05108                                 sSlaveConfig->TriggerPolarity,
05109                                 sSlaveConfig->TriggerFilter);
05110     }
05111     break;
05112
05113   case TIM_TS_ITR0:
05114     {
05115       /* Check the parameter */
05116       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05117     }
05118     break;
05119
05120   case TIM_TS_ITR1:
05121     {
05122       /* Check the parameter */
05123       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05124     }
05125     break;
05126
05127   case TIM_TS_ITR2:
05128     {
05129       /* Check the parameter */
05130       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05131     }
05132     break;
05133
05134   case TIM_TS_ITR3:
05135     {
05136       /* Check the parameter */
05137       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05138     }
05139     break;
05140
05141   default:
05142     break;
05143   }
05144 }
05145
05146 /**
05147   * @brief  Configure the TI1 as Input.
05148   * @param  TIMx to select the TIM peripheral.
05149   * @param  TIM_ICPolarity : The Input Polarity.
05150   *          This parameter can be one of the following values:
05151   *            @arg TIM_ICPolarity_Rising
05152   *            @arg TIM_ICPolarity_Falling
05153   *            @arg TIM_ICPolarity_BothEdge
05154   * @param  TIM_ICSelection: specifies the input to be used.
05155   *          This parameter can be one of the following values:
05156   *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
05157   *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
05158   *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
05159   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05160   *          This parameter must be a value between 0x00 and 0x0F.
05161   * @retval None
05162   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
05163   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
05164   *        protected against un-initialized filter and polarity values.
05165   */
05166 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05167                        uint32_t TIM_ICFilter)
05168 {
05169   uint32_t tmpccmr1 = 0;
05170   uint32_t tmpccer = 0;
05171
05172   /* Disable the Channel 1: Reset the CC1E Bit */
05173   TIMx->CCER &= ~TIM_CCER_CC1E;
05174   tmpccmr1 = TIMx->CCMR1;
05175   tmpccer = TIMx->CCER;
05176
05177   /* Select the Input */
05178   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
05179   {
05180     tmpccmr1 &= ~TIM_CCMR1_CC1S;
05181     tmpccmr1 |= TIM_ICSelection;
05182   }
05183   else
05184   {
05185     tmpccmr1 |= TIM_CCMR1_CC1S_0;
05186   }
05187
05188   /* Set the filter */
05189   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05190   tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
05191
05192   /* Select the Polarity and set the CC1E Bit */
05193   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05194   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
05195
05196   /* Write to TIMx CCMR1 and CCER registers */
05197   TIMx->CCMR1 = tmpccmr1;
05198   TIMx->CCER = tmpccer;
05199 }
05200
05201 /**
05202   * @brief  Configure the Polarity and Filter for TI1.
05203   * @param  TIMx to select the TIM peripheral.
05204   * @param  TIM_ICPolarity : The Input Polarity.
05205   *          This parameter can be one of the following values:
05206   *            @arg TIM_ICPolarity_Rising
05207   *            @arg TIM_ICPolarity_Falling
05208   *            @arg TIM_ICPolarity_BothEdge
05209   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05210   *          This parameter must be a value between 0x00 and 0x0F.
05211   * @retval None
05212   */
05213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05214 {
05215   uint32_t tmpccmr1 = 0;
05216   uint32_t tmpccer = 0;
05217
05218   /* Disable the Channel 1: Reset the CC1E Bit */
05219   tmpccer = TIMx->CCER;
05220   TIMx->CCER &= ~TIM_CCER_CC1E;
05221   tmpccmr1 = TIMx->CCMR1;
05222
05223   /* Set the filter */
05224   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05225   tmpccmr1 |= (TIM_ICFilter << 4);
05226
05227   /* Select the Polarity and set the CC1E Bit */
05228   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05229   tmpccer |= TIM_ICPolarity;
05230
05231   /* Write to TIMx CCMR1 and CCER registers */
05232   TIMx->CCMR1 = tmpccmr1;
05233   TIMx->CCER = tmpccer;
05234 }
05235
05236 /**
05237   * @brief  Configure the TI2 as Input.
05238   * @param  TIMx to select the TIM peripheral
05239   * @param  TIM_ICPolarity : The Input Polarity.
05240   *          This parameter can be one of the following values:
05241   *            @arg TIM_ICPolarity_Rising
05242   *            @arg TIM_ICPolarity_Falling
05243   *            @arg TIM_ICPolarity_BothEdge
05244   * @param  TIM_ICSelection: specifies the input to be used.
05245   *          This parameter can be one of the following values:
05246   *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
05247   *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
05248   *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
05249   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05250   *          This parameter must be a value between 0x00 and 0x0F.
05251   * @retval None
05252   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
05253   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
05254   *        protected against un-initialized filter and polarity values.
05255   */
05256 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05257                        uint32_t TIM_ICFilter)
05258 {
05259   uint32_t tmpccmr1 = 0;
05260   uint32_t tmpccer = 0;
05261
05262   /* Disable the Channel 2: Reset the CC2E Bit */
05263   TIMx->CCER &= ~TIM_CCER_CC2E;
05264   tmpccmr1 = TIMx->CCMR1;
05265   tmpccer = TIMx->CCER;
05266
05267   /* Select the Input */
05268   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05269   tmpccmr1 |= (TIM_ICSelection << 8);
05270
05271   /* Set the filter */
05272   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05273   tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
05274
05275   /* Select the Polarity and set the CC2E Bit */
05276   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05277   tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05278
05279   /* Write to TIMx CCMR1 and CCER registers */
05280   TIMx->CCMR1 = tmpccmr1 ;
05281   TIMx->CCER = tmpccer;
05282 }
05283
05284 /**
05285   * @brief  Configure the Polarity and Filter for TI2.
05286   * @param  TIMx to select the TIM peripheral.
05287   * @param  TIM_ICPolarity : The Input Polarity.
05288   *          This parameter can be one of the following values:
05289   *            @arg TIM_ICPolarity_Rising
05290   *            @arg TIM_ICPolarity_Falling
05291   *            @arg TIM_ICPolarity_BothEdge
05292   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05293   *          This parameter must be a value between 0x00 and 0x0F.
05294   * @retval None
05295   */
05296 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05297 {
05298 uint32_t tmpccmr1 = 0;
05299   uint32_t tmpccer = 0;
05300
05301   /* Disable the Channel 2: Reset the CC2E Bit */
05302   TIMx->CCER &= ~TIM_CCER_CC2E;
05303   tmpccmr1 = TIMx->CCMR1;
05304   tmpccer = TIMx->CCER;
05305
05306   /* Set the filter */
05307   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05308   tmpccmr1 |= (TIM_ICFilter << 12);
05309
05310   /* Select the Polarity and set the CC2E Bit */
05311   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05312   tmpccer |= (TIM_ICPolarity << 4);
05313
05314   /* Write to TIMx CCMR1 and CCER registers */
05315   TIMx->CCMR1 = tmpccmr1 ;
05316   TIMx->CCER = tmpccer;
05317 }
05318
05319 /**
05320   * @brief  Configure the TI3 as Input.
05321   * @param  TIMx to select the TIM peripheral
05322   * @param  TIM_ICPolarity : The Input Polarity.
05323   *          This parameter can be one of the following values:
05324   *            @arg TIM_ICPolarity_Rising
05325   *            @arg TIM_ICPolarity_Falling
05326   *            @arg TIM_ICPolarity_BothEdge
05327   * @param  TIM_ICSelection: specifies the input to be used.
05328   *          This parameter can be one of the following values:
05329   *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
05330   *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
05331   *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
05332   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05333   *          This parameter must be a value between 0x00 and 0x0F.
05334   * @retval None
05335   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
05336   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05337   *        protected against un-initialized filter and polarity values.
05338   */
05339 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05340                        uint32_t TIM_ICFilter)
05341 {
05342   uint32_t tmpccmr2 = 0;
05343   uint32_t tmpccer = 0;
05344
05345   /* Disable the Channel 3: Reset the CC3E Bit */
05346   TIMx->CCER &= ~TIM_CCER_CC3E;
05347   tmpccmr2 = TIMx->CCMR2;
05348   tmpccer = TIMx->CCER;
05349
05350   /* Select the Input */
05351   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05352   tmpccmr2 |= TIM_ICSelection;
05353
05354   /* Set the filter */
05355   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05356   tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
05357
05358   /* Select the Polarity and set the CC3E Bit */
05359   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05360   tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05361
05362   /* Write to TIMx CCMR2 and CCER registers */
05363   TIMx->CCMR2 = tmpccmr2;
05364   TIMx->CCER = tmpccer;
05365 }
05366
05367 /**
05368   * @brief  Configure the TI4 as Input.
05369   * @param  TIMx to select the TIM peripheral
05370   * @param  TIM_ICPolarity : The Input Polarity.
05371   *          This parameter can be one of the following values:
05372   *            @arg TIM_ICPolarity_Rising
05373   *            @arg TIM_ICPolarity_Falling
05374   *            @arg TIM_ICPolarity_BothEdge
05375   * @param  TIM_ICSelection: specifies the input to be used.
05376   *          This parameter can be one of the following values:
05377   *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
05378   *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
05379   *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
05380   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05381   *          This parameter must be a value between 0x00 and 0x0F.
05382   * @retval None
05383   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
05384   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05385   *        protected against un-initialized filter and polarity values.
05386   */
05387 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05388                        uint32_t TIM_ICFilter)
05389 {
05390   uint32_t tmpccmr2 = 0;
05391   uint32_t tmpccer = 0;
05392
05393   /* Disable the Channel 4: Reset the CC4E Bit */
05394   TIMx->CCER &= ~TIM_CCER_CC4E;
05395   tmpccmr2 = TIMx->CCMR2;
05396   tmpccer = TIMx->CCER;
05397
05398   /* Select the Input */
05399   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05400   tmpccmr2 |= (TIM_ICSelection << 8);
05401
05402   /* Set the filter */
05403   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05404   tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
05405
05406   /* Select the Polarity and set the CC4E Bit */
05407   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
05408   tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
05409
05410   /* Write to TIMx CCMR2 and CCER registers */
05411   TIMx->CCMR2 = tmpccmr2;
05412   TIMx->CCER = tmpccer ;
05413 }
05414
05415 /**
05416   * @brief  Selects the Input Trigger source
05417   * @param  TIMx to select the TIM peripheral
05418   * @param  TIM_ITRx: The Input Trigger source.
05419   *          This parameter can be one of the following values:
05420   *            @arg TIM_TS_ITR0: Internal Trigger 0
05421   *            @arg TIM_TS_ITR1: Internal Trigger 1
05422   *            @arg TIM_TS_ITR2: Internal Trigger 2
05423   *            @arg TIM_TS_ITR3: Internal Trigger 3
05424   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
05425   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
05426   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
05427   *            @arg TIM_TS_ETRF: External Trigger input
05428   * @retval None
05429   */
05430 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
05431 {
05432   uint32_t tmpsmcr = 0;
05433
05434    /* Get the TIMx SMCR register value */
05435    tmpsmcr = TIMx->SMCR;
05436    /* Reset the TS Bits */
05437    tmpsmcr &= ~TIM_SMCR_TS;
05438    /* Set the Input Trigger source and the slave mode*/
05439    tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
05440    /* Write to TIMx SMCR */
05441    TIMx->SMCR = tmpsmcr;
05442 }
05443
05444 /**
05445   * @brief  Configures the TIMx External Trigger (ETR).
05446   * @param  TIMx to select the TIM peripheral
05447   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
05448   *          This parameter can be one of the following values:
05449   *            @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
05450   *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
05451   *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
05452   *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
05453   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
05454   *          This parameter can be one of the following values:
05455   *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
05456   *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
05457   * @param  ExtTRGFilter: External Trigger Filter.
05458   *          This parameter must be a value between 0x00 and 0x0F
05459   * @retval None
05460   */
05461 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05462                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05463 {
05464   uint32_t tmpsmcr = 0;
05465
05466   tmpsmcr = TIMx->SMCR;
05467
05468   /* Reset the ETR Bits */
05469   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05470
05471   /* Set the Prescaler, the Filter value and the Polarity */
05472   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
05473
05474   /* Write to TIMx SMCR */
05475   TIMx->SMCR = tmpsmcr;
05476 }
05477
05478 /**
05479   * @brief  Enables or disables the TIM Capture Compare Channel x.
05480   * @param  TIMx to select the TIM peripheral
05481   * @param  Channel: specifies the TIM Channel
05482   *          This parameter can be one of the following values:
05483   *            @arg TIM_Channel_1: TIM Channel 1
05484   *            @arg TIM_Channel_2: TIM Channel 2
05485   *            @arg TIM_Channel_3: TIM Channel 3
05486   *            @arg TIM_Channel_4: TIM Channel 4
05487   * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
05488   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
05489   * @retval None
05490   */
05491 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
05492 {
05493   uint32_t tmp = 0;
05494
05495   /* Check the parameters */
05496   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
05497   assert_param(IS_TIM_CHANNELS(Channel));
05498
05499   tmp = TIM_CCER_CC1E << Channel;
05500
05501   /* Reset the CCxE Bit */
05502   TIMx->CCER &= ~tmp;
05503
05504   /* Set or reset the CCxE Bit */
05505   TIMx->CCER |= (uint32_t)(ChannelState << Channel);
05506 }
05507
05508
05509 /**
05510   * @}
05511   */
05512
05513 #endif /* HAL_TIM_MODULE_ENABLED */
05514 /**
05515   * @}
05516   */
05517
05518 /**
05519   * @}
05520   */
05521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim.h Source File

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stm32f7xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of TIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_TIM_H
00040 #define __STM32F7xx_HAL_TIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIM_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Time base Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00068                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00069
00070   uint32_t CounterMode;       /*!< Specifies the counter mode.
00071                                    This parameter can be a value of @ref TIM_Counter_Mode */
00072
00073   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00074                                    Auto-Reload Register at the next update event.
00075                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00076
00077   uint32_t ClockDivision;     /*!< Specifies the clock division.
00078                                    This parameter can be a value of @ref TIM_ClockDivision */
00079
00080   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00081                                     reaches zero, an update event is generated and counting restarts
00082                                     from the RCR value (N).
00083                                     This means in PWM mode that (N+1) corresponds to:
00084                                         - the number of PWM periods in edge-aligned mode
00085                                         - the number of half PWM period in center-aligned mode
00086                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00087                                      @note This parameter is valid only for TIM1 and TIM8. */
00088 } TIM_Base_InitTypeDef;
00089
00090 /**
00091   * @brief  TIM Output Compare Configuration Structure definition
00092   */
00093
00094 typedef struct
00095 {
00096   uint32_t OCMode;        /*!< Specifies the TIM mode.
00097                                This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
00098
00099   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00100                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00101
00102   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00103                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00104
00105   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00106                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00107                                @note This parameter is valid only for TIM1 and TIM8. */
00108
00109   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00110                                This parameter can be a value of @ref TIM_Output_Fast_State
00111                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00112
00113
00114   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00115                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00116                                @note This parameter is valid only for TIM1 and TIM8. */
00117
00118   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00119                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00120                                @note This parameter is valid only for TIM1 and TIM8. */
00121 } TIM_OC_InitTypeDef;
00122
00123 /**
00124   * @brief  TIM One Pulse Mode Configuration Structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t OCMode;        /*!< Specifies the TIM mode.
00129                                This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
00130
00131   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00132                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00133
00134   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00135                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00136
00137   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00138                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00139                                @note This parameter is valid only for TIM1 and TIM8. */
00140
00141   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00142                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00143                                @note This parameter is valid only for TIM1 and TIM8. */
00144
00145   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00146                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00147                                @note This parameter is valid only for TIM1 and TIM8. */
00148
00149   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00150                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00151
00152   uint32_t ICSelection;   /*!< Specifies the input.
00153                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00154
00155   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00156                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00157 } TIM_OnePulse_InitTypeDef;
00158
00159
00160 /**
00161   * @brief  TIM Input Capture Configuration Structure definition
00162   */
00163
00164 typedef struct
00165 {
00166   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00167                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00168
00169   uint32_t ICSelection;  /*!< Specifies the input.
00170                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00171
00172   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00173                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00174
00175   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00176                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00177 } TIM_IC_InitTypeDef;
00178
00179 /**
00180   * @brief  TIM Encoder Configuration Structure definition
00181   */
00182
00183 typedef struct
00184 {
00185   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00186                                This parameter can be a value of @ref TIM_Encoder_Mode */
00187
00188   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00189                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00190
00191   uint32_t IC1Selection;  /*!< Specifies the input.
00192                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00193
00194   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00195                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00196
00197   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00198                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00199
00200   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00201                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00202
00203   uint32_t IC2Selection;  /*!< Specifies the input.
00204                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00205
00206   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00207                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00208
00209   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00210                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00211 } TIM_Encoder_InitTypeDef;
00212
00213 /**
00214   * @brief  Clock Configuration Handle Structure definition
00215   */
00216 typedef struct
00217 {
00218   uint32_t ClockSource;     /*!< TIM clock sources.
00219                                  This parameter can be a value of @ref TIM_Clock_Source */
00220   uint32_t ClockPolarity;   /*!< TIM clock polarity.
00221                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00222   uint32_t ClockPrescaler;  /*!< TIM clock prescaler.
00223                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00224   uint32_t ClockFilter;    /*!< TIM clock filter.
00225                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00226 }TIM_ClockConfigTypeDef;
00227
00228 /**
00229   * @brief  Clear Input Configuration Handle Structure definition
00230   */
00231 typedef struct
00232 {
00233   uint32_t ClearInputState;      /*!< TIM clear Input state.
00234                                       This parameter can be ENABLE or DISABLE */
00235   uint32_t ClearInputSource;     /*!< TIM clear Input sources.
00236                                       This parameter can be a value of @ref TIMEx_ClearInput_Source */
00237   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity.
00238                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00239   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler.
00240                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00241   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter.
00242                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00243 }TIM_ClearInputConfigTypeDef;
00244
00245 /**
00246   * @brief  TIM Slave configuration Structure definition
00247   */
00248 typedef struct {
00249   uint32_t  SlaveMode;         /*!< Slave mode selection
00250                                   This parameter can be a value of @ref TIMEx_Slave_Mode */
00251   uint32_t  InputTrigger;      /*!< Input Trigger source
00252                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00253   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00254                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00255   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00256                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00257   uint32_t  TriggerFilter;     /*!< Input trigger filter
00258                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00259
00260 }TIM_SlaveConfigTypeDef;
00261
00262 /**
00263   * @brief  HAL State structures definition
00264   */
00265 typedef enum
00266 {
00267   HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
00268   HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
00269   HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
00270   HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
00271   HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
00272 }HAL_TIM_StateTypeDef;
00273
00274 /**
00275   * @brief  HAL Active channel structures definition
00276   */
00277 typedef enum
00278 {
00279   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
00280   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
00281   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
00282   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
00283   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00     /*!< All active channels cleared */
00284 }HAL_TIM_ActiveChannel;
00285
00286 /**
00287   * @brief  TIM Time Base Handle Structure definition
00288   */
00289 typedef struct
00290 {
00291   TIM_TypeDef                 *Instance;     /*!< Register base address             */
00292   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
00293   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
00294   DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
00295                                              This array is accessed by a @ref DMA_Handle_index */
00296   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
00297   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00298 }TIM_HandleTypeDef;
00299 /**
00300   * @}
00301   */
00302
00303 /* Exported constants --------------------------------------------------------*/
00304 /** @defgroup TIM_Exported_Constants  TIM Exported Constants
00305   * @{
00306   */
00307
00308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
00309   * @{
00310   */
00311 #define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
00312 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00313 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup TIM_ETR_Polarity  TIM ETR Polarity
00319   * @{
00320   */
00321 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00322 #define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler
00328   * @{
00329   */
00330 #define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
00331 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
00332 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
00333 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup TIM_Counter_Mode  TIM Counter Mode
00339   * @{
00340   */
00341 #define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
00342 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
00343 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
00344 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
00345 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup TIM_ClockDivision TIM Clock Division
00351   * @{
00352   */
00353 #define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
00354 #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
00355 #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00361   * @{
00362   */
00363 #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
00364 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
00365
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup TIM_Output_Fast_State  TIM Output Fast State
00371   * @{
00372   */
00373 #define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
00374 #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00380   * @{
00381   */
00382 #define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
00383 #define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00389   * @{
00390   */
00391 #define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
00392 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00398   * @{
00399   */
00400 #define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
00401 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State
00407   * @{
00408   */
00409 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00410 #define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State
00416   * @{
00417   */
00418 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00419 #define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity
00425   * @{
00426   */
00427 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00428 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00429 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection
00435   * @{
00436   */
00437 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00438                                                                      connected to IC1, IC2, IC3 or IC4, respectively */
00439 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00440                                                                      connected to IC2, IC1, IC4 or IC3, respectively */
00441 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00442
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler
00448   * @{
00449   */
00450 #define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)       /*!< Capture performed each time an edge is detected on the capture input */
00451 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00452 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00453 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00459   * @{
00460   */
00461 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00462 #define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00468   * @{
00469   */
00470 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00471 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00472 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00473
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup TIM_Interrupt_definition  TIM Interrupt definition
00479   * @{
00480   */
00481 #define TIM_IT_UPDATE           (TIM_DIER_UIE)
00482 #define TIM_IT_CC1              (TIM_DIER_CC1IE)
00483 #define TIM_IT_CC2              (TIM_DIER_CC2IE)
00484 #define TIM_IT_CC3              (TIM_DIER_CC3IE)
00485 #define TIM_IT_CC4              (TIM_DIER_CC4IE)
00486 #define TIM_IT_COM              (TIM_DIER_COMIE)
00487 #define TIM_IT_TRIGGER          (TIM_DIER_TIE)
00488 #define TIM_IT_BREAK            (TIM_DIER_BIE)
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00494   * @{
00495   */
00496 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00497 #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
00498 /**
00499   * @}
00500   */
00501
00502 /** @defgroup TIM_DMA_sources  TIM DMA sources
00503   * @{
00504   */
00505 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00506 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00507 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00508 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00509 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00510 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00511 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup TIM_Event_Source  TIM Event Source
00517   * @{
00518   */
00519 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG
00520 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
00521 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
00522 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
00523 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
00524 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
00525 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
00526 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
00527 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G
00528 /**
00529   * @}
00530   */
00531
00532 /** @defgroup TIM_Flag_definition  TIM Flag definition
00533   * @{
00534   */
00535 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00536 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00537 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00538 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00539 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00540 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00541 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00542 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00543 #define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
00544 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00545 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00546 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00547 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup TIM_Clock_Source  TIM Clock Source
00553   * @{
00554   */
00555 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00556 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00557 #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
00558 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00559 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00560 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00561 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00562 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00563 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00564 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup TIM_Clock_Polarity  TIM Clock Polarity
00570   * @{
00571   */
00572 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
00573 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
00574 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
00575 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00576 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler
00582   * @{
00583   */
00584 #define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00585 #define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00586 #define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00587 #define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00588 /**
00589   * @}
00590   */
00591
00592 /** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity
00593   * @{
00594   */
00595 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00596 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */
00597 /**
00598   * @}
00599   */
00600
00601 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00602   * @{
00603   */
00604 #define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00605 #define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00606 #define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00607 #define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00613   * @{
00614   */
00615 #define TIM_OSSR_ENABLE               (TIM_BDTR_OSSR)
00616 #define TIM_OSSR_DISABLE          ((uint32_t)0x0000)
00617 /**
00618   * @}
00619   */
00620
00621 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00622   * @{
00623   */
00624 #define TIM_OSSI_ENABLE             (TIM_BDTR_OSSI)
00625 #define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup TIM_Lock_level  TIM Lock level
00631   * @{
00632   */
00633 #define TIM_LOCKLEVEL_OFF          ((uint32_t)0x0000)
00634 #define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
00635 #define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
00636 #define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
00637 /**
00638   * @}
00639   */
00640 /** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State
00641   * @{
00642   */
00643 #define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
00644 #define TIM_BREAK_DISABLE         ((uint32_t)0x0000)
00645 /**
00646   * @}
00647   */
00648
00649 /** @defgroup TIM_Break_Polarity  TIM Break Polarity
00650   * @{
00651   */
00652 #define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000)
00653 #define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State
00659   * @{
00660   */
00661 #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
00662 #define TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00668   * @{
00669   */
00670 #define TIM_TRGO_RESET            ((uint32_t)0x0000)
00671 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00672 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00673 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00674 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00675 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00676 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00677 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00678 /**
00679   * @}
00680   */
00681
00682 /** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode
00683   * @{
00684   */
00685 #define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
00686 #define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
00687 /**
00688   * @}
00689   */
00690
00691 /** @defgroup TIM_Trigger_Selection  TIM Trigger Selection
00692   * @{
00693   */
00694 #define TIM_TS_ITR0                        ((uint32_t)0x0000)
00695 #define TIM_TS_ITR1                        ((uint32_t)0x0010)
00696 #define TIM_TS_ITR2                        ((uint32_t)0x0020)
00697 #define TIM_TS_ITR3                        ((uint32_t)0x0030)
00698 #define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
00699 #define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
00700 #define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
00701 #define TIM_TS_ETRF                        ((uint32_t)0x0070)
00702 #define TIM_TS_NONE                        ((uint32_t)0xFFFF)
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00708   * @{
00709   */
00710 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
00711 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
00712 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00713 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00714 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00720   * @{
00721   */
00722 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00723 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00724 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00725 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00726 /**
00727   * @}
00728   */
00729
00730
00731 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
00732   * @{
00733   */
00734 #define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
00735 #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
00736 /**
00737   * @}
00738   */
00739
00740 /** @defgroup TIM_DMA_Base_address  TIM DMA Base address
00741   * @{
00742   */
00743 #define TIM_DMABASE_CR1                    (0x00000000)
00744 #define TIM_DMABASE_CR2                    (0x00000001)
00745 #define TIM_DMABASE_SMCR                   (0x00000002)
00746 #define TIM_DMABASE_DIER                   (0x00000003)
00747 #define TIM_DMABASE_SR                     (0x00000004)
00748 #define TIM_DMABASE_EGR                    (0x00000005)
00749 #define TIM_DMABASE_CCMR1                  (0x00000006)
00750 #define TIM_DMABASE_CCMR2                  (0x00000007)
00751 #define TIM_DMABASE_CCER                   (0x00000008)
00752 #define TIM_DMABASE_CNT                    (0x00000009)
00753 #define TIM_DMABASE_PSC                    (0x0000000A)
00754 #define TIM_DMABASE_ARR                    (0x0000000B)
00755 #define TIM_DMABASE_RCR                    (0x0000000C)
00756 #define TIM_DMABASE_CCR1                   (0x0000000D)
00757 #define TIM_DMABASE_CCR2                   (0x0000000E)
00758 #define TIM_DMABASE_CCR3                   (0x0000000F)
00759 #define TIM_DMABASE_CCR4                   (0x00000010)
00760 #define TIM_DMABASE_BDTR                   (0x00000011)
00761 #define TIM_DMABASE_DCR                    (0x00000012)
00762 #define TIM_DMABASE_OR                     (0x00000013)
00763 /**
00764   * @}
00765   */
00766
00767 /** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length
00768   * @{
00769   */
00770 #define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000)
00771 #define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100)
00772 #define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200)
00773 #define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300)
00774 #define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400)
00775 #define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500)
00776 #define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600)
00777 #define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700)
00778 #define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800)
00779 #define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900)
00780 #define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00)
00781 #define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00)
00782 #define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00)
00783 #define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00)
00784 #define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00)
00785 #define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00)
00786 #define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000)
00787 #define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100)
00788 /**
00789   * @}
00790   */
00791
00792 /** @defgroup DMA_Handle_index  DMA Handle index
00793   * @{
00794   */
00795 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
00796 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00797 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00798 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00799 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00800 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
00801 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
00802 /**
00803   * @}
00804   */
00805
00806 /** @defgroup Channel_CC_State  Channel CC State
00807   * @{
00808   */
00809 #define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
00810 #define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
00811 #define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
00812 #define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
00813 /**
00814   * @}
00815   */
00816
00817 /**
00818   * @}
00819   */
00820
00821 /* Exported macro ------------------------------------------------------------*/
00822 /** @defgroup TIM_Exported_Macros TIM Exported Macros
00823   * @{
00824   */
00825 /** @brief Reset TIM handle state
00826   * @param  __HANDLE__: TIM handle
00827   * @retval None
00828   */
00829 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
00830
00831 /**
00832   * @brief  Enable the TIM peripheral.
00833   * @param  __HANDLE__: TIM handle
00834   * @retval None
00835  */
00836 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
00837
00838 /**
00839   * @brief  Enable the TIM update source request.
00840   * @param  __HANDLE__: TIM handle
00841   * @retval None
00842  */
00843 #define __HAL_TIM_URS_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
00844
00845 /**
00846   * @brief  Enable the TIM main Output.
00847   * @param  __HANDLE__: TIM handle
00848   * @retval None
00849   */
00850 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
00851
00852
00853 /* The counter of a timer instance is disabled only if all the CCx and CCxN
00854    channels have been disabled */
00855 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
00856 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
00857
00858 /**
00859   * @brief  Disable the TIM peripheral.
00860   * @param  __HANDLE__: TIM handle
00861   * @retval None
00862   */
00863 #define __HAL_TIM_DISABLE(__HANDLE__) \
00864                         do { \
00865                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
00866                           { \
00867                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
00868                             { \
00869                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
00870                             } \
00871                           } \
00872                         } while(0)
00873
00874 /**
00875   * @brief  Disable the TIM update source request.
00876   * @param  __HANDLE__: TIM handle
00877   * @retval None
00878  */
00879 #define __HAL_TIM_URS_DISABLE(__HANDLE__)            ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
00880
00881
00882 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
00883    channels have been disabled */
00884 /**
00885   * @brief  Disable the TIM main Output.
00886   * @param  __HANDLE__: TIM handle
00887   * @retval None
00888   */
00889 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
00890                         do { \
00891                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
00892                           { \
00893                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
00894                             { \
00895                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
00896                             } \
00897                           } \
00898                         } while(0)
00899
00900 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
00901 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
00902 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
00903 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
00904 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
00905 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00906
00907 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00908 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
00909
00910 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
00911 #define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
00912
00913 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
00914 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
00915  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
00916  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
00917  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
00918
00919 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
00920 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
00921  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
00922  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
00923  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
00924
00925 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
00926 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
00927  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
00928  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
00929  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
00930
00931 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
00932 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
00933  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
00934  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
00935  ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
00936
00937 /**
00938   * @brief  Sets the TIM Counter Register value on runtime.
00939   * @param  __HANDLE__: TIM handle.
00940   * @param  __COUNTER__: specifies the Counter register new value.
00941   * @retval None
00942   */
00943 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
00944
00945 /**
00946   * @brief  Gets the TIM Counter Register value on runtime.
00947   * @param  __HANDLE__: TIM handle.
00948   * @retval None
00949   */
00950 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
00951
00952 /**
00953   * @brief  Sets the TIM Autoreload Register value on runtime without calling
00954   *         another time any Init function.
00955   * @param  __HANDLE__: TIM handle.
00956   * @param  __AUTORELOAD__: specifies the Counter register new value.
00957   * @retval None
00958   */
00959 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \
00960                         do{                                                  \
00961                             (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
00962                             (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
00963                           } while(0)
00964 /**
00965   * @brief  Gets the TIM Autoreload Register value on runtime
00966   * @param  __HANDLE__: TIM handle.
00967   * @retval None
00968   */
00969 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
00970
00971 /**
00972   * @brief  Sets the TIM Clock Division value on runtime without calling
00973   *         another time any Init function.
00974   * @param  __HANDLE__: TIM handle.
00975   * @param  __CKD__: specifies the clock division value.
00976   *          This parameter can be one of the following value:
00977   *            @arg TIM_CLOCKDIVISION_DIV1
00978   *            @arg TIM_CLOCKDIVISION_DIV2
00979   *            @arg TIM_CLOCKDIVISION_DIV4
00980   * @retval None
00981   */
00982 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
00983                         do{                                                             \
00984                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
00985                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
00986                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
00987                           } while(0)
00988 /**
00989   * @brief  Gets the TIM Clock Division value on runtime
00990   * @param  __HANDLE__: TIM handle.
00991   * @retval None
00992   */
00993 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
00994
00995 /**
00996   * @brief  Sets the TIM Input Capture prescaler on runtime without calling
00997   *         another time HAL_TIM_IC_ConfigChannel() function.
00998   * @param  __HANDLE__: TIM handle.
00999   * @param  __CHANNEL__ : TIM Channels to be configured.
01000   *          This parameter can be one of the following values:
01001   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01002   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01003   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01004   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01005   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
01006   *          This parameter can be one of the following values:
01007   *            @arg TIM_ICPSC_DIV1: no prescaler
01008   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01009   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01010   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01011   * @retval None
01012   */
01013 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01014                         do{                                                    \
01015                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01016                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01017                           } while(0)
01018
01019 /**
01020   * @brief  Gets the TIM Input Capture prescaler on runtime
01021   * @param  __HANDLE__: TIM handle.
01022   * @param  __CHANNEL__ : TIM Channels to be configured.
01023   *          This parameter can be one of the following values:
01024   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01025   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01026   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01027   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01028   * @retval None
01029   */
01030 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01031   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01032    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
01033    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01034    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
01035
01036 /**
01037   * @brief  Sets the TIM Capture x input polarity on runtime.
01038   * @param  __HANDLE__: TIM handle.
01039   * @param  __CHANNEL__: TIM Channels to be configured.
01040   *          This parameter can be one of the following values:
01041   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01042   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01043   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01044   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01045   * @param  __POLARITY__: Polarity for TIx source
01046   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01047   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01048   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01049   * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.
01050   * @retval None
01051   */
01052 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \
01053                        do{                                                                            \
01054                            TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01055                            TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01056                          }while(0)
01057
01058 /**
01059   * @}
01060   */
01061
01062 /* Include TIM HAL Extension module */
01063 #include "stm32f7xx_hal_tim_ex.h"
01064
01065 /* Exported functions --------------------------------------------------------*/
01066 /** @addtogroup TIM_Exported_Functions
01067   * @{
01068   */
01069
01070 /** @addtogroup TIM_Exported_Functions_Group1
01071   * @{
01072   */
01073
01074 /* Time Base functions ********************************************************/
01075 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01076 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01077 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01078 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01079 /* Blocking mode: Polling */
01080 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01081 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01082 /* Non-Blocking mode: Interrupt */
01083 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01084 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01085 /* Non-Blocking mode: DMA */
01086 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01087 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01088 /**
01089   * @}
01090   */
01091
01092 /** @addtogroup TIM_Exported_Functions_Group2
01093   * @{
01094   */
01095 /* Timer Output Compare functions **********************************************/
01096 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01097 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01098 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01099 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01100 /* Blocking mode: Polling */
01101 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01102 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01103 /* Non-Blocking mode: Interrupt */
01104 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01105 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01106 /* Non-Blocking mode: DMA */
01107 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01108 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01109
01110 /**
01111   * @}
01112   */
01113
01114 /** @addtogroup TIM_Exported_Functions_Group3
01115   * @{
01116   */
01117 /* Timer PWM functions *********************************************************/
01118 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01119 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01120 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01121 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01122 /* Blocking mode: Polling */
01123 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01124 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01125 /* Non-Blocking mode: Interrupt */
01126 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01127 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01128 /* Non-Blocking mode: DMA */
01129 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01130 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01131
01132 /**
01133   * @}
01134   */
01135
01136 /** @addtogroup TIM_Exported_Functions_Group4
01137   * @{
01138   */
01139 /* Timer Input Capture functions ***********************************************/
01140 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01141 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01142 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01143 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01144 /* Blocking mode: Polling */
01145 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01146 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01147 /* Non-Blocking mode: Interrupt */
01148 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01149 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01150 /* Non-Blocking mode: DMA */
01151 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01152 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01153
01154 /**
01155   * @}
01156   */
01157
01158 /** @addtogroup TIM_Exported_Functions_Group5
01159   * @{
01160   */
01161 /* Timer One Pulse functions ***************************************************/
01162 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01163 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01164 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01165 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01166 /* Blocking mode: Polling */
01167 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01168 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01169
01170 /* Non-Blocking mode: Interrupt */
01171 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01172 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01173
01174 /**
01175   * @}
01176   */
01177
01178 /** @addtogroup TIM_Exported_Functions_Group6
01179   * @{
01180   */
01181 /* Timer Encoder functions *****************************************************/
01182 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01183 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01184 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01185 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01186  /* Blocking mode: Polling */
01187 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01188 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01189 /* Non-Blocking mode: Interrupt */
01190 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01191 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01192 /* Non-Blocking mode: DMA */
01193 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01194 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01195
01196 /**
01197   * @}
01198   */
01199
01200 /** @addtogroup TIM_Exported_Functions_Group7
01201   * @{
01202   */
01203 /* Interrupt Handler functions  **********************************************/
01204 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01205
01206 /**
01207   * @}
01208   */
01209
01210 /** @addtogroup TIM_Exported_Functions_Group8
01211   * @{
01212   */
01213 /* Control functions  *********************************************************/
01214 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01215 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01216 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01217 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01218 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01219 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01220 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01221 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01222 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01223 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01224                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01225 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01226 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01227                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01228 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01229 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01230 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01231
01232 /**
01233   * @}
01234   */
01235
01236 /** @addtogroup TIM_Exported_Functions_Group9
01237   * @{
01238   */
01239 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01240 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01241 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01242 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01243 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01244 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01245 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01246
01247 /**
01248   * @}
01249   */
01250
01251 /** @addtogroup TIM_Exported_Functions_Group10
01252   * @{
01253   */
01254 /* Peripheral State functions  **************************************************/
01255 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01256 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01257 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01258 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01259 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01260 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01261
01262 /**
01263   * @}
01264   */
01265
01266 /**
01267   * @}
01268   */
01269
01270 /* Private macros ------------------------------------------------------------*/
01271 /** @defgroup TIM_Private_Macros TIM Private Macros
01272   * @{
01273   */
01274
01275 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
01276   * @{
01277   */
01278 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01279                                        ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01280                                        ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01281                                        ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01282                                        ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01283
01284 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01285                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01286                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01287
01288 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
01289                                       ((__STATE__) == TIM_OCFAST_ENABLE))
01290
01291 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
01292                                     ((STATE) == TIM_OUTPUTSTATE_ENABLE))
01293
01294 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
01295                                      ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
01296
01297 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01298                                           ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01299
01300 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01301                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01302
01303 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01304                                         ((__STATE__) == TIM_OCIDLESTATE_RESET))
01305
01306 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01307                                          ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01308
01309 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01310                                           ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01311                                           ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01312
01313 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01314                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01315                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01316
01317 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01318                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01319                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01320                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01321
01322 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
01323                                    ((__MODE__) == TIM_OPMODE_REPETITIVE))
01324
01325 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01326                                        ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01327                                        ((__MODE__) == TIM_ENCODERMODE_TI12))
01328
01329 #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))
01330
01331
01332 #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE)  || \
01333                                ((__IT__) == TIM_IT_CC1)     || \
01334                                ((__IT__) == TIM_IT_CC2)     || \
01335                                ((__IT__) == TIM_IT_CC3)     || \
01336                                ((__IT__) == TIM_IT_CC4)     || \
01337                                ((__IT__) == TIM_IT_COM)     || \
01338                                ((__IT__) == TIM_IT_TRIGGER) || \
01339                                ((__IT__) == TIM_IT_BREAK))
01340
01341 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
01342
01343 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
01344
01345 #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
01346                                ((__FLAG__) == TIM_FLAG_CC1)     || \
01347                                ((__FLAG__) == TIM_FLAG_CC2)     || \
01348                                ((__FLAG__) == TIM_FLAG_CC3)     || \
01349                                ((__FLAG__) == TIM_FLAG_CC4)     || \
01350                                ((__FLAG__) == TIM_FLAG_COM)     || \
01351                                ((__FLAG__) == TIM_FLAG_TRIGGER) || \
01352                                ((__FLAG__) == TIM_FLAG_BREAK)   || \
01353                                ((__FLAG__) == TIM_FLAG_BREAK2)  || \
01354                                ((__FLAG__) == TIM_FLAG_CC1OF)   || \
01355                                ((__FLAG__) == TIM_FLAG_CC2OF)   || \
01356                                ((__FLAG__) == TIM_FLAG_CC3OF)   || \
01357                                ((__FLAG__) == TIM_FLAG_CC4OF))
01358
01359 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01360                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01361                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01362                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01363                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01364                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
01365                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01366                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01367                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01368                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
01369
01370 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01371                                         ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01372                                         ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01373                                         ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01374                                         ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01375
01376 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01377                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01378                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01379                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01380
01381 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xF)
01382
01383 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01384                                                     ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01385
01386 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)   (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01387                                                  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01388                                                  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01389                                                  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01390
01391 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
01392
01393 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
01394                                       ((__STATE__) == TIM_OSSR_DISABLE))
01395
01396 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
01397                                       ((__STATE__) == TIM_OSSI_DISABLE))
01398
01399 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01400                                       ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
01401                                       ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
01402                                       ((__LEVEL__) == TIM_LOCKLEVEL_3))
01403
01404 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
01405                                        ((__STATE__) == TIM_BREAK_DISABLE))
01406
01407 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01408                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01409
01410 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01411                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01412
01413 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
01414                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01415                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01416                                         ((__SOURCE__) == TIM_TRGO_OC1) || \
01417                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01418                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01419                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01420                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01421
01422 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01423                                      ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01424
01425 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01426                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
01427                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
01428                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
01429                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
01430                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
01431                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
01432                                                  ((__SELECTION__) == TIM_TS_ETRF))
01433
01434 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
01435                                                       ((SELECTION) == TIM_TS_ITR1) || \
01436                                                       ((SELECTION) == TIM_TS_ITR2) || \
01437                                                       ((SELECTION) == TIM_TS_ITR3))
01438
01439 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01440                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
01441                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
01442                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
01443                                                                ((__SELECTION__) == TIM_TS_NONE))
01444
01445 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)     (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01446                                                   ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01447                                                   ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
01448                                                   ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01449                                                   ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01450
01451 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__)  (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
01452                                                  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
01453                                                  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
01454                                                  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
01455
01456 #define IS_TIM_TRIGGERFILTER(__ICFILTER__)     ((__ICFILTER__) <= 0xF)
01457
01458 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)   (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
01459                                                  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
01460
01461 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
01462                                    ((__BASE__) == TIM_DMABASE_CR2) || \
01463                                    ((__BASE__) == TIM_DMABASE_SMCR) || \
01464                                    ((__BASE__) == TIM_DMABASE_DIER) || \
01465                                    ((__BASE__) == TIM_DMABASE_SR) || \
01466                                    ((__BASE__) == TIM_DMABASE_EGR) || \
01467                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01468                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01469                                    ((__BASE__) == TIM_DMABASE_CCER) || \
01470                                    ((__BASE__) == TIM_DMABASE_CNT) || \
01471                                    ((__BASE__) == TIM_DMABASE_PSC) || \
01472                                    ((__BASE__) == TIM_DMABASE_ARR) || \
01473                                    ((__BASE__) == TIM_DMABASE_RCR) || \
01474                                    ((__BASE__) == TIM_DMABASE_CCR1) || \
01475                                    ((__BASE__) == TIM_DMABASE_CCR2) || \
01476                                    ((__BASE__) == TIM_DMABASE_CCR3) || \
01477                                    ((__BASE__) == TIM_DMABASE_CCR4) || \
01478                                    ((__BASE__) == TIM_DMABASE_BDTR) || \
01479                                    ((__BASE__) == TIM_DMABASE_DCR) || \
01480                                    ((__BASE__) == TIM_DMABASE_OR))
01481
01482 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01483                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01484                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01485                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01486                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01487                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01488                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01489                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01490                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01491                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01492                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01493                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01494                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01495                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01496                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01497                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01498                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01499                                        ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
01500
01501 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
01502
01503
01504 /**
01505   * @}
01506   */
01507
01508 /**
01509   * @}
01510   */
01511
01512 /* Private functions ---------------------------------------------------------*/
01513 /** @defgroup TIM_Private_Functions TIM Private Functions
01514   * @{
01515   */
01516 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01517 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01518 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01519 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01520 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01521 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01522 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
01523
01524 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01525 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
01526 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01527 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01528 /**
01529   * @}
01530   */
01531
01532 /**
01533   * @}
01534   */
01535
01536 /**
01537   * @}
01538   */
01539
01540 #ifdef __cplusplus
01541 }
01542 #endif
01543
01544 #endif /* __STM32F7xx_HAL_TIM_H */
01545
01546 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim_ex.c Source File

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stm32f7xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer extension peripheral:
00010   *           + Time Hall Sensor Interface Initialization
00011   *           + Time Hall Sensor Interface Start
00012   *           + Time Complementary signal bread and dead time configuration
00013   *           + Time Master and Slave synchronization configuration
00014   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00015   *           + Time OCRef clear configuration
00016   *           + Timer remapping capabilities configuration
00017   @verbatim
00018   ==============================================================================
00019                       ##### TIMER Extended features #####
00020   ==============================================================================
00021   [..]
00022     The Timer Extension features include:
00023     (#) Complementary outputs with programmable dead-time for :
00024         (++) Input Capture
00025         (++) Output Compare
00026         (++) PWM generation (Edge and Center-aligned Mode)
00027         (++) One-pulse mode output
00028     (#) Synchronization circuit to control the timer with external signals and to
00029         interconnect several timers together.
00030     (#) Break input to put the timer output signals in reset state or in a known state.
00031     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00032         positioning purposes
00033
00034                         ##### How to use this driver #####
00035   ==============================================================================
00036   [..]
00037      (#) Initialize the TIM low level resources by implementing the following functions
00038          depending from feature used :
00039            (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
00040            (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
00041            (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00042            (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
00043
00044      (#) Initialize the TIM low level resources :
00045         (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
00046         (##) TIM pins configuration
00047             (+++) Enable the clock for the TIM GPIOs using the following function:
00048                  __GPIOx_CLK_ENABLE();
00049             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00050
00051      (#) The external Clock can be configured, if needed (the default clock is the
00052          internal clock from the APBx), using the following function:
00053          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00054          any start function.
00055
00056     (#) Configure the TIM in the desired functioning mode using one of the
00057         initialization function of this driver:
00058         (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
00059              Timer Hall Sensor Interface and the commutation event with the corresponding
00060              Interrupt and DMA request if needed (Note that One Timer is used to interface
00061              with the Hall sensor Interface and another Timer should be used to use
00062              the commutation event).
00063
00064     (#) Activate the TIM peripheral using one of the start functions:
00065            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
00066            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00067            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00068            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00069
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32f7xx_hal.h"
00104
00105 /** @addtogroup STM32F7xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup TIMEx TIMEx
00110   * @brief TIM Extended HAL module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_TIM_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 #define BDTR_BKF_SHIFT  (16)
00119 #define BDTR_BK2F_SHIFT (20)
00120 /* Private macro -------------------------------------------------------------*/
00121 /* Private variables ---------------------------------------------------------*/
00122 /* Private function prototypes -----------------------------------------------*/
00123 /** @addtogroup TIMEx_Private_Functions
00124   * @{
00125   */
00126 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00127 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00128 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00129 /**
00130   * @}
00131   */
00132 /* Private functions ---------------------------------------------------------*/
00133
00134 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
00135   * @{
00136   */
00137
00138 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00139  *  @brief    Timer Hall Sensor functions
00140  *
00141 @verbatim
00142   ==============================================================================
00143                       ##### Timer Hall Sensor functions #####
00144   ==============================================================================
00145   [..]
00146     This section provides functions allowing to:
00147     (+) Initialize and configure TIM HAL Sensor.
00148     (+) De-initialize TIM HAL Sensor.
00149     (+) Start the Hall Sensor Interface.
00150     (+) Stop the Hall Sensor Interface.
00151     (+) Start the Hall Sensor Interface and enable interrupts.
00152     (+) Stop the Hall Sensor Interface and disable interrupts.
00153     (+) Start the Hall Sensor Interface and enable DMA transfers.
00154     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00155
00156 @endverbatim
00157   * @{
00158   */
00159 /**
00160   * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
00161   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00162   *                the configuration information for TIM module.
00163   * @param  sConfig: TIM Hall Sensor configuration structure
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00167 {
00168   TIM_OC_InitTypeDef OC_Config;
00169
00170   /* Check the TIM handle allocation */
00171   if(htim == NULL)
00172   {
00173     return HAL_ERROR;
00174   }
00175
00176   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00177   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00178   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00179   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00180   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00181   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00182
00183   /* Set the TIM state */
00184   htim->State= HAL_TIM_STATE_BUSY;
00185
00186   /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00187   HAL_TIMEx_HallSensor_MspInit(htim);
00188
00189   /* Configure the Time base in the Encoder Mode */
00190   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00191
00192   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00193   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00194
00195   /* Reset the IC1PSC Bits */
00196   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00197   /* Set the IC1PSC value */
00198   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00199
00200   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00201   htim->Instance->CR2 |= TIM_CR2_TI1S;
00202
00203   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00204   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00205   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00206
00207   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00208   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00209   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00210
00211   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00212   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00213   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00214   OC_Config.OCMode = TIM_OCMODE_PWM2;
00215   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00216   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00217   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00218   OC_Config.Pulse = sConfig->Commutation_Delay;
00219
00220   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00221
00222   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00223     register to 101 */
00224   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00225   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00226
00227   /* Initialize the TIM state*/
00228   htim->State= HAL_TIM_STATE_READY;
00229
00230   return HAL_OK;
00231 }
00232
00233 /**
00234   * @brief  DeInitializes the TIM Hall Sensor interface
00235   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00236   *                the configuration information for TIM module.
00237   * @retval HAL status
00238   */
00239 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00240 {
00241   /* Check the parameters */
00242   assert_param(IS_TIM_INSTANCE(htim->Instance));
00243
00244   htim->State = HAL_TIM_STATE_BUSY;
00245
00246   /* Disable the TIM Peripheral Clock */
00247   __HAL_TIM_DISABLE(htim);
00248
00249   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00250   HAL_TIMEx_HallSensor_MspDeInit(htim);
00251
00252   /* Change TIM state */
00253   htim->State = HAL_TIM_STATE_RESET;
00254
00255   /* Release Lock */
00256   __HAL_UNLOCK(htim);
00257
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  Initializes the TIM Hall Sensor MSP.
00263   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00264   *                the configuration information for TIM module.
00265   * @retval None
00266   */
00267 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(htim);
00271
00272   /* NOTE : This function Should not be modified, when the callback is needed,
00273             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00274    */
00275 }
00276
00277 /**
00278   * @brief  DeInitializes TIM Hall Sensor MSP.
00279   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00280   *                the configuration information for TIM module.
00281   * @retval None
00282   */
00283 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00284 {
00285   /* Prevent unused argument(s) compilation warning */
00286   UNUSED(htim);
00287
00288   /* NOTE : This function Should not be modified, when the callback is needed,
00289             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00290    */
00291 }
00292
00293 /**
00294   * @brief  Starts the TIM Hall Sensor Interface.
00295   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00296   *                the configuration information for TIM module.
00297   * @retval HAL status
00298   */
00299 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00300 {
00301   /* Check the parameters */
00302   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00303
00304   /* Enable the Input Capture channels 1
00305     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00306   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00307
00308   /* Enable the Peripheral */
00309   __HAL_TIM_ENABLE(htim);
00310
00311   /* Return function status */
00312   return HAL_OK;
00313 }
00314
00315 /**
00316   * @brief  Stops the TIM Hall sensor Interface.
00317   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00318   *                the configuration information for TIM module.
00319   * @retval HAL status
00320   */
00321 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00322 {
00323   /* Check the parameters */
00324   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00325
00326   /* Disable the Input Capture channels 1, 2 and 3
00327     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00328   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00329
00330   /* Disable the Peripheral */
00331   __HAL_TIM_DISABLE(htim);
00332
00333   /* Return function status */
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00339   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00340   *                the configuration information for TIM module.
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00344 {
00345   /* Check the parameters */
00346   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00347
00348   /* Enable the capture compare Interrupts 1 event */
00349   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00350
00351   /* Enable the Input Capture channels 1
00352     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00353   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00354
00355   /* Enable the Peripheral */
00356   __HAL_TIM_ENABLE(htim);
00357
00358   /* Return function status */
00359   return HAL_OK;
00360 }
00361
00362 /**
00363   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00364   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00365   *                the configuration information for TIM module.
00366   * @retval HAL status
00367   */
00368 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00369 {
00370   /* Check the parameters */
00371   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00372
00373   /* Disable the Input Capture channels 1
00374     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00375   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00376
00377   /* Disable the capture compare Interrupts event */
00378   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00379
00380   /* Disable the Peripheral */
00381   __HAL_TIM_DISABLE(htim);
00382
00383   /* Return function status */
00384   return HAL_OK;
00385 }
00386
00387 /**
00388   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00389   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00390   *                the configuration information for TIM module.
00391   * @param  pData: The destination Buffer address.
00392   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00396 {
00397   /* Check the parameters */
00398   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00399
00400    if((htim->State == HAL_TIM_STATE_BUSY))
00401   {
00402      return HAL_BUSY;
00403   }
00404   else if((htim->State == HAL_TIM_STATE_READY))
00405   {
00406     if(((uint32_t)pData == 0 ) && (Length > 0))
00407     {
00408       return HAL_ERROR;
00409     }
00410     else
00411     {
00412       htim->State = HAL_TIM_STATE_BUSY;
00413     }
00414   }
00415   /* Enable the Input Capture channels 1
00416     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00417   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00418
00419   /* Set the DMA Input Capture 1 Callback */
00420   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
00421   /* Set the DMA error callback */
00422   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
00423
00424   /* Enable the DMA Stream for Capture 1*/
00425   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00426
00427   /* Enable the capture compare 1 Interrupt */
00428   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00429
00430   /* Enable the Peripheral */
00431   __HAL_TIM_ENABLE(htim);
00432
00433   /* Return function status */
00434   return HAL_OK;
00435 }
00436
00437 /**
00438   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00439   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00440   *                the configuration information for TIM module.
00441   * @retval HAL status
00442   */
00443 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00444 {
00445   /* Check the parameters */
00446   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00447
00448   /* Disable the Input Capture channels 1
00449     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00450   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00451
00452
00453   /* Disable the capture compare Interrupts 1 event */
00454   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00455
00456   /* Disable the Peripheral */
00457   __HAL_TIM_DISABLE(htim);
00458
00459   /* Return function status */
00460   return HAL_OK;
00461 }
00462
00463 /**
00464   * @}
00465   */
00466
00467 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00468  *  @brief    Timer Complementary Output Compare functions
00469  *
00470 @verbatim
00471   ==============================================================================
00472               ##### Timer Complementary Output Compare functions #####
00473   ==============================================================================
00474   [..]
00475     This section provides functions allowing to:
00476     (+) Start the Complementary Output Compare/PWM.
00477     (+) Stop the Complementary Output Compare/PWM.
00478     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00479     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00480     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00481     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00482
00483 @endverbatim
00484   * @{
00485   */
00486
00487 /**
00488   * @brief  Starts the TIM Output Compare signal generation on the complementary
00489   *         output.
00490   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00491   *                the configuration information for TIM module.
00492   * @param  Channel: TIM Channel to be enabled.
00493   *          This parameter can be one of the following values:
00494   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00495   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00496   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00497   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00498   * @retval HAL status
00499   */
00500 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00501 {
00502   /* Check the parameters */
00503   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00504
00505      /* Enable the Capture compare channel N */
00506      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00507
00508   /* Enable the Main Output */
00509     __HAL_TIM_MOE_ENABLE(htim);
00510
00511   /* Enable the Peripheral */
00512   __HAL_TIM_ENABLE(htim);
00513
00514   /* Return function status */
00515   return HAL_OK;
00516 }
00517
00518 /**
00519   * @brief  Stops the TIM Output Compare signal generation on the complementary
00520   *         output.
00521   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00522   *                the configuration information for TIM module.
00523   * @param  Channel: TIM Channel to be disabled.
00524   *          This parameter can be one of the following values:
00525   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00526   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00527   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00528   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00529   * @retval HAL status
00530   */
00531 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00532 {
00533   /* Check the parameters */
00534   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00535
00536     /* Disable the Capture compare channel N */
00537   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00538
00539   /* Disable the Main Output */
00540     __HAL_TIM_MOE_DISABLE(htim);
00541
00542   /* Disable the Peripheral */
00543   __HAL_TIM_DISABLE(htim);
00544
00545   /* Return function status */
00546   return HAL_OK;
00547 }
00548
00549 /**
00550   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00551   *         on the complementary output.
00552   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00553   *                the configuration information for TIM module.
00554   * @param  Channel: TIM Channel to be enabled.
00555   *          This parameter can be one of the following values:
00556   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00557   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00558   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00559   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00560   * @retval HAL status
00561   */
00562 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00563 {
00564   /* Check the parameters */
00565   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00566
00567   switch (Channel)
00568   {
00569     case TIM_CHANNEL_1:
00570     {
00571       /* Enable the TIM Output Compare interrupt */
00572       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00573     }
00574     break;
00575
00576     case TIM_CHANNEL_2:
00577     {
00578       /* Enable the TIM Output Compare interrupt */
00579       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00580     }
00581     break;
00582
00583     case TIM_CHANNEL_3:
00584     {
00585       /* Enable the TIM Output Compare interrupt */
00586       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00587     }
00588     break;
00589
00590     case TIM_CHANNEL_4:
00591     {
00592       /* Enable the TIM Output Compare interrupt */
00593       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00594     }
00595     break;
00596
00597     default:
00598     break;
00599   }
00600
00601   /* Enable the TIM Break interrupt */
00602   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00603
00604   /* Enable the Capture compare channel N */
00605   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00606
00607   /* Enable the Main Output */
00608  __HAL_TIM_MOE_ENABLE(htim);
00609
00610   /* Enable the Peripheral */
00611   __HAL_TIM_ENABLE(htim);
00612
00613   /* Return function status */
00614   return HAL_OK;
00615 }
00616
00617 /**
00618   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00619   *         on the complementary output.
00620   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00621   *                the configuration information for TIM module.
00622   * @param  Channel: TIM Channel to be disabled.
00623   *          This parameter can be one of the following values:
00624   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00625   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00626   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00627   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00628   * @retval HAL status
00629   */
00630 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00631 {
00632   uint32_t tmpccer = 0;
00633
00634   /* Check the parameters */
00635   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00636
00637   switch (Channel)
00638   {
00639     case TIM_CHANNEL_1:
00640     {
00641       /* Disable the TIM Output Compare interrupt */
00642       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00643     }
00644     break;
00645
00646     case TIM_CHANNEL_2:
00647     {
00648       /* Disable the TIM Output Compare interrupt */
00649       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00650     }
00651     break;
00652
00653     case TIM_CHANNEL_3:
00654     {
00655       /* Disable the TIM Output Compare interrupt */
00656       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00657     }
00658     break;
00659
00660     case TIM_CHANNEL_4:
00661     {
00662       /* Disable the TIM Output Compare interrupt */
00663       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00664     }
00665     break;
00666
00667     default:
00668     break;
00669   }
00670
00671   /* Disable the Capture compare channel N */
00672   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00673
00674   /* Disable the TIM Break interrupt (only if no more channel is active) */
00675   tmpccer = htim->Instance->CCER;
00676   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00677   {
00678     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00679   }
00680
00681   /* Disable the Main Output */
00682   __HAL_TIM_MOE_DISABLE(htim);
00683
00684   /* Disable the Peripheral */
00685   __HAL_TIM_DISABLE(htim);
00686
00687   /* Return function status */
00688   return HAL_OK;
00689 }
00690
00691 /**
00692   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00693   *         on the complementary output.
00694   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00695   *                the configuration information for TIM module.
00696   * @param  Channel: TIM Channel to be enabled.
00697   *          This parameter can be one of the following values:
00698   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00699   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00700   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00701   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00702   * @param  pData: The source Buffer address.
00703   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00704   * @retval HAL status
00705   */
00706 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00707 {
00708   /* Check the parameters */
00709   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00710
00711   if((htim->State == HAL_TIM_STATE_BUSY))
00712   {
00713      return HAL_BUSY;
00714   }
00715   else if((htim->State == HAL_TIM_STATE_READY))
00716   {
00717     if(((uint32_t)pData == 0 ) && (Length > 0))
00718     {
00719       return HAL_ERROR;
00720     }
00721     else
00722     {
00723       htim->State = HAL_TIM_STATE_BUSY;
00724     }
00725   }
00726   switch (Channel)
00727   {
00728     case TIM_CHANNEL_1:
00729     {
00730       /* Set the DMA Period elapsed callback */
00731       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00732
00733       /* Set the DMA error callback */
00734       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
00735
00736       /* Enable the DMA Stream */
00737       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00738
00739       /* Enable the TIM Output Compare DMA request */
00740       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00741     }
00742     break;
00743
00744     case TIM_CHANNEL_2:
00745     {
00746       /* Set the DMA Period elapsed callback */
00747       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00748
00749       /* Set the DMA error callback */
00750       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
00751
00752       /* Enable the DMA Stream */
00753       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00754
00755       /* Enable the TIM Output Compare DMA request */
00756       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00757     }
00758     break;
00759
00760     case TIM_CHANNEL_3:
00761 {
00762       /* Set the DMA Period elapsed callback */
00763       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00764
00765       /* Set the DMA error callback */
00766       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
00767
00768       /* Enable the DMA Stream */
00769       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00770
00771       /* Enable the TIM Output Compare DMA request */
00772       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00773     }
00774     break;
00775
00776     case TIM_CHANNEL_4:
00777     {
00778      /* Set the DMA Period elapsed callback */
00779       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
00780
00781       /* Set the DMA error callback */
00782       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
00783
00784       /* Enable the DMA Stream */
00785       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00786
00787       /* Enable the TIM Output Compare DMA request */
00788       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00789     }
00790     break;
00791
00792     default:
00793     break;
00794   }
00795
00796   /* Enable the Capture compare channel N */
00797   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00798
00799   /* Enable the Main Output */
00800   __HAL_TIM_MOE_ENABLE(htim);
00801
00802   /* Enable the Peripheral */
00803   __HAL_TIM_ENABLE(htim);
00804
00805   /* Return function status */
00806   return HAL_OK;
00807 }
00808
00809 /**
00810   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00811   *         on the complementary output.
00812   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00813   *                the configuration information for TIM module.
00814   * @param  Channel: TIM Channel to be disabled.
00815   *          This parameter can be one of the following values:
00816   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00817   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00818   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00819   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00820   * @retval HAL status
00821   */
00822 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00823 {
00824   /* Check the parameters */
00825   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00826
00827   switch (Channel)
00828   {
00829     case TIM_CHANNEL_1:
00830     {
00831       /* Disable the TIM Output Compare DMA request */
00832       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00833     }
00834     break;
00835
00836     case TIM_CHANNEL_2:
00837     {
00838       /* Disable the TIM Output Compare DMA request */
00839       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00840     }
00841     break;
00842
00843     case TIM_CHANNEL_3:
00844     {
00845       /* Disable the TIM Output Compare DMA request */
00846       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00847     }
00848     break;
00849
00850     case TIM_CHANNEL_4:
00851     {
00852       /* Disable the TIM Output Compare interrupt */
00853       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00854     }
00855     break;
00856
00857     default:
00858     break;
00859   }
00860
00861   /* Disable the Capture compare channel N */
00862   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00863
00864   /* Disable the Main Output */
00865   __HAL_TIM_MOE_DISABLE(htim);
00866
00867   /* Disable the Peripheral */
00868   __HAL_TIM_DISABLE(htim);
00869
00870   /* Change the htim state */
00871   htim->State = HAL_TIM_STATE_READY;
00872
00873   /* Return function status */
00874   return HAL_OK;
00875 }
00876
00877 /**
00878   * @}
00879   */
00880
00881 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00882  *  @brief    Timer Complementary PWM functions
00883  *
00884 @verbatim
00885   ==============================================================================
00886                  ##### Timer Complementary PWM functions #####
00887   ==============================================================================
00888   [..]
00889     This section provides functions allowing to:
00890     (+) Start the Complementary PWM.
00891     (+) Stop the Complementary PWM.
00892     (+) Start the Complementary PWM and enable interrupts.
00893     (+) Stop the Complementary PWM and disable interrupts.
00894     (+) Start the Complementary PWM and enable DMA transfers.
00895     (+) Stop the Complementary PWM and disable DMA transfers.
00896     (+) Start the Complementary Input Capture measurement.
00897     (+) Stop the Complementary Input Capture.
00898     (+) Start the Complementary Input Capture and enable interrupts.
00899     (+) Stop the Complementary Input Capture and disable interrupts.
00900     (+) Start the Complementary Input Capture and enable DMA transfers.
00901     (+) Stop the Complementary Input Capture and disable DMA transfers.
00902     (+) Start the Complementary One Pulse generation.
00903     (+) Stop the Complementary One Pulse.
00904     (+) Start the Complementary One Pulse and enable interrupts.
00905     (+) Stop the Complementary One Pulse and disable interrupts.
00906
00907 @endverbatim
00908   * @{
00909   */
00910
00911 /**
00912   * @brief  Starts the PWM signal generation on the complementary output.
00913   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00914   *                the configuration information for TIM module.
00915   * @param  Channel: TIM Channel to be enabled.
00916   *          This parameter can be one of the following values:
00917   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00918   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00919   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00920   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00921   * @retval HAL status
00922   */
00923 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00924 {
00925   /* Check the parameters */
00926   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00927
00928   /* Enable the complementary PWM output  */
00929   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00930
00931   /* Enable the Main Output */
00932   __HAL_TIM_MOE_ENABLE(htim);
00933
00934   /* Enable the Peripheral */
00935   __HAL_TIM_ENABLE(htim);
00936
00937   /* Return function status */
00938   return HAL_OK;
00939 }
00940
00941 /**
00942   * @brief  Stops the PWM signal generation on the complementary output.
00943   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00944   *                the configuration information for TIM module.
00945   * @param  Channel: TIM Channel to be disabled.
00946   *          This parameter can be one of the following values:
00947   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00948   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00949   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00950   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00951   * @retval HAL status
00952   */
00953 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00954 {
00955   /* Check the parameters */
00956   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00957
00958   /* Disable the complementary PWM output  */
00959   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00960
00961   /* Disable the Main Output */
00962   __HAL_TIM_MOE_DISABLE(htim);
00963
00964   /* Disable the Peripheral */
00965   __HAL_TIM_DISABLE(htim);
00966
00967   /* Return function status */
00968   return HAL_OK;
00969 }
00970
00971 /**
00972   * @brief  Starts the PWM signal generation in interrupt mode on the
00973   *         complementary output.
00974   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00975   *                the configuration information for TIM module.
00976   * @param  Channel: TIM Channel to be disabled.
00977   *          This parameter can be one of the following values:
00978   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00979   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00980   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00981   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00982   * @retval HAL status
00983   */
00984 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00985 {
00986   /* Check the parameters */
00987   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00988
00989   switch (Channel)
00990   {
00991     case TIM_CHANNEL_1:
00992     {
00993       /* Enable the TIM Capture/Compare 1 interrupt */
00994       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00995     }
00996     break;
00997
00998     case TIM_CHANNEL_2:
00999     {
01000       /* Enable the TIM Capture/Compare 2 interrupt */
01001       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01002     }
01003     break;
01004
01005     case TIM_CHANNEL_3:
01006     {
01007       /* Enable the TIM Capture/Compare 3 interrupt */
01008       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01009     }
01010     break;
01011
01012     case TIM_CHANNEL_4:
01013     {
01014       /* Enable the TIM Capture/Compare 4 interrupt */
01015       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01016     }
01017     break;
01018
01019     default:
01020     break;
01021   }
01022
01023   /* Enable the TIM Break interrupt */
01024   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01025
01026   /* Enable the complementary PWM output  */
01027   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01028
01029   /* Enable the Main Output */
01030   __HAL_TIM_MOE_ENABLE(htim);
01031
01032   /* Enable the Peripheral */
01033   __HAL_TIM_ENABLE(htim);
01034
01035   /* Return function status */
01036   return HAL_OK;
01037 }
01038
01039 /**
01040   * @brief  Stops the PWM signal generation in interrupt mode on the
01041   *         complementary output.
01042   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01043   *                the configuration information for TIM module.
01044   * @param  Channel: TIM Channel to be disabled.
01045   *          This parameter can be one of the following values:
01046   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01047   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01048   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01049   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01050   * @retval HAL status
01051   */
01052 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01053 {
01054   uint32_t tmpccer = 0;
01055
01056   /* Check the parameters */
01057   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01058
01059   switch (Channel)
01060   {
01061     case TIM_CHANNEL_1:
01062     {
01063       /* Disable the TIM Capture/Compare 1 interrupt */
01064       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01065     }
01066     break;
01067
01068     case TIM_CHANNEL_2:
01069     {
01070       /* Disable the TIM Capture/Compare 2 interrupt */
01071       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01072     }
01073     break;
01074
01075     case TIM_CHANNEL_3:
01076     {
01077       /* Disable the TIM Capture/Compare 3 interrupt */
01078       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01079     }
01080     break;
01081
01082     case TIM_CHANNEL_4:
01083     {
01084       /* Disable the TIM Capture/Compare 3 interrupt */
01085       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01086     }
01087     break;
01088
01089     default:
01090     break;
01091   }
01092
01093   /* Disable the complementary PWM output  */
01094   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01095
01096   /* Disable the TIM Break interrupt (only if no more channel is active) */
01097   tmpccer = htim->Instance->CCER;
01098   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01099   {
01100     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01101   }
01102
01103   /* Disable the Main Output */
01104   __HAL_TIM_MOE_DISABLE(htim);
01105
01106   /* Disable the Peripheral */
01107   __HAL_TIM_DISABLE(htim);
01108
01109   /* Return function status */
01110   return HAL_OK;
01111 }
01112
01113 /**
01114   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01115   *         complementary output
01116   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01117   *                the configuration information for TIM module.
01118   * @param  Channel: TIM Channel to be enabled.
01119   *          This parameter can be one of the following values:
01120   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01121   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01122   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01123   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01124   * @param  pData: The source Buffer address.
01125   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01126   * @retval HAL status
01127   */
01128 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01129 {
01130   /* Check the parameters */
01131   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01132
01133   if((htim->State == HAL_TIM_STATE_BUSY))
01134   {
01135      return HAL_BUSY;
01136   }
01137   else if((htim->State == HAL_TIM_STATE_READY))
01138   {
01139     if(((uint32_t)pData == 0 ) && (Length > 0))
01140     {
01141       return HAL_ERROR;
01142     }
01143     else
01144     {
01145       htim->State = HAL_TIM_STATE_BUSY;
01146     }
01147   }
01148   switch (Channel)
01149   {
01150     case TIM_CHANNEL_1:
01151     {
01152       /* Set the DMA Period elapsed callback */
01153       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01154
01155       /* Set the DMA error callback */
01156       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
01157
01158       /* Enable the DMA Stream */
01159       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01160
01161       /* Enable the TIM Capture/Compare 1 DMA request */
01162       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01163     }
01164     break;
01165
01166     case TIM_CHANNEL_2:
01167     {
01168       /* Set the DMA Period elapsed callback */
01169       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01170
01171       /* Set the DMA error callback */
01172       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
01173
01174       /* Enable the DMA Stream */
01175       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01176
01177       /* Enable the TIM Capture/Compare 2 DMA request */
01178       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01179     }
01180     break;
01181
01182     case TIM_CHANNEL_3:
01183     {
01184       /* Set the DMA Period elapsed callback */
01185       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01186
01187       /* Set the DMA error callback */
01188       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
01189
01190       /* Enable the DMA Stream */
01191       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01192
01193       /* Enable the TIM Capture/Compare 3 DMA request */
01194       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01195     }
01196     break;
01197
01198     case TIM_CHANNEL_4:
01199     {
01200      /* Set the DMA Period elapsed callback */
01201       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
01202
01203       /* Set the DMA error callback */
01204       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
01205
01206       /* Enable the DMA Stream */
01207       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01208
01209       /* Enable the TIM Capture/Compare 4 DMA request */
01210       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01211     }
01212     break;
01213
01214     default:
01215     break;
01216   }
01217
01218   /* Enable the complementary PWM output  */
01219      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01220
01221   /* Enable the Main Output */
01222     __HAL_TIM_MOE_ENABLE(htim);
01223
01224   /* Enable the Peripheral */
01225   __HAL_TIM_ENABLE(htim);
01226
01227   /* Return function status */
01228   return HAL_OK;
01229 }
01230
01231 /**
01232   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01233   *         output
01234   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01235   *                the configuration information for TIM module.
01236   * @param  Channel: TIM Channel to be disabled.
01237   *          This parameter can be one of the following values:
01238   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01239   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01240   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01241   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01242   * @retval HAL status
01243   */
01244 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01245 {
01246   /* Check the parameters */
01247   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01248
01249   switch (Channel)
01250   {
01251     case TIM_CHANNEL_1:
01252     {
01253       /* Disable the TIM Capture/Compare 1 DMA request */
01254       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01255     }
01256     break;
01257
01258     case TIM_CHANNEL_2:
01259     {
01260       /* Disable the TIM Capture/Compare 2 DMA request */
01261       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01262     }
01263     break;
01264
01265     case TIM_CHANNEL_3:
01266     {
01267       /* Disable the TIM Capture/Compare 3 DMA request */
01268       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01269     }
01270     break;
01271
01272     case TIM_CHANNEL_4:
01273     {
01274       /* Disable the TIM Capture/Compare 4 DMA request */
01275       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01276     }
01277     break;
01278
01279     default:
01280     break;
01281   }
01282
01283   /* Disable the complementary PWM output */
01284     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01285
01286   /* Disable the Main Output */
01287     __HAL_TIM_MOE_DISABLE(htim);
01288
01289   /* Disable the Peripheral */
01290   __HAL_TIM_DISABLE(htim);
01291
01292   /* Change the htim state */
01293   htim->State = HAL_TIM_STATE_READY;
01294
01295   /* Return function status */
01296   return HAL_OK;
01297 }
01298
01299 /**
01300   * @}
01301   */
01302
01303 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01304  *  @brief    Timer Complementary One Pulse functions
01305  *
01306 @verbatim
01307   ==============================================================================
01308                 ##### Timer Complementary One Pulse functions #####
01309   ==============================================================================
01310   [..]
01311     This section provides functions allowing to:
01312     (+) Start the Complementary One Pulse generation.
01313     (+) Stop the Complementary One Pulse.
01314     (+) Start the Complementary One Pulse and enable interrupts.
01315     (+) Stop the Complementary One Pulse and disable interrupts.
01316
01317 @endverbatim
01318   * @{
01319   */
01320
01321 /**
01322   * @brief  Starts the TIM One Pulse signal generation on the complemetary
01323   *         output.
01324   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01325   *                the configuration information for TIM module.
01326   * @param  OutputChannel: TIM Channel to be enabled.
01327   *          This parameter can be one of the following values:
01328   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01329   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01330   * @retval HAL status
01331   */
01332 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01333   {
01334   /* Check the parameters */
01335   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01336
01337   /* Enable the complementary One Pulse output */
01338   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01339
01340   /* Enable the Main Output */
01341   __HAL_TIM_MOE_ENABLE(htim);
01342
01343   /* Return function status */
01344   return HAL_OK;
01345 }
01346
01347 /**
01348   * @brief  Stops the TIM One Pulse signal generation on the complementary
01349   *         output.
01350   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01351   *                the configuration information for TIM module.
01352   * @param  OutputChannel: TIM Channel to be disabled.
01353   *          This parameter can be one of the following values:
01354   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01355   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01356   * @retval HAL status
01357   */
01358 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01359 {
01360
01361   /* Check the parameters */
01362   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01363
01364   /* Disable the complementary One Pulse output */
01365     TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01366
01367   /* Disable the Main Output */
01368     __HAL_TIM_MOE_DISABLE(htim);
01369
01370   /* Disable the Peripheral */
01371   __HAL_TIM_DISABLE(htim);
01372
01373   /* Return function status */
01374   return HAL_OK;
01375 }
01376
01377 /**
01378   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01379   *         complementary channel.
01380   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01381   *                the configuration information for TIM module.
01382   * @param  OutputChannel: TIM Channel to be enabled.
01383   *          This parameter can be one of the following values:
01384   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01385   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01386   * @retval HAL status
01387   */
01388 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01389 {
01390   /* Check the parameters */
01391   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01392
01393   /* Enable the TIM Capture/Compare 1 interrupt */
01394   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01395
01396   /* Enable the TIM Capture/Compare 2 interrupt */
01397   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01398
01399   /* Enable the complementary One Pulse output */
01400   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01401
01402   /* Enable the Main Output */
01403   __HAL_TIM_MOE_ENABLE(htim);
01404
01405   /* Return function status */
01406   return HAL_OK;
01407   }
01408
01409 /**
01410   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01411   *         complementary channel.
01412   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01413   *                the configuration information for TIM module.
01414   * @param  OutputChannel: TIM Channel to be disabled.
01415   *          This parameter can be one of the following values:
01416   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01417   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01418   * @retval HAL status
01419   */
01420 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01421 {
01422   /* Check the parameters */
01423   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01424
01425   /* Disable the TIM Capture/Compare 1 interrupt */
01426   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01427
01428   /* Disable the TIM Capture/Compare 2 interrupt */
01429   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01430
01431   /* Disable the complementary One Pulse output */
01432   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01433
01434   /* Disable the Main Output */
01435   __HAL_TIM_MOE_DISABLE(htim);
01436
01437   /* Disable the Peripheral */
01438    __HAL_TIM_DISABLE(htim);
01439
01440   /* Return function status */
01441   return HAL_OK;
01442 }
01443
01444 /**
01445   * @}
01446   */
01447
01448 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01449  *  @brief      Peripheral Control functions
01450  *
01451 @verbatim
01452   ==============================================================================
01453                     ##### Peripheral Control functions #####
01454   ==============================================================================
01455   [..]
01456     This section provides functions allowing to:
01457     (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
01458     (+) Configure External Clock source.
01459     (+) Configure Complementary channels, break features and dead time.
01460     (+) Configure Master and the Slave synchronization.
01461     (+) Configure the commutation event in case of use of the Hall sensor interface.
01462     (+) Configure the DMA Burst Mode.
01463
01464 @endverbatim
01465   * @{
01466   */
01467 /**
01468   * @brief  Configure the TIM commutation event sequence.
01469   * @note  This function is mandatory to use the commutation event in order to
01470   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01471   *        the typical use of this feature is with the use of another Timer(interface Timer)
01472   *        configured in Hall sensor interface, this interface Timer will generate the
01473   *        commutation at its TRGO output (connected to Timer used in this function) each time
01474   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01475   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01476   *                the configuration information for TIM module.
01477   * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01478   *          This parameter can be one of the following values:
01479   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01480   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01481   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01482   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01483   *            @arg TIM_TS_NONE: No trigger is needed
01484   * @param  CommutationSource: the Commutation Event source.
01485   *          This parameter can be one of the following values:
01486   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01487   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01488   * @retval HAL status
01489   */
01490 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01491 {
01492   /* Check the parameters */
01493   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
01494   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01495
01496   __HAL_LOCK(htim);
01497
01498   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01499       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01500   {
01501     /* Select the Input trigger */
01502     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01503     htim->Instance->SMCR |= InputTrigger;
01504   }
01505
01506   /* Select the Capture Compare preload feature */
01507   htim->Instance->CR2 |= TIM_CR2_CCPC;
01508   /* Select the Commutation event source */
01509   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01510   htim->Instance->CR2 |= CommutationSource;
01511
01512   __HAL_UNLOCK(htim);
01513
01514   return HAL_OK;
01515 }
01516
01517 /**
01518   * @brief  Configure the TIM commutation event sequence with interrupt.
01519   * @note  This function is mandatory to use the commutation event in order to
01520   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01521   *        the typical use of this feature is with the use of another Timer(interface Timer)
01522   *        configured in Hall sensor interface, this interface Timer will generate the
01523   *        commutation at its TRGO output (connected to Timer used in this function) each time
01524   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01525   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01526   *                the configuration information for TIM module.
01527   * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01528   *          This parameter can be one of the following values:
01529   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01530   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01531   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01532   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01533   *            @arg TIM_TS_NONE: No trigger is needed
01534   * @param  CommutationSource: the Commutation Event source.
01535   *          This parameter can be one of the following values:
01536   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01537   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01538   * @retval HAL status
01539   */
01540 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01541 {
01542   /* Check the parameters */
01543   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
01544   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01545
01546   __HAL_LOCK(htim);
01547
01548   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01549       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01550   {
01551     /* Select the Input trigger */
01552     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01553     htim->Instance->SMCR |= InputTrigger;
01554   }
01555
01556   /* Select the Capture Compare preload feature */
01557   htim->Instance->CR2 |= TIM_CR2_CCPC;
01558   /* Select the Commutation event source */
01559   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01560   htim->Instance->CR2 |= CommutationSource;
01561
01562   /* Enable the Commutation Interrupt Request */
01563   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01564
01565   __HAL_UNLOCK(htim);
01566
01567   return HAL_OK;
01568 }
01569
01570 /**
01571   * @brief  Configure the TIM commutation event sequence with DMA.
01572   * @note  This function is mandatory to use the commutation event in order to
01573   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01574   *        the typical use of this feature is with the use of another Timer(interface Timer)
01575   *        configured in Hall sensor interface, this interface Timer will generate the
01576   *        commutation at its TRGO output (connected to Timer used in this function) each time
01577   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01578   * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
01579   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01580   *                the configuration information for TIM module.
01581   * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01582   *          This parameter can be one of the following values:
01583   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01584   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01585   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01586   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01587   *            @arg TIM_TS_NONE: No trigger is needed
01588   * @param  CommutationSource: the Commutation Event source.
01589   *          This parameter can be one of the following values:
01590   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01591   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01592   * @retval HAL status
01593   */
01594 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01595 {
01596   /* Check the parameters */
01597   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
01598   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01599
01600   __HAL_LOCK(htim);
01601
01602   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01603       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01604   {
01605     /* Select the Input trigger */
01606     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01607     htim->Instance->SMCR |= InputTrigger;
01608   }
01609
01610   /* Select the Capture Compare preload feature */
01611   htim->Instance->CR2 |= TIM_CR2_CCPC;
01612   /* Select the Commutation event source */
01613   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01614   htim->Instance->CR2 |= CommutationSource;
01615
01616   /* Enable the Commutation DMA Request */
01617   /* Set the DMA Commutation Callback */
01618   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
01619   /* Set the DMA error callback */
01620   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
01621
01622   /* Enable the Commutation DMA Request */
01623   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01624
01625   __HAL_UNLOCK(htim);
01626
01627   return HAL_OK;
01628 }
01629
01630 /**
01631   * @brief  Initializes the TIM Output Compare Channels according to the specified
01632   *         parameters in the TIM_OC_InitTypeDef.
01633   * @param  htim: TIM Output Compare handle
01634   * @param  sConfig: TIM Output Compare configuration structure
01635   * @param  Channel : TIM Channels to configure
01636   *          This parameter can be one of the following values:
01637   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01638   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01639   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01640   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01641   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01642   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01643   *            @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
01644   * @retval HAL status
01645   */
01646 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
01647 {
01648   /* Check the parameters */
01649   assert_param(IS_TIM_CHANNELS(Channel));
01650   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
01651   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
01652
01653   /* Check input state */
01654   __HAL_LOCK(htim);
01655
01656   htim->State = HAL_TIM_STATE_BUSY;
01657
01658   switch (Channel)
01659   {
01660     case TIM_CHANNEL_1:
01661     {
01662       /* Check the parameters */
01663       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
01664
01665      /* Configure the TIM Channel 1 in Output Compare */
01666       TIM_OC1_SetConfig(htim->Instance, sConfig);
01667     }
01668     break;
01669
01670     case TIM_CHANNEL_2:
01671     {
01672       /* Check the parameters */
01673       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
01674
01675       /* Configure the TIM Channel 2 in Output Compare */
01676       TIM_OC2_SetConfig(htim->Instance, sConfig);
01677     }
01678     break;
01679
01680     case TIM_CHANNEL_3:
01681     {
01682       /* Check the parameters */
01683       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
01684
01685       /* Configure the TIM Channel 3 in Output Compare */
01686       TIM_OC3_SetConfig(htim->Instance, sConfig);
01687     }
01688     break;
01689
01690     case TIM_CHANNEL_4:
01691     {
01692       /* Check the parameters */
01693       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
01694
01695        /* Configure the TIM Channel 4 in Output Compare */
01696        TIM_OC4_SetConfig(htim->Instance, sConfig);
01697     }
01698     break;
01699
01700     case TIM_CHANNEL_5:
01701     {
01702       /* Check the parameters */
01703       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
01704
01705        /* Configure the TIM Channel 5 in Output Compare */
01706        TIM_OC5_SetConfig(htim->Instance, sConfig);
01707     }
01708     break;
01709
01710     case TIM_CHANNEL_6:
01711     {
01712       /* Check the parameters */
01713       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
01714
01715        /* Configure the TIM Channel 6 in Output Compare */
01716        TIM_OC6_SetConfig(htim->Instance, sConfig);
01717     }
01718     break;
01719
01720     default:
01721     break;
01722   }
01723
01724   htim->State = HAL_TIM_STATE_READY;
01725
01726   __HAL_UNLOCK(htim);
01727
01728   return HAL_OK;
01729 }
01730
01731 /**
01732   * @brief  Initializes the TIM PWM  channels according to the specified
01733   *         parameters in the TIM_OC_InitTypeDef.
01734   * @param  htim: TIM PWM handle
01735   * @param  sConfig: TIM PWM configuration structure
01736   * @param  Channel : TIM Channels to be configured
01737   *          This parameter can be one of the following values:
01738   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01739   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01740   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01741   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01742   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01743   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01744   *            @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
01745   * @retval HAL status
01746   */
01747 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
01748                                             TIM_OC_InitTypeDef* sConfig,
01749                                             uint32_t Channel)
01750 {
01751   /* Check the parameters */
01752   assert_param(IS_TIM_CHANNELS(Channel));
01753   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
01754   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
01755   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
01756
01757   /* Check input state */
01758   __HAL_LOCK(htim);
01759
01760   htim->State = HAL_TIM_STATE_BUSY;
01761
01762   switch (Channel)
01763   {
01764     case TIM_CHANNEL_1:
01765     {
01766       /* Check the parameters */
01767       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
01768
01769       /* Configure the Channel 1 in PWM mode */
01770       TIM_OC1_SetConfig(htim->Instance, sConfig);
01771
01772       /* Set the Preload enable bit for channel1 */
01773       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
01774
01775       /* Configure the Output Fast mode */
01776       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
01777       htim->Instance->CCMR1 |= sConfig->OCFastMode;
01778     }
01779     break;
01780
01781     case TIM_CHANNEL_2:
01782     {
01783       /* Check the parameters */
01784       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
01785
01786       /* Configure the Channel 2 in PWM mode */
01787       TIM_OC2_SetConfig(htim->Instance, sConfig);
01788
01789       /* Set the Preload enable bit for channel2 */
01790       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
01791
01792       /* Configure the Output Fast mode */
01793       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
01794       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
01795     }
01796     break;
01797
01798     case TIM_CHANNEL_3:
01799     {
01800       /* Check the parameters */
01801       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
01802
01803       /* Configure the Channel 3 in PWM mode */
01804       TIM_OC3_SetConfig(htim->Instance, sConfig);
01805
01806       /* Set the Preload enable bit for channel3 */
01807       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
01808
01809      /* Configure the Output Fast mode */
01810       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
01811       htim->Instance->CCMR2 |= sConfig->OCFastMode;
01812     }
01813     break;
01814
01815     case TIM_CHANNEL_4:
01816     {
01817       /* Check the parameters */
01818       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
01819
01820       /* Configure the Channel 4 in PWM mode */
01821       TIM_OC4_SetConfig(htim->Instance, sConfig);
01822
01823       /* Set the Preload enable bit for channel4 */
01824       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
01825
01826      /* Configure the Output Fast mode */
01827       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
01828       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
01829     }
01830     break;
01831
01832     case TIM_CHANNEL_5:
01833     {
01834        /* Check the parameters */
01835       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
01836
01837      /* Configure the Channel 5 in PWM mode */
01838       TIM_OC5_SetConfig(htim->Instance, sConfig);
01839
01840       /* Set the Preload enable bit for channel5*/
01841       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
01842
01843      /* Configure the Output Fast mode */
01844       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
01845       htim->Instance->CCMR3 |= sConfig->OCFastMode;
01846     }
01847     break;
01848
01849     case TIM_CHANNEL_6:
01850     {
01851        /* Check the parameters */
01852       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
01853
01854      /* Configure the Channel 5 in PWM mode */
01855       TIM_OC6_SetConfig(htim->Instance, sConfig);
01856
01857       /* Set the Preload enable bit for channel6 */
01858       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
01859
01860      /* Configure the Output Fast mode */
01861       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
01862       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
01863     }
01864     break;
01865
01866     default:
01867     break;
01868   }
01869
01870   htim->State = HAL_TIM_STATE_READY;
01871
01872   __HAL_UNLOCK(htim);
01873
01874   return HAL_OK;
01875 }
01876
01877 /**
01878   * @brief  Configures the OCRef clear feature
01879   * @param  htim: TIM handle
01880   * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
01881   *         contains the OCREF clear feature and parameters for the TIM peripheral.
01882   * @param  Channel: specifies the TIM Channel
01883   *          This parameter can be one of the following values:
01884   *            @arg TIM_Channel_1: TIM Channel 1
01885   *            @arg TIM_Channel_2: TIM Channel 2
01886   *            @arg TIM_Channel_3: TIM Channel 3
01887   *            @arg TIM_Channel_4: TIM Channel 4
01888   *            @arg TIM_Channel_5: TIM Channel 5
01889   *            @arg TIM_Channel_6: TIM Channel 6
01890   * @retval None
01891   */
01892 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
01893                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
01894                                            uint32_t Channel)
01895 {
01896   uint32_t tmpsmcr = 0;
01897
01898   /* Check the parameters */
01899   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
01900   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
01901
01902   /* Check input state */
01903   __HAL_LOCK(htim);
01904
01905   switch (sClearInputConfig->ClearInputSource)
01906   {
01907     case TIM_CLEARINPUTSOURCE_NONE:
01908     {
01909       /* Clear the OCREF clear selection bit */
01910       tmpsmcr &= ~TIM_SMCR_OCCS;
01911
01912       /* Clear the ETR Bits */
01913       tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
01914
01915       /* Set TIMx_SMCR */
01916       htim->Instance->SMCR = tmpsmcr;
01917    }
01918     break;
01919
01920     case TIM_CLEARINPUTSOURCE_OCREFCLR:
01921     {
01922       /* Clear the OCREF clear selection bit */
01923       htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
01924     }
01925     break;
01926
01927     case TIM_CLEARINPUTSOURCE_ETR:
01928     {
01929       /* Check the parameters */
01930       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
01931       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
01932       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
01933
01934       TIM_ETR_SetConfig(htim->Instance,
01935                         sClearInputConfig->ClearInputPrescaler,
01936                         sClearInputConfig->ClearInputPolarity,
01937                         sClearInputConfig->ClearInputFilter);
01938
01939       /* Set the OCREF clear selection bit */
01940       htim->Instance->SMCR |= TIM_SMCR_OCCS;
01941     }
01942     break;
01943     default:
01944     break;
01945   }
01946
01947   switch (Channel)
01948   {
01949     case TIM_CHANNEL_1:
01950       {
01951         if(sClearInputConfig->ClearInputState != RESET)
01952         {
01953           /* Enable the Ocref clear feature for Channel 1 */
01954           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
01955         }
01956         else
01957         {
01958           /* Disable the Ocref clear feature for Channel 1 */
01959           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
01960         }
01961       }
01962       break;
01963     case TIM_CHANNEL_2:
01964       {
01965         if(sClearInputConfig->ClearInputState != RESET)
01966         {
01967           /* Enable the Ocref clear feature for Channel 2 */
01968           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
01969         }
01970         else
01971         {
01972           /* Disable the Ocref clear feature for Channel 2 */
01973           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
01974         }
01975       }
01976     break;
01977     case TIM_CHANNEL_3:
01978       {
01979         if(sClearInputConfig->ClearInputState != RESET)
01980         {
01981           /* Enable the Ocref clear feature for Channel 3 */
01982           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
01983         }
01984         else
01985         {
01986           /* Disable the Ocref clear feature for Channel 3 */
01987           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
01988         }
01989       }
01990     break;
01991     case TIM_CHANNEL_4:
01992       {
01993         if(sClearInputConfig->ClearInputState != RESET)
01994         {
01995           /* Enable the Ocref clear feature for Channel 4 */
01996           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
01997         }
01998         else
01999         {
02000           /* Disable the Ocref clear feature for Channel 4 */
02001           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
02002         }
02003       }
02004     break;
02005     case TIM_CHANNEL_5:
02006       {
02007         if(sClearInputConfig->ClearInputState != RESET)
02008         {
02009           /* Enable the Ocref clear feature for Channel 1 */
02010           htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
02011         }
02012         else
02013         {
02014           /* Disable the Ocref clear feature for Channel 1 */
02015           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
02016         }
02017       }
02018     break;
02019     case TIM_CHANNEL_6:
02020       {
02021         if(sClearInputConfig->ClearInputState != RESET)
02022         {
02023           /* Enable the Ocref clear feature for Channel 1 */
02024           htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
02025         }
02026         else
02027         {
02028           /* Disable the Ocref clear feature for Channel 1 */
02029           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
02030         }
02031       }
02032     break;
02033     default:
02034     break;
02035   }
02036
02037   __HAL_UNLOCK(htim);
02038
02039   return HAL_OK;
02040 }
02041
02042 /**
02043   * @brief  Configures the TIM in master mode.
02044   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02045   *                the configuration information for TIM module.
02046   * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
02047   *         contains the selected trigger output (TRGO) and the Master/Slave
02048   *         mode.
02049   * @retval HAL status
02050   */
02051 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
02052 {
02053   uint32_t tmpcr2;
02054   uint32_t tmpsmcr;
02055
02056   /* Check the parameters */
02057   assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
02058   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
02059   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
02060
02061   /* Check input state */
02062   __HAL_LOCK(htim);
02063
02064  /* Get the TIMx CR2 register value */
02065   tmpcr2 = htim->Instance->CR2;
02066
02067   /* Get the TIMx SMCR register value */
02068   tmpsmcr = htim->Instance->SMCR;
02069
02070   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
02071   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
02072   {
02073     /* Check the parameters */
02074     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
02075
02076     /* Clear the MMS2 bits */
02077     tmpcr2 &= ~TIM_CR2_MMS2;
02078     /* Select the TRGO2 source*/
02079     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
02080   }
02081
02082   /* Reset the MMS Bits */
02083   tmpcr2 &= ~TIM_CR2_MMS;
02084   /* Select the TRGO source */
02085   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
02086
02087   /* Reset the MSM Bit */
02088   tmpsmcr &= ~TIM_SMCR_MSM;
02089   /* Set master mode */
02090   tmpsmcr |= sMasterConfig->MasterSlaveMode;
02091
02092   /* Update TIMx CR2 */
02093   htim->Instance->CR2 = tmpcr2;
02094
02095   /* Update TIMx SMCR */
02096   htim->Instance->SMCR = tmpsmcr;
02097
02098   __HAL_UNLOCK(htim);
02099
02100   return HAL_OK;
02101 }
02102
02103 /**
02104   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
02105   *         and the AOE(automatic output enable).
02106   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02107   *                the configuration information for TIM module.
02108   * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
02109   *         contains the BDTR Register configuration  information for the TIM peripheral.
02110   * @retval HAL status
02111   */
02112 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
02113                                               TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
02114 {
02115   uint32_t tmpbdtr = 0;
02116
02117   /* Check the parameters */
02118   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02119   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
02120   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
02121   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
02122   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
02123   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
02124   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
02125   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
02126   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
02127   assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
02128   assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
02129   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
02130
02131   /* Check input state */
02132   __HAL_LOCK(htim);
02133
02134   htim->State = HAL_TIM_STATE_BUSY;
02135
02136   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
02137      the OSSI State, the dead time value and the Automatic Output Enable Bit */
02138
02139   /* Clear the BDTR bits */
02140   tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
02141                TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
02142                TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
02143                TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
02144
02145   /* Set the BDTR bits */
02146   tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
02147   tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
02148   tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
02149   tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
02150   tmpbdtr |= sBreakDeadTimeConfig->BreakState;
02151   tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
02152   tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
02153   tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
02154   tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
02155   tmpbdtr |= sBreakDeadTimeConfig->Break2State;
02156   tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
02157
02158   /* Set TIMx_BDTR */
02159   htim->Instance->BDTR = tmpbdtr;
02160
02161   __HAL_UNLOCK(htim);
02162
02163   return HAL_OK;
02164 }
02165
02166 /**
02167   * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
02168   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02169   *                the configuration information for TIM module.
02170   * @param  Remap: specifies the TIM input remapping source.
02171   *          This parameter can be one of the following values:
02172   *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
02173   *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
02174   *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
02175   *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
02176   *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
02177   *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
02178   *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
02179   *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
02180   *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default)
02181   *            @arg TIM_TIM11_SPDIF:    SPDIF Frame synchronous
02182   *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
02183   *                                     (HSE divided by a programmable prescaler)
02184   *            @arg TIM_TIM11_MCO1:     TIM11 CH1 input is connected to MCO1
02185   * @retval HAL status
02186   */
02187 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
02188 {
02189   __HAL_LOCK(htim);
02190
02191   /* Check parameters */
02192   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02193   assert_param(IS_TIM_REMAP(Remap));
02194
02195   /* Set the Timer remapping configuration */
02196   htim->Instance->OR = Remap;
02197
02198   htim->State = HAL_TIM_STATE_READY;
02199
02200   __HAL_UNLOCK(htim);
02201
02202   return HAL_OK;
02203 }
02204
02205 /**
02206   * @brief  Group channel 5 and channel 1, 2 or 3
02207   * @param  htim: TIM handle.
02208   * @param  OCRef: specifies the reference signal(s) the OC5REF is combined with.
02209   *         This parameter can be any combination of the following values:
02210   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02211   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02212   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02213   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02214   * @retval HAL status
02215   */
02216 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
02217 {
02218   /* Check parameters */
02219   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02220   assert_param(IS_TIM_GROUPCH5(OCRef));
02221
02222   /* Process Locked */
02223   __HAL_LOCK(htim);
02224
02225   htim->State = HAL_TIM_STATE_BUSY;
02226
02227   /* Clear GC5Cx bit fields */
02228   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
02229
02230   /* Set GC5Cx bit fields */
02231   htim->Instance->CCR5 |= OCRef;
02232
02233   htim->State = HAL_TIM_STATE_READY;
02234
02235   __HAL_UNLOCK(htim);
02236
02237   return HAL_OK;
02238 }
02239
02240 /**
02241   * @}
02242   */
02243
02244 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02245   * @brief    Extended Callbacks functions
02246  *
02247 @verbatim
02248   ==============================================================================
02249                     ##### Extension Callbacks functions #####
02250   ==============================================================================
02251   [..]
02252     This section provides Extension TIM callback functions:
02253     (+) Timer Commutation callback
02254     (+) Timer Break callback
02255
02256 @endverbatim
02257   * @{
02258   */
02259
02260 /**
02261   * @brief  Hall commutation changed callback in non blocking mode
02262   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02263   *                the configuration information for TIM module.
02264   * @retval None
02265   */
02266 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
02267 {
02268   /* Prevent unused argument(s) compilation warning */
02269   UNUSED(htim);
02270
02271   /* NOTE : This function Should not be modified, when the callback is needed,
02272             the HAL_TIMEx_CommutationCallback could be implemented in the user file
02273    */
02274 }
02275
02276 /**
02277   * @brief  Hall Break detection callback in non blocking mode
02278   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02279   *                the configuration information for TIM module.
02280   * @retval None
02281   */
02282 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02283 {
02284   /* Prevent unused argument(s) compilation warning */
02285   UNUSED(htim);
02286
02287   /* NOTE : This function Should not be modified, when the callback is needed,
02288             the HAL_TIMEx_BreakCallback could be implemented in the user file
02289    */
02290 }
02291
02292 /**
02293   * @}
02294   */
02295
02296 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02297  *  @brief    Extended Peripheral State functions
02298  *
02299 @verbatim
02300   ==============================================================================
02301                 ##### Extension Peripheral State functions #####
02302   ==============================================================================
02303   [..]
02304     This subsection permits to get in run-time the status of the peripheral
02305     and the data flow.
02306
02307 @endverbatim
02308   * @{
02309   */
02310
02311 /**
02312   * @brief  Return the TIM Hall Sensor interface state
02313   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02314   *                the configuration information for TIM module.
02315   * @retval HAL state
02316   */
02317 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02318 {
02319   return htim->State;
02320 }
02321
02322 /**
02323   * @}
02324   */
02325
02326 /**
02327   * @brief  TIM DMA Commutation callback.
02328   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02329   *                the configuration information for the specified DMA module.
02330   * @retval None
02331   */
02332 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02333 {
02334   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02335
02336   htim->State= HAL_TIM_STATE_READY;
02337
02338   HAL_TIMEx_CommutationCallback(htim);
02339 }
02340
02341 /**
02342   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02343   * @param  TIMx to select the TIM peripheral
02344   * @param  Channel: specifies the TIM Channel
02345   *          This parameter can be one of the following values:
02346   *            @arg TIM_Channel_1: TIM Channel 1
02347   *            @arg TIM_Channel_2: TIM Channel 2
02348   *            @arg TIM_Channel_3: TIM Channel 3
02349   * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
02350   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02351   * @retval None
02352   */
02353 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
02354 {
02355   uint32_t tmp = 0;
02356
02357   /* Check the parameters */
02358   assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
02359   assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
02360
02361   tmp = TIM_CCER_CC1NE << Channel;
02362
02363   /* Reset the CCxNE Bit */
02364   TIMx->CCER &= ~tmp;
02365
02366   /* Set or reset the CCxNE Bit */
02367   TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
02368 }
02369
02370 /**
02371   * @brief  Timer Output Compare 5 configuration
02372   * @param  TIMx to select the TIM peripheral
02373   * @param  OC_Config: The output configuration structure
02374   * @retval None
02375   */
02376 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
02377 {
02378   uint32_t tmpccmrx = 0;
02379   uint32_t tmpccer = 0;
02380   uint32_t tmpcr2 = 0;
02381
02382   /* Disable the output: Reset the CCxE Bit */
02383   TIMx->CCER &= ~TIM_CCER_CC5E;
02384
02385   /* Get the TIMx CCER register value */
02386   tmpccer = TIMx->CCER;
02387   /* Get the TIMx CR2 register value */
02388   tmpcr2 =  TIMx->CR2;
02389   /* Get the TIMx CCMR1 register value */
02390   tmpccmrx = TIMx->CCMR3;
02391
02392   /* Reset the Output Compare Mode Bits */
02393   tmpccmrx &= ~(TIM_CCMR3_OC5M);
02394   /* Select the Output Compare Mode */
02395   tmpccmrx |= OC_Config->OCMode;
02396
02397   /* Reset the Output Polarity level */
02398   tmpccer &= ~TIM_CCER_CC5P;
02399   /* Set the Output Compare Polarity */
02400   tmpccer |= (OC_Config->OCPolarity << 16);
02401
02402   if(IS_TIM_BREAK_INSTANCE(TIMx))
02403   {
02404     /* Reset the Output Compare IDLE State */
02405     tmpcr2 &= ~TIM_CR2_OIS5;
02406     /* Set the Output Idle state */
02407     tmpcr2 |= (OC_Config->OCIdleState << 8);
02408   }
02409   /* Write to TIMx CR2 */
02410   TIMx->CR2 = tmpcr2;
02411
02412   /* Write to TIMx CCMR3 */
02413   TIMx->CCMR3 = tmpccmrx;
02414
02415   /* Set the Capture Compare Register value */
02416   TIMx->CCR5 = OC_Config->Pulse;
02417
02418   /* Write to TIMx CCER */
02419   TIMx->CCER = tmpccer;
02420 }
02421
02422 /**
02423   * @brief  Timer Output Compare 6 configuration
02424   * @param  TIMx to select the TIM peripheral
02425   * @param  OC_Config: The output configuration structure
02426   * @retval None
02427   */
02428 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
02429 {
02430   uint32_t tmpccmrx = 0;
02431   uint32_t tmpccer = 0;
02432   uint32_t tmpcr2 = 0;
02433
02434   /* Disable the output: Reset the CCxE Bit */
02435   TIMx->CCER &= ~TIM_CCER_CC6E;
02436
02437   /* Get the TIMx CCER register value */
02438   tmpccer = TIMx->CCER;
02439   /* Get the TIMx CR2 register value */
02440   tmpcr2 =  TIMx->CR2;
02441   /* Get the TIMx CCMR1 register value */
02442   tmpccmrx = TIMx->CCMR3;
02443
02444   /* Reset the Output Compare Mode Bits */
02445   tmpccmrx &= ~(TIM_CCMR3_OC6M);
02446   /* Select the Output Compare Mode */
02447   tmpccmrx |= (OC_Config->OCMode << 8);
02448
02449   /* Reset the Output Polarity level */
02450   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
02451   /* Set the Output Compare Polarity */
02452   tmpccer |= (OC_Config->OCPolarity << 20);
02453
02454   if(IS_TIM_BREAK_INSTANCE(TIMx))
02455   {
02456     /* Reset the Output Compare IDLE State */
02457     tmpcr2 &= ~TIM_CR2_OIS6;
02458     /* Set the Output Idle state */
02459     tmpcr2 |= (OC_Config->OCIdleState << 10);
02460   }
02461
02462   /* Write to TIMx CR2 */
02463   TIMx->CR2 = tmpcr2;
02464
02465   /* Write to TIMx CCMR3 */
02466   TIMx->CCMR3 = tmpccmrx;
02467
02468   /* Set the Capture Compare Register value */
02469   TIMx->CCR6 = OC_Config->Pulse;
02470
02471   /* Write to TIMx CCER */
02472   TIMx->CCER = tmpccer;
02473 }
02474
02475 /**
02476   * @}
02477   */
02478
02479 #endif /* HAL_TIM_MODULE_ENABLED */
02480 /**
02481   * @}
02482   */
02483
02484 /**
02485   * @}
02486   */
02487 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_tim_ex.h Source File

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stm32f7xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of TIM HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_TIM_EX_H
00040 #define __STM32F7xx_HAL_TIM_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIMEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIMEx_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Hall sensor Configuration Structure definition
00064   */
00065
00066 typedef struct
00067 {
00068
00069   uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
00070                                         This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00071
00072   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00073                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00074
00075   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00076                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00077   uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00078                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00079 } TIM_HallSensor_InitTypeDef;
00080
00081 /**
00082   * @brief  TIM Master configuration Structure definition
00083   */
00084 typedef struct {
00085   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection.
00086                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00087   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00088                                       This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
00089   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection.
00090                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00091 }TIM_MasterConfigTypeDef;
00092
00093 /**
00094   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00095   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00096   *        filter and polarity.
00097   */
00098 typedef struct
00099 {
00100   uint32_t OffStateRunMode;             /*!< TIM off state in run mode.
00101                                        This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00102   uint32_t OffStateIDLEMode;        /*!< TIM off state in IDLE mode.
00103                                        This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00104   uint32_t LockLevel;                   /*!< TIM Lock level.
00105                                        This parameter can be a value of @ref TIM_Lock_level */
00106   uint32_t DeadTime;                    /*!< TIM dead Time.
00107                                        This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00108   uint32_t BreakState;                  /*!< TIM Break State.
00109                                        This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00110   uint32_t BreakPolarity;           /*!< TIM Break input polarity.
00111                                        This parameter can be a value of @ref TIM_Break_Polarity */
00112   uint32_t BreakFilter;             /*!< Specifies the break input filter.
00113                                        This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00114   uint32_t Break2State;                 /*!< TIM Break2 State
00115                                        This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
00116   uint32_t Break2Polarity;          /*!< TIM Break2 input polarity
00117                                        This parameter can be a value of @ref TIMEx_Break2_Polarity */
00118   uint32_t Break2Filter;            /*!< TIM break2 input filter.
00119                                        This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00120   uint32_t AutomaticOutput;         /*!< TIM Automatic Output Enable state
00121                                        This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00122 } TIM_BreakDeadTimeConfigTypeDef;
00123
00124 /**
00125   * @}
00126   */
00127 /* Exported constants --------------------------------------------------------*/
00128 /** @defgroup TIMEx_Exported_Constants  TIMEx Exported Constants
00129   * @{
00130   */
00131
00132 /** @defgroup TIMEx_Channel TIMEx Channel
00133   * @{
00134   */
00135
00136 #define TIM_CHANNEL_1                      ((uint32_t)0x0000)
00137 #define TIM_CHANNEL_2                      ((uint32_t)0x0004)
00138 #define TIM_CHANNEL_3                      ((uint32_t)0x0008)
00139 #define TIM_CHANNEL_4                      ((uint32_t)0x000C)
00140 #define TIM_CHANNEL_5                      ((uint32_t)0x0010)
00141 #define TIM_CHANNEL_6                      ((uint32_t)0x0014)
00142 #define TIM_CHANNEL_ALL                    ((uint32_t)0x003C)
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
00149   * @{
00150   */
00151 #define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
00152 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
00153 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
00154 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00155 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
00156 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00157 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
00158 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
00159
00160 #define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
00161 #define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
00162 #define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
00163 #define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00164 #define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00165 #define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup TIMEx_Remap  TIMEx Remap
00171   * @{
00172   */
00173 #define TIM_TIM2_TIM8_TRGO                     (0x00000000)
00174 #define TIM_TIM2_ETH_PTP                       (0x00000400)
00175 #define TIM_TIM2_USBFS_SOF                     (0x00000800)
00176 #define TIM_TIM2_USBHS_SOF                     (0x00000C00)
00177 #define TIM_TIM5_GPIO                          (0x00000000)
00178 #define TIM_TIM5_LSI                           (0x00000040)
00179 #define TIM_TIM5_LSE                           (0x00000080)
00180 #define TIM_TIM5_RTC                           (0x000000C0)
00181 #define TIM_TIM11_GPIO                         (0x00000000)
00182 #define TIM_TIM11_SPDIFRX                      (0x00000001)
00183 #define TIM_TIM11_HSE                          (0x00000002)
00184 #define TIM_TIM11_MCO1                         (0x00000003)
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
00190   * @{
00191   */
00192 #define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001)
00193 #define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002)
00194 #define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup TIMEx_Break2_Input_enable_disable  TIMEx Break input 2 Enable
00200   * @{
00201   */
00202 #define TIM_BREAK2_DISABLE         ((uint32_t)0x00000000)
00203 #define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity
00209   * @{
00210   */
00211 #define TIM_BREAK2POLARITY_LOW        ((uint32_t)0x00000000)
00212 #define TIM_BREAK2POLARITY_HIGH       (TIM_BDTR_BK2P)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3
00218   * @{
00219   */
00220 #define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00221 #define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
00222 #define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
00223 #define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
00229   * @{
00230   */
00231 #define TIM_TRGO2_RESET                          ((uint32_t)0x00000000)
00232 #define TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
00233 #define TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
00234 #define TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00235 #define TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
00236 #define TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00237 #define TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
00238 #define TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00239 #define TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
00240 #define TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
00241 #define TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
00242 #define TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00243 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
00244 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00245 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
00246 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
00252   * @{
00253   */
00254 #define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000)
00255 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
00256 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
00257 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
00258 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
00259 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @}
00266   */
00267
00268 /* Exported macro ------------------------------------------------------------*/
00269 /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
00270   * @{
00271   */
00272
00273 /**
00274   * @brief  Sets the TIM Capture Compare Register value on runtime without
00275   *         calling another time ConfigChannel function.
00276   * @param  __HANDLE__: TIM handle.
00277   * @param  __CHANNEL__ : TIM Channels to be configured.
00278   *          This parameter can be one of the following values:
00279   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00280   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00281   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00282   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00283   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00284   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00285   * @param  __COMPARE__: specifies the Capture Compare register new value.
00286   * @retval None
00287   */
00288 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
00289 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
00290  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
00291  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
00292  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
00293  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
00294  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
00295
00296 /**
00297   * @brief  Gets the TIM Capture Compare Register value on runtime
00298   * @param  __HANDLE__: TIM handle.
00299   * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
00300   *          This parameter can be one of the following values:
00301   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
00302   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
00303   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
00304   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
00305   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
00306   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
00307   * @retval None
00308   */
00309 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
00310 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
00311  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
00312  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
00313  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
00314  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
00315  ((__HANDLE__)->Instance->CCR6))
00316
00317 /**
00318   * @}
00319   */
00320
00321 /* Exported functions --------------------------------------------------------*/
00322 /** @addtogroup TIMEx_Exported_Functions
00323   * @{
00324   */
00325
00326 /** @addtogroup TIMEx_Exported_Functions_Group1
00327   * @{
00328   */
00329 /*  Timer Hall Sensor functions  **********************************************/
00330 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
00331 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
00332
00333 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
00334 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
00335
00336  /* Blocking mode: Polling */
00337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
00338 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
00339 /* Non-Blocking mode: Interrupt */
00340 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
00341 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
00342 /* Non-Blocking mode: DMA */
00343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
00344 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
00345 /**
00346   * @}
00347   */
00348
00349 /** @addtogroup TIMEx_Exported_Functions_Group2
00350   * @{
00351   */
00352 /*  Timer Complementary Output Compare functions  *****************************/
00353 /* Blocking mode: Polling */
00354 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
00355 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
00356
00357 /* Non-Blocking mode: Interrupt */
00358 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00359 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00360
00361 /* Non-Blocking mode: DMA */
00362 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00363 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
00364 /**
00365   * @}
00366   */
00367
00368 /** @addtogroup TIMEx_Exported_Functions_Group3
00369   * @{
00370   */
00371 /*  Timer Complementary PWM functions  ****************************************/
00372 /* Blocking mode: Polling */
00373 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
00374 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
00375
00376 /* Non-Blocking mode: Interrupt */
00377 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00378 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00379 /* Non-Blocking mode: DMA */
00380 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00381 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
00382 /**
00383   * @}
00384   */
00385
00386 /** @addtogroup TIMEx_Exported_Functions_Group4
00387   * @{
00388   */
00389 /*  Timer Complementary One Pulse functions  **********************************/
00390 /* Blocking mode: Polling */
00391 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00392 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00393
00394 /* Non-Blocking mode: Interrupt */
00395 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00396 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00397 /**
00398   * @}
00399   */
00400
00401 /** @addtogroup TIMEx_Exported_Functions_Group5
00402   * @{
00403   */
00404 /* Extension Control functions  ************************************************/
00405 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00406 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00407 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00408 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
00409 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00410 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
00411 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);
00412 /**
00413   * @}
00414   */
00415
00416 /** @addtogroup TIMEx_Exported_Functions_Group6
00417   * @{
00418   */
00419 /* Extension Callback *********************************************************/
00420 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
00421 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
00422 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00423 /**
00424   * @}
00425   */
00426
00427 /** @addtogroup TIMEx_Exported_Functions_Group7
00428   * @{
00429   */
00430 /* Extension Peripheral State functions  **************************************/
00431 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
00432 /**
00433   * @}
00434   */
00435
00436 /**
00437   * @}
00438   */
00439
00440 /* Private types -------------------------------------------------------------*/
00441 /* Private variables ---------------------------------------------------------*/
00442 /* Private constants ---------------------------------------------------------*/
00443 /* Private macros ------------------------------------------------------------*/
00444 /** @defgroup TIMEx_Private_Macros TIMEx Private Macros
00445   * @{
00446   */
00447 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00448                                   ((CHANNEL) == TIM_CHANNEL_2) || \
00449                                   ((CHANNEL) == TIM_CHANNEL_3) || \
00450                                   ((CHANNEL) == TIM_CHANNEL_4) || \
00451                                   ((CHANNEL) == TIM_CHANNEL_5) || \
00452                                   ((CHANNEL) == TIM_CHANNEL_6) || \
00453                                   ((CHANNEL) == TIM_CHANNEL_ALL))
00454
00455 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00456                                        ((CHANNEL) == TIM_CHANNEL_2))
00457
00458 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00459                                       ((CHANNEL) == TIM_CHANNEL_2))
00460
00461 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00462                                                 ((CHANNEL) == TIM_CHANNEL_2) || \
00463                                                 ((CHANNEL) == TIM_CHANNEL_3))
00464 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1)               || \
00465                                ((MODE) == TIM_OCMODE_PWM2)               || \
00466                                ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \
00467                                ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \
00468                                ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
00469                                ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
00470
00471 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)             || \
00472                              ((MODE) == TIM_OCMODE_ACTIVE)             || \
00473                              ((MODE) == TIM_OCMODE_INACTIVE)           || \
00474                              ((MODE) == TIM_OCMODE_TOGGLE)             || \
00475                              ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \
00476                              ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \
00477                              ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
00478                              ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
00479 #define IS_TIM_REMAP(__TIM_REMAP__)      (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
00480                                       ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
00481                                       ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
00482                                       ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
00483                                       ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
00484                                       ((__TIM_REMAP__) == TIM_TIM5_LSI)||\
00485                                       ((__TIM_REMAP__) == TIM_TIM5_LSE)||\
00486                                       ((__TIM_REMAP__) == TIM_TIM5_RTC)||\
00487                                       ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
00488                                       ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
00489                                       ((__TIM_REMAP__) == TIM_TIM11_HSE)||\
00490                                       ((__TIM_REMAP__) == TIM_TIM11_MCO1))
00491 #define IS_TIM_DEADTIME(__DEADTIME__)      ((__DEADTIME__) <= 0xFF)
00492 #define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
00493 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \
00494                                         ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR)  || \
00495                                         ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
00496 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
00497                                     ((STATE) == TIM_BREAK2_DISABLE))
00498 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
00499                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
00500 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
00501 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET)                        || \
00502                                      ((SOURCE) == TIM_TRGO2_ENABLE)                       || \
00503                                      ((SOURCE) == TIM_TRGO2_UPDATE)                       || \
00504                                      ((SOURCE) == TIM_TRGO2_OC1)                          || \
00505                                      ((SOURCE) == TIM_TRGO2_OC1REF)                       || \
00506                                      ((SOURCE) == TIM_TRGO2_OC2REF)                       || \
00507                                      ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
00508                                      ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
00509                                      ((SOURCE) == TIM_TRGO2_OC4REF)                       || \
00510                                      ((SOURCE) == TIM_TRGO2_OC5REF)                       || \
00511                                      ((SOURCE) == TIM_TRGO2_OC6REF)                       || \
00512                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
00513                                      ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
00514                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
00515                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
00516                                      ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
00517                                      ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
00518 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE)   || \
00519                                  ((MODE) == TIM_SLAVEMODE_RESET)     || \
00520                                  ((MODE) == TIM_SLAVEMODE_GATED)     || \
00521                                  ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \
00522                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
00523                                  ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
00524
00525 /**
00526   * @}
00527   */
00528
00529 /* Private functions ---------------------------------------------------------*/
00530 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
00531   * @{
00532   */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /**
00543   * @}
00544   */
00545
00546 #ifdef __cplusplus
00547 }
00548 #endif
00549
00550 #endif /* __STM32F7xx_HAL_TIM_EX_H */
00551
00552 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_uart.c Source File

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stm32f7xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   UART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     The UART HAL driver can be used as follows:
00021
00022     (#) Declare a UART_HandleTypeDef handle structure.
00023
00024     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00025         (##) Enable the USARTx interface clock.
00026         (##) UART pins configuration:
00027             (+++) Enable the clock for the UART GPIOs.
00028             (+++) Configure these UART pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00030              and HAL_UART_Receive_IT() APIs):
00031             (+++) Configure the USARTx interrupt priority.
00032             (+++) Enable the NVIC USART IRQ handle.
00033         (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00034              and HAL_UART_Receive_DMA() APIs):
00035             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00036             (+++) Enable the DMAx interface clock.
00037             (+++) Configure the declared DMA handle structure with the required
00038                   Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx Stream.
00040             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete
00042                   interrupt on the DMA Tx/Rx Stream.
00043
00044     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00045         flow control and Mode(Receiver/Transmitter) in the Init structure.
00046
00047     (#) For the UART asynchronous mode, initialize the UART registers by calling
00048         the HAL_UART_Init() API.
00049
00050     (#) For the UART Half duplex mode, initialize the UART registers by calling
00051         the HAL_HalfDuplex_Init() API.
00052
00053     (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
00054
00055     (#) For the Multi-Processor mode, initialize the UART registers by calling
00056         the HAL_MultiProcessor_Init() API.
00057
00058      [..]
00059        (@) The specific UART interrupts (Transmission complete interrupt,
00060             RXNE interrupt and Error Interrupts) will be managed using the macros
00061             __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
00062             and receive process.
00063
00064      [..]
00065        (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
00066             low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
00067             HAL_UART_MspInit() API.
00068
00069      [..]
00070         Three operation modes are available within this driver :
00071
00072      *** Polling mode IO operation ***
00073      =================================
00074      [..]
00075        (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
00076        (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
00077
00078      *** Interrupt mode IO operation ***
00079      ===================================
00080      [..]
00081        (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
00082        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00083             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00084        (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
00085        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00086             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00087        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00088             add his own code by customization of function pointer HAL_UART_ErrorCallback
00089
00090      *** DMA mode IO operation ***
00091      ==============================
00092      [..]
00093        (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
00094        (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
00095             add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
00096        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00097             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00098        (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
00099        (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
00100             add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
00101        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00102             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00103        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00104             add his own code by customization of function pointer HAL_UART_ErrorCallback
00105        (+) Pause the DMA Transfer using HAL_UART_DMAPause()
00106        (+) Resume the DMA Transfer using HAL_UART_DMAResume()
00107        (+) Stop the DMA Transfer using HAL_UART_DMAStop()
00108
00109      *** UART HAL driver macros list ***
00110      =============================================
00111      [..]
00112        Below the list of most used macros in UART HAL driver.
00113
00114       (+) __HAL_UART_ENABLE: Enable the UART peripheral
00115       (+) __HAL_UART_DISABLE: Disable the UART peripheral
00116       (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
00117       (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag
00118       (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
00119       (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
00120       (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
00121
00122      [..]
00123        (@) You can refer to the UART HAL driver header file for more useful macros
00124
00125   @endverbatim
00126   ******************************************************************************
00127   * @attention
00128   *
00129   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00130   *
00131   * Redistribution and use in source and binary forms, with or without modification,
00132   * are permitted provided that the following conditions are met:
00133   *   1. Redistributions of source code must retain the above copyright notice,
00134   *      this list of conditions and the following disclaimer.
00135   *   2. Redistributions in binary form must reproduce the above copyright notice,
00136   *      this list of conditions and the following disclaimer in the documentation
00137   *      and/or other materials provided with the distribution.
00138   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00139   *      may be used to endorse or promote products derived from this software
00140   *      without specific prior written permission.
00141   *
00142   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00143   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00144   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00145   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00146   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00147   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00148   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00149   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00150   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00151   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00152   *
00153   ******************************************************************************
00154   */
00155
00156 /* Includes ------------------------------------------------------------------*/
00157 #include "stm32f7xx_hal.h"
00158
00159 /** @addtogroup STM32F7xx_HAL_Driver
00160   * @{
00161   */
00162
00163 /** @defgroup UART UART
00164   * @brief HAL UART module driver
00165   * @{
00166   */
00167 #ifdef HAL_UART_MODULE_ENABLED
00168
00169 /* Private typedef -----------------------------------------------------------*/
00170 /* Private define ------------------------------------------------------------*/
00171 #define HAL_UART_TXDMA_TIMEOUTVALUE                      22000
00172 #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00173                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
00174 /* Private macro -------------------------------------------------------------*/
00175 /* Private variables ---------------------------------------------------------*/
00176 /* Private function prototypes -----------------------------------------------*/
00177 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00178 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00179 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00180 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00181 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00182 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
00183 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00184 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
00185 /* Private functions ---------------------------------------------------------*/
00186
00187 /** @defgroup UART_Exported_Functions UART Exported Functions
00188   * @{
00189   */
00190
00191 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00192   *  @brief    Initialization and Configuration functions
00193   *
00194 @verbatim
00195 ===============================================================================
00196             ##### Initialization and Configuration functions #####
00197  ===============================================================================
00198     [..]
00199     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00200     in asynchronous mode.
00201       (+) For the asynchronous mode only these parameters can be configured:
00202         (++) Baud Rate
00203         (++) Word Length
00204         (++) Stop Bit
00205         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00206              in the data register is transmitted but is changed by the parity bit.
00207              Depending on the frame length defined by the M bit (8-bits or 9-bits),
00208              please refer to Reference manual for possible UART frame formats.
00209         (++) Hardware flow control
00210         (++) Receiver/transmitter modes
00211         (++) Over Sampling Method
00212     [..]
00213     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
00214     follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
00215     configuration procedures (details for the procedures are available in reference manual (RM0329)).
00216
00217 @endverbatim
00218   * @{
00219   */
00220
00221 /**
00222   * @brief Initializes the UART mode according to the specified
00223   *         parameters in the UART_InitTypeDef and creates the associated handle .
00224   * @param huart: uart handle
00225   * @retval HAL status
00226   */
00227 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00228 {
00229   /* Check the UART handle allocation */
00230   if(huart == NULL)
00231   {
00232     return HAL_ERROR;
00233   }
00234
00235   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00236   {
00237     /* Check the parameters */
00238     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00239   }
00240   else
00241   {
00242     /* Check the parameters */
00243     assert_param(IS_UART_INSTANCE(huart->Instance));
00244   }
00245
00246   if(huart->State == HAL_UART_STATE_RESET)
00247   {
00248     /* Allocate lock resource and initialize it */
00249     huart->Lock = HAL_UNLOCKED;
00250
00251     /* Init the low level hardware : GPIO, CLOCK */
00252     HAL_UART_MspInit(huart);
00253   }
00254
00255   huart->State = HAL_UART_STATE_BUSY;
00256
00257   /* Disable the Peripheral */
00258   __HAL_UART_DISABLE(huart);
00259
00260   /* Set the UART Communication parameters */
00261   if (UART_SetConfig(huart) == HAL_ERROR)
00262   {
00263     return HAL_ERROR;
00264   }
00265
00266   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00267   {
00268     UART_AdvFeatureConfig(huart);
00269   }
00270
00271   /* In asynchronous mode, the following bits must be kept cleared:
00272   - LINEN and CLKEN bits in the USART_CR2 register,
00273   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00274   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00275   huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00276
00277   /* Enable the Peripheral */
00278   __HAL_UART_ENABLE(huart);
00279
00280   /* TEACK and/or REACK to check before moving huart->State to Ready */
00281   return (UART_CheckIdleState(huart));
00282 }
00283
00284 /**
00285   * @brief Initializes the half-duplex mode according to the specified
00286   *         parameters in the UART_InitTypeDef and creates the associated handle .
00287   * @param huart: UART handle
00288   * @retval HAL status
00289   */
00290 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00291 {
00292   /* Check the UART handle allocation */
00293   if(huart == NULL)
00294   {
00295     return HAL_ERROR;
00296   }
00297
00298   if(huart->State == HAL_UART_STATE_RESET)
00299   {
00300     /* Allocate lock resource and initialize it */
00301     huart->Lock = HAL_UNLOCKED;
00302     /* Init the low level hardware : GPIO, CLOCK */
00303     HAL_UART_MspInit(huart);
00304   }
00305
00306   huart->State = HAL_UART_STATE_BUSY;
00307
00308   /* Disable the Peripheral */
00309   __HAL_UART_DISABLE(huart);
00310
00311   /* Set the UART Communication parameters */
00312   if (UART_SetConfig(huart) == HAL_ERROR)
00313   {
00314     return HAL_ERROR;
00315   }
00316
00317   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00318   {
00319     UART_AdvFeatureConfig(huart);
00320   }
00321
00322   /* In half-duplex mode, the following bits must be kept cleared:
00323   - LINEN and CLKEN bits in the USART_CR2 register,
00324   - SCEN and IREN bits in the USART_CR3 register.*/
00325   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00326   huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
00327
00328   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00329   huart->Instance->CR3 |= USART_CR3_HDSEL;
00330
00331   /* Enable the Peripheral */
00332   __HAL_UART_ENABLE(huart);
00333
00334   /* TEACK and/or REACK to check before moving huart->State to Ready */
00335   return (UART_CheckIdleState(huart));
00336 }
00337
00338
00339 /**
00340   * @brief Initializes the LIN mode according to the specified
00341   *         parameters in the UART_InitTypeDef and creates the associated handle .
00342   * @param huart: uart handle
00343   * @param BreakDetectLength: specifies the LIN break detection length.
00344   *        This parameter can be one of the following values:
00345   *          @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
00346   *          @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00350 {
00351   /* Check the UART handle allocation */
00352   if(huart == NULL)
00353   {
00354     return HAL_ERROR;
00355   }
00356
00357   /* Check the parameters */
00358   assert_param(IS_UART_INSTANCE(huart->Instance));
00359   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00360   assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));
00361
00362   if(huart->State == HAL_UART_STATE_RESET)
00363   {
00364     /* Allocate lock resource and initialize it */
00365     huart->Lock = HAL_UNLOCKED;
00366     /* Init the low level hardware : GPIO, CLOCK */
00367     HAL_UART_MspInit(huart);
00368   }
00369
00370   huart->State = HAL_UART_STATE_BUSY;
00371
00372   /* Disable the Peripheral */
00373   __HAL_UART_DISABLE(huart);
00374
00375   /* Set the UART Communication parameters */
00376   if (UART_SetConfig(huart) == HAL_ERROR)
00377   {
00378     return HAL_ERROR;
00379   }
00380
00381   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00382   {
00383     UART_AdvFeatureConfig(huart);
00384   }
00385
00386   /* In LIN mode, the following bits must be kept cleared:
00387   - LINEN and CLKEN bits in the USART_CR2 register,
00388   - SCEN and IREN bits in the USART_CR3 register.*/
00389   huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
00390   huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
00391
00392   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00393   huart->Instance->CR2 |= USART_CR2_LINEN;
00394
00395   /* Set the USART LIN Break detection length. */
00396   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00397
00398     /* Enable the Peripheral */
00399   __HAL_UART_ENABLE(huart);
00400
00401   /* TEACK and/or REACK to check before moving huart->State to Ready */
00402   return (UART_CheckIdleState(huart));
00403 }
00404
00405
00406
00407 /**
00408   * @brief Initializes the multiprocessor mode according to the specified
00409   *         parameters in the UART_InitTypeDef and creates the associated handle.
00410   * @param huart: UART handle
00411   * @param Address: UART node address (4-, 6-, 7- or 8-bit long)
00412   * @param WakeUpMethod: specifies the UART wakeup method.
00413   *        This parameter can be one of the following values:
00414   *          @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
00415   *          @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
00416   * @note  If the user resorts to idle line detection wake up, the Address parameter
00417   *        is useless and ignored by the initialization function.
00418   * @note  If the user resorts to address mark wake up, the address length detection
00419   *        is configured by default to 4 bits only. For the UART to be able to
00420   *        manage 6-, 7- or 8-bit long addresses detection
00421   * @retval HAL status
00422   */
00423 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00424 {
00425   /* Check the UART handle allocation */
00426   if(huart == NULL)
00427   {
00428     return HAL_ERROR;
00429   }
00430
00431   /* Check the wake up method parameter */
00432   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00433
00434   if(huart->State == HAL_UART_STATE_RESET)
00435   {
00436     /* Allocate lock resource and initialize it */
00437     huart->Lock = HAL_UNLOCKED;
00438     /* Init the low level hardware : GPIO, CLOCK */
00439     HAL_UART_MspInit(huart);
00440   }
00441
00442   huart->State = HAL_UART_STATE_BUSY;
00443
00444   /* Disable the Peripheral */
00445   __HAL_UART_DISABLE(huart);
00446
00447   /* Set the UART Communication parameters */
00448   if (UART_SetConfig(huart) == HAL_ERROR)
00449   {
00450     return HAL_ERROR;
00451   }
00452
00453   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00454   {
00455     UART_AdvFeatureConfig(huart);
00456   }
00457
00458   /* In multiprocessor mode, the following bits must be kept cleared:
00459   - LINEN and CLKEN bits in the USART_CR2 register,
00460   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00461   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00462   huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00463
00464   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00465   {
00466     /* If address mark wake up method is chosen, set the USART address node */
00467     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00468   }
00469
00470   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00471   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00472
00473   /* Enable the Peripheral */
00474   __HAL_UART_ENABLE(huart);
00475
00476   /* TEACK and/or REACK to check before moving huart->State to Ready */
00477   return (UART_CheckIdleState(huart));
00478 }
00479
00480
00481
00482
00483 /**
00484   * @brief DeInitializes the UART peripheral
00485   * @param huart: uart handle
00486   * @retval HAL status
00487   */
00488 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00489 {
00490   /* Check the UART handle allocation */
00491   if(huart == NULL)
00492   {
00493     return HAL_ERROR;
00494   }
00495
00496   /* Check the parameters */
00497   assert_param(IS_UART_INSTANCE(huart->Instance));
00498
00499   huart->State = HAL_UART_STATE_BUSY;
00500
00501   /* Disable the Peripheral */
00502   __HAL_UART_DISABLE(huart);
00503
00504   huart->Instance->CR1 = 0x0;
00505   huart->Instance->CR2 = 0x0;
00506   huart->Instance->CR3 = 0x0;
00507
00508   /* DeInit the low level hardware */
00509   HAL_UART_MspDeInit(huart);
00510
00511   huart->ErrorCode = HAL_UART_ERROR_NONE;
00512   huart->State = HAL_UART_STATE_RESET;
00513
00514   /* Process Unlock */
00515   __HAL_UNLOCK(huart);
00516
00517   return HAL_OK;
00518 }
00519
00520 /**
00521   * @brief UART MSP Init
00522   * @param huart: uart handle
00523   * @retval None
00524   */
00525  __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00526 {
00527   /* Prevent unused argument(s) compilation warning */
00528   UNUSED(huart);
00529
00530   /* NOTE : This function should not be modified, when the callback is needed,
00531             the HAL_UART_MspInit can be implemented in the user file
00532    */
00533 }
00534
00535 /**
00536   * @brief UART MSP DeInit
00537   * @param huart: uart handle
00538   * @retval None
00539   */
00540  __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00541 {
00542   /* Prevent unused argument(s) compilation warning */
00543   UNUSED(huart);
00544
00545   /* NOTE : This function should not be modified, when the callback is needed,
00546             the HAL_UART_MspDeInit can be implemented in the user file
00547    */
00548 }
00549
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00555   *  @brief UART Transmit/Receive functions
00556   *
00557 @verbatim
00558  ===============================================================================
00559                       ##### IO operation functions #####
00560  ===============================================================================
00561     This subsection provides a set of functions allowing to manage the UART asynchronous
00562     and Half duplex data transfers.
00563
00564     (#) There are two mode of transfer:
00565        (+) Blocking mode: The communication is performed in polling mode.
00566             The HAL status of all data processing is returned by the same function
00567             after finishing transfer.
00568        (+) No-Blocking mode: The communication is performed using Interrupts
00569            or DMA, These API's return the HAL status.
00570            The end of the data processing will be indicated through the
00571            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00572            using DMA mode.
00573            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00574            will be executed respectively at the end of the transmit or Receive process
00575            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
00576
00577     (#) Blocking mode API's are :
00578         (+) HAL_UART_Transmit()
00579         (+) HAL_UART_Receive()
00580
00581     (#) Non-Blocking mode API's with Interrupt are :
00582         (+) HAL_UART_Transmit_IT()
00583         (+) HAL_UART_Receive_IT()
00584         (+) HAL_UART_IRQHandler()
00585         (+) UART_Transmit_IT()
00586         (+) UART_Receive_IT()
00587
00588     (#) No-Blocking mode API's with DMA are :
00589         (+) HAL_UART_Transmit_DMA()
00590         (+) HAL_UART_Receive_DMA()
00591         (+) HAL_UART_DMAPause()
00592         (+) HAL_UART_DMAResume()
00593         (+) HAL_UART_DMAStop()
00594
00595     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00596         (+) HAL_UART_TxHalfCpltCallback()
00597         (+) HAL_UART_TxCpltCallback()
00598         (+) HAL_UART_RxHalfCpltCallback()
00599         (+) HAL_UART_RxCpltCallback()
00600         (+) HAL_UART_ErrorCallback()
00601
00602
00603     -@- In the Half duplex communication, it is forbidden to run the transmit
00604         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
00605
00606 @endverbatim
00607   * @{
00608   */
00609
00610 /**
00611   * @brief Send an amount of data in blocking mode
00612   * @param huart: uart handle
00613   * @param pData: pointer to data buffer
00614   * @param Size: amount of data to be sent
00615   * @param Timeout : Timeout duration
00616   * @retval HAL status
00617   */
00618 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00619 {
00620    uint16_t* tmp;
00621
00622   if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
00623   {
00624     if((pData == NULL ) || (Size == 0))
00625     {
00626       return  HAL_ERROR;
00627     }
00628
00629     /* Process Locked */
00630     __HAL_LOCK(huart);
00631
00632     huart->ErrorCode = HAL_UART_ERROR_NONE;
00633     /* Check if a non-blocking receive process is ongoing or not */
00634     if(huart->State == HAL_UART_STATE_BUSY_RX)
00635     {
00636       huart->State = HAL_UART_STATE_BUSY_TX_RX;
00637     }
00638     else
00639     {
00640       huart->State = HAL_UART_STATE_BUSY_TX;
00641     }
00642
00643     huart->TxXferSize = Size;
00644     huart->TxXferCount = Size;
00645     while(huart->TxXferCount > 0)
00646     {
00647       huart->TxXferCount--;
00648         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00649         {
00650           return HAL_TIMEOUT;
00651         }
00652       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00653       {
00654         tmp = (uint16_t*) pData;
00655         huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00656         pData += 2;
00657       }
00658       else
00659       {
00660         huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00661       }
00662     }
00663     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
00664     {
00665       return HAL_TIMEOUT;
00666     }
00667     /* Check if a non-blocking receive Process is ongoing or not */
00668     if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
00669     {
00670       huart->State = HAL_UART_STATE_BUSY_RX;
00671     }
00672     else
00673     {
00674       huart->State = HAL_UART_STATE_READY;
00675     }
00676
00677     /* Process Unlocked */
00678     __HAL_UNLOCK(huart);
00679
00680     return HAL_OK;
00681   }
00682   else
00683   {
00684     return HAL_BUSY;
00685   }
00686 }
00687
00688 /**
00689   * @brief Receive an amount of data in blocking mode
00690   * @param huart: uart handle
00691   * @param pData: pointer to data buffer
00692   * @param Size: amount of data to be received
00693   * @param Timeout : Timeout duration
00694   * @retval HAL status
00695   */
00696 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00697 {
00698   uint16_t* tmp;
00699   uint16_t uhMask;
00700
00701   if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
00702   {
00703     if((pData == NULL ) || (Size == 0))
00704     {
00705       return  HAL_ERROR;
00706     }
00707
00708     /* Process Locked */
00709     __HAL_LOCK(huart);
00710
00711     huart->ErrorCode = HAL_UART_ERROR_NONE;
00712     /* Check if a non-blocking transmit process is ongoing or not */
00713     if(huart->State == HAL_UART_STATE_BUSY_TX)
00714     {
00715       huart->State = HAL_UART_STATE_BUSY_TX_RX;
00716     }
00717     else
00718     {
00719       huart->State = HAL_UART_STATE_BUSY_RX;
00720     }
00721
00722     huart->RxXferSize = Size;
00723     huart->RxXferCount = Size;
00724
00725     /* Computation of UART mask to apply to RDR register */
00726     UART_MASK_COMPUTATION(huart);
00727     uhMask = huart->Mask;
00728
00729     /* as long as data have to be received */
00730     while(huart->RxXferCount > 0)
00731     {
00732       huart->RxXferCount--;
00733         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00734         {
00735           return HAL_TIMEOUT;
00736         }
00737       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00738       {
00739         tmp = (uint16_t*) pData ;
00740         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
00741         pData +=2;
00742       }
00743       else
00744       {
00745         *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
00746       }
00747     }
00748
00749     /* Check if a non-blocking transmit Process is ongoing or not */
00750     if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
00751     {
00752       huart->State = HAL_UART_STATE_BUSY_TX;
00753     }
00754     else
00755     {
00756       huart->State = HAL_UART_STATE_READY;
00757     }
00758     /* Process Unlocked */
00759     __HAL_UNLOCK(huart);
00760
00761     return HAL_OK;
00762   }
00763   else
00764   {
00765     return HAL_BUSY;
00766   }
00767 }
00768
00769 /**
00770   * @brief Send an amount of data in interrupt mode
00771   * @param huart: uart handle
00772   * @param pData: pointer to data buffer
00773   * @param Size: amount of data to be sent
00774   * @retval HAL status
00775   */
00776 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00777 {
00778   if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
00779   {
00780     if((pData == NULL ) || (Size == 0))
00781     {
00782       return HAL_ERROR;
00783     }
00784
00785     /* Process Locked */
00786     __HAL_LOCK(huart);
00787
00788     huart->pTxBuffPtr = pData;
00789     huart->TxXferSize = Size;
00790     huart->TxXferCount = Size;
00791
00792     huart->ErrorCode = HAL_UART_ERROR_NONE;
00793     /* Check if a receive process is ongoing or not */
00794     if(huart->State == HAL_UART_STATE_BUSY_RX)
00795     {
00796       huart->State = HAL_UART_STATE_BUSY_TX_RX;
00797     }
00798     else
00799     {
00800       huart->State = HAL_UART_STATE_BUSY_TX;
00801     }
00802
00803     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00804     __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
00805
00806     /* Process Unlocked */
00807     __HAL_UNLOCK(huart);
00808
00809     /* Enable the UART Transmit Data Register Empty Interrupt */
00810     __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
00811
00812     return HAL_OK;
00813   }
00814   else
00815   {
00816     return HAL_BUSY;
00817   }
00818 }
00819
00820 /**
00821   * @brief Receive an amount of data in interrupt mode
00822   * @param huart: uart handle
00823   * @param pData: pointer to data buffer
00824   * @param Size: amount of data to be received
00825   * @retval HAL status
00826   */
00827 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00828 {
00829   if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
00830   {
00831     if((pData == NULL ) || (Size == 0))
00832     {
00833       return HAL_ERROR;
00834     }
00835
00836     /* Process Locked */
00837     __HAL_LOCK(huart);
00838
00839     huart->pRxBuffPtr = pData;
00840     huart->RxXferSize = Size;
00841     huart->RxXferCount = Size;
00842
00843     /* Computation of UART mask to apply to RDR register */
00844     UART_MASK_COMPUTATION(huart);
00845
00846     huart->ErrorCode = HAL_UART_ERROR_NONE;
00847     /* Check if a transmit process is ongoing or not */
00848     if(huart->State == HAL_UART_STATE_BUSY_TX)
00849     {
00850       huart->State = HAL_UART_STATE_BUSY_TX_RX;
00851     }
00852     else
00853     {
00854       huart->State = HAL_UART_STATE_BUSY_RX;
00855     }
00856
00857     /* Enable the UART Parity Error Interrupt */
00858     __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
00859
00860     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00861     __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
00862
00863     /* Process Unlocked */
00864     __HAL_UNLOCK(huart);
00865
00866     /* Enable the UART Data Register not empty Interrupt */
00867     __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
00868
00869     return HAL_OK;
00870   }
00871   else
00872   {
00873     return HAL_BUSY;
00874   }
00875 }
00876
00877 /**
00878   * @brief Send an amount of data in DMA mode
00879   * @param huart: uart handle
00880   * @param pData: pointer to data buffer
00881   * @param Size: amount of data to be sent
00882   * @retval HAL status
00883   */
00884 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00885 {
00886   uint32_t *tmp;
00887
00888   if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
00889   {
00890     if((pData == NULL ) || (Size == 0))
00891     {
00892       return HAL_ERROR;
00893     }
00894
00895     /* Process Locked */
00896     __HAL_LOCK(huart);
00897
00898     huart->pTxBuffPtr = pData;
00899     huart->TxXferSize = Size;
00900     huart->TxXferCount = Size;
00901
00902     huart->ErrorCode = HAL_UART_ERROR_NONE;
00903     /* Check if a receive process is ongoing or not */
00904     if(huart->State == HAL_UART_STATE_BUSY_RX)
00905     {
00906       huart->State = HAL_UART_STATE_BUSY_TX_RX;
00907     }
00908     else
00909     {
00910       huart->State = HAL_UART_STATE_BUSY_TX;
00911     }
00912
00913     /* Set the UART DMA transfer complete callback */
00914     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
00915
00916     /* Set the UART DMA Half transfer complete callback */
00917     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
00918
00919     /* Set the DMA error callback */
00920     huart->hdmatx->XferErrorCallback = UART_DMAError;
00921
00922     /* Enable the UART transmit DMA channel */
00923     tmp = (uint32_t*)&pData;
00924     HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
00925
00926     /* Clear the TC flag in the SR register by writing 0 to it */
00927     __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);
00928
00929
00930     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00931        in the UART CR3 register */
00932     huart->Instance->CR3 |= USART_CR3_DMAT;
00933
00934     /* Process Unlocked */
00935     __HAL_UNLOCK(huart);
00936
00937     return HAL_OK;
00938   }
00939   else
00940   {
00941     return HAL_BUSY;
00942   }
00943 }
00944
00945 /**
00946   * @brief Receive an amount of data in DMA mode
00947   * @param huart: uart handle
00948   * @param pData: pointer to data buffer
00949   * @param Size: amount of data to be received
00950   * @note   When the UART parity is enabled (PCE = 1), the received data contain
00951   *         the parity bit (MSB position)
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00955 {
00956   uint32_t *tmp;
00957
00958   if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
00959   {
00960     if((pData == NULL ) || (Size == 0))
00961     {
00962       return HAL_ERROR;
00963     }
00964
00965     /* Process Locked */
00966     __HAL_LOCK(huart);
00967
00968     huart->pRxBuffPtr = pData;
00969     huart->RxXferSize = Size;
00970
00971     huart->ErrorCode = HAL_UART_ERROR_NONE;
00972     /* Check if a transmit process is ongoing or not */
00973     if(huart->State == HAL_UART_STATE_BUSY_TX)
00974     {
00975       huart->State = HAL_UART_STATE_BUSY_TX_RX;
00976     }
00977     else
00978     {
00979       huart->State = HAL_UART_STATE_BUSY_RX;
00980     }
00981
00982     /* Set the UART DMA transfer complete callback */
00983     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
00984
00985     /* Set the UART DMA Half transfer complete callback */
00986     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
00987
00988     /* Set the DMA error callback */
00989     huart->hdmarx->XferErrorCallback = UART_DMAError;
00990
00991     /* Enable the DMA channel */
00992     tmp = (uint32_t*)&pData;
00993     HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
00994
00995     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00996        in the UART CR3 register */
00997      huart->Instance->CR3 |= USART_CR3_DMAR;
00998
00999      /* Process Unlocked */
01000      __HAL_UNLOCK(huart);
01001
01002     return HAL_OK;
01003   }
01004   else
01005   {
01006     return HAL_BUSY;
01007   }
01008 }
01009
01010 /**
01011   * @brief Pauses the DMA Transfer.
01012   * @param huart: UART handle
01013   * @retval None
01014   */
01015 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01016 {
01017   /* Process Locked */
01018   __HAL_LOCK(huart);
01019
01020   if(huart->State == HAL_UART_STATE_BUSY_TX)
01021   {
01022     /* Disable the UART DMA Tx request */
01023     huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
01024   }
01025   else if(huart->State == HAL_UART_STATE_BUSY_RX)
01026   {
01027     /* Disable the UART DMA Rx request */
01028     huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
01029   }
01030   else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
01031   {
01032     /* Disable the UART DMA Tx request */
01033     huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
01034     /* Disable the UART DMA Rx request */
01035     huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
01036   }
01037
01038   /* Process Unlocked */
01039   __HAL_UNLOCK(huart);
01040
01041   return HAL_OK;
01042 }
01043
01044 /**
01045   * @brief Resumes the DMA Transfer.
01046   * @param huart: UART handle
01047   * @retval None
01048   */
01049 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01050 {
01051   /* Process Locked */
01052   __HAL_LOCK(huart);
01053
01054   if(huart->State == HAL_UART_STATE_BUSY_TX)
01055   {
01056     /* Enable the UART DMA Tx request */
01057     huart->Instance->CR3 |= USART_CR3_DMAT;
01058   }
01059   else if(huart->State == HAL_UART_STATE_BUSY_RX)
01060   {
01061                 /* Clear the Overrun flag before resuming the Rx transfer*/
01062     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
01063
01064     /* Enable the UART DMA Rx request */
01065     huart->Instance->CR3 |= USART_CR3_DMAR;
01066   }
01067   else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
01068   {
01069                 /* Clear the Overrun flag before resuming the Rx transfer*/
01070     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
01071
01072     /* Enable the UART DMA Rx request  before the DMA Tx request */
01073     huart->Instance->CR3 |= USART_CR3_DMAR;
01074
01075     /* Enable the UART DMA Tx request */
01076     huart->Instance->CR3 |= USART_CR3_DMAT;
01077   }
01078
01079   /* If the UART peripheral is still not enabled, enable it */
01080   if ((huart->Instance->CR1 & USART_CR1_UE) == 0)
01081   {
01082     /* Enable UART peripheral */
01083     __HAL_UART_ENABLE(huart);
01084   }
01085
01086   return HAL_OK;
01087 }
01088
01089 /**
01090   * @brief Stops the DMA Transfer.
01091   * @param huart: UART handle
01092   * @retval None
01093   */
01094 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01095 {
01096   /* The Lock is not implemented on this API to allow the user application
01097      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01098      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01099      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01100      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01101      the stream and the corresponding call back is executed. */
01102
01103   /* Disable the UART Tx/Rx DMA requests */
01104   huart->Instance->CR3 &= ~USART_CR3_DMAT;
01105   huart->Instance->CR3 &= ~USART_CR3_DMAR;
01106
01107   /* Abort the UART DMA tx channel */
01108   if(huart->hdmatx != NULL)
01109   {
01110     HAL_DMA_Abort(huart->hdmatx);
01111   }
01112   /* Abort the UART DMA rx channel */
01113   if(huart->hdmarx != NULL)
01114   {
01115     HAL_DMA_Abort(huart->hdmarx);
01116   }
01117
01118   huart->State = HAL_UART_STATE_READY;
01119
01120   return HAL_OK;
01121 }
01122
01123 /**
01124   * @brief This function handles UART interrupt request.
01125   * @param huart: uart handle
01126   * @retval None
01127   */
01128 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
01129 {
01130   /* UART parity error interrupt occurred -------------------------------------*/
01131   if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
01132   {
01133                 __HAL_UART_CLEAR_PEFLAG(huart);
01134
01135     huart->ErrorCode |= HAL_UART_ERROR_PE;
01136     /* Set the UART state ready to be able to start again the process */
01137     huart->State = HAL_UART_STATE_READY;
01138   }
01139
01140   /* UART frame error interrupt occurred --------------------------------------*/
01141   if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
01142   {
01143     __HAL_UART_CLEAR_FEFLAG(huart);
01144
01145     huart->ErrorCode |= HAL_UART_ERROR_FE;
01146     /* Set the UART state ready to be able to start again the process */
01147     huart->State = HAL_UART_STATE_READY;
01148   }
01149
01150   /* UART noise error interrupt occurred --------------------------------------*/
01151   if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
01152   {
01153     __HAL_UART_CLEAR_NEFLAG(huart);
01154
01155     huart->ErrorCode |= HAL_UART_ERROR_NE;
01156     /* Set the UART state ready to be able to start again the process */
01157     huart->State = HAL_UART_STATE_READY;
01158   }
01159
01160   /* UART Over-Run interrupt occurred -----------------------------------------*/
01161   if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
01162   {
01163     __HAL_UART_CLEAR_OREFLAG(huart);
01164
01165     huart->ErrorCode |= HAL_UART_ERROR_ORE;
01166     /* Set the UART state ready to be able to start again the process */
01167     huart->State = HAL_UART_STATE_READY;
01168   }
01169
01170    /* Call UART Error Call back function if need be --------------------------*/
01171   if(huart->ErrorCode != HAL_UART_ERROR_NONE)
01172   {
01173     HAL_UART_ErrorCallback(huart);
01174   }
01175
01176   /* UART in mode Receiver ---------------------------------------------------*/
01177   if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
01178   {
01179     UART_Receive_IT(huart);
01180     /* Clear RXNE interrupt flag */
01181     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01182   }
01183
01184
01185   /* UART in mode Transmitter ------------------------------------------------*/
01186  if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
01187   {
01188     UART_Transmit_IT(huart);
01189   }
01190
01191   /* UART in mode Transmitter (transmission end) -----------------------------*/
01192  if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
01193   {
01194     UART_EndTransmit_IT(huart);
01195   }
01196
01197 }
01198
01199
01200 /**
01201   * @brief  This function handles UART Communication Timeout.
01202   * @param  huart: UART handle
01203   * @param  Flag: specifies the UART flag to check.
01204   * @param  Status: The new Flag status (SET or RESET).
01205   * @param  Timeout: Timeout duration
01206   * @retval HAL status
01207   */
01208 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01209 {
01210   uint32_t tickstart = HAL_GetTick();
01211
01212   /* Wait until flag is set */
01213   if(Status == RESET)
01214   {
01215     while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
01216     {
01217       /* Check for the Timeout */
01218       if(Timeout != HAL_MAX_DELAY)
01219       {
01220         if((Timeout == 0)||((HAL_GetTick()-tickstart) >=  Timeout))
01221         {
01222           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01223           __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
01224           __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
01225           __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
01226           __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
01227
01228           huart->State= HAL_UART_STATE_READY;
01229
01230           /* Process Unlocked */
01231           __HAL_UNLOCK(huart);
01232
01233           return HAL_TIMEOUT;
01234         }
01235       }
01236     }
01237   }
01238   else
01239   {
01240     while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
01241     {
01242       /* Check for the Timeout */
01243       if(Timeout != HAL_MAX_DELAY)
01244       {
01245         if((Timeout == 0)||((HAL_GetTick()-tickstart) >=  Timeout))
01246         {
01247           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01248           __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
01249           __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
01250           __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
01251           __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
01252
01253           huart->State= HAL_UART_STATE_READY;
01254
01255           /* Process Unlocked */
01256           __HAL_UNLOCK(huart);
01257
01258           return HAL_TIMEOUT;
01259         }
01260       }
01261     }
01262   }
01263   return HAL_OK;
01264 }
01265
01266
01267
01268 /**
01269   * @brief DMA UART transmit process complete callback
01270   * @param hdma: DMA handle
01271   * @retval None
01272   */
01273 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01274 {
01275   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01276
01277   /* DMA Normal mode*/
01278   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01279   {
01280     huart->TxXferCount = 0;
01281
01282     /* Disable the DMA transfer for transmit request by setting the DMAT bit
01283        in the UART CR3 register */
01284     huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
01285
01286     /* Enable the UART Transmit Complete Interrupt */
01287     __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
01288   }
01289   /* DMA Circular mode */
01290   else
01291   {
01292     HAL_UART_TxCpltCallback(huart);
01293   }
01294 }
01295
01296 /**
01297   * @brief DMA UART transmit process half complete callback
01298   * @param hdma : DMA handle
01299   * @retval None
01300   */
01301 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01302 {
01303   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01304
01305   HAL_UART_TxHalfCpltCallback(huart);
01306 }
01307
01308 /**
01309   * @brief DMA UART receive process complete callback
01310   * @param hdma: DMA handle
01311   * @retval None
01312   */
01313 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01314 {
01315   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01316
01317   /* DMA Normal mode */
01318   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01319   {
01320     huart->RxXferCount = 0;
01321
01322     /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01323     in the UART CR3 register */
01324     huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
01325
01326     /* Check if a transmit Process is ongoing or not */
01327     if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
01328     {
01329       huart->State = HAL_UART_STATE_BUSY_TX;
01330     }
01331     else
01332     {
01333       huart->State = HAL_UART_STATE_READY;
01334     }
01335   }
01336   HAL_UART_RxCpltCallback(huart);
01337 }
01338
01339 /**
01340   * @brief DMA UART receive process half complete callback
01341   * @param hdma : DMA handle
01342   * @retval None
01343   */
01344 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01345 {
01346   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01347
01348   HAL_UART_RxHalfCpltCallback(huart);
01349 }
01350
01351 /**
01352   * @brief DMA UART communication error callback
01353   * @param hdma: DMA handle
01354   * @retval None
01355   */
01356 static void UART_DMAError(DMA_HandleTypeDef *hdma)
01357 {
01358   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01359   huart->RxXferCount = 0;
01360   huart->TxXferCount = 0;
01361   huart->State= HAL_UART_STATE_READY;
01362   huart->ErrorCode |= HAL_UART_ERROR_DMA;
01363   HAL_UART_ErrorCallback(huart);
01364 }
01365
01366 /**
01367   * @brief Tx Transfer completed callbacks
01368   * @param huart: uart handle
01369   * @retval None
01370   */
01371  __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
01372 {
01373   /* Prevent unused argument(s) compilation warning */
01374   UNUSED(huart);
01375
01376   /* NOTE : This function should not be modified, when the callback is needed,
01377             the HAL_UART_TxCpltCallback can be implemented in the user file
01378    */
01379 }
01380
01381 /**
01382   * @brief  Tx Half Transfer completed callbacks.
01383   * @param  huart: UART handle
01384   * @retval None
01385   */
01386  __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
01387 {
01388   /* Prevent unused argument(s) compilation warning */
01389   UNUSED(huart);
01390
01391   /* NOTE: This function should not be modified, when the callback is needed,
01392            the HAL_UART_TxHalfCpltCallback can be implemented in the user file
01393    */
01394 }
01395
01396 /**
01397   * @brief Rx Transfer completed callbacks
01398   * @param huart: uart handle
01399   * @retval None
01400   */
01401 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
01402 {
01403   /* Prevent unused argument(s) compilation warning */
01404   UNUSED(huart);
01405
01406   /* NOTE : This function should not be modified, when the callback is needed,
01407             the HAL_UART_RxCpltCallback can be implemented in the user file
01408    */
01409 }
01410
01411 /**
01412   * @brief  Rx Half Transfer completed callbacks.
01413   * @param  huart: UART handle
01414   * @retval None
01415   */
01416 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
01417 {
01418   /* Prevent unused argument(s) compilation warning */
01419   UNUSED(huart);
01420
01421   /* NOTE: This function should not be modified, when the callback is needed,
01422            the HAL_UART_RxHalfCpltCallback can be implemented in the user file
01423    */
01424 }
01425
01426 /**
01427   * @brief UART error callbacks
01428   * @param huart: uart handle
01429   * @retval None
01430   */
01431  __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
01432 {
01433   /* Prevent unused argument(s) compilation warning */
01434   UNUSED(huart);
01435
01436   /* NOTE : This function should not be modified, when the callback is needed,
01437             the HAL_UART_ErrorCallback can be implemented in the user file
01438    */
01439 }
01440
01441 /**
01442   * @brief Send an amount of data in interrupt mode
01443   *         Function called under interruption only, once
01444   *         interruptions have been enabled by HAL_UART_Transmit_IT()
01445   * @param  huart: UART handle
01446   * @retval HAL status
01447   */
01448 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
01449 {
01450   uint16_t* tmp;
01451
01452   if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
01453   {
01454
01455     if(huart->TxXferCount == 0)
01456     {
01457       /* Disable the UART Transmit Data Register Empty Interrupt */
01458       __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
01459
01460       /* Check if a receive Process is ongoing or not */
01461       if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
01462       {
01463         huart->State = HAL_UART_STATE_BUSY_RX;
01464       }
01465       else
01466       {
01467         huart->State = HAL_UART_STATE_READY;
01468       }
01469
01470       /* Wait on TC flag to be able to start a second transfer */
01471       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
01472       {
01473         return HAL_TIMEOUT;
01474       }
01475
01476       HAL_UART_TxCpltCallback(huart);
01477
01478       return HAL_OK;
01479     }
01480     else
01481     {
01482       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01483       {
01484         tmp = (uint16_t*) huart->pTxBuffPtr;
01485         huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
01486         huart->pTxBuffPtr += 2;
01487       }
01488       else
01489       {
01490         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
01491       }
01492
01493       huart->TxXferCount--;
01494
01495       return HAL_OK;
01496     }
01497   }
01498   else
01499   {
01500     return HAL_BUSY;
01501   }
01502 }
01503
01504 /**
01505   * @brief  Wrap up transmission in non-blocking mode.
01506   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01507   *                the configuration information for the specified UART module.
01508   * @retval HAL status
01509   */
01510 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
01511 {
01512   /* Disable the UART Transmit Complete Interrupt */
01513   __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
01514
01515   /* Check if a receive process is ongoing or not */
01516   if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
01517   {
01518     huart->State = HAL_UART_STATE_BUSY_RX;
01519   }
01520   else
01521   {
01522     huart->State = HAL_UART_STATE_READY;
01523   }
01524
01525   HAL_UART_TxCpltCallback(huart);
01526
01527   return HAL_OK;
01528 }
01529
01530 /**
01531   * @brief Receive an amount of data in interrupt mode
01532   *         Function called under interruption only, once
01533   *         interruptions have been enabled by HAL_UART_Receive_IT()
01534   * @param  huart: UART handle
01535   * @retval HAL status
01536   */
01537 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
01538 {
01539   uint16_t* tmp;
01540   uint16_t uhMask = huart->Mask;
01541
01542   if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
01543   {
01544
01545     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01546     {
01547       tmp = (uint16_t*) huart->pRxBuffPtr ;
01548       *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
01549       huart->pRxBuffPtr +=2;
01550     }
01551     else
01552     {
01553       *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
01554     }
01555
01556     if(--huart->RxXferCount == 0)
01557     {
01558       __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
01559
01560       /* Check if a transmit Process is ongoing or not */
01561       if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
01562       {
01563         huart->State = HAL_UART_STATE_BUSY_TX;
01564       }
01565       else
01566       {
01567         /* Disable the UART Parity Error Interrupt */
01568         __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
01569
01570         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01571         __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
01572
01573         huart->State = HAL_UART_STATE_READY;
01574       }
01575
01576       HAL_UART_RxCpltCallback(huart);
01577
01578       return HAL_OK;
01579     }
01580
01581     return HAL_OK;
01582   }
01583   else
01584   {
01585     return HAL_BUSY;
01586   }
01587 }
01588
01589 /**
01590   * @}
01591   */
01592
01593 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
01594   *  @brief   UART control functions
01595   *
01596 @verbatim
01597  ===============================================================================
01598                       ##### Peripheral Control functions #####
01599  ===============================================================================
01600     [..]
01601     This subsection provides a set of functions allowing to control the UART.
01602      (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
01603      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
01604      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
01605      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
01606      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
01607      (+) UART_SetConfig() API configures the UART peripheral
01608      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
01609      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
01610      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
01611      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
01612      (+) HAL_LIN_SendBreak() API transmits the break characters
01613 @endverbatim
01614   * @{
01615   */
01616
01617 /**
01618   * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;
01619   * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
01620   * @param huart: UART handle
01621   * @retval HAL status
01622   */
01623 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
01624 {
01625   /* Process Locked */
01626   __HAL_LOCK(huart);
01627
01628   huart->State = HAL_UART_STATE_BUSY;
01629
01630   /* Enable USART mute mode by setting the MME bit in the CR1 register */
01631   huart->Instance->CR1 |= USART_CR1_MME;
01632
01633   huart->State = HAL_UART_STATE_READY;
01634
01635   return (UART_CheckIdleState(huart));
01636 }
01637
01638 /**
01639   * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,
01640   * as it may not have been in mute mode at this very moment).
01641   * @param huart: uart handle
01642   * @retval HAL status
01643   */
01644 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
01645 {
01646   /* Process Locked */
01647   __HAL_LOCK(huart);
01648
01649   huart->State = HAL_UART_STATE_BUSY;
01650
01651    /* Disable USART mute mode by clearing the MME bit in the CR1 register */
01652   huart->Instance->CR1 &= ~(USART_CR1_MME);
01653
01654   huart->State = HAL_UART_STATE_READY;
01655
01656   return (UART_CheckIdleState(huart));
01657 }
01658
01659 /**
01660   * @brief Enter UART mute mode (means UART actually enters mute mode).
01661   * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
01662   * @param huart: uart handle
01663   * @retval HAL status
01664   */
01665 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
01666 {
01667   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
01668 }
01669
01670
01671
01672 /**
01673   * @brief return the UART state
01674   * @param huart: uart handle
01675   * @retval HAL state
01676   */
01677 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
01678 {
01679   return huart->State;
01680 }
01681
01682 /**
01683 * @brief  Return the UART error code
01684 * @param  huart : pointer to a UART_HandleTypeDef structure that contains
01685   *              the configuration information for the specified UART.
01686 * @retval UART Error Code
01687 */
01688 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
01689 {
01690   return huart->ErrorCode;
01691 }
01692
01693 /**
01694   * @brief Configure the UART peripheral
01695   * @param huart: uart handle
01696   * @retval None
01697   */
01698 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
01699 {
01700   uint32_t tmpreg                     = 0x00000000;
01701   UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
01702   uint16_t brrtemp                    = 0x0000;
01703   uint16_t usartdiv                   = 0x0000;
01704   HAL_StatusTypeDef ret               = HAL_OK;
01705
01706   /* Check the parameters */
01707   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
01708   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
01709   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
01710   assert_param(IS_UART_PARITY(huart->Init.Parity));
01711   assert_param(IS_UART_MODE(huart->Init.Mode));
01712   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
01713   assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
01714
01715
01716   /*-------------------------- USART CR1 Configuration -----------------------*/
01717   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
01718    *  the UART Word Length, Parity, Mode and oversampling:
01719    *  set the M bits according to huart->Init.WordLength value
01720    *  set PCE and PS bits according to huart->Init.Parity value
01721    *  set TE and RE bits according to huart->Init.Mode value
01722    *  set OVER8 bit according to huart->Init.OverSampling value */
01723   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
01724   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
01725
01726   /*-------------------------- USART CR2 Configuration -----------------------*/
01727   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
01728    * to huart->Init.StopBits value */
01729   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
01730
01731   /*-------------------------- USART CR3 Configuration -----------------------*/
01732   /* Configure
01733    * - UART HardWare Flow Control: set CTSE and RTSE bits according
01734    *   to huart->Init.HwFlowCtl value
01735    * - one-bit sampling method versus three samples' majority rule according
01736    *   to huart->Init.OneBitSampling */
01737   tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
01738   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
01739
01740   /*-------------------------- USART BRR Configuration -----------------------*/
01741   UART_GETCLOCKSOURCE(huart, clocksource);
01742
01743   /* Check UART Over Sampling to set Baud Rate Register */
01744   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
01745   {
01746     switch (clocksource)
01747     {
01748     case UART_CLOCKSOURCE_PCLK1:
01749         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
01750       break;
01751     case UART_CLOCKSOURCE_PCLK2:
01752         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
01753       break;
01754     case UART_CLOCKSOURCE_HSI:
01755         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
01756       break;
01757     case UART_CLOCKSOURCE_SYSCLK:
01758         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
01759       break;
01760     case UART_CLOCKSOURCE_LSE:
01761         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
01762       break;
01763       case UART_CLOCKSOURCE_UNDEFINED:
01764     default:
01765         ret = HAL_ERROR;
01766       break;
01767     }
01768
01769     brrtemp = usartdiv & 0xFFF0;
01770     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
01771     huart->Instance->BRR = brrtemp;
01772   }
01773   else
01774   {
01775     switch (clocksource)
01776     {
01777     case UART_CLOCKSOURCE_PCLK1:
01778         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
01779       break;
01780     case UART_CLOCKSOURCE_PCLK2:
01781         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
01782       break;
01783     case UART_CLOCKSOURCE_HSI:
01784         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
01785       break;
01786     case UART_CLOCKSOURCE_SYSCLK:
01787         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
01788       break;
01789     case UART_CLOCKSOURCE_LSE:
01790         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
01791       break;
01792       case UART_CLOCKSOURCE_UNDEFINED:
01793     default:
01794         ret = HAL_ERROR;
01795       break;
01796     }
01797   }
01798
01799   return ret;
01800
01801 }
01802
01803
01804 /**
01805   * @brief Configure the UART peripheral advanced features
01806   * @param huart: uart handle
01807   * @retval None
01808   */
01809 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
01810 {
01811   /* Check whether the set of advanced features to configure is properly set */
01812   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
01813
01814   /* if required, configure TX pin active level inversion */
01815   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
01816   {
01817     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
01818     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
01819   }
01820
01821   /* if required, configure RX pin active level inversion */
01822   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
01823   {
01824     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
01825     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
01826   }
01827
01828   /* if required, configure data inversion */
01829   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
01830   {
01831     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
01832     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
01833   }
01834
01835   /* if required, configure RX/TX pins swap */
01836   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
01837   {
01838     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
01839     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
01840   }
01841
01842   /* if required, configure RX overrun detection disabling */
01843   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
01844   {
01845     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
01846     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
01847   }
01848
01849   /* if required, configure DMA disabling on reception error */
01850   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
01851   {
01852     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
01853     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
01854   }
01855
01856   /* if required, configure auto Baud rate detection scheme */
01857   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
01858   {
01859     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
01860     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
01861     /* set auto Baudrate detection parameters if detection is enabled */
01862     if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
01863     {
01864       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
01865       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
01866     }
01867   }
01868
01869   /* if required, configure MSB first on communication line */
01870   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
01871   {
01872     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
01873     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
01874   }
01875 }
01876
01877
01878
01879 /**
01880   * @brief Check the UART Idle State
01881   * @param huart: uart handle
01882   * @retval HAL status
01883   */
01884 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
01885 {
01886   /* Initialize the UART ErrorCode */
01887   huart->ErrorCode = HAL_UART_ERROR_NONE;
01888
01889   /* Check if the Transmitter is enabled */
01890   if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01891   {
01892     /* Wait until TEACK flag is set */
01893     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
01894     {
01895       /* Timeout Occurred */
01896       return HAL_TIMEOUT;
01897     }
01898   }
01899   /* Check if the Receiver is enabled */
01900   if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01901   {
01902     /* Wait until REACK flag is set */
01903     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET,  HAL_UART_TIMEOUT_VALUE) != HAL_OK)
01904     {
01905       /* Timeout Occurred */
01906       return HAL_TIMEOUT;
01907     }
01908   }
01909
01910   /* Initialize the UART State */
01911   huart->State= HAL_UART_STATE_READY;
01912
01913   /* Process Unlocked */
01914   __HAL_UNLOCK(huart);
01915
01916   return HAL_OK;
01917 }
01918
01919 /**
01920   * @brief  Enables the UART transmitter and disables the UART receiver.
01921   * @param  huart: UART handle
01922   * @retval HAL status
01923   * @retval None
01924   */
01925 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
01926 {
01927   /* Process Locked */
01928   __HAL_LOCK(huart);
01929   huart->State = HAL_UART_STATE_BUSY;
01930
01931   /* Clear TE and RE bits */
01932   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01933   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
01934   SET_BIT(huart->Instance->CR1, USART_CR1_TE);
01935
01936   huart->State= HAL_UART_STATE_READY;
01937   /* Process Unlocked */
01938   __HAL_UNLOCK(huart);
01939
01940   return HAL_OK;
01941 }
01942
01943 /**
01944   * @brief  Enables the UART receiver and disables the UART transmitter.
01945   * @param  huart: UART handle
01946   * @retval HAL status
01947   */
01948 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
01949 {
01950   /* Process Locked */
01951   __HAL_LOCK(huart);
01952   huart->State = HAL_UART_STATE_BUSY;
01953
01954   /* Clear TE and RE bits */
01955   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01956   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
01957   SET_BIT(huart->Instance->CR1, USART_CR1_RE);
01958
01959   huart->State = HAL_UART_STATE_READY;
01960   /* Process Unlocked */
01961   __HAL_UNLOCK(huart);
01962
01963   return HAL_OK;
01964 }
01965
01966
01967 /**
01968   * @brief  Transmits break characters.
01969   * @param  huart: UART handle
01970   * @retval HAL status
01971   */
01972 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
01973 {
01974   /* Check the parameters */
01975   assert_param(IS_UART_INSTANCE(huart->Instance));
01976
01977   /* Process Locked */
01978   __HAL_LOCK(huart);
01979
01980   huart->State = HAL_UART_STATE_BUSY;
01981
01982   /* Send break characters */
01983   huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
01984
01985   huart->State = HAL_UART_STATE_READY;
01986
01987   /* Process Unlocked */
01988   __HAL_UNLOCK(huart);
01989
01990   return HAL_OK;
01991 }
01992
01993
01994 /**
01995   * @}
01996   */
01997
01998 /**
01999   * @}
02000   */
02001
02002 #endif /* HAL_UART_MODULE_ENABLED */
02003 /**
02004   * @}
02005   */
02006
02007 /**
02008   * @}
02009   */
02010
02011 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_uart.h Source File

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stm32f7xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of UART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_UART_H
00040 #define __STM32F7xx_HAL_UART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UART_Exported_Types UART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief UART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                            - If oversampling is 16 or in LIN mode,
00070                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
00071                                            - If oversampling is 8,
00072                                               Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
00073                                               Baud Rate Register[3] =  0
00074                                               Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
00075
00076   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00077                                            This parameter can be a value of @ref UARTEx_Word_Length */
00078
00079   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00080                                            This parameter can be a value of @ref UART_Stop_Bits */
00081
00082   uint32_t Parity;                    /*!< Specifies the parity mode.
00083                                            This parameter can be a value of @ref UART_Parity
00084                                            @note When parity is enabled, the computed parity is inserted
00085                                                  at the MSB position of the transmitted data (9th bit when
00086                                                  the word length is set to 9 data bits; 8th bit when the
00087                                                  word length is set to 8 data bits). */
00088
00089   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00090                                            This parameter can be a value of @ref UART_Mode */
00091
00092   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00093                                            or disabled.
00094                                            This parameter can be a value of @ref UART_Hardware_Flow_Control */
00095
00096   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
00097                                            This parameter can be a value of @ref UART_Over_Sampling */
00098
00099   uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00100                                            Selecting the single sample method increases the receiver tolerance to clock
00101                                            deviations. This parameter can be a value of @ref UART_OneBit_Sampling */
00102 }UART_InitTypeDef;
00103
00104 /**
00105   * @brief  UART Advanced Features initialization structure definition
00106   */
00107 typedef struct
00108 {
00109   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00110                                        Advanced Features may be initialized at the same time .
00111                                        This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
00112
00113   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00114                                        This parameter can be a value of @ref UART_Tx_Inv  */
00115
00116   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00117                                        This parameter can be a value of @ref UART_Rx_Inv  */
00118
00119   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00120                                        vs negative/inverted logic).
00121                                        This parameter can be a value of @ref UART_Data_Inv */
00122
00123   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00124                                        This parameter can be a value of @ref UART_Rx_Tx_Swap */
00125
00126   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00127                                        This parameter can be a value of @ref UART_Overrun_Disable */
00128
00129   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00130                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
00131
00132   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00133                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable */
00134
00135   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00136                                        detection is carried out.
00137                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
00138
00139   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00140                                        This parameter can be a value of @ref UART_MSB_First */
00141 } UART_AdvFeatureInitTypeDef;
00142
00143
00144
00145 /**
00146   * @brief HAL UART State structures definition
00147   */
00148 typedef enum
00149 {
00150   HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                      */
00151   HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
00152   HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
00153   HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
00154   HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
00155   HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00156   HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
00157   HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */
00158 }HAL_UART_StateTypeDef;
00159
00160 /**
00161   * @brief UART clock sources definition
00162   */
00163 typedef enum
00164 {
00165   UART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source  */
00166   UART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source  */
00167   UART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source    */
00168   UART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source */
00169   UART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
00170   UART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
00171 }UART_ClockSourceTypeDef;
00172
00173 /**
00174   * @brief  UART handle Structure definition
00175   */
00176 typedef struct
00177 {
00178   USART_TypeDef            *Instance;        /*!< UART registers base address        */
00179
00180   UART_InitTypeDef         Init;             /*!< UART communication parameters      */
00181
00182   UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
00183
00184   uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
00185
00186   uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
00187
00188   uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
00189
00190   uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
00191
00192   uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
00193
00194   uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
00195
00196   uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
00197
00198   DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
00199
00200   DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
00201
00202   HAL_LockTypeDef           Lock;            /*!< Locking object                     */
00203
00204   __IO HAL_UART_StateTypeDef    State;       /*!< UART communication state           */
00205
00206   __IO uint32_t             ErrorCode;   /*!< UART Error code                    */
00207
00208 }UART_HandleTypeDef;
00209
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported constants --------------------------------------------------------*/
00215 /** @defgroup UART_Exported_Constants UART Exported Constants
00216   * @{
00217   */
00218 /** @defgroup UART_Error_Definition   UART Error Definition
00219   * @{
00220   */
00221 #define  HAL_UART_ERROR_NONE       ((uint32_t)0x00000000)    /*!< No error            */
00222 #define  HAL_UART_ERROR_PE         ((uint32_t)0x00000001)    /*!< Parity error        */
00223 #define  HAL_UART_ERROR_NE         ((uint32_t)0x00000002)    /*!< Noise error         */
00224 #define  HAL_UART_ERROR_FE         ((uint32_t)0x00000004)    /*!< frame error         */
00225 #define  HAL_UART_ERROR_ORE        ((uint32_t)0x00000008)    /*!< Overrun error       */
00226 #define  HAL_UART_ERROR_DMA        ((uint32_t)0x00000010)    /*!< DMA transfer error  */
00227 /**
00228   * @}
00229   */
00230 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00231   * @{
00232   */
00233 #define UART_STOPBITS_1                     ((uint32_t)0x0000)
00234 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup UART_Parity  UART Parity
00240   * @{
00241   */
00242 #define UART_PARITY_NONE                    ((uint32_t)0x00000000)
00243 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00244 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00250   * @{
00251   */
00252 #define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
00253 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
00254 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
00255 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup UART_Mode UART Transfer Mode
00261   * @{
00262   */
00263 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
00264 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
00265 #define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00266 /**
00267   * @}
00268   */
00269
00270  /** @defgroup UART_State  UART State
00271   * @{
00272   */
00273 #define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
00274 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup UART_Over_Sampling UART Over Sampling
00280   * @{
00281   */
00282 #define UART_OVERSAMPLING_16                ((uint32_t)0x00000000)
00283 #define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00289   * @{
00290   */
00291 #define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)
00292 #define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00298   * @{
00299   */
00300 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x0000)
00301 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
00302 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)
00303 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
00309   * @{
00310   */
00311 #define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000)
00312 #define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00318   * @{
00319   */
00320 #define UART_LIN_DISABLE                    ((uint32_t)0x00000000)
00321 #define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00327   * @{
00328   */
00329 #define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000)
00330 #define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup UART_DMA_Tx    UART DMA Tx
00336   * @{
00337   */
00338 #define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000)
00339 #define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup UART_DMA_Rx   UART DMA Rx
00345   * @{
00346   */
00347 #define UART_DMA_RX_DISABLE                 ((uint32_t)0x0000)
00348 #define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00354   * @{
00355   */
00356 #define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x0000)
00357 #define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00363   * @{
00364   */
00365 #define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000)
00366 #define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup UART_Request_Parameters UART Request Parameters
00372   * @{
00373   */
00374 #define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */
00375 #define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request */
00376 #define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request */
00377 #define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */
00378 #define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00384   * @{
00385   */
00386 #define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)
00387 #define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)
00388 #define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)
00389 #define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)
00390 #define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)
00391 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)
00392 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)
00393 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040)
00394 #define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00400   * @{
00401   */
00402 #define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000)
00403 #define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00409   * @{
00410   */
00411 #define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000)
00412 #define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00418   * @{
00419   */
00420 #define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000)
00421 #define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)
00422 /**
00423   * @}
00424   */
00425
00426 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00427   * @{
00428   */
00429 #define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000)
00430 #define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00436   * @{
00437   */
00438 #define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000)
00439 #define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00445   * @{
00446   */
00447 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000)
00448 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00454   * @{
00455   */
00456 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000)
00457 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00463   * @{
00464   */
00465 #define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000)
00466 #define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00472   * @{
00473   */
00474 #define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000)
00475 #define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00481   * @{
00482   */
00483 #define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24)
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00489   * @{
00490   */
00491 #define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000)
00492 #define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00498   * @{
00499   */
00500 #define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21)
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00506   * @{
00507   */
00508 #define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16)
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00514   * @{
00515   */
00516 #define UART_IT_MASK                        ((uint32_t)0x001F)
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00522   * @{
00523   */
00524 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFF
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup UART_Flags     UART Status Flags
00530   *        Elements values convention: 0xXXXX
00531   *           - 0xXXXX  : Flag mask in the ISR register
00532   * @{
00533   */
00534 #define UART_FLAG_TEACK                     ((uint32_t)0x00200000)
00535 #define UART_FLAG_SBKF                      ((uint32_t)0x00040000)
00536 #define UART_FLAG_CMF                       ((uint32_t)0x00020000)
00537 #define UART_FLAG_BUSY                      ((uint32_t)0x00010000)
00538 #define UART_FLAG_ABRF                      ((uint32_t)0x00008000)
00539 #define UART_FLAG_ABRE                      ((uint32_t)0x00004000)
00540 #define UART_FLAG_EOBF                      ((uint32_t)0x00001000)
00541 #define UART_FLAG_RTOF                      ((uint32_t)0x00000800)
00542 #define UART_FLAG_CTS                       ((uint32_t)0x00000400)
00543 #define UART_FLAG_CTSIF                     ((uint32_t)0x00000200)
00544 #define UART_FLAG_LBDF                      ((uint32_t)0x00000100)
00545 #define UART_FLAG_TXE                       ((uint32_t)0x00000080)
00546 #define UART_FLAG_TC                        ((uint32_t)0x00000040)
00547 #define UART_FLAG_RXNE                      ((uint32_t)0x00000020)
00548 #define UART_FLAG_IDLE                      ((uint32_t)0x00000010)
00549 #define UART_FLAG_ORE                       ((uint32_t)0x00000008)
00550 #define UART_FLAG_NE                        ((uint32_t)0x00000004)
00551 #define UART_FLAG_FE                        ((uint32_t)0x00000002)
00552 #define UART_FLAG_PE                        ((uint32_t)0x00000001)
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00558   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00559   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00560   *           - XX  : Interrupt source register (2bits)
00561   *                 - 01: CR1 register
00562   *                 - 10: CR2 register
00563   *                 - 11: CR3 register
00564   *           - ZZZZ  : Flag position in the ISR register(4bits)
00565   * @{
00566   */
00567 #define UART_IT_PE                          ((uint32_t)0x0028)
00568 #define UART_IT_TXE                         ((uint32_t)0x0727)
00569 #define UART_IT_TC                          ((uint32_t)0x0626)
00570 #define UART_IT_RXNE                        ((uint32_t)0x0525)
00571 #define UART_IT_IDLE                        ((uint32_t)0x0424)
00572 #define UART_IT_LBD                         ((uint32_t)0x0846)
00573 #define UART_IT_CTS                         ((uint32_t)0x096A)
00574 #define UART_IT_CM                          ((uint32_t)0x112E)
00575
00576 /**       Elements values convention: 000000000XXYYYYYb
00577   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00578   *           - XX  : Interrupt source register (2bits)
00579   *                 - 01: CR1 register
00580   *                 - 10: CR2 register
00581   *                 - 11: CR3 register
00582   */
00583 #define UART_IT_ERR                         ((uint32_t)0x0060)
00584
00585 /**       Elements values convention: 0000ZZZZ00000000b
00586   *           - ZZZZ  : Flag position in the ISR register(4bits)
00587   */
00588 #define UART_IT_ORE                         ((uint32_t)0x0300)
00589 #define UART_IT_NE                          ((uint32_t)0x0200)
00590 #define UART_IT_FE                          ((uint32_t)0x0100)
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00596   * @{
00597   */
00598 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */
00599 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */
00600 #define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */
00601 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */
00602 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */
00603 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00604 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag */
00605 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */
00606 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */
00607 #define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */
00608 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag */
00609 /**
00610   * @}
00611   */
00612
00613
00614 /**
00615   * @}
00616   */
00617
00618 /* Exported macros -----------------------------------------------------------*/
00619 /** @defgroup UART_Exported_Macros UART Exported Macros
00620   * @{
00621   */
00622
00623 /** @brief Reset UART handle state
00624   * @param  __HANDLE__: UART handle.
00625   * @retval None
00626   */
00627 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
00628
00629 /** @brief  Flush the UART Data registers
00630   * @param  __HANDLE__: specifies the UART Handle.
00631   */
00632 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00633   do{                \
00634       SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00635       SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00636     }  while(0)
00637
00638 /** @brief  Clears the specified UART ISR flag, in setting the proper ICR register flag.
00639   * @param  __HANDLE__: specifies the UART Handle.
00640   * @param  __FLAG__: specifies the interrupt clear register flag that needs to be set
00641   *                       to clear the corresponding interrupt
00642   *          This parameter can be one of the following values:
00643   *            @arg UART_CLEAR_PEF: Parity Error Clear Flag
00644   *            @arg UART_CLEAR_FEF: Framing Error Clear Flag
00645   *            @arg UART_CLEAR_NEF: Noise detected Clear Flag
00646   *            @arg UART_CLEAR_OREF: OverRun Error Clear Flag
00647   *            @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
00648   *            @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
00649   *            @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
00650   *            @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
00651   *            @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
00652   *            @arg UART_CLEAR_EOBF: End Of Block Clear Flag
00653   *            @arg UART_CLEAR_CMF: Character Match Clear Flag
00654   * @retval None
00655   */
00656 #define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
00657
00658 /** @brief  Clear the UART PE pending flag.
00659   * @param  __HANDLE__: specifies the UART Handle.
00660   * @retval None
00661   */
00662 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
00663
00664 /** @brief  Clear the UART FE pending flag.
00665   * @param  __HANDLE__: specifies the UART Handle.
00666   * @retval None
00667   */
00668 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
00669
00670 /** @brief  Clear the UART NE pending flag.
00671   * @param  __HANDLE__: specifies the UART Handle.
00672   * @retval None
00673   */
00674 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
00675
00676 /** @brief  Clear the UART ORE pending flag.
00677   * @param  __HANDLE__: specifies the UART Handle.
00678   * @retval None
00679   */
00680 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
00681
00682 /** @brief  Clear the UART IDLE pending flag.
00683   * @param  __HANDLE__: specifies the UART Handle.
00684   * @retval None
00685   */
00686 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
00687
00688 /** @brief  Checks whether the specified UART flag is set or not.
00689   * @param  __HANDLE__: specifies the UART Handle.
00690   * @param  __FLAG__: specifies the flag to check.
00691   *        This parameter can be one of the following values:
00692   *            @arg UART_FLAG_REACK: Receive enable acknowledge flag
00693   *            @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
00694   *            @arg UART_FLAG_WUF:   Wake up from stop mode flag
00695   *            @arg UART_FLAG_RWU:   Receiver wake up flag (is the UART in mute mode)
00696   *            @arg UART_FLAG_SBKF:  Send Break flag
00697   *            @arg UART_FLAG_CMF:   Character match flag
00698   *            @arg UART_FLAG_BUSY:  Busy flag
00699   *            @arg UART_FLAG_ABRF:  Auto Baud rate detection flag
00700   *            @arg UART_FLAG_ABRE:  Auto Baud rate detection error flag
00701   *            @arg UART_FLAG_EOBF:  End of block flag
00702   *            @arg UART_FLAG_RTOF:  Receiver timeout flag
00703   *            @arg UART_FLAG_CTS:   CTS Change flag (not available for UART4 and UART5)
00704   *            @arg UART_FLAG_LBD:   LIN Break detection flag
00705   *            @arg UART_FLAG_TXE:   Transmit data register empty flag
00706   *            @arg UART_FLAG_TC:    Transmission Complete flag
00707   *            @arg UART_FLAG_RXNE:  Receive data register not empty flag
00708   *            @arg UART_FLAG_IDLE:  Idle Line detection flag
00709   *            @arg UART_FLAG_ORE:   OverRun Error flag
00710   *            @arg UART_FLAG_NE:    Noise Error flag
00711   *            @arg UART_FLAG_FE:    Framing Error flag
00712   *            @arg UART_FLAG_PE:    Parity Error flag
00713   * @retval The new state of __FLAG__ (TRUE or FALSE).
00714   */
00715 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00716
00717 /** @brief  Enables the specified UART interrupt.
00718   * @param  __HANDLE__: specifies the UART Handle.
00719   * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
00720   *          This parameter can be one of the following values:
00721   *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt
00722   *            @arg UART_IT_CM:   Character match interrupt
00723   *            @arg UART_IT_CTS:  CTS change interrupt
00724   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00725   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00726   *            @arg UART_IT_TC:   Transmission complete interrupt
00727   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00728   *            @arg UART_IT_IDLE: Idle line detection interrupt
00729   *            @arg UART_IT_PE:   Parity Error interrupt
00730   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00731   * @retval None
00732   */
00733 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00734                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00735                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00736
00737
00738 /** @brief  Disables the specified UART interrupt.
00739   * @param  __HANDLE__: specifies the UART Handle.
00740   * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
00741   *          This parameter can be one of the following values:
00742   *            @arg UART_IT_CM:   Character match interrupt
00743   *            @arg UART_IT_CTS:  CTS change interrupt
00744   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00745   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00746   *            @arg UART_IT_TC:   Transmission complete interrupt
00747   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00748   *            @arg UART_IT_IDLE: Idle line detection interrupt
00749   *            @arg UART_IT_PE:   Parity Error interrupt
00750   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00751   * @retval None
00752   */
00753 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00754                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00755                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00756
00757 /** @brief  Checks whether the specified UART interrupt has occurred or not.
00758   * @param  __HANDLE__: specifies the UART Handle.
00759   * @param  __IT__: specifies the UART interrupt to check.
00760   *          This parameter can be one of the following values:
00761   *            @arg UART_IT_CM:   Character match interrupt
00762   *            @arg UART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
00763   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00764   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00765   *            @arg UART_IT_TC:   Transmission complete interrupt
00766   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00767   *            @arg UART_IT_IDLE: Idle line detection interrupt
00768   *            @arg UART_IT_ORE:  OverRun Error interrupt
00769   *            @arg UART_IT_NE:   Noise Error interrupt
00770   *            @arg UART_IT_FE:   Framing Error interrupt
00771   *            @arg UART_IT_PE:   Parity Error interrupt
00772   * @retval The new state of __IT__ (TRUE or FALSE).
00773   */
00774 #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00775
00776 /** @brief  Checks whether the specified UART interrupt source is enabled.
00777   * @param  __HANDLE__: specifies the UART Handle.
00778   * @param  __IT__: specifies the UART interrupt source to check.
00779   *          This parameter can be one of the following values:
00780   *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
00781   *            @arg UART_IT_LBD: LIN Break detection interrupt
00782   *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
00783   *            @arg UART_IT_TC:  Transmission complete interrupt
00784   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00785   *            @arg UART_IT_IDLE: Idle line detection interrupt
00786   *            @arg UART_IT_ORE: OverRun Error interrupt
00787   *            @arg UART_IT_NE: Noise Error interrupt
00788   *            @arg UART_IT_FE: Framing Error interrupt
00789   *            @arg UART_IT_PE: Parity Error interrupt
00790   * @retval The new state of __IT__ (TRUE or FALSE).
00791   */
00792 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
00793                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
00794
00795 /** @brief  Set a specific UART request flag.
00796   * @param  __HANDLE__: specifies the UART Handle.
00797   * @param  __REQ__: specifies the request flag to set
00798   *          This parameter can be one of the following values:
00799   *            @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
00800   *            @arg UART_SENDBREAK_REQUEST: Send Break Request
00801   *            @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
00802   *            @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
00803   *            @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
00804   * @retval None
00805   */
00806 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
00807
00808 /** @brief  Enables the UART one bit sample method
00809   * @param  __HANDLE__: specifies the UART Handle.
00810   * @retval None
00811   */
00812 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00813
00814 /** @brief  Disables the UART one bit sample method
00815   * @param  __HANDLE__: specifies the UART Handle.
00816   * @retval None
00817   */
00818 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00819
00820 /** @brief  Enable UART
00821   * @param  __HANDLE__: specifies the UART Handle.
00822   * @retval None
00823   */
00824 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00825
00826 /** @brief  Disable UART
00827   * @param  __HANDLE__: specifies the UART Handle.
00828   * @retval None
00829   */
00830 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00831
00832 /** @brief  Enable CTS flow control
00833   *         This macro allows to enable CTS hardware flow control for a given UART instance,
00834   *         without need to call HAL_UART_Init() function.
00835   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00836   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00837   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00838   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00839   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00840   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00841   * @param  __HANDLE__: specifies the UART Handle.
00842   *         The Handle Instance can be USART1, USART2 or LPUART.
00843   * @retval None
00844   */
00845 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
00846   do{                                                      \
00847     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
00848     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
00849   } while(0)
00850
00851 /** @brief  Disable CTS flow control
00852   *         This macro allows to disable CTS hardware flow control for a given UART instance,
00853   *         without need to call HAL_UART_Init() function.
00854   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00855   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00856   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00857   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00858   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00859   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00860   * @param  __HANDLE__: specifies the UART Handle.
00861   *         The Handle Instance can be USART1, USART2 or LPUART.
00862   * @retval None
00863   */
00864 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
00865   do{                                                       \
00866     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
00867     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
00868   } while(0)
00869
00870 /** @brief  Enable RTS flow control
00871   *         This macro allows to enable RTS hardware flow control for a given UART instance,
00872   *         without need to call HAL_UART_Init() function.
00873   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00874   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00875   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00876   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00877   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00878   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00879   * @param  __HANDLE__: specifies the UART Handle.
00880   *         The Handle Instance can be USART1, USART2 or LPUART.
00881   * @retval None
00882   */
00883 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
00884   do{                                                     \
00885     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
00886     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
00887   } while(0)
00888
00889 /** @brief  Disable RTS flow control
00890   *         This macro allows to disable RTS hardware flow control for a given UART instance,
00891   *         without need to call HAL_UART_Init() function.
00892   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00893   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00894   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00895   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00896   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00897   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00898   * @param  __HANDLE__: specifies the UART Handle.
00899   *         The Handle Instance can be USART1, USART2 or LPUART.
00900   * @retval None
00901   */
00902 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
00903   do{                                                      \
00904     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
00905     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
00906   } while(0)
00907
00908 /**
00909   * @}
00910   */
00911
00912 /* Private macros --------------------------------------------------------*/
00913 /** @defgroup UART_Private_Macros   UART Private Macros
00914   * @{
00915   */
00916 /** @brief  BRR division operation to set BRR register with LPUART
00917   * @param  _PCLK_: LPUART clock
00918   * @param  _BAUD_: Baud rate set by the user
00919   * @retval Division result
00920   */
00921 #define UART_DIV_LPUART(_PCLK_, _BAUD_)                (((_PCLK_)*256)/((_BAUD_)))
00922
00923 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode
00924   * @param  _PCLK_: UART clock
00925   * @param  _BAUD_: Baud rate set by the user
00926   * @retval Division result
00927   */
00928 #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*2)/((_BAUD_)))
00929
00930 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode
00931   * @param  _PCLK_: UART clock
00932   * @param  _BAUD_: Baud rate set by the user
00933   * @retval Division result
00934   */
00935 #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)             (((_PCLK_))/((_BAUD_)))
00936
00937 /** @brief  Check UART Baud rate
00938   * @param  BAUDRATE: Baudrate specified by the user
00939   *         The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
00940   *         divided by the smallest oversampling used on the USART (i.e. 8)
00941   * @retval Test result (TRUE or FALSE).
00942   */
00943 #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
00944
00945 /** @brief  Check UART assertion time
00946   * @param  TIME: 5-bit value assertion time
00947   * @retval Test result (TRUE or FALSE).
00948   */
00949 #define IS_UART_ASSERTIONTIME(TIME)    ((TIME) <= 0x1F)
00950
00951 /** @brief  Check UART deassertion time
00952   * @param  TIME: 5-bit value deassertion time
00953   * @retval Test result (TRUE or FALSE).
00954   */
00955 #define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
00956
00957 #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
00958                                     ((STOPBITS) == UART_STOPBITS_2))
00959
00960 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
00961                                 ((PARITY) == UART_PARITY_EVEN) || \
00962                                 ((PARITY) == UART_PARITY_ODD))
00963
00964 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
00965                               (((CONTROL) == UART_HWCONTROL_NONE) || \
00966                                ((CONTROL) == UART_HWCONTROL_RTS) || \
00967                                ((CONTROL) == UART_HWCONTROL_CTS) || \
00968                                ((CONTROL) == UART_HWCONTROL_RTS_CTS))
00969
00970 #define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
00971
00972 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
00973                               ((STATE) == UART_STATE_ENABLE))
00974
00975 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
00976                                         ((SAMPLING) == UART_OVERSAMPLING_8))
00977
00978 #define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \
00979                                         ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))
00980
00981 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE)  (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
00982                                                     ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
00983                                                     ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
00984                                                     ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
00985
00986 #define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
00987                                            ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
00988
00989 #define IS_UART_LIN(LIN)            (((LIN) == UART_LIN_DISABLE) || \
00990                                      ((LIN) == UART_LIN_ENABLE))
00991
00992 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
00993                                       ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
00994
00995 #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
00996                                                  ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
00997
00998 #define IS_UART_DMA_TX(DMATX)         (((DMATX) == UART_DMA_TX_DISABLE) || \
00999                                        ((DMATX) == UART_DMA_TX_ENABLE))
01000
01001 #define IS_UART_DMA_RX(DMARX)         (((DMARX) == UART_DMA_RX_DISABLE) || \
01002                                        ((DMARX) == UART_DMA_RX_ENABLE))
01003
01004 #define IS_UART_HALF_DUPLEX(HDSEL)         (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
01005                                             ((HDSEL) == UART_HALF_DUPLEX_ENABLE))
01006
01007 #define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
01008                                           ((PARAM) == UART_SENDBREAK_REQUEST) || \
01009                                           ((PARAM) == UART_MUTE_MODE_REQUEST) || \
01010                                           ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
01011                                           ((PARAM) == UART_TXDATA_FLUSH_REQUEST))
01012
01013 #define IS_UART_ADVFEATURE_INIT(INIT)           ((INIT) <= (UART_ADVFEATURE_NO_INIT | \
01014                                                             UART_ADVFEATURE_TXINVERT_INIT | \
01015                                                             UART_ADVFEATURE_RXINVERT_INIT | \
01016                                                             UART_ADVFEATURE_DATAINVERT_INIT | \
01017                                                             UART_ADVFEATURE_SWAP_INIT | \
01018                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
01019                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT   | \
01020                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
01021                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01022
01023 #define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
01024                                          ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
01025
01026 #define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
01027                                          ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
01028
01029 #define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01030                                              ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
01031
01032 #define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
01033                                        ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
01034
01035 #define IS_UART_OVERRUN(OVERRUN)         (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01036                                           ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
01037
01038 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE)  (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01039                                                         ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01040
01041 #define IS_UART_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01042                                                    ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01043
01044 #define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01045                                                ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01046
01047 #define IS_UART_MUTE_MODE(MUTE)           (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01048                                            ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01049
01050 #define IS_UART_DE_POLARITY(POLARITY)    (((POLARITY) == UART_DE_POLARITY_HIGH) || \
01051                                           ((POLARITY) == UART_DE_POLARITY_LOW))
01052
01053 /**
01054   * @}
01055   */
01056 /* Include UART HAL Extension module */
01057 #include "stm32f7xx_hal_uart_ex.h"
01058 /* Exported functions --------------------------------------------------------*/
01059 /** @addtogroup UART_Exported_Functions UART Exported Functions
01060   * @{
01061   */
01062
01063 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01064   * @{
01065   */
01066
01067 /* Initialization and de-initialization functions  ****************************/
01068 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01069 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01070 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01071 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01072 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
01073 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01074 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01075
01076 /**
01077   * @}
01078   */
01079
01080 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01081   * @{
01082   */
01083
01084 /* IO operation functions *****************************************************/
01085 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01086 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01087 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01088 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01089 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01090 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01091 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01092 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01093 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01094 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01095 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01096 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01097 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01098 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01099 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01100
01101 /**
01102   * @}
01103   */
01104
01105 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01106   * @{
01107   */
01108
01109 /* Peripheral Control functions  ************************************************/
01110 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01111 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01112 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01113 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01114 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01115 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01116
01117 /**
01118   * @}
01119   */
01120
01121 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01122   * @{
01123   */
01124
01125 /* Peripheral State and Errors functions  **************************************************/
01126 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
01127 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
01128
01129 /**
01130   * @}
01131   */
01132
01133 /**
01134   * @}
01135   */
01136
01137 /* Private functions -----------------------------------------------------------*/
01138 /** @addtogroup UART_Private_Functions UART Private Functions
01139   * @{
01140   */
01141
01142 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01143 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01144 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
01145 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01146
01147 /**
01148   * @}
01149   */
01150
01151 /**
01152   * @}
01153   */
01154
01155 /**
01156   * @}
01157   */
01158
01159 #ifdef __cplusplus
01160 }
01161 #endif
01162
01163 #endif /* __STM32F7xx_HAL_UART_H */
01164
01165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_uart_ex.h Source File

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stm32f7xx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of UART HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_UART_EX_H
00040 #define __STM32F7xx_HAL_UART_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UARTEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup UARTEx_Word_Length UARTEx Word Length
00064   * @{
00065   */
00066 #define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)
00067 #define UART_WORDLENGTH_8B                  ((uint32_t)0x0000)
00068 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)
00069 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00070                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00071                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00072 #define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
00073 /**
00074   * @}
00075   */
00076
00077
00078 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
00079   * @{
00080   */
00081 #define UART_ADDRESS_DETECT_4B                ((uint32_t)0x00000000)
00082 #define UART_ADDRESS_DETECT_7B                ((uint32_t)USART_CR2_ADDM7)
00083 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00084                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00085 /**
00086   * @}
00087   */
00088
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported macro ------------------------------------------------------------*/
00095
00096 /** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
00097   * @{
00098   */
00099
00100 /** @brief  Reports the UART clock source.
00101   * @param  __HANDLE__: specifies the UART Handle
00102   * @param  __CLOCKSOURCE__: output variable
00103   * @retval UART clocking source, written in __CLOCKSOURCE__.
00104   */
00105 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
00106   do {                                                        \
00107     if((__HANDLE__)->Instance == USART1)                      \
00108     {                                                         \
00109        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00110        {                                                      \
00111         case RCC_USART1CLKSOURCE_PCLK2:                       \
00112           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00113           break;                                              \
00114         case RCC_USART1CLKSOURCE_HSI:                         \
00115           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00116           break;                                              \
00117         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00118           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00119           break;                                              \
00120         case RCC_USART1CLKSOURCE_LSE:                         \
00121           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00122           break;                                              \
00123         default:                                              \
00124           break;                                              \
00125        }                                                      \
00126     }                                                         \
00127     else if((__HANDLE__)->Instance == USART2)                 \
00128     {                                                         \
00129        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00130        {                                                      \
00131         case RCC_USART2CLKSOURCE_PCLK1:                       \
00132           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00133           break;                                              \
00134         case RCC_USART2CLKSOURCE_HSI:                         \
00135           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00136           break;                                              \
00137         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00138           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00139           break;                                              \
00140         case RCC_USART2CLKSOURCE_LSE:                         \
00141           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00142           break;                                              \
00143         default:                                              \
00144           break;                                              \
00145        }                                                      \
00146     }                                                         \
00147     else if((__HANDLE__)->Instance == USART3)                 \
00148     {                                                         \
00149        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00150        {                                                      \
00151         case RCC_USART3CLKSOURCE_PCLK1:                       \
00152           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00153           break;                                              \
00154         case RCC_USART3CLKSOURCE_HSI:                         \
00155           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00156           break;                                              \
00157         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00158           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00159           break;                                              \
00160         case RCC_USART3CLKSOURCE_LSE:                         \
00161           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00162           break;                                              \
00163         default:                                              \
00164           break;                                              \
00165        }                                                      \
00166     }                                                         \
00167     else if((__HANDLE__)->Instance == UART4)                  \
00168     {                                                         \
00169        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00170        {                                                      \
00171         case RCC_UART4CLKSOURCE_PCLK1:                        \
00172           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00173           break;                                              \
00174         case RCC_UART4CLKSOURCE_HSI:                          \
00175           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00176           break;                                              \
00177         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00178           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00179           break;                                              \
00180         case RCC_UART4CLKSOURCE_LSE:                          \
00181           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00182           break;                                              \
00183         default:                                              \
00184           break;                                              \
00185        }                                                      \
00186     }                                                         \
00187     else if ((__HANDLE__)->Instance == UART5)                 \
00188     {                                                         \
00189        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00190        {                                                      \
00191         case RCC_UART5CLKSOURCE_PCLK1:                        \
00192           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00193           break;                                              \
00194         case RCC_UART5CLKSOURCE_HSI:                          \
00195           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00196           break;                                              \
00197         case RCC_UART5CLKSOURCE_SYSCLK:                       \
00198           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00199           break;                                              \
00200         case RCC_UART5CLKSOURCE_LSE:                          \
00201           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00202           break;                                              \
00203         default:                                              \
00204           break;                                              \
00205        }                                                      \
00206     }                                                         \
00207     else if((__HANDLE__)->Instance == USART6)                 \
00208     {                                                         \
00209        switch(__HAL_RCC_GET_USART6_SOURCE())                  \
00210        {                                                      \
00211         case RCC_USART6CLKSOURCE_PCLK2:                       \
00212           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00213           break;                                              \
00214         case RCC_USART6CLKSOURCE_HSI:                         \
00215           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00216           break;                                              \
00217         case RCC_USART6CLKSOURCE_SYSCLK:                      \
00218           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00219           break;                                              \
00220         case RCC_USART6CLKSOURCE_LSE:                         \
00221           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00222           break;                                              \
00223         default:                                              \
00224           break;                                              \
00225        }                                                      \
00226     }                                                         \
00227     else if ((__HANDLE__)->Instance == UART7)                 \
00228     {                                                         \
00229        switch(__HAL_RCC_GET_UART7_SOURCE())                   \
00230        {                                                      \
00231         case RCC_UART7CLKSOURCE_PCLK1:                        \
00232           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00233           break;                                              \
00234         case RCC_UART7CLKSOURCE_HSI:                          \
00235           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00236           break;                                              \
00237         case RCC_UART7CLKSOURCE_SYSCLK:                       \
00238           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00239           break;                                              \
00240         case RCC_UART7CLKSOURCE_LSE:                          \
00241           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00242           break;                                              \
00243         default:                                              \
00244           break;                                              \
00245        }                                                      \
00246     }                                                                                                                                                                                                                           \
00247     else if ((__HANDLE__)->Instance == UART8)                 \
00248     {                                                         \
00249        switch(__HAL_RCC_GET_UART8_SOURCE())                   \
00250        {                                                      \
00251         case RCC_UART8CLKSOURCE_PCLK1:                        \
00252           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00253           break;                                              \
00254         case RCC_UART8CLKSOURCE_HSI:                          \
00255           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00256           break;                                              \
00257         case RCC_UART8CLKSOURCE_SYSCLK:                       \
00258           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00259           break;                                              \
00260         case RCC_UART8CLKSOURCE_LSE:                          \
00261           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00262           break;                                              \
00263         default:                                              \
00264           break;                                              \
00265        }                                                      \
00266     }                                                                                                                                                                                                                           \
00267   } while(0)
00268
00269 /** @brief  Reports the UART mask to apply to retrieve the received data
00270   *         according to the word length and to the parity bits activation.
00271   *         If PCE = 1, the parity bit is not included in the data extracted
00272   *         by the reception API().
00273   *         This masking operation is not carried out in the case of
00274   *         DMA transfers.
00275   * @param  __HANDLE__: specifies the UART Handle
00276   * @retval mask to apply to UART RDR register value.
00277   */
00278 #define UART_MASK_COMPUTATION(__HANDLE__)                       \
00279   do {                                                                \
00280   if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
00281   {                                                                   \
00282      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00283      {                                                                \
00284         (__HANDLE__)->Mask = 0x01FF ;                                 \
00285      }                                                                \
00286      else                                                             \
00287      {                                                                \
00288         (__HANDLE__)->Mask = 0x00FF ;                                 \
00289      }                                                                \
00290   }                                                                   \
00291   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
00292   {                                                                   \
00293      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00294      {                                                                \
00295         (__HANDLE__)->Mask = 0x00FF ;                                 \
00296      }                                                                \
00297      else                                                             \
00298      {                                                                \
00299         (__HANDLE__)->Mask = 0x007F ;                                 \
00300      }                                                                \
00301   }                                                                   \
00302   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
00303   {                                                                   \
00304      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00305      {                                                                \
00306         (__HANDLE__)->Mask = 0x007F ;                                 \
00307      }                                                                \
00308      else                                                             \
00309      {                                                                \
00310         (__HANDLE__)->Mask = 0x003F ;                                 \
00311      }                                                                \
00312   }                                                                   \
00313 } while(0)
00314
00315 /**
00316   * @}
00317   */
00318
00319 /* Exported functions --------------------------------------------------------*/
00320
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 #ifdef __cplusplus
00330 }
00331 #endif
00332
00333 #endif /* __STM32F7xx_HAL_UART_EX_H */
00334
00335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_usart.c Source File

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stm32f7xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   USART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00010   *          Peripheral (USART).
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral Control functions
00014   *
00015   @verbatim
00016   ===============================================================================
00017                         ##### How to use this driver #####
00018  ===============================================================================
00019     [..]
00020       The USART HAL driver can be used as follows:
00021
00022       (#) Declare a USART_HandleTypeDef handle structure.
00023       (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:
00024           (##) Enable the USARTx interface clock.
00025           (##) USART pins configuration:
00026             (+++) Enable the clock for the USART GPIOs.
00027             (+++) Configure these USART pins as alternate function pull-up.
00028           (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00029                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00030             (+++) Configure the USARTx interrupt priority.
00031             (+++) Enable the NVIC USART IRQ handle.
00032             (+++) The specific USART interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00035           (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00036                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx Stream.
00041             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
00043
00044       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00045           flow control and Mode(Receiver/Transmitter) in the husart Init structure.
00046
00047       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00048           (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00049                by calling the customed HAL_USART_MspInit(&husart) API.
00050
00051   @endverbatim
00052   ******************************************************************************
00053   * @attention
00054   *
00055   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00056   *
00057   * Redistribution and use in source and binary forms, with or without modification,
00058   * are permitted provided that the following conditions are met:
00059   *   1. Redistributions of source code must retain the above copyright notice,
00060   *      this list of conditions and the following disclaimer.
00061   *   2. Redistributions in binary form must reproduce the above copyright notice,
00062   *      this list of conditions and the following disclaimer in the documentation
00063   *      and/or other materials provided with the distribution.
00064   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00065   *      may be used to endorse or promote products derived from this software
00066   *      without specific prior written permission.
00067   *
00068   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00069   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00070   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00071   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00072   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00073   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00074   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00075   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00076   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00077   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00078   *
00079   ******************************************************************************
00080   */
00081
00082 /* Includes ------------------------------------------------------------------*/
00083 #include "stm32f7xx_hal.h"
00084
00085 /** @addtogroup STM32F7xx_HAL_Driver
00086   * @{
00087   */
00088
00089 /** @defgroup USART USART
00090   * @brief HAL USART Synchronous module driver
00091   * @{
00092   */
00093
00094 #ifdef HAL_USART_MODULE_ENABLED
00095
00096 /* Private typedef -----------------------------------------------------------*/
00097 /* Private define ------------------------------------------------------------*/
00098 /** @addtogroup USART_Private_Constants
00099   * @{
00100   */
00101 #define DUMMY_DATA                             ((uint16_t) 0xFFFF)
00102 #define TEACK_REACK_TIMEOUT                    ((uint32_t) 1000)
00103 #define USART_TXDMA_TIMEOUTVALUE            22000
00104 #define USART_TIMEOUT_VALUE                 22000
00105 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00106                                      USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))
00107 #define USART_CR2_FIELDS       ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
00108                             USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))
00109 /**
00110   * @}
00111   */
00112 /* Private macro -------------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 /* Private function prototypes -----------------------------------------------*/
00115 /* Private functions ---------------------------------------------------------*/
00116 /** @addtogroup USART_Private_Functions
00117   * @{
00118   */
00119 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00120 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00121 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00122 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00123 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00124 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00125 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00126 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00127 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
00128 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00129 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
00130 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
00131 /**
00132   * @}
00133   */
00134
00135 /* Exported functions --------------------------------------------------------*/
00136
00137 /** @defgroup USART_Exported_Functions USART Exported Functions
00138   * @{
00139   */
00140
00141 /** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
00142   *  @brief    Initialization and Configuration functions
00143   *
00144 @verbatim
00145  ===============================================================================
00146             ##### Initialization and Configuration functions #####
00147  ===============================================================================
00148     [..]
00149     This subsection provides a set of functions allowing to initialize the USART
00150     in asynchronous and in synchronous modes.
00151       (+) For the asynchronous mode only these parameters can be configured:
00152         (++) Baud Rate
00153         (++) Word Length
00154         (++) Stop Bit
00155         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00156              in the data register is transmitted but is changed by the parity bit.
00157              Depending on the frame length defined by the M1 and M0 bits (7-bit,
00158              8-bit or 9-bit), the possible USART frame formats are as listed in the
00159              following table:
00160
00161    (+++) +---------------------------------------------------------------+
00162    (+++) | M1M0 bits |  PCE bit  |            USART frame                |
00163    (+++) |-----------------------|---------------------------------------|
00164    (+++) |     10    |     0     |    | SB | 7-bit data | STB |          |
00165    (+++) |-----------|-----------|---------------------------------------|
00166    (+++) |     10    |     1     |    | SB | 6-bit data | PB | STB |     |
00167    (+++) +---------------------------------------------------------------+
00168
00169         (++) USART polarity
00170         (++) USART phase
00171         (++) USART LastBit
00172         (++) Receiver/transmitter modes
00173
00174     [..]
00175     The HAL_USART_Init() function follows the USART  synchronous configuration
00176     procedure (details for the procedure are available in reference manual).
00177
00178 @endverbatim
00179   * @{
00180   */
00181
00182 /**
00183   * @brief  Initializes the USART mode according to the specified
00184   *         parameters in the USART_InitTypeDef and create the associated handle.
00185   * @param husart: USART handle
00186   * @retval HAL status
00187   */
00188 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00189 {
00190   /* Check the USART handle allocation */
00191   if(husart == NULL)
00192   {
00193     return HAL_ERROR;
00194   }
00195
00196   /* Check the parameters */
00197   assert_param(IS_USART_INSTANCE(husart->Instance));
00198
00199   if(husart->State == HAL_USART_STATE_RESET)
00200   {
00201     /* Allocate lock resource and initialize it */
00202     husart->Lock = HAL_UNLOCKED;
00203     /* Init the low level hardware : GPIO, CLOCK */
00204     HAL_USART_MspInit(husart);
00205   }
00206
00207   husart->State = HAL_USART_STATE_BUSY;
00208
00209   /* Disable the Peripheral */
00210   __HAL_USART_DISABLE(husart);
00211
00212   /* Set the Usart Communication parameters */
00213   if (USART_SetConfig(husart) == HAL_ERROR)
00214   {
00215     return HAL_ERROR;
00216   }
00217
00218   /* In Synchronous mode, the following bits must be kept cleared:
00219   - LINEN bit in the USART_CR2 register
00220   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00221   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00222   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00223
00224   /* Enable the Peripheral */
00225   __HAL_USART_ENABLE(husart);
00226
00227   /* TEACK and/or REACK to check before moving husart->State to Ready */
00228   return (USART_CheckIdleState(husart));
00229 }
00230
00231 /**
00232   * @brief DeInitializes the USART peripheral
00233   * @param husart: USART handle
00234   * @retval HAL status
00235   */
00236 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00237 {
00238    /* Check the USART handle allocation */
00239   if(husart == NULL)
00240   {
00241     return HAL_ERROR;
00242   }
00243
00244   /* Check the parameters */
00245   assert_param(IS_USART_INSTANCE(husart->Instance));
00246
00247   husart->State = HAL_USART_STATE_BUSY;
00248
00249   husart->Instance->CR1 = 0x0;
00250   husart->Instance->CR2 = 0x0;
00251   husart->Instance->CR3 = 0x0;
00252
00253   /* DeInit the low level hardware */
00254   HAL_USART_MspDeInit(husart);
00255
00256   husart->ErrorCode = HAL_USART_ERROR_NONE;
00257   husart->State = HAL_USART_STATE_RESET;
00258
00259   /* Process Unlock */
00260   __HAL_UNLOCK(husart);
00261
00262   return HAL_OK;
00263 }
00264
00265 /**
00266   * @brief USART MSP Init
00267   * @param husart: USART handle
00268   * @retval None
00269   */
00270  __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00271 {
00272   /* Prevent unused argument(s) compilation warning */
00273   UNUSED(husart);
00274
00275   /* NOTE : This function should not be modified, when the callback is needed,
00276             the HAL_USART_MspInit can be implemented in the user file
00277    */
00278 }
00279
00280 /**
00281   * @brief USART MSP DeInit
00282   * @param husart: USART handle
00283   * @retval None
00284   */
00285  __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00286 {
00287   /* Prevent unused argument(s) compilation warning */
00288   UNUSED(husart);
00289
00290   /* NOTE : This function should not be modified, when the callback is needed,
00291             the HAL_USART_MspDeInit can be implemented in the user file
00292    */
00293 }
00294
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00300   *  @brief   USART Transmit and Receive functions
00301   *
00302 @verbatim
00303  ===============================================================================
00304                       ##### IO operation functions #####
00305  ===============================================================================
00306     This subsection provides a set of functions allowing to manage the USART synchronous
00307     data transfers.
00308
00309     [..] The USART supports master mode only: it cannot receive or send data related to an input
00310          clock (SCLK is always an output).
00311
00312     (#) There are two mode of transfer:
00313        (++) Blocking mode: The communication is performed in polling mode.
00314             The HAL status of all data processing is returned by the same function
00315             after finishing transfer.
00316        (++) No-Blocking mode: The communication is performed using Interrupts
00317            or DMA, These API's return the HAL status.
00318            The end of the data processing will be indicated through the
00319            dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00320            using DMA mode.
00321            The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00322            will be executed respectively at the end of the transmit or Receive process
00323            The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00324
00325     (#) Blocking mode API's are :
00326         (++) HAL_USART_Transmit()in simplex mode
00327         (++) HAL_USART_Receive() in full duplex receive only
00328         (++) HAL_USART_TransmitReceive() in full duplex mode
00329
00330     (#) Non-Blocking mode API's with Interrupt are :
00331         (++) HAL_USART_Transmit_IT()in simplex mode
00332         (++) HAL_USART_Receive_IT() in full duplex receive only
00333         (++) HAL_USART_TransmitReceive_IT()in full duplex mode
00334         (++) HAL_USART_IRQHandler()
00335
00336     (#) No-Blocking mode functions with DMA are :
00337         (++) HAL_USART_Transmit_DMA()in simplex mode
00338         (++) HAL_USART_Receive_DMA() in full duplex receive only
00339         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00340         (++) HAL_USART_DMAPause()
00341         (++) HAL_USART_DMAResume()
00342         (++) HAL_USART_DMAStop()
00343
00344     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00345         (++) HAL_USART_TxCpltCallback()
00346         (++) HAL_USART_RxCpltCallback()
00347         (++) HAL_USART_TxHalfCpltCallback()
00348         (++) HAL_USART_RxHalfCpltCallback()
00349         (++) HAL_USART_ErrorCallback()
00350         (++) HAL_USART_TxRxCpltCallback()
00351
00352 @endverbatim
00353   * @{
00354   */
00355
00356 /**
00357   * @brief  Simplex Send an amount of data in blocking mode
00358   * @param  husart: USART handle
00359   * @param pTxData: pointer to data buffer
00360   * @param Size: amount of data to be sent
00361   * @param Timeout : Timeout duration
00362   * @retval HAL status
00363   */
00364 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00365 {
00366   uint16_t* tmp;
00367
00368   if(husart->State == HAL_USART_STATE_READY)
00369   {
00370     if((pTxData == NULL) || (Size == 0))
00371     {
00372       return  HAL_ERROR;
00373     }
00374
00375     /* Process Locked */
00376     __HAL_LOCK(husart);
00377
00378     husart->ErrorCode = HAL_USART_ERROR_NONE;
00379     husart->State = HAL_USART_STATE_BUSY_TX;
00380
00381     husart->TxXferSize = Size;
00382     husart->TxXferCount = Size;
00383
00384     /* Check the remaining data to be sent */
00385     while(husart->TxXferCount > 0)
00386     {
00387       husart->TxXferCount--;
00388       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
00389         {
00390           return HAL_TIMEOUT;
00391         }
00392       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00393       {
00394         tmp = (uint16_t*) pTxData;
00395         husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00396         pTxData += 2;
00397       }
00398       else
00399       {
00400         husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
00401       }
00402     }
00403
00404     if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
00405     {
00406       return HAL_TIMEOUT;
00407     }
00408
00409     husart->State = HAL_USART_STATE_READY;
00410
00411     /* Process Unlocked */
00412     __HAL_UNLOCK(husart);
00413
00414     return HAL_OK;
00415   }
00416   else
00417   {
00418     return HAL_BUSY;
00419   }
00420 }
00421
00422 /**
00423   * @brief Receive an amount of data in blocking mode
00424   * @note To receive synchronous data, dummy data are simultaneously transmitted
00425   * @param husart: USART handle
00426   * @param pRxData: pointer to data buffer
00427   * @param Size: amount of data to be received
00428   * @param Timeout : Timeout duration
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00432 {
00433   uint16_t* tmp;
00434   uint16_t uhMask;
00435
00436   if(husart->State == HAL_USART_STATE_READY)
00437   {
00438     if((pRxData == NULL) || (Size == 0))
00439     {
00440       return  HAL_ERROR;
00441     }
00442     /* Process Locked */
00443     __HAL_LOCK(husart);
00444
00445     husart->ErrorCode = HAL_USART_ERROR_NONE;
00446     husart->State = HAL_USART_STATE_BUSY_RX;
00447
00448     husart->RxXferSize = Size;
00449     husart->RxXferCount = Size;
00450
00451     /* Computation of USART mask to apply to RDR register */
00452     __HAL_USART_MASK_COMPUTATION(husart);
00453     uhMask = husart->Mask;
00454
00455     /* as long as data have to be received */
00456     while(husart->RxXferCount > 0)
00457     {
00458       husart->RxXferCount--;
00459
00460       /* Wait until TC flag is set to send dummy byte in order to generate the
00461       * clock for the slave to send data.
00462        * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00463        * can be written for all the cases. */
00464       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
00465       {
00466         return HAL_TIMEOUT;
00467       }
00468       husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF);
00469
00470       /* Wait for RXNE Flag */
00471       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00472       {
00473         return HAL_TIMEOUT;
00474       }
00475
00476       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00477       {
00478         tmp = (uint16_t*) pRxData ;
00479         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00480         pRxData +=2;
00481       }
00482       else
00483       {
00484         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00485       }
00486     }
00487
00488     husart->State = HAL_USART_STATE_READY;
00489
00490     /* Process Unlocked */
00491     __HAL_UNLOCK(husart);
00492
00493     return HAL_OK;
00494   }
00495   else
00496   {
00497     return HAL_BUSY;
00498   }
00499 }
00500
00501 /**
00502   * @brief Full-Duplex Send and Receive an amount of data in blocking mode
00503   * @param husart: USART handle
00504   * @param pTxData: pointer to TX data buffer
00505   * @param pRxData: pointer to RX data buffer
00506   * @param Size: amount of data to be sent (same amount to be received)
00507   * @param Timeout : Timeout duration
00508   * @retval HAL status
00509   */
00510 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00511 {
00512   uint16_t* tmp;
00513   uint16_t uhMask;
00514
00515   if(husart->State == HAL_USART_STATE_READY)
00516   {
00517     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00518     {
00519       return  HAL_ERROR;
00520     }
00521     /* Process Locked */
00522     __HAL_LOCK(husart);
00523
00524     husart->ErrorCode = HAL_USART_ERROR_NONE;
00525     husart->State = HAL_USART_STATE_BUSY_RX;
00526
00527     husart->RxXferSize = Size;
00528     husart->TxXferSize = Size;
00529     husart->TxXferCount = Size;
00530     husart->RxXferCount = Size;
00531
00532     /* Computation of USART mask to apply to RDR register */
00533     __HAL_USART_MASK_COMPUTATION(husart);
00534     uhMask = husart->Mask;
00535
00536     /* Check the remain data to be sent */
00537     while(husart->TxXferCount > 0)
00538     {
00539       husart->TxXferCount--;
00540       husart->RxXferCount--;
00541
00542       /* Wait until TC flag is set to send data */
00543       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
00544       {
00545         return HAL_TIMEOUT;
00546       }
00547       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00548       {
00549         tmp = (uint16_t*) pTxData;
00550         husart->Instance->TDR = (*tmp & uhMask);
00551         pTxData += 2;
00552       }
00553       else
00554       {
00555         husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
00556       }
00557
00558       /* Wait for RXNE Flag */
00559       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00560       {
00561         return HAL_TIMEOUT;
00562       }
00563
00564       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00565       {
00566         tmp = (uint16_t*) pRxData ;
00567         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00568         pRxData +=2;
00569       }
00570       else
00571       {
00572         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00573       }
00574     }
00575
00576     husart->State = HAL_USART_STATE_READY;
00577
00578     /* Process Unlocked */
00579     __HAL_UNLOCK(husart);
00580
00581     return HAL_OK;
00582   }
00583   else
00584   {
00585     return HAL_BUSY;
00586   }
00587 }
00588
00589 /**
00590   * @brief  Send an amount of data in interrupt mode
00591   * @param  husart: USART handle
00592   * @param pTxData: pointer to data buffer
00593   * @param Size: amount of data to be sent
00594   * @retval HAL status
00595   */
00596 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00597 {
00598   if(husart->State == HAL_USART_STATE_READY)
00599   {
00600     if((pTxData == NULL ) || (Size == 0))
00601     {
00602       return HAL_ERROR;
00603     }
00604
00605     /* Process Locked */
00606     __HAL_LOCK(husart);
00607
00608     husart->pTxBuffPtr = pTxData;
00609     husart->TxXferSize = Size;
00610     husart->TxXferCount = Size;
00611
00612     husart->ErrorCode = HAL_USART_ERROR_NONE;
00613     husart->State = HAL_USART_STATE_BUSY_TX;
00614
00615     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
00616     are not managed by the USART Transmit Process to avoid the overrun interrupt
00617     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
00618     to benefit for the frame error and noise interrupts the usart mode should be
00619     configured only for transmit "USART_MODE_TX" */
00620
00621     /* Process Unlocked */
00622     __HAL_UNLOCK(husart);
00623
00624     /* Enable the USART Transmit Data Register Empty Interrupt */
00625     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00626
00627     return HAL_OK;
00628   }
00629   else
00630   {
00631     return HAL_BUSY;
00632   }
00633 }
00634
00635 /**
00636   * @brief Receive an amount of data in blocking mode
00637   *        To receive synchronous data, dummy data are simultaneously transmitted
00638   * @param husart: USART handle
00639   * @param pRxData: pointer to data buffer
00640   * @param Size: amount of data to be received
00641   * @retval HAL status
00642   */
00643 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00644 {
00645   if(husart->State == HAL_USART_STATE_READY)
00646   {
00647     if((pRxData == NULL ) || (Size == 0))
00648     {
00649       return HAL_ERROR;
00650     }
00651     /* Process Locked */
00652     __HAL_LOCK(husart);
00653
00654     husart->pRxBuffPtr = pRxData;
00655     husart->RxXferSize = Size;
00656     husart->RxXferCount = Size;
00657
00658     __HAL_USART_MASK_COMPUTATION(husart);
00659
00660     husart->ErrorCode = HAL_USART_ERROR_NONE;
00661     husart->State = HAL_USART_STATE_BUSY_RX;
00662
00663     /* Enable the USART Parity Error Interrupt */
00664     __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
00665
00666     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00667     __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
00668
00669     /* Enable the USART Data Register not empty Interrupt */
00670     __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
00671
00672     /* Process Unlocked */
00673     __HAL_UNLOCK(husart);
00674
00675
00676     /* Send dummy byte in order to generate the clock for the Slave to send the next data */
00677     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00678     {
00679       husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF);
00680     }
00681     else
00682     {
00683       husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);
00684     }
00685
00686     return HAL_OK;
00687   }
00688   else
00689   {
00690     return HAL_BUSY;
00691   }
00692 }
00693
00694 /**
00695   * @brief Full-Duplex Send and Receive an amount of data in interrupt mode
00696   * @param husart: USART handle
00697   * @param pTxData: pointer to TX data buffer
00698   * @param pRxData: pointer to RX data buffer
00699   * @param Size: amount of data to be sent (same amount to be received)
00700   * @retval HAL status
00701   */
00702 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
00703 {
00704
00705   if(husart->State == HAL_USART_STATE_READY)
00706   {
00707     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00708     {
00709       return HAL_ERROR;
00710     }
00711     /* Process Locked */
00712     __HAL_LOCK(husart);
00713
00714     husart->pRxBuffPtr = pRxData;
00715     husart->RxXferSize = Size;
00716     husart->RxXferCount = Size;
00717     husart->pTxBuffPtr = pTxData;
00718     husart->TxXferSize = Size;
00719     husart->TxXferCount = Size;
00720
00721     /* Computation of USART mask to apply to RDR register */
00722     __HAL_USART_MASK_COMPUTATION(husart);
00723
00724     husart->ErrorCode = HAL_USART_ERROR_NONE;
00725     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00726
00727     /* Enable the USART Data Register not empty Interrupt */
00728     __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
00729
00730     /* Enable the USART Parity Error Interrupt */
00731     __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
00732
00733     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00734     __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
00735
00736     /* Process Unlocked */
00737     __HAL_UNLOCK(husart);
00738
00739     /* Enable the USART Transmit Data Register Empty Interrupt */
00740     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00741
00742     return HAL_OK;
00743   }
00744   else
00745   {
00746     return HAL_BUSY;
00747   }
00748
00749 }
00750
00751 /**
00752   * @brief Send an amount of data in DMA mode
00753   * @param husart: USART handle
00754   * @param pTxData: pointer to data buffer
00755   * @param Size: amount of data to be sent
00756   * @retval HAL status
00757   */
00758 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00759 {
00760   uint32_t *tmp;
00761
00762   if(husart->State == HAL_USART_STATE_READY)
00763   {
00764     if((pTxData == NULL ) || (Size == 0))
00765     {
00766       return HAL_ERROR;
00767     }
00768     /* Process Locked */
00769     __HAL_LOCK(husart);
00770
00771     husart->pTxBuffPtr = pTxData;
00772     husart->TxXferSize = Size;
00773     husart->TxXferCount = Size;
00774
00775     husart->ErrorCode = HAL_USART_ERROR_NONE;
00776     husart->State = HAL_USART_STATE_BUSY_TX;
00777
00778     /* Set the USART DMA transfer complete callback */
00779     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00780
00781     /* Set the USART DMA Half transfer complete callback */
00782     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00783
00784     /* Set the DMA error callback */
00785     husart->hdmatx->XferErrorCallback = USART_DMAError;
00786
00787     /* Enable the USART transmit DMA channel */
00788     tmp = (uint32_t*)&pTxData;
00789     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00790
00791
00792     /* Clear the TC flag in the SR register by writing 0 to it */
00793     __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);
00794
00795     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00796        in the USART CR3 register */
00797     husart->Instance->CR3 |= USART_CR3_DMAT;
00798
00799     /* Process Unlocked */
00800     __HAL_UNLOCK(husart);
00801
00802     return HAL_OK;
00803   }
00804   else
00805   {
00806     return HAL_BUSY;
00807   }
00808 }
00809
00810 /**
00811   * @brief Receive an amount of data in DMA mode
00812   * @param husart: USART handle
00813   * @param pRxData: pointer to data buffer
00814   * @param Size: amount of data to be received
00815   * @note   When the USART parity is enabled (PCE = 1), the received data contain
00816   *         the parity bit (MSB position)
00817   * @retval HAL status
00818   * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.
00819   */
00820 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00821 {
00822   uint32_t *tmp;
00823
00824   if(husart->State == HAL_USART_STATE_READY)
00825   {
00826     if((pRxData == NULL ) || (Size == 0))
00827     {
00828       return HAL_ERROR;
00829     }
00830
00831     /* Process Locked */
00832     __HAL_LOCK(husart);
00833
00834     husart->pRxBuffPtr = pRxData;
00835     husart->RxXferSize = Size;
00836     husart->pTxBuffPtr = pRxData;
00837     husart->TxXferSize = Size;
00838
00839     husart->ErrorCode = HAL_USART_ERROR_NONE;
00840     husart->State = HAL_USART_STATE_BUSY_RX;
00841
00842     /* Set the USART DMA Rx transfer complete callback */
00843     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00844
00845     /* Set the USART DMA Half transfer complete callback */
00846     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00847
00848     /* Set the USART DMA Rx transfer error callback */
00849     husart->hdmarx->XferErrorCallback = USART_DMAError;
00850
00851     /* Enable the USART receive DMA channel */
00852     tmp = (uint32_t*)&pRxData;
00853     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
00854
00855     /* Enable the USART transmit DMA channel: the transmit stream is used in order
00856        to generate in the non-blocking mode the clock to the slave device,
00857        this mode isn't a simplex receive mode but a full-duplex receive mode */
00858     tmp = (uint32_t*)&pRxData;
00859     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00860
00861     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00862        in the USART CR3 register */
00863     husart->Instance->CR3 |= USART_CR3_DMAR;
00864
00865     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00866        in the USART CR3 register */
00867     husart->Instance->CR3 |= USART_CR3_DMAT;
00868
00869     /* Process Unlocked */
00870     __HAL_UNLOCK(husart);
00871
00872     return HAL_OK;
00873   }
00874   else
00875   {
00876     return HAL_BUSY;
00877   }
00878 }
00879
00880 /**
00881   * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
00882   * @param husart: USART handle
00883   * @param pTxData: pointer to TX data buffer
00884   * @param pRxData: pointer to RX data buffer
00885   * @param Size: amount of data to be received/sent
00886   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
00887   * @retval HAL status
00888   */
00889 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
00890 {
00891   uint32_t *tmp;
00892
00893   if(husart->State == HAL_USART_STATE_READY)
00894   {
00895     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00896     {
00897       return HAL_ERROR;
00898     }
00899     /* Process Locked */
00900     __HAL_LOCK(husart);
00901
00902     husart->pRxBuffPtr = pRxData;
00903     husart->RxXferSize = Size;
00904     husart->pTxBuffPtr = pTxData;
00905     husart->TxXferSize = Size;
00906
00907     husart->ErrorCode = HAL_USART_ERROR_NONE;
00908     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00909
00910     /* Set the USART DMA Rx transfer complete callback */
00911     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00912
00913     /* Set the USART DMA Half transfer complete callback */
00914     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00915
00916     /* Set the USART DMA Tx transfer complete callback */
00917     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00918
00919     /* Set the USART DMA Half transfer complete callback */
00920     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00921
00922     /* Set the USART DMA Tx transfer error callback */
00923     husart->hdmatx->XferErrorCallback = USART_DMAError;
00924
00925     /* Set the USART DMA Rx transfer error callback */
00926     husart->hdmarx->XferErrorCallback = USART_DMAError;
00927
00928     /* Enable the USART receive DMA channel */
00929     tmp = (uint32_t*)&pRxData;
00930     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
00931
00932     /* Enable the USART transmit DMA channel */
00933     tmp = (uint32_t*)&pTxData;
00934     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00935
00936     /* Clear the TC flag in the SR register by writing 0 to it */
00937     __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);
00938
00939     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00940        in the USART CR3 register */
00941     husart->Instance->CR3 |= USART_CR3_DMAR;
00942
00943     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00944        in the USART CR3 register */
00945     husart->Instance->CR3 |= USART_CR3_DMAT;
00946
00947     /* Process Unlocked */
00948     __HAL_UNLOCK(husart);
00949
00950     return HAL_OK;
00951   }
00952   else
00953   {
00954     return HAL_BUSY;
00955   }
00956 }
00957
00958 /**
00959   * @brief Pauses the DMA Transfer.
00960   * @param husart: USART handle
00961   * @retval None
00962   */
00963 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
00964 {
00965   /* Process Locked */
00966   __HAL_LOCK(husart);
00967
00968   if(husart->State == HAL_USART_STATE_BUSY_TX)
00969   {
00970     /* Disable the USART DMA Tx request */
00971     husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
00972   }
00973   else if(husart->State == HAL_USART_STATE_BUSY_RX)
00974   {
00975     /* Disable the USART DMA Rx request */
00976     husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
00977   }
00978   else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
00979   {
00980     /* Disable the USART DMA Tx request */
00981     husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
00982     /* Disable the USART DMA Rx request */
00983     husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
00984   }
00985
00986   /* Process Unlocked */
00987   __HAL_UNLOCK(husart);
00988
00989   return HAL_OK;
00990 }
00991
00992 /**
00993   * @brief Resumes the DMA Transfer.
00994   * @param husart: USART handle
00995   * @retval None
00996   */
00997 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
00998 {
00999   /* Process Locked */
01000   __HAL_LOCK(husart);
01001
01002   if(husart->State == HAL_USART_STATE_BUSY_TX)
01003   {
01004     /* Enable the USART DMA Tx request */
01005     husart->Instance->CR3 |= USART_CR3_DMAT;
01006   }
01007   else if(husart->State == HAL_USART_STATE_BUSY_RX)
01008   {
01009     /* Clear the Overrun flag before resuming the Rx transfer*/
01010     __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
01011
01012     /* Enable the USART DMA Rx request */
01013     husart->Instance->CR3 |= USART_CR3_DMAR;
01014   }
01015   else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
01016   {
01017     /* Clear the Overrun flag before resuming the Rx transfer*/
01018     __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
01019
01020     /* Enable the USART DMA Rx request  before the DMA Tx request */
01021     husart->Instance->CR3 |= USART_CR3_DMAR;
01022
01023     /* Enable the USART DMA Tx request */
01024     husart->Instance->CR3 |= USART_CR3_DMAT;
01025   }
01026
01027   /* Process Unlocked */
01028   __HAL_UNLOCK(husart);
01029
01030   return HAL_OK;
01031 }
01032
01033 /**
01034   * @brief Stops the DMA Transfer.
01035   * @param husart: USART handle
01036   * @retval None
01037   */
01038 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01039 {
01040   /* The Lock is not implemented on this API to allow the user application
01041      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01042      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01043      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01044      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01045      the stream and the corresponding call back is executed. */
01046
01047   /* Disable the USART Tx/Rx DMA requests */
01048   husart->Instance->CR3 &= ~USART_CR3_DMAT;
01049   husart->Instance->CR3 &= ~USART_CR3_DMAR;
01050
01051   /* Abort the USART DMA tx Stream */
01052   if(husart->hdmatx != NULL)
01053   {
01054     HAL_DMA_Abort(husart->hdmatx);
01055   }
01056   /* Abort the USART DMA rx Stream */
01057   if(husart->hdmarx != NULL)
01058   {
01059     HAL_DMA_Abort(husart->hdmarx);
01060   }
01061
01062   husart->State = HAL_USART_STATE_READY;
01063
01064   return HAL_OK;
01065 }
01066
01067 /**
01068   * @brief  This function handles USART interrupt request.
01069   * @param  husart: USART handle
01070   * @retval None
01071   */
01072 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
01073 {
01074
01075   /* USART parity error interrupt occurred ------------------------------------*/
01076   if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET))
01077   {
01078     __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
01079     husart->ErrorCode |= HAL_USART_ERROR_PE;
01080     /* Set the USART state ready to be able to start again the process */
01081     husart->State = HAL_USART_STATE_READY;
01082   }
01083
01084   /* USART frame error interrupt occurred -------------------------------------*/
01085   if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
01086   {
01087     __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
01088     husart->ErrorCode |= HAL_USART_ERROR_FE;
01089     /* Set the USART state ready to be able to start again the process */
01090     husart->State = HAL_USART_STATE_READY;
01091   }
01092
01093   /* USART noise error interrupt occurred -------------------------------------*/
01094   if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
01095   {
01096     __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
01097     husart->ErrorCode |= HAL_USART_ERROR_NE;
01098     /* Set the USART state ready to be able to start again the process */
01099     husart->State = HAL_USART_STATE_READY;
01100   }
01101
01102   /* USART Over-Run interrupt occurred ----------------------------------------*/
01103   if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
01104   {
01105     __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
01106     husart->ErrorCode |= HAL_USART_ERROR_ORE;
01107     /* Set the USART state ready to be able to start again the process */
01108     husart->State = HAL_USART_STATE_READY;
01109   }
01110
01111    /* Call USART Error Call back function if need be --------------------------*/
01112   if(husart->ErrorCode != HAL_USART_ERROR_NONE)
01113   {
01114     HAL_USART_ErrorCallback(husart);
01115   }
01116
01117   /* USART in mode Receiver --------------------------------------------------*/
01118   if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET))
01119   {
01120     if(husart->State == HAL_USART_STATE_BUSY_RX)
01121     {
01122       USART_Receive_IT(husart);
01123     }
01124     else
01125     {
01126       USART_TransmitReceive_IT(husart);
01127     }
01128   }
01129
01130   /* USART in mode Transmitter -----------------------------------------------*/
01131   if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET))
01132   {
01133     if(husart->State == HAL_USART_STATE_BUSY_TX)
01134     {
01135       USART_Transmit_IT(husart);
01136     }
01137     else
01138     {
01139       USART_TransmitReceive_IT(husart);
01140     }
01141   }
01142
01143   /* USART in mode Transmitter (transmission end) -----------------------------*/
01144   if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET))
01145   {
01146     USART_EndTransmit_IT(husart);
01147   }
01148
01149 }
01150
01151 /**
01152   * @brief Tx Transfer completed callbacks
01153   * @param husart: USART handle
01154   * @retval None
01155   */
01156 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
01157 {
01158   /* Prevent unused argument(s) compilation warning */
01159   UNUSED(husart);
01160
01161   /* NOTE : This function should not be modified, when the callback is needed,
01162             the HAL_USART_TxCpltCallback can be implemented in the user file
01163    */
01164 }
01165
01166 /**
01167   * @brief  Tx Half Transfer completed callbacks.
01168   * @param  husart: USART handle
01169   * @retval None
01170   */
01171  __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
01172 {
01173   /* Prevent unused argument(s) compilation warning */
01174   UNUSED(husart);
01175
01176   /* NOTE: This function should not be modified, when the callback is needed,
01177            the HAL_USART_TxHalfCpltCallback can be implemented in the user file
01178    */
01179 }
01180
01181 /**
01182   * @brief  Rx Transfer completed callbacks.
01183   * @param  husart: USART handle
01184   * @retval None
01185   */
01186 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
01187 {
01188   /* Prevent unused argument(s) compilation warning */
01189   UNUSED(husart);
01190
01191   /* NOTE: This function should not be modified, when the callback is needed,
01192            the HAL_USART_RxCpltCallback can be implemented in the user file
01193    */
01194 }
01195
01196 /**
01197   * @brief Rx Half Transfer completed callbacks
01198   * @param husart: usart handle
01199   * @retval None
01200   */
01201 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
01202 {
01203   /* Prevent unused argument(s) compilation warning */
01204   UNUSED(husart);
01205
01206   /* NOTE : This function should not be modified, when the callback is needed,
01207             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
01208    */
01209 }
01210
01211 /**
01212   * @brief Tx/Rx Transfers completed callback for the non-blocking process
01213   * @param husart: USART handle
01214   * @retval None
01215   */
01216 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
01217 {
01218   /* Prevent unused argument(s) compilation warning */
01219   UNUSED(husart);
01220
01221   /* NOTE : This function should not be modified, when the callback is needed,
01222             the HAL_USART_TxRxCpltCallback can be implemented in the user file
01223    */
01224 }
01225
01226 /**
01227   * @brief USART error callbacks
01228   * @param husart: USART handle
01229   * @retval None
01230   */
01231 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
01232 {
01233   /* Prevent unused argument(s) compilation warning */
01234   UNUSED(husart);
01235
01236   /* NOTE : This function should not be modified, when the callback is needed,
01237             the HAL_USART_ErrorCallback can be implemented in the user file
01238    */
01239 }
01240
01241 /**
01242   * @}
01243   */
01244
01245 /** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
01246   *  @brief   USART State and Errors functions
01247   *
01248 @verbatim
01249   ==============================================================================
01250                   ##### Peripheral State and Errors functions #####
01251   ==============================================================================
01252   [..]
01253     This subsection provides a set of functions allowing to return the State of
01254     USART communication
01255     process, return Peripheral Errors occurred during communication process
01256      (+) HAL_USART_GetState() API can be helpful to check in run-time the state
01257          of the USART peripheral.
01258      (+) HAL_USART_GetError() check in run-time errors that could be occurred during
01259          communication.
01260 @endverbatim
01261   * @{
01262   */
01263
01264 /**
01265   * @brief return the USART state
01266   * @param husart: USART handle
01267   * @retval HAL state
01268   */
01269 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
01270 {
01271   return husart->State;
01272 }
01273
01274 /**
01275   * @brief  Return the USART error code
01276   * @param  husart : pointer to a USART_HandleTypeDef structure that contains
01277   *              the configuration information for the specified USART.
01278   * @retval USART Error Code
01279   */
01280 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
01281 {
01282   return husart->ErrorCode;
01283 }
01284
01285 /**
01286   * @}
01287   */
01288
01289
01290 /**
01291   * @brief  Simplex Send an amount of data in non-blocking mode.
01292   * @note   Function called under interruption only, once
01293   *         interruptions have been enabled by HAL_USART_Transmit_IT().
01294   * @param  husart: USART handle
01295   * @retval HAL status
01296   * @note   The USART errors are not managed to avoid the overrun error.
01297   */
01298 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
01299 {
01300   uint16_t* tmp;
01301
01302   if(husart->State == HAL_USART_STATE_BUSY_TX)
01303   {
01304
01305     if(husart->TxXferCount == 0)
01306     {
01307       /* Disable the USART Transmit Complete Interrupt */
01308       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01309
01310       /* Enable the USART Transmit Complete Interrupt */
01311       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01312
01313       return HAL_OK;
01314     }
01315     else
01316     {
01317       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01318       {
01319         tmp = (uint16_t*) husart->pTxBuffPtr;
01320         husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
01321         husart->pTxBuffPtr += 2;
01322       }
01323       else
01324       {
01325         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
01326       }
01327
01328       husart->TxXferCount--;
01329
01330       return HAL_OK;
01331     }
01332   }
01333   else
01334   {
01335     return HAL_BUSY;
01336   }
01337 }
01338
01339 /**
01340   * @brief  Wraps up transmission in non-blocking mode.
01341   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01342   *                the configuration information for the specified USART module.
01343   * @retval HAL status
01344   */
01345 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
01346 {
01347   /* Disable the USART Transmit Complete Interrupt */
01348   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
01349
01350   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01351   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01352
01353   husart->State = HAL_USART_STATE_READY;
01354
01355   HAL_USART_TxCpltCallback(husart);
01356
01357   return HAL_OK;
01358 }
01359
01360 /**
01361   * @brief  Simplex Receive an amount of data in non-blocking mode.
01362   *         Function called under interruption only, once
01363   *         interruptions have been enabled by HAL_USART_Receive_IT()
01364   * @param  husart: USART handle
01365   * @retval HAL status
01366   */
01367 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
01368 {
01369   uint16_t* tmp;
01370   uint16_t uhMask = husart->Mask;
01371
01372   if(husart->State == HAL_USART_STATE_BUSY_RX)
01373   {
01374
01375     if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01376     {
01377       tmp = (uint16_t*) husart->pRxBuffPtr;
01378       *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
01379       husart->pRxBuffPtr += 2;
01380     }
01381     else
01382     {
01383       *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
01384     }
01385       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
01386       husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);
01387
01388     if(--husart->RxXferCount == 0)
01389     {
01390       __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01391
01392       /* Disable the USART Parity Error Interrupt */
01393       __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01394
01395       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01396       __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01397
01398       husart->State = HAL_USART_STATE_READY;
01399
01400       HAL_USART_RxCpltCallback(husart);
01401
01402       return HAL_OK;
01403     }
01404
01405     return HAL_OK;
01406   }
01407   else
01408   {
01409     return HAL_BUSY;
01410   }
01411 }
01412
01413 /**
01414   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
01415   *         Function called under interruption only, once
01416   *         interruptions have been enabled by HAL_USART_TransmitReceive_IT()
01417   * @param  husart: USART handle
01418   * @retval HAL status
01419   */
01420 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
01421 {
01422   uint16_t* tmp;
01423   uint16_t uhMask = husart->Mask;
01424
01425   if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
01426   {
01427     if(husart->TxXferCount != 0x00)
01428     {
01429       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
01430       {
01431         if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01432         {
01433           tmp = (uint16_t*) husart->pTxBuffPtr;
01434           husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
01435           husart->pTxBuffPtr += 2;
01436         }
01437         else
01438         {
01439           husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
01440         }
01441         husart->TxXferCount--;
01442
01443         /* Check the latest data transmitted */
01444         if(husart->TxXferCount == 0)
01445         {
01446            __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01447         }
01448       }
01449     }
01450
01451     if(husart->RxXferCount != 0x00)
01452     {
01453       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
01454       {
01455         if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01456         {
01457           tmp = (uint16_t*) husart->pRxBuffPtr;
01458           *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
01459           husart->pRxBuffPtr += 2;
01460         }
01461         else
01462         {
01463           *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
01464         }
01465         husart->RxXferCount--;
01466       }
01467     }
01468
01469     /* Check the latest data received */
01470     if(husart->RxXferCount == 0)
01471     {
01472       __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01473
01474       /* Disable the USART Parity Error Interrupt */
01475       __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01476
01477       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01478       __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01479
01480       husart->State = HAL_USART_STATE_READY;
01481
01482       HAL_USART_TxRxCpltCallback(husart);
01483
01484       return HAL_OK;
01485     }
01486
01487     return HAL_OK;
01488   }
01489   else
01490   {
01491     return HAL_BUSY;
01492   }
01493 }
01494
01495 /**
01496   * @brief  This function handles USART Communication Timeout.
01497   * @param  husart: USART handle
01498   * @param  Flag: specifies the USART flag to check.
01499   * @param  Status: The new Flag status (SET or RESET).
01500   * @param  Timeout: Timeout duration
01501   * @retval HAL status
01502   */
01503 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01504 {
01505   uint32_t tickstart = HAL_GetTick();
01506
01507   /* Wait until flag is set */
01508   if(Status == RESET)
01509   {
01510     while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
01511     {
01512       /* Check for the Timeout */
01513       if(Timeout != HAL_MAX_DELAY)
01514       {
01515         if((Timeout == 0)||((HAL_GetTick()-tickstart) >=  Timeout))
01516         {
01517           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01518           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01519           __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01520           __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01521           __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01522
01523           husart->State= HAL_USART_STATE_READY;
01524
01525           /* Process Unlocked */
01526           __HAL_UNLOCK(husart);
01527
01528           return HAL_TIMEOUT;
01529         }
01530       }
01531     }
01532   }
01533   else
01534   {
01535     while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
01536     {
01537       /* Check for the Timeout */
01538       if(Timeout != HAL_MAX_DELAY)
01539       {
01540         if((Timeout == 0)||((HAL_GetTick()-tickstart) >=  Timeout))
01541         {
01542           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01543           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01544           __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01545           __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01546           __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01547
01548           husart->State= HAL_USART_STATE_READY;
01549
01550           /* Process Unlocked */
01551           __HAL_UNLOCK(husart);
01552
01553           return HAL_TIMEOUT;
01554         }
01555       }
01556     }
01557   }
01558   return HAL_OK;
01559 }
01560
01561
01562 /**
01563   * @brief DMA USART transmit process complete callback
01564   * @param  hdma: DMA handle
01565   * @retval None
01566   */
01567 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01568 {
01569   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01570
01571   /* DMA Normal mode */
01572   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01573   {
01574     husart->TxXferCount = 0;
01575
01576     if(husart->State == HAL_USART_STATE_BUSY_TX)
01577     {
01578       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01579          in the USART CR3 register */
01580       husart->Instance->CR3 &= ~(USART_CR3_DMAT);
01581
01582       /* Enable the USART Transmit Complete Interrupt */
01583       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01584     }
01585   }
01586   /* DMA Circular mode */
01587   else
01588   {
01589     if(husart->State == HAL_USART_STATE_BUSY_TX)
01590     {
01591     HAL_USART_TxCpltCallback(husart);
01592    }
01593  }
01594 }
01595
01596
01597 /**
01598   * @brief DMA USART transmit process half complete callback
01599   * @param hdma : DMA handle
01600   * @retval None
01601   */
01602 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01603 {
01604   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01605
01606   HAL_USART_TxHalfCpltCallback(husart);
01607 }
01608
01609 /**
01610   * @brief DMA USART receive process complete callback
01611   * @param  hdma: DMA handle
01612   * @retval None
01613   */
01614 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01615 {
01616   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01617
01618   /* DMA Normal mode */
01619   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
01620   {
01621     husart->RxXferCount = 0;
01622
01623     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
01624     in USART CR3 register */
01625     husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
01626     /* similarly, disable the DMA TX transfer that was started to provide the
01627        clock to the slave device */
01628     husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
01629
01630       if(husart->State == HAL_USART_STATE_BUSY_RX)
01631       {
01632         HAL_USART_RxCpltCallback(husart);
01633       }
01634       /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01635       else
01636       {
01637         HAL_USART_TxRxCpltCallback(husart);
01638       }
01639     husart->State= HAL_USART_STATE_READY;
01640   }
01641   /* DMA circular mode */
01642   else
01643   {
01644     if(husart->State == HAL_USART_STATE_BUSY_RX)
01645     {
01646       HAL_USART_RxCpltCallback(husart);
01647     }
01648     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01649     else
01650     {
01651       HAL_USART_TxRxCpltCallback(husart);
01652     }
01653   }
01654 }
01655
01656 /**
01657   * @brief DMA USART receive process half complete callback
01658   * @param hdma : DMA handle
01659   * @retval None
01660   */
01661 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01662 {
01663   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01664
01665   HAL_USART_RxHalfCpltCallback(husart);
01666 }
01667
01668 /**
01669   * @brief DMA USART communication error callback
01670   * @param  hdma: DMA handle
01671   * @retval None
01672   */
01673 static void USART_DMAError(DMA_HandleTypeDef *hdma)
01674 {
01675   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01676
01677   husart->RxXferCount = 0;
01678   husart->TxXferCount = 0;
01679   husart->ErrorCode |= HAL_USART_ERROR_DMA;
01680   husart->State= HAL_USART_STATE_READY;
01681
01682   HAL_USART_ErrorCallback(husart);
01683 }
01684
01685 /**
01686   * @brief Configure the USART peripheral
01687   * @param husart: USART handle
01688   * @retval None
01689   */
01690 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
01691 {
01692   uint32_t tmpreg      = 0x0;
01693   USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
01694   HAL_StatusTypeDef ret                = HAL_OK;
01695   uint16_t brrtemp                     = 0x0000;
01696   uint16_t usartdiv                    = 0x0000;
01697
01698   /* Check the parameters */
01699   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
01700   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
01701   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
01702   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
01703   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
01704   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
01705   assert_param(IS_USART_PARITY(husart->Init.Parity));
01706   assert_param(IS_USART_MODE(husart->Init.Mode));
01707   assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling));
01708
01709
01710   /*-------------------------- USART CR1 Configuration -----------------------*/
01711    /* Clear M, PCE, PS, TE and RE bits and configure
01712    *  the USART Word Length, Parity, Mode and OverSampling:
01713    *  set the M bits according to husart->Init.WordLength value
01714    *  set PCE and PS bits according to husart->Init.Parity value
01715    *  set TE and RE bits according to husart->Init.Mode value
01716    *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
01717   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
01718   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
01719
01720   /*---------------------------- USART CR2 Configuration ---------------------*/
01721   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
01722    * set CPOL bit according to husart->Init.CLKPolarity value
01723    * set CPHA bit according to husart->Init.CLKPhase value
01724    * set LBCL bit according to husart->Init.CLKLastBit value
01725    * set STOP[13:12] bits according to husart->Init.StopBits value */
01726   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
01727   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
01728   tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
01729   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
01730
01731   /*-------------------------- USART CR3 Configuration -----------------------*/
01732   /* no CR3 register configuration                                            */
01733
01734   /*-------------------------- USART BRR Configuration -----------------------*/
01735   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
01736   USART_GETCLOCKSOURCE(husart, clocksource);
01737   switch (clocksource)
01738   {
01739     case USART_CLOCKSOURCE_PCLK1:
01740       usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate);
01741       break;
01742     case USART_CLOCKSOURCE_PCLK2:
01743       usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate);
01744       break;
01745     case USART_CLOCKSOURCE_HSI:
01746       usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate);
01747       break;
01748     case USART_CLOCKSOURCE_SYSCLK:
01749       usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate);
01750       break;
01751     case USART_CLOCKSOURCE_LSE:
01752       usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate);
01753       break;
01754     case USART_CLOCKSOURCE_UNDEFINED:
01755     default:
01756       ret = HAL_ERROR;
01757       break;
01758   }
01759
01760   brrtemp = usartdiv & 0xFFF0;
01761   brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
01762   husart->Instance->BRR = brrtemp;
01763
01764   return ret;
01765 }
01766
01767 /**
01768   * @brief Check the USART Idle State
01769   * @param husart: USART handle
01770   * @retval HAL status
01771   */
01772 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
01773 {
01774    /* Initialize the USART ErrorCode */
01775   husart->ErrorCode = HAL_USART_ERROR_NONE;
01776
01777   /* Check if the Transmitter is enabled */
01778   if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01779   {
01780     /* Wait until TEACK flag is set */
01781     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
01782     {
01783       husart->State= HAL_USART_STATE_TIMEOUT;
01784       return HAL_TIMEOUT;
01785     }
01786   }
01787   /* Check if the Receiver is enabled */
01788   if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01789   {
01790     /* Wait until REACK flag is set */
01791     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
01792     {
01793       husart->State= HAL_USART_STATE_TIMEOUT;
01794       return HAL_TIMEOUT;
01795     }
01796   }
01797
01798   /* Initialize the USART state*/
01799   husart->State= HAL_USART_STATE_READY;
01800
01801   /* Process Unlocked */
01802   __HAL_UNLOCK(husart);
01803
01804   return HAL_OK;
01805 }
01806
01807 /**
01808   * @}
01809   */
01810
01811 #endif /* HAL_USART_MODULE_ENABLED */
01812 /**
01813   * @}
01814   */
01815
01816 /**
01817   * @}
01818   */
01819
01820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_usart.h Source File

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stm32f7xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of USART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_USART_H
00040 #define __STM32F7xx_HAL_USART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup USART_Exported_Types USART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief USART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter can be a value of @ref USARTEx_Word_Length */
00073
00074   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00075                                            This parameter can be a value of @ref USART_Stop_Bits */
00076
00077   uint32_t Parity;                   /*!< Specifies the parity mode.
00078                                            This parameter can be a value of @ref USART_Parity
00079                                            @note When parity is enabled, the computed parity is inserted
00080                                                  at the MSB position of the transmitted data (9th bit when
00081                                                  the word length is set to 9 data bits; 8th bit when the
00082                                                  word length is set to 8 data bits). */
00083
00084   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00085                                            This parameter can be a value of @ref USART_Mode */
00086
00087   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
00088                                            This parameter can be a value of @ref USART_Over_Sampling */
00089
00090   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00091                                            This parameter can be a value of @ref USART_Clock_Polarity */
00092
00093   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00094                                            This parameter can be a value of @ref USART_Clock_Phase */
00095
00096   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00097                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00098                                            This parameter can be a value of @ref USART_Last_Bit */
00099 }USART_InitTypeDef;
00100
00101 /**
00102   * @brief HAL USART State structures definition
00103   */
00104 typedef enum
00105 {
00106   HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized   */
00107   HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
00108   HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
00109   HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
00110   HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
00111   HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
00112   HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
00113   HAL_USART_STATE_ERROR             = 0x04     /*!< Error */
00114 }HAL_USART_StateTypeDef;
00115
00116
00117 /**
00118   * @brief  USART clock sources definitions
00119   */
00120 typedef enum
00121 {
00122   USART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source  */
00123   USART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source  */
00124   USART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source    */
00125   USART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source */
00126   USART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
00127   USART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
00128 }USART_ClockSourceTypeDef;
00129
00130
00131 /**
00132   * @brief  USART handle Structure definition
00133   */
00134 typedef struct
00135 {
00136   USART_TypeDef                 *Instance;        /*!<  USART registers base address        */
00137
00138   USART_InitTypeDef             Init;             /*!< USART communication parameters      */
00139
00140   uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
00141
00142   uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
00143
00144   uint16_t                      TxXferCount;      /*!< USART Tx Transfer Counter           */
00145
00146   uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
00147
00148   uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
00149
00150   uint16_t                      RxXferCount;      /*!< USART Rx Transfer Counter           */
00151
00152   uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
00153
00154   DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
00155
00156   DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
00157
00158   HAL_LockTypeDef               Lock;            /*!<  Locking object                      */
00159
00160   HAL_USART_StateTypeDef        State;           /*!< USART communication state           */
00161
00162   __IO uint32_t                 ErrorCode;       /*!< USART Error code                    */
00163
00164 }USART_HandleTypeDef;
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported constants --------------------------------------------------------*/
00170 /** @defgroup USART_Exported_Constants USART Exported Constants
00171   * @{
00172   */
00173
00174 /** @defgroup USART_Error_Code USART Error Code
00175   * @brief    USART Error Code
00176   * @{
00177   */
00178 #define HAL_USART_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
00179 #define HAL_USART_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
00180 #define HAL_USART_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
00181 #define HAL_USART_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
00182 #define HAL_USART_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
00183 #define HAL_USART_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00189   * @{
00190   */
00191 #define USART_STOPBITS_1                     ((uint32_t)0x0000)
00192 #define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
00193 #define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup USART_Parity    USART Parity
00199   * @{
00200   */
00201 #define USART_PARITY_NONE                   ((uint32_t)0x0000)
00202 #define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)
00203 #define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup USART_Mode   USART Mode
00209   * @{
00210   */
00211 #define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)
00212 #define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)
00213 #define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup USART_Over_Sampling USART Over Sampling
00219   * @{
00220   */
00221 #define USART_OVERSAMPLING_16               ((uint32_t)0x0000)
00222 #define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)
00223 /**
00224   * @}
00225   */
00226 /** @defgroup USART_Clock  USART Clock
00227   * @{
00228   */
00229 #define USART_CLOCK_DISABLE                 ((uint32_t)0x0000)
00230 #define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00236   * @{
00237   */
00238 #define USART_POLARITY_LOW                  ((uint32_t)0x0000)
00239 #define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup USART_Clock_Phase   USART Clock Phase
00245   * @{
00246   */
00247 #define USART_PHASE_1EDGE                   ((uint32_t)0x0000)
00248 #define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup USART_Last_Bit  USART Last Bit
00254   * @{
00255   */
00256 #define USART_LASTBIT_DISABLE               ((uint32_t)0x0000)
00257 #define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup USART_Request_Parameters  USART Request Parameters
00263   * @{
00264   */
00265 #define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */
00266 #define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup USART_Flags      USART Flags
00272   *        Elements values convention: 0xXXXX
00273   *           - 0xXXXX  : Flag mask in the ISR register
00274   * @{
00275   */
00276 #define USART_FLAG_REACK                     ((uint32_t)0x00400000)
00277 #define USART_FLAG_TEACK                     ((uint32_t)0x00200000)
00278 #define USART_FLAG_BUSY                      ((uint32_t)0x00010000)
00279 #define USART_FLAG_CTS                       ((uint32_t)0x00000400)
00280 #define USART_FLAG_CTSIF                     ((uint32_t)0x00000200)
00281 #define USART_FLAG_LBDF                      ((uint32_t)0x00000100)
00282 #define USART_FLAG_TXE                       ((uint32_t)0x00000080)
00283 #define USART_FLAG_TC                        ((uint32_t)0x00000040)
00284 #define USART_FLAG_RXNE                      ((uint32_t)0x00000020)
00285 #define USART_FLAG_IDLE                      ((uint32_t)0x00000010)
00286 #define USART_FLAG_ORE                       ((uint32_t)0x00000008)
00287 #define USART_FLAG_NE                        ((uint32_t)0x00000004)
00288 #define USART_FLAG_FE                        ((uint32_t)0x00000002)
00289 #define USART_FLAG_PE                        ((uint32_t)0x00000001)
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00295   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00296   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00297   *           - XX  : Interrupt source register (2bits)
00298   *                 - 01: CR1 register
00299   *                 - 10: CR2 register
00300   *                 - 11: CR3 register
00301   *           - ZZZZ  : Flag position in the ISR register(4bits)
00302   * @{
00303   */
00304
00305 #define USART_IT_PE                          ((uint16_t)0x0028)
00306 #define USART_IT_TXE                         ((uint16_t)0x0727)
00307 #define USART_IT_TC                          ((uint16_t)0x0626)
00308 #define USART_IT_RXNE                        ((uint16_t)0x0525)
00309 #define USART_IT_IDLE                        ((uint16_t)0x0424)
00310 #define USART_IT_ERR                         ((uint16_t)0x0060)
00311
00312 #define USART_IT_ORE                         ((uint16_t)0x0300)
00313 #define USART_IT_NE                          ((uint16_t)0x0200)
00314 #define USART_IT_FE                          ((uint16_t)0x0100)
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00320   * @{
00321   */
00322 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */
00323 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */
00324 #define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */
00325 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */
00326 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */
00327 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00328 #define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 /* Exported macros -----------------------------------------------------------*/
00338 /** @defgroup USART_Exported_Macros USART Exported Macros
00339   * @{
00340   */
00341
00342 /** @brief Reset USART handle state
00343   * @param  __HANDLE__: USART handle.
00344   * @retval None
00345   */
00346 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00347
00348 /** @brief  Checks whether the specified USART flag is set or not.
00349   * @param  __HANDLE__: specifies the USART Handle
00350   * @param  __FLAG__: specifies the flag to check.
00351   *        This parameter can be one of the following values:
00352   *            @arg USART_FLAG_REACK: Receive enable acknowledge flag
00353   *            @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
00354   *            @arg USART_FLAG_BUSY:  Busy flag
00355   *            @arg USART_FLAG_CTS:   CTS Change flag
00356   *            @arg USART_FLAG_TXE:   Transmit data register empty flag
00357   *            @arg USART_FLAG_TC:    Transmission Complete flag
00358   *            @arg USART_FLAG_RXNE:  Receive data register not empty flag
00359   *            @arg USART_FLAG_IDLE:  Idle Line detection flag
00360   *            @arg USART_FLAG_ORE:   OverRun Error flag
00361   *            @arg USART_FLAG_NE:    Noise Error flag
00362   *            @arg USART_FLAG_FE:    Framing Error flag
00363   *            @arg USART_FLAG_PE:    Parity Error flag
00364   * @retval The new state of __FLAG__ (TRUE or FALSE).
00365   */
00366 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00367
00368
00369 /** @brief  Enables the specified USART interrupt.
00370   * @param  __HANDLE__: specifies the USART Handle
00371   * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
00372   *          This parameter can be one of the following values:
00373   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
00374   *            @arg USART_IT_TC:   Transmission complete interrupt
00375   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00376   *            @arg USART_IT_IDLE: Idle line detection interrupt
00377   *            @arg USART_IT_PE:   Parity Error interrupt
00378   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00379   * @retval None
00380   */
00381 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00382                                                             ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00383                                                             ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00384
00385 /** @brief  Disables the specified USART interrupt.
00386   * @param  __HANDLE__: specifies the USART Handle.
00387   * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
00388   *          This parameter can be one of the following values:
00389   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
00390   *            @arg USART_IT_TC:   Transmission complete interrupt
00391   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00392   *            @arg USART_IT_IDLE: Idle line detection interrupt
00393   *            @arg USART_IT_PE:   Parity Error interrupt
00394   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00395   * @retval None
00396   */
00397 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00398                                                             ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00399                                                             ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00400
00401
00402 /** @brief  Checks whether the specified USART interrupt has occurred or not.
00403   * @param  __HANDLE__: specifies the USART Handle
00404   * @param  __IT__: specifies the USART interrupt source to check.
00405   *          This parameter can be one of the following values:
00406   *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
00407   *            @arg USART_IT_TC:  Transmission complete interrupt
00408   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00409   *            @arg USART_IT_IDLE: Idle line detection interrupt
00410   *            @arg USART_IT_ORE: OverRun Error interrupt
00411   *            @arg USART_IT_NE: Noise Error interrupt
00412   *            @arg USART_IT_FE: Framing Error interrupt
00413   *            @arg USART_IT_PE: Parity Error interrupt
00414   * @retval The new state of __IT__ (TRUE or FALSE).
00415   */
00416 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00417
00418 /** @brief  Checks whether the specified USART interrupt source is enabled.
00419   * @param  __HANDLE__: specifies the USART Handle.
00420   * @param  __IT__: specifies the USART interrupt source to check.
00421   *          This parameter can be one of the following values:
00422   *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
00423   *            @arg USART_IT_TC:  Transmission complete interrupt
00424   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00425   *            @arg USART_IT_IDLE: Idle line detection interrupt
00426   *            @arg USART_IT_ORE: OverRun Error interrupt
00427   *            @arg USART_IT_NE: Noise Error interrupt
00428   *            @arg USART_IT_FE: Framing Error interrupt
00429   *            @arg USART_IT_PE: Parity Error interrupt
00430   * @retval The new state of __IT__ (TRUE or FALSE).
00431   */
00432 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
00433                                                    (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
00434                                                    (((uint16_t)(__IT__)) & USART_IT_MASK)))
00435
00436
00437 /** @brief  Clears the specified USART ISR flag, in setting the proper ICR register flag.
00438   * @param  __HANDLE__: specifies the USART Handle.
00439   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00440   *                       to clear the corresponding interrupt
00441   *          This parameter can be one of the following values:
00442   *            @arg USART_CLEAR_PEF: Parity Error Clear Flag
00443   *            @arg USART_CLEAR_FEF: Framing Error Clear Flag
00444   *            @arg USART_CLEAR_NEF: Noise detected Clear Flag
00445   *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag
00446   *            @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
00447   *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
00448   *            @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
00449   * @retval None
00450   */
00451 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00452
00453 /** @brief  Set a specific USART request flag.
00454   * @param  __HANDLE__: specifies the USART Handle.
00455   * @param  __REQ__: specifies the request flag to set
00456   *          This parameter can be one of the following values:
00457   *            @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
00458   *            @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
00459   *
00460   * @retval None
00461   */
00462 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00463
00464 /** @brief  Enable USART
00465   * @param  __HANDLE__: specifies the USART Handle.
00466   * @retval None
00467   */
00468 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00469
00470 /** @brief  Disable USART
00471   * @param  __HANDLE__: specifies the USART Handle.
00472   * @retval None
00473   */
00474 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00475
00476 /**
00477   * @}
00478   */
00479 /* Include UART HAL Extension module */
00480 #include "stm32f7xx_hal_usart_ex.h"
00481
00482 /* Exported functions --------------------------------------------------------*/
00483 /** @addtogroup USART_Exported_Functions
00484   * @{
00485   */
00486
00487 /** @addtogroup USART_Exported_Functions_Group1
00488   * @{
00489   */
00490 /* Initialization/de-initialization functions  **********************************/
00491 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00492 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00493 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00494 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00495 HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);
00496 /**
00497   * @}
00498   */
00499
00500 /** @addtogroup USART_Exported_Functions_Group2
00501   * @{
00502   */
00503 /* IO operation functions *******************************************************/
00504 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
00505 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00506 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00507 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00508 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00509 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
00510 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00511 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00512 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00513 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00514 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00515 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00516 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00517 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00518 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00519 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00520 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00521 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00522 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00523
00524 /**
00525   * @}
00526   */
00527
00528 /** @addtogroup USART_Exported_Functions_Group3
00529   * @{
00530   */
00531 /* Peripheral State functions  ************************************************/
00532 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
00533 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
00534
00535 /**
00536   * @}
00537   */
00538
00539 /**
00540   * @}
00541   */
00542 /* Private types -------------------------------------------------------------*/
00543 /* Private variables ---------------------------------------------------------*/
00544 /* Private constants ---------------------------------------------------------*/
00545 /** @defgroup USART_Private_Constants USART Private Constants
00546   * @{
00547   */
00548 /** @brief USART interruptions flag mask
00549   *
00550   */
00551 #define USART_IT_MASK                             ((uint16_t)0x001F)
00552
00553 /**
00554   * @}
00555   */
00556 /* Private macros ------------------------------------------------------------*/
00557 /** @defgroup USART_Private_Macros USART Private Macros
00558   * @{
00559   */
00560 /** @brief  Reports the USART clock source.
00561   * @param  __HANDLE__: specifies the USART Handle
00562   * @param  __CLOCKSOURCE__ : output variable
00563   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00564   */
00565 #define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\
00566   do {                                                         \
00567     if((__HANDLE__)->Instance == USART1)                       \
00568     {                                                          \
00569        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00570        {                                                       \
00571         case RCC_USART1CLKSOURCE_PCLK2:                        \
00572           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00573           break;                                               \
00574         case RCC_USART1CLKSOURCE_HSI:                          \
00575           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00576           break;                                               \
00577         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00578           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00579           break;                                               \
00580         case RCC_USART1CLKSOURCE_LSE:                          \
00581           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00582           break;                                               \
00583         default:                                               \
00584           break;                                               \
00585        }                                                       \
00586     }                                                          \
00587     else if((__HANDLE__)->Instance == USART2)                  \
00588     {                                                          \
00589        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00590        {                                                       \
00591         case RCC_USART2CLKSOURCE_PCLK1:                        \
00592           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00593           break;                                               \
00594         case RCC_USART2CLKSOURCE_HSI:                          \
00595           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00596           break;                                               \
00597         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00598           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00599           break;                                               \
00600         case RCC_USART2CLKSOURCE_LSE:                          \
00601           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00602           break;                                               \
00603         default:                                               \
00604           break;                                               \
00605        }                                                       \
00606     }                                                          \
00607     else if((__HANDLE__)->Instance == USART3)                  \
00608     {                                                          \
00609        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00610        {                                                       \
00611         case RCC_USART3CLKSOURCE_PCLK1:                        \
00612           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00613           break;                                               \
00614         case RCC_USART3CLKSOURCE_HSI:                          \
00615           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00616           break;                                               \
00617         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00618           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00619           break;                                               \
00620         case RCC_USART3CLKSOURCE_LSE:                          \
00621           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00622           break;                                               \
00623         default:                                               \
00624           break;                                               \
00625        }                                                       \
00626     }                                                          \
00627     else if((__HANDLE__)->Instance == USART6)                  \
00628     {                                                          \
00629        switch(__HAL_RCC_GET_USART6_SOURCE())                   \
00630        {                                                       \
00631         case RCC_USART6CLKSOURCE_PCLK2:                        \
00632           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00633           break;                                               \
00634         case RCC_USART6CLKSOURCE_HSI:                          \
00635           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00636           break;                                               \
00637         case RCC_USART6CLKSOURCE_SYSCLK:                       \
00638           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00639           break;                                               \
00640         case RCC_USART6CLKSOURCE_LSE:                          \
00641           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00642           break;                                               \
00643         default:                                               \
00644           break;                                               \
00645        }                                                       \
00646     }                                                          \
00647  } while(0)
00648
00649
00650 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
00651                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00652                                          ((__STOPBITS__) == USART_STOPBITS_2))
00653 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00654                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00655                                      ((__PARITY__) == USART_PARITY_ODD))
00656 #define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
00657 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
00658                                              ((__SAMPLING__) == USART_OVERSAMPLING_8))
00659 #define IS_USART_CLOCK(__CLOCK__)     (((__CLOCK__)== USART_CLOCK_DISABLE) || \
00660                                        ((__CLOCK__)== USART_CLOCK_ENABLE))
00661 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00662 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00663 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00664                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00665 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00666                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00667 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
00668
00669 /**
00670   * @}
00671   */
00672
00673 /* Private functions ---------------------------------------------------------*/
00674 /** @defgroup USART_Private_Functions USART Private Functions
00675   * @{
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /**
00687   * @}
00688   */
00689
00690 #ifdef __cplusplus
00691 }
00692 #endif
00693
00694 #endif /* __STM32F7xx_HAL_USART_H */
00695
00696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_usart_ex.h Source File

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stm32f7xx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of USART HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_USART_EX_H
00040 #define __STM32F7xx_HAL_USART_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USARTEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00064   * @{
00065   */
00066 #define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)
00067 #define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
00068 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported functions --------------------------------------------------------*/
00078
00079 /* Private macros ------------------------------------------------------------*/
00080 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00081   * @{
00082   */
00083
00084 /** @brief  Computes the USART mask to apply to retrieve the received data
00085   *         according to the word length and to the parity bits activation.
00086   *         If PCE = 1, the parity bit is not included in the data extracted
00087   *         by the reception API().
00088   *         This masking operation is not carried out in the case of
00089   *         DMA transfers.
00090   * @param  __HANDLE__: specifies the USART Handle
00091   * @retval none
00092   */
00093 #define __HAL_USART_MASK_COMPUTATION(__HANDLE__)                      \
00094   do {                                                                \
00095   if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
00096   {                                                                   \
00097      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00098      {                                                                \
00099         (__HANDLE__)->Mask = 0x01FF ;                                 \
00100      }                                                                \
00101      else                                                             \
00102      {                                                                \
00103         (__HANDLE__)->Mask = 0x00FF ;                                 \
00104      }                                                                \
00105   }                                                                   \
00106   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
00107   {                                                                   \
00108      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00109      {                                                                \
00110         (__HANDLE__)->Mask = 0x00FF ;                                 \
00111      }                                                                \
00112      else                                                             \
00113      {                                                                \
00114         (__HANDLE__)->Mask = 0x007F ;                                 \
00115      }                                                                \
00116   }                                                                   \
00117   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
00118   {                                                                   \
00119      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00120      {                                                                \
00121         (__HANDLE__)->Mask = 0x007F ;                                 \
00122      }                                                                \
00123      else                                                             \
00124      {                                                                \
00125         (__HANDLE__)->Mask = 0x003F ;                                 \
00126      }                                                                \
00127   }                                                                   \
00128 } while(0)
00129
00130 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00131                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00132                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported functions --------------------------------------------------------*/
00138 /* Initialization/de-initialization methods  **********************************/
00139 /* IO operation methods *******************************************************/
00140 /* Peripheral Control methods  ************************************************/
00141 /* Peripheral State methods  **************************************************/
00142
00143
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152 #ifdef __cplusplus
00153 }
00154 #endif
00155
00156 #endif /* __STM32F7xx_HAL_USART_EX_H */
00157
00158 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_wwdg.c Source File

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stm32f7xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   WWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Window Watchdog (WWDG) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State functions
00013   @verbatim
00014   ==============================================================================
00015                       ##### WWDG specific features #####
00016   ==============================================================================
00017   [..]
00018     Once enabled the WWDG generates a system reset on expiry of a programmed
00019     time period, unless the program refreshes the counter (down-counter)
00020     before reaching 0x3F value (i.e. a reset is generated when the counter
00021     value rolls over from 0x40 to 0x3F).
00022
00023     (+) An MCU reset is also generated if the counter value is refreshed
00024         before the counter has reached the refresh window value. This
00025         implies that the counter must be refreshed in a limited window.
00026     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00027     (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
00028         reset occurs.
00029     (+) The WWDG counter input clock is derived from the APB clock divided
00030         by a programmable prescaler.
00031     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00032     (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
00033     (+) WWDG Counter refresh is allowed between the following limits :
00034         (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
00035         (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
00036
00037     (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
00038
00039
00040                      ##### How to use this driver #####
00041   ==============================================================================
00042   [..]
00043     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00044     (+) Set the WWDG prescaler, refresh window and counter value
00045         using HAL_WWDG_Init() function.
00046     (+) Start the WWDG using HAL_WWDG_Start() function.
00047         When the WWDG is enabled the counter value should be configured to
00048         a value greater than 0x40 to prevent generating an immediate reset.
00049     (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
00050         generated when the counter reaches 0x40, and then start the WWDG using
00051         HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
00052         add his own code by customization of function pointer HAL_WWDG_WakeupCallback
00053         Once enabled, EWI interrupt cannot be disabled except by a system reset.
00054     (+) Then the application program must refresh the WWDG counter at regular
00055         intervals during normal operation to prevent an MCU reset, using
00056         HAL_WWDG_Refresh() function. This operation must occur only when
00057         the counter is lower than the refresh window value already programmed.
00058
00059      *** WWDG HAL driver macros list ***
00060      ==================================
00061      [..]
00062        Below the list of most used macros in WWDG HAL driver.
00063
00064       (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
00065       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
00066       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
00067       (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wake-up interrupt
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f7xx_hal.h"
00102
00103 /** @addtogroup STM32F7xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup WWDG WWDG
00108   * @brief WWDG HAL module driver.
00109   * @{
00110   */
00111
00112 #ifdef HAL_WWDG_MODULE_ENABLED
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00121   * @{
00122   */
00123
00124 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
00125  *  @brief    Initialization and Configuration functions.
00126  *
00127 @verbatim
00128   ==============================================================================
00129           ##### Initialization and de-initialization functions #####
00130   ==============================================================================
00131   [..]
00132     This section provides functions allowing to:
00133     (+) Initialize the WWDG according to the specified parameters
00134         in the WWDG_InitTypeDef and create the associated handle
00135     (+) DeInitialize the WWDG peripheral
00136     (+) Initialize the WWDG MSP
00137     (+) DeInitialize the WWDG MSP
00138
00139 @endverbatim
00140   * @{
00141   */
00142
00143 /**
00144   * @brief  Initializes the WWDG according to the specified
00145   *         parameters in the WWDG_InitTypeDef and creates the associated handle.
00146   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00147   *              the configuration information for the specified WWDG module.
00148   * @retval HAL status
00149   */
00150 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00151 {
00152   /* Check the WWDG handle allocation */
00153   if(hwwdg == NULL)
00154   {
00155     return HAL_ERROR;
00156   }
00157
00158   /* Check the parameters */
00159   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00160   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00161   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00162   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00163
00164   if(hwwdg->State == HAL_WWDG_STATE_RESET)
00165   {
00166     /* Allocate lock resource and initialize it */
00167     hwwdg->Lock = HAL_UNLOCKED;
00168     /* Init the low level hardware */
00169     HAL_WWDG_MspInit(hwwdg);
00170   }
00171
00172   /* Change WWDG peripheral state */
00173   hwwdg->State = HAL_WWDG_STATE_BUSY;
00174
00175   /* Set WWDG Prescaler and Window */
00176   MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
00177   /* Set WWDG Counter */
00178   MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
00179
00180   /* Change WWDG peripheral state */
00181   hwwdg->State = HAL_WWDG_STATE_READY;
00182
00183   /* Return function status */
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief  DeInitializes the WWDG peripheral.
00189   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00190   *              the configuration information for the specified WWDG module.
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
00194 {
00195   /* Check the WWDG handle allocation */
00196   if(hwwdg == NULL)
00197   {
00198     return HAL_ERROR;
00199   }
00200
00201   /* Check the parameters */
00202   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00203
00204   /* Change WWDG peripheral state */
00205   hwwdg->State = HAL_WWDG_STATE_BUSY;
00206
00207   /* DeInit the low level hardware */
00208   HAL_WWDG_MspDeInit(hwwdg);
00209
00210   /* Reset WWDG Control register */
00211   hwwdg->Instance->CR  = (uint32_t)0x0000007F;
00212
00213   /* Reset WWDG Configuration register */
00214   hwwdg->Instance->CFR = (uint32_t)0x0000007F;
00215
00216   /* Reset WWDG Status register */
00217   hwwdg->Instance->SR  = 0;
00218
00219   /* Change WWDG peripheral state */
00220   hwwdg->State = HAL_WWDG_STATE_RESET;
00221
00222   /* Release Lock */
00223   __HAL_UNLOCK(hwwdg);
00224
00225   /* Return function status */
00226   return HAL_OK;
00227 }
00228
00229 /**
00230   * @brief  Initializes the WWDG MSP.
00231   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00232   *              the configuration information for the specified WWDG module.
00233   * @retval None
00234   */
00235 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00236 {
00237   /* Prevent unused argument(s) compilation warning */
00238   UNUSED(hwwdg);
00239
00240   /* NOTE: This function Should not be modified, when the callback is needed,
00241            the HAL_WWDG_MspInit could be implemented in the user file
00242    */
00243 }
00244
00245 /**
00246   * @brief  DeInitializes the WWDG MSP.
00247   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00248   *              the configuration information for the specified WWDG module.
00249   * @retval None
00250   */
00251 __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
00252 {
00253   /* Prevent unused argument(s) compilation warning */
00254   UNUSED(hwwdg);
00255
00256   /* NOTE: This function Should not be modified, when the callback is needed,
00257            the HAL_WWDG_MspDeInit could be implemented in the user file
00258    */
00259 }
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00266  *  @brief    IO operation functions
00267  *
00268 @verbatim
00269   ==============================================================================
00270                        ##### IO operation functions #####
00271   ==============================================================================
00272   [..]
00273     This section provides functions allowing to:
00274     (+) Start the WWDG.
00275     (+) Refresh the WWDG.
00276     (+) Handle WWDG interrupt request.
00277
00278 @endverbatim
00279   * @{
00280   */
00281
00282 /**
00283   * @brief  Starts the WWDG.
00284   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00285   *              the configuration information for the specified WWDG module.
00286   * @retval HAL status
00287   */
00288 HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
00289 {
00290   /* Process Locked */
00291   __HAL_LOCK(hwwdg);
00292
00293   /* Change WWDG peripheral state */
00294   hwwdg->State = HAL_WWDG_STATE_BUSY;
00295
00296   /* Enable the peripheral */
00297   __HAL_WWDG_ENABLE(hwwdg);
00298
00299   /* Change WWDG peripheral state */
00300   hwwdg->State = HAL_WWDG_STATE_READY;
00301
00302   /* Process Unlocked */
00303   __HAL_UNLOCK(hwwdg);
00304
00305   /* Return function status */
00306   return HAL_OK;
00307 }
00308
00309 /**
00310   * @brief  Starts the WWDG with interrupt enabled.
00311   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00312   *              the configuration information for the specified WWDG module.
00313   * @retval HAL status
00314   */
00315 HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
00316 {
00317   /* Process Locked */
00318   __HAL_LOCK(hwwdg);
00319
00320   /* Change WWDG peripheral state */
00321   hwwdg->State = HAL_WWDG_STATE_BUSY;
00322
00323   /* Enable the Early Wakeup Interrupt */
00324   __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
00325
00326   /* Enable the peripheral */
00327   __HAL_WWDG_ENABLE(hwwdg);
00328
00329   /* Return function status */
00330   return HAL_OK;
00331 }
00332
00333 /**
00334   * @brief  Refreshes the WWDG.
00335   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00336   *              the configuration information for the specified WWDG module.
00337   * @param  Counter: value of counter to put in WWDG counter
00338   * @retval HAL status
00339   */
00340 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
00341 {
00342   /* Process Locked */
00343   __HAL_LOCK(hwwdg);
00344
00345   /* Change WWDG peripheral state */
00346   hwwdg->State = HAL_WWDG_STATE_BUSY;
00347
00348   /* Check the parameters */
00349   assert_param(IS_WWDG_COUNTER(Counter));
00350
00351   /* Write to WWDG CR the WWDG Counter value to refresh with */
00352   MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
00353
00354   /* Change WWDG peripheral state */
00355   hwwdg->State = HAL_WWDG_STATE_READY;
00356
00357   /* Process Unlocked */
00358   __HAL_UNLOCK(hwwdg);
00359
00360   /* Return function status */
00361   return HAL_OK;
00362 }
00363
00364 /**
00365   * @brief  Handles WWDG interrupt request.
00366   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00367   *         or data logging must be performed before the actual reset is generated.
00368   *         The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
00369   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00370   *         generated and the corresponding Interrupt Service Routine (ISR) can
00371   *         be used to trigger specific actions (such as communications or data
00372   *         logging), before resetting the device.
00373   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00374   *              the configuration information for the specified WWDG module.
00375   * @retval None
00376   */
00377 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00378 {
00379   /* Check if Early Wakeup Interrupt is enable */
00380   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00381   {
00382     /* Check if WWDG Early Wakeup Interrupt occurred */
00383     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00384     {
00385       /* Early Wakeup callback */
00386       HAL_WWDG_WakeupCallback(hwwdg);
00387
00388       /* Change WWDG peripheral state */
00389       hwwdg->State = HAL_WWDG_STATE_READY;
00390
00391       /* Clear the WWDG Early Wakeup flag */
00392       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00393
00394       /* Process Unlocked */
00395       __HAL_UNLOCK(hwwdg);
00396     }
00397   }
00398 }
00399
00400 /**
00401   * @brief  Early Wakeup WWDG callback.
00402   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00403   *              the configuration information for the specified WWDG module.
00404   * @retval None
00405   */
00406 __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
00407 {
00408   /* Prevent unused argument(s) compilation warning */
00409   UNUSED(hwwdg);
00410
00411   /* NOTE: This function Should not be modified, when the callback is needed,
00412            the HAL_WWDG_WakeupCallback could be implemented in the user file
00413    */
00414 }
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
00421  *  @brief    Peripheral State functions.
00422  *
00423 @verbatim
00424   ==============================================================================
00425                         ##### Peripheral State functions #####
00426   ==============================================================================
00427   [..]
00428     This subsection permits to get in run-time the status of the peripheral
00429     and the data flow.
00430
00431 @endverbatim
00432   * @{
00433   */
00434
00435 /**
00436   * @brief  Returns the WWDG state.
00437   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00438   *              the configuration information for the specified WWDG module.
00439   * @retval HAL state
00440   */
00441 HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
00442 {
00443   return hwwdg->State;
00444 }
00445
00446 /**
00447   * @}
00448   */
00449
00450 /**
00451   * @}
00452   */
00453
00454 #endif /* HAL_WWDG_MODULE_ENABLED */
00455 /**
00456   * @}
00457   */
00458
00459 /**
00460   * @}
00461   */
00462
00463 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Nov 13 2015 11:37:27 for STM32F745xx HAL User Manual by doxygen 1.7.6.1


STM32F745xx HAL User Manual: stm32f7xx_hal_wwdg.h Source File

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stm32f7xx_hal_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f7xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.0.3
00006   * @date    13-November-2015
00007   * @brief   Header file of WWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F7xx_HAL_WWDG_H
00040 #define __STM32F7xx_HAL_WWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f7xx_hal_def.h"
00048
00049 /** @addtogroup STM32F7xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup WWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  WWDG HAL State Structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_WWDG_STATE_RESET     = 0x00,  /*!< WWDG not yet initialized or disabled */
00068   HAL_WWDG_STATE_READY     = 0x01,  /*!< WWDG initialized and ready for use   */
00069   HAL_WWDG_STATE_BUSY      = 0x02,  /*!< WWDG internal process is ongoing     */
00070   HAL_WWDG_STATE_TIMEOUT   = 0x03,  /*!< WWDG timeout state                   */
00071   HAL_WWDG_STATE_ERROR     = 0x04   /*!< WWDG error state                     */
00072 }HAL_WWDG_StateTypeDef;
00073
00074 /**
00075   * @brief  WWDG Init structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
00080                             This parameter can be a value of @ref WWDG_Prescaler */
00081
00082   uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
00083                             This parameter must be a number lower than Max_Data = 0x80 */
00084
00085   uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
00086                             This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00087
00088 }WWDG_InitTypeDef;
00089
00090 /**
00091   * @brief  WWDG handle Structure definition
00092   */
00093 typedef struct
00094 {
00095   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
00096
00097   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
00098
00099   HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
00100
00101   __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
00102
00103 }WWDG_HandleTypeDef;
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported constants --------------------------------------------------------*/
00109 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00110   * @{
00111   */
00112
00113 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00114   * @{
00115   */
00116 #define WWDG_IT_EWI                       WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00122   * @brief WWDG Flag definition
00123   * @{
00124   */
00125 #define WWDG_FLAG_EWIF                    WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup WWDG_Prescaler WWDG Prescaler
00131   * @{
00132   */
00133 #define WWDG_PRESCALER_1                 ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
00134 #define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
00135 #define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
00136 #define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported macro ------------------------------------------------------------*/
00146 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00147   * @{
00148   */
00149
00150 /** @brief Reset WWDG handle state
00151   * @param  __HANDLE__: WWDG handle
00152   * @retval None
00153   */
00154 #define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
00155
00156 /**
00157   * @brief  Enables the WWDG peripheral.
00158   * @param  __HANDLE__: WWDG handle
00159   * @retval None
00160   */
00161 #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00162
00163 /**
00164   * @brief  Disables the WWDG peripheral.
00165   * @param  __HANDLE__: WWDG handle
00166   * @note   WARNING: This is a dummy macro for HAL code alignment.
00167   *         Once enable, WWDG Peripheral cannot be disabled except by a system reset.
00168   * @retval None
00169   */
00170 #define __HAL_WWDG_DISABLE(__HANDLE__)                      /* dummy  macro */
00171
00172 /**
00173   * @brief  Gets the selected WWDG's it status.
00174   * @param  __HANDLE__: WWDG handle
00175   * @param  __INTERRUPT__: specifies the it to check.
00176   *        This parameter can be one of the following values:
00177   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00178   * @retval The new state of WWDG_FLAG (SET or RESET).
00179   */
00180 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)       __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00181
00182 /** @brief  Clear the WWDG's interrupt pending bits
00183   *         bits to clear the selected interrupt pending bits.
00184   * @param  __HANDLE__: WWDG handle
00185   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00186   *         This parameter can be one of the following values:
00187   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00188   */
00189 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00190
00191 /**
00192   * @brief  Enables the WWDG early wakeup interrupt.
00193   * @param  __HANDLE__: WWDG handle
00194   * @param  __INTERRUPT__: specifies the interrupt to enable.
00195   *         This parameter can be one of the following values:
00196   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00197   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00198   * @retval None
00199   */
00200 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00201
00202 /**
00203   * @brief  Disables the WWDG early wakeup interrupt.
00204   * @param  __HANDLE__: WWDG handle
00205   * @param  __INTERRUPT__: specifies the interrupt to disable.
00206   *         This parameter can be one of the following values:
00207   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00208   * @note   WARNING: This is a dummy macro for HAL code alignment.
00209   *         Once enabled this interrupt cannot be disabled except by a system reset.
00210   * @retval None
00211   */
00212 #define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__)                   /* dummy  macro */
00213
00214 /**
00215   * @brief  Gets the selected WWDG's flag status.
00216   * @param  __HANDLE__: WWDG handle
00217   * @param  __FLAG__: specifies the flag to check.
00218   *         This parameter can be one of the following values:
00219   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00220   * @retval The new state of WWDG_FLAG (SET or RESET).
00221   */
00222 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00223
00224 /**
00225   * @brief  Clears the WWDG's pending flags.
00226   * @param  __HANDLE__: WWDG handle
00227   * @param  __FLAG__: specifies the flag to clear.
00228   *         This parameter can be one of the following values:
00229   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00230   * @retval None
00231   */
00232 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
00233
00234 /** @brief  Checks if the specified WWDG interrupt source is enabled or disabled.
00235   * @param  __HANDLE__: WWDG Handle.
00236   * @param  __INTERRUPT__: specifies the WWDG interrupt source to check.
00237   *          This parameter can be one of the following values:
00238   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00239   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00240   */
00241 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
00242
00243 /**
00244   * @}
00245   */
00246
00247 /* Exported functions --------------------------------------------------------*/
00248 /** @addtogroup WWDG_Exported_Functions
00249   * @{
00250   */
00251
00252 /** @addtogroup WWDG_Exported_Functions_Group1
00253   * @{
00254   */
00255 /* Initialization/de-initialization functions  **********************************/
00256 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00257 HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
00258 void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00259 void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
00260 void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
00261 /**
00262   * @}
00263   */
00264
00265 /** @addtogroup WWDG_Exported_Functions_Group2
00266   * @{
00267   */
00268 /* I/O operation functions ******************************************************/
00269 HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
00270 HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
00271 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
00272 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00273 /**
00274   * @}
00275   */
00276
00277 /** @addtogroup WWDG_Exported_Functions_Group3
00278   * @{
00279   */
00280 /* Peripheral State functions  **************************************************/
00281 HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290 /* Private types -------------------------------------------------------------*/
00291 /* Private variables ---------------------------------------------------------*/
00292 /* Private constants ---------------------------------------------------------*/
00293 /** @defgroup WWDG_Private_Constants WWDG Private Constants
00294   * @{
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301 /* Private macros ------------------------------------------------------------*/
00302 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00303   * @{
00304   */
00305 #define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
00306                                           ((__PRESCALER__) == WWDG_PRESCALER_2) || \
00307                                           ((__PRESCALER__) == WWDG_PRESCALER_4) || \
00308                                           ((__PRESCALER__) == WWDG_PRESCALER_8))
00309 #define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
00310 #define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
00311 /**
00312   * @}
00313   */
00314
00315 /* Private functions ---------------------------------------------------------*/
00316 /** @defgroup WWDG_Private_Functions WWDG Private Functions
00317   * @{
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331 #ifdef __cplusplus
00332 }
00333 #endif
00334
00335 #endif /* __STM32F7xx_HAL_WWDG_H */
00336
00337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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